Interlayer coupler with mode confinement rod arrays for multi-layer photonic integrated circuits

Abstract

A photonic integrated circuit includes a first optical waveguide in a lower layer, a second optical waveguide in an upper layer, and an interlayer coupler between these waveguides. The coupler has confinement rods, formed and encapsulated within cladding layers, that shape the optical modes as they transition from one waveguide to the other. In one embodiment, the lower waveguide tapers from a nominal width to a narrow section near the coupler, while the upper waveguide expands from a narrow section near the coupler to its nominal width. The method of formation involves CMOS-compatible processes, including depositing waveguide layers, patterning the confinement rods, and encapsulating them within cladding. The disclosure offers a compact, low-loss solution for guiding signals between different vertical levels in an integrated photonic device operating near the 1550 nm wavelength range.

Description

[0001] INTERLAYER COUPLER WITH MODE CONFINEMENT ROD ARRAYS FOR MULTILAYER PHOTONIC INTEGRATED CIRCUITS

[0002] RELATED APPLICATIONS

[0003]

[0001] This application claims the benefit under 35 USC 119(e) of U.S. Provisional Application No. 63 / 558,417, filed on February 27, 2024, which is incorporated herein by reference in its entirety.

[0004] BACKGROUND OF THE INVENTION

[0005]

[0002] Photonic integrated circuits are increasingly being developed for applications that demand compact and efficient optical functionality on a single chip. These integrated devices combine multiple optical components, such as switches, wavelength splitters, mode-size converters, multiplexers and demultiplexers, resonators, polarizers, phase shifters, modulators and waveguides side-by-side with electrical signal routing and electronic components, and can perform complex tasks while occupying a small footprint. By leveraging semiconductor fabrication methods, photonic integrated circuits can also benefit from the maturity of microelectronics manufacturing. This has led to a wider adoption of photonic chips in telecommunications, data communications, and sensing applications.

[0006]

[0003] Silicon photonics, in particular, has emerged as a leading technology for large-scale photonic integrated circuits. Because silicon photonics leverages complementary metal-oxide- semiconductor (CMOS) processes, it can offer economies of scale, reduced manufacturing costs, and compatibility with existing electronic device fabrication infrastructure. This is especially relevant in data centers, where photonic links and silicon-based optical components can potentially replace or enhance conventional copper interconnects, and in many emerging applications that call for higher bandwidth and lower latency.

[0007]

[0004] Waveguide structures form the backbone of photonic integrated circuits by guiding light from one component to another on the chip. The waveguides define the optical paths and cross-sectionally consist of a high-refractive-index material core surrounded by lower- refractive-index cladding layers. The choice of materials, geometry, and fabrication techniques affects the performance of the waveguides and impacts optical losses, bandwidth, and power consumption.

[0005] In silicon photonics, waveguides are typically formed from crystalline or amorphous silicon or silicon nitride. Both materials are compatible with conventional CMOS fabrication processes. Silicon waveguides commonly rely on single-crystal or polycrystalline silicon for the core, with silica or silicon dioxide (SiO2) or silicon oxynitride for the cladding. Silicon nitride waveguides, on the other hand, may use silicon nitride for the core, again with silica or other oxide material as the cladding. The waveguide cross-section is usually patterned using lithography steps, and subsequent etching methods define the waveguide shape in the core layer.

[0008]

[0006] Another important consideration is the thickness of the waveguide layers, which often depends on the desired optical mode confinement and the target operating wavelength. Waveguides in silicon photonics commonly target near-infrared wavelengths, such as 1310 nm or 1550 nm, aligning with standard telecommunication windows. Precise control over the waveguide thickness, etch depth, and material composition is maintained through CMOS process steps, such as dry etching, chemical vapor deposition, and thermal oxidation.

[0009]

[0007] Photonic integrated circuits often incorporate multiple layers or strata to increase functionality and density. In some cases, the design may call for routing different signals at different layers in order to reduce optical cross-talk or integrate specific optical components and / or materials in separate layers. However, a challenge arises when optical signals must transition from a waveguide located in one layer to a waveguide in another layer. The different waveguide layers may be vertically separated by intervening materials, leading to potential alignment issues and increased coupling losses if not properly addressed.

[0010]

[0008] In conventional designs, simple vertical transitions between waveguides may exhibit significant insertion loss because of mismatches in waveguide geometry or effective index since the optical mode must be guided out of plane. These losses can severely affect the overall efficiency of the integrated photonic circuit, especially in complex multi-layer designs. Moreover, the reliability of the chip may be compromised if the process requires many delicate transitions or if any misalignment introduces further loss. SUMMARY OF THE INVENTION

[0011]

[0009] It is therefore desirable to develop interlayer coupler structures that enable low-loss and broadband transfer of light between waveguides in different layers within a photonic integrated circuit. Such solutions should ideally maintain compatibility with CMOS processes to preserve the cost and throughput advantages of silicon-based photonics. By employing a more carefully designed coupler, optical signals can be routed between distinct vertical layers without incurring high losses or introducing significant fabrication complexities.

[0012]

[0010] In one aspect, the present invention provides a photonic integrated circuit that includes a first optical waveguide formed in a first vertical level of the circuit and a second optical waveguide formed in a second vertical level of the circuit above the first optical waveguide. Between these two waveguides, an interlayer coupler is positioned to guide optical modes between the different vertical levels. The interlayer coupler includes a set of confinement rods adjacent to each waveguide, and these rods are fabricated and encapsulated within cladding layers to shape the optical modes (e.g., of the first and second optical waveguides) as they transition from one waveguide to the other between the different vertical levels.

[0013]

[0011] In certain embodiments, an inner set of rods and an outer set of rods are arranged on opposing sides of each waveguide. The rods can extend in a direction substantially parallel to the waveguides.

[0014]

[0012] The rod dimensions may be selected to reduce optical loss when transferring signals between the waveguides, for example at about 1550 nanometers (nm), or in a range of about 1400 nm to 1700 nm.

[0015]

[0013] One waveguide may taper from a nominal width section that is sized based on the waveguide width used for transmission between components of the circuit to a narrower section near a central portion of the interlayer coupler, while the other waveguide can expand from a narrow section near the central portion to a nominal width section.

[0016]

[0014] The interlayer coupler is formed through processes compatible with semiconductor manufacturing, such as depositing and patterning silicon or silicon nitride waveguide layers for the first and second waveguides and surrounding them with cladding materials. In one example, silicon oxide or similar materials are used for the cladding layers.

[0017]

[0015] In another aspect, the invention provides a method for forming an interlayer coupler in a photonic integrated circuit. A first waveguide is formed in a first layer. Multiple cladding layers are then deposited above the first layer, and a mode confinement rod array is patterned in a region above the first waveguide. Additional cladding layers are deposited, and a second waveguide is formed in a second layer above the first waveguide, with the rods structured to guide light between the two waveguides at reduced optical loss.

[0018]

[0016] In certain embodiments, this method further includes patterning an upper mode confinement rod array above the lower mode confinement rod array before forming the second waveguide. The first waveguide may be formed with a taper that narrows toward the interlayer coupler, and the second waveguide may expand from a narrower width near the interlayer coupler to a nominal width, facilitating the transfer of optical signals.

[0019]

[0017] The confinement rods can be formed with particular thicknesses and widths, such as in the range of 50 to 150 nanometers in thickness and 150 to 600 nanometers in width, depending on the desired coupling efficiency and operating wavelength. In some embodiments, the confinement rods can be formed with particular thicknesses and widths based on waveguide dimensions (e.g., of the first and / or second waveguide). For example, the confinement rods may be formed with a particular width in the range of 15% to 60% of waveguide width.

[0020]

[0018] This method is carried out using conventional CMOS -compatible fabrication steps, such as depositing dielectric claddings, patterning rod arrays, and forming waveguide cores. The interlayer coupler is disposed in a multi-layer stack formed by successive CMOS- compatible deposition and patterning steps, in one example.

[0021]

[0019] The above and other features of the invention including various novel details of construction and combinations of parts, and other advantages, will now be more particularly described with reference to the accompanying drawings and pointed out in the claims. It will be understood that the particular method and device embodying the invention are shown by way of illustration and not as a limitation of the invention. The principles and features of this invention may be employed in various and numerous embodiments without departing from the scope of the invention.

[0022] BRIEF DESCRIPTION OF THE DRAWINGS

[0023]

[0020] In the accompanying drawings, reference characters refer to the same parts throughout the different views. The drawings are not necessarily to scale; emphasis has instead been placed upon illustrating the principles of the invention. Of the drawings:

[0024]

[0021] Fig. 1 includes various views of an interlayer coupler (ILC) according to the present invention, including a side schematic view, a schematic top view, and three cross- sectional views;

[0025]

[0022] Figs. 2A and 2B are plots of transmission for, respectively, a conventional interlayer coupler and an interlay coupler according to the present invention; and

[0026]

[0023] Figs. 3 A and 3B are a schematic top view and a side schematic view of interlayer couplers of a PIC chip according to embodiments of the present invention.

[0027] DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0028]

[0024] The invention now will be described more fully hereinafter with reference to the accompanying drawings, in which illustrative embodiments of the invention are shown. This invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art.

[0029]

[0025] As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items. Also, all conjunctions used are to be understood in the most inclusive sense possible. Thus, the word "or" should be understood as having the definition of a logical "or" rather than that of a logical "exclusive or" unless the context clearly necessitates otherwise. Further, the singular forms and the articles "a", "an" and "the" are intended to include the plural forms as well, unless expressly stated otherwise. It will be further understood that the terms: includes, comprises, including and / or comprising, when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof. Further, it will be understood that when an element, including component or subsystem, is referred to and / or shown as being connected or coupled to another element, it can be directly connected or coupled to the other element or intervening elements may be present.

[0030]

[0026] It will be understood that although terms such as “first” and “second” are used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element. Thus, an element discussed below could be termed a second element, and similarly, a second element may be termed a first element without departing from the teachings of the present invention.

[0031]

[0027] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

[0032]

[0028] Fig. 1 depicts various views of an interlayer coupler (ILC)100 of a PIC chip 100, according to the present invention. Fig. 1 includes portions (A), (B), and (C). Portion (A) provides a side schematic view of the ILC 100 according to the present invention. Portion (B) provides a schematic top view of the ILC 100. Portion (C) provides three cross-sectional views at a right side, a center and a left side of the ILC 100. Three dotted lines a, b, c show the relationship between the side view of portion (A) and the top view of portion (B) and the three corresponding cross sections of portion (C).

[0033]

[0029] Referring to portion (A) of Fig. 1, the interlayer coupler 100 is formed on a silicon or silicon on insulator base wafer 50, with a first waveguide and a second waveguide, namely with both a lower waveguide 110 and an upper waveguide 120 positioned in different layers or strata of the photonic integrated circuit chip 10. For example, the lower waveguide 110 is formed in a first or lower vertical level of the PIC chip 100, and the upper waveguide 120 is formed in a second or upper vertical level of the PIC chip 100. The lower waveguide 110 extends from left of the figure and continues to the right, terminating near the right edge. The upper waveguide 120 begins in the left region of the figure and extends out toward the left, essentially overlying the lower waveguide 110 but at a higher vertical level within the device stack. Both waveguides 110, 120 are encapsulated by one or more cladding layers 52. The waveguide cores and claddings are formed according to CMOS -compatible processes, and the thickness and composition of these layers are chosen to guide optical signals with minimal loss.

[0034]

[0030] The interlayer coupler 100 enables optical signals to pass between components located in lower layers of the chip for which lower waveguide 110 provides routing and those located in higher layers for which upper waveguide 120 provides routing. These signals can originate in the lower waveguide 110 and then transition upward into the upper waveguide 120, and / or they can propagate in the reverse direction.

[0035]

[0031] According to an aspect of the invention, the coupler 100 includes one or more mode confinement rod arrays fabricated in the layers between the lower and upper waveguides. In the example shown, a lower mode confinement rod horizontal array 132 and an upper mode confinement rod horizontal array 134 are placed between the respective vertical levels of the two waveguides. These arrays 132, 134 extend in a direction parallel to the paths of the waveguides 110, 120 and occupy the region where the transition of the optical mode occurs. The rods are likewise encapsulated in cladding layers, so they perform a mode guiding function. By controlling the geometry and refractive index of these rods and cladding, the arrays guide the optical mode in a manner that reduces scattering loss and enhances the coupling efficiency between the two waveguides 110, 120. In this way the confinement rod arrays 132, 134 are structured to guide light between the lower waveguide 110 and the upper waveguide 120 with reduced optical loss.

[0036]

[0032] In practice, the interlayer coupler 100 can be used in many photonic circuits that feature vertically stacked or multi-strata waveguides. Such circuits may include components such as edge couplers, multiplexers and demultiplexers, polarizers, phase shifters, modulators, filters, resonators, or arrayed waveguides formed in lower layers and other similar optical components fabricated in higher layers. The coupler’s function is to transfer light between these different layers without requiring lengthy detours or separate external coupling structures. In this way, the ILC 100 allows designers to use multiple vertical levels of waveguides while still maintaining low-loss connectivity between them.

[0037]

[0033] Referring to portion (B) of Fig. 1, a top view of the interlayer coupler 100 is shown, including both the lower waveguide 110 and the upper waveguide 120, along with two sets of confinement rods on either side. On one side, an inner set of rods LI and an outer set of rods LO are arranged adjacent to the lower and upper waveguides, while on the opposite side, an inner set of rods RI and an outer set of rods RO are similarly arranged. These rods help guide and varying the confinement of the propagating optical modes as they transition between layers. The lower waveguide 110 can be seen entering from the left portion of the figure wherein it connects with other optical components in the lower layers. It begins with a nominal waveguide width section 112 that has a width similar to widths used for routing in the lower layers, then gradually tapers its horizontal width at a tapering section 114 that extends from left to right until near the midpoint of the coupler. At that midpoint, the lower waveguide continues into a narrower section 116 that remains substantially uniform in its width for the remainder of its length to the right of the figure.

[0038]

[0034] By contrast, the upper waveguide 120 is shown initially in a narrow section 126 on the right side of the figure. Its horizontal width remains constant until it reaches the center region of the interlayer coupler 100. Beyond that central point, in an expanding section 124, the width of the upper waveguide increases moving further rightward until it reaches its nominal waveguide width section 122 that has a width similar to widths used for routing in the upper layers. Thus, as the top view reveals, the upper waveguide transitions from a narrower geometry to a nominal width section, while the lower waveguide transitions from a nominal width down to a narrower section. The confinement rods, located to the left and right of these waveguide paths including the inner arrays RI, LI and outer arrays RO, LO, work in concert to guide the optical field or mode(s) between the waveguides, thereby promoting efficient light coupling between the differing vertical layers of the photonic integrated circuit.

[0039]

[0035] Referring to portion (C) of Fig. 1 , the separate eight mode confinement rods 132LO, 132LI, 132RI, 132RO, 134LI, 134RI, 134LO, 134RO of the lower mode confinement rod horizontal array 132 and the upper mode confinement rod horizontal array 134 are shown in each of the three cross-sections along line a, b, c.

[0036] In designs suitable for operation at a wavelength of about 1550 nm, each confinement rod in the lower and upper mode confinement rod arrays can typically measure on the order of tens to hundreds of nanometers in thickness and width, for example ranging from approximately 50 nm to 150 nm in thickness or height, and from roughly 150 nm to 600 nm in lateral width, depending on the chosen material and the intended degree of mode confinement. The rods can be patterned to span lengths from about 1 pm to several micrometers (e.g., in the order of tens to hundreds of micrometers), with their overall dimensions tuned to guide and shape the mode as it transitions between the lower and upper waveguides. In some embodiments, rod dimensions may deviate from these approximate ranges to accommodate specific fabrication tolerances or to optimize coupling efficiency for particular layer spacings, cladding refractive indices, or targeted photonic device geometries. In some embodiments, each confinement rod in the lower and upper mode confinement rod arrays can have particular thicknesses and particular widths based on waveguide dimensions (e.g., of the upper and / or lower waveguide). For example, the confinement rods may be formed with a particular width in the range of 15% to 60% of waveguide width of the upper waveguide and / or the lower waveguide.

[0040]

[0037] In some embodiments, the interlayer coupler 100 is disposed in a multi-layer stack formed by successive CMOS -compatible deposition and patterning steps.

[0041]

[0038] In one example, a method for forming the interlayer coupler 100 may comprise forming a first waveguide such as the lower waveguide 110 in a first layer, depositing a plurality of cladding layers such as the cladding layers 52 above the first layer, patterning one or more confinement rod arrays (e.g., the lower mode confinement rod horizontal array 132 and / or the upper mode confinement rod horizontal array 134) in a region above the lower waveguide 110, depositing further cladding layers such as the cladding layers 52, and forming a second waveguide such as the upper waveguide 120 in a second layer above the lower waveguide 110.

[0042]

[0039] Fig. 2A is a plot of transmission for a conventional interlayer coupler.

[0043]

[0040] More particularly, Fig. 2A presents a graph of transmission efficiency (dB) as a function of ILC slow length (pm) for a conventional interlayer coupler (ILC) transitioning from a 300 nm-thick silicon nitride (SiN300) waveguide to a multi-mode nanophotonic waveguide (mNWG).

[0044]

[0041] In the illustrated graph, the y-axis is labeled "Transmission (dB)" and ranges from - 4 dB to 0 dB in increments of 0.5 dB. Here, transmission closer to 0 dB indicates lower optical loss, while more negative values indicate greater loss.

[0045]

[0042] The x-axis is labeled "ILC slow length (pm)" and spans from 0 to 700 pm, increasing in increments of 100 pm. This represents the physical length of the interlayer coupler’s transition section.

[0046]

[0043] Two transmission curves are plotted, representing TE (Transverse Electric) mode and TM (Transverse Magnetic) mode.

[0047]

[0044] The TM mode plot begins at around -3 dB at approximately 50 pm, indicating a significant initial loss. However, as the ILC length increases, the TM transmission improves rapidly, reaching approximately 0 dB at 250 pm. From this point onward, the TM mode remains stable near 0 dB, suggesting efficient coupling for TM polarization.

[0048]

[0045] The TE mode plot shows worse performance initially, starting at around -4.5 dB at 275 pm, which is a higher loss compared to the TM mode. The TE transmission gradually improves as the length increases but only reaches approximately -1.5 dB by 700 pm, indicating that the conventional design is less efficient for TE -polarized light and experiences significant coupling losses over a longer distance.

[0049]

[0046] The TM mode achieves nearly lossless transmission after 250 pm, indicating that conventional ILC designs work relatively well for TM-polarized light.

[0050]

[0047] However, the TE mode suffers from higher insertion loss and slower improvement over length, suggesting that conventional interlayer couplers struggle with TE -polarized light.

[0051]

[0048] The relatively long slow length (up to 700 pm) suggests that conventional ILCs require longer structures to achieve acceptable transmission, which limits integration density in compact photonic circuits.

[0052]

[0049] Fig. 2B is a plot of transmission for an interlay coupler according to the present invention (e.g., the interlayer coupler 100 illustrated in Fig. 1).

[0050] More particularly, Fig. 2B presents a graph of transmission efficiency (dB) as a function of ILC slow section length (pm) for an interlayer coupler that incorporates confinement rods according to the present invention (also called nanorods).

[0053]

[0051] The y-axis is labeled "Transmission (dB)" and ranges from -0.4 dB to 0 dB in increments of 0.05 dB.

[0054]

[0052] The x-axis is labeled "Slow section 1 (pm)" and spans from 0 to 400 pm, increasing in 50 pm increments.

[0055]

[0053] A vertical line appears at 235 pm, labeled "total length: 470 pm", indicating the total length of the nanorod-enhanced ILC structure.

[0056]

[0054] Two transmission curves are plotted, representing TE mode and TM mode.

[0057]

[0055] The TM mode plot starts at -0.4 dB at 0 pm and rapidly improves, reaching approximately -0.075 dB at 150 pm. After this peak, the TM transmission gradually tapers down slightly to around -0.175 dB at 400 pm, still demonstrating very low loss.

[0058]

[0056] The TE mode plot starts at -0.4 dB at 125 pm, similar to TM mode but delayed in its improvement. It then rapidly increases to approximately -0.025 dB by 225 pm, indicating exceptionally low loss. After reaching this peak, the TE mode tapers slightly downward to about -0.225 dB at 400 pm, but remains significantly better than in Fig. 2A.

[0059]

[0057] The transmission losses for both TE and TM modes are significantly lower than in Fig. 2A, demonstrating the effectiveness of the nanorod-based ILC.

[0060]

[0058] Both polarization modes reach peak efficiency much sooner (around 200 pm) compared to the conventional ILC, which required over 700 pm for TE mode to achieve a -1.5 dB level.

[0061]

[0059] The nanorod-based ILC achieves lower insertion loss in a much shorter length, making it far more efficient and compact.

[0062]

[0060] The comparison between Fig. 2A (conventional ILC) and Fig. 2B (nanorod-based ILC) highlights the major improvements achieved by the present invention.

[0061] In Fig. 2A, the TE mode suffers from high losses (-4.5 dB initially, improving only to -1.5 dB by 700 pm), while in Fig. 2B, the TE mode improves rapidly, reaching near -0.025 dB at 225 pm. The TM mode in Fig. 2B also shows much lower losses, peaking at -0.075 dB compared to -3 dB in Fig. 2A. Thus, the transmission low is significantly lower in the IEC according to the present invention.

[0063]

[0062] The conventional IEC in Fig. 2 A takes 700 pm to approach reasonable TE mode transmission, whereas the nanorod IEC in Fig. 2B achieves better performance in less than 400 pm. This reduction in required length means that photonic circuits can be made more compact and densely integrated, a crucial advantage for scaling photonic devices. Thus, a shorter required coupling length is enabled by the present invention.

[0064]

[0063] In Fig. 2A, TM mode performs well, but TE mode lags behind significantly. In Fig. 2B, both TE and TM modes exhibit nearly equal transmission efficiency, demonstrating that the nanorod-based IEC ensures better polarization performance. Thus the presently disclosed ILC provides more balanced TE and TM performance.

[0065]

[0064] The nanorod-enhanced ILC (e.g., ILC 100) effectively guides light more efficiently between layers while minimizing scattering loss. This makes it easier to integrate multi-layer photonic circuits with lower power loss, making it ideal for applications such as telecommunications, optical interconnects, and sensing, to list a few examples.

[0066]

[0065] Fig. 3 A shows a schematic top view of another embodiment of the ILC 100. The confinement rods inner arrays LI, RI and the outer arrays LO, RO have varying widths across the length of the ILC 100. The rods are wider near the center and then narrow moving away from the center.

[0067]

[0066] In addition, the different tapers are used for the lower waveguide 110 and the upper waveguide 120. Rather than the linear taper of Fig. 1, here the lower waveguide 110 and the upper waveguide 120 exhibit faster narrowing as then transition into the ILC 100.

[0068]

[0067] Fig. 3B shows another embodiment in which four layers of confinement rod arrays 132, 132’, 134’, 134 are employed.

[0069]

[0068] While this invention has been particularly shown and described with references to preferred embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the scope of the invention encompassed by the appended claims.

Claims

CLAIMSWhat is claimed is:

1. A photonic integrated circuit, comprising: a first optical waveguide formed in a first vertical level of the circuit, a second optical waveguide formed in a second vertical level of the circuit above the first optical waveguide, and an interlayer coupler positioned between the first and second optical waveguides, the interlayer coupler including a set confinement rods adjacent to each waveguide that are fabricated and encapsulated within cladding layers to shape optical modes of the first and second optical waveguides as they transition between the different vertical levels.

2. The photonic integrated circuit of claim 1, wherein the set of confinement rods comprises at least one inner set of rods and at least one outer set of rods placed on opposing sides of the first and second optical waveguides.

3. The photonic integrated circuit of either of claims 1 or 2, wherein the confinement rods extend in a direction substantially parallel to the first and second optical waveguides.

4. The photonic integrated circuit of any of claims 1-3, wherein each confinement rod has a thickness in a range of about 50 nanometers to about 150 nanometers and a width in a range of about 150 nanometers to about 600 nanometers.

5. The photonic integrated circuit of any of claims 1-4, wherein the first optical waveguide tapers from a nominal waveguide width section to a narrower width section proximate the interlayer coupler.

6. The photonic integrated circuit of any of claims 1-5, wherein the second optical waveguide expands from a narrower width section proximate the interlayer coupler to a nominal waveguide width section.

7. The photonic integrated circuit of any of claims 1-6, wherein the interlayer coupler is configured to operate at an optical wavelength of approximately 1550 nanometers.

8. The photonic integrated circuit of any of claims 1-7, wherein the interlayer coupler is disposed in a multi-layer stack formed by successive CMOS -compatible deposition and patterning steps.

9. A method for forming an interlayer coupler in a photonic integrated circuit, the method comprising: forming a first waveguide in a first layer, depositing a plurality of cladding layers above the first layer, patterning a lower mode confinement rod array in a region above the first waveguide, depositing further cladding layers, and forming a second waveguide in a second layer above the first waveguide, wherein the confinement rod array are structured to guide light between the first waveguide and the second waveguide with reduced optical loss.

10. The method according to claim 9, further comprising patterning an upper mode confinement rod array above the lower mode confinement rod array before depositing the further cladding layers and forming the second waveguide.

11. The method according to either of claims 9 or 10, wherein the first waveguide is formed to have a taper that narrows toward a center region of the interlayer coupler, and the second waveguide is formed to have an expanding section that widens away from the center region of the interlayer coupler.

12. The method according to any of claims 9-11, wherein each confinement rod in the lower mode confinement rod array has a thickness in a range of about 50 nanometers to about 150 nanometers and a width in a range of about 150 nanometers to about 600 nanometers.

13. The method according to any of claims 9-12, wherein the lower mode confinement rod array extends in a direction substantially parallel to the first and second waveguides.

14. The method according to any of claims 9-13, wherein the method is performed with CMOS-compatible processes, including depositing and patterning silicon or silicon nitride layers for the first and second waveguides and using silicon oxide or similar materials for the cladding layers.

15. The method according to any of claims 9-14, wherein the photonic integrated circuit is configured to operate at an optical wavelength of about 1550 nanometers.

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