Semiconductor device

Abstract

A semiconductor device according to the present invention includes: a first transistor that is formed on a substrate and includes first and second semiconductor layers, a first nanosheet, and a first gate electrode; a second transistor that is formed on the first transistor and includes third and fourth semiconductor layers, a second nanosheet, and the first gate electrode; first and second power supply lines that are formed on the substrate and are respectively connected to the first and second semiconductor layers; and third and fourth power supply lines that are formed on the substrate and are respectively connected to one and the other of the third and fourth semiconductor layers. The present invention thereby makes it possible to appropriately position a power supply switch circuit that includes nanosheet transistors within a semiconductor device.

Description

Semiconductor Devices

[0001] The present invention relates to a semiconductor device.

[0002] Known technologies include CFET (Complementary Field Effect Transistor) technology, which forms transistors by stacking them, BPR (Buried Power Rail) technology, which supplies a power supply voltage or a ground voltage to a transistor by using buried wiring in which a conductor is formed in a trench formed in the surface of a semiconductor substrate, and technology, which provides a semiconductor device with a power switch circuit that switches the power supply to a circuit on and off.

[0003] US Patent Application Publication No. 2023 / 0178435 US Patent Application Publication No. 2023 / 0067311 US Patent Application Publication No. 2022 / 0123023 US Patent Application Publication No. 2022 / 0181258 International Publication No. 2020 / 065916 International Publication No. 2020 / 066797 International Publication No. 2020 / 217396 International Publication No. 2020 / 217400 US Patent Application Publication No. 2021 / 0366902 US Patent Application Publication No. 2022 / 0102479 US Patent Application Publication No. 2021 / 0210600

[0004] Depending on the type of power switch circuit, there are some cases where detailed consideration has not been given to how the power switch circuit should be arranged in the semiconductor device.

[0005] The present invention has been made in view of the above points, and aims to appropriately arrange a power switch circuit having a transistor with a nanosheet structure in a semiconductor device.

[0006] In one aspect of the present invention, a semiconductor device includes a substrate; a first power supply line, a second power supply line, a third power supply line, and a fourth power supply line formed on the substrate; a first semiconductor layer and a second semiconductor layer formed on the substrate and having a first conductivity type; a first nanosheet formed between the first semiconductor layer and the second semiconductor layer; a third semiconductor layer formed on the first semiconductor layer and having a second conductivity type different from the first conductivity type; a fourth semiconductor layer formed on the second semiconductor layer and having the second conductivity type; a second nanosheet formed between the third semiconductor layer and the fourth semiconductor layer; a first gate electrode covering the first nanosheet and the second nanosheet; a first transistor provided between the second power supply line and the fourth power supply line, the first transistor having the first semiconductor layer, the second semiconductor layer, the first nanosheet, and the first gate electrode; and a second transistor electrically provided between the third power supply line and the fourth power supply line, the second transistor having the third semiconductor layer, the fourth semiconductor layer, the second nanosheet, and the first gate electrode, wherein the first semiconductor layer is electrically connected to the first power supply line, the second semiconductor layer is electrically connected to the second power supply line, one of the third semiconductor layer and the fourth semiconductor layer is electrically connected to the third power supply line, and the other of the third semiconductor layer and the fourth semiconductor layer is electrically connected to the fourth power supply line.

[0007] According to the disclosed technology, a power switch circuit having a transistor with a nanosheet structure can be appropriately arranged in a semiconductor device.

[0008] 1. A plan view showing an example of a layout of a semiconductor device in a first embodiment. 2. A cross-sectional view showing an example of a cross-sectional structure of the semiconductor device of FIG. 1. 3. A circuit diagram showing an example of a circuit arranged in the standard cell block of FIG. 1. 4. An explanatory diagram showing a legend for circuit elements used in the plan views of the circuits described below. 5. A perspective view showing an example of a layout of the power switch circuit of FIG. 3. 6. A plan view showing an example of a bottom-side circuit layout formed on the surface of a substrate in a region where the power switch circuit and standard cells of FIG. 5 are formed. 7. A plan view showing an example of a top-side circuit layout formed on the bottom-side circuit of FIG. 6 in a region where the power switch circuit and standard cells of FIG. 5 are formed. 8. A cross-sectional view showing an example of a cross section taken along line X1-X1' in FIGS. 6 and 7. A cross-sectional view showing an example of a cross section taken along line X2-X2' in FIGS. 6 and 7. A cross-sectional view showing an example of a cross section taken along line Y1-Y1' in FIGS. 6 and 7. 9. A perspective view showing an example of a layout of a buffer circuit in a semiconductor device of a second embodiment. 10. A circuit diagram showing an example of a circuit image of a standard cell block including the buffer circuit of FIG. 11. 11. A circuit diagram showing another example of a circuit image of a standard cell block including the buffer circuit of FIG. 11. 12 is a circuit diagram showing yet another example of a circuit image of a standard cell block including the buffer circuit of Fig. 11. FIG. 13 is a plan view showing an example of a circuit layout on the bottom side in a region where the standard cell block of Fig. 12 is formed. FIG. 14 is a plan view showing an example of a circuit layout on the top side in a region where the standard cell block SCB of Fig. 12 is formed.

[0009] Hereinafter, embodiments will be described with reference to the drawings. In the following, a symbol indicating a signal is also used to indicate a signal line or a signal terminal. A symbol indicating a power supply voltage is also used to indicate a power supply line or a power supply terminal to which the power supply voltage is supplied.

[0010] 1 shows an example of the layout of a semiconductor device according to the first embodiment. For example, the semiconductor device 100 shown in FIG. 1 may be a SoC (System on Chip), a standalone FPGA (Field-Programmable Gate Array), or the like.

[0011] The semiconductor device 100 has a plurality of I / O cells IOC and IOCP and an internal circuit region INTR. The I / O cell IOC is an interface circuit for a signal SGNL such as an input signal, an output signal, or an input / output signal. The I / O cell IOCP is an interface circuit for a power supply voltage or a ground voltage.

[0012] Each I / O cell IOC, IOCP is connected to an internal circuit region INTR. For example, the internal circuit region INTR has one or more standard cell blocks SCB in which standard cells are provided. Note that the internal circuit region INTR may also be equipped with logic circuits other than standard cells, or may also be equipped with a memory. The memory may be equipped within the standard cell block SCB.

[0013] FIG. 2 shows an example of the cross-sectional structure of the semiconductor device 100 of FIG. 1. The semiconductor device 100 has a substrate SUB and a wiring layer WL1 formed on the substrate. A CFET is formed on the surface FS of the substrate SUB. The CFET has a source / drain S / D formed in a semiconductor layer on the bottom BTM, which is closer to the substrate SUB, a nanosheet NS on the bottom BTM side that interconnects the source S and drain D, a source / drain S / D formed in a semiconductor layer on the top TOP side, which is farther from the substrate SUB, and a nanosheet NS on the top TOP side that interconnects the source S and drain D. The CFET also has a gate insulating film (not shown) and a gate electrode GT formed on the nanosheet NS.

[0014] The nanosheet NS that interconnects the source S and drain D on the bottom BTM side is an example of a first nanosheet. The nanosheet NS that interconnects the source S and drain D on the top TOP side is an example of a second nanosheet. Hereinafter, the gate electrode GT will also be simply referred to as the gate GT. In addition, the wiring and semiconductor layer arranged on the bottom BTM side may be indicated by the symbol BTM, and the wiring and semiconductor layer arranged on the top TOP side may be indicated by the symbol TOP. The wiring arranged on the bottom BTM side may also be referred to as the bottom wiring BTMW, and the wiring arranged on the top TOP side may also be referred to as the top wiring TOPW.

[0015] Furthermore, a part of the CFET structure may be referred to as an NMOS transistor or a PMOS transistor depending on the conductivity type of its semiconductor layer. The semiconductor layer may be referred to as a source / drain S / D, even if it does not function as a transistor. Furthermore, a part of the CFET structure may be referred to as an NMOS transistor or a PMOS transistor depending on the conductivity type of its semiconductor layer, even if it does not function as a transistor.

[0016] For example, the source / drain S / D or gate GT of the CFET may be connected to a wiring W1 formed in a wiring layer FSM1 (FSM stands for Frontside Metal) or the like. The wiring layer WL1 may have a plurality of wiring layers FSM (such as an FSM1 layer and an FSM2 layer). Hereinafter, the wiring layers FSM1 and FSM2 are also referred to as an FSM1 layer and an FSM2 layer. A groove is formed in the surface of the substrate SUB, and a conductive buried wiring BPR is formed in the groove. Hereinafter, the surface of the substrate SUB on which the buried wiring BPR is formed is also referred to as a BPR layer.

[0017] 3 shows an example of a circuit arranged in the standard cell block SCB of FIG. 1. The standard cell block SCB has a power switch circuit PSW and standard cells SC1 and SC2 having different power domains. The standard cell SC1 is an example of a first standard cell region, and the standard cell SC2 is an example of a second standard cell region.

[0018] The power switch circuit PSW has a control circuit CNTL and a switch transistor SWT, and operates by receiving a power supply voltage TVDD supplied from a power line TVDD and a ground voltage TVSS supplied from a ground line TVSS. The control circuit CNTL has a buffer circuit BUF including inverters INV1 and INV2 connected in series. The buffer circuit BUF generates a control signal PSWsig for controlling the switch transistor SWT from the output of the inverter INV1.

[0019] The switch transistor SWT has a PMOS transistor PM whose gate is connected to the control signal line PSWsig, whose source is connected to the power supply line TVDD, and whose drain is connected to the virtual power supply line VVDD. The switch transistor SWT also has an NMOS transistor NM whose gate is connected to the control signal line PSWsig, whose source is connected to the ground line TVSS, and whose drain is connected to the virtual ground line VVSS.

[0020] The PMOS transistor PM of the switch transistor SWT turns on when it receives a low-level control signal PSWsig, connecting the power supply line TVDD to the virtual power supply line VVDD, and turns off when it receives a high-level control signal PSWsig, setting the virtual power supply line VVDD in a floating state. The NMOS transistor NM of the switch transistor SWT turns on when it receives a high-level control signal PSWsig, connecting the ground line TVSS to the virtual ground line VVSS, and turns off when it receives a low-level control signal PSWsig, setting the virtual ground line VVSS in a floating state.

[0021] In this way, the PMOS transistor PM and NMOS transistor NM of the switch transistor SWT operate exclusively to supply the power supply voltage TVDD to the virtual power line VVDD and the ground voltage TVSS to the virtual ground line VVSS. This enables the standard cell SC1 to operate when the control signal PSWsig is at a high level, and the standard cell SC2 to operate when the control signal PSWsig is at a low level. The power supply line TVDD is an example of a first power supply line, and the virtual power supply line VVDD is an example of a second power supply line. The ground line TVSS is an example of a third power supply line. The virtual ground line VVSS is an example of a fourth power supply line.

[0022] The standard cell SC1 is connected to a power supply line TVDD and a virtual ground line VVSS. The standard cell SC1 is provided in a block of a footer-type power domain FPD that operates when receiving the virtual ground line VVSS. The standard cell SC2 is connected to a virtual power supply line VVDD and a ground line TVSS. The standard cell SC2 is provided in a block of a header-type power domain HPD that operates when receiving the virtual power supply voltage VVDD. The standard cells SC1 and SC2 have various logic circuits such as an inverter INV.

[0023] Although not particularly limited, the standard cells SC1 and SC2 may be arranged on both sides of the power switch circuit PSW, sandwiching the power switch circuit PSW. Furthermore, the power supply lines TVDD and the virtual ground lines VVSS may be arranged alternately in the block of the footer-type power domain FPD, and the virtual power supply lines VVDD and the ground lines TVSS may be arranged alternately in the header-type power domain HPD. Furthermore, the power supply lines TVDD, the virtual power supply lines VVDD, the ground lines TVSS, and the virtual ground lines VVSS may be arranged in a mixed manner in the region where the power switch circuit PSW is arranged.

[0024] 4 shows a legend for circuit elements used in the plan views of the circuits described below. Note that in the legend, various vias are indicated by solid line shapes, but in the plan views shown in FIG. 6 and subsequent figures, vias hidden by wiring arranged above are indicated by dashed line shapes.

[0025] FIG. 5 shows an example of the layout of the power switch circuit PSW of FIG. 3. In FIG. 5, the interlayer insulating film is omitted, and the substrate SUB is simply indicated by a thick dashed line. The power switch circuit PSW has a semiconductor layer provided on the bottom BTM side and a nanosheet NS (BTM) on the bottom BTM side that connects the semiconductor layers arranged side by side in the Y direction. The Y direction is an example of the second direction. FIG. 5 shows an example in which the semiconductor layer on the bottom BTM side is the source / drain S / D (P-type conductivity) of the PMOS transistor PM of the CFET.

[0026] The power switch circuit PSW has a semiconductor layer provided on the TOP side and a nanosheet NS(TOP) on the TOP side that connects the semiconductor layers arranged side by side in the Y direction. In Fig. 5, an example is shown in which the semiconductor layer on the TOP side is the source / drain S / D (N-type conductivity) of the NMOS transistor NM of the CFET.

[0027] The power switch circuit PSW has a common gate electrode GT that covers the top nanosheet NS (TOP) and the bottom nanosheet NS (BTM). A gate insulating film (not shown) is formed between the gate electrode GT and the bottom BTM and the top nanosheet NS.

[0028] The semiconductor layers on the bottom BTM side are partially connected by bottom wiring BTMW on the bottom BTM side. The semiconductor layers on the top TOP side are partially connected by top wiring TOPW on the top TOP side. The ground line TVSS, power line TVDD, virtual power line VVDD, and virtual ground line VVSS are provided extending in the Y direction as buried wiring BPR provided in the substrate SUB. The ground line TVSS and virtual ground line VVSS are arranged at both ends in the X direction in the region where the power switch circuit PSW is formed, and the power line TVDD and virtual power line VVDD are arranged between the ground line TVSS and virtual ground line VVSS.

[0029] The ground line TVSS may be electrically connected to the source S of the NMOS transistor NM of the switch transistor SWT, and the virtual ground line VVSS may be electrically connected to the drain D of the NMOS transistor NM of the switch transistor SWT. The power supply line TVDD may be electrically connected to the source S of the PMOS transistor PM of the switch transistor SWT, and the virtual power supply line VVDD of the switch transistor SWT may be electrically connected to the drain D of the PMOS transistor PM.

[0030] 5, the source S of the NMOS transistor and the source S of the PMOS transistor are arranged to overlap in the Z direction. The drain D of the NMOS transistor and the drain D of the PMOS transistor are arranged to overlap in the Z direction. Note that the positions of the power supply line TVDD and the virtual power supply line VVDD may be interchanged, and the positions of the ground line TVSS and the virtual ground line VVSS may be interchanged.

[0031] In order to connect the semiconductor layer (S / D) on the top TOP side to the buried wiring BPR, it is not possible to provide a bottom wiring BTMW having a different voltage from the top wiring TOPW below the top wiring TOPW connected to the semiconductor layer (S / D) on the top TOP side. Therefore, the buried wiring BPR connected to the semiconductor layer (S / D) on the top TOP side is arranged on both sides of the power switch circuit PSW in the X direction as shown in FIG.

[0032] This allows the top wiring TOPW and the buried wiring BPR to be connected by the via VIA without being blocked by the bottom wiring BTMW of another voltage. This allows the top wiring TOPW and the buried wiring BPR to be connected without providing a detour wiring or the like to avoid the bottom wiring BTMW, thereby improving wiring efficiency. The X direction is an example of the first direction.

[0033] For example, in the case where an NMOS transistor is formed on the bottom BTM side and a PMOS transistor is formed on the top TOP side, the wiring efficiency can be improved by arranging the power supply line TVDD and the virtual power supply line VVDD on both sides in the X direction. Note that the power switch circuits PSW formed on the four embedded wirings BPR aligned in the X direction shown in FIG. 5 may be repeatedly arranged in the X direction.

[0034] The PMOS transistor PM and NMOS transistor NM of the power switch circuit PSW are disposed on the substrate SUB at a position corresponding to the position between the two buried wirings BPR in plan view. That is, the PMOS transistor PM and NMOS transistor NM of the power switch circuit PSW are disposed at a position shifted in the X direction with respect to the buried wirings BPR in plan view.

[0035] 6 shows an example of a circuit layout on the bottom BTM side formed on the surface of the substrate SUB in the region where the power switch circuit PSW and standard cells SC1 and SC2 of FIG. 5 are formed. The standard cells SC1 and SC2 are formed on both sides of the power switch circuit PSW in the X direction. A PMOS transistor including a P-type semiconductor layer Pdiff is formed on the bottom BTM side. The symbols S and D shown in the semiconductor layer Pdiff indicate the source and drain, respectively. A semiconductor layer Pdiff without the symbols S and D indicates, for example, that it is set in an open state and does not function as a transistor. The source S of the PMOS transistor is an example of one of the first semiconductor layer and the second semiconductor layer, and the drain D of the PMOS transistor is an example of the other of the first semiconductor layer and the second semiconductor layer.

[0036] In the region of the power switch circuit PSW, the switch transistor SWT is formed by a gate GT and a plurality of PMOS transistors, each including a source S and a drain D adjacent to the gate GT in the Y direction. The PMOS transistor of the switch transistor SWT is an example of a first transistor, and the gate GT of the switch transistor SWT is an example of a first gate electrode.

[0037] The source S of the PMOS transistor of the switch transistor SWT is connected to the power supply line TVDD of the BPR layer through the bottom wiring BTMW and the via VIA (BPR-BTM). The source S of the PMOS transistor may be connected to the bottom wiring BTMW connected to the via VIA (BPR-BTM) through the source S of another PMOS transistor.

[0038] The drain D of the PMOS transistor of the switch transistor SWT is connected to the virtual power line VVDD of the BPR layer through the bottom wiring BTMW and the via VIA (BPR-BTM). The drain D of the PMOS transistor may be connected to the bottom wiring BTMW connected to the via VIA (BPR-BTM) through the drain D of another PMOS transistor.

[0039] 6, the inverter INV shown in FIG. 3 is formed in standard cells SC1 and SC2. The source S (TVDD) of the PMOS transistor of standard cell SC1 is connected to the source S of the PMOS transistor of switch transistor SWT via bottom wiring BTMW and is electrically connected to the power supply line TVDD of the BPR layer. The source S (VVDD) of the PMOS transistor of standard cell SC2 is connected to the drain D of switch transistor SWT via bottom wiring BTMW and is electrically connected to the virtual power supply line VVDD of the BPR layer.

[0040] 7 shows an example of a circuit layout on the top TOP side formed on the circuit on the bottom BTM side of FIG. 6 in the region where the power switch circuit PSW and standard cells SC1 and SC2 of FIG. 5 are formed. An NMOS transistor including an N-type semiconductor layer Ndiff is formed on the top side. The symbols S and D shown in the semiconductor layer Ndiff indicate the source and drain, respectively. A semiconductor layer Ndiff without either the symbol S or D indicates, for example, that it is set to an open state and does not function as a transistor. The source S of the NMOS transistor is an example of one of the third semiconductor layer or the fourth semiconductor layer, and the drain D of the NMOS transistor is an example of the other of the third semiconductor layer or the fourth semiconductor layer. Note that in FIG. 7, the diamond-shaped via VIA connecting the top wiring TOPW to the wiring FSM1W is hidden by the wiring FSM1W arranged above, but is shown with a solid line instead of a dashed line for ease of viewing.

[0041] In the area of ​​the power switch circuit PSW, the gate of the switch transistor SWT is connected to a wiring FSM1W in the FSM1 layer through a via VIA (GT-FSM1), and is further connected to a wiring FSM2W in the FSM2 layer through a via (FSM1-FSM2). A control signal PSWsig is supplied to the wiring FSM2W electrically connected to the gate of the switch transistor SWT. The NMOS transistor of the switch transistor SWT is an example of a second transistor.

[0042] 7, the inverter INV shown in FIG. 3 is also formed in the standard cells SC1 and SC2. The source S (VVSS) of the NMOS transistor of the standard cell SC1 is connected to the drain D of the NMOS transistor of the switch transistor SWT via the top wiring TOPW, a via VIA (TOP-FSM1), a wiring FSM1W, a via VIA (TOP-FSM1), and the top wiring TOPW. The gates GT of the NMOS transistor and PMOS transistor of the standard cell SC1 are connected to the wiring FSM1W via a via VIA (GT-FSM1).

[0043] The source S (TVSS) of the NMOS transistor of the standard cell SC2 is connected to the source S of the NMOS transistor of the switch transistor SWT via the top wiring TOPW, a via VIA (TOP-FSM1), a wiring FSM1W, a via VIA (TOP-FSM1), and the top wiring TOPW. The gates of the NMOS transistor and the PMOS transistor of the standard cell SC2 are connected to the wiring FSM1W via a via VIA (GT-FSM1).

[0044] 8 shows an example of a cross section taken along line X1-X1' in Figures 6 and 7. In the power switch circuit PSW, a P-type semiconductor layer Pdiff formed on the bottom BTM side functions as the drain D of the PMOS transistor of the switch transistor SWT, and they are connected to each other via a bottom wiring BTMW. In the power switch circuit PSW, an N-type semiconductor layer Ndiff formed on the top TOP side functions as the drain D of the NMOS transistor of the switch transistor SWT, and they are connected to each other via a top wiring TOPW.

[0045] A P-type semiconductor layer Pdiff formed on the bottom BTM side of the standard cell SC1 functions as, for example, the drain D of the PMOS transistor of the inverter INV. An N-type semiconductor layer Ndiff formed on the top TOP side of the standard cell SC1 functions as, for example, the drain D of the NMOS transistor of the inverter INV. The drain D of the PMOS transistor of the inverter INV of the standard cell SC1 and the drain D of the NMOS transistor NM are connected to each other via a top wiring TOPW, a via VIA (BTM-TOP), and a bottom wiring BTMW (not shown).

[0046] A P-type semiconductor layer Pdiff formed on the bottom BTM side of the standard cell SC2 functions as, for example, the source S of the PMOS transistor of the inverter INV and is connected to the drain D of the PMOS transistor of the switch transistor SWT via the bottom wiring BTMW. An N-type semiconductor layer Ndiff formed on the top TOP side of the standard cell SC2 functions as, for example, the source S of the NMOS transistor of the inverter INV and is connected to the top wiring TOP to which the ground voltage TVSS is supplied.

[0047] 9 shows an example of a cross section taken along line X2-X2' in FIGS. 6 and 7. Each gate GT of the switch transistor SWT is connected to a wiring FSM2W via a via (GT-FSM1), a wiring FSM1W, and a via VIA (FSM1-FSM2). In the standard cells SC1 and SC2, the wiring FSM1W and the like connected to the gate GT via the via (GT-FSM1) are not shown.

[0048] Fig. 10 shows an example of a cross section taken along line Y1-Y1' in Fig. 6 and Fig. 7. As described in Fig. 9, the gate GT of the switch transistor SWT is connected to the wiring FSM2W through the via (GT-FSM1), the wiring FSM1W, and the via VIA (FSM1-FSM2).

[0049] As described above, in the first embodiment, the power switch circuit PSW having a nanosheet structure transistor can be appropriately arranged in the standard cell block SCB by connecting the power switch circuit PSW having nanosheet structure transistors to the power lines (TVSS, TVDD, VVDD, VVSS) of the BPR layer in the layout shown in Fig. 5. Furthermore, as shown in Fig. 6 and Fig. 7, the standard cell SC1 or SC2 receiving the virtual ground voltage VVSS or the virtual power supply voltage VVDD from the power switch circuit PSW can be appropriately arranged in the standard cell block SCB together with the power switch circuit PSW.

[0050] As shown in FIG. 5 and other figures, by arranging the embedded wiring BPR (TVSS, VVSS in the example of FIG. 5) connected to the semiconductor layer (S / D) on the top TOP side on both sides of the power switch circuit PSW in the X direction, it is possible to connect the top wiring TOPW and the embedded wiring BPR without providing a detour wiring or the like to avoid the bottom wiring BTMW, thereby improving wiring efficiency.

[0051] Second Embodiment Fig. 11 shows an example of the layout of a buffer circuit in a semiconductor device according to a second embodiment. Detailed description of elements similar to those in Fig. 5 will be omitted. The semiconductor device including the buffer circuit BUF in Fig. 11 is similar to the semiconductor device 100 in Fig. 1, has a cross-sectional structure similar to that in Fig. 2, and has a standard cell block SCB similar to that in Fig. 3.

[0052] The drains D (PSWsig) of the PMOS transistor PM and NMOS transistor NM, which are the outputs of the inverter INV1 of the buffer circuit BUF, are connected to each other via a bottom wiring BTMW, a via VIA, and a top wiring TOPW, and are further connected to a wiring FSM1W via a via VIA. For example, the switch transistor SWT shown in FIG. 5 is disposed at the end in the Y direction in FIG. 11, and operates in response to a control signal PSWsig output from the inverter INV1.

[0053] Although it is hidden by elements in the foreground in the perspective view and cannot be seen, the source S (TVDD) of the PMOS transistor PM of the inverters INV1 and INV2 of the buffer circuit BUF may be provided in common with the source of the PMOS transistor PM of the switch transistor SWT. Similarly, the source S (TVSS) of the NMOS transistor NM of the inverters INV1 and INV2 may be provided in common with the source of the NMOS transistor NM of the switch transistor SWT. In other words, the switch transistor SWT of the power switch circuit PSW may be disposed at the boundary portion on the front side in the Y direction of the buffer circuit BUF.

[0054] Fig. 12 shows an example of a circuit image of a standard cell block SCB including the buffer circuit of Fig. 11. In Fig. 12, the power switch circuits PSW are arranged in, for example, two regions ROW1 and ROW2.

[0055] An inverter INV1 of the buffer circuit BUF and a switch transistor SWT1, which is a part of the switch transistor SWT, are arranged in the region ROW1. An inverter INV2 of the buffer circuit BUF and a switch transistor SWT2, which is another part of the switch transistor SWT, are arranged in the region ROW2. For example, the inverter INV1 is arranged at the interface of the switch transistor SWT1, and the inverter INV2 is arranged at the interface of the switch transistor SWT2.

[0056] 15 and 16, the source of the switch transistor SWT and the sources of the inverters INV1 and INV2 can be made common, allowing the transistors to be arranged efficiently. Note that the switch transistors SWT1 and SWT2 are arranged in the same power domain.

[0057] As shown by the bold lines, the output (PSWsig) of the inverter INV1 is connected to the input of the switch transistor SWT1, the input of the inverter INV2 in the region ROW2, and the input of the switch transistor SWT2 in the region ROW2. The output of the inverter INV2 may be connected to another control circuit CNTL (FIG. 3) (not shown).

[0058] The drains of the PMOS transistors PM of the switch transistors SWT1 and SWT2 are connected to the virtual power line VVDD. The drains of the NMOS transistors NM of the switch transistors SWT1 and SWT2 are connected to the virtual ground line VVSS. Each standard cell SC1 is connected to the power line TVDD and the virtual ground line VVSS. Each standard cell SC2 is connected to the virtual power line VVDD and the ground line TVSS. Each of the circuit elements shown in FIG. 12 is connected to one or both of the common power line TVDD and the common virtual power line VVDD, and one or both of the common ground line TVSS and the common virtual power line VVDD.

[0059] Fig. 13 shows another example of a circuit image of a standard cell block SCB including the buffer circuit of Fig. 11. Detailed description of elements similar to those in Fig. 12 will be omitted. In Fig. 13, the power switch circuits PSW are arranged in, for example, two regions ROW1 and ROW2.

[0060] The inverter INV1 of the buffer circuit BUF, the dummy circuit DMY1, and the switch transistor SWT1, which is a part of the switch transistor SWT, are arranged in the region ROW1. The inverter INV2 of the buffer circuit BUF, the dummy circuit DMY2, and the switch transistor SWT2, which is another part of the switch transistor SWT, are arranged in the region ROW2. The switch transistors SWT1 and SWT2 are arranged in the same power domain.

[0061] For example, the dummy circuit DMY1 is arranged between the switch transistor SWT1 and the inverter INV1, and the dummy circuit DMY2 is arranged between the switch transistor SWT2 and the inverter INV2. That is, the dummy circuit DMY1 is arranged at the interface of the switch transistor SWT1, and the dummy circuit DMY2 is arranged at the interface of the switch transistor SWT2.

[0062] This makes it easier to electrically isolate the switch transistor SWT1 from the inverter INV1 and the switch transistor SWT2 from the inverter INV2. That is, the switch transistors SWT can be appropriately arranged in the standard cell block SCB.

[0063] As shown by the thick lines, the output (PSWsig) of the inverter INV1 is connected to the input of the dummy circuit DMY1, the input of the switch transistor SWT1, the input of the inverter INV2, the input of the dummy circuit DMY2, and the input of the switch transistor SWT2. The output of the inverter INV2 may be connected to another control circuit CNTL (FIG. 3) (not shown).

[0064] The dummy circuits DMY1 and DMY2 have a PMOS transistor PM and an NMOS transistor NM. The PMOS transistor PM of the dummy circuits DMY1 and DMY2 has a source and a drain fixed to the power supply voltage TVDD and a gate connected to the control signal line PSWsig. The NMOS transistor NM of the dummy circuits DMY1 and DMY2 has a source and a drain fixed to the ground voltage TVSS and a gate connected to the control signal line PSWsig.

[0065] Fig. 14 shows yet another example of a circuit image of a standard cell block SCB including the buffer circuit of Fig. 11. Detailed description of elements similar to those in Fig. 12 will be omitted. In Fig. 14, the power switch circuits PSW are arranged in, for example, two regions ROW1 and ROW2.

[0066] In the region ROW1, inverters INV1 (INV11, INV12) of the buffer circuit BUF and a switch transistor SWT1, which is a part of the switch transistor SWT, are arranged. In the region ROW2, inverters INV2 (INV21, INV22) of the buffer circuit BUF and a switch transistor SWT2, which is another part of the switch transistor SWT, are arranged. Note that the switch transistors SWT1 and SWT2 are arranged in the same power domain. Furthermore, the region ROW1 may have a dummy circuit DMY1 similar to that in FIG. 13, and the region ROW2 may have a dummy circuit DMY2 similar to that in FIG. 13.

[0067] The output (PSWsig) of the inverter INV11 is connected to the input of the inverter INV12 and the input of the switch transistor SWT1. The output of the inverter INV12 is connected to the input of the inverter INV21. The output of the inverter INV21 is connected to the input of the inverter INV22 and the input of the switch transistor SWT2. The output of the inverter INV22 may be connected to another control circuit CNTL (FIG. 3) not shown.

[0068] The switch transistor SWT1 operates by receiving the output of the inverter INV11, and the switch transistor SWT2 operates by receiving the output of the inverter INV11 via the inverters INV12 and INV21. Therefore, the switch transistor SWT2 receives the control signal PSWsig with a delay of the propagation delay time of two stages of the inverters INV12 and INV21 compared to the control signal PSWsig received by the switch transistor SWT1. By shifting the operation timing of the switch transistors SWT1 and SWT2, it is possible to shift the peak of the power supply current flowing through the switch transistors SWT1 and SWT2, and it is possible to suppress power supply noise.

[0069] 15 shows an example of a circuit layout on the bottom BTM side in the region where the standard cell block SCB in FIG. 12 is formed. Detailed description of elements similar to those in FIG. 6 will be omitted. The circuit layout shown in FIG. 15 is similar to that in FIG. 6 except that inverters INV1 and INV2 are arranged adjacent to the power switch circuit PSW.

[0070] 15, of the six PMOS transistors PM of the power switch circuit PSW, the sources of two PMOS transistors PM are shared with the sources of the PMOS transistors PM of the inverters INV1 and INV2, respectively. The drain of the PMOS transistor PM of the inverter INV1 outputs a control signal PSWsig. The gate GT of the inverter INV2 receives the control signal PSWsig. The drains D of the PMOS transistors PM of the inverters INV1 and INV2 are connected to a top wiring TOPW (not shown) via a bottom wiring BTMW and a via VIA (BTM-TOP), respectively.

[0071] 16 shows an example of a circuit layout on the TOP side in the region where the standard cell block SCB in FIG. 12 is formed. Detailed description of elements similar to those in FIG. 7 will be omitted. The circuit layout shown in FIG. 16 is similar to that in FIG. 7 except that inverters INV1 and INV2 are arranged adjacent to the power switch circuit PSW. Note that, in FIG. 16 as well, the diamond-shaped via VIA connecting the top wiring TOPW to the wiring FSM1W is hidden by the wiring FSM1W arranged above, but is shown with a solid line instead of a dashed line for ease of viewing.

[0072] 16, the sources of two of the six NMOS transistors NM of the power switch circuit PSW are provided in common with the sources of the NMOS transistors NM of the inverters INV1 and INV2, respectively. The drain of the NMOS transistor NM of the inverter INV1 outputs a control signal PSWsig.

[0073] The drain D of the NMOS transistor NM of the inverter INV1 is connected to the gate of the switch transistor SWT via the top wiring TOPW, via VIA (TOP-FSM1), wiring FSM1W, via VIA (FSM1-FSM2), wiring FSM2W, via VIA (FSM1-FSM2), wiring FSM1W and via (GT-FSM1). The drain D of the inverter INV2 is connected to the bottom wiring BTMW (not shown) via the top wiring TOPW and via VIA (BTM-TOP).

[0074] The gate GT of the inverter INV2 receives a control signal PSWsig through a wiring FSM2W, a via VIA (FSM1-FSM2), a wiring FSM1W, and a via (GT-FSM1) provided in the region of the switch transistor SWT. The drain D of the NMOS transistor NM of the inverter INV2 is connected to the bottom wiring BTMW in FIG. 15 through a top wiring TOPW and a via VIA (BTM-TOP).

[0075] As described above, in the second embodiment, as in the first embodiment, a power switch circuit PSW having a transistor with a nanosheet structure can be appropriately arranged in a standard cell block SCB. Furthermore, a standard cell SC1 or SC2 that receives a virtual ground voltage VVSS or a virtual power supply voltage VVDD from the power switch circuit PSW can be appropriately arranged in the standard cell block SCB together with the power switch circuit PSW.

[0076] Furthermore, in the second embodiment, by arranging the inverters INV1 and INV2 at the interface of the switch transistor SWT, the source of the switch transistor SWT and the sources of the inverters INV1 and INV2 can be shared, allowing the transistors to be arranged efficiently. Also, the inverter INV1 that outputs the control signal PSWsig to the power switch circuit PSW can be appropriately arranged in the standard cell block SCB together with the power switch circuit PSW and the standard cells SC1 and SC2.

[0077] Although the present invention has been described above based on the embodiments, the present invention is not limited to the requirements shown in the above embodiments. These requirements can be changed without departing from the spirit of the present invention, and can be appropriately determined depending on the application form.

[0078] 100 semiconductor device BPR buried wiring BTM bottom BTMW bottom wiring BUF buffer circuit CNTL control circuit COUT, / COUT control signal D drain DMY1, DMY2 dummy circuit FPD footer type power domain FS surface FSM1, FSM2 wiring layer FSM1W, FSM1W wiring GT gate electrode HPD header type power domain IN input signal line INTR internal circuit area INV, INV1, INV11, INV12, INV2, INV21, INV22 inverter IOC, IOCP I / O cell Ndiff semiconductor layer NM NMOS transistor NS nanosheet OUT output signal line PAD pad Pdiff semiconductor layer PM PMOS transistor PSW power switch circuit PSWsig Control signal ROW1, ROW2 Area S Source SC1, SC2 Standard cell SCB Standard cell block SGNL Signal SUB Substrate SWT, SWT1, SWT2 Switch transistor TOP Top TOPW Top wiring TVDD Power supply line TVSS Ground line VIA Via VVDD Virtual power supply line VVSS Virtual ground line W1 Wiring WL1 Wiring layer

Claims

1. A substrate; a first power supply line, a second power supply line, a third power supply line, and a fourth power supply line formed on the substrate; a first semiconductor layer and a second semiconductor layer formed on the substrate and having a first conductivity type; a first nanosheet formed between the first semiconductor layer and the second semiconductor layer; a third semiconductor layer formed on the first semiconductor layer and having a second conductivity type different from the first conductivity type; a fourth semiconductor layer formed on the second semiconductor layer and having the second conductivity type; a second nanosheet formed between the third semiconductor layer and the fourth semiconductor layer; a first gate electrode covering the first nanosheet and the second nanosheet; and a first transistor electrically provided between the first power supply line and the second power supply line, the first transistor having the first semiconductor layer, the second semiconductor layer, the first nanosheet, and the first gate electrode. a second transistor electrically provided between the third power supply line and the fourth power supply line, the second transistor having the third semiconductor layer, the fourth semiconductor layer, the second nanosheet, and the first gate electrode, wherein the first semiconductor layer is electrically connected to the first power supply line, the second semiconductor layer is electrically connected to the second power supply line, one of the third semiconductor layer and the fourth semiconductor layer is electrically connected to the third power supply line, and the other of the third semiconductor layer and the fourth semiconductor layer is electrically connected to the fourth power supply line.

2. The semiconductor device according to claim 1, comprising: a first standard cell region in which the first power supply line and the fourth power supply line are arranged; a second standard cell region in which the second power supply line and the third power supply line are arranged; and a power switch circuit including the first transistor and the second transistor, wherein the first standard cell region and the second standard cell region are arranged in a first direction in a plan view, with the power switch circuit sandwiched between them.

3. The semiconductor device according to claim 1 or claim 2, wherein the first power supply line, the second power supply line, the third power supply line, and the fourth power supply line are arranged side by side in a first direction in a planar view and extend in a second direction different from the first direction in a planar view; the first semiconductor layer, the second semiconductor layer, the first nanosheet, and the first gate electrode of the first transistor are arranged side by side in the second direction; and the third semiconductor layer, the fourth semiconductor layer, the second nanosheet, and the first gate electrode of the second transistor are arranged side by side in the second direction.

4. The semiconductor device according to claim 3, wherein the third power supply line and the fourth power supply line are arranged at opposite ends in the first direction in a region where the first transistor and the second transistor are formed, and the first power supply line and the second power supply line are arranged between the third power supply line and the fourth power supply line.

5. The semiconductor device according to claim 1 or claim 2, further comprising a control circuit arranged adjacent to an area in which the first transistor and the second transistor are arranged, the output of the control circuit being connected to the first gate electrodes of the first transistor and the second transistor.

6. The semiconductor device according to claim 5, wherein the control circuit has an inverter that outputs a control signal, the source of a PMOS transistor of the inverter being provided in common with the first semiconductor layer, and the source of an NMOS transistor of the inverter being provided in common with either the third semiconductor layer or the fourth semiconductor layer.

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