Semiconductor device

Abstract

A semiconductor device according to the present invention comprises: first and second semiconductor layers formed on a second surface of a substrate; a first transistor having a first nanosheet and a first gate electrode; a second transistor having third and fourth semiconductor layers formed on the first transistor, a second nanosheet, and the first gate electrode; first and second power supply lines formed on the first surface of the substrate and respectively connected to the first and second semiconductor layers; and third and fourth power supply lines respectively connected to one and the other of the third and fourth semiconductor layers. Thus, a power supply switch circuit having a transistor having a nanosheet structure can be appropriately arranged in the semiconductor device.

Description

Semiconductor Devices

[0001] The present invention relates to a semiconductor device.

[0002] A known technology is the CFET (Complementary Field Effect Transistor) technology, which forms transistors by stacking them. A known technology is the BS-PDN (Backside Power Delivery Network) technology, which supplies power to elements such as transistors formed on the surface of a semiconductor substrate from the back surface of the substrate. A known technology is to provide a via that directly connects the back surface of the substrate to the gate electrode of the transistor on the surface. A known technology is to provide a power switch circuit in a semiconductor device that switches on / off the supply of power to a circuit.

[0003] US Patent Application Publication No. 2023 / 0178435 US Patent Application Publication No. 2023 / 0067311 US Patent Application Publication No. 2022 / 0123023 US Patent Application Publication No. 2022 / 0181258 International Publication No. 2020 / 065916 International Publication No. 2020 / 066797 International Publication No. 2020 / 217396 International Publication No. 2020 / 217400 US Patent Application Publication No. 2021 / 0366902 US Patent Application Publication No. 2022 / 0102479 US Patent Application Publication No. 2021 / 0210600

[0004] Depending on the type of power switch circuit, there are some cases where detailed consideration has not been given to how the power switch circuit should be arranged in the semiconductor device.

[0005] The present invention has been made in view of the above points, and aims to appropriately arrange a power switch circuit having a transistor with a nanosheet structure in a semiconductor device.

[0006] In one aspect of the present invention, a semiconductor device includes a substrate; a first power supply line, a second power supply line, a third power supply line, and a fourth power supply line formed on a first surface of the substrate; a first semiconductor layer and a second semiconductor layer having a first conductivity type formed on a second surface of the substrate opposite to the first surface; a first nanosheet formed between the first semiconductor layer and the second semiconductor layer; a third semiconductor layer formed on the first semiconductor layer and having a second conductivity type different from the first conductivity type; a fourth semiconductor layer formed on the second semiconductor layer and having the second conductivity type; a second nanosheet formed between the third semiconductor layer and the fourth semiconductor layer; and a first gate electrode covering the first nanosheet and the second nanosheet. The semiconductor device includes: a first transistor electrically provided between the first power supply line and the second power supply line, the first transistor having the first semiconductor layer, the second semiconductor layer, the first nanosheet, and the first gate electrode; and a second transistor electrically provided between the third power supply line and the fourth power supply line, the second transistor having the third semiconductor layer, the fourth semiconductor layer, the second nanosheet, and the first gate electrode, wherein the first semiconductor layer is electrically connected to the first power supply line, the second semiconductor layer is electrically connected to the second power supply line, one of the third semiconductor layer and the fourth semiconductor layer is electrically connected to the third power supply line, and the other of the third semiconductor layer and the fourth semiconductor layer is electrically connected to the fourth power supply line.

[0007] According to the disclosed technology, a power switch circuit having a transistor with a nanosheet structure can be appropriately arranged in a semiconductor device.

[0008] 1 is a plan view showing an example of a layout of a semiconductor device in a first embodiment. It is a cross-sectional view showing an example of a cross-sectional structure of the semiconductor device of FIG. 1. It is a circuit diagram showing an example of a circuit arranged in the standard cell block of FIG. 1. It is an explanatory diagram showing a legend of circuit elements used in the plan views of the circuits described below. It is a perspective view showing an example of a layout of the power switch circuit of FIG. 3. It is an explanatory diagram showing an example of a method of connecting top wiring and wiring of a BSM1 layer formed on the back surface of a substrate. It is a plan view showing an example of a plan view of the BSM1 layer and the BSM2 layer in a region where the power switch circuit and standard cells of FIG. 3 are formed. It is a plan view showing an example of a bottom-side circuit layout formed on the front surface of a substrate in a region where the power switch circuit and standard cells of FIG. 3 are formed. It is a plan view showing an example of a top-side circuit layout formed on the bottom-side circuit of FIG. 6 in a region where the power switch circuit and standard cells of FIG. 3 are formed. It is a cross-sectional view showing an example of a cross section taken along line X1-X1' in FIGS. 7 to 9. It is a cross-sectional view showing an example of a cross section taken along line X2-X2' in FIGS. 7 to 9. It is a cross-sectional view showing an example of a cross section taken along line Y1-Y1' in FIGS. 7 to 9. It is a perspective view showing an example of a layout of a buffer circuit in a semiconductor device of a second embodiment. 14 is a plan view showing an example of a circuit layout on the bottom side in a region where a standard cell block SCB including the buffer circuit of FIG. 13 is formed, and a plan view showing an example of a circuit layout on the top side in a region where a standard cell block SCB including the buffer circuit of FIG.

[0009] Hereinafter, embodiments will be described with reference to the drawings. In the following, a symbol indicating a signal is also used to indicate a signal line or a signal terminal. A symbol indicating a power supply voltage is also used to indicate a power supply line or a power supply terminal to which the power supply voltage is supplied.

[0010] 1 shows an example of the layout of a semiconductor device according to the first embodiment. For example, the semiconductor device 100 shown in FIG. 1 may be a SoC (System on Chip), a standalone FPGA (Field-Programmable Gate Array), or the like.

[0011] The semiconductor device 100 has a plurality of I / O cells IOC and IOCP and an internal circuit region INTR. The I / O cell IOC is an interface circuit for a signal SGNL such as an input signal, an output signal, or an input / output signal. The I / O cell IOCP is an interface circuit for a power supply voltage or a ground voltage.

[0012] Each I / O cell IOC, IOCP is connected to an internal circuit region INTR. For example, the internal circuit region INTR has one or more standard cell blocks SCB in which standard cells are provided. Note that the internal circuit region INTR may also be equipped with logic circuits other than standard cells, or may also be equipped with a memory. The memory may be equipped within the standard cell block SCB.

[0013] Fig. 2 shows an example of a cross-sectional structure of the semiconductor device 100 of Fig. 1. The semiconductor device 100 has a substrate SUB, a wiring layer WL1 formed on the front surface FS side of the substrate SUB, and a wiring layer WL2 formed on the back surface BS side of the substrate SUB. The front surface FS of the substrate SUB is an example of a second surface, and the back surface BS of the substrate SUB is an example of a first surface.

[0014] A CFET is formed on the surface FS of the substrate. The CFET has a source / drain S / D formed in a semiconductor layer on the bottom BTM, which is closer to the substrate SUB, a nanosheet NS on the bottom BTM side that interconnects the source S and drain D, a source / drain S / D formed in a semiconductor layer on the top TOP side, which is farther from the substrate SUB, and a nanosheet NS on the top TOP side that interconnects the source S and drain D. The CFET also has a gate insulating film (not shown) and a gate electrode GT formed on the nanosheet NS.

[0015] The nanosheet NS that interconnects the source S and drain D on the bottom BTM side is an example of a first nanosheet. The nanosheet NS that interconnects the source S and drain D on the top TOP side is an example of a second nanosheet. Hereinafter, the gate electrode GT will also be simply referred to as the gate GT. In addition, the wiring and semiconductor layer arranged on the bottom BTM side may be indicated by the symbol BTM, and the wiring and semiconductor layer arranged on the top TOP side may be indicated by the symbol TOP. The wiring arranged on the bottom BTM side may also be referred to as the bottom wiring BTMW, and the wiring arranged on the top TOP side may also be referred to as the top wiring TOPW.

[0016] Furthermore, a part of the structure of a CFET may be referred to as an NMOS transistor or a PMOS transistor depending on the conductivity type of its semiconductor layer. The semiconductor layer may be referred to as a source / drain S / D, even if it does not function as a transistor. Furthermore, a part of the structure of a CFET may be referred to as an NMOS transistor or a PMOS transistor depending on the conductivity type of its semiconductor layer, even if it does not function as a transistor. For example, the source / drain S / D or gate GT of the CFET may be connected to wiring W1 formed in a wiring layer FSM1 (FSM stands for Frontside Metal) or the like.

[0017] The wiring layer WL1 may have a wiring layer FSM1 on which the wiring W3 is formed above the region on the top side TOP. Note that the wiring layer WL1 may have multiple wiring layers FSM (such as an FSM1 layer and an FSM2 layer). Hereinafter, the wiring layers FSM1 and FSM2 are also referred to as the FSM1 layer and the FSM2 layer.

[0018] The wiring layer WL2 has wiring layers BSM1 and BSM2 (BSM stands for Backside Metal). The wiring layer WL2 may have one wiring layer BSM, or may have three or more wiring layers BSM. For example, wirings W1 and W2 such as power supply lines or ground lines are formed in the wiring layers BSM1 and BSM2, respectively. The wirings W1 and W2 may be connected to each other via vias VIA.

[0019] A power supply line or a ground line of the wiring layer BSM1 is connected to one end of a via VIA such as a TSV formed in the substrate SUB, and the other end of the via VIA is directly connected to the source S or drain D of the CFET. A wire W1 of the wiring layer BSM1 may be connected to a buried wiring BPR (Buried Power Rail) buried in the surface of the substrate SUB through a via VIA such as a TSV. The wiring layer WL2 may be a wiring layer formed on the back surface of the substrate SUB, or may be a wiring layer formed in another chip bonded to the back surface of the substrate SUB. Hereinafter, the wiring layers BSM1 and BSM2 are also referred to as a BSM1 layer and a BSM2 layer.

[0020] 3 shows an example of a circuit arranged in the standard cell block SCB of FIG. 1. The standard cell block SCB has a power switch circuit PSW and standard cells SC1 and SC2 having different power domains. The standard cell SC1 is an example of a first standard cell region, and the standard cell SC2 is an example of a second standard cell region.

[0021] The power switch circuit PSW has a control circuit CNTL and a switch transistor SWT, and operates by receiving a power supply voltage TVDD supplied from a power line TVDD and a ground voltage TVSS supplied from a ground line TVSS. The control circuit CNTL has a buffer circuit BUF including inverters INV1 and INV2 connected in series. The buffer circuit BUF generates a control signal PSWsig for controlling the switch transistor SWT from the output of the inverter INV1.

[0022] The switch transistor SWT has a PMOS transistor PM whose gate is connected to the control signal line PSWsig, whose source is connected to the power supply line TVDD, and whose drain is connected to the virtual power supply line VVDD. The switch transistor SWT also has an NMOS transistor NM whose gate is connected to the control signal line PSWsig, whose source is connected to the ground line TVSS, and whose drain is connected to the virtual ground line VVSS.

[0023] The PMOS transistor PM of the switch transistor SWT turns on when it receives a low-level control signal PSWsig, connecting the power supply line TVDD to the virtual power supply line VVDD, and turns off when it receives a high-level control signal PSWsig, setting the virtual power supply line VVDD in a floating state. The NMOS transistor NM of the switch transistor SWT turns on when it receives a high-level control signal PSWsig, connecting the ground line TVSS to the virtual ground line VVSS, and turns off when it receives a low-level control signal PSWsig, setting the virtual ground line VVSS in a floating state.

[0024] In this way, the PMOS transistor PM and NMOS transistor NM of the switch transistor SWT operate exclusively to supply the power supply voltage TVDD to the virtual power line VVDD and the ground voltage TVSS to the virtual ground line VVSS. This enables the standard cell SC1 to operate when the control signal PSWsig is at a high level, and the standard cell SC2 to operate when the control signal PSWsig is at a low level. The power supply line TVDD is an example of a first power supply line, and the virtual power supply line VVDD is an example of a second power supply line. The ground line TVSS is an example of a third power supply line, and the virtual ground line VVSS is an example of a fourth power supply line.

[0025] The standard cell SC1 is connected to a power supply line TVDD and a virtual ground line VVSS. The standard cell SC1 is provided in a block of a footer-type power domain FPD that operates when the virtual ground line VVSS is applied. The standard cell SC2 is connected to a virtual power supply line VVDD and a ground line TVSS. The standard cell SC2 is provided in a block of a header-type power domain HPD that operates when the virtual power supply voltage VVDD is applied. The standard cells SC1 and SC2 have various logic circuits such as an inverter INV.

[0026] Although not particularly limited, the standard cells SC1 and SC2 may be arranged on both sides of the power switch circuit PSW, sandwiching the power switch circuit PS. Furthermore, in the block of the footer-type power domain FPD, the power supply lines TVDD and the virtual ground lines VVSS may be arranged alternately, and in the header-type power domain HPD, the virtual power supply lines VVDD and the ground lines TVSS may be arranged alternately. Furthermore, in the region where the power switch circuit PSE is arranged, the power supply lines TVDD, the virtual power supply lines VVDD, the ground lines TVSS, and the virtual ground lines VVSS may be arranged in a mixed manner.

[0027] 4 shows a legend for circuit elements used in the plan views of the circuits described below. Note that in the legend, various vias are indicated by solid line shapes, but in the plan views shown in FIG. 7 and subsequent figures, vias hidden by wiring arranged above are indicated by dashed line shapes.

[0028] FIG. 5 shows an example of the layout of the power switch circuit PSW of FIG. 3. In FIG. 5, the interlayer insulating film is omitted, and the substrate SUB is simply indicated by a thick dashed line. The power switch circuit PSW has a semiconductor layer provided on the bottom BTM side and a nanosheet NS (BTM) on the bottom BTM side that connects the semiconductor layers arranged side by side in the Y direction. The Y direction is an example of the second direction. FIG. 5 shows an example in which the semiconductor layer on the bottom BTM side is the source / drain S / D (P-type conductivity) of the PMOS transistor PM of the CFET.

[0029] The power switch circuit PSW has a semiconductor layer provided on the TOP side and a nanosheet NS(TOP) on the TOP side that connects the semiconductor layers arranged side by side in the Y direction. In Fig. 5, an example is shown in which the semiconductor layer on the TOP side is the source / drain S / D (N-type conductivity) of the NMOS transistor NM of the CFET.

[0030] The power switch circuit PSW has a common gate electrode GT that covers the top nanosheet NS (TOP) and the bottom nanosheet NS (BTM). A gate insulating film (not shown) is formed between the gate electrode GT and the bottom BTM and the top nanosheet NS.

[0031] The semiconductor layers on the bottom BTM side are partially connected by bottom wiring BTMW on the bottom BTM side. The semiconductor layers on the top TOP side are partially connected by top wiring TOPW on the top TOP side. The ground line TVSS, power line TVDD, virtual power line VVDD, and virtual ground line VVSS are provided extending in the Y direction as wiring in the BSM1 layer provided on the back surface of the substrate SUB. The ground line TVSS and virtual ground line VVSS are arranged at both ends in the X direction in the region where the power switch circuit PSW is formed, and the power line TVDD and virtual power line VVDD are arranged between the ground line TVSS and virtual ground line VVSS.

[0032] The ground line TVSS of the wiring layer BSM1 is connected to one end of a via VIA such as a TSV formed in the substrate SUB, and the other end of the via VIA may be directly connected to the source S of the NMOS transistor NM of the CFET. The power supply line TVDD of the wiring layer BSM1 is connected to one end of a via VIA such as a TSV formed in the substrate SUB, and the other end of the via VIA may be directly connected to the source S of the PMOS transistor PM of the CFET.

[0033] The virtual ground line VVSS of the wiring layer BSM1 may be connected to one end of a via VIA such as a TSV formed in the substrate SUB, and the other end of the via VIA may be electrically connected to the drain D of the NMOS transistor NM of the CFET. The virtual power supply line VVDD of the wiring layer BSM1 may be connected to one end of a via VIA such as a TSV (not shown) formed in the substrate SUB, and the other end of the via VIA may be electrically connected to the drain D of the PMOS transistor PM of the CFET.

[0034] 5, the source S of the NMOS transistor and the source S of the PMOS transistor are arranged to overlap in the Z direction. The drain D of the NMOS transistor and the drain D of the PMOS transistor are arranged to overlap in the Z direction.

[0035] 6A and 6B show examples of a method for connecting the top wiring TOPW and the wiring in the BSM1 layer formed on the back surface of the substrate. As shown in FIG. 6A, the top wiring TOPW and the wiring in the BSM1 layer may be connected via the bottom wiring BTMW, as in the layout of FIG. 5. Also, as shown in FIG. 6B, the top wiring TOPW and the wiring in the BSM1 layer may be directly connected by a TSV without using the bottom wiring BTMW. Note that the wiring method of FIG. 6B may be applied to other embodiments.

[0036] 7 shows an example of a plan view of the BSM1 layer and the BSM2 layer in the region where the power switch circuit PSW and the standard cells SC in FIG. 3 are formed. The wiring in the BSM1 layer extends in the Y direction and is arranged at intervals in the X direction. The wiring in the BSM2 layer extends in the X direction and is arranged at intervals in the Y direction. The X direction is an example of a first direction. In the BSM1 layer and the BSM2 layer, wiring of the same type (e.g., virtual power line VVDD) may be connected to each other through vias VIA (BSM1-BSM2).

[0037] 8 shows an example of a circuit layout on the bottom BTM side formed on the surface of the substrate SUB in the region where the power switch circuit PSW and standard cells SC1 and SC2 of FIG. 3 are formed. The standard cells SC1 and SC2 are formed on both sides of the power switch circuit PSW in the X direction. A PMOS transistor including a P-type semiconductor layer Pdiff is formed on the bottom BTM side. The symbols S and D shown in the semiconductor layer Pdiff indicate the source and drain, respectively. A semiconductor layer Pdiff without the symbols S and D indicates, for example, that it is set in an open state and does not function as a transistor. The source S of the PMOS transistor is an example of one of the first semiconductor layer and the second semiconductor layer, and the drain D of the PMOS transistor is an example of the other of the first semiconductor layer and the second semiconductor layer.

[0038] In the region of the power switch circuit PSW, the switch transistor SWT has a gate GT and a plurality of PMOS transistors, each including a source S and a drain D adjacent to the gate GT in the Y direction. The PMOS transistor of the switch transistor SWT is an example of a first transistor, and the gate GT of the switch transistor SWT is an example of a first gate electrode.

[0039] The source S of the PMOS transistor of the switch transistor SWT is connected to the power supply line TVDD of the BSM1 layer through a via VIA (BSM1-BTM). The drain D of the PMOS transistor of the switch transistor SWT is connected to the virtual power supply line VVDD of the BSM1 layer through a bottom wiring BTMW and a via VIA (BSM1-BTM).

[0040] 8, the inverter INV shown in FIG. 3 is formed in standard cells SC1 and SC2. The source S (TVDD) of the PMOS transistor of standard cell SC1 is connected to the power supply line TVDD of the BSM1 layer through a via VIA (BSM1-BTM). The drain D of the PMOS transistor of standard cell SC1 is connected to a top wiring TOPW (not shown) through a bottom wiring BTMW and a via VIA (BTM2-TOP).

[0041] The source S (VVDD) of the PMOS transistor of the standard cell SC2 is connected to the virtual power line VVDD of the BSM1 layer through a via VIA (BSM1-BTM). The drain D of the PMOS transistor of the standard cell SC1 is connected to a top wiring TOPW (not shown) through a bottom wiring BTMW and a via VIA (BTM2-TOP).

[0042] 9 shows an example of a circuit layout on the top TOP side formed on the circuit on the bottom BTM side of FIG. 8 in the region where the power switch circuit PSW and standard cells SC1 and SC2 of FIG. 3 are formed. An NMOS transistor including an N-type semiconductor layer Ndiff is formed on the top side. The symbols S and D shown in the semiconductor layer Ndiff indicate the source and drain, respectively. A semiconductor layer Ndiff without either the symbol S or D indicates, for example, that it is set in an open state and does not function as a transistor. The source S of the NMOS transistor is an example of either the third semiconductor layer or the fourth semiconductor layer, and the drain D of the NMOS transistor is an example of the other of the third semiconductor layer or the fourth semiconductor layer.

[0043] In the region of the power switch circuit PSW, the switch transistor SWT has a gate GT and a plurality of NMOS transistors each including a source S and a drain D adjacent to the gate GT in the Y direction. The NMOS transistor of the switch transistor SWT is an example of a second transistor.

[0044] The gate GT of the switch transistor SWT is connected to a wiring FSM1W in the FSM1 layer through a via VIA (GT-FSM1), and is further connected to a wiring FSM2W in the FSM2 layer through a via (FSM1-FSM2). A control signal PSWsig is supplied to the wiring FSM2W electrically connected to the gate of the switch transistor SWT.

[0045] The source S of the NMOS transistor NM of the switch transistor SWT is connected to a bottom wiring BTMW (not shown) through a top wiring TOPW and a via VIA (BTMW-TOPW). The drain D of the NMOS transistor NM of the switch transistor SWT is connected to a virtual ground line VVSS of the BSM1 layer through a top wiring TOPW and a via VIA (BSM1-TOP).

[0046] 9, the inverter INV shown in FIG. 3 is also formed in standard cells SC1 and SC2. The source S (VVSS) of the NMOS transistor in standard cell SC1 is connected to the virtual ground line VVSS of the BSM layer through the top wiring TOPW and a via VIA (BSM1-TOP). The drain D of the NMOS transistor in standard cell SC1 is connected to the bottom wiring BTMW (not shown) through the top wiring TOPW and a via VIA (BTMW-TOPW). The gates of the NMOS transistor and PMOS transistor in standard cell SC1 are connected to wiring FSM1W through a via VIA (GT-FSM1).

[0047] The source S (TVSS) of the NMOS transistor of the standard cell SC2 is connected to a bottom wiring BTMW (not shown) through a top wiring TOPW and a via VIA (BTMW-TOPW). The drain D of the NMOS transistor of the standard cell SC2 is connected to a bottom wiring BTMW (not shown) through a top wiring TOPW and a via VIA (BTMW-TOPW). The gates of the NMOS transistor and PMOS transistor of the standard cell SC2 are connected to a wiring FSM1W through a via VIA (GT-FSM1).

[0048] 10 shows an example of a cross section taken along line X1-X1' in FIGS. 7 to 9. In the power switch circuit PSW, the P-type semiconductor layer Pdiff formed on the bottom BTM side functions as the drain D of the PMOS transistor of the switch transistor SWT, and is connected to each other via bottom wiring BTMW and to the virtual power line VVDD of the BSM1 layer via a via VIA. In the power switch circuit PSW, the N-type semiconductor layer Ndiff formed on the top TOP side functions as the drain D of the NMOS transistor of the switch transistor SWT, and is connected to each other via top wiring TOPW.

[0049] A P-type semiconductor layer Pdiff formed on the bottom BTM side of the standard cell SC1 functions as, for example, the source S of the PMOS transistor of the inverter INV. An N-type semiconductor layer Ndiff formed on the top TOP side of the standard cell SC1 functions as, for example, the source S of the NMOS transistor of the inverter INV.

[0050] A P-type semiconductor layer Pdiff formed on the bottom BTM side of the standard cell SC2 functions as, for example, the drain D of the PMOS transistor of the inverter INV. An N-type semiconductor layer Ndiff formed on the top TOP side of the standard cell SC2 functions as, for example, the drain D of the NMOS transistor of the inverter INV and is electrically connected to the drain of the PMOS transistor of the inverter INV.

[0051] 11 shows an example of a cross section taken along line X2-X2' in Figures 7 to 9. Each gate GT of the switch transistor SWT is connected to wiring FSM2W through a via (GT-FSM1), wiring FSM1W, and via VIA (FSM1-FSM2). The gates GT of the standard cells SC1 and SC2 are connected to wiring FSM1W through a via VIA (GT-FSM1).

[0052] Fig. 12 shows an example of a cross section taken along line Y1-Y1' in Fig. 7 to Fig. 9. As described in Fig. 11, the gate GT of the switch transistor SWT is connected to the wiring FSM2W through the via (GT-FSM1), the wiring FSM1W, and the via VIA (FSM1-FSM2).

[0053] As described above, in the first embodiment, the power switch circuit PSW having a nanosheet structure transistor can be appropriately arranged in the standard cell block SCB by connecting the power switch circuit PSW having nanosheet structure transistors to the power lines (TVSS, TVDD, VVDD, VVSS) of the BSM1 layer in the layout shown in Fig. 5. Furthermore, as shown in Figs. 8 and 9, the standard cell SC1 or SC2 receiving the virtual ground voltage VVSS or the virtual power supply voltage VVDD from the power switch circuit PSW can be appropriately arranged in the standard cell block SCB together with the power switch circuit PSW.

[0054] As shown in FIG. 5 and other figures, by arranging the power supply lines (TVSS, VVSS in the example of FIG. 5) of the BSM1 layer connected to the semiconductor layer (S / D) on the top TOP side on both sides of the power switch circuit PSW in the X direction, it is possible to connect the top wiring TOPW and the power supply lines of the BSM1 layer without providing detour wiring or the like to avoid the bottom wiring BTMW, thereby improving wiring efficiency.

[0055] The semiconductor layer of the transistor arranged on the bottom BTM side (the source of the PMOS transistor in the example of FIG. 5) is arranged to overlap the power supply line of the BSM1 layer (TVDD in the example of FIG. 5) in a plan view. This allows one end of a via VIA such as a TSV formed in the substrate SUB to be directly connected to the semiconductor layer of the transistor, and the other end of the via VIA to be directly connected to the power supply line of the BSM1 layer.

[0056] Second Embodiment Fig. 13 shows an example of a buffer circuit in a semiconductor device according to a second embodiment. Detailed description of elements similar to those in Fig. 5 will be omitted. A semiconductor memory device including the buffer circuit BUF in Fig. 13 is similar to the semiconductor device 100 in Fig. 1, has a cross-sectional structure similar to that in Fig. 2, and has a standard cell block SCB similar to that in Fig. 3.

[0057] The drains D (PSWsig) of the PMOS transistor PM and NMOS transistor NM, which are the outputs of the inverter INV1 of the buffer circuit BUF, are connected to each other via a bottom wiring BTMW, a via VIA (BTM-TOP), and a top wiring TOPW, and are further connected to a wiring FSM1W via a via VIA (TOP-FSM1). For example, the switch transistor SWT shown in FIG. 5 is disposed at the end in the Y direction in FIG. 13, and operates in response to a control signal PSWsig output from the inverter INV1.

[0058] Although it is hidden by elements in the foreground in the perspective view and cannot be seen, the source S (TVDD) of the PMOS transistor PM of the inverters INV1 and INV2 may be provided in common with the source of the PMOS transistor PM of the switch transistor SWT. Similarly, the source S (TVSS) of the NMOS transistor NM of the inverters INV1 and INV2 may be provided in common with the source of the NMOS transistor NM of the switch transistor SWT. In other words, the switch transistor SWT of the power switch circuit PSW may be disposed at the boundary portion on the front side in the Y direction of the buffer circuit BUF.

[0059] Fig. 14 shows an example of a circuit layout on the bottom BTM side in an area where a standard cell block SCB including the buffer circuit BUF in Fig. 13 is formed. Detailed description of elements similar to those in Fig. 8 will be omitted. The circuit layout shown in Fig. 14 is similar to that in Fig. 8 except that inverters INV1 and INV2 are arranged adjacent to the power switch circuit PSW.

[0060] 14, of the six PMOS transistors PM of the power switch circuit PSW, the sources of two PMOS transistors PM are shared with the sources of the PMOS transistors PM of the inverters INV1 and INV2, respectively. The drain of the PMOS transistor PM of the inverter INV1 outputs a control signal PSWsig. The gate GT of the inverter INV2 receives the control signal PSWsig. The drains D of the PMOS transistors PM of the inverters INV1 and INV2 are connected to a top wiring TOPW (not shown) via a bottom wiring BTMW and a via VIA (BTM-TOP).

[0061] 15 shows an example of a circuit layout on the TOP side in an area where a standard cell block SCB including the buffer circuit BUF of FIG. 13 is formed. Detailed description of elements similar to those in FIG. 9 will be omitted. The circuit layout shown in FIG. 15 is similar to that in FIG. 9 except that inverters INV1 and INV2 are arranged adjacent to the power switch circuit PSW. Note that in FIG. 15, the diamond-shaped via VIA connecting the top wiring TOPW to the wiring FSM1W is hidden by the wiring FSM1W arranged above, but is shown with a solid line instead of a dashed line for ease of viewing.

[0062] 15, the sources S of two of the six NMOS transistors NM of the power switch circuit PSW are shared with the sources of the NMOS transistors NM of the inverters INV1 and INV2, respectively. The drain D of the NMOS transistor NM of the inverter INV1 outputs a control signal PSWsig.

[0063] The drain of the NMOS transistor NM of the inverter INV1 is connected to the gate of the switch transistor SWT via the top wiring TOPW, a via VIA (TOP-FSM1), a wiring FSM1W, a via VIA (FSM1-FSM2), a wiring FSM2W, a via VIA (FSM1-FSM2), a wiring FSM1W, and a via (GT-FSM1). The drain D of the inverter INV2 is connected to the bottom wiring BTMW (not shown) via the top wiring TOPW and a via VIA (BTM-TOP).

[0064] The gate GT of the inverter INV2 receives a control signal PSWsig through a wiring FSM2W, a via VIA (FSM1-FSM2), a wiring FSM1W, and a via (GT-FSM1) provided in the region of the switch transistor SWT. The drain D of the NMOS transistor NM of the inverter INV2 is connected to the bottom wiring BTMW in FIG. 15 through a top wiring TOPW and a via VIA (BTM-TOP).

[0065] As described above, in the second embodiment, as in the first embodiment, a power switch circuit PSW having a transistor with a nanosheet structure can be appropriately arranged in a standard cell block SCB. Furthermore, a standard cell SC1 or SC2 that receives a virtual ground voltage VVSS or a virtual power supply voltage VVDD from the power switch circuit PSW can be appropriately arranged in the standard cell block SCB together with the power switch circuit PSW.

[0066] Furthermore, in the second embodiment, by arranging the inverters INV1 and INV2 at the interface of the switch transistor SWT, the source of the switch transistor SWT and the sources of the inverters INV1 and INV2 can be shared, allowing the transistors to be arranged efficiently. Also, the inverter INV1 that outputs the control signal PSWsig to the power switch circuit PSW can be appropriately arranged in the standard cell block SCB together with the power switch circuit PSW and the standard cells SC1 and SC2.

[0067] Although the present invention has been described above based on the embodiments, the present invention is not limited to the requirements shown in the above embodiments. These requirements can be changed without departing from the spirit of the present invention, and can be appropriately determined depending on the application form.

[0068] 100 Semiconductor device BS Back surface BSM1, BSM2 Wiring layer BTM Bottom BTMW Bottom wiring BUF Buffer circuit CNTL Control circuit COUT, / COUT Control signal D Drain FPD Footer type power domain FS Top surface FSM1, FSM2 Wiring layer FSM1W, FSM1W Wiring GT Gate electrode HPD Header type power domain IN Input signal line INTR Internal circuit area INV, INV1, INV2 Inverter IOC, IOCP I / O cell Ndiff Semiconductor layer NM NMOS transistor NS Nanosheet OUT Output signal line PAD Pad Pdiff Semiconductor layer PM PMOS transistor PSW Power switch circuit PSWsig Control signal S Source SC1, SC2 Standard cell SCB Standard cell block SGNL Signal SUB Substrate SWT Switch transistor TOP Top TOPW Top wiring TVDD Power line TVSS Ground line VIA Via VVDD Virtual power line VVSS Virtual ground line W1, W2, W3 Wiring WL1, WL2 Wiring layer

Claims

1. A substrate; a first power line, a second power line, a third power line, and a fourth power line formed on a first surface of the substrate; a first semiconductor layer and a second semiconductor layer having a first conductivity type formed on a second surface of the substrate opposite to the first surface; a first nanosheet formed between the first semiconductor layer and the second semiconductor layer; a third semiconductor layer formed on the first semiconductor layer and having a second conductivity type different from the first conductivity type; a fourth semiconductor layer formed on the second semiconductor layer and having the second conductivity type; a second nanosheet formed between the third semiconductor layer and the fourth semiconductor layer; a first gate electrode covering the first nanosheet and the second nanosheet; and a first transistor electrically provided between the first power line and the second power line, the first transistor having the first semiconductor layer, the second semiconductor layer, the first nanosheet, and the first gate electrode. a second transistor electrically provided between the third power supply line and the fourth power supply line, the second transistor having the third semiconductor layer, the fourth semiconductor layer, the second nanosheet, and the first gate electrode, wherein the first semiconductor layer is electrically connected to the first power supply line, the second semiconductor layer is electrically connected to the second power supply line, one of the third semiconductor layer and the fourth semiconductor layer is electrically connected to the third power supply line, and the other of the third semiconductor layer and the fourth semiconductor layer is electrically connected to the fourth power supply line.

2. The semiconductor device according to claim 1, comprising: a first standard cell region in which the first power supply line and the fourth power supply line are arranged; a second standard cell region in which the second power supply line and the third power supply line are arranged; and a power switch circuit including the first transistor and the second transistor, wherein the first standard cell region and the second standard cell region are arranged in a first direction in a plan view, with the power switch circuit sandwiched between them.

3. The semiconductor device according to claim 1 or claim 2, wherein the first power supply line, the second power supply line, the third power supply line, and the fourth power supply line are arranged side by side in a first direction in a planar view and extend in a second direction different from the first direction in a planar view; the first semiconductor layer, the second semiconductor layer, the first nanosheet, and the first gate electrode of the first transistor are arranged side by side in the second direction; and the third semiconductor layer, the fourth semiconductor layer, the second nanosheet, and the first gate electrode of the second transistor are arranged side by side in the second direction.

4. The semiconductor device according to claim 3, wherein the third power supply line and the fourth power supply line are arranged at opposite ends in the first direction in a region where the first transistor and the second transistor are formed, and the first power supply line and the second power supply line are arranged between the third power supply line and the fourth power supply line.

5. The semiconductor device according to claim 3, further comprising a via formed in the substrate, the first power supply line being arranged to overlap the first transistor in a planar view, one end of the via being directly connected to the first semiconductor layer, and the other end of the via being connected to the first power supply line.

6. The semiconductor device according to claim 1 or claim 2, further comprising a control circuit arranged adjacent to an area in which the first transistor and the second transistor are arranged, the output of the control circuit being connected to the first gate electrodes of the first transistor and the second transistor.

7. The semiconductor device according to claim 6, wherein the control circuit has an inverter that outputs a control signal, the source of a PMOS transistor of the inverter being provided in common with the first semiconductor layer, and the source of an NMOS transistor of the inverter being provided in common with either the third semiconductor layer or the fourth semiconductor layer.

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