Semiconductor device and power conversion device

Abstract

This semiconductor device includes an IGBT region (105), a diode region (106), and an IGBT / diode boundary region (210) in a plan view. The IGBT / diode boundary region (210) is provided with a low-concentration p-type anode layer (211) which is adjacent to a low-concentration n-type drift layer (214), is formed in the vicinity of the surface opposite to a p-type collector layer (209), is electrically connected to a surface metal electrode (208), is doped at a concentration lower than that of a p-type base layer, is formed deeper than a side gate (204) and a trench (205), and covers the trench (205).

Description

Semiconductor device and power conversion device

[0001] The present invention relates to a semiconductor device and a power conversion device.

[0002] Due to the global trend toward realizing a carbon-neutral society, the power semiconductor market is growing steadily at an average annual growth rate of 9.8%. In recent years, reverse conducting IGBTs (RC-IGBTs), which incorporate an IGBT (Insulated Gate Bipolar Transistor) and a diode on the same chip, have been commercialized, achieving low loss and low cost. Reverse conducting IGBTs can reduce chip size by sharing the termination area between the IGBT and diode. Another advantage is that thermal resistance can be reduced because losses generated in the IGBT or diode area are dissipated throughout the entire chip.

[0003] In order to reduce the thermal resistance (uniform temperature) and reduce the on-state voltage of these reverse conducting IGBTs, various configurations of diode arrangements, such as dot type and stripe type, have been proposed.

[0004] For example, Patent Document 1 discloses an IGBT having a trench gate and an emitter layer formed on the front side of a substrate and a collector layer formed on the back side of the substrate, and a diode having a trench gate and an anode layer formed on the front side of the substrate and a cathode layer formed on the back side of the substrate, wherein the trench gate of the diode portion is insulated from the trench gate of the IGBT portion, the trench gate of the IGBT portion has a plurality of stripes, the trench gate of the diode portion has a plurality of stripes, and the trench gate of the diode portion is arranged with a gap from the trench gate of the IGBT portion in the extension direction of the trench gate of the IGBT portion, the gap being staggered in a plan view. By adopting such a structure, it is possible to reduce the distance between the trench gate of the IGBT and the trench gate of the diode, or by providing a p-well layer between the trench gate of the IGBT and the trench gate of the diode, thereby ensuring sufficient breakdown voltage while reducing gate capacitance.

[0005] Japanese Patent Application Laid-Open No. 2018-41983

[0006] In a reverse conducting IGBT, an IGBT and a diode are combined and arranged on the same chip. When the IGBT region is conductive, electrons flow to the high concentration n-type cathode layer in the diode region (MOS operation), and the forward bias of the high concentration p-type collector layer is limited, resulting in insufficient hole injection and causing the snapback phenomenon.

[0007] Here, we explain the mechanism of snapback in IGBT mode. When the gate opens with a forward bias applied in IGBT mode, electrons are supplied from the emitter. In devices such as FS-IGBTs (Field Stop-IGBTs), these electrons must overcome a potential barrier consisting of the buffer layer and p-type collector diffusion layer. On the other hand, in RC-IGBTs, electrons can pass through the adjacent n-type cathode diffusion layer. This is called MOS mode, and due to this characteristic, the rise time on the low-current side of RC-IGBTs is generally faster than that of FS-IGBTs. A portion of the electron current in MOS mode flows across the buffer layer. The lateral current component causes a voltage drop, with the largest voltage drop occurring at the center of the p-type collector diffusion layer (the location farthest from the n-type diffusion layer). Hole injection begins at this point. As holes are injected and accumulate in the drift layer, the device enters a conductivity modulation state, reducing resistance and voltage. This results in snapback. When the diode is conductive, holes are injected from the P body of the IGBT region into the low-concentration n-type drift layer, which causes a problem of an increase in recovery current.

[0008] Therefore, an object of the present invention is to provide a structure in a reverse conducting IGBT that can suppress the snapback phenomenon when the IGBT is turned on and the hole injection from the IGBT region to the diode region when the diode is conducting.

[0009] In order to achieve the above object, a semiconductor device of the present invention is configured to include, in a plan view, an IGBT region, a diode region, and a boundary region between the IGBT region and the diode region, and the IGBT region includes a first semiconductor layer of a first conductivity type, a second semiconductor layer of a second conductivity type formed in the vicinity of a surface of the first semiconductor layer, a first main electrode electrically connected to the second semiconductor layer, a third semiconductor layer of the second conductivity type adjacent to the first semiconductor layer and formed in the vicinity of a surface on the opposite side to the second semiconductor layer, a fourth semiconductor layer of the first conductivity type selectively provided on an upper part of the third semiconductor layer, a second main electrode electrically connected to the third semiconductor layer and the fourth semiconductor layer, and a gate electrode provided on an inner wall of a trench that penetrates the fourth semiconductor layer and the third semiconductor layer and reaches the first semiconductor layer. the diode region includes a fifth semiconductor layer of a first conductivity type formed near the surface of the first semiconductor layer and electrically connected to the first main electrode, a sixth semiconductor layer of a second conductivity type adjacent to the first semiconductor layer and formed near the surface on the opposite side from the second semiconductor layer, and a seventh semiconductor layer of the second conductivity type selectively provided on top of the third semiconductor layer and electrically connected to the second main electrode; and the boundary region includes an eighth semiconductor layer adjacent to the first semiconductor layer and formed near the surface on the opposite side from the second semiconductor layer, electrically connected to the second main electrode, which is of the second conductivity type and is doped at a lower concentration than the third semiconductor layer, and is formed deeper than the gate electrode and the trench to cover the trench.

[0010] That is, the power conversion device of the present invention is a power conversion device having AC terminals in the same number as the number of phases of AC output, switching legs connected between a pair of DC terminals and each having two parallel circuits of a switching element and a diode of opposite polarity connected in series, in the same number as the number of phases of AC output, and a gate circuit for controlling the switching elements, wherein the switching elements are semiconductor devices as defined in any one of claims 1 to 7. Other means will be described in the description of the embodiment of the invention.

[0011] According to the present invention, in a reverse conducting IGBT, it is possible to suppress the snapback phenomenon that occurs when the IGBT is turned on and the hole injection from the IGBT region to the diode region when the diode is conducting.

[0012] FIG. 1 is a top view of a reverse conducting IGBT chip of a first embodiment. FIG. 2 is an A-A cross-sectional view of a reverse conducting IGBT chip. FIG. 3 is a view showing an A-A cross-section of a reverse conducting IGBT chip of a second embodiment. FIG. 4 is a view showing an A-A cross-section of a reverse conducting IGBT chip of a third embodiment. FIG. 5 is a view showing an A-A cross-section of a reverse conducting IGBT chip of a fourth embodiment. FIG. 6 is a view showing an A-A cross-section of a reverse conducting IGBT chip of a fifth embodiment. FIG. 7 is a view showing an A-A cross-section of a reverse conducting IGBT chip of a sixth embodiment. FIG. 8 is a circuit diagram showing a schematic configuration of a power conversion device.

[0013] Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. FIG. 1 is a top view of a reverse conducting IGBT chip 100 according to a first embodiment. The reverse conducting IGBT chip 100, which is a semiconductor device according to the first embodiment of the present invention, has a plurality of diode regions 106 surrounded by an IGBT region 105. An emitter electrode 104 is formed on one surface of the IGBT region 105. A gate wiring 102 is provided insulated from the emitter electrode 104 of the IGBT region 105 and surrounding the emitter electrode 104, and a gate electrode pad 103 is provided in electrical contact with the gate wiring 102. The gate wiring 102 is in electrical contact with a plurality of side gates 204, which will be described later. That is, the reverse conducting IGBT chip 100 includes an IGBT region 105, a diode region 106, and an IGBT / diode boundary region 210 which is the boundary region between the IGBT region 105 and the diode region 106 when viewed in plan.

[0014] 2 is an A-A cross-sectional view of the reverse conducting IGBT chip 100. In the reverse conducting IGBT chip 100, trenches 205 are repeatedly formed at predetermined intervals in a direction perpendicular to this cross section. An insulator is formed on the sidewall of the trench 205, and a conductive side gate 204 is formed along the sidewall. A conductive field plate polysilicon 206 is formed in the center of the trench 205, separated by the side gate 204 and the insulator.

[0015] <<IGBT Region>> The IGBT region 105 of the reverse conducting IGBT chip 100 has a back surface metal electrode (first main electrode) 217 ​​which is a collector electrode, a p-type collector layer (second semiconductor layer) 209, an n-type buffer layer 215, a low-concentration n-type drift layer (first semiconductor layer) 214, a p-type base layer (third semiconductor layer) 203, a high-concentration n-type emitter layer (fourth semiconductor layer) 201, a high-concentration p-type contact layer 202, a trench 205, a side gate 204, insulating films 322 and 323 in the trench 205, a field plate polysilicon 206 provided between the gate electrodes in the trench 205, an interlayer insulating film 231, and an emitter contact (second main electrode) 207.

[0016] The IGBT region 105 includes a low-concentration n-type drift layer 214 and an n-type buffer layer 215, which are first semiconductor layers, a p-type collector layer (second semiconductor layer) 209 formed near the surface on the back side of the first semiconductor layer, and a back surface metal electrode (first main electrode) 217 ​​electrically connected to the second semiconductor layer. The IGBT region 105 further includes a p-type base layer (third semiconductor layer) 203 adjacent to the low-concentration n-type drift layer 214 and formed near the surface on the side opposite to the p-type collector layer (second semiconductor layer) 209, a high-concentration n-type emitter layer (fourth semiconductor layer) 201 selectively provided on the top of the p-type base layer 203, a front surface metal electrode (second main electrode) 208 electrically connected to the third and fourth semiconductor layers, and a side gate (gate electrode) 204 provided on the inner wall of a trench 205 that penetrates the fourth and third semiconductor layers and reaches the first semiconductor layer.

[0017] Note that layers labeled n-type and p-type refer to n-type layers with electrons as majority carriers and p-type layers with holes as majority carriers, respectively, and high concentration and low concentration refer to the layer's relatively high or relatively low concentration of majority carriers (impurity concentration). Note that the first conductivity type and second conductivity type described in the claims correspond to n-type and p-type. If the first conductivity type is n-type, the second conductivity type is p-type, and if the first conductivity type is n-type, the second conductivity type corresponds to p-type.

[0018] The IGBT region 105 of the reverse conducting IGBT chip 100 is an n-channel IGBT. An n-type buffer layer 215, a p-type collector layer 209, and a back surface metal electrode 217 are stacked near the surface on the back side of a low-concentration n-type drift layer 214. The back surface metal electrode 217 is electrically connected to the p-type collector layer 209.

[0019] A p-type base layer 203 adjacent to the low-concentration n-type drift layer 214 is formed near the surface on the front side of the low-concentration n-type drift layer 214. The high-concentration n-type emitter layer 201 is selectively provided on top of the p-type base layer 203. Therefore, the high-concentration n-type emitter layer 201 and the p-type base layer 203 are alternately arranged in a direction along the side surface of the trench 205. The emitter contact 207 is electrically connected to the p-type base layer 203 and also electrically connected to the high-concentration n-type emitter layer 201 via the high-concentration p-type contact layer 202.

[0020] The insulating film 232 on the side surface of the trench 205 contacts the high-concentration n-type emitter layer 201 and the p-type base layer 203. The bottom surface of the trench 205 is deeper than the bottom surfaces of the high-concentration n-type emitter layer 201 and the p-type base layer 203 and reaches the low-concentration n-type drift layer 214. Inside the trench 205, an insulating film 232, a side gate 204 serving as a gate electrode, an interlayer insulating film 231, and a field plate polysilicon 206 are provided. The insulating film 232 is provided on the side surface and bottom surface of the trench 205. The side gate 204 serving as a gate electrode is provided on the insulating film 232 along the side surface of the trench 205. The insulating film 232 is provided in the center of the bottom surface of the trench 205. The field plate polysilicon 206 is provided on the insulating film 232. The field plate polysilicon 206 is provided a predetermined distance away from the side gate 204 serving as a gate electrode. The field plate polysilicon 206 is electrically connected to a surface metal electrode 208 which is an emitter electrode.

[0021] Field plate polysilicon 206 is also formed to be wide inside wide trench 205. In contrast, contact hole 20 formed on field plate polysilicon 206 is formed in the center of field plate polysilicon 206, so internal resistance occurs within field plate polysilicon 206.

[0022] The emitter electrode of the reverse conducting IGBT chip 100 is disposed along the sidewall of the trench 205 on the surfaces of the high-concentration n-type emitter layer 201, the p-type base layer 203, and the low-concentration n-type drift layer 214, with an insulating film 232 interposed between them. In this embodiment, a side gate 204, which is a gate electrode of the reverse conducting IGBT chip 100, is provided on the sidewall of one p-type base layer 203 in the IGBT region 105, with the insulating film 232 interposed between them. Two side gates 204, i.e., a pair of gate electrodes, are provided for one p-type base layer 203, and are arranged in a stripe pattern. Here, the gate structure may be a trench gate or a planar structure.

[0023] On the opposite surface of the surface structure of the IGBT region 105 , a p-type collector layer 209 is formed and connected to a backside metal electrode 217 .

[0024] Furthermore, field plate polysilicon 206 is provided between the gate electrodes inside the trench 205. The field plate polysilicon 206 is electrically connected to a surface metal electrode 208 via a contact. Similarly, the heavily doped n-type emitter layer 201, the p-type base layer 203, and the heavily doped p-type contact layer 202 are electrically connected to the surface metal electrode 208 by an emitter contact 207 etched deeper than the heavily doped n-type emitter layer 201. By forming the emitter contact 207 deeper than the heavily doped n-type emitter layer 201, it is possible to suppress the operation of a thyristor formed by the heavily doped n-type emitter layer 201, the p-type base layer 203, the lightly doped n-type drift layer 214, and the p-type collector layer 209, and to suppress breakdown due to current concentration. The field plate polysilicon 206 also contributes to the flat structure and stabilization of the breakdown voltage of the IGBT region 105.

[0025] <<Diode Region>> Trenches 205 are formed at predetermined intervals near the surface on the front side of the low-concentration n-type drift layer 214 in the diode region 106. A low-concentration p-type anode layer 211 and a high-concentration p-type anode layer 212 are stacked between the trenches 205. A surface metal electrode 208 functions as an anode electrode in the diode region 106. The high-concentration p-type anode layer 212 is connected to the surface metal electrode 208 by an anode contact 213.

[0026] An n-type buffer layer 215, a high-concentration n-type cathode layer 216, and a backside metal electrode 217 are stacked near the surface on the back side of the low-concentration n-type drift layer 214 in the diode region 106. The backside metal electrode 217 is electrically connected to the high-concentration n-type cathode layer 216 and functions as a cathode electrode.

[0027] The diode region 106 has a side gate 204 inside the trench 205, similar to the IGBT region 105, and is electrically connected to a surface metal electrode 208. The side gates 204 in the diode region 106 are provided on the side walls of the trench 205 adjacent to the low-concentration p-type anode layer 211 and the high-concentration p-type anode layer 212, and two side gates 204 are arranged in a stripe shape for one p-type base layer 203.

[0028] This diode region 106 is formed near the back surface of the first semiconductor layer, that is, the low-concentration n-type drift layer 214 and the n-type buffer layer 215, and includes a high-concentration n-type cathode layer (fifth semiconductor layer) 216 electrically connected to a back surface metal electrode (first main electrode) 217, a low-concentration p-type anode layer (sixth semiconductor layer) 211 adjacent to the first semiconductor layer and formed near the surface on the opposite side from the p-type collector layer (second semiconductor layer) 209, and a high-concentration p-type anode layer (seventh semiconductor layer) 212 selectively provided on the top of the p-type base layer (third semiconductor layer) 203 and electrically connected to the front surface metal electrode (the second main electrode) 208.

[0029] <<Boundary Region>> An IGBT / diode boundary region 210 is disposed at the boundary between the IGBT region 105 and the diode region 106. Trenches 205 are formed at predetermined intervals near the front surface of the low-concentration n-type drift layer 214 in the IGBT / diode boundary region 210. A low-concentration p-type anode layer 211 is formed at a lower concentration than the p-type base layer 203 in the IGBT region 105 and deeper than the p-type base layer 203 so as to completely cover the trenches 205. The surface of the IGBT / diode boundary region 210 opposite the low-concentration p-type anode layer 211 is the back surface of the low-concentration n-type drift layer 214, and an n-type buffer layer 215, a high-concentration n-type cathode layer 216, and a back surface metal electrode 217 are stacked on this surface.

[0030] In the IGBT / diode boundary region 210, similar to the IGBT region 105, a side gate 204 is provided inside the trench 205 and is electrically connected to the surface metal electrode 208. The side gates 204 in the diode region 106 are provided on the side walls of the trench 205 adjacent to the low-concentration p-type anode layer 211 and the high-concentration p-type anode layer 212, and two side gates are arranged in a stripe shape for one p-type base layer 203.

[0031] In the IGBT / diode boundary region 210, a low-concentration p-type anode layer (eighth semiconductor layer) 211 is provided, which is adjacent to the low-concentration n-type drift layer 214 and n-type buffer layer 215, which are the first semiconductor layers, and is formed near the surface on the opposite side from the p-type collector layer (second semiconductor layer) 209, is electrically connected to the surface metal electrode (second main electrode) 208, is doped at a lower concentration than the p-type base layer (third semiconductor layer) 203, and is formed deeper than the gate electrode and trench 205 to cover the trench 205.

[0032] When the diode is ON (conducting), holes are injected from the p-type base layer 203 in the IGBT region 105 into the low-concentration n-type drift layer 214, which may increase the recovery current. With this structure, the recovery current in the diode region 106 can be alleviated by the IGBT / diode boundary region 210, making it possible to prevent element destruction due to current concentration.

[0033] The low-concentration p-type anode layer 211 in the IGBT / diode boundary region 210 has a lower concentration than the p-type base layer 203 in the IGBT region 105, and the hole current from the IGBT / diode boundary region 210 is smaller than that from the IGBT region 105. This increases the current concentration suppression effect.

[0034] Furthermore, a low-concentration p-type anode layer 211 is formed to cover the trench 205. This suppresses avalanche current due to electric field concentration at the corners of the trench 205, and hole and electron current due to electric field concentration, thereby further suppressing current concentration.

[0035] 3 is a diagram showing an A-A cross section of the reverse conducting IGBT chip 100 of the second embodiment. The reverse conducting IGBT chip 100 of the second embodiment differs from the reverse conducting IGBT chip 100 of the first embodiment in that a low-concentration p-type anode layer 211 is formed to cover the trench 205 in both the diode region 106 and the IGBT / diode boundary region 210. The low-concentration p-type anode layer 211 of the second embodiment has a lower concentration and a greater depth than the p-type base layer 203 of the IGBT region 105. A high-concentration n-type cathode layer 216 is formed on the surface opposite the low-concentration p-type anode layer 211 in the IGBT / diode boundary region 210 and the anode layer of the diode region 106, and is connected to a back metal electrode 217.

[0036] In other words, the low-concentration p-type anode layer (sixth semiconductor layer) 211 in the diode region 106 and the low-concentration p-type anode layer (eighth semiconductor layer) 211 in the IGBT / diode boundary region 210 are integrated, doped at a lower concentration than the p-type base layer (third semiconductor layer) 203 in the IGBT region 105, and have a structure deeper than the p-type base layer (third semiconductor layer) 203.

[0037] With this structure, the low-concentration p-type anode layer 211 in the diode region 106 is formed so as to cover the trench 205, and further, the corner portions of the trench 205 in the diode region 106 are also formed so as to cover with the low-concentration p-type anode layer 211. This suppresses the avalanche current due to electric field concentration at the corner portions of the trench 205, and by suppressing the hole and electron current due to the electric field concentration, it is possible to further suppress current concentration. In addition, since the electric field concentration at the corner portions of the trench 205 is suppressed, the breakdown voltage is improved.

[0038] 4 is a diagram showing an A-A cross section of the reverse conducting IGBT chip 100 of the third embodiment. The reverse conducting IGBT chip 100 of the third embodiment differs from the reverse conducting IGBT chips 100 of the first and second embodiments in that a p-type collector layer 209 is formed on the surface of the IGBT / diode boundary region 210 opposite to the surface facing the low-concentration p-type anode layer 211, and is connected to a back surface metal electrode 217.

[0039] A p-type collector layer (second semiconductor layer) 209 of the IGBT region 105 extends near the surface of the back surface of the low-concentration n-type drift layer (first semiconductor layer) 214 that faces the low-concentration p-type anode layer (eighth semiconductor layer) 211 in the IGBT / diode boundary region 210, and is electrically connected to a back surface metal electrode (first main electrode) 217.

[0040] A p-type collector layer (second semiconductor layer) 209 of the IGBT region 105 extends near the surface of the low-concentration n-type drift layer (first semiconductor layer) 214 that faces the low-concentration p-type anode layer (eighth semiconductor layer) 211 in the IGBT / diode boundary region 210, and is electrically connected to a back surface metal electrode (first main electrode) 217.

[0041] This structure suppresses MOS operation, in which electrons flow to the high-concentration n-type cathode layer 216 in the diode region 106, when the IGBT is on (conducting), promoting forward bias of the p-type collector layer 209 when the IGBT is on and suppressing snapback. Furthermore, when the diode is on (conducting), hole injection from the low-concentration p-type anode layer 211 in the IGBT / diode boundary region 210 and excessive hole injection from the p-type base layer 203 in the IGBT region 105 are suppressed, reducing the recovery current.

[0042] 5 is a diagram showing an A-A cross section of the reverse conducting IGBT chip 100 of the fourth embodiment. The reverse conducting IGBT chip 100 of the fourth embodiment differs from the first to third embodiments in that an n-type buffer layer 215, which has a lower concentration than the high-concentration n-type cathode layer 216, is connected to a back surface metal electrode 217 on the surface opposite to the low-concentration p-type anode layer 211 in the IGBT / diode boundary region 210. That is, in the IGBT / diode boundary region 210 of this embodiment, the n-type buffer layer 215 is connected to the back surface metal electrode 217.

[0043] The surface of the low-concentration n-type drift layer (first semiconductor layer) 214 facing the low-concentration p-type anode layer (sixth semiconductor layer) 211 in the IGBT / diode boundary region 210 is doped to a lower concentration than the high-concentration n-type cathode layer (fifth semiconductor layer) 216 in the diode region 106.

[0044] This structure suppresses MOS operation, in which electrons flow to the high-concentration n-type cathode layer 216 of the diode, when the IGBT is on (conducting), promoting forward bias of the p-type collector layer 209 when the IGBT is on and suppressing snapback. Furthermore, when the diode is on (conducting), hole injection from the low-concentration p-type anode layer 211 in the IGBT / diode boundary region 210 and excessive hole injection from the p-type base layer 203 in the IGBT region 105 are suppressed, reducing the recovery current.

[0045] Furthermore, compared to the second embodiment, excessive hole current from the p-type collector layer 209 through the IGBT / diode boundary region 210 can be reduced when the IGBT is turned off, improving the interruption capability.

[0046] 6 is a diagram showing an A-A cross section of a reverse conducting IGBT chip 100 of the fifth embodiment. The reverse conducting IGBT chip 100 of the fifth embodiment differs from the first to fourth embodiments in that a p-type base layer 203 in the IGBT region 105 and a low-concentration p-type anode layer 211 that has a lower concentration and is deeper than the p-type base layer 203 are disposed apart from each other in an IGBT / diode boundary region 210. In the IGBT / diode boundary region 210, a high-concentration n-type cathode layer 216 is formed on the surface opposite to the low-concentration p-type anode layer 211 and is connected to a back surface metal electrode 217.

[0047] The low-concentration p-type anode layer (eighth semiconductor layer) 211 in the IGBT / diode boundary region 210 and the p-type base layer (third semiconductor layer) 203 in the IGBT region 105 are disposed apart from each other with a low-concentration n-type drift layer (first semiconductor layer) 214 sandwiched therebetween. A high-concentration n-type cathode layer (fifth semiconductor layer) 216 in the diode region 106 extends near the surface of the low-concentration p-type anode layer (eighth semiconductor layer) 211 in the IGBT / diode boundary region 210 and the low-concentration n-type drift layer (first semiconductor layer) 214 facing the IGBT region 105, and is electrically connected to a back surface metal electrode (first main electrode) 217.

[0048] This structure suppresses hole current injected from the p-type base layer 203 in the IGBT region 105 through the low-concentration p-type anode layer 211 in the IGBT / diode boundary region 210, thereby reducing the recovery current.

[0049] FIG. 7 is a diagram showing the A-A cross section of the reverse conducting IGBT chip 100 of the sixth embodiment. The reverse conducting IGBT chip 100 of the sixth embodiment differs from the first to fifth embodiments in that the anode contacts 213 are formed deep relative to the upper silicon surface in both the diode region 106 and the IGBT / diode boundary region 210, similar to the emitter contact 207 in the IGBT region 105. This structure reduces the number of steps for forming the high-concentration p-type anode layer 212 by performing self-aligned ion implantation after forming the contact hole in the diode region 106, enabling low-cost manufacturing. When self-aligned ion implantation is performed, the high-concentration p-type anode layer 212 is also formed on the sidewall of the contact hole.

[0050] In the IGBT / diode boundary region 210 , a high-concentration n-type surface layer 601 with a higher concentration than the anode layer is disposed to suppress hole injection from the sidewall of the contact hole in the IGBT / diode boundary region 210 .

[0051] This structure suppresses hole current in the IGBT / diode boundary region 210, making it possible to prevent element breakdown due to current concentration.

[0052] Fig. 8 is a circuit diagram showing a schematic configuration of a power conversion device 500. A sixth embodiment in which a semiconductor device of the present invention is applied to the power conversion device 500 will be described with reference to Fig. 8. Fig. 8 is a circuit diagram showing the configuration of the power conversion device 500 that employs the semiconductor device according to the first embodiment. Fig. 8 shows an example of the circuit configuration of the power conversion device 500 of this embodiment and the relationship of connections between a DC power supply and a three-phase AC motor (AC load).

[0053] In a power conversion device 500 of this embodiment, the semiconductor device of the first embodiment is used as power switching elements 501 to 506. The power switching elements 501 to 506 are the reverse conducting IGBT chips 100 of the first embodiment, which are elements in which an IGBT and a diode are combined.

[0054] As shown in Fig. 8 , the power conversion device 500 of this embodiment includes a pair of DC terminals, namely, P-terminal 531 and N-terminal 532, and AC terminals, namely, U-terminal 533, V-terminal 534, and W-terminal 535, the number of which is the same as the number of phases of the AC output. The power conversion device 500 also includes a switching leg consisting of a pair of power switching elements 501 and 502 connected in series, with the U-terminal 533 connected to their series connection point as its output. The power conversion device 500 also includes a switching leg consisting of a pair of power switching elements 503 and 504 connected in series with the same configuration as the P-terminal 531, with the V-terminal 534 connected to their series connection point as its output. The power conversion device 500 also includes a switching leg consisting of a pair of power switching elements 505 and 506 connected in series with the same configuration as the P-terminal 531, with the W-terminal 535 connected to their series connection point as its output.

[0055] The three-phase switching legs consisting of power switching elements 501 to 506 are connected between DC terminals P terminal 531 and N terminal 532, and DC power is supplied from a DC power supply (not shown). The three-phase AC terminals of power conversion device 500, namely U terminal 533, V terminal 534, and W terminal 535, are connected to a three-phase AC motor (not shown) as a three-phase AC power supply.

[0056] Gate circuits 511 to 516 are connected to the input terminals of the gates of the power switching elements 501 to 506, each of which is made up of a reverse conducting IGBT, and the power switching elements 501 to 506 are controlled by the gate circuits 511 to 516, respectively. The gate circuits 511 to 516 are controlled in an integrated manner by an integrated control circuit (not shown).

[0057] The gate circuits 511 to 516 comprehensively and appropriately control the power switching elements 501 to 506, converting the DC power of the DC power supply Vcc into three-phase AC power, which is output from the U terminal 533, the V terminal 534, and the W terminal 535.

[0058] By applying the semiconductor devices according to the first to sixth embodiments to the power conversion device 500, it is possible to reduce costs by sharing the termination regions of the IGBT and diode. Furthermore, heat loss generated in the IGBT region 105 or the diode region 106 is dissipated throughout the entire chip, thereby reducing thermal resistance.

[0059] [1] The semiconductor device is configured to include, in a plan view, an IGBT region (105), a diode region (106), and a boundary region (IGBT / diode boundary region 210) between the IGBT region (105) and the diode region (106), wherein the IGBT region (105) includes: a first semiconductor layer of a first conductivity type (n) (low-concentration n-type drift layer 214, n-type buffer layer 215); a second semiconductor layer of a second conductivity type (P) (p-type collector layer 209) formed near the surface of the first semiconductor layer; a first main electrode (backside metal electrode 217) electrically connected to the second semiconductor layer; and a third semiconductor layer of a second conductivity type (p) (p-type base layer 203) adjacent to the first semiconductor layer and formed near the surface on the opposite side from the second semiconductor layer. a fourth semiconductor layer (high-concentration n-type emitter layer 201) of a first conductivity type (n) selectively provided on an upper portion of the third semiconductor layer, a second main electrode (front surface metal electrode 208) electrically connected to the third semiconductor layer and the fourth semiconductor layer, and a gate electrode (side gate 204) provided on an inner wall of a trench that penetrates the fourth semiconductor layer and the third semiconductor layer and reaches the first semiconductor layer, and the diode region (106) is provided with: a fifth semiconductor layer (high-concentration n-type cathode layer 216) of a first conductivity type (n) formed near the surface of the first semiconductor layer and electrically connected to the first main electrode (back surface metal electrode 217), and a sixth semiconductor layer (low-concentration p-type anode layer 211) of a second conductivity type (p) adjacent to the first semiconductor layer and formed near the surface on the opposite side from the second semiconductor layer, a seventh semiconductor layer (high-concentration p-type anode layer 212) of the second conductivity type (p) selectively provided on an upper portion of the third semiconductor layer and electrically connected to the second main electrode (surface metal electrode 208); and an eighth semiconductor layer (low-concentration p-type anode layer 211) of the second conductivity type (p) that is formed adjacent to the first semiconductor layer, near the surface on the opposite side from the second semiconductor layer, electrically connected to the second main electrode (anode contact 213), that is doped at a lower concentration than the third semiconductor layer (p-type base layer 203), and that is formed deeper than the gate electrode and the trench (205) and covers the trench (205).

[0060] When the diode is ON (conducting), holes are injected from the third semiconductor layer (p-type base layer 203) in the IGBT region (105) into the first semiconductor layer (low-concentration n-type drift layer 214), which may increase the recovery current. This structure makes it possible to mitigate the recovery current in the diode region (106) by the boundary region (IGBT / diode boundary region 210), making it possible to suppress element destruction due to current concentration.

[0061] The sixth semiconductor layer (low-concentration p-type anode layer 211) in the boundary region (IGBT / diode boundary region 210) has a lower concentration than the third semiconductor layer (p-type base layer 203) in the IGBT region (105), and the hole current from the boundary region (IGBT / diode boundary region 210) is smaller than that from the IGBT region (105). Therefore, the current concentration suppression effect can be enhanced.

[0062] Furthermore, a sixth semiconductor layer (low-concentration p-type anode layer 211) is formed to cover the trench 205. This suppresses avalanche current due to electric field concentration at the corners of the trench 205, and further suppresses hole and electron current due to electric field concentration, thereby making it possible to further suppress current concentration.

[0063] [2] (Second embodiment) The semiconductor device according to claim 1, wherein the sixth semiconductor layer of the diode region (106) and the eighth semiconductor layer (low-concentration p-type anode layer 211) of the boundary region are integrated, doped at a lower concentration than the third semiconductor layer (p-type base layer 203) of the IGBT region, and have a structure deeper than the third semiconductor layer (p-type base layer 203).

[0064] With this structure, the sixth semiconductor layer (low-concentration p-type anode layer 211) in the diode region (106) is formed so as to cover the trench (205), and further, the corners of the trench (205) in the diode region (106) are also formed so as to cover with the sixth semiconductor layer (low-concentration p-type anode layer 211). This suppresses avalanche current due to electric field concentration at the corners of the trench (205), and by suppressing hole and electron current due to electric field concentration, current concentration can be further suppressed. In addition, since electric field concentration at the corners of the trench (205) is suppressed, the breakdown voltage is improved.

[0065] [3] (Third embodiment) The semiconductor device according to claim 1, wherein the second semiconductor layer (p-type collector layer 209) of the IGBT region (105) extends near the surface of the first semiconductor layer facing the eighth semiconductor layer (low-concentration p-type anode layer 211) in the boundary region (IGBT / diode boundary region 210), and is electrically connected to the first main electrode (back surface metal electrode 217).

[0066] With this structure, when the IGBT is ON (conducting), MOS operation in which electrons flow to the fifth semiconductor layer (high-concentration n-type cathode layer 216) in the diode region (106) is suppressed, forward bias of the second semiconductor layer (p-type collector layer 209) is promoted when the IGBT is ON, and snapback is suppressed. Furthermore, when the diode is ON (conducting), hole injection from the eighth semiconductor layer (low-concentration p-type anode layer 211) in the boundary region (IGBT / diode boundary region 210) and excessive hole injection from the third semiconductor layer (p-type base layer 203) in the IGBT region (105) are suppressed, reducing the recovery current.

[0067] [4] (Details of the first embodiment) The semiconductor device according to claim 1, wherein the fifth semiconductor layer (high-concentration n-type cathode layer 216) of the diode region (106) extends to a surface of the first semiconductor layer facing the eighth semiconductor layer (low-concentration p-type anode layer 211) of the boundary region (IGBT / diode boundary region 210), and is electrically connected to the first main electrode (back surface metal electrode 217).

[0068] [5] (Details of the fourth embodiment) The semiconductor device according to claim 1, wherein a surface of the first semiconductor layer facing the sixth semiconductor layer (low-concentration p-type anode layer 211) in the boundary region (IGBT / diode boundary region 210) is doped at a lower concentration than the fifth semiconductor layer (high-concentration n-type cathode layer 216) in the diode region (106).

[0069] With this structure, when the IGBT is ON (conducting), MOS operation in which electrons flow to the fifth semiconductor layer (high-concentration n-type cathode layer 216) of the diode is suppressed, forward bias of the second semiconductor layer (p-type collector layer 209) is promoted when the IGBT is ON, and snapback is suppressed. Furthermore, when the diode is ON (conducting), hole injection from the eighth semiconductor layer (low-concentration p-type anode layer 211) in the boundary region (IGBT / diode boundary region 210) and excessive hole injection from the third semiconductor layer (p-type base layer 203) in the IGBT region (105) are suppressed, reducing the recovery current.

[0070] [6] (Fifth Embodiment) The semiconductor device according to claim 1, wherein the eighth semiconductor layer (low-concentration p-type anode layer 211) in the boundary region (IGBT / diode boundary region 210) and the third semiconductor layer in the IGBT region (105) are arranged apart with the first semiconductor layer sandwiched therebetween, and the fifth semiconductor layer (high-concentration n-type cathode layer 216) in the diode region (106) extends near a surface of the first semiconductor layer that faces the sixth semiconductor layer (low-concentration p-type anode layer 211) in the boundary region (IGBT / diode boundary region 210) and is electrically connected to the first main electrode (back surface metal electrode 217).

[0071] This structure suppresses hole current injected from the third semiconductor layer (p-type base layer 203) in the IGBT region (105) through the eighth semiconductor layer (low-concentration p-type anode layer 211) in the boundary region (IGBT / diode boundary region 210), thereby reducing the recovery current.

[0072] [7] The semiconductor device according to claim 1, wherein: the third semiconductor layer (p-type base layer 203) in the IGBT region (105) is connected to the second main electrode by a trench structure; the sixth semiconductor layer (low-concentration p-type anode layer 211) in the diode region (106) is connected to the second main electrode (surface metal electrode 208) by a trench structure; the eighth semiconductor layer (low-concentration p-type anode layer 211) in the boundary region is connected to the second main electrode (surface metal electrode 208) by a trench structure; and the trench structure of the boundary region (IGBT / diode boundary region 210) has a first conductivity type (n) having a higher concentration than the anode layer in the boundary region in contact with a sidewall of the trench (205).

[0073] This structure suppresses hole current in the boundary region (IGBT / diode boundary region 210), making it possible to prevent element breakdown due to current concentration.

[0074] [8] A power conversion device (500) having: AC terminals in the same number as the number of phases of AC output; switching legs connected between a pair of DC terminals, each of which has two parallel circuits of a switching element and a diode of opposite polarity connected in series; and a gate circuit for controlling the switching elements, wherein the switching elements are semiconductor devices according to any one of claims 1 to 7.

[0075] By applying the semiconductor device according to claims 1 to 7 to the power conversion device (500), the termination region of the IGBT and the diode can be shared, thereby reducing costs. Furthermore, the loss generated in the IGBT region (105) or the diode region (106) is dissipated throughout the entire chip, thereby reducing thermal resistance.

[0076] (Modifications) The present invention is not limited to the above-described embodiments and includes various modifications. For example, the above-described embodiments have been described in detail to clearly explain the present invention, and are not necessarily limited to those including all of the described configurations. It is possible to replace part of the configuration of one embodiment with the configuration of another embodiment, and it is also possible to add the configuration of another embodiment to the configuration of one embodiment. Furthermore, it is also possible to add, delete, or replace part of the configuration of each embodiment with other configurations.

[0077] The above-described configurations, functions, processing units, processing means, etc. may be realized in part or in whole by hardware such as integrated circuits. In each embodiment, the control lines and information lines shown are those considered necessary for explanation, and not all control lines and information lines in the product are necessarily shown. In reality, it can be considered that almost all configurations are interconnected.

[0078] Modifications of the present invention include, for example, the following (a) and (b). (a) The gate structure is not limited to a side gate structure, and may be a trench gate or a planar structure. (b) The reverse conducting IGBT is not limited to an n-channel IGBT, and may be a p-channel IGBT. In this case, it can be realized by switching the n-type and p-type of each semiconductor phase.

[0079] 100 Reverse conducting IGBT chip 201 Highly doped n-type emitter layer (fourth semiconductor layer) 202 Highly doped p-type contact layer 203 P-type base layer (third semiconductor layer) 204 Side gate (gate electrode) 214 Lowly doped n-type drift layer (first semiconductor layer) 215 N-type buffer layer (first semiconductor layer) 209 P-type collector layer (second semiconductor layer) 217 ​​Back metal electrode (first main electrode) 206 Field plate polysilicon 208 Front metal electrode (second main electrode) 207 Emitter contact 211 Lowly doped p-type anode layer (sixth semiconductor layer, eighth semiconductor layer) 212 Highly doped p-type anode layer (seventh semiconductor layer) 213 Anode contact (second main electrode) 216 Highly doped n-type cathode layer (fifth semiconductor layer) 105 IGBT region 106 Diode region 210 IGBT / diode boundary region (boundary region) 601 Surface layer 500 Power conversion device 501 to 506 Power switching elements 531 P terminal 532 N terminal 533 U terminal 534 V terminal 535 W terminal 511 to 516 Gate circuit

Claims

1. A semiconductor device is configured to include, in a plan view, an IGBT region, a diode region, and a boundary region between the IGBT region and the diode region, wherein the IGBT region is provided with: a first semiconductor layer of a first conductivity type; a second semiconductor layer of a second conductivity type formed near the surface of the first semiconductor layer; a first main electrode electrically connected to the second semiconductor layer; a third semiconductor layer of a second conductivity type adjacent to the first semiconductor layer and formed near the surface on the opposite side from the second semiconductor layer; a fourth semiconductor layer of a first conductivity type selectively provided on top of the third semiconductor layer; a second main electrode electrically connected to the third semiconductor layer and the fourth semiconductor layer; and a gate electrode provided on an inner wall of a trench that penetrates the fourth semiconductor layer and the third semiconductor layer and reaches the first semiconductor layer, and wherein the diode region is provided with: a fifth semiconductor layer of a first conductivity type formed near the surface of the first semiconductor layer and electrically connected to the first main electrode, a sixth semiconductor layer of a second conductivity type adjacent to the first semiconductor layer and formed near the surface on the opposite side from the second semiconductor layer; and a seventh semiconductor layer of the second conductivity type selectively provided on top of the third semiconductor layer and electrically connected to the second main electrode, wherein the boundary region is provided with an eighth semiconductor layer adjacent to the first semiconductor layer, formed near the surface on the opposite side from the second semiconductor layer, electrically connected to the second main electrode, the eighth semiconductor layer being of the second conductivity type and doped at a lower concentration than the third semiconductor layer, and formed deeper than the gate electrode and the trench to cover the trench.

2. The semiconductor device according to claim 1, wherein the sixth semiconductor layer in the diode region and the eighth semiconductor layer in the boundary region are integrated, doped at a lower concentration than the third semiconductor layer in the IGBT region, and have a deeper structure than the third semiconductor layer.

3. The semiconductor device according to claim 1, wherein the second semiconductor layer in the IGBT region extends near the surface of the first semiconductor layer facing the eighth semiconductor layer in the boundary region and is electrically connected to the first main electrode.

4. The semiconductor device according to claim 1, wherein the fifth semiconductor layer in the diode region extends to a surface of the first semiconductor layer facing the eighth semiconductor layer in the boundary region and is electrically connected to the first main electrode.

5. The semiconductor device according to claim 1, wherein the surface of the first semiconductor layer facing the sixth semiconductor layer in the boundary region is doped to a lower concentration than the fifth semiconductor layer in the diode region.

6. The semiconductor device according to claim 1, wherein the eighth semiconductor layer in the boundary region and the third semiconductor layer in the IGBT region are arranged apart with the first semiconductor layer sandwiched therebetween, and the fifth semiconductor layer in the diode region extends near the surface of the first semiconductor layer facing the sixth semiconductor layer in the boundary region and is electrically connected to the first main electrode.

7. The semiconductor device according to claim 1, wherein the third semiconductor layer in the IGBT region is connected to the second main electrode by a trench structure, the sixth semiconductor layer in the diode region is connected to the second main electrode by a trench structure, the eighth semiconductor layer in the boundary region is connected to the second main electrode by a trench structure, and the trench structure in the boundary region has a first conductivity type that is more highly doped than the anode layer in the boundary region in contact with a trench sidewall.

8. A power conversion device having: AC terminals in the same number as the number of phases of AC output; switching legs connected between a pair of DC terminals, each of which has two parallel circuits of a switching element and a diode of opposite polarity connected in series, in the same number as the number of phases of AC output; and a gate circuit for controlling said switching elements, wherein said switching elements are semiconductor devices as defined in any one of claims 1 to 7.

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