Photodetector and electronic apparatus

Abstract

A photodetector includes a first substrate, a second substrate, and a wiring layer provided in the first or second substrate. The first substrate includes a photoelectric conversion element and one or more components of a readout circuit. The photoelectric conversion element is configured to photoelectrically convert light to an electric charge and the readout circuit is configured to output a signal based on the electric charge converted by the photoelectric conversion element. The second substrate includes one or more components of a signal processing circuit. The signal processing circuit is configured to process the signal and the second substrate is stacked on the first substrate. The signal processing circuit includes one or more portions of a first transistor and a capacitor provided in the wiring layer.

Description

PHOTODETECTOR AND ELECTRONIC APPARATUSCROSS REFERENCE TO RELATED APPLICATIONS

[0001] This application claims the benefit of Japanese Priority Patent Application JP2024-031606 filed March 1, 2024, the entire contents of which are incorporated herein by reference.

[0002] The present disclosure relates to a photodetector and an electronic apparatus.

[0003] A device has been proposed that has a structure in which a first semiconductor substrate and a second semiconductor substrate are stacked. The first semiconductor substrate includes a pixel section formed therein, and the second semiconductor substrate includes column circuits and column memories formed therein (PTL 1).

[0004] [PTL 1] Japanese Unexamined Patent Application Publication No. 2022-171700Summary

[0005] It is desired for, a device that detects light, to enable a reduction in a circuit area.

[0006] It is desirable to provide a photodetector that enables a reduction in a circuit area.

[0007] According to an embodiment of the present disclosure, there is provided a photodetector including a first substrate including a photoelectric conversion element and one or more components of a readout circuit. The photoelectric conversion element is configured to photoelectrically convert light to an electric charge and the readout circuit is configured to output a signal based on the electric charge converted by the photoelectric conversion element. The photodetector also includes a second substrate including one or more components of a signal processing circuit. The signal processing circuit is configured to process the signal and the second substrate is stacked on the first substrate. The photodetector also includes a wiring layer provided in one of the first substrate and the second substrate. The signal processing circuit includes one or more portions of a first transistor and a capacitor provided in the wiring layer. According to an aspect of the present disclosure, the signal processing circuit includes the first transistor provided in the wiring layer. According to an aspect of the present disclosure, the first transistor comprises a thin-film transistor. According to an aspect of the present disclosure, the first transistor includes a channel region including an oxide semiconductor. According to an aspect of the present disclosure, the readout circuit is further configured to output the signal to a signal line, the first transistor is electrically coupled to the signal line, and the first transistor is configured to supply a current to the signal line. According to an aspect of the present disclosure, the signal processing circuit includes an analog-to-digital (“AD”) conversion circuit configured to convert the signal into a digital signal. According to an aspect of the present disclosure, the AD conversion circuit includes a comparison circuit including the first transistor, and the comparison circuit is configured to compare the signal inputted to the first transistor with a reference signal. According to an aspect of the present disclosure, the AD conversion circuit includes a comparison circuit including a differential pair and the first transistor, and the first transistor is configured to supply a current to the differential pair. According to an aspect of the present disclosure, the first transistor is electrically coupled between a signal line and a potential line, the signal line configured to transmit the signal. According to an aspect of the present disclosure, the signal processing circuit includes the capacitor provided in the wiring layer. According to an aspect of the present disclosure, the signal processing circuit includes an analog-to-digital (“AD”) conversion circuit configured to convert the signal into a digital signal, and the AD conversion circuit includes a comparison circuit configured to compare the signal inputted via the capacitor with a reference signal. According to an aspect of the present disclosure, the first substrate includes a semiconductor layer, the readout circuit includes a second transistor, one or more portions of the second transistor are provided in the semiconductor layer, and the one of the first transistor and the capacitor is provided above the second transistor. According to an aspect of the present disclosure, the readout circuit includes a floating diffusion and a transfer transistor, the transfer transistor configured to transfer the electric charge converted by the photoelectric conversion element to the floating diffusion, the second transistor is configured to output the signal based on electric charge accumulated in the floating diffusion, and the one of the first transistor and the capacitor is electrically coupled to the second transistor. According to an aspect of the present disclosure, the signal processing circuit includes a semiconductor region and a gate electrode of the first transistor in the wiring layer. According to an aspect of the present disclosure, the second substrate includes a semiconductor layer, the signal processing circuit includes a transistor provided on a surface of the semiconductor layer, and the one of the first transistor and the capacitor is provided above the transistor. According to an aspect of the present disclosure, the one of the first transistor and the capacitor is electrically coupled to the transistor. According to an aspect of the present disclosure, the one of the first transistor and the capacitor is above a semiconductor layer of the first substrate and below a semiconductor layer of the second substrate. According to an aspect of the present disclosure, the signal processing circuit includes the first transistor and a second transistor provided in the wiring layer, and the first transistor and the second transistor are provided in different tiers of the wiring layer. According to an aspect of the present disclosure, the first transistor is electrically coupled to the second transistor. According to an embodiment of the present disclosure, there is provided an electronic apparatus, including an optical system and a photodetector that receives light transmitted through the optical system. The photodetector includes a first substrate including a photoelectric conversion element and one or more components of a readout circuit. The photoelectric conversion element is configured to photoelectrically convert light to an electric charge and the readout circuit is configured to output a signal based on the electric charge converted by the photoelectric conversion element. The photodetector includes a second substrate including one or more components of a signal processing circuit. The signal processing circuit is configured to process the signal and the second substrate is stacked on the first substrate. The photodetector includes a wiring layer provided in one of the first substrate and the second substrate. The signal processing circuit includes one or more portions of a first transistor and a capacitor provided in the wiring layer A photodetector according to an embodiment of the present disclosure includes a first substrate, a second substrate, and a wiring layer. The first substrate includes a photoelectric conversion element and at least a portion of a readout circuit. The photoelectric conversion element photoelectrically converts light. The readout circuit is configured to output a first signal based on electric charge converted by the photoelectric conversion element. The second substrate includes at least a portion of a signal processing circuit configured to execute signal processing on the first signal. The second substrate is stacked on the first substrate. The wiring layer is provided in the first substrate or the second substrate. The signal processing circuit includes a first element provided in the wiring layer. An electronic apparatus according to an embodiment of the present disclosure includes an optical system, and a photodetector that receives light transmitted through the optical system. The photodetector includes a first substrate, a second substrate, and a wiring layer. The first substrate includes a photoelectric conversion element and at least a portion of a readout circuit. The photoelectric conversion element photoelectrically converts light. The readout circuit is configured to output a first signal based on electric charge converted by the photoelectric conversion element. The second substrate includes at least a portion of a signal processing circuit configured to execute signal processing on the first signal. The second substrate is stacked on the first substrate. The wiring layer is provided in the first substrate or the second substrate. The signal processing circuit includes a first element provided in the wiring layer.

[0008] Fig. 1 is a block diagram illustrating an example of a schematic configuration of an imaging device which is an example of a photodetector according to an embodiment of the present disclosure.Fig. 2 is a diagram illustrating an example of a pixel section of the imaging device according to an embodiment of the present disclosure.Fig. 3 is an explanatory diagram of an example of a circuit configuration of a pixel of the imaging device according to an embodiment of the present disclosure.Fig. 4 is an explanatory diagram of a configuration example of a signal processing circuit of the imaging device according to an embodiment of the present disclosure.Fig. 5 is an explanatory diagram of an example of a cross-sectional configuration of the imaging device according to an embodiment of the present disclosure.Fig. 6A is an explanatory diagram of a configuration example of the imaging device according to an embodiment of the present disclosure.Fig. 6B is an explanatory diagram of the configuration example of the imaging device according to an embodiment of the present disclosure.Fig. 7A is an explanatory diagram of another configuration example of the imaging device according to an embodiment of the present disclosure.Fig. 7B is an explanatory diagram of the other configuration example of the imaging device according to an embodiment of the present disclosure.Fig. 8A is an explanatory diagram of the other configuration example of the imaging device according to an embodiment of the present disclosure.Fig. 8B is an explanatory diagram of the other configuration example of the imaging device according to an embodiment of the present disclosure.Fig. 9A is an explanatory diagram of the other configuration example of the imaging device according to an embodiment of the present disclosure.Fig. 9B is an explanatory diagram of the other configuration example of the imaging device according to an embodiment of the present disclosure.Fig. 10A is an explanatory diagram of the other configuration example of the imaging device according to an embodiment of the present disclosure.Fig. 10B is an explanatory diagram of the other configuration example of the imaging device according to an embodiment of the present disclosure.Fig. 11 is an explanatory diagram of a configuration example of an imaging device according to Modification Example 1 of the present disclosure.Fig. 12 is an explanatory diagram of another configuration example of the imaging device according to Modification Example 1 of the present disclosure.Fig. 13 is an explanatory diagram of a configuration example of an imaging device according to Modification Example 2 of the present disclosure.Fig. 14 is a block diagram illustrating a configuration example of an electronic apparatus including the imaging device.Fig. 15 is a block diagram depicting an example of schematic configuration of a vehicle control system.Fig. 16 is a diagram of assistance in explaining an example of installation positions of an outside-vehicle information detecting section and an imaging section.Fig. 17 is a view depicting an example of a schematic configuration of an endoscopic surgery system.Fig. 18 is a block diagram depicting an example of a functional configuration of a camera head and a camera control unit (CCU).

[0009] Hereinafter, description is given in detail of embodiments of the present disclosure with reference to the drawings. It is to be noted that the description is given in the following order. 1. Embodiment 2. Modification Examples 3. Application Example 4. Practical Application Examples <1. Embodiment>

[0010] Fig. 1 is a block diagram illustrating an example of a schematic configuration of an imaging device which is an example of a photodetector according to an embodiment of the present disclosure. Fig. 2 is a diagram illustrating an example of a pixel section of the imaging device according to the embodiment. The photodetector is a device that is able to detect incident light. An imaging device 1, which is a photodetector, includes a plurality of pixels P each including a photoelectric conversion section (photoelectric conversion element), and is configured to photoelectrically convert incident light and generate a signal.

[0011] The imaging device 1 may receive light transmitted through an optical system (unillustrated) including an optical lens and generate a signal. The imaging device 1 is configured using, for example, a semiconductor substrate (e.g., a silicon substrate) provided with the plurality of pixels P. The photoelectric conversion section of each of the pixels P of the imaging device 1 is, for example, a photodiode (PD), and is configured to be able to photoelectrically convert light.

[0012] As an example, as illustrated in Figs. 1 and 2, the imaging device 1 includes, as an imaging area, a region (a pixel section 100) in which the plurality of pixels P is two-dimensionally arranged in matrix. The pixel section 100 of the imaging device 1 can be referred to as a pixel array in which the plurality of pixels P is arranged, and can also be referred to as a light-receiving region. The photoelectric conversion section of each of the pixels P can also be referred to as a photoelectric conversion region.

[0013] The imaging device 1 takes in incident light (image light) from a subject, which is a measurement target, via the optical system including the optical lens. The imaging device 1 captures an image of the subject formed by the optical lens. The imaging device 1 may photoelectrically convert received light (e.g., visible light, infrared light, etc.) and generate a pixel signal. The imaging device 1, which is a photodetector, is a device that is able to receive incident light and generate a signal. The imaging device 1 can also be referred to as a light-receiving device.

[0014] As an example, the imaging device 1 (photodetector) may be configured as an image sensor. The imaging device 1 is, for example, a CMOS (Complementary Metal Oxide Semiconductor) image sensor. The imaging device 1 may have a structure (stacked structure) configured by stacking a plurality of semiconductor layers. The imaging device 1 is usable for various electronic apparatuses such as a digital still camera, a video camera, and a mobile phone.

[0015] It is to be noted that, as illustrated in Fig. 2, a direction in which light from the subject is incident is defined as a Z-axis direction; a right-left direction on the sheet orthogonal to the Z-axis direction is defined as an X-axis direction; and an up-down direction on the sheet orthogonal to the Z-axis direction and the X-axis direction is defined as a Y-axis direction. In the following drawings, the arrow directions in Fig. 2 may be used, in some cases, as a standard to express directions.Schematic Configuration of Imaging Device

[0016] As an example, the imaging device 1 includes a pixel section 100, a pixel control section 105, a signal processing block 112, a control section 113, and a processing section 114, as in the example illustrated in Fig. 1. In addition, the imaging device 1 is provided with, for example, a plurality of control lines Lread and a plurality of signal lines VSL.

[0017] The control line Lread is a signal line that is able to convey a signal to control the pixel P, and is coupled to the pixel control section 105 and the pixel P of the pixel section 100. In the example illustrated in Fig. 1, the plurality of control lines Lread is wired for respective pixel rows configured by the plurality of pixels P arranged in a horizontal direction (row direction) in the pixel section 100. The control line Lread is configured to transmit a control signal to read a signal from the pixel P.

[0018] As an example, the plurality of control lines Lread for the respective pixel rows of the imaging device 1 includes wiring that transmits a signal to control a transfer transistor, wiring that transmits a signal to control a selection transistor, wiring that transmits a signal to control a reset transistor, and the like. The control line Lread can also be referred to as a drive line (pixel drive line) that transmits a signal to drive the pixel P.

[0019] The signal line VSL is a signal line that is able to convey a signal from the pixel P, and is coupled to the pixels P of the pixel section 100 and the signal processing block 112. In the pixel section 100, for example, the signal lines VSL are wired for respective pixel columns configured by the plurality of pixels P arranged in a vertical direction (column direction). The signal line VSL is a vertical signal line, and is configured to be able to transmit a signal outputted from the pixel P.

[0020] The pixel control section 105 is configured to be able to control each of the pixels P of the pixel section 100. The pixel control section 105 is a control circuit, and is configured by a plurality of circuits including a buffer, a shift register, an address decoder, and the like, for example. The pixel control section 105 generates a signal for controlling the pixel P, and outputs the generated signal to each of the pixels P of the pixel section 100 via the control line Lread. The pixel control section 105 is controlled by the control section 113, and controls the pixel P of the pixel section 100.

[0021] The pixel control section 105 generates, for example, a signal to control the pixel P, such as a signal to control a transfer transistor of the pixel P, a signal to control a selection transistor, and a signal to control a reset transistor, and supplies the generated signal to each of the pixels P by the control line Lread. The pixel control section 105 may perform a control to read a pixel signal from each of the pixels P. The pixel control section 105 can also be referred to as a pixel drive section configured to be able to drive each of the pixels P. It is to be noted that the pixel control section 105 and the control section 113 can also be collectively referred to as the pixel control section.

[0022] The signal processing block 112 is configured to be able to execute signal processing on an inputted pixel signal. The signal processing block 112 includes a signal processing circuit 200 provided for every plurality of pixels P, for example. The signal processing circuit 200 (signal processing section) is provided for each of the plurality of signal lines VSL, for example.

[0023] The signal processing circuit 200 includes, for example, a load circuit, an AD (Analog Digital) conversion circuit, a horizontal selection switch, and the like. In the imaging device 1, as an example, the load circuit, the AD conversion circuit, and the like are provided for each pixel column configured by the plurality of pixels P arranged in the column direction (vertical direction) in pixel section 100. The signal processing circuit 200 is provided for the pixel column, and can be referred to as a column circuit. In the imaging device 1, a plurality of signal processing circuits 200 (column circuits) is arranged in a size (arrangement interval) corresponding to a size (pitch) of the pixel P, for example.

[0024] The signal outputted from each of the pixels P selectively scanned by the pixel control section 105 is inputted to the signal processing block 112 via the signal line VSL. The signal processing block 112 may perform, for example, signal processing such as CDS (Correlated Double Sampling: correlated double sampling) and AD conversion of a signal of the pixel P. The signal of each of the pixels P transmitted through each of the signal lines VSL is subjected to signal processing by the signal processing block 112, and is outputted to the processing section 114.

[0025] The processing section 114 is configured to be able to execute signal processing on an inputted signal. The processing section 114 is a processing circuit, and is configured by, for example, a circuit that performs various types of signal processing on a pixel signal. The processing section 114 may include a processor and a memory. The processing section 114 performs signal processing on the pixel signal inputted from the signal processing block 112, and outputs the processed pixel signal. The processing section 114 may perform, for example, various types of signal processing such as noise reduction processing or gradation correction processing.

[0026] The control section 113 is configured to be able to control each section of the imaging device 1. The control section 113 may receive a clock applied from the outside, data commanding an operation mode, or the like, and output data such as internal information on the imaging device 1. The control section 113 is a control circuit, and includes, for example, a timing generator configured to be able to generate various timing signals.

[0027] The control section 113 controls driving of the pixel control section 105, the signal processing block 112, and the like on the basis of the various timing signals (pulse signals, clock signals, etc.) generated by the timing generator. It is to be noted that the control section 113 and the processing section 114 may be integrally configured.Configuration of Pixel

[0028] Fig. 3 is an explanatory diagram of an example of a circuit configuration of the pixel of the imaging device according to the embodiment. The pixel P includes a photoelectric conversion section 12 (photoelectric conversion element) and a readout circuit 20. The photoelectric conversion section 12 is configured to receive light and generate a signal. The readout circuit 20 is configured to be able to output a signal based on photoelectrically converted electric charge.

[0029] The photoelectric conversion section 12 is a light-receiving section (light-receiving element), and is configured to be able to generate electric charge by photoelectric conversion. In the example illustrated in Fig. 3, the photoelectric conversion section 12 is a photodiode (PD), and converts incident light into electric charge. The photoelectric conversion section 12 may perform photoelectric conversion to generate electric charge corresponding to a received light amount.

[0030] As an example, the readout circuit 20 includes a transistor TG, a floating diffusion FD, a transistor AMP, a transistor SEL, and a transistor RST. The readout circuit 20 may read a pixel signal based on the electric charge photoelectrically converted by the photoelectric conversion section 12.

[0031] The transistor TG is a transfer transistor, and is configured to be able to transfer the electric charge photoelectrically converted by the photoelectric conversion section 12 to the floating diffusion FD. The transistor TG is controlled by a signal STR, and electrically couples or decouples the photoelectric conversion section 12 and the floating diffusion FD to or from each other. The transistor TG may transfer the electric charge photoelectrically converted by and accumulated in the photoelectric conversion section 12 to the floating diffusion FD.

[0032] The floating diffusion FD is an accumulation section, and is configured to be able to accumulate the transferred electric charge. The floating diffusion FD may accumulate the electric charge photoelectrically converted by the photoelectric conversion section 12. The floating diffusion FD can also be referred to as a holding section that is able to hold the transferred electric charge. The floating diffusion FD accumulates the transferred electric charge, and converts the electric charge into a voltage corresponds to capacitance of the floating diffusion FD.

[0033] The transistor AMP is configured to generate and output a signal based on the electric charge accumulated in the floating diffusion FD. The transistor AMP is an amplification transistor, and may generate and output a signal based on the electric charge converted by the photoelectric conversion section 12.

[0034] As illustrated in Fig. 3, a gate of the transistor AMP is electrically coupled to the floating diffusion FD, and receives an input of the voltage converted by the floating diffusion FD. A drain of the transistor AMP is coupled to a power supply line to be supplied with a power supply voltage (a power supply voltage VDD1 in the example illustrated in Fig. 3).

[0035] A source of the transistor AMP is coupled to the signal line VSL via the transistor SEL. The transistor AMP is configured to generate a signal based on the electric charge accumulated in the floating diffusion FD, i.e., a signal based on the voltage of the floating diffusion FD and to output the generated signal to the signal line VSL.

[0036] The transistor SEL is configured to be able to control the output of the pixel signal. The transistor SEL is electrically coupled in series to the transistor AMP, for example, as in the example illustrated in Fig. 3. The transistor SEL is controlled by a signal SSEL, and is configured to be able to output the signal from the transistor AMP to the signal line VSL. The transistor SEL is a selection transistor, and may control an output timing of the pixel signal.

[0037] The transistor SEL is configured to be able to output the signal based on the electric charge converted by the photoelectric conversion section 12. The transistor SEL may output the pixel signal of the pixel P to the signal line VSL. It is to be noted that the transistor SEL may be electrically coupled in series between the power supply line to be supplied with the power supply voltage VDD and the transistor AMP. In addition, the transistor SEL may be omitted as necessary.

[0038] The transistor RST is configured to be able to reset the voltage of the floating diffusion FD. In the example illustrated in Fig. 3, the transistor RST is electrically coupled to the power supply line to be supplied with the power supply voltage VDD1, and is configured to reset the electric charge of the pixel P. The transistor RST is a reset transistor.

[0039] The transistor RST may be controlled by a signal SRST to reset the electric charge accumulated in the floating diffusion FD and to reset the voltage of the floating diffusion FD. The transistor RST may electrically couple the power supply line and the floating diffusion FD to each other and discharge the electric charge accumulated in the floating diffusion FD. It is to be noted that the transistor RST may discharge the electric charge accumulated in the photoelectric conversion section 12 via the transistor TG.

[0040] It is to be noted that the readout circuit 20 may be configured to be able to change conversion efficiency (gain) upon conversion of electric charge into a voltage. For example, the readout circuit 20 may include a transistor (switching transistor) to be used for setting of the conversion efficiency. As an example, the switching transistor is electrically coupled between the floating diffusion FD and the transistor RST.

[0041] The switching transistor coming into an ON state in the readout circuit 20 increases capacitance to be added to the floating diffusion FD of the pixel P, thus switching the conversion efficiency (gain) upon conversion of the electric charge into the voltage. The switching transistor may switch capacitance to be coupled to the gate of the transistor AMP to change the conversion efficiency.

[0042] The transistor TG (transfer transistor), the transistor AMP (amplification transistor), the transistor SEL (selection transistor), the transistor RST (reset transistor), and the switching transistor, which are described above, are each a MOS transistor (MOSFET) including terminals of a gate, a source, and a drain.

[0043] In the example illustrated in Fig. 3, the transistor TG, the transistor AMP, the transistor SEL, and the transistor RST are each configured by an NMOS transistor. It is to be noted that the transistor of the pixel P may also be configured by a PMOS transistor.

[0044] The pixel control section 105 (see Fig. 1) of the imaging device 1 supplies a control signal to gates of the transistor TG, the transistor SEL, the transistor RST, the switching transistor, and the like of each of the pixels P via the above-described control line Lread to bring the transistors into an ON state (electrically-conductive state) or an OFF state (non-electrically-conductive state).

[0045] The plurality of control lines Lread for the respective pixel rows of the imaging device 1 includes, as an example, wiring that transmits a signal STG to control the transistor TG, wiring that transmits the signal SSEL to control the transistor SEL, wiring that transmits the signal SRST to control the transistor RST, and the like.

[0046] The transistor TG, the transistor SEL, the transistor RST, the switching transistor, and the like are controlled ON / OFF by the pixel control section 105. The pixel control section 105 controls the readout circuit 20 of each of the pixels P to thereby allow the pixel signal to be outputted from each of the pixels P to the signal line VSL. The pixel control section 105 may perform a control to read the pixel signal of each of the pixels P to the signal line VSL.

[0047] It is to be noted that the imaging device 1 may have a configuration in which the plurality of pixels P shares one readout circuit 20. For example, in the imaging device 1, the readout circuit 20 may be provided for the plurality of pixels P. The readout circuit 20 is disposed for every plurality of pixels P, and the plurality of pixels P shares one readout circuit 20. As an example, 2 by 2 pixels configured by four adjacent pixels P may share one readout circuit 20.

[0048] Fig. 4 is an explanatory diagram of a configuration example of a signal processing circuit of the imaging device according to the embodiment. As illustrated in Fig. 4, the signal processing circuit 200 includes a load circuit 30 and an AD conversion circuit 40. The load circuit 30 and the AD conversion circuit 40 are provided for each of the plurality of signal lines VSL.

[0049] In addition, the signal processing circuit 200 may include a switch SW1, a switch SW11, a switch SW12, and a signal generation circuit 80. The switch SW1 is provided between the signal line VSL and the AD conversion circuit 40. A pixel signal read from the pixel P is inputted to the AD conversion circuit 40 via the switch SW1. The switch SW1 is configured using a transistor, for example.

[0050] The load circuit 30 is configured by, for example, a current source that is able to supply a current to the signal line VSL and the readout circuit 20. The load circuit 30 is provided for each of the signal lines VSL. The readout circuit 20 of the pixel P is electrically coupled to the load circuit 30 via the signal line VSL and the switch SW1, for example. In the example illustrated in Fig. 4, the load circuit 30 includes a transistor Tr1 as a current source.

[0051] The transistor Tr1 of the load circuit 30 is electrically coupled to the signal line VSL, and is configured to be able to supply a current to the signal line VSL. The transistor Tr1 is electrically coupled to the transistor SEL and the transistor AMP of each of the pixels P via the signal line VSL. For example, the transistor Tr1 may generate a current corresponding to a signal level of a signal to be inputted to a gate thereof, and may supply the generated current to the transistor AMP. The transistor Tr1 constitutes a source follower circuit together with the transistor AMP.

[0052] The signal processing circuit 200 includes a plurality of AD conversion circuits 40 (AD converters), and may output a pixel signal having been converted to a digital signal by the AD conversion circuit 40. The AD conversion circuit 40 is an ADC (Analog to Digital Converter). The AD conversion circuit 40 is provided for each of the plurality of signal lines VSL, for example. The AD conversion circuit 40 may be provided for each of the pixel columns of the pixel section 100.

[0053] The AD conversion circuit 40 is configured to convert an inputted analog signal into a digital signal. The AD conversion circuit 40 performs AD conversion processing on a pixel signal, which is an analog signal, inputted from each of the pixels P via the signal line VSL.

[0054] The signal generation circuit 80 is configured to be able to generate a reference signal. The signal generation circuit 80 (signal generation section) is configured to generate a signal of which a signal level changes as time elapses, for example. The signal generation circuit 80 may be coupled in common to the AD conversion circuits 40, and may generate a reference signal (reference signal) to be used for the AD conversion to supply the generated reference signal to each of the AD conversion circuits 40.

[0055] The signal generation circuit 80 includes, for example, a DA conversion circuit (DAC: Digital to Analog Converter), and is configured to generate a ramp signal which is an analog signal. The signal generation circuit 80 is configured, for example, as a ramp signal generation circuit, and generates a ramp signal RAMP which is a reference signal that changes as time elapses.

[0056] The AD conversion circuit 40 includes, for example, a comparison circuit 50 and a counter (unillustrated). The AD conversion circuit 40 is configured to be able to convert an inputted pixel signal into a digital signal of a predetermined bit number. The AD conversion circuit 40 is a single-slope ADC, for example.

[0057] The comparison circuit 50 is configured by a comparator circuit, for example, and is configured to be able to compare a pixel signal and a reference signal (reference signal) with each other. The comparison circuit 50 (comparator) may compare a pixel signal and a reference signal with each other. The pixel signal is an analog signal and is a conversion target, and the reference signal is a comparison target.

[0058] As an example, the comparison circuit 50 includes an input section 51, an input section 52, and an output section 53, and is configured using a differential amplifier that is able to amplify a signal. In the example illustrated in Fig. 4, the comparison circuit 50 includes the differential amplifier including a transistor Tr11 and a transistor Tr12 constituting a differential pair 55, and a transistor Tr21 and a transistor Tr22 constituting a current mirror 56.

[0059] In addition, the comparison circuit 50 includes a current source 57 including a transistor Tr25. The transistor Tr25 of the current source 57 is configured to be able to supply a current to the differential pair 55 and the current mirror 56. The differential pair 55, the current mirror 56, and the current source 57 are electrically coupled to each other between a power supply line to be supplied with a power supply voltage VDD2 and a potential line L1. The potential line L1 is wiring to be supplied with a predetermined potential (voltage), and may also be referred to as a reference potential line. The potential line L1 is a ground line (GND line), for example.

[0060] The transistors Tr11 and Tr12 are each a differential input transistor. The transistor Tr11 and the transistor Tr12 are each configured by an NMOS transistor, for example. The transistor Tr21 and the transistor Tr22 are each an active load transistor. The transistor Tr21 and the transistor Tr22 are each configured by a PMOS transistor, for example.

[0061] The input section 51 and the input section 52 of the comparison circuit 50 are each an input terminal. A capacitor 41 is electrically coupled in series to the input section 51, and a capacitor 42 is electrically coupled in series to the input section 52. In the example illustrated in Fig. 4, one electrode (terminal) of the capacitor 41 is electrically coupled to the switch SW1, the load circuit 30, and the like. Another electrode of the capacitor 41 is electrically coupled to a gate of the transistor Tr11.

[0062] One electrode of the capacitor 42 is electrically coupled to the signal generation circuit 80. Another electrode of the capacitor 42 is electrically coupled to a gate of the transistor Tr12. The capacitors 41 and 42 are each configured by a capacitor such as a MOS capacitor or an MIM (Metal-Insulator-Metal) capacitor.

[0063] A pixel signal outputted from the pixel P to the signal line VSL is inputted to the input section 51 of the comparison circuit 50 via the capacitor 41. In addition, the ramp signal RAMP is inputted to the input section 52 of the comparison circuit 50 from the signal generation circuit 80 via the capacitor 42.

[0064] The comparison circuit 50 compares a signal outputted from the pixel P and the ramp signal RAMP of which a voltage (potential) changes with each other, and outputs a signal Vout which is a result of the comparison from the output section 53. The signal Vout outputted from the comparison circuit 50 is a signal indicating a magnitude relationship between the signal outputted from the pixel P and the ramp signal RAMP.

[0065] A counter (unillustrated) of the AD conversion circuit 40 is configured to count (perform counting) in accordance with an inputted signal. The counter (counter circuit) may measure time until inversion of the comparison result at the comparison circuit 50 on the basis of an inputted clock signal and the signal Vout from the comparison circuit 50, and may generate a signal indicating a count value.

[0066] The counter may hold, as a pixel signal after AD conversion, a digital signal indicating a count value corresponding to a period from the start of the comparison by the comparison circuit 50 to the inversion (change) of the comparison result. Pixel signals sequentially outputted from the respective pixels P are converted into digital signals by the AD conversion by the AD conversion circuit 40.

[0067] The switch SW11 and the switch SW12 are each configured using a transistor, for example. In the example illustrated in Fig. 4, the switch SW11 includes a transistor Tr31, and is electrically coupled between a node N1 and the potential line L1. The node N1 couples the signal line VSL and the capacitor 41 to each other. The switch SW11 electrically couples or decouples the node N1 and the potential line L1 to or from each other.

[0068] In addition, in the example illustrated in Fig. 4, the switch SW12 includes a transistor Tr32, and is electrically coupled between a node N2 and the potential line L1. The node N2 couples the signal generation circuit 80 and the capacitor 42 to each other. The switch SW12 electrically couples or decouples the node N2 and the potential line L1 to or from each other. Using the switch SW11 and the switch SW12 makes it possible to prevent (or alternatively reduce the possibility of) the node N1 and the node N2 from being brought into an electrically floating state (floating state).Configuration of Imaging Device

[0069] Fig. 5 is an explanatory diagram of an example of a cross-sectional configuration of the imaging device according to the embodiment. As in the example illustrated in Fig. 5, for example, the imaging device 1 includes a semiconductor layer 101, a wiring layer 111, a wiring layer 121, and a semiconductor layer 102. The imaging device 1 has a configuration in which the semiconductor layer 101, the wiring layer 111, the wiring layer 121, and the semiconductor layer 102 are stacked in the Z-axis direction.

[0070] In the example illustrated in Fig. 5, the semiconductor layer 101, the wiring layer 111, the wiring layer 121, and the semiconductor layer 102 are provided from a light-incident side. The semiconductor layer 101 and the semiconductor layer 102 are each configured by a semiconductor substrate (e.g., a silicon substrate, an SOI (Silicon On Insulator) substrate, etc.). It is to be noted that the semiconductor layer 101 and the semiconductor layer 102 may be configured using an SiGe (silicon germanium) substrate, another compound semiconductor material, or the like.

[0071] As an example, the imaging device 1 may be configured by a substrate 201 and a substrate 202. The substrate 201 includes the semiconductor layer 101 and the wiring layer 111, and the substrate 202 includes the semiconductor layer 102 and the wiring layer 121. For example, the substrate 201 includes the photoelectric conversion section 12, the readout circuit 20, and the like described above which are formed therein. The semiconductor layer 101 has a surface 11S1 and a surface 11S2 opposed to each other, as illustrated in Fig. 5. The surface 11S2 is a surface on a side opposite to the surface 11S1. The surface 11S2 of the semiconductor layer 101 is a light-receiving surface (light incident surface), for example.

[0072] In addition, the semiconductor layer 102 has a surface 12S1 and a surface 12S2 opposed to each other. The surface 12S2 of the semiconductor layer 102 is a surface on a side opposite to the surface 12S1. The surface 11S1 and the surface 12S1 are each, for example, an element formation surface on which an element such as a transistor is formed. Each of the surfaces 11S1 and 12S1 may be provided with a gate electrode, a gate insulating film (e.g., a gate oxide film), or the like.

[0073] In the semiconductor layer 101, a plurality of photoelectric conversion sections 12 (photoelectric conversion elements) is provided along the surface 11S1 and the surface 11S2 of the semiconductor layer 101. The photoelectric conversion section 12 can also be referred to as a photoelectric conversion layer. For example, the plurality of photoelectric conversion sections 12 is formed to be embedded in the semiconductor layer 101. The photoelectric conversion section 12 is provided between the surface 11S1 and the surface 11S2 of the semiconductor layer 101.

[0074] As an example, the transistor TG, the floating diffusion FD, and the like are provided on a side of the surface 11S1 of the semiconductor layer 101. The floating diffusion FD includes, for example, an n-type semiconductor region. In addition, at least some of other transistors (such as the transistors AMP, SEL, and RST) of the readout circuit 20 may be provided on the side of the surface 11S1 of the semiconductor layer 101.

[0075] The wiring layer 111 is provided on the side of the surface 11S1 of the semiconductor layer 101. For example, a lens 31 and a filter 32 are provided on a side of the surface 11S2 of the semiconductor layer 101. The lens 31 (lens section) is a lens that condenses light, and is an optical member also called an on-chip lens. The lens 31 is provided above the photoelectric conversion section 12 for each of the pixels P or for every plurality of pixels P, for example.

[0076] Light from a subject, which is a measurement target, is incident on the lens 31 via an optical system such as an imaging lens. The lens 31 guides the incident light toward a side of the photoelectric conversion section 12 of the pixel P. The photoelectric conversion sections 12 of the pixels P each photoelectrically convert light incident via the lens 31 and the filter 32.

[0077] The filter 32 is configured to selectively transmit light of a specific wavelength region of incident light. The filter 32 is a color filter of RGB, a color filter of a complementary color system, a filter that transmits infrared light, or the like. The filter 32 is provided above the photoelectric conversion section 12, for example, for each of the pixels P or for every plurality of pixels P. As an example, the filter 32 is formed between the lens 31 and the semiconductor layer 101.

[0078] The filter 32 is provided on the side of the surface 11S2 of the semiconductor layer 101, for example, for each of the pixels P or for every plurality of pixels P. It is to be noted that, in the imaging device 1, the filter 32 may be omitted as necessary. The filter 32 may not be provided in some or all of the pixels P of the imaging device 1. For example, the filter 32 may not be provided in the pixel P in which white (W) light is received to perform photoelectric conversion.

[0079] The lens 31, the filter 32, and the like are provided on the side on which light from the optical system is incident, and the wiring layer 111 is provided on a side opposite to the light incident side. The lens 31 and the filter 32 are stacked on the semiconductor layer 101 in a thickness direction orthogonal to the surface 11S2 of the semiconductor layer 101. The imaging device 1 is a so-called back side illumination imaging device.

[0080] The wiring layer 121 is provided on a side of the surface 12S1 of the semiconductor layer 102. The wiring layers 111 and 121 each include, for example, a conductive film and an insulating film, and includes a plurality of pieces of wiring, a via (VIA), and the like. The wiring layers 111 and 121 each include, for example, wiring of two or more layers, or wiring of three or more layers.

[0081] The wiring layers 111 and 121 each have, for example, a configuration in which a plurality of pieces of wiring is stacked with an insulating film as an interlayer insulating film (interlayer insulating layer) being interposed therebetween. At least some of each of the wiring layers 111 and 121 are each, for example, a wiring layer formed by BEOL (Back End of Line), and can also be referred to as a BEOL layer (or a BEOL wiring layer).

[0082] Each wiring of the wiring layers 111 and 121 is formed using a metal material such as aluminum (Al), tungsten (W), or copper (Cu). It is to be noted that each wiring of the wiring layers 111 and 121 may be configured using polysilicon, or another electrically-conductive material. The interlayer insulating film is formed using, for example, silicon oxide (SiO), silicon nitride (SiN), silicon oxynitride (SiON), or the like.

[0083] The imaging device 1 includes a separation region 70 which is a separation region (separation section) provided around the pixel P. The separation region 70 is configured using a trench (groove), for example. As an example, the separation region 70 is provided to penetrate the semiconductor layer 101.

[0084] The separation region 70 is provided between the plurality of pixels P adjacent to each other in the semiconductor layer 101, and separates the pixels P (or the photoelectric conversion sections 12) from each other. At least a portion of the separation region 70 is provided at a boundary between the pixels P adjacent to each other. It can also be said that the pixel P has a structure partitioned by the separation region 70.

[0085] The separation region 70 has an FTI (Full Trench Isolation) structure, for example, and is formed to penetrate the semiconductor layer 101. The separation region 70 is provided to surround each of the photoelectric conversion sections 12 in the semiconductor layer 101. The separation region 70 can also be referred to as an inter-pixel separation section or an inter-pixel separation wall.

[0086] As an example, an insulating film (insulator) such as an oxide film (e.g., a silicon oxide film) or a nitride film (e.g., a silicon nitride film) is provided in the trench of the separation region 70. The separation region 70 may be filled with polysilicon, a metal material, another insulating material, or the like. In addition, the separation region 70 may have an air gap (cavity).

[0087] The wiring layer 111 is provided with a plurality of electrodes 91, and the wiring layer 121 is provided with a plurality of electrodes 92. The electrode 91 and the electrode 92 are each, for example, an electrode formed using copper (Cu). The electrodes 91 and 92 are each an electrode to be used for bonding between metal electrodes, and can also each be referred to as a bonding electrode. It is to be noted that the electrode 91 and the electrode 92 may each be configured by a metal material other than copper, e.g., nickel (Ni), cobalt (Co), tin (Sn), gold (Au), or the like, or may be configured by another material.

[0088] As an example, the substrate 201 and the substrate 202 are attached to each other by bonding between metal electrodes (electrodes 91 and 92) including Cu, i.e., by Cu-Cu bonding. The electrode 91 and the electrode 92 allow a circuit of the substrate 201 and a circuit of the substrate 202 to be electrically coupled to each other. It is to be noted that a bump may be used to stack the substrate 201 and the substrate 202.

[0089] The semiconductor layer 102 and the wiring layer 121 are provided with the signal processing block 112 including the signal processing circuit 200 described above, for example. It is to be noted that the pixel control section 105, the control section 113, and the processing section 114 (see Fig. 1) may be provided in the substrate 202 or another substrate other than the substrate 202.

[0090] In the imaging device 1, at least some of circuit elements of the signal processing circuit 200 are provided in the wiring layers 121 and 111. Some of the circuit elements included in the signal processing circuit 200, e.g., a transistor, a capacitor, and resistance element may be formed in the wiring layer 121 or the wiring layer 111. For example, in the wiring layer 121, a transistor used for the load circuit 30 or the AD conversion circuit 40 is provided as a thin-film transistor (TFT: Thin Film Transistor).

[0091] In the imaging device 1, a transistor constituting the load circuit 30, some of transistors included in the comparison circuit 50, and the like may each be configured as the thin-film transistor, and may be disposed in the wiring layer 121 or in the wiring layer 111. For example, the transistor Tr1 of the load circuit 30 may be disposed in the wiring layer 121 or in the wiring layer 111. Some of transistors among a plurality of transistors of the comparison circuit 50 may be disposed in the wiring layer 121, and some of other transistors may be disposed in the semiconductor layer 102.

[0092] In the example illustrated in Fig. 5, the wiring layer 121 of the imaging device 1 is provided with a circuit element C1. In the imaging device 1, for example, a plurality of circuit elements C1 is provided for each signal processing circuit 200. The circuit element C1 is a transistor, a capacitor, a resistance element, or the like included in the signal processing circuit 200. The circuit element C1 may be a resistance element configured by a diode-coupled transistor. As an example, the circuit element C1 is used as the transistor Tr1 of the above-described load circuit 30, or the transistor Tr11, the transistor Tr12, the capacitor 41, or the capacitor 42 of the comparison circuit 50.

[0093] The circuit element C1 includes, for example, a semiconductor region 61, an electrode 62a, an electrode 62b, a gate insulating film 65, and a gate electrode 66. In the example illustrated in Fig. 5, the semiconductor region 61 is provided in the wiring layer 121, with an insulating film (interlayer insulating film) of the wiring layer 121 used as a base film. It can also be said that the semiconductor region 61 is disposed to replace a portion of the wiring layer 121.

[0094] The insulating film (interlayer insulating film) of the wiring layer 121 is configured using, for example, silicon oxide (SiO), silicon nitride (SiN), TEOS, or the like. The insulating film of the wiring layer 121 may be formed using SiCN, SiCON, Al2O3, HfO2, ZrO2, or the like, or may be configured using another insulating material. The insulating film of the wiring layer 121 is also a passivation film (protective film) of the thin-film transistor, and may be formed to cover a periphery of each thin-film transistor.

[0095] The semiconductor region 61 is a region (channel region) in which a channel is formed. The semiconductor region 61 is, for example, a channel region including an oxide semiconductor. The semiconductor region 61 may be configured by an oxide semiconductor such as InGaZnO, InZnO, ZnO, SnO, or TiO2.

[0096] It is to be noted that the semiconductor region 61 may be formed using a two-dimensional substance (such as MoS2, WS2, MoSe2, WSe2, or HfS2). The semiconductor region 61 may be configured using, as a channel material, an organic semiconductor (such as fullerene, rubrene, or pentacene), a carbon nanotube, hydrogenated amorphous silicon, low-temperature polysilicon, or the like.

[0097] The electrode 62a and the electrode 62b are each available as a source electrode and a drain electrode, for example. One of the electrodes 62a and 62b is a source electrode of the circuit element C1, and another of the electrodes 62a and 62b is a drain electrode of the circuit element C1. It is to be noted that the electrode 62a and the electrode 62b are also each available as an electrode (terminal) of a capacitor (e.g., MOS capacitor).

[0098] The electrode 62a and the electrode 62b are each formed using a metal material such as copper (Cu), tungsten (W), cobalt (Co), or ruthenium (Ru), for example. It is to be noted that the electrode 62a and the electrode 62b may be configured using another electrically-conductive material. The electrodes 62a and 62b may be configured by a low-resistance electrically-conductive material.

[0099] The gate insulating film 65 is configured by, for example, silicon oxide (SiO), silicon nitride (SiN), or the like. In addition, for example, the gate insulating film 65 is formed using an insulating material such as Al2O3, HfO2, ZrO2, LaO2, HfSiO, Y2O3, or SiON. It is to be noted that the gate insulating film 65 may be constructed using another material.

[0100] The gate electrode 66 is formed using, for example, a metal material such as Au, Pt, Cu, Ti, W, Pd, TiN, TaN, TiAl, Bi, In, Al, Sc, Co, or Mo. The gate electrode 66 may be configured using another electrically-conductive material.

[0101] It is to be noted that the circuit element C1 may have a planar (Planer) structure, or may have a three-dimensional structure. The circuit element C1 may be a planar transistor, for example. In addition, the circuit element C1 may be an element of a vertical structure (e.g., vertical transistor).

[0102] As described above, in the imaging device 1 according to the present embodiment, some of the plurality of circuit elements included in the signal processing circuit 200 are provided in the wiring layers (the wiring layers 121 and 111, etc.). For example, the plurality of circuit elements constituting the signal processing circuit 200 is provided separately in the semiconductor layer 102 and the wiring layer 121. This makes it possible to reduce a chip area of the imaging device 1.

[0103] In the present embodiment, for example, at least some of the transistors of the signal processing circuit 200 are each provided as the thin-film transistor (TFT) in the wiring layer 121. In addition, for example, at least some of the capacitors of the signal processing circuit 200 are provided in the wiring layer 121. This makes it possible to reduce an occupied area (footprint) of the signal processing circuit 200.

[0104] In the imaging device, a load circuit of each pixel column tends to occupy a high percentage of the chip area. Accordingly, disposing the transistor Tr1 of the load circuit 30 for each pixel column in the wiring layer 121 enables the circuit area of the signal processing circuit 200 to be significantly reduced. This makes it possible to effectively reduce the chip area.

[0105] In addition, it is possible to increase an area of a region where another circuit element is disposed in the semiconductor layer 102. For example, it is possible to increase a size of the transistor used in the comparison circuit 50. It is possible to increase areas (a gate width, a gate length, etc.) of the transistors of the comparison circuit 50, e.g., the transistors Tr11 and Tr12 constituting the differential pair 55, thus making it possible to suppress noise mixture into a pixel signal. It becomes possible to suppress degradation in image quality of an image.

[0106] Further, it is possible, in the imaging device 1, to electrically couple a circuit element provided in the wiring layers 121 and 111 and a circuit element provided in the semiconductor layer 102 to each other by wiring of the wiring layers 121 and 111. This makes it possible to improve layout flexibility.

[0107] Figs. 6A and 6B are each an explanatory diagram of a configuration example of the imaging device according to the embodiment. The signal processing circuit 200 may include, for example, the circuit element C1 provided in the wiring layer 121 and a circuit element C2 provided on the side of the surface 12S1 of the semiconductor layer 102. The circuit element C1 and the circuit element C2 are each, for example, a transistor, a capacitor, a resistance element, or the like.

[0108] As in the example illustrated in Fig. 6A, for example, the circuit element C1 is provided above the circuit element C2. The circuit element C1 may be provided, in a plan view, to overlap at least a portion of the circuit element C2. In the example illustrated in Fig. 6A, the circuit element C1 is provided, in a plan view, to allow the electrode 62a of the circuit element C1 to overlap a gate electrode of the circuit element C2.

[0109] The electrode 62a of the circuit element C1 is positioned above the gate of the circuit element C2. It is to be noted that the circuit element C1 may be provided to allow the electrode 62b of the circuit element C1 to be positioned above the gate of the circuit element C2. The electrode 62a of the circuit element C1 may be electrically coupled to the gate of the circuit element C2 through a via (also referred to as a contact), for example.

[0110] The via coupled to the circuit elements C1 and C2 is formed using, for example, a metal material such as Au (gold), Pt (platinum), Pd (palladium), copper (Cu), titanium (Ti), tungsten (W), titanium nitride (TiN), tantalum nitride (TaN), titanium aluminum (TiAl), bismuth (Bi), indium (In), aluminum (Al), scandium (Sc), cobalt (Co), or molybdenum (Mo). It is to be noted that the via may be configured using another electrically-conductive material.

[0111] As an example, as illustrated in Fig. 6B, the circuit element C1 may be configured as the transistor Tr1 of the load circuit 30. In addition, the circuit element C2 may be configured as the transistor Tr11 (or the transistor Tr12) of the differential pair 55 of the comparison circuit 50. For example, the electrode 62a that serves as a drain of the transistor Tr1 is electrically coupled to the gate electrode of the transistor Tr11. It is to be noted that, in the wiring layer 121, the capacitor 41 (or the capacitor 42) may be provided between the transistor Tr1 and the transistor Tr11 (or the transistor Tr12).

[0112] Figs. 7A and 7B are each an explanatory diagram of another configuration example of the imaging device according to the embodiment. The circuit element C1 and the circuit element C2 of the signal processing circuit 200 may have structures illustrated in Fig. 7A. In the example illustrated in Fig. 7A, the electrode 62a of the circuit element C1 is provided above a source or a drain of the circuit element C2. The semiconductor region 61 and the gate electrode 66 of the circuit element C1 are positioned above the gate of the circuit element C2. The electrode 62a of the circuit element C1 is electrically coupled to the drain or the source of the circuit element C2.

[0113] As an example, as illustrated in Fig. 7B, the circuit element C1 may be configured as the transistor Tr1 of the load circuit 30. In addition, the circuit element C2 may be configured as the transistor Tr31 of the switch SW11. For example, the electrode 62a that serves as the drain of the transistor Tr1 is electrically coupled to a drain or a source of the transistor Tr31.

[0114] Figs. 8A and 8B are each an explanatory diagram of another configuration example of the imaging device according to the embodiment. In the example illustrated in Fig. 8A, the electrode 62a of the circuit element C1 is provided above the source or the drain of the circuit element C2. It is to be noted that the electrode 62b of the circuit element C1 may be provided above the source or the drain of the circuit element C2. For example, the electrode 62a of the circuit element C1 is electrically coupled to the drain or the source of the circuit element C2.

[0115] As an example, as illustrated in Fig. 8B, the circuit element C1 may be configured as the transistor Tr1 of the load circuit 30. In addition, the circuit element C2 may be configured as the transistor Tr31 of the switch SW11. For example, the electrode 62a that serves as the drain of the transistor Tr1 is electrically coupled to a drain or a source of the transistor Tr31.

[0116] Figs. 9A and 9B are each an explanatory diagram of another configuration example of the imaging device according to the embodiment. In the example illustrated in Fig. 9A, a portion of the gate electrode 66 of the circuit element C1 is provided above the gate electrode of the circuit element C2. The gate electrode 66 of the circuit element C1 is electrically coupled to the gate electrode of the circuit element C2 through the via.

[0117] As an example, as illustrated in Fig. 9B, the circuit element C1 may be configured as the capacitor 41. In addition, the circuit element C2 may be configured as the transistor Tr11 of the comparison circuit 50. For example, one electrode (terminal) of the capacitor 41 is electrically coupled to the gate electrode of the transistor Tr11. It is to be noted that the circuit element C1 may be configured as the capacitor 42, and the circuit element C2 may be configured as the transistor Tr12.

[0118] Figs. 10A and 10B are each an explanatory diagram of another configuration example of the imaging device according to the embodiment. In the example illustrated in Fig. 10A, a portion of the gate electrode 66 of the circuit element C1 is provided above the source or the drain of the circuit element C2. The gate electrode 66 of the circuit element C1 is electrically coupled to the source or the drain of the circuit element C2 through the via.

[0119] As an example, as illustrated in Fig. 10B, the circuit element C1 may be configured as the capacitor 41. In addition, the circuit element C2 may be configured as the transistor Tr31 of the switch SW11. For example, one electrode of the capacitor 41 is electrically coupled to the source or the drain of the transistor Tr31. It is to be noted that the circuit element C1 may be configured as the capacitor 42, and the circuit element C2 may be configured as the transistor Tr32.Workings and Effects

[0120] The photodetector according to the present embodiment includes: a first substrate (substrate 201) including a photoelectric conversion element (photoelectric conversion section 12) that photoelectrically converts light and at least a portion of a readout circuit (readout circuit 20) configured to output a first signal based on electric charge converted by the photoelectric conversion element; a second substrate (substrate 202) including at least a portion of a signal processing circuit (signal processing circuit 200) configured to execute signal processing on the first signal, the second substrate being stacked on the first substrate; and a wiring layer (wiring layer 121 or wiring layer 111) provided in the first substrate or the second substrate. The signal processing circuit includes a first element (e.g., circuit element C1) provided in the wiring layer.

[0121] In the photodetector (imaging device 1) according to the present embodiment, at least some of the circuit elements of the signal processing circuit 200 are provided in the wiring layer 121 (or the wiring layer 111). This makes it possible, in the imaging device 1, to reduce a circuit area of the signal processing circuit 200. It becomes possible to achieve a photodetector that enables a reduction in the circuit area.

[0122] Next, description is given of modification examples of the present disclosure. Hereinafter, components similar to those in the foregoing embodiment are denoted by the same reference numerals, and descriptions thereof are omitted as appropriate. <2. Modification Examples> (2-1. Modification Example 1)

[0123] Fig. 11 is an explanatory diagram of a configuration example of an imaging device according to Modification Example 1 of the present disclosure. The circuit elements of the signal processing circuit 200 may be provided separately in a plurality of wiring layers (tiers). In the example illustrated in Fig. 11, the wiring layer 121 is a multilayer wiring layer, and includes a wiring layer 221 and a wiring layer 222.

[0124] The wiring layer 221 and the wiring layer 222 each include, for example, a conductive film and an insulating film, and includes a plurality of pieces of wiring, a via, an interlayer insulating film, and the like. In the wiring layer 121 (multilayer wiring layer), for example, there may be formed, as a thin-film transistor, at least some of transistors of the signal processing circuit 200 described above.

[0125] Some of the plurality of circuit elements of the signal processing circuit 200 may be provided separately in the wiring layer 221 and the wiring layer 222. In the example illustrated in Fig. 11, the wiring layer 221 is provided with a circuit element C1a, and the wiring layer 222 is provided with a circuit element C1b. The circuit element C1a and the circuit element C1b may each be configured as a thin-film transistor, for example. At least one of the circuit element C1a or the circuit element C1b may be a capacitor or a resistance element.

[0126] As illustrated in Fig. 11, the circuit element C1a is positioned in the wiring layer 221, and is provided in a tier different from that of the circuit element C2. In addition, the circuit element C1b is positioned in the wiring layer 222, and is provided in a tier different from those of the circuit element C1a and the circuit element C2. It can be said that the circuit element C1b is provided in an upper layer part of the wiring layer 121 which is the multilayer wiring layer and that the circuit element C1a is provided in a lower layer part of the wiring layer 121.

[0127] As described above, at least some of the circuit elements of the signal processing circuit 200 are disposed in the wiring layer 121. In the case of the present modification example, transistors, capacitors, or the like of the signal processing circuit 200 are disposed, for example, as the circuit element C1a or the circuit element C1b, in the wiring layer 221 and the wiring layer 222. This enables the imaging device 1 to effectively reduce the circuit area.

[0128] Fig. 12 is an explanatory diagram of another configuration example of the imaging device according to Modification Example 1. In the example illustrated in Fig. 12, the wiring layer 121 includes the wiring layer 221, the wiring layer 222, and a wiring layer 223. The signal processing circuit 200 includes the circuit element C1a provided in the wiring layer 221 and the circuit element C1b provided in the wiring layer 222.

[0129] In addition, the signal processing circuit 200 may include a circuit element C1c provided in the wiring layer 223. The circuit element C1a, the circuit element C1b, and the circuit element C1c may be formed in different tiers, and may be provided to be stacked on each other. It is to be noted that the signal processing circuit 200 may include the circuit elements such as transistors and capacitors only in one or two of the wiring layer 221 to the wiring layer 223. (2-2. Modification Example 2)

[0130] The description has been given, in the foregoing embodiment and modification example, of the configuration examples of the photodetector; however, the configuration of the photodetector (imaging device) is not limited to the examples described above. For example, the thin-film transistor provided in the wiring layer may be a vertical transistor. The thin-film transistor may be, for example, a gate-all-around (GAA: Gate All Around) TFT having a structure in which a gate is provided to surround a periphery of a channel region.

[0131] Some of the circuit elements of the signal processing circuit 200 may be provided in the wiring layer 121, or may be provided in the wiring layer 111. In addition, the plurality of circuit elements of the signal processing circuit 200 may be disposed separately in the wiring layer 121 and the wiring layer 111. Each transistor (such as the transistor AMP, SEL, or RST) of the readout circuit 20 of the pixel P may be disposed as a thin-film transistor in the wiring layer 111.

[0132] Fig. 13 is an explanatory diagram of a configuration example of an imaging device according to Modification Example 2. The imaging device 1 may include the circuit element C1 provided in the wiring layer 121 and a circuit element C3 provided in the wiring layer 111. The circuit element C3 may be configured as a circuit element of the signal processing circuit 200 or as a circuit element of the readout circuit 20.

[0133] At least some of the transistors of the pixel P may be provided as the circuit element C3 in the wiring layer 111. For example, the transistor TG, the transistor AMP, the transistor SEL, the transistor RST, the switching transistor, and the like may be provided separately in the semiconductor layer 101 and the wiring layer 111. It is possible for the imaging device 1 to have a structure that is advantageous to miniaturization. <3. Application Example>

[0134] The above-described imaging device 1 or the like is applicable, for example, to any type of electronic apparatus with an imaging function including a camera system such as a digital still camera or a video camera, a mobile phone having an imaging function, and the like. Fig. 14 illustrates a schematic configuration of an electronic apparatus 1000.

[0135] The electronic apparatus 1000 includes, for example, a lens group 1001, the imaging device 1, a DSP (Digital Signal Processor) circuit 1002, a frame memory 1003, a display unit 1004, a recording unit 1005, an operation unit 1006, and a power supply unit 1007. They are coupled to each other via a bus line 1008.

[0136] The lens group 1001 takes in incident light (image light) from a subject, and forms an image on an imaging surface of the imaging device 1. The imaging device 1 converts the amount of incident light formed as an image on the imaging surface by the lens group 1001 into electric signals on a pixel-by-pixel basis, and supplies the DSP circuit 1002 with the electric signals as pixel signals.

[0137] The DSP circuit 1002 is a signal processing circuit that processes signals supplied from the imaging device 1. The DSP circuit 1002 outputs image data obtained by processing the signals from the imaging device 1. The frame memory 1003 temporarily holds the image data processed by the DSP circuit 1002 on a frame-by-frame basis.

[0138] The display unit 1004 includes, for example, a panel-type display device such as a liquid crystal panel or an organic EL (Electro Luminescence) panel, and records image data of a moving image or a still image captured by the imaging device 1 in a recording medium such as a semiconductor memory or a hard disk.

[0139] The operation unit 1006 outputs an operation signal for a variety of functions of the electronic apparatus 1000 in accordance with an operation by a user. The power supply unit 1007 appropriately supplies the DSP circuit 1002, the frame memory 1003, the display unit 1004, the recording unit 1005, and the operation unit 1006 with various kinds of power for operations of these supply targets. <4. Practical Application Examples> (Example of Practical Application to Mobile Body)

[0140] The technology (the present technology) according to the present disclosure is applicable to a variety of products. For example, the technology according to the present disclosure may be achieved as a device mounted on any type of mobile body such as an automobile, an electric vehicle, a hybrid electric vehicle, a motorcycle, a bicycle, a personal mobility, an aircraft, a drone, a vessel, or a robot.

[0141] Fig. 15 is a block diagram depicting an example of schematic configuration of a vehicle control system as an example of a mobile body control system to which the technology according to an embodiment of the present disclosure can be applied.

[0142] The vehicle control system 12000 includes a plurality of electronic control units connected to each other via a communication network 12001. In the example depicted in Fig. 15, the vehicle control system 12000 includes a driving system control unit 12010, a body system control unit 12020, an outside-vehicle information detecting unit 12030, an in-vehicle information detecting unit 12040, and an integrated control unit 12050. In addition, a microcomputer 12051, a sound / image output section 12052, and a vehicle-mounted network interface (I / F) 12053 are illustrated as a functional configuration of the integrated control unit 12050.

[0143] The driving system control unit 12010 controls the operation of devices related to the driving system of the vehicle in accordance with various kinds of programs. For example, the driving system control unit 12010 functions as a control device for a driving force generating device for generating the driving force of the vehicle, such as an internal combustion engine, a driving motor, or the like, a driving force transmitting mechanism for transmitting the driving force to wheels, a steering mechanism for adjusting the steering angle of the vehicle, a braking device for generating the braking force of the vehicle, and the like.

[0144] The body system control unit 12020 controls the operation of various kinds of devices provided to a vehicle body in accordance with various kinds of programs. For example, the body system control unit 12020 functions as a control device for a keyless entry system, a smart key system, a power window device, or various kinds of lamps such as a headlamp, a backup lamp, a brake lamp, a turn signal, a fog lamp, or the like. In this case, radio waves transmitted from a mobile device as an alternative to a key or signals of various kinds of switches can be input to the body system control unit 12020. The body system control unit 12020 receives these input radio waves or signals, and controls a door lock device, the power window device, the lamps, or the like of the vehicle.

[0145] The outside-vehicle information detecting unit 12030 detects information about the outside of the vehicle including the vehicle control system 12000. For example, the outside-vehicle information detecting unit 12030 is connected with an imaging section 12031. The outside-vehicle information detecting unit 12030 makes the imaging section 12031 image an image of the outside of the vehicle, and receives the imaged image. On the basis of the received image, the outside-vehicle information detecting unit 12030 may perform processing of detecting an object such as a human, a vehicle, an obstacle, a sign, a character on a road surface, or the like, or processing of detecting a distance thereto.

[0146] The imaging section 12031 is an optical sensor that receives light, and which outputs an electric signal corresponding to a received light amount of the light. The imaging section 12031 can output the electric signal as an image, or can output the electric signal as information about a measured distance. In addition, the light received by the imaging section 12031 may be visible light, or may be invisible light such as infrared rays or the like.

[0147] The in-vehicle information detecting unit 12040 detects information about the inside of the vehicle. The in-vehicle information detecting unit 12040 is, for example, connected with a driver state detecting section 12041 that detects the state of a driver. The driver state detecting section 12041, for example, includes a camera that images the driver. On the basis of detection information input from the driver state detecting section 12041, the in-vehicle information detecting unit 12040 may calculate a degree of fatigue of the driver or a degree of concentration of the driver, or may determine whether the driver is dozing.

[0148] The microcomputer 12051 can calculate a control target value for the driving force generating device, the steering mechanism, or the braking device on the basis of the information about the inside or outside of the vehicle which information is obtained by the outside-vehicle information detecting unit 12030 or the in-vehicle information detecting unit 12040, and output a control command to the driving system control unit 12010. For example, the microcomputer 12051 can perform cooperative control intended to implement functions of an advanced driver assistance system (ADAS) which functions include collision avoidance or shock mitigation for the vehicle, following driving based on a following distance, vehicle speed maintaining driving, a warning of collision of the vehicle, a warning of deviation of the vehicle from a lane, or the like.

[0149] In addition, the microcomputer 12051 can perform cooperative control intended for automated driving, which makes the vehicle to travel automatedly without depending on the operation of the driver, or the like, by controlling the driving force generating device, the steering mechanism, the braking device, or the like on the basis of the information about the outside or inside of the vehicle which information is obtained by the outside-vehicle information detecting unit 12030 or the in-vehicle information detecting unit 12040.

[0150] In addition, the microcomputer 12051 can output a control command to the body system control unit 12020 on the basis of the information about the outside of the vehicle which information is obtained by the outside-vehicle information detecting unit 12030. For example, the microcomputer 12051 can perform cooperative control intended to prevent (or alternatively reduce the possibility of) a glare by controlling the headlamp so as to change from a high beam to a low beam, for example, in accordance with the position of a preceding vehicle or an oncoming vehicle detected by the outside-vehicle information detecting unit 12030.

[0151] The sound / image output section 12052 transmits an output signal of at least one of a sound and an image to an output device capable of visually or auditorily notifying information to an occupant of the vehicle or the outside of the vehicle. In the example of Fig. 15, an audio speaker 12061, a display section 12062, and an instrument panel 12063 are illustrated as the output device. The display section 12062 may, for example, include at least one of an on-board display and a head-up display.

[0152] Fig. 16 is a diagram depicting an example of the installation position of the imaging section 12031.

[0153] In Fig. 16, the imaging section 12031 includes imaging sections 12101, 12102, 12103, 12104, and 12105.

[0154] The imaging sections 12101, 12102, 12103, 12104, and 12105 are, for example, disposed at positions on a front nose, sideview mirrors, a rear bumper, and a back door of the vehicle 12100 as well as a position on an upper portion of a windshield within the interior of the vehicle. The imaging section 12101 provided to the front nose and the imaging section 12105 provided to the upper portion of the windshield within the interior of the vehicle obtain mainly an image of the front of the vehicle 12100. The imaging sections 12102 and 12103 provided to the sideview mirrors obtain mainly an image of the sides of the vehicle 12100. The imaging section 12104 provided to the rear bumper or the back door obtains mainly an image of the rear of the vehicle 12100. The imaging section 12105 provided to the upper portion of the windshield within the interior of the vehicle is used mainly to detect a preceding vehicle, a pedestrian, an obstacle, a signal, a traffic sign, a lane, or the like.

[0155] Incidentally, Fig. 16 depicts an example of photographing ranges of the imaging sections 12101 to 12104. An imaging range 12111 represents the imaging range of the imaging section 12101 provided to the front nose. Imaging ranges 12112 and 12113 respectively represent the imaging ranges of the imaging sections 12102 and 12103 provided to the sideview mirrors. An imaging range 12114 represents the imaging range of the imaging section 12104 provided to the rear bumper or the back door. A bird’s-eye image of the vehicle 12100 as viewed from above is obtained by superimposing image data imaged by the imaging sections 12101 to 12104, for example.

[0156] At least one of the imaging sections 12101 to 12104 may have a function of obtaining distance information. For example, at least one of the imaging sections 12101 to 12104 may be a stereo camera constituted of a plurality of imaging elements, or may be an imaging element having pixels for phase difference detection.

[0157] For example, the microcomputer 12051 can determine a distance to each three-dimensional object within the imaging ranges 12111 to 12114 and a temporal change in the distance (relative speed with respect to the vehicle 12100) on the basis of the distance information obtained from the imaging sections 12101 to 12104, and thereby extract, as a preceding vehicle, a nearest three-dimensional object in particular that is present on a traveling path of the vehicle 12100 and which travels in substantially the same direction as the vehicle 12100 at a predetermined speed (for example, equal to or more than 0 km / hour). Further, the microcomputer 12051 can set a following distance to be maintained in front of a preceding vehicle in advance, and perform automatic brake control (including following stop control), automatic acceleration control (including following start control), or the like. It is thus possible to perform cooperative control intended for automated driving that makes the vehicle travel automatedly without depending on the operation of the driver or the like.

[0158] For example, the microcomputer 12051 can classify three-dimensional object data on three-dimensional objects into three-dimensional object data of a two-wheeled vehicle, a standard-sized vehicle, a large-sized vehicle, a pedestrian, a utility pole, and other three-dimensional objects on the basis of the distance information obtained from the imaging sections 12101 to 12104, extract the classified three-dimensional object data, and use the extracted three-dimensional object data for automatic avoidance of an obstacle. For example, the microcomputer 12051 identifies obstacles around the vehicle 12100 as obstacles that the driver of the vehicle 12100 can recognize visually and obstacles that are difficult for the driver of the vehicle 12100 to recognize visually. Then, the microcomputer 12051 determines a collision risk indicating a risk of collision with each obstacle. In a situation in which the collision risk is equal to or higher than a set value and there is thus a possibility of collision, the microcomputer 12051 outputs a warning to the driver via the audio speaker 12061 or the display section 12062, and performs forced deceleration or avoidance steering via the driving system control unit 12010. The microcomputer 12051 can thereby assist in driving to avoid collision.

[0159] At least one of the imaging sections 12101 to 12104 may be an infrared camera that detects infrared rays. The microcomputer 12051 can, for example, recognize a pedestrian by determining whether or not there is a pedestrian in imaged images of the imaging sections 12101 to 12104. Such recognition of a pedestrian is, for example, performed by a procedure of extracting characteristic points in the imaged images of the imaging sections 12101 to 12104 as infrared cameras and a procedure of determining whether or not it is the pedestrian by performing pattern matching processing on a series of characteristic points representing the contour of the object. When the microcomputer 12051 determines that there is a pedestrian in the imaged images of the imaging sections 12101 to 12104, and thus recognizes the pedestrian, the sound / image output section 12052 controls the display section 12062 so that a square contour line for emphasis is displayed so as to be superimposed on the recognized pedestrian. The sound / image output section 12052 may also control the display section 12062 so that an icon or the like representing the pedestrian is displayed at a desired position.

[0160] The description has been given hereinabove of the mobile body control system to which the technology according to an embodiment of the present disclosure is applicable. The technology according to an embodiment of the present disclosure is applicable to the imaging section 12031, for example, of the configurations described above. Specifically, for example, the imaging device 1 or the like can be applied to the imaging section 12031. Applying the technology according to an embodiment of the present disclosure to the imaging section 12031 enables obtainment of a photographed image having high definition. It becomes possible to perform highly accurate control utilizing the photographed image in the mobile body control system. (Example of Practical Application to Endoscopic Surgery System)

[0161] The technology according to an embodiment of the present disclosure (present technology) is applicable to various products. For example, the technology according to an embodiment of the present disclosure may be applied to an endoscopic surgery system.

[0162] Fig. 17 is a view depicting an example of a schematic configuration of an endoscopic surgery system to which the technology according to an embodiment of the present disclosure (present technology) can be applied.

[0163] In Fig. 17, a state is illustrated in which a surgeon (medical doctor) 11131 is using an endoscopic surgery system 11000 to perform surgery for a patient 11132 on a patient bed 11133. As depicted, the endoscopic surgery system 11000 includes an endoscope 11100, other surgical tools 11110 such as a pneumoperitoneum tube 11111 and an energy device 11112, a supporting arm apparatus 11120 which supports the endoscope 11100 thereon, and a cart 11200 on which various apparatus for endoscopic surgery are mounted.

[0164] The endoscope 11100 includes a lens barrel 11101 having a region of a predetermined length from a distal end thereof to be inserted into a body cavity of the patient 11132, and a camera head 11102 connected to a proximal end of the lens barrel 11101. In the example depicted, the endoscope 11100 is depicted which includes as a rigid endoscope having the lens barrel 11101 of the hard type. However, the endoscope 11100 may otherwise be included as a flexible endoscope having the lens barrel 11101 of the flexible type.

[0165] The lens barrel 11101 has, at a distal end thereof, an opening in which an objective lens is fitted. A light source apparatus 11203 is connected to the endoscope 11100 such that light generated by the light source apparatus 11203 is introduced to a distal end of the lens barrel 11101 by a light guide extending in the inside of the lens barrel 11101 and is irradiated toward an observation target in a body cavity of the patient 11132 through the objective lens. It is to be noted that the endoscope 11100 may be a forward-viewing endoscope or may be an oblique-viewing endoscope or a side-viewing endoscope.

[0166] An optical system and an image pickup element are provided in the inside of the camera head 11102 such that reflected light (observation light) from the observation target is condensed on the image pickup element by the optical system. The observation light is photo-electrically converted by the image pickup element to generate an electric signal corresponding to the observation light, namely, an image signal corresponding to an observation image. The image signal is transmitted as RAW data to a CCU 11201.

[0167] The CCU 11201 includes a central processing unit (CPU), a graphics processing unit (GPU) or the like and integrally controls operation of the endoscope 11100 and a display apparatus 11202. Further, the CCU 11201 receives an image signal from the camera head 11102 and performs, for the image signal, various image processes for displaying an image based on the image signal such as, for example, a development process (demosaic process).

[0168] The display apparatus 11202 displays thereon an image based on an image signal, for which the image processes have been performed by the CCU 11201, under the control of the CCU 11201.

[0169] The light source apparatus 11203 includes a light source such as, for example, a light emitting diode (LED) and supplies irradiation light upon imaging of a surgical region to the endoscope 11100.

[0170] An inputting apparatus 11204 is an input interface for the endoscopic surgery system 11000. A user can perform inputting of various kinds of information or instruction inputting to the endoscopic surgery system 11000 through the inputting apparatus 11204. For example, the user would input an instruction or a like to change an image pickup condition (type of irradiation light, magnification, focal distance or the like) by the endoscope 11100.

[0171] A treatment tool controlling apparatus 11205 controls driving of the energy device 11112 for cautery or incision of a tissue, sealing of a blood vessel or the like. A pneumoperitoneum apparatus 11206 feeds gas into a body cavity of the patient 11132 through the pneumoperitoneum tube 11111 to inflate the body cavity in order to secure the field of view of the endoscope 11100 and secure the working space for the surgeon. A recorder 11207 is an apparatus capable of recording various kinds of information relating to surgery. A printer 11208 is an apparatus capable of printing various kinds of information relating to surgery in various forms such as a text, an image or a graph.

[0172] It is to be noted that the light source apparatus 11203 which supplies irradiation light when a surgical region is to be imaged to the endoscope 11100 may include a white light source which includes, for example, an LED, a laser light source or a combination of them. Where a white light source includes a combination of red, green, and blue (RGB) laser light sources, since the output intensity and the output timing can be controlled with a high degree of accuracy for each color (each wavelength), adjustment of the white balance of a picked up image can be performed by the light source apparatus 11203. Further, in this case, if laser beams from the respective RGB laser light sources are irradiated time-divisionally on an observation target and driving of the image pickup elements of the camera head 11102 are controlled in synchronism with the irradiation timings. Then images individually corresponding to the R, G and B colors can be also picked up time-divisionally. According to this method, a color image can be obtained even if color filters are not provided for the image pickup element.

[0173] Further, the light source apparatus 11203 may be controlled such that the intensity of light to be outputted is changed for each predetermined time. By controlling driving of the image pickup element of the camera head 11102 in synchronism with the timing of the change of the intensity of light to acquire images time-divisionally and synthesizing the images, an image of a high dynamic range free from underexposed blocked up shadows and overexposed highlights can be created.

[0174] Further, the light source apparatus 11203 may be configured to supply light of a predetermined wavelength band ready for special light observation. In special light observation, for example, by utilizing the wavelength dependency of absorption of light in a body tissue to irradiate light of a narrow band in comparison with irradiation light upon ordinary observation (namely, white light), narrow band observation (narrow band imaging) of imaging a predetermined tissue such as a blood vessel of a superficial portion of the mucous membrane or the like in a high contrast is performed. Alternatively, in special light observation, fluorescent observation for obtaining an image from fluorescent light generated by irradiation of excitation light may be performed. In fluorescent observation, it is possible to perform observation of fluorescent light from a body tissue by irradiating excitation light on the body tissue (autofluorescence observation) or to obtain a fluorescent light image by locally injecting a reagent such as indocyanine green (ICG) into a body tissue and irradiating excitation light corresponding to a fluorescent light wavelength of the reagent upon the body tissue. The light source apparatus 11203 can be configured to supply such narrow-band light and / or excitation light suitable for special light observation as described above.

[0175] Fig. 18 is a block diagram depicting an example of a functional configuration of the camera head 11102 and the CCU 11201 depicted in Fig. 17.

[0176] The camera head 11102 includes a lens unit 11401, an image pickup unit 11402, a driving unit 11403, a communication unit 11404 and a camera head controlling unit 11405. The CCU 11201 includes a communication unit 11411, an image processing unit 11412 and a control unit 11413. The camera head 11102 and the CCU 11201 are connected for communication to each other by a transmission cable 11400.

[0177] The lens unit 11401 is an optical system, provided at a connecting location to the lens barrel 11101. Observation light taken in from a distal end of the lens barrel 11101 is guided to the camera head 11102 and introduced into the lens unit 11401. The lens unit 11401 includes a combination of a plurality of lenses including a zoom lens and a focusing lens.

[0178] The number of image pickup elements which is included by the image pickup unit 11402 may be one (single-plate type) or a plural number (multi-plate type). Where the image pickup unit 11402 is configured as that of the multi-plate type, for example, image signals corresponding to respective R, G and B are generated by the image pickup elements, and the image signals may be synthesized to obtain a color image. The image pickup unit 11402 may also be configured so as to have a pair of image pickup elements for acquiring respective image signals for the right eye and the left eye ready for three dimensional (3D) display. If 3D display is performed, then the depth of a living body tissue in a surgical region can be comprehended more accurately by the surgeon 11131. It is to be noted that, where the image pickup unit 11402 is configured as that of stereoscopic type, a plurality of systems of lens units 11401 are provided corresponding to the individual image pickup elements.

[0179] Further, the image pickup unit 11402 may not necessarily be provided on the camera head 11102. For example, the image pickup unit 11402 may be provided immediately behind the objective lens in the inside of the lens barrel 11101.

[0180] The driving unit 11403 includes an actuator and moves the zoom lens and the focusing lens of the lens unit 11401 by a predetermined distance along an optical axis under the control of the camera head controlling unit 11405. Consequently, the magnification and the focal point of a picked up image by the image pickup unit 11402 can be adjusted suitably.

[0181] The communication unit 11404 includes a communication apparatus for transmitting and receiving various kinds of information to and from the CCU 11201. The communication unit 11404 transmits an image signal acquired from the image pickup unit 11402 as RAW data to the CCU 11201 through the transmission cable 11400.

[0182] In addition, the communication unit 11404 receives a control signal for controlling driving of the camera head 11102 from the CCU 11201 and supplies the control signal to the camera head controlling unit 11405. The control signal includes information relating to image pickup conditions such as, for example, information that a frame rate of a picked up image is designated, information that an exposure value upon image picking up is designated and / or information that a magnification and a focal point of a picked up image are designated.

[0183] It is to be noted that the image pickup conditions such as the frame rate, exposure value, magnification or focal point may be designated by the user or may be set automatically by the control unit 11413 of the CCU 11201 on the basis of an acquired image signal. In the latter case, an auto exposure (AE) function, an auto focus (AF) function and an auto white balance (AWB) function are incorporated in the endoscope 11100.

[0184] The camera head controlling unit 11405 controls driving of the camera head 11102 on the basis of a control signal from the CCU 11201 received through the communication unit 11404.

[0185] The communication unit 11411 includes a communication apparatus for transmitting and receiving various kinds of information to and from the camera head 11102. The communication unit 11411 receives an image signal transmitted thereto from the camera head 11102 through the transmission cable 11400.

[0186] Further, the communication unit 11411 transmits a control signal for controlling driving of the camera head 11102 to the camera head 11102. The image signal and the control signal can be transmitted by electrical communication, optical communication or the like.

[0187] The image processing unit 11412 performs various image processes for an image signal in the form of RAW data transmitted thereto from the camera head 11102.

[0188] The control unit 11413 performs various kinds of control relating to image picking up of a surgical region or the like by the endoscope 11100 and display of a picked up image obtained by image picking up of the surgical region or the like. For example, the control unit 11413 creates a control signal for controlling driving of the camera head 11102.

[0189] Further, the control unit 11413 controls, on the basis of an image signal for which image processes have been performed by the image processing unit 11412, the display apparatus 11202 to display a picked up image in which the surgical region or the like is imaged. Thereupon, the control unit 11413 may recognize various objects in the picked up image using various image recognition technologies. For example, the control unit 11413 can recognize a surgical tool such as forceps, a particular living body region, bleeding, mist when the energy device 11112 is used and so forth by detecting the shape, color and so forth of edges of objects included in a picked up image. The control unit 11413 may cause, when it controls the display apparatus 11202 to display a picked up image, various kinds of surgery supporting information to be displayed in an overlapping manner with an image of the surgical region using a result of the recognition. Where surgery supporting information is displayed in an overlapping manner and presented to the surgeon 11131, the burden on the surgeon 11131 can be reduced and the surgeon 11131 can proceed with the surgery with certainty.

[0190] The transmission cable 11400 which connects the camera head 11102 and the CCU 11201 to each other is an electric signal cable ready for communication of an electric signal, an optical fiber ready for optical communication or a composite cable ready for both of electrical and optical communications.

[0191] Here, while, in the example depicted, communication is performed by wired communication using the transmission cable 11400, the communication between the camera head 11102 and the CCU 11201 may be performed by wireless communication.

[0192] The description has been given hereinabove of one example of the endoscopic surgery system, to which the technology according to an embodiment of the present disclosure is applicable. The technology according to an embodiment of the present disclosure is suitably applicable to, for example, the image pickup unit 11402 provided in the camera head 11102 of the endoscope 11100 of the configurations described above. Applying the technology according to an embodiment of the present disclosure to the image pickup unit 11402 makes it possible to provide the endoscope 11100 having high definition.

[0193] Although the description has been given hereinabove of the present disclosure with reference to the embodiment, the modification examples, the application example, and the practical application examples, the present technology is not limited to the foregoing embodiment and the like, and may be modified in a wide variety of ways. For example, although the foregoing modification examples have been described as modification examples of the foregoing embodiments, the configurations of the respective modification examples may be combined as appropriate.

[0194] In the foregoing embodiments and the like, the imaging device has been exemplified for description. However, it is sufficient for the photodetector of the present disclosure to be, for example, a device that receives incident light and converts the light into electric charge. A signal to be outputted may be a signal of image information or a signal of information on a measured distance. The photodetector (imaging device) is applicable to an image sensor, a distance measurement sensor, or the like. It is to be noted that the present disclosure is not limited to a back side illumination image sensor, and is also applicable to a front side illumination image sensor.

[0195] The photodetector according to the present disclosure is also applicable as a distance measurement sensor that enables distance measurement of a TOF (Time Of Flight) method. The photodetector (imaging device) is also applicable as a sensor that is able to detect an event, e.g., an event-driven sensor (referred to as EVS (Event Vision Sensor), EDS (Event Driven Sensor), DVS (Dynamic Vision Sensor), etc.).

[0196] The photodetector according to an embodiment of the present disclosure includes: a first substrate including a photoelectric conversion element and at least a portion of a readout circuit configured to output a first signal based on electric charge converted by the photoelectric conversion element; a second substrate including at least a portion of a signal processing circuit configured to execute signal processing on the first signal, the second substrate being stacked on the first substrate; and a wiring layer provided in the first substrate or the second substrate. The signal processing circuit includes a first element provided in the wiring layer. This makes it possible to achieve a photodetector that enables a reduction in a circuit area.

[0197] It is to be noted that the effects described herein are merely exemplary and are not limited to the description, and may further include other effects. In addition, the present disclosure may also have the following configurations. (1) A photodetector including: a first substrate including a photoelectric conversion element and at least a portion of a readout circuit, the photoelectric conversion element photoelectrically converting light, the readout circuit being configured to output a first signal based on electric charge converted by the photoelectric conversion element; a second substrate including at least a portion of a signal processing circuit configured to execute signal processing on the first signal, the second substrate being stacked on the first substrate; and a wiring layer provided in the first substrate or the second substrate, in which the signal processing circuit includes a first element provided in the wiring layer. (2) The photodetector according to (1), in which the signal processing circuit includes, as the first element, a first transistor provided in the wiring layer. (3) The photodetector according to (2), in which the first transistor includes a thin-film transistor. (4) The photodetector according to (2) or (3), in which the first transistor includes a channel region including an oxide semiconductor. (5) The photodetector according to any one of (2) to (4), in which the readout circuit is configured to output the first signal to a first signal line, and the first transistor is electrically coupled to the first signal line, and is configured to supply a current to the first signal line. (6) The photodetector according to any one of (2) to (5), in which the signal processing circuit includes an AD conversion circuit configured to convert the first signal into a digital signal. (7) The photodetector according to (6), in which the AD conversion circuit includes a comparison circuit including the first transistor, and the comparison circuit is configured to compare the first signal inputted to the first transistor and a reference signal with each other. (8) The photodetector according to (6) or (7), in which the AD conversion circuit includes a comparison circuit including a differential pair and the first transistor, and the first transistor is configured to supply a current to the differential pair. (9) The photodetector according to any one of (2) to (8), in which the first transistor is electrically coupled between the first signal line and a first potential line, the first signal line transmitting the first signal. (10) The photodetector according to (1), in which the signal processing circuit includes, as the first element, a capacitor provided in the wiring layer. (11) The photodetector according to (10), in which the signal processing circuit includes an AD conversion circuit configured to convert the first signal into a digital signal, and the AD conversion circuit includes a comparison circuit configured to compare the first signal inputted via the capacitor and a reference signal with each other. (12) The photodetector according to any one of (1) to (11), in which the first substrate includes a first semiconductor layer, the readout circuit includes a second transistor provided on a side of a first surface of the first semiconductor layer, and the first element is provided above the second transistor. (13) The photodetector according to (12), in which the readout circuit includes a floating diffusion, and a transfer transistor configured to transfer electric charge converted by the photoelectric conversion element to the floating diffusion, the second transistor is configured to output the first signal based on electric charge accumulated in the floating diffusion, and the first element is electrically coupled to the second transistor. (14) The photodetector according to any one of (1) to (13), in which the first substrate includes the first semiconductor layer and the wiring layer, the readout circuit includes the second transistor provided on the side of the first surface of the first semiconductor layer, and the first element is provided above the second transistor. (15) The photodetector according to any one of (1) to (14), in which the second substrate includes a second semiconductor layer, the signal processing circuit includes a third transistor provided on a side of a second surface of the second semiconductor layer, and the first element is provided above the third transistor. (16) The photodetector according to (15), in which the first element is electrically coupled to the third transistor. (17) The photodetector according to any one of (1) to (16), in which the second substrate includes the second semiconductor layer and the wiring layer, the signal processing circuit includes the third transistor provided on the side of the second surface of the second semiconductor layer, and the first element is provided above the third transistor. (18) The photodetector according to any one of (1) to (17), in which the signal processing circuit includes the first element and a second element provided in the wiring layer, and the first element and the second element are provided in tiers different from each other. (19) The photodetector according to (18), in which the first element is electrically coupled to the second element. (20) An electronic apparatus including: an optical system; and a photodetector that receives light transmitted through the optical system, the photodetector including a first substrate including a photoelectric conversion element and at least a portion of a readout circuit, the photoelectric conversion element photoelectrically converting light, the readout circuit being configured to output a first signal based on electric charge converted by the photoelectric conversion element, a second substrate including at least a portion of a signal processing circuit configured to execute signal processing on the first signal, the second substrate being stacked on the first substrate, and a wiring layer provided in the first substrate or the second substrate, in which the signal processing circuit includes a first element provided in the wiring layer. (21) A photodetector, comprising: a first substrate including a photoelectric conversion element and one or more components of a readout circuit, wherein the photoelectric conversion element is configured to photoelectrically convert light to an electric charge and the readout circuit is configured to output a signal based on the electric charge converted by the photoelectric conversion element; a second substrate including one or more components of a signal processing circuit, wherein the signal processing circuit is configured to process the signal and the second substrate is stacked on the first substrate; and a wiring layer provided in one of the first substrate and the second substrate, wherein the signal processing circuit includes one or more portions of a first transistor and a capacitor provided in the wiring layer. (22) The photodetector of (21), wherein the signal processing circuit includes the first transistor provided in the wiring layer. (23) The photodetector of (22), wherein the first transistor comprises a thin-film transistor. (24) The photodetector of (22), wherein the first transistor includes a channel region including an oxide semiconductor. (25) The photodetector of (22), wherein: the readout circuit is further configured to output the signal to a signal line, the first transistor is electrically coupled to the signal line, and the first transistor is configured to supply a current to the signal line. (26) The photodetector of (22), wherein the signal processing circuit includes an analog-to-digital (“AD”) conversion circuit configured to convert the signal into a digital signal. (27) The photodetector of (26), wherein: the AD conversion circuit includes a comparison circuit including the first transistor, and the comparison circuit is configured to compare the signal inputted to the first transistor with a reference signal. (28) The photodetector of (26), wherein: the AD conversion circuit includes a comparison circuit including a differential pair and the first transistor, and the first transistor is configured to supply a current to the differential pair. (29) The photodetector of (22), wherein the first transistor is electrically coupled between a signal line and a potential line, the signal line configured to transmit the signal. (30) The photodetector of (21), wherein the signal processing circuit includes the capacitor provided in the wiring layer. (31) The photodetector of (30), wherein the signal processing circuit includes an analog-to-digital (“AD”) conversion circuit configured to convert the signal into a digital signal, and the AD conversion circuit includes a comparison circuit configured to compare the signal inputted via the capacitor with a reference signal. (32) The photodetector of (21), wherein the first substrate includes a semiconductor layer, the readout circuit includes a second transistor, one or more portions of the second transistor are provided in the semiconductor layer, and the one of the first transistor and the capacitor is provided above the second transistor. (33) The photodetector of (32), wherein the readout circuit includes a floating diffusion and a transfer transistor, the transfer transistor configured to transfer the electric charge converted by the photoelectric conversion element to the floating diffusion, the second transistor is configured to output the signal based on electric charge accumulated in the floating diffusion, and the one of the first transistor and the capacitor is electrically coupled to the second transistor. (34) The photodetector of (21), wherein the signal processing circuit includes a semiconductor region and a gate electrode of the first transistor in the wiring layer. (35) The photodetector of (21), wherein the second substrate includes a semiconductor layer, the signal processing circuit includes a transistor provided on a surface of the semiconductor layer, and the one of the first transistor and the capacitor is provided above the transistor. (36) The photodetector of (35), wherein the one of the first transistor and the capacitor is electrically coupled to the transistor. (37) The photodetector of (21), wherein the one of the first transistor and the capacitor is above a semiconductor layer of the first substrate and below a semiconductor layer of the second substrate. (38) The photodetector of (21), wherein the signal processing circuit includes the first transistor and a second transistor provided in the wiring layer, and the first transistor and the second transistor are provided in different tiers of the wiring layer. (39) The photodetector of (38), wherein the first transistor is electrically coupled to the second transistor. (40) An electronic apparatus, comprising: an optical system; and a photodetector that receives light transmitted through the optical system, the photodetector including: a first substrate including a photoelectric conversion element and one or more components of a readout circuit, wherein the photoelectric conversion element is configured to photoelectrically convert light to an electric charge and the readout circuit is configured to output a signal based on the electric charge converted by the photoelectric conversion element, a second substrate including one or more components of a signal processing circuit, wherein the signal processing circuit is configured to process the signal and the second substrate is stacked on the first substrate, and a wiring layer provided in one of the first substrate and the second substrate, wherein the signal processing circuit includes one or more portions of a first transistor and a capacitor provided in the wiring layer.Reference Numerals List

[0198] 1 imaging device 12 photoelectric conversion section 20 readout circuit 101, 102 semiconductor layer 111, 121 wiring layer 200 signal processing circuit 201, 202 substrate

Claims

1. A photodetector, comprising: a first substrate including a photoelectric conversion element and one or more components of a readout circuit, wherein the photoelectric conversion element is configured to photoelectrically convert light to an electric charge and the readout circuit is configured to output a signal based on the electric charge converted by the photoelectric conversion element; a second substrate including one or more components of a signal processing circuit, wherein the signal processing circuit is configured to process the signal and the second substrate is stacked on the first substrate; and a wiring layer provided in one of the first substrate and the second substrate, wherein the signal processing circuit includes one or more portions of a first transistor and a capacitor provided in the wiring layer.

2. The photodetector according to claim 1, wherein the signal processing circuit includes the first transistor provided in the wiring layer.

3. The photodetector according to claim 2, wherein the first transistor comprises a thin-film transistor.

4. The photodetector according to claim 2, wherein the first transistor includes a channel region including an oxide semiconductor.

5. The photodetector according to claim 2, wherein: the readout circuit is further configured to output the signal to a signal line, the first transistor is electrically coupled to the signal line, and the first transistor is configured to supply a current to the signal line.

6. The photodetector according to claim 2, wherein the signal processing circuit includes an analog-to-digital (“AD”) conversion circuit configured to convert the signal into a digital signal.

7. The photodetector according to claim 6, wherein: the AD conversion circuit includes a comparison circuit including the first transistor, and the comparison circuit is configured to compare the signal inputted to the first transistor with a reference signal.

8. The photodetector according to claim 6, wherein: the AD conversion circuit includes a comparison circuit including a differential pair and the first transistor, and the first transistor is configured to supply a current to the differential pair.

9. The photodetector according to claim 2, wherein the first transistor is electrically coupled between a signal line and a potential line, the signal line configured to transmit the signal.

10. The photodetector according to claim 1, wherein the signal processing circuit includes the capacitor provided in the wiring layer.

11. The photodetector according to claim 10, wherein the signal processing circuit includes an analog-to-digital (“AD”) conversion circuit configured to convert the signal into a digital signal, and the AD conversion circuit includes a comparison circuit configured to compare the signal inputted via the capacitor with a reference signal.

12. The photodetector according to claim 1, wherein the first substrate includes a semiconductor layer, the readout circuit includes a second transistor, one or more portions of the second transistor are provided in the semiconductor layer, and the one of the first transistor and the capacitor is provided above the second transistor.

13. The photodetector according to claim 12, wherein the readout circuit includes a floating diffusion and a transfer transistor, the transfer transistor configured to transfer the electric charge converted by the photoelectric conversion element to the floating diffusion, the second transistor is configured to output the signal based on electric charge accumulated in the floating diffusion, and the one of the first transistor and the capacitor is electrically coupled to the second transistor.

14. The photodetector according to claim 1, wherein the signal processing circuit includes a semiconductor region and a gate electrode of the first transistor in the wiring layer.

15. The photodetector according to claim 1, wherein the second substrate includes a semiconductor layer, the signal processing circuit includes a transistor provided on a surface of the semiconductor layer, and the one of the first transistor and the capacitor is provided above the transistor.

16. The photodetector according to claim 15, wherein the one of the first transistor and the capacitor is electrically coupled to the transistor.

17. The photodetector according to claim 1, wherein the one of the first transistor and the capacitor is above a semiconductor layer of the first substrate and below a semiconductor layer of the second substrate.

18. The photodetector according to claim 1, wherein the signal processing circuit includes the first transistor and a second transistor provided in the wiring layer, and the first transistor and the second transistor are provided in different tiers of the wiring layer.

19. The photodetector according to claim 18, wherein the first transistor is electrically coupled to the second transistor.

20. An electronic apparatus, comprising: an optical system; and a photodetector that receives light transmitted through the optical system, the photodetector including: a first substrate including a photoelectric conversion element and one or more components of a readout circuit, wherein the photoelectric conversion element is configured to photoelectrically convert light to an electric charge and the readout circuit is configured to output a signal based on the electric charge converted by the photoelectric conversion element, a second substrate including one or more components of a signal processing circuit, wherein the signal processing circuit is configured to process the signal and the second substrate is stacked on the first substrate, and a wiring layer provided in one of the first substrate and the second substrate, wherein the signal processing circuit includes one or more portions of a first transistor and a capacitor provided in the wiring layer.

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