Semiconductor chip, momentary failure countermeasure system, and semiconductor chip control method

Abstract

The present invention reduces a rush current in a system for writing data from a volatile storage unit to a nonvolatile memory.　This semiconductor chip comprises a volatile storage unit, a nonvolatile storage unit, a writing processing unit, a reading processing unit, and a saving / recovery processing unit. The writing processing unit writes write data to the same address in the volatile storage unit and the nonvolatile storage unit. The reading processing unit reads data from addresses in the volatile storage unit as first read data and reads data from addresses in the nonvolatile storage unit as second read data. The saving / recovery processing unit performs saving processing for writing the first read data to addresses in which the corresponding second read data does not match the first read data, among all addresses in the nonvolatile storage unit.

Description

Semiconductor chip, instantaneous power interruption prevention system, and semiconductor chip control method

[0001] The present technology relates to a semiconductor chip, and more particularly to a semiconductor chip provided with a volatile storage unit and a nonvolatile storage unit, a power outage recovery system, and a method for controlling the semiconductor chip.

[0002] Conventionally, in various systems and devices that use semiconductor chips, data may be saved and restored within the semiconductor chip when the power supply voltage drops or when an interrupt occurs. For example, a system has been proposed in which all data in a volatile memory is written to a nonvolatile memory when the power supply voltage drops, and the data is written back to the volatile memory when the power supply voltage rises (see, for example, Patent Document 1).

[0003] Patent No. 5284142

[0004] The above-mentioned conventional technology attempts to prevent data loss by saving the data in non-volatile memory. However, in the above-mentioned system, because all data is written to non-volatile memory, a larger rush current occurs when writing data compared to when only a portion of the data is written.

[0005] This technology was developed in light of these circumstances, and aims to reduce rush current in a system that writes data from a volatile storage unit to a nonvolatile memory.

[0006] The present technology has been made to solve the above-mentioned problems, and a first aspect thereof is a semiconductor chip including a volatile memory unit, a nonvolatile memory unit, a write processing unit that writes write data to the same address in the volatile memory unit and the nonvolatile memory unit, a read processing unit that reads data from the address in the volatile memory unit as first read data and reads data from the address in the nonvolatile memory unit as second read data, and a save / restore processing unit that performs save processing to write the first read data to an address among all addresses in the nonvolatile memory unit where the corresponding second read data does not match the first read data, and a control method thereof, thereby resulting in an effect of reducing rush current.

[0007] In addition, in this first aspect, the write processing unit may write the write data using a first write pulse, and the save / recovery processing unit may write the first read data using a second write pulse having a pulse width and / or voltage greater than those of the first write pulse, thereby providing an effect of suppressing write errors.

[0008] In addition, in this first aspect, the save / recovery processing unit may further perform a recovery process in which, after the save process, the read data newly read from the nonvolatile storage unit is written to the volatile storage unit, thereby achieving the effect of recovering the saved data.

[0009] In addition, in this first aspect, the volatile memory unit may hold tag bits of initial values ​​for each of the addresses, the write processing unit may write the write data to the addresses using the first write pulse and update the corresponding tag bits to values ​​different from the initial values, the read processing unit may update the corresponding tag bits to the initial values ​​if the first read data and the second read data match, and the save / recovery processing unit may write the first read data to an address of all the addresses whose corresponding tag bits are different from the initial values ​​using the second write pulse. This brings about the effect of determining whether or not there is a mismatch based on the tag bits.

[0010] In addition, in this first aspect, the nonvolatile memory unit may include a plurality of nonvolatile banks, thereby providing an effect of reducing rush current in a multi-bank configuration.

[0011] In addition, in this first aspect, the memory device may further include a bank switching control unit that switches a running bank among the plurality of non-volatile banks, and the save / restore processing unit may perform the save process of writing the first read data by the second write pulse to an address of the running bank where the corresponding tag bit is different from the initial value, among all addresses of the running bank, and the restore process of writing read data read from the restore target bank designated by the bank switching to the volatile memory unit after the save process and updating the corresponding tag bit to the initial value. This provides the effect of determining whether or not there is a mismatch based on the tag bit in a multi-bank configuration.

[0012] In this first aspect, each of the volatile memory unit and the non-volatile memory unit may include at least one of a general-purpose register, a stack pointer register, a program counter register, a saved program counter register, a processor status word register, a saved status register, a procedure register, a multiplication register, a base register, a vector base register, a read data buffer register, and a write data buffer register, thereby reducing rush current when writing to a general-purpose register or the like.

[0013] In addition, in this first aspect, the volatile memory unit may include a volatile shared resource that stores shared data shared by a plurality of entities and a volatile non-shared resource that stores data other than the shared data, and the non-volatile memory unit may include a non-volatile shared resource that stores the shared data and a plurality of non-volatile non-shared banks that store data other than the shared data, thereby achieving an effect of efficient memory utilization.

[0014] In this first aspect, the volatile memory unit may include a predetermined number of volatile registers, and the nonvolatile memory unit may include a predetermined number of nonvolatile registers, thereby suppressing rush current when writing to the nonvolatile registers.

[0015] In addition, in this first aspect, the volatile memory unit may include a predetermined number of volatile memory circuits, the nonvolatile memory unit may include a predetermined number of nonvolatile memory circuits, and the volatile memory circuits and the nonvolatile memory circuits may be arranged in the same register, thereby providing the effect of integrating the nonvolatile register and the volatile register.

[0016] A second aspect of the present technology is a momentary power failure response system including a semiconductor chip including: a detection circuit that detects that a power supply voltage has dropped to a value lower than a second threshold, a volatile storage unit, a nonvolatile storage unit, a write processing unit that writes write data to the same address in the volatile storage unit and the nonvolatile storage unit, a read processing unit that reads data from the address in the volatile storage unit as first read data and reads data from the address in the nonvolatile storage unit as second read data, and a save / recovery processing unit that performs save processing, when the power supply voltage has dropped to a value lower than the second threshold, to write the first read data to an address among all addresses in the nonvolatile storage unit where the corresponding second read data does not match the first read data. This brings about the effect of suppressing rush current during save in response to a power supply drop.

[0017] In addition, in the second aspect, the device may further include an energy harvester, and a power supply control unit that supplies power from the energy harvester to the detection circuit when the power supply voltage falls below a first threshold that is higher than the second threshold, thereby eliminating the need for rollback processing.

[0018] In the second aspect, the semiconductor chip may further include a storage battery, and the power supply control unit may supply power from at least one of the energy harvester and the storage battery to the semiconductor chip when the power supply voltage falls below the first threshold, thereby providing an effect of continuing power supply even when environmental energy is insufficient.

[0019] 1 is a block diagram showing an example configuration of a semiconductor chip according to a first embodiment of the present technology. FIG. 2 is a block diagram showing an example configuration of a digital signal processing unit according to the first embodiment of the present technology. FIG. 3 is a block diagram showing an example configuration of a non-volatile register file according to the first embodiment of the present technology. FIG. 4 is a block diagram showing an example configuration of a volatile register file according to the first embodiment of the present technology. FIG. 5 is a circuit diagram showing an example configuration of a non-volatile register according to the first embodiment of the present technology. FIG. 6 is a circuit diagram showing an example configuration of a volatile register according to the first embodiment of the present technology. FIG. 7 is a diagram showing an example configuration of a signal list according to the first embodiment of the present technology. FIG. 8 is a flowchart showing an example of a write process according to the first embodiment of the present technology. FIG. 9 is a flowchart showing an example of a read process according to the first embodiment of the present technology. FIG. 10 is a flowchart showing an example of a save and restore process according to the first embodiment of the present technology. FIG. 11 is a flowchart showing another example of a save and restore process according to the first embodiment of the present technology. FIG. 12 is a block diagram showing an example configuration of a storage unit according to a modified example of the first embodiment of the present technology. FIG. 13 is a block diagram showing an example configuration of a register according to a modified example of the first embodiment of the present technology. FIG. 14 is a block diagram showing an example configuration of an embedded register according to a modified example of the first embodiment of the present technology. FIG. 15 is a diagram showing an example setting of a control signal according to a modified example of the first embodiment of the present technology. 1 is a diagram summarizing conditions under which each signal becomes "1" in a modified example of the first embodiment of the present technology. FIG. 2 is a timing chart showing an example of a waveform of a clock signal and an operation of a digital signal processing unit in a modified example of the first embodiment of the present technology. FIG. 3 is a block diagram showing an example of a configuration of a storage unit in a second embodiment of the present technology. FIG. 4 is a block diagram showing an example of a configuration of a CPU (Central Processing Unit) system compatible with power interruption recovery in a second embodiment of the present technology. FIG. 5 is a diagram showing an example of a configuration of a BN register configured by a nonvolatile register or nonvolatile memory in which read verification is performed until writing is successful in a modified example of the second embodiment of the present technology. FIG. 6 is a diagram showing an example of a configuration of a BN register configured by a nonvolatile register or nonvolatile memory in which read verification is performed until writing is successful in a modified example of the second embodiment of the present technology.10 is a block diagram showing an example configuration of a CPU system for recovery from power interruption according to a third embodiment of the present technology. FIG. 11 is a diagram showing a list of registers according to the third embodiment of the present technology. FIG. 12 is a block diagram showing an example configuration of a storage unit according to the third embodiment of the present technology. FIG. 13 is a block diagram showing an example configuration of a storage unit when a non-volatile register and a volatile register are integrated according to the third embodiment of the present technology. FIG. 14 is a block diagram showing an example configuration of a storage unit according to a modified example of the third embodiment of the present technology. FIG. 15 is a block diagram showing an example configuration of a CPU system for recovery from power interruption according to a modified example of the third embodiment of the present technology. FIG. 16 is a block diagram showing an example configuration of a non-volatile memory according to a fourth embodiment of the present technology. FIG. 17 is a block diagram showing an example configuration of a volatile memory according to the fourth embodiment of the present technology. FIG. 18 is a block diagram showing an example configuration of a CPU system for recovery from power interruption according to the fourth embodiment of the present technology. FIG. 19 is a block diagram showing an example configuration of an instantaneous power interruption countermeasure system according to a fifth embodiment of the present technology. FIG. 19 is a block diagram showing an implementation example of an instantaneous power interruption countermeasure system according to a modified example of the ...

[0020] Hereinafter, modes for carrying out the present technology (hereinafter referred to as embodiments) will be described. The description will be given in the following order: 1. First embodiment (an example of saving data to an address where read data does not match) 2. Second embodiment (an example of saving data to an address where read data does not match in a bank currently being executed) 3. Third embodiment (an example of saving data to an address where read data does not match in a CPU register file) 4. Fourth embodiment (an example of providing a shared resource and a non-shared resource and saving data to an address where read data does not match) 5. Fifth embodiment (an example of saving data to an address where read data does not match in response to a power drop)

[0021] 1 is a block diagram showing a configuration example of a semiconductor chip 200 according to a first embodiment of the present technology. The semiconductor chip 200 is a CIS (CMOS Image Sensor) and includes a vertical drive circuit 211, a timing control unit 212, a DAC (Digital to Analog Converter) 213, and a pixel array unit 214. The semiconductor chip 200 further includes a column signal processing unit 215, a horizontal transfer control unit 216, and a digital signal processing unit 220.

[0022] A plurality of pixels are arranged in a two-dimensional lattice in the pixel array section 214. The vertical drive circuit 211 sequentially selects rows in the pixel array section 214, drives each pixel in that row, and outputs an analog signal to the column signal processing section 215.

[0023] The timing control section 212 controls the operation timing of each of the vertical drive circuit 211 , the DAC 213 , the column signal processing section 215 and the horizontal transfer control section 216 .

[0024] The DAC 213 generates a sawtooth ramp signal by DA (Digital to Analog) conversion and supplies it to the column signal processing unit 215 .

[0025] An ADC (Analog to Digital Converter) is arranged in the column signal processing unit 215 for each column of the pixel array unit 214. The ADC converts an analog signal from the corresponding column into a digital signal and supplies the digital signal to the digital signal processing unit 220 under the control of the horizontal transfer control unit 216.

[0026] The horizontal transfer control unit 216 controls the column signal processing unit 215 to output the digital signals of each column in sequence.

[0027] The digital signal processing unit 220 performs various signal processing such as white balance correction and demosaic processing on the digital signal from the column signal processing unit 215. The digital signal processing unit 220 outputs image data after processing.

[0028] 2 is a block diagram showing an example of the configuration of the digital signal processing unit 220 according to the first embodiment of the present technology. The digital signal processing unit 220 includes an external setting input / output interface 221, an external setting nonvolatile register group 222, and a power interruption recovery compatible CPU system 300.

[0029] The external setting input / output interface 221 receives data for initial setting and mid-setting changes from the outside and stores the data in the external setting nonvolatile register group 222. The external setting input / output interface 221 also transmits data read from the external setting nonvolatile register group 222 to the outside.

[0030] The power interruption recovery compatible CPU system 300 saves data when the power supply voltage drops and restores the data when the power supply voltage is restored. This power interruption recovery compatible CPU system 300 includes an access control unit 310 and a storage unit 400. The storage unit 400 can be provided with a frame memory or the like. Details of providing a frame memory will be described later in the fifth embodiment.

[0031] The access control unit 310 includes a write processing unit 311, a read processing unit 312, and a save / restore processing unit 313. The storage unit 400 includes a non-volatile register file 410 and a volatile register file 450.

[0032] Although the figure uses a nonvolatile register file 410 and a volatile register file 450, volatile memory and nonvolatile memory can be used instead. For example, a combination of static random access memory (SRAM) and nonvolatile RAM, or a combination of dynamic random access memory (DRAM) and nonvolatile RAM can be used. Furthermore, a magnetic memory can be used as the nonvolatile memory. For example, a spin transfer torque (STT)-magnetoresistive random access memory (MRAM) can be used as this magnetic memory. Furthermore, the magnetic memory is not limited to STT-MRAM, and new magnetic memories such as voltage-controlled magnetic anisotropy (VMCA)-MRAM and spin-orbit torque (SOT)-MRAM can also be used.

[0033] Furthermore, the nonvolatile register file 410 is an example of a nonvolatile storage unit as defined in the claims, and the volatile register file 450 is an example of a nonvolatile storage unit as defined in the claims.

[0034] The details of the processing performed by the write processing unit 311, the read processing unit 312, and the save / recovery processing unit 313 will be described later.

[0035] It should be noted that a power interruption recovery support system having the same functions as the power interruption recovery support CPU system 300 can be provided independently in an AE (Auto Exposure) control unit external to the digital signal processing unit 220. In this case, the power interruption recovery support system in the AE control unit performs recovery operations after a power interruption independently of the power interruption recovery support CPU system 300 in accordance with user settings.

[0036] Furthermore, although the power interruption recovery compatible CPU system 300 is disposed within the semiconductor chip 200, which is a CIS, the present invention is not limited to this configuration. The power interruption recovery compatible CPU system 300 can also be disposed within various semiconductor chips other than a CIS.

[0037] 3 is a block diagram showing an example of the configuration of the nonvolatile register file 410 according to the first embodiment of the present technology. The nonvolatile register file 410 includes an address decoder 411, a nonvolatile register group 412, and an output selector 413. The nonvolatile register group 412 includes K (K is an integer equal to or greater than 2) nonvolatile registers 420. Each of the nonvolatile registers 420 has an address ADDR ＮＶ is assigned.

[0038] The address decoder 411 receives the address ADDR from the access control unit 310. ＮＶ The address decoder 411 receives the address ADDR ＮＶ The address ADDR of the one-hot signal DEC is decoded to generate a K-bit one-hot signal DEC. ＮＶ Only the bits corresponding to these registers are set to a logical value of “1”, and the remaining bits are set to a logical value of “0”. The address decoder 411 outputs a one-hot signal DEC to the non-volatile register group 412 and the output selector 413.

[0039] The address ADDR from the access control unit 310 ＮＶ However, if it is outside the range, the address decoder 411 may output a one-hot signal DEC in which all bits are logical "0".

[0040] The output selector 413 selects one of the nonvolatile register output signals NVQ from each of the nonvolatile registers 420 based on the one-hot signal DEC. The output selector 413 selects a signal corresponding to a bit with a logic value of "1" from the one-hot signal DEC and outputs it to the volatile register file 450.

[0041] When all bits of the one-hot signal DEC are logically "0", the output selector 413 may output the previous value as is, may make some selection, or may output a specific constant.

[0042] 4 is a block diagram showing an example of the configuration of a volatile register file 450 according to the first embodiment of the present technology. The volatile register file 450 includes an address decoder 451, a volatile register group 452, an output selector 453, and a comparator 454. The volatile register group 452 has K volatile registers 460 arranged therein. Each of these volatile registers 460 has an address ADDR Ｖ is assigned.

[0043] The volatile register group 452 also stores an address ADDR Ｖ A one-bit tag bit TAG is maintained for each.

[0044] The address decoder 451 is configured as follows: Ｖ and generates a K-bit one-hot signal DEC, which is output to the volatile register group 452 and the output selector 453 .

[0045] The output selector 413 selects one of the volatile register output signals VQ from each of the volatile registers 460 based on the one-hot signal DEC. The output selector 413 selects a signal corresponding to a bit with a logical value of "1" from the one-hot signal DEC and outputs it to the comparator 454.

[0046] The comparator 454 compares the nonvolatile register output signal NVQ from the nonvolatile register file 410 with the volatile register output signal VQ from the output selector 453. The comparator 454 supplies a comparison result signal CMP_OUT indicating the comparison result to the volatile register group 452.

[0047] 5 is a circuit diagram showing an example of the configuration of the nonvolatile register 420 according to the first embodiment of the present technology. The nonvolatile register 420 receives the DEC[k] from the address decoder 411, the access control signal R / W, the data input signal D, and the register save enable signal REN from the access control unit 310, and the clock signal CK. The nonvolatile register 420 also receives the volatile register output signal VQ and tag bit TAG from the volatile register file 450. The nonvolatile register 420 then outputs the nonvolatile register output signal NVQ to the volatile register file 450 and the output selector 413.

[0048] DEC[k] indicates the kth (k is an integer from 1 to K) bit of the one-hot signal DEC, and is input to the kth nonvolatile register 420 .

[0049] The access control signal R / W is a signal that indicates either a read without a write or a write. For example, the access control signal R / W is set to a logical value "0" when reading without a write, and to a logical value "1" when writing.

[0050] The data input signal D indicates write data to be written to the nonvolatile register 420 and the volatile register 460. The data size of this write data is assumed to be J bits (J is an integer).

[0051] The volatile register output signal VQ indicates read data read from the volatile register 460 in the volatile register file 450. The data size of this read data is also J bits. The volatile register output signal VQ is an example of the first read data described in the claims.

[0052] The tag bit TAG is a signal indicating the status of writing to the corresponding nonvolatile register 420. For example, when there is no writing to the nonvolatile register 420 (in other words, the initial state) or when writing is completed, the corresponding tag bit TAG is set to a logical value of "0" as an initial value, and when writing is temporarily performed, a logical value of "1" is set.

[0053] The register save enable signal REN is a signal indicating whether or not the function of saving from the volatile register 460 to the non-volatile register 420 is enabled. For example, when disabled, the register save enable signal REN is set to a logical value of "0," and when enabled, the signal is set to a logical value of "1."

[0054] The nonvolatile register output signal NVQ indicates the read data read from the nonvolatile register 420. The nonvolatile register output signal NVQ is an example of the second read data set forth in the claims.

[0055] Here, K addresses ADDR on the nonvolatile side ＮＶ and K addresses ADDR on the volatile side Ｖ and have a one-to-one correspondence. The volatile register output signal VQ and tag bit TAG from the kth volatile register 460 are input to the kth nonvolatile register 420. The nonvolatile register output signal NVQ from the kth nonvolatile register 420 is output to the kth volatile register 460 and the output selector 413.

[0056] The nonvolatile register 420 also includes AND (logical product) gates 421 and 422 , selectors 423 and 424 , and a nonvolatile multi-bit flip-flop 425 .

[0057] The AND gate 421 outputs the logical product of the access control signal R / W and the k-th bit DEC[k] of the one-hot signal to the selector 423 .

[0058] The selector 423 selects the output signal of the AND gate 421 when the register save enable signal REN is a logical value "0", and selects the tag bit TAG and outputs it to the AND gate 422 when the register save enable signal REN is a logical value "1".

[0059] The AND gate 422 outputs the logical product of the output signal of the selector 423 and the clock signal CK to the clock terminal of the nonvolatile multi-bit flip-flop 425 .

[0060] The selector 423 selects the data input signal D when the register save enable signal REN is a logical value "0", and selects the volatile register output signal NQ when the register save enable signal REN is a logical value "1", and outputs it to the input terminal of the non-volatile multi-bit flip-flop 425.

[0061] The nonvolatile multi-bit flip-flop 425 holds the output signal of the selector 424. The size of this nonvolatile multi-bit flip-flop 425 is J bits. The nonvolatile multi-bit flip-flop 425 outputs the held signal as a nonvolatile register output signal NVQ.

[0062] The configuration illustrated in the figure achieves the following operation. First, we will explain the case where the register save enable signal REN is disabled. In this case, when R / W is a logical value "1" indicating a write and DEC[k] is a logical value "1" (i.e., the kth address is selected), the nonvolatile register 420 at that address writes the data input signal D to the nonvolatile multi-bit flip-flop 425. The R / W pulse of "1" during this write is called write pulse P1. If this condition is not met, the nonvolatile register 420 retains the previous value.

[0063] Next, a case where the register save enable signal REN is enabled will be described. In this case, when the tag bit TAG from the kth volatile register 460 is a logical value "1," the kth nonvolatile register 420 writes the VQ from that volatile register 460 to the nonvolatile multi-bit flip-flop 425. If the write pulse used in this write is designated P2, at least one of the pulse width and voltage of P2 is greater than P1. The pulse width and voltage of the write pulse P2 are set to values ​​that ensure 100% successful writing. Note that the write pulses P1 and P2 are examples of the first and second write pulses set forth in the claims.

[0064] Furthermore, after writing during backup, the access control unit 310 reads data from the volatile register 460 and the nonvolatile register 420, determines whether they match, and repeatedly rewrites the data until they match. Note that the nonvolatile multi-bit flip-flop 425 always outputs the stored value, and if the value is updated, the updated value is reflected in the output signal from the cycle following the write cycle.

[0065] 6 is a circuit diagram showing an example of the configuration of the volatile register 460 according to the first embodiment of the present technology. The volatile register 460 receives the DEC[k] signal from the address decoder 411, the access control signal R / W, the data input signal D, and the register restore signal REST from the access control unit 310, and the clock signal CK. The volatile register 460 also receives the nonvolatile register output signal NVQ from the nonvolatile register file 410 and the comparison result signal CMP_OUT from the comparator 454. The volatile register 460 then outputs the volatile register output signal VQ to the nonvolatile register file 410 and the output selector 453. The volatile register 460 also outputs the tag bit TAG to the nonvolatile register file 410.

[0066] The comparison result signal CMP_OUT is a signal that indicates whether or not the read data of the non-volatile register 420 matches the read data of the corresponding volatile register 460. For example, if the read data matches, the comparison result signal CMP_OUT is set to a logical value of "1," and if they do not match, the logical value is set to "0."

[0067] The register restore signal REST is a signal indicating whether or not to write (in other words, restore) data from the nonvolatile register 420 to the corresponding volatile register 460 after saving. For example, if restoration is to be performed, the register restore signal REST is set to a logical value of "1," and if restoration is not to be performed, the register restore signal REST is set to a logical value of "0."

[0068] Volatile register 460 also includes AND gates 461 to 464 , logic gates 465 and 466 , an OR (logical sum) gate 467 , a selector 468 , a volatile multi-bit flip-flop 469 , and a one-bit flip-flop 470 .

[0069] The AND gate 461 outputs the logical product of the access control signal R / W and the k-th bit DEC[k] of the one-hot signal to the OR gate 467 .

[0070] The OR gate 467 outputs the logical sum of the register restore signal REST and the output signal of the AND gate 461 to the AND gate 462 .

[0071] The AND gate 462 outputs the logical product of the output signal of the OR gate 467 and the clock signal CK to the clock terminal of the volatile multi-bit flip-flop 469 .

[0072] The selector 468 selects the data input signal D when the register recovery signal REST is a logical value "0", and selects the non-volatile register output signal NVQ when the register recovery signal REST is a logical value "1", and outputs it to the input terminal of the volatile multi-bit flip-flop 469.

[0073] The volatile multi-bit flip-flop 469 holds the output signal of the selector 468. The size of this volatile multi-bit flip-flop 469 is J bits. The volatile multi-bit flip-flop 469 outputs the held signal as a volatile register output signal VQ.

[0074] The logic gate 466 outputs to the logic gate 465 the logical product of the inverted value of the access control signal R / W and the k-th bit DEC[k] of the one-hot signal.

[0075] The logic gate 465 calculates the logical product of the inverted value of the clock signal CK, the comparison result signal CMP_OUT, and the output signal of the logic gate 466 , and outputs the logical sum of this logical product and the register restore signal REST to the 1-bit flip-flop 470 .

[0076] The AND gate 464 outputs to the AND gate 463 the logical product of the access control signal R / W and the k-th bit DEC[k] of the one-hot signal.

[0077] The AND gate 463 inputs the logical product of the output signal of the AND gate 464 and the clock signal CK to the clock terminal of the 1-bit flip-flop 470 .

[0078] The one-bit flip-flop 470 is volatile and holds the tag bit TAG. A high level (i.e., a logical value "1") is input to a set terminal S of the one-bit flip-flop 470. An inverted value of the output signal of the logic gate 465 is input to a reset terminal R of the one-bit flip-flop 470. The input to the reset terminal R of the one-bit flip-flop 470 takes priority in determining the output value. The one-bit flip-flop 470 also outputs the tag bit TAG to the non-volatile register file 410.

[0079] The configuration illustrated in the figure achieves the following operations. First, we will explain the case where the register restore signal REST is disabled. In this case, when R / W is a logical value "1" indicating a write and DEC[k] is a logical value "1," the volatile register 460 writes the data input signal D to the volatile multi-bit flip-flop 469 and updates the one-bit flip-flop 470 to a logical value "1." Also, when R / W is a logical value "0" indicating a read and DEC[k] is a logical value "1," the volatile register 460 initializes the one-bit flip-flop 470 to a logical value "0" while the clock signal CK is "0" if the comparison result signal CMP_OUT is a logical value "1." If these conditions are not met, the volatile register 460 retains its previous value.

[0080] Next, a case where the register restore signal REST is enabled will be described. In this case, the volatile register 460 writes the nonvolatile register output signal NVQ from the nonvolatile register 420 having the same DEC[k] to the volatile multi-bit flip-flop 469 and initializes the one-bit flip-flop 470 to a logical value of "0."

[0081] Fig. 7 is a diagram showing an example of a signal list according to the first embodiment of the present technology, which lists the signal names and descriptions of the signals described above with reference to Figs.

[0082] [Example of Operation of Semiconductor Chip] Next, the operation of the CPU system 300 for recovery from power interruption will be described with reference to Figures 8 to 10. Execution of various programs within the CPU system 300 for recovery from power interruption generates write and read requests. The order of write and read requests and the timing of the requests are determined depending on the contents of the programs and the processing status. When a write request occurs, the write process of Figure 8 is executed, and when a read request without writing occurs, the read process of Figure 9 is executed. Furthermore, when data evacuation is required due to an interrupt, task switching, a drop in power supply voltage, or the like, the save / recovery process of Figure 10 is executed.

[0083] However, the device equipped with the semiconductor chip 200 is equipped with an auxiliary power supply, which will be described later, and even if the power supply voltage drops, the power supply from the auxiliary power supply will continue for a certain period of time, and the power will not be cut off while the data is being saved.

[0084] 8 is a flowchart illustrating an example of a write process according to the first embodiment of the present technology. The write processing unit 311 in the power interruption recovery compatible CPU system 300 writes write data to the same address in the volatile register file 450 and the non-volatile register file 410 using a write pulse P1 (step S901).

[0085] For example, the kth volatile address ADDR is used as the write destination. Ｖ When the address is specified, the address and the corresponding k-th non-volatile side address ADDR ＮＶ The same write data is written to both.

[0086] The write processing unit 311 also updates the tag bit corresponding to the address of the access destination to a logical value of "1" (step S902), and ends the write processing.

[0087] 9 is a flowchart illustrating an example of a read process according to the first embodiment of the present technology. The read processing unit 312 in the power interruption recovery compatible CPU system 300 reads data from the same address in the volatile register file 450 and the non-volatile register file 410 as read data (step S911).

[0088] For example, the kth volatile side address ADDR is used as the read destination. Ｖ When the address is specified, the address and the corresponding k-th non-volatile side address ADDR ＮＶ The read data on the volatile side corresponds to the volatile register output signal VQ described above, and the read data on the nonvolatile side corresponds to the nonvolatile register output signal NVQ described above.

[0089] The comparator 454 in the volatile register file 450 determines whether the read data (VQ) on the volatile side and the read data (NVQ) on the non-volatile side match (step S912).

[0090] If the read data matches (step S912: Yes), the read processing unit 312 updates the tag bit of the access destination to the logical value "0" (step S913). If the read data does not match (step S912: No), or after step S913, the read processing unit 312 ends the read process.

[0091] 8 and 9 , the access control unit 310 can also execute the following process. For example, the access control unit 310 periodically checks the tag bits of the volatile register file 450, and if any of them contain a logical value of "1," it performs revisions such as gradually increasing the voltage or lengthening the write pulse width up to the upper limit of the period corresponding to the frequency. The access control unit 310 then writes data at an address where the tag bit has a logical value of "1" from the volatile register file 450 to the non-volatile register file 410 using the revised high voltage and long write pulse width. The access control unit 310 then clears the tag bit to a logical value of "0" after writing is complete.

[0092] If all tag bits become logical "0," the access control unit 310 may store the voltage and write pulse width in nonvolatile memory and use them as default values ​​thereafter. When a logical "1" appears in the tag bit value, the access control unit 310 performs an additional update. This allows for stable writing at a low voltage and short write pulse width appropriately selected according to the operating conditions of the chip, rather than the voltage and write pulse width that are previously set to ensure 100% successful writing.

[0093] 10 is a flowchart showing an example of a save / restore process according to the first embodiment of the present technology. The save / restore processor 313 in the power interruption recovery-compatible CPU system 300 specifies an address to be accessed (step S921), and determines whether the tag bit of the address is logical "1" (step S922).

[0094] If the tag bit has a logical value of "1" (step S922: Yes), the save / restore processing unit 313 writes the read data (VQ) from the volatile register 460 to the non-volatile register 420 using a high-voltage write pulse P2 (step S923).

[0095] For example, the kth nonvolatile address ADDR ＮＶ If the corresponding k-th tag bit is a logical "1", then the k-th volatile side address ADDR Ｖ The read data (VQ) is at its address ADDR ＮＶ is written to.

[0096] If the tag bit is logical "0" (step S922: No), or after step S923, the save / restore processor 313 determines whether all addresses have been specified (step S924). If all addresses have not been specified (step S924: No), the save / restore processor 313 repeats step S921 and subsequent steps. Alternatively, as described below, all data corresponding to a group of addresses on the volatile side where the tag bit has a logical value of "1" may be written at once at a high voltage to the same corresponding group of addresses on the non-volatile side.

[0097] If all addresses have been specified (step S924: Yes), the save / restore processor 313 determines whether it is time to perform restoration, such as when the power supply voltage rises (step S925). If it is not time to perform restoration (step S925: No), the save / restore processor 313 returns to step S925.

[0098] If it is time to perform recovery (step S925: Yes), the save / recovery processor 313 specifies the address to be accessed (step S926).

[0099] The save / restore processing unit 313 writes the read data (NVQ) from the nonvolatile register 420 at the specified address to the corresponding volatile register 460 (step S927), and updates the tag bit at that address to the logical value "1" (step S928).

[0100] The save / restore processor 313 then determines whether all addresses have been specified (step S929). If all addresses have not been specified (step S929: No), the save / restore processor 313 repeats step S926 and subsequent steps. Alternatively, as will be described later, all data corresponding to all addresses on the non-volatile side may be written to the same corresponding addresses on the volatile side at once.

[0101] If all addresses have been specified (step S929: Yes), the save / restore processor 313 ends the save / restore process.

[0102] Alternatively, the save / restore processing unit 313 can perform the save / restore processing illustrated in FIG. 11 . The save / restore processing unit 313 determines whether to perform save (step S921) or restore (step S922). If it determines to perform save (step S921: Yes), the save / restore processing unit 313 writes all data corresponding to the volatile side address group whose tag bit has a logical value of "1" to the corresponding same address group on the nonvolatile side at once with high voltage (step S923). If it determines to perform restore (step S922: Yes), the save / restore processing unit 313 writes all data corresponding to all nonvolatile side address groups to the corresponding same address group on the volatile side at once (step S924). If neither of these conditions is met (No in both steps S921 and S922), the save / restore processing unit 313 performs neither save processing nor restore processing.

[0103] 10 and 11, when saving, the VQ is written to an address where the read data (NVQ) on the nonvolatile side does not match the read data (VQ) on the volatile side among all addresses of the nonvolatile register file 410. This makes it possible to reduce rush current during saving compared to when data is written to all addresses on the nonvolatile side during saving.

[0104] Furthermore, by writing with write pulse P2, which has a voltage and / or pulse width greater than write pulse P1, during the save operation, write errors can be reduced compared to when writing with P1. When writing before the save operation, by writing with P1, which has a voltage lower than P2 or a pulse width shorter than P2, stable writing can be achieved with an appropriate voltage and pulse width according to the operating status of the chip, and power consumption can be reduced.

[0105] Furthermore, even when write pulse P1 is used during saving, a method of suppressing write errors can be considered by duplicating the nonvolatile register file 410 as described in Japanese Patent Application Laid-Open No. 2018-0215777. However, this method increases the area and power consumption of the nonvolatile register file 410 due to the duplication. In contrast, the first embodiment, in which writing is performed using write pulse P2 during saving, does not require duplication, and therefore can reduce the area and power consumption of the nonvolatile register file 410 while suppressing write errors, compared to Japanese Patent Application Laid-Open No. 2018-0215777.

[0106] Thus, according to the first embodiment of the present technology, the save / restore processing unit 313 writes data to the addresses of all addresses in the non-volatile register file 410 where the read data does not match during save, thereby reducing the rush current during save.

[0107] In the first embodiment described above, the nonvolatile register 420 and the volatile register 460 are separately provided, but they may also be integrated. The semiconductor chip 200 in this modification of the first embodiment differs from the first embodiment in that a single register includes both a nonvolatile and a volatile memory circuit.

[0108] 12 is a block diagram showing an example configuration of a storage unit 400 according to a modification of the first embodiment of the present technology. The storage unit 400 according to the modification of the first embodiment includes an address decoder 411, a register group 414, and an output selector 413. The register group 414 includes K registers 500, each of which is assigned an address ADDR.

[0109] In the modification of the first embodiment, the address decoder 411 decodes the address ADDR from the access control unit 310 , generates a one-hot signal DEC, and outputs it to the register group 414 and the output selector 413 .

[0110] The output selector 413 selects one of the output signals of the register 500 based on the one-hot signal DEC, and outputs the selected signal to the access control unit 310 .

[0111] 13 is a block diagram showing an example of a configuration of a register 500 according to a modification of the first embodiment of the present technology. The register 500 includes AND gates 511 to 514, logic gates 515 and 516, an embedded register 520, and a 1-bit flip-flop 517.

[0112] The AND gate 511 outputs to the AND gate 512 the logical product of the access control signal R / W and the k-th bit DEC[k] of the one-hot signal.

[0113] The AND gate 512 outputs the logical product of the output signal of the AND gate 511 and the divided clock signal CK_DIV as a clock signal C to the clock terminal of the mixed register 520 .

[0114] Here, the divided clock signal CK_DIV is a signal obtained by dividing the source clock signal CK. The source clock signal CK, which is the source of the divided signal, is used in a circuit external to the register 500.

[0115] The mixed register 520 receives the data input signal D, control signal CTRL, restore control signal SR1, store control signal SR2, verify restore control signal SR3, control signal LPGS, and control signal LPGB from the access control unit 310. The mixed register 520 also outputs a register output signal Q to the output selector 413 and outputs a comparison result signal CMP_OUT to the logic gate 516.

[0116] The logic gate 515 outputs to the logic gate 516 the logical product of the inverted value of the access control signal R / W and the k-th bit DEC[k] of the one-hot signal.

[0117] The logic gate 516 calculates the logical product of the inverted value of the clock signal CK, the comparison result signal CMP_OUT, and the output signal of the logic gate 515 , and outputs the logical sum of this logical product and the register restore signal REST to the 1-bit flip-flop 517 .

[0118] The AND gate 514 outputs to the AND gate 513 the logical product of the access control signal R / W and the k-th bit DEC[k] of the one-hot signal.

[0119] The AND gate 513 inputs the logical product of the output signal of the AND gate 514 and the frequency-divided clock signal CK_DIV to the clock terminal of the 1-bit flip-flop 517 .

[0120] The 1-bit flip-flop 517 holds the tag bit TAG. A high level (i.e., a logical value "1") is input to a set terminal S of the 1-bit flip-flop 517. Furthermore, an inverted value of the output signal of the logic gate 516 is input to a reset terminal R of the 1-bit flip-flop 517 while the clock signal CK is "0". Furthermore, the input to the reset terminal R of the 1-bit flip-flop 517 takes priority in determining the output value. Furthermore, the 1-bit flip-flop 517 outputs the tag bit TAG to the output selector 413.

[0121] 14 is a block diagram showing an example configuration of an embedded register 520 according to a modification of the first embodiment of the present technology. The embedded register 520 includes pMOS (p-channel MOS) transistors 521 to 529, NAND (negative AND) gates 531 to 536, inverters 541 to 544, and transmission gates 551 to 554. The embedded register 520 further includes nMOS (n-channel MOS) transistors 560 to 569, a nonvolatile storage circuit 570, an OR gate 581, and an NXOR (exclusive NOR) gate 582.

[0122] The nonvolatile memory circuit 570 is a nonvolatile circuit that holds one bit, and includes MTJ (Magnetic Tunnel Junction) elements 571 and 572 arranged therein.

[0123] The inverter 541 inverts the data input signal D and outputs it to the transmission gate 551 .

[0124] The transmission gate 551 outputs the output signal of the inverter 541 to the NAND gate 533 when the clock signal C is at a low level and its inverted signal CB is at a high level.

[0125] The NAND gate 533 outputs the NAND of the set signal SN from the access control unit 310 and the wired OR of the output signals of the transmission gates 551 and 552 to the transmission gate 553 and the NAND gate 535 .

[0126] The NAND gate 535 outputs the NAND of the output signal of the NAND gate 533 and the reset signal CN from the access control unit 310 to the transmission gate 552 .

[0127] The transmission gate 552 outputs the output signal of the NAND gate 535 to the NAND gate 533 when the clock signal C is at a low level and its inverted signal CB is at a high level.

[0128] The transmission gate 553 outputs the output signal of the NAND gate 533 to the NAND gate 534 when the clock signal C is at a low level and its inverted signal CB is at a high level.

[0129] The NAND gate 534 outputs the NAND of the reset signal CN from the access control unit 310 and the wired OR of the output signals of the transmission gates 553 and 554 to the NXOR gate 582 , the inverter 543 and the NAND gate 536 .

[0130] The pMOS transistor 523 is inserted between the power supply voltage and the power supply terminal of the NAND gate 534, and the control signal LPGS is input to the gate of the pMOS transistor 523.

[0131] The inverter 543 inverts the output signal of the NAND gate 534 and outputs it as a register output signal Q.

[0132] The NAND gate 536 outputs the NAND of the set signal SN and the output signal of the NAND gate 534 to the transmission gate 554 .

[0133] The pMOS transistor 524 is inserted between the power supply voltage and the power supply terminal of the NAND gate 536, and the control signal LPGS is input to the gate of the pMOS transistor 524.

[0134] The transmission gate 554 outputs the output signal of the NAND gate 536 to the NAND gate 534 when the clock signal C is at a low level and its inverted signal CB is at a high level.

[0135] The nMOS transistor 565 shorts between the NAND gates 536 and 534 when the restore control signal SR1 has a logic value of "1".

[0136] A circuit including the above-described inverters 541 and 543, transmission gates 551 to 554, NAND gates 533 to 536, pMOS transistors 523 and 524, and nMOS transistor 565 is referred to as a volatile storage circuit 530. This volatile storage circuit 530 functions as a flip-flop that holds one volatile bit.

[0137] The NAND gate 531 outputs the NAND of the output signal of the MTJ element 571 and the set signal SN to the NAND gate 532 and the NXOR gate 582 .

[0138] The pMOS transistor 521 is inserted between the power supply voltage and the power supply terminal of the NAND gate 531, and the control signal LPGB is input to the gate of the pMOS transistor 521.

[0139] The NAND gate 532 outputs to the NAND gate 531 the NAND of the output signal of the NAND gate 531 and the reset signal CN.

[0140] The pMOS transistor 522 is inserted between the power supply voltage and the power supply terminal of the NAND gate 532, and the control signal LPGB is input to the gate of the pMOS transistor 522.

[0141] The NXOR gate 582 performs an exclusive NOR on the output signal of the NAND gate 531 and the output signal of the NAND gate 534, and outputs the result as a comparison result signal CMP_OUT.

[0142] The nMOS transistor 566 short-circuits the connection node between the NAND gates 531 and 532 and the reference layer of the MTJ element 572 when the verify restore control signal SR3 has a logical value of "1."

[0143] A circuit including the above-mentioned pMOS transistors 521 and 522 , NAND gates 531 and 532 , NXOR gate 582 , and nMOS transistor 566 functions as a comparator 580 .

[0144] The OR gate 581 outputs the logical sum of the restore control signal SR 1 , the store control signal SR 2 and the verify restore control signal SR 3 to the gate of the nMOS transistor 563 .

[0145] The pMOS transistor 529 and the nMOS transistors 562 and 533 are connected in series between the power supply voltage and the ground voltage, with the pMOS transistor 529 on the power supply side.

[0146] A control signal CTRL is input to the gates of the pMOS transistor 529 and the nMOS transistor 562. The connection node between the pMOS transistor 529 and the nMOS transistor 562 is commonly connected to the free layers of the MTJ elements 571 and 572.

[0147] The inverter 542 inverts the store control signal SR 2 and outputs it to the gate of the pMOS transistor 527 .

[0148] The pMOS transistors 527 and 528 and the nMOS transistors 560 and 561 are connected in series between the power supply voltage and the ground voltage, with the pMOS transistors 527 and 528 on the power supply side.

[0149] A store control signal SR2 is input to the gate of the nMOS transistor 561. The gates of the pMOS transistor 528 and the nMOS transistor 560 are commonly connected to the connection node of the transmission gates 553 and 554. The connection node of the pMOS transistor 528 and the nMOS transistor 560 is connected to the reference layer of the MTJ element 572.

[0150] The nMOS transistor 564 short-circuits the output terminal of the NAND gate 536 and the reference layer of the MTJ element 571 when the restore control signal SR1 has a logical value of "1."

[0151] The nMOS transistor 569 short-circuits the output terminal of the NAND gate 534 and the reference layer of the MTJ element 572 when the restore control signal SR1 has a logical value of "1."

[0152] The inverter 544 inverts the store control signal SR 2 and outputs it to the gate of the pMOS transistor 525 .

[0153] The pMOS transistors 525 and 526 and the nMOS transistors 567 and 568 are connected in series between the power supply voltage and the ground voltage, with the pMOS transistors 525 and 526 on the power supply side.

[0154] The gates of the pMOS transistor 526 and the nMOS transistor 567 are commonly connected to the connection node of the NAND gates 534 and 536. The connection node of the pMOS transistor 526 and the nMOS transistor 567 is connected to the reference layer of the MTJ element 571. The gate of the nMOS transistor 568 receives a store control signal SR2.

[0155] The circuit illustrated in the figure is described in Fig. 8 of Japanese Patent Application Laid-Open No. 2021-68488. Note that a circuit other than that shown in Fig. 8 of that document can also be applied to the embedded register 520.

[0156] 15 is a diagram illustrating an example of setting control signals in a modification of the first embodiment of the present technology. When the access control unit 310 writes back from one non-volatile bit to one volatile bit (in other words, register recovery), among the restore control signal SR1, the store control signal SR2, and the verify restore control signal SR3, only SR1 is set to the logical value “1.”

[0157] Furthermore, when the access control unit 310 writes from one volatile bit to one nonvolatile bit before or during saving, the logical value "1" is set only in SR2.

[0158] Furthermore, when the embedded register 520 reads and compares data from one volatile bit and one nonvolatile bit, a logical value of "1" is set only in SR3.

[0159] FIG. 16 is a diagram summarizing conditions under which each signal becomes "1" in the modified example of the first embodiment of the present technology.

[0160] When the access control unit 310 performs register restoration, if the logical product of the divided clock signal CK_DIV and the register restoration signal REST is a logical value "1", a logical value "1" is set to the control signal CTRL.

[0161] Consider a case where the access control unit 310 stores (writes) data to a nonvolatile bit. In this case, if the logical product of the inverted value of the logical sum of CK_DIV and the source clock signal CK, the write control signal W, the inverted value of the store signal STR, and DEC[k] is 1, the logical value "1" is set to the control signal CTRL.

[0162] Consider a case where the access control unit 310 saves data to a nonvolatile bit. In this case, if the logical product of the inverted value of the logical sum of CK_DIV and CK, STR, and the tag bit TAG is "1," the logical value "1" is set to the control signal CTRL.

[0163] Consider a case where the embedded register 520 reads and compares the nonvolatile bit and the volatile bit. In this case, if the logical product of the exclusive OR of CK_DIV and CK, the inverted value of the read control signal R, and DEC[k] is 1, the logical value "1" is set to the control signal CTRL.

[0164] When the access control unit 310 performs register restoration, if the logical product of CK_DIV and the register restoration signal REST is logical "1", the restore control signal SR1 is set to logical "1".

[0165] When the access control unit 310 stores to a non-volatile bit, if the logical product of the inverted value of CK_DIV, W, the inverted value of STR, and DEC[k] is logical "1", the store control signal SR2 is set to logical "1".

[0166] When the access control unit 310 saves data to a nonvolatile bit, if the logical product of the inverted value of CK_DIV, STR, and TAG is logical "1," the store control signal SR2 is set to logical "1."

[0167] Consider a case where the volatile and nonvolatile bits are read and compared by the embedded register 520. In this case, if the logical product of the exclusive OR of CK_DIV and CK, the inverted value of R, and DEC[k] is logical "1," then the verify restore control signal SR3 is set to logical "1."

[0168] When the access control unit 310 performs register restoration, if the logical product of the inverted value of CK, CK_DIV, the inverted value of R, and DEC[k] is logical "1," the logical value "1" is set to the control signal LPGS.

[0169] When embedded register 520 reads and compares the volatile and non-volatile bits, if the logical AND of CK, CK_DIV, and REST is a logical "1", then control signal LPGB is set to a logical "1".

[0170] 17 is a timing chart showing an example of the waveforms of clock signals and the operation of a digital signal processing unit in a modified example of the first embodiment of the present technology. In the same figure, "a" is a timing chart showing an example of the waveforms of a source clock signal CK and a frequency-divided clock signal CK_DIV. In the same figure, "b" is a timing chart showing an example of the operation of the digital signal processing unit 220.

[0171] As shown in FIG. 10A, the frequency-divided clock signal CK_DIV is generated by dividing the source clock signal CK by two.

[0172] As shown in FIG. 1B, the access control unit 310 in the digital signal processing unit 220 writes (i.e., stores) data during a period from timing T0 to T3. For example, a high-level data input signal D is written to both the volatile storage circuit 530 and the nonvolatile storage circuit 570, and a high-level output signal Q is output from the embedded register 520. The access control unit 310 also controls the reset signal CN and the set signal SN to a high level, transmits a pulse of the store control signal SR2 at timing T1, and transmits a pulse of the control signal CTRL at timing T2.

[0173] Then, during the period from timing T3 to T6, the access control unit 310 performs a read, and at that time the embedded register 520 compares the bits read from the volatile storage circuit 530 with the bits read from the non-volatile storage circuit 570. At timing T4, the access control unit 310 transmits a pulse of the control signal CTRL, a pulse of the verify restore control signal SR3, and a pulse of the control signal LPGB. If there is a mismatch, the embedded register 520 outputs a low-level comparison result signal CMP_OUT at timing T5.

[0174] At timing T6, when the sleep period in which the power supply voltage is reduced starts, the access control unit 310 sets the control signal LPGB to high level.

[0175] When the sleep period ends at timing T7, the access control unit 310 supplies a pulse of CTRL, a pulse of the restore control signal SR1, and a pulse of the control signal LPGS to perform recovery processing.

[0176] The processing illustrated in FIGS. 8 to 10 can be realized by the circuit configurations and controls illustrated in FIGS. 12 to 17.

[0177] Thus, according to the modified example of the first embodiment of the present technology, since both the volatile memory circuit 530 and the non-volatile memory circuit 570 are arranged within the same register 500, there is no need to provide a volatile register and a non-volatile register separately.

[0178] 2. Second Embodiment In the first embodiment described above, data is saved to the non-volatile register file 410. However, it is also possible to provide a non-volatile memory including multiple banks and save data to the currently active bank. The semiconductor chip 200 in this second embodiment differs from the first embodiment in that data is saved to the currently active bank among the multiple banks.

[0179] 18 is a block diagram showing a configuration example of a storage unit 400 according to the second embodiment of the present technology. The storage unit 400 according to the second embodiment includes a nonvolatile memory 430 and a volatile memory 480. The nonvolatile memory 430 includes an address decoder 431, a bank number decoder 432, a memory cell array 433, and an output selector 434. The memory cell array 433 has a plurality of memory cells (not shown) arranged in a two-dimensional lattice pattern. The memory cell array 433 is divided into N (N is an integer equal to or greater than 2) nonvolatile memory banks 435.

[0180] The address decoder 431 receives the address ADDR ＮＶ is decoded to obtain a K-bit one-hot signal DEC Ａ The address decoder 431 generates a one-hot signal DEC Ａ is supplied to the memory cell array 433 and the output selector 434 .

[0181] The bank number decoder 432 decodes the bank number BN from the access control unit 310 and outputs an N-bit one-hot signal DEC Ｂ This bank number BN indicates the number of the bank currently being executed among the N bits. Of the N bits, only the bit corresponding to the bank number BN is set to a logical value of "1", and the remaining bits are set to a logical value of "0". This bank number decoder 432 generates a one-hot signal DEC Ｂ is supplied to the memory cell array 433 and the output selector 434 .

[0182] The output selector 434 selects the one-hot signal DEC Ａ and DEC ＢThe output selector 434 selects one of the nonvolatile register output signals NVQ of each memory cell based on the one-hot signal DEC. Ｂ , the nonvolatile memory bank 435 corresponding to the bit with the logic value "1" is selected, and the one-hot signal DEC Ａ , the output selector 434 selects a memory cell corresponding to a bit with a logic value of “1.” The output selector 434 then outputs the output signal (NVQ) of the selected memory cell to the volatile memory 480.

[0183] On the other hand, the memory cell array (not shown) in the volatile memory 480 is not divided into multiple banks. The volatile memory 480 also holds a tag bit for each address, as in the first embodiment. The memory capacity of each of the nonvolatile memory banks 435 is the same as that of the volatile memory 480.

[0184] 19 is a block diagram showing an example configuration of a power interruption recovery support CPU system 300 according to a second embodiment of the present technology. This power interruption recovery support CPU system 300 differs from the first embodiment in that it further includes a BN register 320 and further includes a bank switching control unit 314 within the access control unit 310.

[0185] The bank switching control unit 314 switches the bank during execution as necessary, and stores the bank number BN of the bank during execution in a BN register 320.

[0186] In the second embodiment, the write processing unit 311 acquires the bank number BN of the active bank by referring to the BN register 320, and writes the write data to the same address in the volatile memory 480 as the active bank.

[0187] The read processing unit 312 also references the BN register 320 to acquire the current bank number BN, and reads and compares the read data from the volatile memory 480 and the current bank. If the read data does not match, the volatile memory 480 controls the volatile memory 480 to update the corresponding tag bit to a logical value of "1."

[0188] The save / restore processing unit 313 performs a save process to a bank when, for example, a task switch is performed by an interrupt handler or a drop in power supply voltage occurs. In this save process, the save / restore processing unit 313 writes read data read from the same address in the volatile memory 480 to an address of the bank currently being executed whose corresponding tag bit has a logical value of "1" using a write pulse P2. In particular, when the power supply voltage drops, the save / restore processing unit 313 compares the read data as a verify every time it writes, and if the data do not match, it repeats the write and verify process until the write is complete.

[0189] In the second embodiment, task switching is not performed by an OS (Operation System) kernel, although a configuration in which task switching is performed by an OS kernel will be described later.

[0190] The save / restore processor 313 performs recovery processing when an interrupt process by an interrupt handler ends, when the power supply voltage rises, etc. In this recovery processing, the save / restore processor 313 writes data read from all addresses of the bank to be restored indicated by the bank number BN updated by the interrupt in the case of the interrupt process, or of the bank currently being restored in the case of a power supply voltage rise, etc., to the volatile memory 480, and initializes each tag bit to the logical value "0." The save / restore processor 313 compares the read data as a verify every time it writes, and if there is a mismatch, it repeats the write and verify until the write is complete.

[0191] Although the nonvolatile memory 430 is divided into a plurality of banks, the present invention is not limited to this configuration. A nonvolatile register file or a nonvolatile RAM may be divided into a plurality of banks and used as a save destination.

[0192] 20 is a diagram showing an example of the configuration of the BN register 320 according to the second embodiment of the present technology. The BN register 320 includes a BN1 register and a BN2 register. The size of each register is, for example, 16 bits.

[0193] For simplicity, the interrupt numbers are assumed to be, for example, 1 to 15. A fixed priority system is used, where the larger the interrupt number, the higher the interrupt priority. Note that a round-robin system may be used instead of the fixed priority system.

[0194] Furthermore, HE01 to HE15, which set whether to allow or prohibit bank use for each interrupt number, are assigned to bits 1 to 15 of the BN1 register. Each of HE01 to HE15 is set to a logical value of "0" when the corresponding bank is prohibited from use, and a logical value of "1" when the bank is permitted to be used. Bit 0 of the BN1 register is a reserved bit.

[0195] The BN2 register also has a field for holding a bank enable BNE and a field for holding the current bank number BN.

[0196] The size of the bank enable BNE is, for example, 2 bits. If the use of a bank is prohibited for all interrupts, the bank enable BNE is set to "00" in binary. If the use of a bank is permitted for all interrupts except for NMI (Non Maskable Interrupt), the bank enable BNE is set to "01" in binary. If the permission or prohibition of bank use follows the setting of the BN1 register, the bank enable BNE is set to "11" in binary. The value "10" in binary is reserved for the bank enable BNE.

[0197] The bank number BN field holds the bank number currently being executed or the first address of the bank currently being executed. For simplicity, we will assume that there are 16 banks, and that the bank numbers correspond to the interrupt numbers. Bank number "0" is assigned, for example, to initialization processing from startup before an interrupt is accepted.

[0198] Even when using the write pulse P1 during the save operation, a method of suppressing write errors by duplicating each bank of the nonvolatile memory 430, as described in Japanese Patent Application Laid-Open No. 2018-0215777, is conceivable. However, this method increases the area and power consumption of the nonvolatile memory 430 due to the duplication. In contrast, in the second embodiment, in which writing is performed using a high-voltage write pulse P2 during the save operation, bank duplication is not necessary. Therefore, while suppressing write errors, the area and power consumption of the nonvolatile memory 430 can be reduced compared to Japanese Patent Application Laid-Open No. 2018-0215777.

[0199] In the second embodiment, when data is saved to a bank, the data is written to the mismatched address among all addresses of that bank. This makes it possible to reduce rush current during saving even in a multi-bank configuration, just like in the first embodiment.

[0200] As described above, according to the second embodiment of the present technology, the backup / restore processing unit 313 writes data to the mismatched addresses among all addresses of the bank when backing up to the bank, thereby reducing the rush current during backup even in a multi-bank configuration.

[0201] [Modification] The second embodiment described above does not support task switching by the OS kernel, but this is not a limitation. The semiconductor chip 200 in this modification of the second embodiment differs from the second embodiment in that it also supports task switching by the OS kernel.

[0202] 21 is a diagram illustrating an example of a configuration of the BN register 320 according to a modification of the second embodiment of the present technology. In the figure, "a" illustrates an example of the data structure of the BN register 320, and "b" illustrates an example of a configuration of the associative memory.

[0203] As shown in the example of a in the figure, the BN register 320 in the modified example of the second embodiment includes a BN1 register, a BN(i) sub-register, a BN2 register, and an associative memory BN0, where i is an integer from 0 to 15. The data size of each of the BN1 register, the BN(i) sub-register, and the BN2 register is, for example, 16 bits.

[0204] For simplicity, the hardware interrupt numbers range from 1 to 15, and the OS interrupt numbers range from 1 to 255. The higher the number, the higher the interrupt priority, and hardware interrupts have higher priority than OS interrupts. A fixed priority system is used between hardware interrupts and between OS interrupts, but a round-robin system can also be used.

[0205] For each interrupt number, permission or prohibition of bank use is set. HE1 to HE15 are assigned to bits 1 to 15 of the BN1 register, and OSE1 to OSE255 are assigned to each bit of the 16 BN1(i) sub-registers.

[0206] Each of HE01 to HE15 is set to a logical value "0" when the corresponding bank is prohibited from use, and to a logical value "1" when the bank is permitted to be used. The 0th bit of the BN1 register is a reserved bit.

[0207] Each of OSE1 to OSE255 is set to a logical value "0" when the corresponding bank is prohibited from use, and to a logical value "1" when the bank is permitted to be used. The 0th bit of the BN1(0) sub-register is a reserved bit.

[0208] The BN2 register also has a field for holding a bank enable BNE and a field for holding the current bank number BN.

[0209] The size of the bank enable BNE is, for example, 2 bits. If the use of a bank is prohibited for all interrupts, the bank enable BNE is set to "00" in binary. If the use of a bank is permitted for all interrupts except NMI, the bank enable BNE is set to "01" in binary. If the permission or prohibition of bank use follows the settings of the BN1 register and the BN(i) subregister, the bank enable BNE is set to "11" in binary. The value "10" in binary is reserved for the bank enable BNE.

[0210] The bank number BN field holds the bank number currently being executed or the leading address of the bank currently being executed.

[0211] For simplicity, let us assume that there are 272 banks, and for example, of the bank numbers 0 to 271, 1 to 15 correspond to hardware interrupt numbers, and 17 to 271 correspond to OS interrupt numbers. Bank number 0 is assigned, for example, to initialization processing from startup before accepting an interrupt and initialization processing before OS startup. Bank number 16 is assigned, for example, to processing from OS startup until task execution begins.

[0212] The associative memory BN0 is a memory for registering task numbers used in task switching in the OS kernel as additional interrupt numbers.

[0213] As shown in FIG. 1B, the associative memory BN0 includes 255 nonvolatile registers 321, a volatile register 322, and an encoder 323.

[0214] The bank switching control unit 314 can store (in other words, register) task numbers in each of the 255 nonvolatile registers 321. OS interrupt numbers ranging from 1 to 255 correspond to the addresses of each of these nonvolatile registers 321. The bank switching control unit 314 can also generate query search data that specifies one of the nonvolatile registers 321 and store it in the volatile register 322. The encoder 323 outputs the address of the nonvolatile register 321 that matches the query search data as the corresponding OS interrupt number. In the case of a fixed priority system, the priority of a task number can be changed by changing the registration address of the task number.

[0215] With the configuration illustrated in the figure, the bank switching control unit 314 can convert a task number into an OS interrupt number using the content addressable memory BN0. If the use of a bank corresponding to the OS interrupt number is permitted, the bank switching control unit 314 can store the bank number of that bank in the BN register 320 as being in execution.

[0216] The save / restore processing unit 313 can also perform save processing when task switching occurs in the OS kernel, in addition to task switching by an interrupt handler or a drop in power supply voltage, for example.

[0217] As described above, according to the modified example of the second embodiment of the present technology, the BN(i) sub-register and the associative memory BN0 are added to the BN register 320, thereby enabling task switching by the OS kernel to be supported.

[0218] 3. Third Embodiment In the first embodiment described above, non-volatile register file 410 and volatile register file 450 are provided, but these can be used as CPU register files within the CPU. Semiconductor chip 200 in this third embodiment differs from the first embodiment in that non-volatile register file 410 and volatile register file 450 are used as CPU register files.

[0219] 22 is a block diagram showing an example of a configuration of a CPU system 300 for recovering from power interruption according to a third embodiment of the present technology. The CPU system 300 for recovering from power interruption according to the third embodiment includes a program ROM (Read Only Memory) 331, a data save / recovery sequencer 332, an instruction fetch decoder 333, an address calculation circuit 334, a storage unit 400, and a calculation circuit 335.

[0220] The storage unit 400 in the third embodiment includes, as in the first embodiment, a non-volatile register file 410 and a volatile register file 450. These are used as CPU register files.

[0221] The program ROM 331 stores programs executed by the CPU.

[0222] The data save / restore sequencer 332 performs data save and restore processes when a power supply voltage drop occurs, when a task is switched by an interrupt handler, or periodically. A detection signal and an interrupt number are input to the data save / restore sequencer 332. The detection signal includes a power supply drop detection signal indicating the result of power supply drop detection, and a power supply rise detection signal indicating the result of power supply rise detection. The save and restore processes performed by the data save / restore sequencer 332 are the same as those described in the first embodiment.

[0223] The instruction fetch decoder 333 fetches and decodes instructions from the program ROM 331. The instruction fetch decoder 333 obtains the access control signal R / W and the address of the access destination by decoding an instruction instructing writing or reading, and supplies them to the storage unit 400.

[0224] The address calculation circuit 334 obtains the address of the register file by decoding an instruction.

[0225] The arithmetic circuit 335 performs various calculations as necessary. This arithmetic circuit 335 supplies initial value data and data obtained by calculations as write data to the storage unit 400. The arithmetic circuit 335 also receives read data from the storage unit 400 and performs various calculations on the read data.

[0226] The configuration illustrated in the figure makes it possible to realize the functions of the access control unit 310 illustrated in FIG.

[0227] 23 is a diagram showing a list of registers according to the third embodiment of the present technology. At least some of the registers shown in the diagram are arranged in each of the non-volatile register file 410 and the volatile register file 450.

[0228] For example, general-purpose registers, stack pointer registers, program counter registers, saved program counter registers, processor status word registers, and saved status registers are used. In addition, procedure registers, multiplication registers, base registers, vector base registers, read data buffer registers, and write data buffer registers can also be used.

[0229] General-purpose register R ０ From R ｎ－２ is a register that can be used as both an address register and a data register. The stack pointer register SP is a register that indicates the address of the stack area that can be stacked. For example, R ｎ－１ can be used as the SP. The program counter register PC is a register that indicates the address of the instruction executed by the CPU. The saved program counter register BPC is a register that saves the program counter when a general exception request or interrupt request is accepted. The processor status word register PSW is a status register that stores the results of instruction execution and the status of the CPU. The saved status register BPSW is a register that saves the PSW when a general exception request or interrupt request is accepted.

[0230] The procedure register PR is a register that stores the return address when a subroutine is called. The multiplication registers MACH and MACL are registers that store the results of multiplication and multiply-accumulate operations. The base register GBR is a register that stores the base address for the indirect addressing mode. The vector base register VBR is a register that stores the base address of the exception processing handler. The read data buffer register RDR is a register that stores read data from memory. The write data buffer register WDR is a register that stores write data to memory.

[0231] In the third embodiment, the CPU may be configured in the following manner.

[0232] First, in the interrupt vector method, the BN register 320 and the interrupt vector are configured as nonvolatile registers such as nonvolatile multi-bit registers. The access control unit 310 repeats writing and read verification until the writing is successful. In addition, the control registers related to access to the nonvolatile memory are also configured as similar nonvolatile registers.

[0233] Next, when an interrupt is executed with an interrupt number that is disallowed by the BN register 320, the program is executed using only the volatile registers. This can be used, for example, to execute a restart handler that is kicked off by an interrupt caused by a voltage rise detection signal when power is restored from a power cut. In the case of a single register, an interrupt number is not assigned, so a control register that registers an interrupt number that involves accessing non-volatile memory is installed in the storage unit 400.

[0234] Consider a case where the program resumes from the program context where the power interruption occurred. In this case, control and status registers in the I / O peripherals, DMA (Direct Memory Access) controller, and interrupt controller that may be set up until the context is reached are located in the storage unit 400. These control and status registers may be implemented using either the method proposed in FIGS. 3 and 4 or a nonvolatile memory method that repeats writing and reading verification until the writing is successful.

[0235] The BN register 320 can also have three fields for specifying the following for each bank. The first field is a field that can specify whether to allow or disallow interrupt numbers. If all are disallowed, the program will be executed using only volatile memory.

[0236] The second field is a field for specifying whether or not to allow a task switching interrupt by registering a task number used in task switching in the OS kernel as an additional interrupt number in the content addressable memory.

[0237] The third field is the BN field. In the case of a register file, the BN value is used to specify a bank number, and in the case of a scratchpad memory or main memory, the BN value is used as the starting address of the bank.

[0238] 24 is a block diagram showing an example of the configuration of the storage unit 400 according to the third embodiment of the present technology. As shown in the figure, the nonvolatile register file 410 stores, for example, a general-purpose register R ０ From R ｎ－２ and a stack pointer register SP. Furthermore, the non-volatile register file 410 includes a program counter register PC, a processor status word register PSW, a procedure register PR, a base register GBR, and a vector base register VBR. The volatile register file 450 includes R ０ From R ｎ－２ In addition to the SP, PC, PSW, PR, GBR, and VBR, each register holds a tag bit TAG.

[0239] As described above, by using the nonvolatile register file 410 and the volatile register file 450 as CPU register files, it is possible to reduce rush current during saving in a single-task CPU.

[0240] As shown in FIG. 25, a modification of the first embodiment in which a nonvolatile register and a volatile register are integrated can be applied to the third embodiment.

[0241] As described above, according to the third embodiment of the present technology, the non-volatile register file 410 and the volatile register file 450 are used as CPU register files, so that rush current during saving can be reduced in a single-task CPU.

[0242] In the third embodiment described above, data is saved to the nonvolatile register file 410. However, it is also possible to provide a nonvolatile memory including a plurality of banks and save data to the bank that is currently being executed. The semiconductor chip 200 in this modification of the third embodiment differs from the third embodiment in that data is saved to the bank that is currently being executed among the plurality of banks.

[0243] 26 is a block diagram showing an example configuration of a storage unit 400 in a modification of the third embodiment of the present technology. The storage unit 400 in this modification of the third embodiment includes a nonvolatile memory 430 and a volatile memory 480. The nonvolatile memory 430 includes N nonvolatile memory banks 435.

[0244] The volatile memory 480 and the non-volatile memory bank 435 each have, for example, R ０ From R ｎ－２ , SP, PC, PSW, PR, GBR, and VBR registers. Volatile memory 480 also includes a tag bit TAG for each register.

[0245] 27 is a block diagram showing an example of a configuration of a power interruption recovery support CPU system 300 according to a modification of the third embodiment of the present technology. The power interruption recovery support CPU system 300 according to the modification of the third embodiment differs from the third embodiment in that it includes a data save / recovery / bank switching sequencer 336 instead of the data save / recovery sequencer 332.

[0246] The data save / restore / bank switching sequencer 336 performs bank switching in addition to data save and restore processing. The data save / restore / bank switching sequencer 336 includes the BN register 320 (not shown) described in the modified example of the second embodiment.

[0247] The data save / restore / bank switching sequencer 336 receives the detection signal and interrupt number of the third embodiment as well as the OS task number.

[0248] When an interrupt number or OS task number is input, the data save / restore / bank switching sequencer 336 compares the priority of that number with the priority of the interrupt number (hardware interrupt number or OS interrupt number) corresponding to the BN in the BN2 register. If the priority of the input number is higher, the data save / restore / bank switching sequencer 336 selects the bank corresponding to that number as the active bank and performs data save processing, restoration processing, and bank switching.

[0249] On the other hand, if the input number has a lower priority, the data save / restore / bank switching sequencer 336 waits for the completion of the currently running process corresponding to the BN before switching to the bank corresponding to the input number. Alternatively, the data save / restore / bank switching sequencer 336 does not accept interrupt nesting. Alternatively, the data save / restore / bank switching sequencer 336 may accept interrupt nesting and store the number in a FIFO (First In, First Out) buffer.

[0250] Furthermore, upon receiving a detection signal of a drop or rise in the power supply voltage, the data save / restore / bank switching sequencer 336 performs the same save processing and restore processing as in the second embodiment with a multi-bank configuration.

[0251] In this way, according to the modified example of the third embodiment of the present technology, the data backup / restore / bank switching sequencer 336 switches banks to back up data when an interrupt occurs, etc., thereby reducing rush current during backup in a multitasking CPU.

[0252] 4. Fourth Embodiment In the second embodiment described above, the nonvolatile memory 430 has a multi-bank configuration, but the memory may be shared by multiple entities, such as the main memory or the scratch pad memory. The semiconductor chip 200 in this fourth embodiment differs from the second embodiment in that shared resources are provided in each of the volatile memory 480 and the nonvolatile memory 430.

[0253] 28 is a block diagram showing a configuration example of a non-volatile memory 430 according to the fourth embodiment of the present technology. The non-volatile memory 430 according to the fourth embodiment includes a non-volatile memory shared resource 441 and a non-volatile memory unshared resource 442. Note that address decoders and output selectors in each resource are omitted in the figure.

[0254] The nonvolatile memory shared resource 441 is a memory area that stores shared data shared by multiple entities (such as tasks and interrupt handlers). The nonvolatile memory unshared resource 442 is a memory area that stores data that does not fall under the category of shared data, and includes N nonvolatile memory unshared banks 443. Note that instead of nonvolatile memory, a nonvolatile register file may have a multi-bank configuration, and nonvolatile shared resources and unshared banks may be provided.

[0255] The nonvolatile memory shared resource 441 is an example of a nonvolatile shared resource as defined in the claims. The nonvolatile memory unshared bank 443 is an example of a nonvolatile unshared bank as defined in the claims.

[0256] 29 is a block diagram showing a configuration example of a volatile memory 480 according to the fourth embodiment of the present technology. The volatile memory 480 according to the fourth embodiment includes a volatile memory shared resource 481 and a volatile memory non-shared resource 482. Note that address decoders and output selectors in each resource are omitted in the figure.

[0257] The volatile memory shared resource 481 is a memory area that stores shared data, and the volatile memory non-shared resource 482 is a memory area that stores data that does not fall under the category of shared data. Note that a volatile register file can be used instead of a volatile memory to provide volatile shared resources and non-shared resources.

[0258] The volatile memory shared resource 481 and the nonvolatile memory shared resource 441 have the same size and number of addresses. The volatile memory unshared resource 482 and the nonvolatile memory unshared bank 443 also have the same size and number of addresses.

[0259] The volatile memory shared resource 481 is an example of a volatile shared resource as defined in the claims, and the volatile memory non-shared resource 482 is an example of a volatile non-shared resource as defined in the claims.

[0260] 30 is a block diagram showing an example configuration of a power interruption recovery-compatible CPU system 300 according to a fourth embodiment of the present technology. The power interruption recovery-compatible CPU system 300 according to the fourth embodiment includes a program ROM 331, a data save / restore / bank switching sequencer 336, an instruction fetch decoder 333, an address calculation circuit 334, and an arithmetic circuit 335. The power interruption recovery-compatible CPU system 300 also includes a volatile memory shared resource addressing register 340, a non-volatile memory shared resource 441, and a non-volatile memory unshared resource 442. The power interruption recovery-compatible CPU system 300 also includes a volatile memory shared resource 481, a volatile memory unshared resource 482, an address converter 337, a data path 338, and an address path 339.

[0261] As described above, the non-volatile memory non-shared resource 442 has a multi-bank configuration, and each register (such as a program counter register) in the CPU register file described above can be placed in each bank and in the volatile memory non-shared resource 482. Furthermore, the volatile memory shared resource 481 and the volatile memory non-shared resource 482 hold a tag bit for each address.

[0262] The address converter 337 may be implemented as a combinational circuit with a flip-flop output. Alternatively, the address converter 337 may be implemented as a register file or SRAM in which the first address of the non-volatile memory unshared bank 443 is registered using the interrupt number as an address. The address converter 337 may perform address conversion using an address conversion mechanism in the number of cycles required for data transmission and reception via the bus.

[0263] The volatile memory shared resource address specification register 340 stores the initial value of the start address of the volatile memory shared resource 481 .

[0264] When an interrupt number or an OS task number is input, the data save / restore / bank switching sequencer 336 performs the data save process, restore process, and bank switching described above with reference to FIG.

[0265] The data backup / restore / bank switching sequencer 336 can also periodically perform data backup processing. For example, the data backup / restore / bank switching sequencer 336 periodically checks the tag bit of the volatile memory and writes data at an address where the tag bit has a logical value of "1" from the volatile memory to the nonvolatile memory while gradually increasing the voltage of the write pulse. The data backup / restore / bank switching sequencer 336 then checks whether the read data matches, clears the tag bit for which writing has been completed to a logical value of "0," and stops increasing the voltage when the writing has been successful for all bits.

[0266] Furthermore, upon receiving a detection signal for a drop or rise in the power supply voltage, the data save / restore / bank switching sequencer 336 performs the same save and restore processes as in the second embodiment with a multi-bank configuration. This enables recovery when power is cut off in a multitasking environment, even if a write error to the nonvolatile memory occurs.

[0267] As described above, shared data is managed by the volatile memory shared resource 481 and the nonvolatile memory shared resource 441, and other data is managed by the volatile memory unshared resource 482 and the nonvolatile memory unshared bank 443. This ensures the consistency of common data in the shared resources.

[0268] The fourth embodiment can also be applied to the third embodiment.

[0269] As described above, according to the fourth embodiment of the present technology, the volatile memory 480 and the non-volatile memory 430 are each provided with shared resources and non-shared resources, so that the memory can be used more efficiently.

[0270] 5. Fifth Embodiment In the second embodiment of the multi-bank configuration described above, the semiconductor chip 200 performs data backup and recovery processes when the power supply voltage drops, assuming the presence of an auxiliary power supply. For example, an energy harvester can be used as this auxiliary power supply. The instantaneous power outage countermeasure system in this fifth embodiment differs from the second embodiment in that it uses an energy harvester.

[0271] 31 is a block diagram showing an example configuration of an instantaneous power interruption countermeasure system 100 according to the fifth embodiment of the present technology. The instantaneous power interruption countermeasure system 100 includes a power supply drop / rise detection circuit 110, a semiconductor chip 200, a power supply control unit 120, and an energy harvester 130. The instantaneous power interruption countermeasure system 100 shown in the figure is applied to an industrial camera or the like.

[0272] The power supply voltage drop / rise detection circuit 110 detects whether the power supply voltage is below a threshold V ｌｗ２ The power supply voltage drop / rise detection circuit 110 detects whether the power supply voltage has dropped below a threshold V ｈｉｇｈ１The power supply voltage drop / rise detection circuit 110 detects that the power supply voltage has risen to a higher value. As described above, the detection signal includes a power supply drop detection signal and a power supply rise detection signal. The power supply voltage drop / rise detection circuit 110 supplies a power supply drop detection signal to the semiconductor chip 200 when it detects a power supply drop, and supplies a power supply rise detection signal to the semiconductor chip 200 when it detects a power supply rise. The power supply voltage drop / rise detection circuit 110 is an example of a detection circuit as defined in the claims.

[0273] The power supply control unit 120 detects whether the power supply voltage is a threshold V ｌｗ１ When the voltage V falls below the threshold V, the power from the energy harvester 130 is supplied to the power drop / rise detection circuit 110. ｌｗ１ is the threshold V ｌｗ２ The threshold value V ｌｗ１ is an example of the first threshold value described in the claims, and the threshold value V ｌｗ２ is an example of the second threshold value described in the claims.

[0274] The energy harvester 130 converts energy such as light, heat, and vibration generated in the surrounding environment into electrical energy.

[0275] Furthermore, the semiconductor chip 200 in the fifth embodiment holds a power-off nonvolatile flag bit in a nonvolatile register or memory, and the initial value of this power-off nonvolatile flag bit is initialized to a logical value of "0" at the time of the first startup.

[0276] 32 is a diagram illustrating an implementation example of an instantaneous power interruption countermeasure system 100 according to the fifth embodiment of the present technology. The instantaneous power interruption countermeasure system 100 includes diodes 141 to 144, pMOS transistors 151 and 152, capacitors 161 and 162, a power supply drop / rise detection circuit 110, a semiconductor chip 200, a power supply control unit 120, and an energy harvester 130.

[0277] The anode of the diode 141 is connected to the power supply voltage, and the cathode is connected to the power supply terminal of the power supply drop / rise detection circuit 110. The anode of the diode 142 is connected to the pMOS transistor 151, and the cathode is connected to the power supply terminal of the power supply drop / rise detection circuit 110.

[0278] The anode of the diode 143 is connected to the power supply voltage and power supply drop / rise detection circuit 110, and the cathode is connected to the capacitor 161 and the semiconductor chip 200. The anode of the diode 144 is connected to the pMOS transistor 152, and the cathode is connected to the capacitor 161 and the semiconductor chip 200.

[0279] The pMOS transistors 151 and 152 are inserted in series between the diodes 142 and 144. The gate of the pMOS transistor 151 is connected to the power supply voltage, and the gate of the pMOS transistor 152 is connected to the power supply drop / rise detection circuit 110. The connection node of the pMOS transistors 151 and 152 is connected to the power supply control unit 120. The capacitor 162 is connected to the connection node of the power supply control unit 120 and the energy harvester 130.

[0280] First, the power supply voltage is at the threshold V ｌｗ１ , the pMOS transistor 151 transitions to the ON state, and the power supply control unit 120 starts supplying power from the energy harvester 130 to the power supply drop / rise detection circuit 110 .

[0281] In addition, the power supply voltage is a threshold V ｌｗ２ When the voltage drops below this value, the power drop / rise detection circuit 110 detects the power drop and turns on the pMOS transistor 152. This causes the energy harvester 130 to start supplying power to the semiconductor chip 200.

[0282] When the semiconductor chip 200 receives the power drop detection signal, it executes the data saving process described above and updates the power cut-off nonvolatile flag bit to a logical value of "1." This power cut-off nonvolatile flag bit is initialized to a logical value of "0" when the power supply voltage rises.

[0283] During the retraction, the semiconductor chip 200 stops the CPU from fetching instructions and completes the execution of the CPU pipeline, during which necessary memory updates are performed.

[0284] Then, as described above during the save process, the semiconductor chip 200 writes the data at the address where the tag bit has a logical value of "1" from the volatile register file 450 to the non-volatile register file 410 using the write pulse P2. If the write is successful, the semiconductor chip 200 clears the tag bit at that address to a logical value of "0".

[0285] Then, when the writing is completed, the bank switching control unit 314 in the semiconductor chip 200 notifies the save / restore processing unit 313 of the completion. The save / restore processing unit 313 notifies the power drop / rise detection circuit 110 of the completion of the writing, and the circuit turns off the pMOS transistor 152 to shut off the power supply.

[0286] Then, the power supply voltage reaches the threshold V ｈｉｇｈ１ When the power supply voltage exceeds the threshold, the power supply drop / rise detection circuit 110 detects this and sends a power supply rise detection signal to the semiconductor chip 200. When the semiconductor chip 200 receives the power supply rise detection signal, it starts a restart handler and checks the power shutdown nonvolatile flag bit. If the power shutdown nonvolatile flag bit is a logical value "1", the semiconductor chip 200 writes back the value of the nonvolatile memory bank specified by the BN register 320 to the volatile memory. On the other hand, if the power shutdown nonvolatile flag bit is a logical value "0", the semiconductor chip 200 executes a normal restart sequence that involves initializing the BN register 320. Here, it is assumed that the program that performs the above-mentioned processing is stored in nonvolatile memory and executed on that memory.

[0287] The instantaneous power outage countermeasure system 100 illustrated in the figure eliminates the need for rollback processing in the CPU program when power is restored, and can prevent unauthorized re-execution. It also eliminates the need to insert checkpoints for rollback processing in the CPU program. In other words, it is no longer necessary to add checkpoint code.

[0288] Next, a process specific to when a CIS is used as the semiconductor chip 200 will be described.

[0289] First, regarding the register settings of the digital signal processing unit 220, these are implemented in nonvolatile memory, and are set to repeat read verify and rewrite until writing is completed at the time of setting in preparation for power shutdown. Also, after the power supply voltage rises, the CIS checks the power shutdown nonvolatile flag bit in the resume handler, and if the value is logical "1", it does nothing and performs the initial setting process.

[0290] Next, since frame synchronization is essential for the line memory used to store image data, the CIS restarts processing from a new frame by discarding or overwriting the line memory after restart. Therefore, the line memory can be used as volatile memory without any problems. In the restart handler after power is restored, the CIS initializes the line memory regardless of the value of the power-off non-volatile flag bit.

[0291] Next, consider the case where a frame memory for storing pixel data is installed. In this case, the CIS allocates the frame memory within the storage unit 400 and simultaneously writes data to both the volatile and non-volatile frame memories. Each time the frame memory is read in subsequent processing, the CIS compares the read data and updates the tag bit. When data for one frame memory is stored, the CIS sets the frame storage flag to a logical value of "1" and clears it to a logical value of "0" when a new write occurs. Furthermore, if power is interrupted during signal processing after data for one frame memory has been stored, the CIS resumes processing from the stored data or from the frame after restart. These options can be selected by the user via register settings.

[0292] After receiving the voltage drop detection signal, the CIS starts the frame memory evacuation process and checks the frame accumulation flag. If the frame accumulation flag is a logical "0," the CIS leaves the nonvolatile frame flag at its initial value and does nothing. On the other hand, if the frame accumulation flag is a logical "1," the CIS writes data at the address where the tag bit in the volatile frame memory is a logical "1" to the nonvolatile frame memory using write pulse P2 and clears the tag bit to a logical "0" once the write is complete. The CIS further retains the nonvolatile frame flag and, if all writes are successful, writes a "1" to the nonvolatile frame flag. If the power-off nonvolatile flag bit is a logical "0," the nonvolatile frame flag is initialized to a "0." If the power-off nonvolatile flag bit is a logical "0," the nonvolatile frame flag is cleared to a "0" after reading it. In other words, if the writing of the logical "1" is not completed within the power supply period of the auxiliary power source (such as an energy harvester), the nonvolatile frame flag remains a logical "0."

[0293] After power is restored, the CIS checks the power shutdown nonvolatile flag bit in the resume handler, and if the value is logical "0", it initializes the nonvolatile frame memory regardless of the register setting value set by the user. On the other hand, if the power shutdown nonvolatile flag bit value is logical "1", the CIS checks the nonvolatile frame flag, and if the value is logical "0", it initializes the nonvolatile frame memory regardless of the user register setting value. If the nonvolatile frame flag is logical "1", the CIS resumes from processing the stored data or from the frame after restart. These can be selected by the user via register settings.

[0294] Next, consider the case where an AE control unit is installed. In this case, the CIS writes statistical processing result information used for adjusting the analog and digital gains in AE control to the volatile memory 480 and the nonvolatile memory 430. After rebooting, the user can select, by register setting, whether to use the statistical processing result information stored in the nonvolatile memory 430 or a separately set default value for gain adjustment.

[0295] Upon receiving the voltage drop detection signal, the CIS saves the statistical processing result information stored in the AE control unit. As described above, the CIS writes data at addresses in the volatile memory 480 where the tag bit has a logical value of "1" to the nonvolatile memory bank 435 using write pulse P2, and clears the tag bit to a logical value of "0" once the write is complete. The CIS also retains the statistical information nonvolatile flag bit, and if all writes are successful, writes a logical value of "1" to the statistical information nonvolatile flag bit. If the power-off nonvolatile flag bit has a logical value of "0," the statistical information nonvolatile flag bit is initialized to a logical value of "0." If the power-off nonvolatile flag bit has a logical value of "1," the statistical information nonvolatile flag bit is cleared to a logical value of "0" after reading it. In other words, if the writing of the logical value "1" is not completed within the power supply period from the auxiliary power source, the statistical information nonvolatile flag bit remains at a logical value of "0."

[0296] Then, after power is restored, the CIS checks the power shutdown non-volatile flag bit in the resume handler. If the power shutdown non-volatile flag bit is a logical value of "0," the CIS uses the default value for gain adjustment regardless of the register setting value set by the user and initializes the statistical processing result information. If the power shutdown non-volatile flag bit is a logical value of "1," the CIS checks the statistical information non-volatile flag bit. If the statistical information non-volatile flag bit is a logical value of "0," the CIS uses the default value for gain adjustment regardless of the register setting value set by the user and initializes the statistical processing result information. If the statistical information non-volatile flag bit value is a logical value of "1," the CIS uses either the statistical processing result information or a separately set default value for gain adjustment according to the register setting value set by the user.

[0297] The above-described processing makes it possible to realize a CIS that can recover from a power outage appropriately and quickly.

[0298] The fifth embodiment can also be applied to the first embodiment, which does not have a multi-bank configuration, and the fifth embodiment can also be applied to the third embodiment and the fourth embodiment.

[0299] In this way, according to the fifth embodiment of the present technology, when the power supply voltage is equal to or lower than the threshold V ｌｗ１When the power supply voltage falls below 100 V, the power supply control unit 120 starts supplying power from the energy harvester 130, which eliminates the need for rollback processing upon recovery and prevents unauthorized re-execution.

[0300] In the fifth embodiment, the power supply control unit 120 is supplied with power from the energy harvester 130, but there is a risk that the energy generated in the environment may be insufficient. The instantaneous power outage countermeasure system 100 in this modification of the fifth embodiment differs from the fifth embodiment in that it further includes a storage battery.

[0301] FIG. 33 is a block diagram illustrating a configuration example of an instantaneous power interruption prevention system 100 according to a modified example of the fifth embodiment of the present technology.

[0302] FIG. 34 is a diagram illustrating an implementation example of an instantaneous power failure prevention system 100 according to a modified example of the fifth embodiment of the present technology.

[0303] As illustrated in FIGS. 33 and 34, the instantaneous power failure countermeasure system 100 in the modified example of the fifth embodiment differs from the fifth embodiment in that it further includes a storage battery 170.

[0304] The power supply voltage is the threshold V ｌｗ１ , the pMOS transistor 151 transitions to the ON state, and the power supply control unit 120 starts supplying power from the energy harvester 130 or the storage battery 170 to the power supply drop / rise detection circuit 110 .

[0305] Thus, according to the modified example of the fifth embodiment of the present technology, the power supply control unit 120 supplies power from the energy harvester 130 or the storage battery 170, and therefore can continue to supply power even when there is a shortage of energy generated in the environment.

[0306] Note that the above-described embodiment shows an example for realizing the present technology, and the matters in the embodiment and the matters specifying the invention in the claims correspond to each other. Similarly, the matters specifying the invention in the claims and the matters in the embodiment of the present technology having the same name correspond to each other. However, the present technology is not limited to the embodiment, and can be realized by applying various modifications to the embodiment within the scope of the gist thereof.

[0307] The effects described in this specification are merely examples and are not limiting, and other effects may also be present.

[0308] The present technology may also be configured as follows: (1) A semiconductor chip comprising: a volatile storage unit; a nonvolatile storage unit; a write processing unit that writes write data to the same address in the volatile storage unit and the nonvolatile storage unit; a read processing unit that reads data from the address in the volatile storage unit as first read data and reads data from the address in the nonvolatile storage unit as second read data; and a save / restore processing unit that performs a save process of writing the first read data to an address among all addresses in the nonvolatile storage unit where the corresponding second read data does not match the first read data. (2) The semiconductor chip according to (1), wherein the write processing unit writes the write data using a first write pulse, and the save / restore processing unit writes the first read data using a second write pulse having at least one of a pulse width and a voltage greater than that of the first write pulse. (3) The semiconductor chip according to (2), wherein the save / restore processing unit further performs a restore process of writing read data newly read from the nonvolatile storage unit to the volatile storage unit after the save process. (4) The semiconductor chip according to (3), wherein the volatile memory unit holds tag bits of an initial value for each address, the write processing unit writes the write data to the address using the first write pulse and updates the corresponding tag bits to a value different from the initial value, the read processing unit updates the corresponding tag bits to the initial value when the first read data and the second read data match, and the save / restore processing unit writes the first read data to an address of all the addresses where the corresponding tag bits are different from the initial value using the second write pulse. (5) The semiconductor chip according to (4), wherein the non-volatile memory unit includes a plurality of non-volatile banks.(6) The semiconductor chip according to any one of (1) to (6), further comprising a bank switching control unit that switches a running bank among the plurality of non-volatile banks, wherein the save / restore processing unit performs the save process of writing the first read data to an address of the running bank, among all addresses of which the corresponding tag bit is different from the initial value, using the second write pulse, and the restore process of writing read data read from a bank to be restored, which is indicated by a bank number BN updated by the bank switching, to the volatile storage unit after the save process, and updating the corresponding tag bit to the initial value. (7) The semiconductor chip according to any one of (1) to (6), wherein the volatile storage unit and the non-volatile storage unit each include at least one of a general-purpose register, a stack pointer register, a program counter register, a saved program counter register, a processor status word register, a saved status register, a procedure register, a multiplication register, a base register, a vector base register, a read data buffer register, and a write data buffer register. (8) The semiconductor chip according to any one of (1) to (7), wherein the volatile memory unit includes a volatile shared resource that stores shared data shared by a plurality of entities, and a volatile non-shared resource that stores data other than the shared data, and the non-volatile memory unit includes a non-volatile shared resource that stores the shared data, and a plurality of non-volatile non-shared banks that store data other than the shared data. (9) The semiconductor chip according to any one of (1) to (8), wherein the volatile memory unit includes a predetermined number of volatile registers, and the non-volatile memory unit includes a predetermined number of non-volatile registers. (10) The semiconductor chip according to (1), wherein the volatile memory unit includes a predetermined number of volatile memory circuits, and the non-volatile memory unit includes a predetermined number of non-volatile memory circuits, and the volatile memory circuits and the non-volatile memory circuits are arranged in the same register.(11) An instantaneous power failure response system comprising: a semiconductor chip including: a detection circuit that detects that a power supply voltage has dropped to a value lower than a second threshold, a volatile storage unit, a nonvolatile storage unit, a write processing unit that writes write data to the same address in the volatile storage unit and the nonvolatile storage unit, a read processing unit that reads data from the address in the volatile storage unit as first read data and reads data from the address in the nonvolatile storage unit as second read data, and a save / recovery processing unit that performs save processing, when the power supply voltage has dropped to a value lower than the second threshold, to write the first read data to an address among all addresses in the nonvolatile storage unit where the corresponding second read data does not match the first read data. (12) An instantaneous power failure response system according to (11), further comprising: an energy harvester; and a power supply control unit that supplies power from the energy harvester to the detection circuit when the power supply voltage falls below a first threshold that is higher than the second threshold. (13) The instantaneous power failure response system according to (12), further comprising a storage battery, wherein the power supply control unit supplies power from at least one of the energy harvester and the storage battery to the semiconductor chip when the power supply voltage falls below the first threshold. (14) A control method for a semiconductor chip, comprising: a write processing procedure for writing write data to the same address in a volatile storage unit and a non-volatile storage unit; a read procedure for reading data from the address in the volatile storage unit as first read data and reading data from the address in the non-volatile storage unit as second read data; and a save / restore processing procedure for performing save processing for writing the first read data to an address among all addresses in the non-volatile storage unit where the corresponding second read data does not match the first read data.

[0309] 100 Instantaneous power failure prevention system 110 Power supply drop / rise detection circuit 120 Power supply control unit 130 Energy harvester 141 to 144 Diodes 151, 152, 521 to 529 pMOS transistors 161, 162 Capacitors 170 Storage battery 200 Semiconductor chip 211 Vertical drive circuit 212 Timing control unit 213 DAC 214 Pixel array unit 215 Column signal processing unit 216 Horizontal transfer control unit 220 Digital signal processing unit 221 External setting input / output interface 222 External setting non-volatile register group 300 Power interruption recovery compatible CPU system 310 Access control unit 311 Write processing unit 312 Read processing unit 313 Save / recovery processing unit 314 Bank switching control unit 320 BN register 321, 420 Non-volatile register 322, 460 Volatile register 323 Encoder 331 Program ROM 332 Data save / restore sequencer 333 Instruction fetch decoder 334 Address calculation circuit 335 Calculation circuit 336 Data save / restore / bank switching sequencer 337 Address converter 338 Data bus 339 Address bus 340 Volatile memory shared resource address specification register 400 Storage unit 410 Non-volatile register file 411, 431, 451 Address decoder 412 Non-volatile register group 413, 434, 453 Output selector 414 Register group 421, 422, 461 to 464, 511 to 514 AND (logical product) gates 423, 424, 468 Selector 425 Non-volatile multi-bit flip-flop 430 Non-volatile memory 432 Bank number decoder 433 Memory cell array 435 Non-volatile memory bank 441 Non-volatile memory shared resource 442 Non-volatile memory non-shared resource 443 Non-volatile memory non-shared memory bank 450 Volatile register file 452 Volatile register group 454, 580 Comparator 465, 466 Logic gate 467, 581 OR (logical sum) gate 469 Volatile multi-bit flip-flop 470, 517 1-bit flip-flop 480 Volatile memory481 Volatile memory shared resource 482 Volatile memory non-shared resource 500 Register 515, 516 Logic gate 520 Embedded register 530 Volatile memory circuit 531 to 536 NAND (negative logical AND) gate 541 to 544 Inverter 551 to 554 Transmission gate 560 to 569 nMOS transistor 570 Nonvolatile memory circuit 571, 572 MTJ element 582 NXOR (negative exclusive OR) gate

Claims

1. A semiconductor chip comprising: a volatile memory unit; a non-volatile memory unit; a write processing unit that writes write data to the same address in the volatile memory unit and the non-volatile memory unit; a read processing unit that reads data from the address in the volatile memory unit as first read data and reads data from the address in the non-volatile memory unit as second read data; and a save / restore processing unit that performs save processing to write the first read data to an address among all addresses in the non-volatile memory unit where the corresponding second read data does not match the first read data.

2. The semiconductor chip according to claim 1, wherein the write processing unit writes the write data using a first write pulse, and the save / restore processing unit writes the first read data using a second write pulse having at least one of a pulse width and a voltage greater than that of the first write pulse.

3. The semiconductor chip according to claim 2, wherein the save / restore processing unit further performs a restore process in which, after the save process, the read data newly read from the nonvolatile storage unit is written to the volatile storage unit.

4. The semiconductor chip of claim 3, wherein the volatile memory unit holds an initial value of a tag bit for each address; the write processing unit writes the write data to the address using the first write pulse and updates the corresponding tag bit to a value different from the initial value; the read processing unit updates the corresponding tag bit to the initial value if the first read data and the second read data match; and the save / restore processing unit writes the first read data to an address of all the addresses where the corresponding tag bit is different from the initial value using the second write pulse.

5. The semiconductor chip according to claim 4, wherein the nonvolatile memory section includes a plurality of nonvolatile banks.

6. A semiconductor chip according to claim 5, further comprising a bank switching control unit that switches a running bank among the plurality of non-volatile banks, wherein the save / restore processing unit performs the save process of writing the first read data by the second write pulse to an address among all addresses of the running bank where the corresponding tag bit is different from the initial value, and the restore process of writing read data read from the bank to be restored specified by the bank switching after the save process to the volatile memory unit and updating the corresponding tag bit to the initial value.

7. The semiconductor chip according to claim 1, wherein each of the volatile storage unit and the non-volatile storage unit includes at least one of a general-purpose register, a stack pointer register, a program counter register, a saved program counter register, a processor status word register, a saved status register, a procedure register, a multiplication register, a base register, a vector base register, a read data buffer register, and a write data buffer register.

8. A semiconductor chip as described in claim 1, wherein the volatile memory unit includes a volatile shared resource that holds shared data shared by multiple entities and a volatile non-shared resource that holds data that does not fall under the shared data, and the non-volatile memory unit includes a non-volatile shared resource that holds the shared data and a plurality of non-volatile non-shared banks that hold data that does not fall under the shared data.

9. The semiconductor chip according to claim 1, wherein the volatile memory unit includes a predetermined number of volatile registers, and the nonvolatile memory unit includes a predetermined number of nonvolatile registers.

10. The semiconductor chip according to claim 1, wherein the volatile memory unit includes a predetermined number of volatile memory circuits, the nonvolatile memory unit includes a predetermined number of nonvolatile memory circuits, and the volatile circuits and the nonvolatile memory circuits are arranged in the same register.

11. A momentary power outage response system comprising: a semiconductor chip including: a detection circuit that detects that the power supply voltage has dropped to a value lower than a second threshold; a volatile memory unit; a non-volatile memory unit; a write processing unit that writes write data to the same address in the volatile memory unit and the non-volatile memory unit; a read processing unit that reads data from the address in the volatile memory unit as first read data and reads data from the address in the non-volatile memory unit as second read data; and a save / recovery processing unit that performs save processing to write the first read data to an address of all addresses in the non-volatile memory unit where the corresponding second read data does not match the first read data, when the power supply voltage has dropped to a value lower than the second threshold.

12. The instantaneous power outage response system according to claim 11, further comprising: an energy harvester; and a power supply control unit that supplies power from the energy harvester to the detection circuit when the power supply voltage falls below a first threshold value that is higher than the second threshold value.

13. The instantaneous power outage response system according to claim 12, further comprising a storage battery, wherein the power supply control unit supplies power from at least one of the energy harvester and the storage battery to the semiconductor chip when the power supply voltage falls below the first threshold.

14. A method for controlling a semiconductor chip comprising: a write processing procedure for writing write data to the same address in a volatile memory unit and a non-volatile memory unit; a read procedure for reading data from the address in the volatile memory unit as first read data and reading data from the address in the non-volatile memory unit as second read data; and a save / restore processing procedure for performing save processing for writing the first read data to an address among all addresses in the non-volatile memory unit where the corresponding second read data does not match the first read data.

Images