Semiconductor device

Abstract

The present invention enables stable performance of a determination operation in a comparator circuit. This semiconductor device is configured by including: a differential amplifier circuit having a three-stage circuit configuration between a power supply and a ground; and an output stage circuit provided at a rear stage of the differential amplifier circuit, the output stage circuit having a current-mirror type circuit configuration, and the circuit configuration between the power supply and the ground having a two-stage circuit configuration, in which a differential between a potential of a reference node of the differential amplifier circuit and a potential of a determination node is detected.

Description

Semiconductor Devices

[0001] The present invention relates to a semiconductor device.

[0002] One technology related to semiconductor devices is disclosed in the following Patent Document 1. Patent Document 1 describes a technology of "a comparator circuit in which the output stage circuit is a common-source circuit." This type of comparator circuit can be used, for example, in a control circuit (control IC) for synchronous rectification switching applications.

[0003] Japanese Patent Application Publication No. 7-245552

[0004] However, a control circuit (control IC) for synchronous rectification switching applications is required to operate over a wide voltage range. In such synchronous rectification switching applications, the comparator circuit described in Patent Document 1 has an output stage circuit configured as a common-source circuit, which creates a dead zone of the judgment node during low-voltage operation, making it difficult to stably perform judgment operations.

[0005] The present invention has been made in view of the above circumstances, and has as its object to enable a stable determination operation.

[0006] In order to solve the above problems, for example, the configuration described in the claims is adopted. The present application includes a plurality of means for solving the above problems, and one example thereof is a semiconductor device including a differential amplifier circuit having a three-stage circuit configuration between a power supply and ground, and an output stage circuit provided in the subsequent stage, wherein the output stage circuit has a current mirror type circuit configuration and the circuit configuration between the power supply and ground is a two-stage configuration, and the semiconductor device detects the difference between the potential of a determination node and the potential of a reference node of the differential amplifier circuit.

[0007] According to the present invention, in addition to the determination of the differential amplifier circuit, the output stage circuit at the subsequent stage performs a differential determination between the potential of the determination node of the differential amplifier circuit and the potential of the reference node, thereby enabling stable determination operation.

[0008] Problems, configurations, and effects other than those described above will become apparent from the following description of the mode for carrying out the invention (hereinafter referred to as the embodiment).

[0009] 1 is a circuit diagram showing an example of the configuration of a comparator circuit according to a first embodiment of the present invention; FIG. 2 is a circuit diagram showing an example of the configuration of a comparator circuit according to a second embodiment of the present invention; FIG. 3 is a circuit diagram showing an example of the configuration of a synchronous rectifier circuit according to a third embodiment of the present invention; FIG. 4 is a circuit diagram showing an example of the configuration of an autonomous synchronous rectifier circuit according to a fourth embodiment of the present invention; and FIG. 5 is a waveform diagram illustrating the operation of the autonomous synchronous rectifier circuit according to the fourth embodiment of the present invention. It is a waveform diagram illustrating the oscillation state of a determination node at the start of rectification in a synchronous rectifier circuit in which the output stage circuit of the comparator circuit is configured as a common-source circuit. It is a diagram illustrating the relationship between the potential of the determination node and the potential of the reference node in a case in which the output stage circuit of the comparator circuit is configured as an output stage current mirror circuit and an output stage common-source circuit.

[0010] Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings. In this specification and drawings, components having substantially the same functions or configurations are designated by the same reference numerals, and redundant description will be omitted.

[0011] First Embodiment [Configuration Example of Comparator Circuit] In a first embodiment of the present invention, a comparator circuit is exemplified as a semiconductor device. Fig. 1 is a circuit diagram showing a configuration example of a comparator circuit according to the first embodiment of the present invention.

[0012] 1, the comparator circuit 10 according to the first embodiment includes a bias circuit 11, a differential amplifier circuit 12, an output stage current mirror circuit 13, and an output stage common-source circuit 14. That is, in the comparator circuit 10 according to the first embodiment, the output stage circuit subsequent to the differential amplifier circuit 12 is configured to include the output stage current mirror circuit 13 and the output stage common-source circuit 14.

[0013] (Bias Circuit) The bias circuit 11 has P-channel MOSFETs (Metal-Oxide-Semiconductor Field Effect Transistors) mp01 and mp02, each having a source terminal connected to a power supply line L1. The MOSFET mp01 is diode-connected, with its gate and drain terminals connected in common, and the MOSFET mp02 and its gate terminal connected in common to form a current mirror circuit. The bias circuit 11 has a current source I connected between the drain terminal of the MOSFET mp01 and a ground line L2 (ground / GND), and forms a reference current source for the differential amplifier circuit 12.

[0014] (Differential Amplifier Circuit) The differential amplifier circuit 12 has a pair of P-channel differential MOSFETs mp1 and mp2, and a pair of N-channel load MOSFETs mn1 and mn2 that serve as loads for the differential MOSFETs mp1 and mp2. The source terminals of the pair of differential MOSFETs mp1 and mp2 are commonly connected, and a MOSFET mp02 of the bias circuit 11 is connected between the common source connection node and the power supply line L1, thereby forming a differential circuit.

[0015] The pair of load MOSFETs mn1, mn2 are connected between the drain terminals of the pair of differential MOSFETs mp1, mp2 and the ground line L2, respectively. That is, the drain terminals of the P-channel differential MOSFET mp1 and the N-channel load MOSFET mn1 are connected in common, and the drain terminals of the P-channel differential MOSFET mp2 and the N-channel load MOSFET mn2 are connected in common.

[0016] One of the pair of load MOSFETs mn1, mn2, the load MOSFET mn1, is diode-connected with its gate terminal and drain terminal connected in common, and has its gate terminal connected in common to the other load MOSFET mn2, thereby forming a current mirror circuit.

[0017] In the differential amplifier circuit 12 configured as described above, a reference potential is input to the gate terminal of the P-channel differential MOSFET mp1. The common drain connection node of the P-channel differential MOSFET mp1 and the N-channel load MOSFET mn1 serves as a reference node n1 of the differential amplifier circuit 12, and the common drain connection node of the P-channel differential MOSFET mp2 and the N-channel load MOSFET mn2 serves as a determination node n2 of the differential amplifier circuit 12.

[0018] (Output Stage Circuit) Output Stage Current Mirror Circuit The output stage current mirror circuit 13 is composed of a P-channel MOSFET mp3 and an N-channel MOSFET mn3 connected in series between the power supply line L1 and the ground line L2. That is, the source terminal of the P-channel MOSFET mp3 is connected to the power supply line L1. The drain terminal of the N-channel MOSFET mn3 is connected in common with the P-channel MOSFET mp3, and the source terminal is connected to the ground line L2. The gate terminal of the N-channel MOSFET mn3 is connected to the reference node n1 of the differential amplifier circuit 12, and the N-channel MOSFET mn3 forms a current mirror circuit together with the N-channel load MOSFET mn1.

[0019] The output stage common-source circuit 14 is composed of a P-channel MOSFET mp4 and an N-channel MOSFET mn4 connected in series between a power supply line L1 and a ground line L2. That is, the source terminal of the P-channel MOSFET mp4 is connected to the power supply line L1. The N-channel MOSFET mn4 has a drain terminal commonly connected to the P-channel MOSFET mp4, a source terminal connected to the ground line L2, and a gate terminal connected to a determination node n2 of the differential amplifier circuit 12. An output is derived from the common drain connection node of the P-channel MOSFET mp4 and the N-channel MOSFET mn4.

[0020] The P-channel MOSFET mp3 of the output stage current mirror circuit 13 is diode-connected with its gate terminal and drain terminal connected in common, and its gate terminal is connected in common to that of the P-channel MOSFET mp4 of the output stage common-source circuit 14 to form a current mirror circuit. The P-channel MOSFET mp3 is configured so that its bias point can be changed according to the voltage level of the input 2 of the differential amplifier circuit 12 (i.e., the gate terminal of the P-channel differential MOSFET mp2). The P-channel MOSFET mp4 is an output load, and its resistance value changes according to the voltage level of the input 2 of the differential amplifier circuit 12.

[0021] [Example of Comparator Circuit Operation] In the comparator circuit 10 configured as described above, the differential amplifier circuit 12 compares the magnitude relationship between the voltage levels of input 1 and input 2, and switches the potentials of the reference node n1 and the determination node n2 to a high level (H) or a low level (L) depending on the comparison result. As the power supply voltage of the power supply line L1 decreases, the difference between the potentials of the reference node n1 and the determination node n2 decreases near the lower limit voltage. This is because the circuit configuration between the power supply line L1 (power supply) and the ground line L2 (ground) is a three-stage configuration consisting of a P-channel MOSFET mp02, a P-channel MOSFET mp1 (mp2), and an N-channel MOSFET mn1 (mn2), and the lower limit of operation is determined by the threshold voltage Vth of these MOSFETs.

[0022] In this way, when the difference between the potential of the reference node n1 and the potential of the judgment node n2 decreases near the lower limit voltage of the power supply voltage, if the comparison result is determined based only on the potential of the judgment node n2, there is a possibility of an erroneous judgment in the lower limit voltage region, and the judgment operation may not be performed stably.

[0023] Therefore, in the comparator circuit 10 according to the first embodiment, in order to assist the determination operation and improve the lower limit voltage of operation, the output stage circuit subsequent to the differential amplifier circuit 12 has a current mirror type circuit configuration consisting of an output stage current mirror circuit 13 and an output stage commoned source circuit 14, and is configured to detect the difference between the potential of the reference node n1 and the potential of the determination node n2 of the differential amplifier circuit 12. In this configuration, the amount of current through the P-channel MOSFET mp4 of the output stage commoned source circuit 14 is controlled in accordance with the potential of the reference node n1, thereby assisting the lower limit operation of the comparator circuit 10 and improving operation in the low voltage region.

[0024] The output stage current mirror circuit 13 has a two-stage circuit configuration between the power supply line L1 (power supply) and the ground line L2 (ground), consisting of a P-channel MOSFET mp3 and an N-channel MOSFET mn3. While the differential amplifier circuit 12 has a three-stage configuration between the power supply line L1 (power supply) and the ground line L2 (ground), the output stage current mirror circuit 13 has a two-stage configuration. This widens the operating range at the lower limit of the power supply voltage by one threshold voltage Vth. Therefore, in addition to the determination operation of the differential amplifier circuit 12, the output stage circuit at the subsequent stage also assists in the differential determination operation between the potential of the reference node n1 and the potential of the determination node n2, thereby enabling the comparator circuit 10 to perform a stable determination operation.

[0025] Incidentally, in the comparator circuit 10 according to the first embodiment, in the judgment operation of the output stage circuit consisting of the output stage current mirror circuit 13 and the output stage common source circuit 14, the output is at a high level when the voltage level of input 2 is greater than the voltage level of input 1, and the output is at a low level when the voltage level of input 2 is less than the voltage level of input 1.

[0026] Second Embodiment A second embodiment of the present invention is a modification of the first embodiment of the present invention. Fig. 2 is a circuit diagram showing an example of the configuration of a comparator circuit according to the second embodiment of the present invention.

[0027] The comparator circuit 10 according to the first embodiment is configured such that the output stage current mirror circuit 13 receives the potential of the reference node n1 of the differential amplifier circuit 12 as an input, and the output stage commoned source circuit 14 receives the potential of the determination node n2 of the differential amplifier circuit 12 as an input. Specifically, the gate terminal of the N-channel MOSFET mn3 of the output stage current mirror circuit 13 is connected to the reference node n1 of the differential amplifier circuit 12, and the gate terminal of the N-channel MOSFET mn4 of the output stage commoned source circuit 14 is connected to the determination node n2 of the differential amplifier circuit 12.

[0028] In contrast to this, the comparator circuit 10a according to the second embodiment is configured such that the output stage current mirror circuit 13 receives the potential of the determination node n2 of the differential amplifier circuit 12 as an input, and the output stage commoned source circuit 14 receives the potential of the reference node n1 of the differential amplifier circuit 12 as an input. Specifically, the gate terminal of the N-channel MOSFET mn3 of the output stage current mirror circuit 13 is connected to the determination node n2 of the differential amplifier circuit 12, and the gate terminal of the N-channel MOSFET mn4 of the output stage commoned source circuit 14 is connected to the reference node n1 of the differential amplifier circuit 12.

[0029] The comparator circuit 10a according to the second embodiment configured as described above outputs an output of opposite polarity to that of the comparator circuit 10 according to the first embodiment. Specifically, in the determination operation of the output stage circuit consisting of the output stage current mirror circuit 13 and the output stage common-source circuit 14, if the voltage level of input 2 is lower than the voltage level of input 1, the output becomes high level, and if the voltage level of input 2 is higher than the voltage level of input 1, the output becomes low level.

[0030] Third Embodiment [Configuration Example of Synchronous Rectifier Circuit] In a third embodiment of the present invention, a synchronous rectifier circuit is exemplified as a semiconductor device. Fig. 3 is a circuit diagram showing a configuration example of a synchronous rectifier circuit according to the third embodiment of the present invention.

[0031] 3, a synchronous rectifier circuit 20 according to the third embodiment includes a comparator circuit 10, a driver circuit 21, a rectifier element 22, and a diode 23. The synchronous rectifier circuit 20 illustrated here is a voltage determination type synchronous rectifier circuit.

[0032] 3 illustrates a synchronous rectifier circuit 20 that uses the comparator circuit 10 according to the first embodiment described above as the comparator circuit. However, the comparator circuit is not limited to the comparator circuit 10 according to the first embodiment, and may also be configured to use the comparator circuit 10a according to the second embodiment described above.

[0033] The driver circuit 21 is connected between the power supply line L1 and the ground line L2. The driver circuit 21 has a configuration in which inverter circuits, each of which has a P-channel MOSFET and an N-channel MOSFET connected in series, are connected in a cascaded multi-stage configuration, and turns on / off the rectifier element 22 in accordance with the determination result of the comparator circuit 10.

[0034] When the comparator circuit 10 according to the first embodiment is used as the comparator circuit, the driver circuit 21 has an odd number of inverter circuits, for example, three cascaded inverter circuits, due to the logic relationship of the outputs of the comparator circuit 10. In contrast, when the comparator circuit 10a according to the second embodiment is used as the comparator circuit, the logic of the output of the comparator circuit 10a is inverted compared to when the comparator circuit 10 according to the first embodiment is used, and therefore the driver circuit 21 has an even number of inverter circuits, for example, two cascaded inverter circuits.

[0035] This means that, compared to the case where the comparator circuit 10 according to the first embodiment is used as the comparator circuit, the number of inverter circuits constituting the driver circuit 21 can be reduced by one when the comparator circuit 10a according to the second embodiment is used as the comparator circuit. As a result, compared to the case where the comparator circuit 10 according to the first embodiment is used as the comparator circuit, the case where the comparator circuit 10a according to the second embodiment is used as the comparator circuit can contribute to simplifying the circuit configuration of the synchronous rectifier circuit 20.

[0036] The rectifying element 22 is an element that performs a rectifying operation. Here, a synchronous rectifying circuit 20 is illustrated that uses, for example, a MOSFET with an SJ (super junction) structure as the rectifying element 22. The anode terminal of the diode 23 is connected to the source terminal of the rectifying element 22, and the cathode terminal is connected to the drain terminal of the rectifying element 22.

[0037] [Example of Operation of Synchronous Rectifier Circuit] In the synchronous rectifier circuit 20 configured as described above, the comparator circuit 10 detects an increase in the voltage between the source terminal (S) and the drain terminal (D), which is proportional to the rectified current of the rectifier element 22, and turns on the rectifier element 22 via the driver circuit 21. The comparator circuit 10 (10a) used in the synchronous rectifier circuit 20 according to the third embodiment assists in the determination operation of the differential amplifier circuit 12 and also in the output stage circuit of the subsequent stage by performing a differential determination operation between the potential of the reference node n1 and the potential of the determination node n2, thereby enabling the comparator circuit 10 (10a) to perform a stable determination operation. For this reason, the synchronous rectifier circuit 20 according to the third embodiment, which uses the comparator circuit 10 (10a), is suitable for use in synchronous rectification switching applications that require operation over a wide voltage range.

[0038] Fourth Embodiment [Configuration Example of an Autonomous Synchronous Rectifier Circuit] In a fourth embodiment of the present invention, an autonomous synchronous rectifier circuit is exemplified as a semiconductor device. Fig. 4 is a circuit diagram showing a configuration example of an autonomous synchronous rectifier circuit according to the fourth embodiment of the present invention. In the autonomous synchronous rectifier circuit, a comparator circuit and a rectifier element are used to achieve an operation equivalent to an ideal diode.

[0039] In the autonomous synchronous rectifier circuit 30 according to the fourth embodiment, a relatively high voltage, for example, a voltage of AC 230 V, is applied to the drain terminal, which is one output terminal of the rectifier element 22. This high voltage is supplied to the step-down circuit 31 via the high-voltage power supply line L3.

[0040] The step-down circuit 31 is composed of resistor elements 311 and 312 connected in series between the power supply line L4 and the ground line L2, a P-channel MOSFET 313 connected between the power supply line L3 and the power supply line L4, and a diode 314 connected between the source terminal and drain terminal of the MOSFET 313. The gate terminal of the MOSFET 313 is connected to a voltage division node n3 of the resistor elements 311 and 312.

[0041] The voltage stepped down by the step-down circuit 31 is applied to the capacitance element 33 via the power supply line L4 and the diode 32. This charges the capacitance element 33. The diode 32 and the capacitance element 33 are connected in series between the power supply line L4 and the ground line L2, and the power supply line L1 of the comparator circuit 10 and the driver circuit 21 is connected to their common connection node n4. That is, a voltage based on the charge stored in the capacitance element 33 is supplied as a power supply voltage to the comparator circuit 10 and the driver circuit 21 via the power supply line L1.

[0042] [Operation Example of Autonomous Synchronous Rectifier Circuit] In the autonomous synchronous rectifier circuit 30 according to the fourth embodiment having the above configuration, the voltage between the source terminal and gate terminal of the rectifier element 22, which is an N-channel MOSFET, is denoted as Vgs, the voltage between the source terminal and drain terminal, i.e., the AC voltage applied to the rectifier element 22, is denoted as Vds, and the current flowing through the rectifier element 22 when the rectifier element 22 is on is denoted as Isd. When the rectifier element 22 is off, no current flows through the rectifier element 22. Furthermore, the power supply voltage supplied to the comparator circuit 10 and the driver circuit 21 via the power supply line L1 is denoted as CIN (CIN voltage), and the positive input of the comparator circuit 10 is denoted as Vdin. A reference potential Vref (e.g., 0 V) ​​is input to the negative input of the comparator circuit 10.

[0043] Here, the operation of the autonomous synchronous rectifier circuit 30 according to the fourth embodiment will be described with reference to the waveform diagram of Fig. 5. Fig. 5 is a waveform diagram provided for explaining the operation of the autonomous synchronous rectifier circuit 30 according to the fourth embodiment. The waveform diagram of Fig. 5 illustrates the waveforms of the AC voltage Vds, the CIN voltage supplied to the comparator circuit 10 and the driver circuit 21, the positive input Vdin of the comparator circuit 10, and the voltage Vgs between the source terminal and gate terminal of the rectifier element 22.

[0044] During the positive period of the AC voltage Vds applied to the rectifying element 22, the positive input Vdin of the comparator circuit 10 is positive. At this time, the output (driver output) of the driver circuit 21 is at a low level (L), and the rectifying element 22 is in an off state. In addition, the capacitive element 33 is in a charging state, and the rectifying element 22 is in a reverse-biased diode state.

[0045] During the negative period of the AC voltage Vds applied to the rectifying element 22, the positive input Vdin of the comparator circuit 10 is negative. At this time, the output (driver output) of the driver circuit 21 is at a high level (H), and the rectifying element 22 is in an ON state. Furthermore, the capacitive element 33 is in a state of outputting the CIN voltage, and the rectifying element 22 is in a state equivalent to a forward diode.

[0046] In the autonomous synchronous rectifier circuit 30, the CIN voltage, which serves as the power supply voltage for the comparator circuit 10, is finite because it uses the charge stored in the capacitance element 33. The CIN voltage gradually decreases during the rectification period because the charge in the capacitance element 33 is consumed depending on the operating conditions and temperature. In this context, the comparator circuit 10 is required to operate over a wide voltage range.

[0047] Incidentally, the autonomous synchronous rectifier circuit 30, which generates the power supply voltage for the comparator circuit 10 using the capacitance element 33, is prone to inducing oscillation of the judgment node due to its negative feedback characteristics. Here, Figure 6 shows the state of oscillation of the judgment node at the start of rectification in a synchronous rectifier circuit in which the output stage circuit of the comparator circuit 10 is configured as a common-source circuit. Figure 6 is a waveform diagram showing the state of oscillation of the judgment node at the start of rectification in a synchronous rectifier circuit in which the output stage circuit of the comparator circuit 10 is configured as a common-source circuit. Figure 6 also shows the relationship between the potential of the judgment node and the potential of the reference node.

[0048] In a synchronous rectification circuit in which the output stage circuit is configured as a source-grounded circuit, the potential of the judgment node and the potential of the reference node cross, and only the potential of the judgment node is detected by the output stage circuit configured as a source-grounded circuit, which makes it prone to erroneous detection in the low-voltage region.

[0049] Therefore, in the comparator circuit 10 according to the first embodiment and the comparator circuit 10a according to the second embodiment, the output stage circuit subsequent to the differential amplifier circuit 12 is configured as a current mirror type circuit consisting of an output stage current mirror circuit 13 and an output stage source grounded circuit 14, and is configured to detect the difference between the potential of the reference node n1 and the potential of the determination node n2 of the differential amplifier circuit 12.

[0050] In the output stage circuit consisting of the output stage current mirror circuit 13 and the output stage common-source circuit 14, it is possible to provide an offset in the potential between the reference node and the determination node by adjusting the constants of the N-channel MOSFETs mn3 and mn4 and the P-channel MOSFETs mp3 and mp4. By providing an offset in the potential between the reference node and the determination node in this way, the influence of oscillation of the determination node can be suppressed, and erroneous detection in the low-voltage region can be prevented.

[0051] Conversely, it is also possible to provide no offset in the potential between the reference node and the judgment node, which is advantageous in terms of lower limit characteristics as well, since both the reference node and the judgment node are monitored even on the lower limit voltage side.

[0052] 7 shows the relationship between the potential of the reference node and the potential of the determination node when the output stage circuit is made up of the output stage current mirror circuit 13 and the output stage common-source circuit 14. In Fig. 7, the diagram on the right shows the waveform of the potential of the determination node relative to the potential of the reference node during the rectification period, and the diagram on the left shows an enlarged view of the diagram on the right at the start of rectification.

[0053] As described above, in the autonomous synchronous rectifier circuit 30 according to the fourth embodiment, by using the comparator circuit 10 according to the first embodiment or the comparator circuit 10a according to the second embodiment as the comparator circuit, the influence of oscillation of the determination node can be suppressed, false detection in the low voltage region can be prevented, and the determination operation of the comparator circuit can be performed stably. The same action and effect can be said for the synchronous rectifier circuit 20 according to the third embodiment.

[0054] <<Modifications>> The present invention is not limited to the above-described embodiments, and various other applications and modifications are possible without departing from the spirit of the present invention as defined in the claims. The above-described embodiments have described the configuration of the semiconductor device in detail and specifically in order to clearly explain the present invention, and the present invention is not necessarily limited to those including all of the described configurations. For example, in the above-described embodiments, a case where an SJ-structure MOSFET is used as the rectifying element is illustrated, but the rectifying element is not limited to a MOSFET, and a power semiconductor element such as an IGBT (Insulated Gate Bipolar Transistor) may also be used.

[0055] 10... Comparator circuit according to the first embodiment, 10a... Comparator circuit according to the second embodiment, 11... Bias circuit, 12... Differential amplifier circuit, 13... Output stage current mirror circuit, 14... Output stage common source circuit, 20... Synchronous rectifier circuit according to the third embodiment, 21... Driver circuit, 22... Rectifier element, 23, 32... Diode, 30... Autonomous synchronous rectifier circuit according to the fourth embodiment, 31... Step-down circuit, 33... Capacitive element

Claims

1. A semiconductor device comprising: a differential amplifier circuit having a three-stage circuit configuration between a power supply and ground; and an output stage circuit provided in the subsequent stage of the differential amplifier circuit, wherein the output stage circuit has a current mirror type circuit configuration and a two-stage circuit configuration between the power supply and ground, and detects the difference between the potential of a reference node and the potential of a determination node of the differential amplifier circuit.

2. The semiconductor device according to claim 1, wherein the differential amplifier circuit has a pair of differential MOSFETs and a pair of load MOSFETs that act as loads for the pair of differential MOSFETs, one of the pair of load MOSFETs being diode-connected and forming a current mirror circuit with the other load MOSFET.

3. The semiconductor device according to claim 1 or 2, wherein the output stage circuit comprises: an output stage current mirror circuit having an input that is the potential of a reference node of the differential amplifier circuit; and an output stage common-source circuit having an input that is the potential of a decision node of the differential amplifier circuit.

4. The semiconductor device according to claim 1 or 2, wherein the output stage circuit comprises: an output stage current mirror circuit having an input that is the potential of a decision node of the differential amplifier circuit; and an output stage common-source circuit having an input that is the potential of a reference node of the differential amplifier circuit.

5. The semiconductor device according to claim 1 or 2, further comprising: a rectifying element; and a driver circuit that turns on / off the rectifying element based on the output of a comparator circuit including the output stage circuit.

6. The semiconductor device according to claim 5, further comprising: a step-down circuit that steps down a relatively high voltage applied to one output terminal of said rectifying element; and a capacitive element that is charged by the voltage stepped down by said step-down circuit and supplies a voltage based on the charged charge to said comparator circuit and said driver circuit as a power supply voltage.

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