Semiconductor module and method for manufacturing semiconductor module

Abstract

A semiconductor module according to the present invention comprises a semiconductor package including a semiconductor element and a sealing resin covering the semiconductor element, and a heat dissipation member including a base part. The base part has a first surface in contact with the sealing resin of the semiconductor package, and a second surface facing the side opposite from the first surface in the thickness direction. The heat dissipation member includes a plurality of heat dissipation fins in contact with the second surface. The second surface includes arrangement regions where the plurality of heat dissipation fins are arranged, and a non-arrangement region where the plurality of heat dissipation fins are not arranged. The arrangement regions are positioned in a range overlapping the semiconductor element as seen in the thickness direction. The non-arrangement region is positioned between the arrangement regions in a first direction.

Description

Semiconductor module and method for manufacturing the same

[0001] The present disclosure relates to a semiconductor module and a method for manufacturing the semiconductor module.

[0002] Conventionally, semiconductor modules incorporating semiconductor elements such as MOSFETs (Metal-Oxide-Semiconductor Field-Effect Transistors) and IGBTs (Insulated-Gate Bipolar Transistors) have been widely known. Patent Document 1 discloses an example of a conventional semiconductor module. The semiconductor module described in Patent Document 1 includes a plurality of semiconductor elements, a conductive substrate, a plurality of input terminals, a plurality of output terminals, and a sealing resin. The plurality of semiconductor elements are, for example, MOSFETs and are bonded to the conductive substrate. The sealing resin covers the plurality of semiconductor elements. The plurality of input terminals and the plurality of output terminals are electrically connected to one of the plurality of semiconductor elements. The plurality of input terminals and the plurality of output terminals are all power supply terminals that handle a power supply voltage. The plurality of input terminals and the plurality of output terminals each protrude from one of a plurality of resin side surfaces of the sealing resin.

[0003] When a semiconductor device (such as the semiconductor module described in Patent Document 1) is in use, heat is generated from each semiconductor element. Such heat generation from the semiconductor elements can increase conduction loss in the semiconductor elements. For example, in switching elements such as the above-mentioned MOSFETs and IGBTs, heat generation increases the on-resistance, and this increase in on-resistance increases conduction loss. Therefore, dissipating heat from the semiconductor elements is an important issue.

[0004] Japanese Patent Application Laid-Open No. 2023-181544

[0005] [Summary] An object of the present disclosure is to provide an improved semiconductor device. In particular, in view of the above circumstances, an object of the present disclosure is to provide a semiconductor module with improved heat dissipation. Another object of the present disclosure is to provide a method for manufacturing a semiconductor module with improved heat dissipation.

[0006] A semiconductor module provided by a first aspect of the present disclosure includes a semiconductor package including at least one semiconductor element and at least one sealing resin covering the at least one semiconductor element, and a heat dissipation member including a base located on one side of the semiconductor package in a thickness direction of the semiconductor package. The base has a first surface to which the semiconductor package is bonded and a second surface facing the opposite side of the first surface in the thickness direction. The at least one sealing resin is in contact with the first surface. The heat dissipation member includes a plurality of heat dissipation fins in contact with the second surface. The second surface has an arrangement region in which the plurality of heat dissipation fins are arranged and a non-arrangement region in which the plurality of heat dissipation fins are not arranged. The arrangement region is located in a range of the second surface that overlaps the at least one semiconductor element when viewed in the thickness direction. The non-arrangement region is located between both ends of the arrangement region in a first direction perpendicular to the thickness direction.

[0007] A second aspect of the present disclosure provides a method for manufacturing a semiconductor module, comprising: a substrate bonding process for bonding at least one substrate to a heat dissipation member; an element bonding process for bonding a semiconductor element to the at least one substrate; and a molding process for forming at least one sealing resin covering the semiconductor element by molding. The heat dissipation member includes a base having a first surface and a second surface spaced apart from each other in a thickness direction of the at least one substrate, and a plurality of heat dissipation fins in contact with the second surface. In the substrate bonding process, the at least one substrate is bonded to the first surface. In the molding process, the first surface and the second surface are respectively sandwiched between an upper mold and a lower mold in the thickness direction. The lower mold includes a recess for accommodating the plurality of heat dissipation fins and an intermediate support in contact with the second surface of the base. The intermediate support is located between the plurality of heat dissipation fins.

[0008] FIG. 1 is a perspective view showing a semiconductor module according to a first embodiment. FIG. 2 is a view of the perspective view of FIG. 1 , with the sealing resin of each semiconductor package omitted. FIG. 3 is a perspective view (different from FIG. 1 ) showing a semiconductor module according to the first embodiment. FIG. 4 is a plan view showing a semiconductor module according to the first embodiment. FIG. 5 is a front view showing a semiconductor module according to the first embodiment. FIG. 6 is a bottom view showing a semiconductor module according to the first embodiment. FIG. 7 is a rear view showing a semiconductor module according to the first embodiment. FIG. 8 is a left side view showing a semiconductor module according to the first embodiment. FIG. 9 is a partially enlarged plan view of a portion of FIG. 4 . FIG. 10 is a view of FIG. 9 , with multiple power terminals omitted. FIG. 11 is a view of FIG. 9 , with the heat dissipation member omitted and the sealing resin shown in imaginary lines. FIG. 12 is a view of FIG. 11 , with the multiple power terminals omitted. FIG. 13 is a view of FIG. 12 , with one of two conductive members and the sealing resin omitted. FIG. 14 is a diagram of FIG. 13 with the other of the two conductive members omitted. FIG. 15 is a bottom view showing one of the multiple semiconductor packages of the semiconductor module according to the first embodiment. FIG. 16 is a cross-sectional view taken along line XVI-XVI in FIG. 11. FIG. 17 is a partially enlarged cross-sectional view of FIG. 16. FIG. 18 is a partially enlarged cross-sectional view of FIG. 16 (a portion different from FIG. 17). FIG. 19 is a partially enlarged cross-sectional view of FIG. 16 (a portion different from FIG. 17 and FIG. 18). FIG. 20 is a cross-sectional view taken along line XX-XX in FIG. 11. FIG. 21 is a cross-sectional view taken along line XXI-XXI in FIG. 11. FIG. 22 is a cross-sectional view taken along line XXII-XXII in FIG. 11. FIG. 23 is a cross-sectional view taken along line XXIII-XXIII in FIG. 11. FIG. 24 is a cross-sectional view taken along line XXIV-XXIV in FIG. 11. Fig. 25 is a cross-sectional view taken along line XXV-XXV in Fig. 11. Fig. 26 is a flowchart illustrating a method for manufacturing a semiconductor module according to the first embodiment. Fig. 27 is a cross-sectional view illustrating a step (support substrate bonding step) of the method for manufacturing a semiconductor module according to the first embodiment, corresponding to the cross section of Fig. 25. Fig. 28 is a cross-sectional view illustrating a step (element bonding step) of the method for manufacturing a semiconductor module according to the first embodiment, corresponding to the cross section of Fig. 25.29 is a cross-sectional view showing a step (signal substrate bonding step, conductive member bonding step, and sleeve bonding step) of a method for manufacturing a semiconductor module according to the first embodiment, and corresponds to the cross section of FIG. 25 . FIG. 30 is a cross-sectional view showing a step (molding step) of a method for manufacturing a semiconductor module according to the first embodiment, and corresponds to the cross section of FIG. 25 . FIG. 31 is a cross-sectional view showing a step (molding step) of a method for manufacturing a semiconductor module according to the first embodiment. FIG. 32 is a cross-sectional view showing a step (molding step) of a method for manufacturing a semiconductor module according to the first embodiment, and corresponds to the cross section of FIG. 25 . FIG. 33 is a flowchart showing another example of a method for manufacturing a semiconductor module according to the first embodiment. FIG. 34 is a front view showing a power conversion unit including a semiconductor module according to the first embodiment. FIG. 35 is an enlarged cross-sectional view of a main portion of the power conversion unit shown in FIG. 34 . FIG. 36 is a front view showing another example of the configuration of a power conversion unit including a semiconductor module according to the first embodiment. FIG. 37 is a schematic diagram of a vehicle including a power conversion unit including a semiconductor module according to the first embodiment. FIG. 38 is a bottom view showing a semiconductor module according to a first modification of the first embodiment. FIG. 39 is a bottom view showing a semiconductor module according to a second modified example of the first embodiment. FIG. 40 is a front view showing a semiconductor module according to a third modified example of the first embodiment. FIG. 41 is a bottom view showing a semiconductor module according to the second embodiment. FIG. 42 is a bottom view showing a semiconductor module according to the third embodiment. FIG. 43 is a plan view showing a step (molding step) of the method for manufacturing a semiconductor device according to the third embodiment. FIG. 44 is a bottom view showing a semiconductor module according to a first modified example of the third embodiment. FIG. 45 is a bottom view showing a semiconductor module according to a second modified example of the third embodiment. FIG. 46 is a front view showing a semiconductor module according to the fourth embodiment. FIG. 47 is a bottom view showing a semiconductor module according to the fifth embodiment. FIG. 48 is a plan view showing a semiconductor module according to a modified example of the fifth embodiment. FIG. 49 is a bottom view showing the semiconductor module shown in FIG. 48. FIG. 50 is a bottom view showing another configuration example of a plurality of heat dissipation fins. FIG. 51 is a cross-sectional view showing another configuration example (first modified example) of a semiconductor package, corresponding to the cross-section of FIG. 20.FIG. 52 is a cross-sectional view showing the semiconductor package shown in FIG. 51 , corresponding to the cross section of FIG. 25 . FIG. 53 is a cross-sectional view showing another configuration example (second modified example) of the semiconductor package, corresponding to the cross section of FIG. 20 . FIG. 54 is a cross-sectional view showing another configuration example (third modified example) of the semiconductor package, corresponding to the cross section of FIG. 20 . FIG. 55 is a plan view showing another configuration example (fourth modified example) of the semiconductor package. FIG. 56 is a perspective view showing another configuration example (fifth modified example) of the semiconductor package. FIG. 57 is a plan view showing the semiconductor package shown in FIG. 56 , with the sealing resin indicated by imaginary lines. FIG. 58 is a cross-sectional view taken along line LVIII-LVIII of FIG. 57 .

[0009] DETAILED DESCRIPTION A preferred embodiment of the semiconductor device of the present disclosure will be described below with reference to the drawings. Hereinafter, identical or similar components will be designated by the same reference numerals, and redundant description will be omitted. Terms such as "first," "second," and "third" in this disclosure are used merely as labels and are not intended to necessarily assign any order to their objects.

[0010] In this disclosure, unless otherwise specified, "a certain object A is formed on a certain object B" and "a certain object A is formed on (an) object B" include "a certain object A is formed directly on a certain object B" and "a certain object A is formed on a certain object B with another object interposed between the certain object A and the certain object B." Similarly, "a certain object A is disposed on a certain object B" and "a certain object A is disposed on (an) object B" include "a certain object A is disposed directly on a certain object B" and "a certain object A is disposed on (an) object B with another object interposed between the certain object A and the certain object B" unless otherwise specified. Similarly, "a certain object A is located on (an) object B" includes "a certain object A is in contact with a certain object B and is located on (an) object B" and "a certain object A is located on (an) object B with another object interposed between the certain object A and the certain object B." Furthermore, "object A overlaps object B when viewed in a certain direction" includes "object A overlaps the entire object B" and "object A overlaps a part of object B," unless otherwise specified. Furthermore, "object A (its material) contains material C" includes "object A (its material) is made of material C" and "object A (its material) is mainly composed of material C." Furthermore, "a surface A faces in a certain direction B (one side or the other side of a certain direction B)," unless otherwise specified, is not limited to the case where surface A is at a 90° angle with respect to direction B, but also includes the case where surface A is tilted with respect to direction B. Furthermore, "a surface A is perpendicular to a surface B," unless otherwise specified, is not limited to the case where surface A is at a 90° angle with respect to surface B, but also includes the case where surface A is tilted with respect to surface B. Furthermore, unless otherwise specified, "an object A (surface A) being parallel to an object B (surface B)" is not limited to a strict definition, and includes cases where an object A (surface A) is tilted relative to an object B (surface B) (for example, a slight deviation due to a manufacturing error, etc.).

[0011] 1 to 25 show a semiconductor module A10 according to a first embodiment. The semiconductor module A10 includes three semiconductor packages B10 and a heat dissipation member C10. The semiconductor module A10 is used, for example, in an inverter for driving a three-phase AC motor, but the use of the semiconductor module A10 is not limited to this.

[0012] For ease of explanation, the thickness direction z, the first direction x, and the second direction y are referred to as being perpendicular to each other. The thickness direction z corresponds to the thickness direction of the semiconductor module A10. "Planar view" refers to the view in the thickness direction z. The first direction x is perpendicular to the thickness direction z. The second direction y is perpendicular to the thickness direction z and the first direction x. One side of the first direction x is referred to as the x1 side of the first direction x, and the other side of the first direction x is referred to as the x2 side of the first direction x. One side of the second direction y is referred to as the y1 side of the second direction y, and the other side of the second direction y is referred to as the y2 side of the second direction y. One side of the thickness direction z is referred to as the z1 side of the thickness direction z, and the other side of the thickness direction z is referred to as the z2 side of the thickness direction z. The z2 side of the thickness direction z is sometimes referred to as the upper side, and the z1 side of the thickness direction z is sometimes referred to as the lower side. The terms "top," "bottom," "upper," "lower," "top surface," and "bottom surface" indicate the relative positional relationship of each part in the thickness direction z, and do not necessarily define the relationship with the direction of gravity.

[0013] The three semiconductor packages B10 are each bonded to a heat dissipation member C10. In a plan view, the heat dissipation member C10 has a rectangular shape with its longitudinal direction aligned in the first direction x. The plan view shape of the heat dissipation member C10 is not limited to the example shown in the figure. The three semiconductor packages B10 are each disposed on the heat dissipation member C10 along the first direction x. A detailed configuration example of each semiconductor package B10 will be described later.

[0014] The heat dissipation member C10 supports the multiple semiconductor packages B10. The heat dissipation member C10 is, for example, a heat sink. Most of the heat dissipation member C10 is located below the multiple semiconductor packages B10 in the thickness direction z (on the z1 side). The heat dissipation member C10 faces the bottom surface (the surface facing the z1 side in the thickness direction z) of each of the multiple semiconductor packages B10. The material of the heat dissipation member C10 includes, for example, aluminum. The material is not limited to aluminum, and may be other metal materials or resin materials (preferably those with good thermal conductivity). The heat dissipation member C10 includes a base 71 and a heat dissipation portion 75.

[0015] The base 71 is a plate material. The plurality of semiconductor packages B10 are mounted on the base 71. The plurality of semiconductor packages B10 are arranged on the base 71 along the first direction x. The base 71 faces the bottom surface of each of the plurality of semiconductor packages B10. The base 71 contacts each semiconductor package B10. The base 71 has, for example, a rectangular shape in a plan view, but the shape of the base 71 in a plan view is not limited in any way.

[0016] The base 71 has a first surface 71a and a second surface 71b. As shown in Figures 5, 7, and 8, the first surface 71a and the second surface 71b are spaced apart in the thickness direction z. The first surface 71a and the second surface 71b face opposite each other in the thickness direction z. The first surface 71a faces upward in the thickness direction z, and the second surface 71b faces downward in the thickness direction z. The multiple semiconductor packages B10 are bonded to the first surface 71a.

[0017] The base 71 includes a main portion 711 and an outer peripheral portion 712. The main portion 711 overlaps each of the multiple semiconductor packages B10 in a plan view. The multiple semiconductor packages B10 are bonded to the main portion 711. In the present embodiment, the main portion 711 is rectangular in a plan view. The outer peripheral portion 712 surrounds the periphery of the main portion 711 in a plan view. The outer peripheral portion 712 forms a ring shape surrounding the main portion 711 in a plan view. The outer peripheral portion 712 is sandwiched by a mold (a mold M10 described below) used to form the sealing resin 50. The outer peripheral portion 712 is located outside the multiple semiconductor packages B10 in a plan view. As shown in FIG. 6 , the outer peripheral portion 712 has multiple through holes 712a formed therein. The multiple through holes 712a penetrate the base 71 (the outer peripheral portion 712) in the thickness direction z. Each of the plurality of through holes 712a can be used as a mounting hole when mounting the semiconductor module A10 to a housing (frame, etc.) of an electronic device or an electric vehicle, or as a positioning hole for a mold M10 described later.

[0018] The heat dissipation portion 75 protrudes in the thickness direction z from the second surface 71b of the base portion 71. The heat dissipation portion 75 is located on the opposite side of the base portion 71 from the semiconductor packages B10 in the thickness direction z.

[0019] The heat dissipation unit 75 includes a plurality of heat dissipation fins 751. The plurality of heat dissipation fins 751 contact the second surface 71b. The plurality of heat dissipation fins 751 extend downward in the thickness direction z from the second surface 71b. In this embodiment, the plurality of heat dissipation fins 751 are pin fins and rod-shaped metal bodies. The plurality of heat dissipation fins 751 are spaced apart from one another in a direction perpendicular to the thickness direction z. In the illustrated example (e.g., FIG. 6 ), each heat dissipation fin 751 is circular in plan view. The planar shape of each heat dissipation fin 751 may not be circular, but may be elliptical, polygonal (triangle, rectangle, diamond, hexagon, etc.), Y-shaped, X-shaped, etc.

[0020] 6, the second surface 71b of the base 71 has a placement area 72 and a non-placement area 73. For ease of understanding, the non-placement area 73 is shown with a dotted pattern in bottom views such as FIG.

[0021] The arrangement region 72 is a region of the second surface 71b where multiple heat dissipation fins 751 are arranged. The multiple heat dissipation fins 751 are arranged in the arrangement region 72 at a certain arrangement density or higher. In the arrangement region 72, the multiple heat dissipation fins 751 are regularly arranged at a certain interval from each other adjacent heat dissipation fins 751. In the illustrated example (e.g., FIG. 6 ), the multiple heat dissipation fins 751 are arranged in a face-centered rectangular lattice pattern of a two-dimensional Bravais lattice in a planar view. The face-centered rectangular lattice pattern of the two-dimensional Bravais lattice is a pattern in which a certain heat dissipation fin 751 is used as a reference and the other heat dissipation fins 751 are arranged as follows: As shown in FIG. 6 , first, the magnitude of vector a1 is different from the magnitude of vector a2, and the angle α between the two vectors a1 and a2 is 90° (i.e., the two vectors a1 and a2 form a rectangle). Second, the heat dissipation fin 751 is arranged at the center of the rectangle formed by the two vectors a1 and a2. Third, the magnitudes of vector b1 and vector b2 are the same, and the angle β between the two vectors b1 and b2 is not 90°. Alternatively, the heat dissipation fins 751 may be arranged in a two-dimensional Bravais lattice pattern, such as a square lattice, a rectangular lattice, a diagonal lattice, or a hexagonal lattice, in a planar view. The arrangement of the heat dissipation fins 751 in a planar view is not limited to the example shown. The regular arrangement of the heat dissipation fins 751 can be appropriately changed by combining the magnitudes of the vectors a1, a2, b1, and b2 and the angles α and β. For example, the arrangement region 72 is located in a range of the second surface 71b that overlaps with the semiconductor elements 21 and 22 (described later) in a planar view.

[0022] The placement area 72 includes two outermost edges 72 a and two outermost edges 72 b. The two outermost edges 72 a are opposite ends of the placement area 72 in the first direction x. The two outermost edges 72 b are opposite ends of the placement area 72 in the second direction y.

[0023] The non-arrangement region 73 is a region of the second surface 71b where the plurality of heat dissipation fins 751 are not arranged. The non-arrangement region 73 is a region of the second surface 71b excluding the arrangement region 72. The non-arrangement region 73 is a region where the plurality of heat dissipation fins 751 do not satisfy the aforementioned arrangement density. In the present disclosure, the gaps between adjacent heat dissipation fins 751 among the plurality of heat dissipation fins 751 regularly arranged in the arrangement region 72 are not non-arrangement regions 73. In this embodiment, the non-arrangement region 73 is located between the two outermost edges 72a.

[0024] The non-placement area 73 includes at least one intervening portion 731. In a plan view, the intervening portion 731 overlaps the area between two adjacent semiconductor packages B10. Therefore, in a semiconductor module A10 in which three semiconductor packages B10 are arranged along the first direction x, the non-placement area 73 includes two intervening portions 731. The placement area 72 is divided into three small areas by the two intervening portions 731.

[0025] Next, a detailed configuration example of each semiconductor package B10 will be described. As shown in Figures 9 to 25, each of the multiple semiconductor packages B10 includes a support substrate 10, multiple power terminals 15, 16, and 17, multiple signal terminals 19, multiple semiconductor elements 21 and 22, two conductive members 31 and 32, multiple connecting members 41 to 45, a sealing resin 50, and two signal boards 601 and 602. Note that the multiple connecting members 41 to 45 are not shown in Figure 2. In the following description, the support substrate 10, multiple power terminals 15, 16, and 17, multiple signal terminals 19, multiple semiconductor elements 21 and 22, two conductive members 31 and 32, multiple connecting members 41 to 45, a sealing resin 50, and two signal boards 601 and 602 are common to each semiconductor package B10 unless otherwise specified. The plurality of signal terminals 19 includes a plurality of signal terminals 191 , 192 , 193 , 194 , 196 , and 197 .

[0026] Each semiconductor package B10 converts a DC power supply voltage applied to power terminals 15 and 16 into an AC voltage using multiple semiconductor elements 21 and 22. The converted AC voltage is input from power terminal 17 to a power supply target such as a motor.

[0027] As shown in FIGS. 13 and 14 , the support substrate 10 supports a plurality of semiconductor elements 21 and 22 in the thickness direction z. The support substrate 10 is, for example, an active metal brazing (AMB) substrate. Alternatively, the support substrate 10 may be a direct copper bonding (DCB) substrate. The support substrate 10 includes an insulating substrate 11, a main surface metal layer 12, and a back surface metal layer 13. In this embodiment, the support substrate 10 is covered with a sealing resin 50.

[0028] As shown in Figures 16 and 20 to 25, the insulating substrate 11 is interposed between the main surface metal layer 12 and the back surface metal layer 13 in the thickness direction z. The insulating substrate 11 supports a plurality of semiconductor elements 21 and a plurality of semiconductor elements 22 via the main surface metal layer 12. The insulating substrate 11 includes a material with relatively high thermal conductivity. The insulating substrate 11 is made of ceramics including aluminum nitride (AlN), for example. The insulating substrate 11 may include an insulating resin sheet in addition to ceramics.

[0029] The insulating substrate 11 has a substrate main surface 11a and a substrate back surface 11b. As shown in Figures 16 and 20 to 25, the substrate main surface 11a and the substrate back surface 11b are spaced apart in the thickness direction z. The substrate main surface 11a and the substrate back surface 11b face opposite each other in the thickness direction z. The substrate main surface 11a faces upward in the thickness direction z, and the substrate back surface 11b faces downward in the thickness direction z. The substrate main surface 11a faces the multiple semiconductor elements 21 and the multiple semiconductor elements 22.

[0030] As shown in Figures 16 and 20 to 25, the main surface metal layer 12 is located above the insulating substrate 11 in the thickness direction z. The main surface metal layer 12 is in contact with and bonded to the substrate main surface 11a. The main surface metal layer 12 contains copper (Cu), but may contain other metals. In a plan view, the main surface metal layer 12 is surrounded by the periphery of the insulating substrate 11. As shown in Figure 14, the main surface metal layer 12 includes a conductor portion 121, a conductor portion 122, and two conductor portions 123. The conductor portion 121, the conductor portion 122, and the two conductor portions 123 are spaced apart from each other.

[0031] The conductor portion 121 and the conductor portion 122 are spaced apart in the second direction y. The conductor portion 121 and the conductor portion 122 are aligned in the second direction y. The two conductor portions 123 are respectively arranged near two corners on one side (y2 side) of the four corners of the support substrate 10 in a plan view in the second direction y. The two conductor portions 123 are located on the opposite side of the conductor portion 121 in the second direction y, sandwiching a part of the conductor portion 122 (a partition portion 1221 described below). The dimension of the conductor portion 121 in the thickness direction z, the dimension of the conductor portion 122 in the thickness direction z, and the dimensions of the two conductor portions 123 in the thickness direction z are all the same.

[0032] The conductor portion 121 is located on the other side (y1 side) in the second direction y with respect to the conductor portion 122. The conductor portion 121 is located closer to the power terminal 17 in the second direction y than the conductor portion 122. The conductor portion 121 has, for example, a rectangular shape in a plan view, but the shape of the conductor portion 121 in a plan view is not limited in any way. A plurality of semiconductor elements 21 and a signal substrate 601 are joined to the conductor portion 121.

[0033] The conductor portion 121 has a conductor principal surface 121a. As shown in FIG. 20 and other figures, the conductor principal surface 121a faces upward in the thickness direction z. The conductor principal surface 121a faces the same direction as the substrate principal surface 11a. In the illustrated example, the conductor principal surface 121a is flat and parallel to the substrate principal surface 11a. The conductor principal surface 121a faces the multiple semiconductor elements 21.

[0034] As shown in Figures 12 to 14, the conductor portion 121 includes two exposed regions 121b. For ease of understanding, the two exposed regions 121b are depicted as dots in Figures 12 to 14. Each of the two exposed regions 121b is exposed from the upper surface of the sealing resin 50 (the resin main surface 51 described below). As shown in Figure 12, the two exposed regions 121b are arranged near the edge of the conductor main surface 121a on the y1 side in the second direction y. The two exposed regions 121b are located closer to the y1 side of the semiconductor element 21 in the second direction y. The two exposed regions 121b are located on both sides of the signal substrate 602 in the first direction x, sandwiching the signal substrate 602 therebetween.

[0035] The conductor portion 122 is located on one side (y2 side) of the conductor portion 121 in the second direction y. The conductor portion 122 includes two partition portions 1221, 1222. A plurality of semiconductor elements 22 are joined to the partition portion 1221. The partition portion 1222 is located on the opposite side of the conductor portion 121 in the second direction y with respect to the partition portion 1221. The partition portion 1222 is located closer to the power terminal 15 than the partition portion 1221. The partition portion 1222 is connected to one side (y2 side) of the partition portion 1221 in the second direction y. The dimension of the partition portion 1221 in the first direction x is the same as the dimension of the conductor portion 121 in the first direction x. The dimension of the partition portion 1222 in the first direction x is smaller than the dimension of the partition portion 1221 in the first direction x.

[0036] The conductor portion 122 has a conductor principal surface 122a. As shown in FIG. 20 and other figures, the conductor principal surface 122a faces upward in the thickness direction z. The conductor principal surface 122a faces the same direction as the substrate principal surface 11a. In the illustrated example, the conductor principal surface 122a is flat and parallel to the substrate principal surface 11a. The conductor principal surface 122a faces the multiple semiconductor elements 22.

[0037] As shown in Figures 12 to 14, the conductor principal surface 122a includes two exposed regions 122b. For ease of understanding, the two exposed regions 122b are depicted as dots in Figures 12 to 14. Each of the two exposed regions 122b is exposed from the upper surface of the sealing resin 50 (a resin principal surface 51 described below). As shown in Figure 12, the two exposed regions 122b are disposed near the edge of the conductor principal surface 122a on the y2 side in the second direction y. The two exposed regions 122b are located on the opposite side of the signal substrate 601 from the multiple semiconductor elements 22 in the second direction y.

[0038] The two conductor portions 123 are located on the opposite side of the conductor portion 121 in the second direction y, with the partition portion 1221 as the reference. The two conductor portions 123 are located closer to the power terminal 16 than the conductor portion 121 in the second direction y. The two conductor portions 123 are located on opposite sides of the partition portion 1222 in the first direction x. The power terminal 16 and the conductive member 32 are respectively joined to the two conductor portions 123.

[0039] Each of the two conductor portions 123 has a conductor principal surface 123a. As shown in Figure 20 and other figures, the conductor principal surface 123a of each conductor portion 123 faces upward in the thickness direction z. The conductor principal surface 123a of each conductor portion 123 faces in the same direction as the substrate principal surface 11a. In the illustrated example, the conductor principal surface 123a of each conductor portion 123 is flat and parallel to the substrate principal surface 11a.

[0040] As shown in Figures 12 to 14, each of the conductor principal surfaces 123a of the two conductor portions 123 includes an exposed region 123b. For ease of understanding, the two exposed regions 123b are depicted as dots in Figures 12 to 14. The exposed region 123b of each conductor portion 123 is exposed from the upper surface of the sealing resin 50 (the resin principal surface 51 described below). In each conductor portion 123, the exposed region 123b is located near the edge of the conductor principal surface 123a on the y2 side in the second direction y, as shown in Figure 12. In each conductor portion 123, the exposed region 123b is located on the y2 side in the second direction y of the conductor principal surface 123a to which the conductive member 32 is joined.

[0041] As shown in Figures 16 and 20 to 25, the back surface metal layer 13 is located below (on the z1 side of) the insulating substrate 11 in the thickness direction z. The back surface metal layer 13 is in contact with and bonded to the substrate back surface 11b. The composition of the back surface metal layer 13 includes copper (Cu), similar to the main surface metal layer 12, but may be other metals. Unlike this example, the composition of the back surface metal layer 13 may be different from that of the main surface metal layer 12. In the illustrated example, the back surface metal layer 13 is rectangular in plan view. The back surface metal layer 13 is surrounded by the periphery of the insulating substrate 11 in plan view.

[0042] The main surface metal layer 12 and the back surface metal layer 13 are metal bodies individually bonded to both sides of the insulating substrate 11 in the thickness direction z. In the main surface metal layer 12, the metal body is divided into multiple conductor portions 121, 122, and 123 by patterning. That is, the conductor portions 121, 122, and two conductor portions 123 are patterns of metal bodies formed on the substrate main surface 11a of the insulating substrate 11. In an example where the support substrate 10 is an AMB substrate, the main surface metal layer 12 and the back surface metal layer 13 are each bonded by an active metal bonding method. In contrast to this example, in an example where the support substrate 10 is a DCB substrate, the main surface metal layer 12 and the back surface metal layer 13 are each bonded to the insulating substrate 11 by a direct bonding method.

[0043] As shown in Figures 16 to 25, each semiconductor package B10 further includes a bonding layer 109. The bonding layer 109 bonds the back surface metal layer 13 (support substrate 10) and the heat dissipation member C10. The bonding layer 109 is interposed between the lower surface of the back surface metal layer 13 and the first surface 71a of the base 71. The bonding layer 109 may be conductive or non-conductive, and may be, for example, solder. Alternatively, the bonding layer 109 may be a sintered body of metal particles. Preferably, the bonding layer 109 has high thermal conductivity. As can be seen from Figures 15 and 19, the periphery of the bonding layer 109 in plan view is covered by the sealing resin 50. Therefore, the bonding layer 109 is enclosed within the periphery of the sealing resin 50 in plan view. The lower surface of the bonding layer 109 (the surface facing downward in the thickness direction z) is flush with the lower surface of the sealing resin 50 (the resin back surface 52 described below).

[0044] The plurality of semiconductor elements 21 and the plurality of semiconductor elements 22 are, for example, metal-oxide-semiconductor field-effect transistors (MOSFETs). Alternatively, the plurality of semiconductor elements 21 and the plurality of semiconductor elements 22 may be other transistors such as insulated gate bipolar transistors (IGBTs) and bipolar transistors, or diodes. In this embodiment, the plurality of semiconductor elements 21 and the plurality of semiconductor elements 22 are each n-channel MOSFETs with a vertical structure.

[0045] The plurality of semiconductor elements 21 and the plurality of semiconductor elements 22 each include a compound semiconductor substrate. The composition of the compound semiconductor substrate includes silicon (Si), a wide bandgap semiconductor with a wider bandgap than Si, or an ultra-wide bandgap semiconductor with an even wider bandgap than the wide bandgap semiconductor. Wide bandgap semiconductors include, but are not limited to, silicon carbide (SiC) and gallium nitride (GaN). Ultra-wide bandgap semiconductors include, but are not limited to, gallium oxide (GaO), diamond, and aluminum nitride (AlN). In this embodiment, the composition of each compound semiconductor substrate of the plurality of semiconductor elements 21 and the plurality of semiconductor elements 22 includes SiC. Note that the types and compositions of the plurality of semiconductor elements 21 and the plurality of semiconductor elements 22 are not limited to being the same, and may be different.

[0046] 14 and 17 , the semiconductor elements 21 are mounted on the conductor portion 121. The semiconductor elements 21 are arranged along the first direction x. In the illustrated example, each semiconductor package B10 includes six semiconductor elements 21, but the number of semiconductor elements 21 is not limited to six and can be changed as appropriate depending on the specifications of the semiconductor module A10 (each semiconductor package B10).

[0047] 17 , each of the multiple semiconductor elements 21 has an element main surface 21a and an element back surface 21b. The element main surface 21a and the element back surface 21b are spaced apart in the thickness direction z. The element main surface 21a and the element back surface 21b face opposite each other in the thickness direction z. The element main surface 21a faces upward in the thickness direction z, and the element back surface 21b faces downward in the thickness direction z. The element main surface 21a faces in the same direction as the substrate main surface 11a in the thickness direction z. The element back surface 21b faces the support substrate 10.

[0048] Each of the semiconductor elements 21 has a back surface electrode 211 and a plurality of principal surface electrodes 212, 213, and 214. The back surface electrode 211 and the plurality of principal surface electrodes 212, 213, and 214 described below are common to all the semiconductor elements 21 unless otherwise specified.

[0049] As shown in FIG. 17 , the back surface electrode 211 is disposed on the element back surface 21b and exposed thereon. As shown in FIGS. 14 and 17 , the plurality of principal surface electrodes 212, 213, and 214 are disposed on the element main surface 21a and exposed thereon. In the illustrated example, the principal surface electrode 212 is divided into two regions in a plan view. The two regions are aligned in the first direction x. Unlike this example, the principal surface electrode 212 may be divided into three or more regions, or may be a single region without being divided. The area of ​​the principal surface electrode 213 in a plan view is smaller than the area of ​​the principal surface electrode 212 in a plan view. The two principal surface electrodes 214 are disposed on either side of the principal surface electrode 213 in the first direction x, sandwiching the principal surface electrode 213 therebetween. Unlike the illustrated example, each semiconductor element 21 may include only one of the two principal surface electrodes 214 or may include neither of the two principal surface electrodes 214 .

[0050] Each semiconductor element 21 is switched between an ON state and an OFF state by a drive signal input to the principal surface electrode 213. The operation of each semiconductor element 21 alternately switching between the ON state and the OFF state is called a switching operation. In the ON state, the back surface electrode 211 and the principal surface electrode 212 are conductive, and in the OFF state, the back surface electrode 211 and the principal surface electrode 212 are non-conductive. In each semiconductor element 21, the back surface electrode 211 and the principal surface electrode 212 are conductive in response to a drive signal input to the principal surface electrode 213. The two principal surface electrodes 214 are short-circuited to the principal surface electrode 212 inside each semiconductor element 21. In this example, the potential of each of the two principal surface electrodes 214 is equal to the potential of the principal surface electrode 212. In an example where each semiconductor element 21 is a MOSFET, the back surface electrode 211 is a drain electrode, the main surface electrode 212 is a source electrode, the main surface electrode 213 is a gate electrode, and each main surface electrode 214 is a source sense electrode.

[0051] The semiconductor module A10 further includes a plurality of conductive bonding layers 219. As shown in Fig. 17, each of the plurality of semiconductor elements 21 is bonded to the conductor portion 121 by a corresponding one of the plurality of conductive bonding layers 219. Each of the plurality of conductive bonding layers 219 is interposed between the back electrode 211 of the corresponding semiconductor element 21 and the conductor portion 121, thereby establishing electrical continuity therebetween. Each of the conductive bonding layers 219 is, for example, solder. Alternatively, each of the conductive bonding layers 219 may include a sintered body of metal particles.

[0052] 14 and other figures, the semiconductor elements 22 are mounted on the partition portions 1221 of the conductor portion 122. The semiconductor elements 22 are arranged along the first direction x. In the illustrated example, each semiconductor package B10 includes six semiconductor elements 22, but the number of semiconductor elements 22 is not limited to six and can be changed as appropriate depending on the specifications of the semiconductor module A10 (each semiconductor package B10).

[0053] 18 , each of the multiple semiconductor elements 22 has an element main surface 22 a and an element back surface 22 b. The element main surface 22 a and the element back surface 22 b are spaced apart in the thickness direction z. The element main surface 22 a and the element back surface 22 b face opposite each other in the thickness direction z. The element main surface 22 a faces upward in the thickness direction z, and the element back surface 22 b faces downward in the thickness direction z. The element main surface 22 a faces the same direction as the substrate main surface 11 a in the thickness direction z. The element back surface 22 b faces the support substrate 10.

[0054] Each of the semiconductor elements 22 has a back surface electrode 221 and a plurality of principal surface electrodes 222, 223, and 224. The back surface electrode 221 and the plurality of principal surface electrodes 222, 223, and 224 described below are common to all the semiconductor elements 22 unless otherwise specified.

[0055] As shown in FIG. 18 , the back surface electrode 221 is disposed on the element back surface 22b and exposed thereon. As shown in FIGS. 14 and 18 , the plurality of principal surface electrodes 222, 223, and 224 are disposed on the element main surface 22a and exposed thereon. In the illustrated example, the principal surface electrode 222 is divided into two regions in a plan view. The two regions are aligned in the first direction x. Unlike this example, the principal surface electrode 222 may be divided into three or more regions, or may be a single region without being divided. The area of ​​the principal surface electrode 223 in a plan view is smaller than the area of ​​the principal surface electrode 222 in a plan view. The two principal surface electrodes 224 are disposed on either side of the principal surface electrode 223 in the first direction x, sandwiching the principal surface electrode 223 therebetween. Unlike the illustrated example, each semiconductor element 22 may include only one of the two principal surface electrodes 224 or may include neither of the two principal surface electrodes 224 .

[0056] Each semiconductor element 22 is switched between an ON state and an OFF state by a drive signal input to the principal surface electrode 223. The operation of each semiconductor element 22 alternately switching between the ON state and the OFF state is called a switching operation. In the ON state, the back surface electrode 221 and the principal surface electrode 222 are conductive, and in the OFF state, the back surface electrode 221 and the principal surface electrode 222 are non-conductive. In each semiconductor element 22, the back surface electrode 221 and the principal surface electrode 222 are conductive in response to a drive signal input to the principal surface electrode 223. The two principal surface electrodes 224 are short-circuited to the principal surface electrode 222 inside each semiconductor element 22. In this example, the potential of each of the two principal surface electrodes 224 is equal to the potential of the principal surface electrode 222. In an example in which each semiconductor element 22 is a MOSFET, the back surface electrode 221 is a drain electrode, the main surface electrode 222 is a source electrode, the main surface electrode 223 is a gate electrode, and each main surface electrode 224 is a source sense electrode.

[0057] The semiconductor module A10 further includes a plurality of conductive bonding layers 229. As shown in FIG. 18 , each of the plurality of semiconductor elements 22 is bonded to the conductor portion 122 (partition portion 1221) by a corresponding one of the plurality of conductive bonding layers 229. Each of the plurality of conductive bonding layers 229 is interposed between the back electrode 221 of the corresponding semiconductor element 22 and the conductor portion 122, providing electrical continuity therebetween. Each of the conductive bonding layers 229 is, for example, solder. Alternatively, each of the conductive bonding layers 229 may include a sintered body of metal particles.

[0058] In the semiconductor module A10, the back electrodes 211 (drain electrodes) of the multiple semiconductor elements 21 are electrically connected, and the main surface electrodes 212 (source electrodes) are electrically connected. That is, the multiple semiconductor elements 21 are electrically connected in parallel with each other. In the multiple semiconductor elements 22, the back electrodes 221 (drain electrodes) of the multiple semiconductor elements 22 are electrically connected, and the main surface electrodes 222 (source electrodes) of the multiple semiconductor elements 22 are electrically connected. That is, the multiple semiconductor elements 22 are electrically connected in parallel with each other. Furthermore, in the semiconductor module A10, the back electrodes 211 (drain electrodes) of the multiple semiconductor elements 21 are electrically connected to the main surface electrodes 222 (source electrodes) of the multiple semiconductor elements 22. That is, the multiple semiconductor elements 21 and the multiple semiconductor elements 22 are connected in series. The semiconductor module A10 configures a half-bridge circuit in which the multiple semiconductor elements 22 form an upper arm circuit and the multiple semiconductor elements 21 form a lower arm circuit.

[0059] As shown in FIGS. 9 to 12 and 14 to 25 , the sealing resin 50 covers the semiconductor elements 21, portions of the two conductor portions 123, and the insulating substrate 11. Furthermore, the sealing resin 50 covers portions of the conductor portion 121, portions of the conductor portion 122, the semiconductor elements 22, the two conductive members 31, 32, the connecting members 41 to 45, the two signal boards 601, 602, and portions of the signal terminals 19 (the signal terminals 191 to 194, 196, and 197 described below). In this embodiment, the power terminals 15, 16, and 17 are disposed outside the sealing resin 50. The sealing resin 50 has electrical insulation properties. The sealing resin 50 includes, for example, a black epoxy resin. The sealing resin 50 is formed, for example, by molding. The sealing resin 50 has a resin main surface 51, a resin back surface 52, and multiple resin side surfaces 531 to 534.

[0060] As shown in FIGS. 16 and 20 to 25, the resin main surface 51 and the resin back surface 52 are spaced apart in the thickness direction z. The resin main surface 51 and the resin back surface 52 face opposite each other in the thickness direction z. The resin main surface 51 faces upward in the thickness direction z, and the resin back surface 52 faces downward in the thickness direction z. The resin main surface 51 faces the same direction in the thickness direction z as the substrate main surface 11a, the element main surface 21a, and the element main surface 22a. Each of the signal terminals 19 protrudes upward in the thickness direction z from the resin main surface 51. As shown in FIGS. 15, 16, and 20 to 25, the lower surface of the bonding layer 109 is exposed from the resin back surface 52. As shown in FIG. 15, the resin back surface 52 has a rectangular ring shape surrounding the bonding layer 109 in a plan view.

[0061] Each of the multiple resin side surfaces 531 to 534 is connected to the resin main surface 51. As shown in FIGS. 9 and 16 , the pair of resin side surfaces 531, 532 are spaced apart in the second direction y. The resin side surface 531 faces one side of the second direction y (the y2 side), and the resin side surface 532 faces the other side of the second direction y (the y1 side). Each of the pair of resin side surfaces 531, 532 extends in the first direction x. In the illustrated example, the pair of resin side surfaces 531, 532 are connected to the resin main surface 51 as well as the resin back surface 52. As shown in FIGS. 9 and 20 to 25 , the pair of resin side surfaces 533, 534 are spaced apart in the first direction x. The resin side surface 533 faces one side of the first direction x (the x2 side), and the resin side surface 534 faces the other side of the first direction x (the x1 side). 15 to 17, each of the pair of resin side surfaces 533 and 534 is connected to the resin main surface 51 as well as the resin rear surface 52.

[0062] The sealing resin 50 has a main surface opening 56. The main surface opening 56 is formed in the resin main surface 51. As shown in Fig. 10 , the main surface opening 56 exposes a portion of the main surface metal layer 12 from the resin main surface 51. The main surface opening 56 includes two openings 561, two openings 562, and two openings 563.

[0063] Each of the two openings 561 overlaps the conductor portion 121 in a planar view. As shown in FIG. 12 and other figures, the two openings 561 individually expose two different regions (two exposed regions 121b) of the conductor principal surface 121a of the conductor portion 121. The two openings 561 expose the two exposed regions 121b from the resin principal surface 51. A power terminal 17 is inserted into each of the two openings 561. The two openings 561 are aligned in the first direction x. In the illustrated example, the two openings 561 are arranged on both sides of the signal terminals 191, 193, and 197 in the first direction x. Each of the two openings 561 has a rectangular shape in a planar view. The long sides of each of the two openings 561 extend in the first direction x and the short sides extend in the second direction y. Unlike this example, each of the two openings 561 may have a short side in the first direction x and a long side in the second direction y. Furthermore, the planar shape of each of the two openings 561 is not limited to a rectangle. In the illustrated example (e.g., FIGS. 20 and 25 ), each of the two openings 561 is tapered. In this example, the cross section of each opening 561 perpendicular to the thickness direction z gradually becomes smaller as it approaches the conductor portion 121 from the resin main surface 51 in the thickness direction z. Unlike this example, each opening 561 does not need to be tapered.

[0064] Each of the two openings 562 overlaps the conductor portion 122 in a planar view. As shown in FIG. 12 and other figures, the two openings 562 individually expose two different regions (two exposed regions 122b) of the conductor principal surface 122a of the conductor portion 122. The two openings 562 expose the two exposed regions 122b from the resin principal surface 51. A power terminal 15 is inserted into each of the two openings 562. The two openings 562 are aligned in the first direction x. Each of the two openings 562 has a rectangular shape in a planar view. Each of the two openings 562 has a long side extending in the second direction y and a short side extending in the first direction x. Unlike this example, each of the two openings 562 may have a short side extending in the second direction y and a long side extending in the first direction x. The planar view shape of each of the two openings 562 is not limited to a rectangle. In the illustrated example (e.g., FIG. 21 ), each of the two openings 562 is tapered. In this example, the cross section of each opening 562 perpendicular to the thickness direction z gradually decreases in size from the resin main surface 51 toward the conductor portion 122. Unlike this example, each opening 562 does not need to be tapered.

[0065] The two openings 563 overlap the two conductor portions 123, respectively, in a plan view. As shown in FIG. 12 and other figures, the two openings 563 each expose a portion (exposed region 123b) of the conductor principal surface 123a of the corresponding conductor portion 123. Each of the two openings 563 exposes the exposed region 123b of the corresponding conductor portion 123 from the resin principal surface 51. A power terminal 16 is inserted through each of the two openings 563. The two openings 563 are aligned in the first direction x. The two openings 563 are arranged on both sides of the two openings 562 in the first direction x. Each of the two openings 563 has a rectangular shape in a plan view. The long side of each of the two openings 563 is in the second direction y and the short side is in the first direction x. Unlike this example, the short side of each of the two openings 563 may be in the second direction y and the long side is in the first direction x. Furthermore, the planar shape of each of the two openings 563 is not limited to a rectangle. In the illustrated example (e.g., FIGS. 20 and 21 ), each of the two openings 563 is tapered. In this example, the cross section of each opening 563 perpendicular to the thickness direction z gradually becomes smaller as it approaches the conductor portion 123 from the resin main surface 51 in the thickness direction z. Unlike this example, each opening 563 does not need to be tapered.

[0066] 9, 10, 16, and 25, the resin main surface 51 has a recess 571 and two recesses 572. As shown in these figures, the recess 571 and the two recesses 572 are each recessed downward in the thickness direction z from the resin main surface 51. In a plan view, the recess 571 and the two recesses 572 are each interposed between the main surface opening 56 and any one of the plurality of signal terminals 19.

[0067] In a plan view, the recess 571 is disposed between the two openings 562 and 563 and the plurality of signal terminals 192, 194, and 196. In a plan view, the recess 571 has a strip shape extending in the first direction x. In the illustrated example, the recess 571 extends from the resin side surface 533 to the resin side surface 534.

[0068] One of the two recesses 572 is located between one of the two openings 561 and the plurality of signal terminals 191, 193, and 197. The other of the two recesses 572 is located between the other of the two openings 561 and the plurality of signal terminals 191, 193, and 197. Each of the two recesses 572 has a strip shape extending in the second direction y in plan view.

[0069] Each of the plurality of power terminals 15, 16, and 17 is electrically connected to one of the plurality of semiconductor elements 21 and the plurality of semiconductor elements 22. A current corresponding to the power before or after conversion by the switching operations of the plurality of semiconductor elements 21 and the plurality of semiconductor elements 22 flows through each of the plurality of power terminals 15, 16, and 17.

[0070] The power terminal 15 is joined to the conductor portion 122 (partition portion 1222). This joining is performed, for example, by laser welding. Alternatively, any joining method capable of electrical connection, such as ultrasonic joining or joining using a conductive adhesive, may be appropriately employed. The power terminal 15 is inserted through the two openings 562 and joined to the two exposed regions 122b of the conductor portion 122, respectively. The power terminal 15 is electrically connected to the back electrodes 221 (drain electrodes of the upper arm circuits) of the multiple semiconductor elements 22 via the conductor portion 122. The power terminal 15 is a P terminal (positive terminal) to which a DC power supply voltage to be converted into power is applied. As shown in FIG. 11 and other figures, the power terminal 15 is located on the opposite side of the conductor portion 121 in the second direction y, with the partition portion 1221 (part of the conductor portion 122) sandwiched therebetween. As shown in FIG. 11, the power terminal 15 is located on the opposite side of the multiple semiconductor elements 21 in the second direction y, with the multiple semiconductor elements 22 sandwiched therebetween.

[0071] As shown in FIGS. 9, 11, 21, and the like, the power terminal 15 includes two joining portions 151, a suspension portion 152, and an extension portion 153.

[0072] The two joints 151 are each individually joined to a portion of the conductor principal surface 122a of the conductor portion 122 (specifically, the two exposed regions 122b). The two joints 151 are each individually housed in the two openings 562. Therefore, the peripheries of the two joints 151 are each enclosed within the peripheries of the corresponding openings 562 in a plan view.

[0073] The suspension portion 152 connects two joint portions 151. In the illustrated example, the suspension portion 152 extends in the first direction x from each joint portion 151. In a plan view, the suspension portion 152 has a strip shape extending in the first direction x. Most of the suspension portion 152 is located above each joint portion 151 in the thickness direction z. Furthermore, most of the suspension portion 152 is located above the resin main surface 51 in the thickness direction z. The end of the suspension portion 152 on the side connected to each joint portion 151 is bent downward in the thickness direction z and inserted into the corresponding opening 562.

[0074] The extension portion 153 protrudes from the suspension portion 152 to one side in the second direction y (y2 side). The extension portion 153 causes a part of the power terminal 15 to protrude from the power terminal 16 in a plan view.

[0075] The power terminal 16 is joined to a corresponding one of the two conductor portions 123. This joining is performed, for example, by laser welding. Alternatively, any joining method capable of electrical connection, such as ultrasonic joining or joining using a conductive adhesive, may be appropriately employed. The power terminal 16 is inserted through the two openings 563 and joined to the exposed regions 123b of the two conductor portions 123. Each of the two power terminals 16 is electrically connected to the principal surface electrodes 212 (source electrodes of the lower arm circuits) of the multiple semiconductor elements 21 via the corresponding conductor portion 123 and the conductive member 32. The power terminal 16 is an N-terminal (negative terminal) to which a DC power supply voltage to be converted is applied. As shown in FIG. 11 and other figures, the power terminal 16 is located on the opposite side of the conductor portion 121 in the second direction y, with the partition portion 1221 (part of the conductor portion 122) sandwiched therebetween. As shown in FIG. 11 , the power terminal 16 is located on the opposite side of the semiconductor elements 21 in the second direction y, with the semiconductor elements 22 sandwiched therebetween.

[0076] As shown in FIGS. 9, 11, and 21, the power terminal 16 includes two joining portions 161 and a suspension portion 162.

[0077] The two joint portions 161 are individually joined to portions (specifically, exposed regions 123b) of the conductor principal surfaces 123a of the two conductor portions 123. The two joint portions 161 are individually housed in the two openings 563. Thus, the peripheries of the two joint portions 161 are respectively contained within the peripheries of the corresponding openings 563 in a plan view.

[0078] The suspension portion 162 connects two joint portions 161. In the illustrated example, the suspension portion 162 extends from each joint portion 161 in the first direction x. In a plan view, the suspension portion 162 has a strip shape extending in the first direction x. Most of the suspension portion 162 is located above each joint portion 161 in the thickness direction z. The end of the suspension portion 162 that connects to each joint portion 161 is bent downward in the thickness direction z and inserted into the corresponding opening 563. In the illustrated example, most of the suspension portion 162 is located above the suspension portion 152 (power terminal 15) in the thickness direction z. Furthermore, most of the suspension portion 162 is located above the resin main surface 51 in the thickness direction z. In a plan view, the suspension portion 152 completely overlaps the suspension portion 162.

[0079] The power terminal 17 is joined to the conductor portion 121. This joining is performed, for example, by laser welding. Alternatively, any joining method capable of electrical connection, such as ultrasonic joining or joining using a conductive adhesive, may be appropriately employed. The power terminal 17 is inserted through the two openings 561 and joined to the two exposed regions 121b of the conductor portion 121, respectively. The power terminal 17 is electrically connected to the back electrodes 211 (drain electrodes of the lower arm circuit) of the multiple semiconductor elements 21 via the conductor portion 121, and is electrically connected to the main surface electrodes 222 (source electrodes of the upper arm circuit) of the multiple semiconductor elements 22 via the conductor portion 121 and the conductive member 31. AC power converted by the multiple semiconductor elements 21 and the multiple semiconductor elements 22 is output from the power terminal 17. In other words, the power terminal 17 is an output terminal for the AC power. As shown in FIG. 11 , the power terminal 17 is located on the opposite side of the multiple semiconductor elements 22 from the multiple semiconductor elements 21 in the second direction y.

[0080] As shown in FIGS. 9, 11, 25, and the like, the power terminal 17 includes two joining portions 171 and a suspension portion 172.

[0081] The two joint portions 171 are individually joined to parts of the conductor principal surface 121a (specifically, the two exposed regions 121b) of the conductor portion 121. The two joint portions 171 are individually housed in the two openings 561. Thus, the peripheries of the two joint portions 171 are respectively contained within the peripheries of the corresponding openings 561 in a plan view.

[0082] The suspension portion 172 connects the two joint portions 171. In the illustrated example, the suspension portion 172 extends a short distance from each joint portion 171 along the second direction y and then bends in the first direction x. More specifically, in a plan view, the suspension portion 172 extends from one of the two joint portions 171 (e.g., the joint portion 171 on the x1 side in the first direction x) along the second direction y (e.g., the y1 side) and bends in the first direction x (e.g., the x2 side). Then, it bends in the second direction y (e.g., the y2 side) and connects to the other of the two joint portions 171 (e.g., the joint portion 171 on the x2 side in the first direction x). With this configuration, the strip-shaped portion of the suspension portion 172 extending along the first direction x is located outside the sealing resin 50 in a plan view. Most of the suspension portion 172 is strip-shaped and extends in the first direction x in a plan view. Most of this suspension portion 172 is located above each joint 171 in the thickness direction z. Also, most of this suspension portion 172 is located above each resin main surface 51 in the thickness direction z. The end of the suspension portion 172 that is connected to each joint 171 is bent downward in the thickness direction z and inserted into the corresponding opening 561.

[0083] The shapes of the multiple power terminals 15, 16, and 17 are not limited to the above example and can be modified as appropriate depending on the specifications of each semiconductor package B10. For example, in the power terminal 15, the two joint portions 151 do not have to be connected by the suspension portion 152. In this example, each semiconductor package B10 includes two power terminals 15. This configuration can also be similarly modified for the other power terminals 16 and 17.

[0084] The pair of signal boards 601, 602 constitute part of the conductive paths between the multiple signal terminals 19 and the multiple semiconductor elements 21 and the multiple semiconductor elements 22. As shown in FIGS. 13 and 14 , the signal board 601 is located on the y1 side of the multiple semiconductor elements 21 in the second direction y. As shown in FIGS. 16 and 25 , the signal board 601 is bonded to the conductor portion 121. As shown in FIGS. 13 and 14 , the signal board 602 is located on the y2 side of the multiple semiconductor elements 22 in the second direction y. As shown in FIGS. 16 and 22 , the signal board 602 is bonded to the conductor portion 122. In the illustrated example, the signal board 602 is bonded so as to overlap the boundary between the two partition portions 1221, 1222 in a plan view. Each of the pair of signal boards 601, 602 is, for example, a DCB board or an AMB board. Unlike this example, each of the pair of signal boards 601, 602 may be a printed circuit board.

[0085] Each of the pair of signal substrates 601, 602 has an insulating layer 61, a wiring layer 62, a metal layer 63, and a plurality of sleeves 64. Each of the pair of signal substrates 601, 602 is covered with a sealing resin 50 except for a portion of each of the plurality of sleeves 64. Unless otherwise specified, the insulating layer 61, the wiring layer 62, the metal layer 63, and the plurality of sleeves 64 described below are common to each of the pair of signal substrates 601, 602.

[0086] The insulating layer 61 is interposed between the wiring layer 62 and the metal layer 63 in the thickness direction z. The insulating layer 61 may be made of, for example, ceramics. Alternatively, the insulating layer 61 may be made of an insulating resin sheet.

[0087] 22 and 25, the wiring layer 62 is located above the insulating layer 61 in the thickness direction z. The composition of the wiring layer 62 is not limited in any way, but may include copper. As shown in FIG. 14, the wiring layer 62 includes a plurality of wiring portions 621 to 624. The plurality of wiring portions 621 to 624 are spaced apart from one another. The planar shape, arrangement, size, and the like of each of the wiring portions 621 to 624 are not limited to the examples shown in the drawings.

[0088] 22 and 25 , the metal layer 63 is located on the opposite side of the wiring layer 62 in the thickness direction z, with the insulating layer 61 sandwiched therebetween. The composition of the metal layer 63 is not limited in any way, but may include copper. The metal layer 63 of the signal substrate 601 is bonded to the conductor portion 121 by an adhesive layer (not shown). The metal layer 63 of the signal substrate 602 is bonded to the conductor portion 122 by an adhesive layer (not shown). These adhesive layers are made of materials that may or may not be conductive. These adhesive layers are, for example, solder.

[0089] 16 , 22 , and 25 , each of the multiple sleeves 64 is bonded to the wiring layer 62 by a conductive bonding layer (e.g., solder) not shown. The multiple sleeves 64 are made of a conductive material such as metal. Each of the multiple sleeves 64 has a cylindrical shape extending along the thickness direction z. One end of each of the multiple sleeves 64 in the thickness direction z (an edge on the z1 side in the thickness direction z) is conductively bonded to the wiring layer 62. As shown in FIGS. 16 , 22 , and 25 , the other end of each of the multiple sleeves 64 in the thickness direction z (an edge on the z2 side in the thickness direction z) is exposed from the sealing resin 50.

[0090] As shown in FIG. 14 , the thermistor 23 is conductively connected across the wiring portion 623 of the signal substrate 601 and the wiring portion 624 of the signal substrate 601. The thermistor 23 is, for example, an NTC (Negative Temperature Coefficient) thermistor. An NTC thermistor has the characteristic that its resistance decreases gradually with increasing temperature. The thermistor 23 is used as a temperature detection sensor for the semiconductor module A10.

[0091] Each of the signal terminals 19 (signal terminals 191 to 194, 196, and 197) is formed by a metal pin and extends in the thickness direction z. The signal terminals 19 protrude from the sealing resin 50 (a resin main surface 51, described below). The signal terminals 19 (signal terminals 191 to 194, 196, and 197) are individually press-fitted into the sleeves 64 of the pair of signal boards 601 and 602. As a result, each of the signal terminals 19 is supported by one of the sleeves 64 and is electrically connected to one of the wiring layers 62 of the pair of signal boards 601 and 602. The signal terminals 191 to 194 and 196 are electrically connected to one of the semiconductor elements 21 and the semiconductor elements 22, respectively. The two signal terminals 197 are not electrically connected (non-conductive) to either the semiconductor elements 21 or the semiconductor elements 22, but are electrically connected to the thermistor 23.

[0092] 14 , the signal terminal 191 is press-fitted into the sleeve 64 joined to the wiring portion 621 of the signal substrate 601. As a result, the signal terminal 191 is supported by the sleeve 64 and is electrically connected to the wiring portion 621 of the signal substrate 601. The signal terminal 191 is electrically connected to each of the main surface electrodes 213 of the plurality of semiconductor elements 21. A drive signal for driving each semiconductor element 21 is input to the signal terminal 191 (a gate voltage is applied).

[0093] 14 , the signal terminal 192 is press-fitted into the sleeve 64 joined to the wiring portion 621 of the signal board 602. As a result, the signal terminal 192 is supported by the sleeve 64 and is electrically connected to the wiring portion 621 of the signal board 602. The signal terminal 192 is electrically connected to each of the main surface electrodes 223 of the plurality of semiconductor elements 22. A drive signal for driving each semiconductor element 22 is input to the signal terminal 192 (a gate voltage is applied).

[0094] 14 , the signal terminal 193 is located next to the signal terminal 191 in the first direction x. As shown in FIG. 14 , the signal terminal 193 is press-fitted into the sleeve 64 joined to the wiring portion 622 of the signal substrate 601. As a result, the signal terminal 193 is supported by the sleeve 64 and is electrically connected to the wiring portion 622 of the signal substrate 601. The signal terminal 193 is electrically connected to the main surface electrodes 214 of the multiple semiconductor elements 21. A voltage corresponding to the maximum current among the currents flowing through the main surface electrodes 214 of the multiple semiconductor elements 21 is applied to the signal terminal 193.

[0095] 14 , the signal terminal 194 is located next to the signal terminal 192 in the first direction x. As shown in FIG. 14 , the signal terminal 194 is press-fitted into the sleeve 64 joined to the wiring portion 622 of the signal substrate 602. As a result, the signal terminal 194 is supported by the sleeve 64 and is electrically connected to the wiring portion 622 of the signal substrate 602. The signal terminal 194 is electrically connected to the main surface electrodes 224 of the multiple semiconductor elements 22. A voltage corresponding to the maximum current among the currents flowing through the main surface electrodes 224 of the multiple semiconductor elements 22 is applied to the signal terminal 194.

[0096] As shown in Fig. 14 , the signal terminal 196 is located on the opposite side of the signal terminal 192 in the first direction x, with the signal terminal 194 sandwiched therebetween. As shown in Fig. 14 , the signal terminal 196 is press-fitted into the sleeve 64 joined to the wiring portion 623 of the signal board 602. As a result, the signal terminal 196 is supported by the sleeve 64 and is electrically connected to the wiring portion 623 of the signal board 602. The signal terminal 196 is electrically connected to the conductor portion 122. A voltage equivalent to the DC power input to the power terminal 15 is applied to the signal terminal 196.

[0097] 14 , the pair of signal terminals 197 are located on the opposite side of the signal terminal 191 in the first direction x with the signal terminal 193 sandwiched therebetween, and the pair of signal terminals 197 are adjacent to each other in the first direction x. As shown in FIG. 14 , the pair of signal terminals 197 are individually press-fitted into a pair of sleeves 64 joined to the wiring portion 623 of the signal board 601 and the wiring portion 624 of the signal board 601, respectively. As a result, the pair of signal terminals 197 are individually supported by the pair of sleeves 64 and are individually conducted to the wiring portion 623 of the signal board 601 and the wiring portion 624 of the signal board 601. The pair of signal terminals 197 are conducted to the thermistor 23.

[0098] Each of the plurality of connection members 41 to 45 electrically connects parts spaced apart from one another. Each of the plurality of connection members 41 to 45 is, for example, a bonding wire. Unlike this example, each of the plurality of connection members 41 to 45 may be a metal plate material. Each of the plurality of connection members 41 to 45 contains gold (Au). Each of the plurality of connection members 41 to 45 may contain copper or aluminum. Note that the plurality of connection members 41 to 45 are omitted from FIGS. 2 and 16.

[0099] 14 , each of the plurality of connection members 41 is conductively joined to the corresponding main surface electrode 213 of the semiconductor element 21 and the wiring portion 621 of the signal substrate 601. As a result, the signal terminal 191 is conductively connected to the main surface electrodes 213 of the plurality of semiconductor elements 21.

[0100] 14 , each of the plurality of connection members 42 is conductively joined to the corresponding main surface electrode 223 of the semiconductor element 22 and the wiring portion 621 of the signal substrate 602. As a result, the signal terminal 192 is conductively connected to the main surface electrodes 223 of the plurality of semiconductor elements 22.

[0101] 14 , each of the plurality of connection members 43 is electrically connected to the corresponding main surface electrode 214 of the semiconductor element 21 and the wiring portion 622 of the signal substrate 601. This allows the signal terminal 193 to be electrically connected to the main surface electrodes 214 of the plurality of semiconductor elements 21. Note that when each semiconductor element 21 does not include either of the two main surface electrodes 214, each of the plurality of connection members 43 is connected to the main surface electrode 212 of the corresponding semiconductor element 21.

[0102] 14 , each of the plurality of connection members 44 is conductively joined to the corresponding main surface electrode 224 of the semiconductor element 22 and the wiring portion 622 of the signal substrate 602. This allows the signal terminal 194 to be conductively connected to the main surface electrodes 224 of the plurality of semiconductor elements 22. Note that when each semiconductor element 22 does not include either of the two main surface electrodes 224, each of the plurality of connection members 44 is joined to the main surface electrode 222 of the corresponding semiconductor element 22.

[0103] 14 , the connection member 45 is electrically connected to the wiring portion 623 of the signal substrate 602 and the conductor portion 122 (partition portion 1222). As a result, the signal terminal 196 is electrically connected to the back surface electrodes 221 of the plurality of semiconductor elements 22 via the conductor portion 122.

[0104] As shown in FIG. 13 and other figures, the conductive member 31 is bonded to the main surface electrodes 222 of the plurality of semiconductor elements 22 and the conductor portion 121 of the support substrate 10. The main surface electrodes 222 of the plurality of semiconductor elements 22 are electrically connected to the conductor portion 121 via the conductive member 31. The conductive member 31 may contain copper. The conductive member 31 is a metal clip. As shown in FIG. 13 and other figures, the conductive member 31 has a main body portion 311 and a plurality of joint portions 312, 313.

[0105] The main body portion 311 forms a main part of the conductive member 31. As shown in FIG. 13 , the main body portion 311 extends in the first direction x. As shown in FIG. 13 , the main body portion 311 straddles the conductor portion 121 and the conductor portion 122. As shown in FIG. 13 , a plurality of through holes 311 a are formed in the main body portion 311. The plurality of through holes 311 a penetrate the main body portion 311 in the thickness direction z. The plurality of through holes 311 a overlap between the conductor portion 121 and the conductor portion 122 in a plan view. This allows the sealing resin 50 to flow smoothly downward in the thickness direction z of the main body portion 311 when forming the sealing resin 50.

[0106] As shown in FIG. 13 , the multiple bonding portions 312 are individually bonded to the principal surface electrodes 222 of the multiple semiconductor elements 22. Each of the multiple bonding portions 312 faces one of the principal surface electrodes 222 of the multiple semiconductor elements 22. In a plan view, each bonding portion 312 extends from the main body portion 311 toward the y2 side in the second direction y. In the illustrated example, the multiple bonding portions 312 are bifurcated from the main body portion 311, but they do not have to be bifurcated. The tip of each bonding portion 312 (the end opposite to the side connected to the main body portion 311) is located below the main body portion 311 in the thickness direction z (on the z1 side in the thickness direction z). The base end of each bonding portion 312 (the end connected to the main body portion 311) is bent in the thickness direction z so as to connect the tip of each bonding portion 312, which is located at a different position in the thickness direction z, to the main body portion 311.

[0107] 13 , the multiple joints 313 are joined to the conductor portion 121. The multiple joints 313 face the conductor portion 121. In a plan view, each joint 313 extends from the main body portion 311 to the y1 side in the second direction y. The tip of each joint 313 (the end opposite to the side connected to the main body portion 311) is located below the main body portion 311 in the thickness direction z (on the z1 side in the thickness direction z). The base end of each joint 313 (the end connected to the main body portion 311) is bent in the thickness direction z so as to connect the tip of each joint 313, which is located at a different position in the thickness direction z, to the main body portion 311.

[0108] 18 , the semiconductor module A10 further includes a conductive bonding layer 33. The conductive bonding layer 33 is interposed between the main surface electrodes 222 of the plurality of semiconductor elements 22 and the plurality of bonding portions 312. The conductive bonding layer 33 conductively bonds the main surface electrodes 222 of the plurality of semiconductor elements 22 to the plurality of bonding portions 312. The conductive bonding layer 33 is, for example, solder. Alternatively, the conductive bonding layer 33 may include a sintered body of metal particles.

[0109] 17 , the semiconductor module A10 further includes a conductive bonding layer 34. The conductive bonding layer 34 is interposed between the conductor portion 121 and the joint portion 313. The conductive bonding layer 34 conductively bonds the conductor portion 121 and the joint portion 313. The conductive bonding layer 34 is, for example, solder. Alternatively, the conductive bonding layer 34 may include a sintered body of metal particles.

[0110] As shown in FIG. 12 , the conductive member 32 is conductively bonded to the principal surface electrodes 212 of the plurality of semiconductor elements 21 and the two conductor portions 123 of the support substrate 10. As a result, the principal surface electrodes 212 of the plurality of semiconductor elements 21 are electrically connected to each of the two conductor portions 123 via the conductive member 32. As described above, the power terminals 16 are respectively bonded to the two conductor portions 123, and therefore the principal surface electrodes 212 of the plurality of semiconductor elements 21 are electrically connected to the power terminals 16. The composition of the conductive member 32 may include copper, for example. The conductive member 32 is a metal clip. As shown in FIG. 12 and other figures, the conductive member 32 includes two main body portions 321, a plurality of joint portions 322, an intermediate portion 323, and a plurality of joint portions 324.

[0111] As shown in FIG. 12 , the two main bodies 321 are spaced apart from each other in the first direction x. The two main bodies 321 extend in the second direction y. As shown in FIG. 20 and other figures, the two main bodies 321 are arranged parallel to the conductor principal surface 121 a of the conductor portion 121, the conductor principal surface 122 a of the conductor portion 122, and the conductor principal surface 123 a of each conductor portion 123. In the thickness direction z, the two main bodies 321 are farther from the main surface metal layer 12 (the conductor portion 121, the conductor portion 122, and the two conductor portions 123) than the main body 311 of the conductive member 31. Each of the two main bodies 321 intersects the conductor portion 122 (the partition portion 1221) in a plan view. That is, each of the two main bodies 321 extends from one edge to the other edge of the partition portion 1221 of the conductor portion 122 in the second direction y in a plan view. Both surfaces of the two main body portions 321 in the thickness direction z are covered with sealing resin 50 .

[0112] The intermediate portion 323 is located between the two main body portions 321 in the first direction x. The intermediate portion 323 extends in the first direction x from each of the two main body portions 321. As can be seen from FIG. 12 , the intermediate portion 323 overlaps some of the multiple joint portions 312 of the conductive member 31 in a planar view. The intermediate portion 323 straddles the two conductor portions 121, 122 in a planar view. The intermediate portion 323 has multiple through holes 323a. The multiple through holes 323a penetrate the intermediate portion 323 in the thickness direction z. The multiple through holes 323a are arranged along the first direction x. Each of the multiple through holes 323a overlaps between the two conductor portions 121, 122 in a planar view.

[0113] 12 and 24 , the multiple bonding portions 322 are individually bonded to the principal surface electrodes 212 of the multiple semiconductor elements 21. Each of the multiple bonding portions 322 faces one of the principal surface electrodes 212 of the multiple semiconductor elements 21. In a plan view, the multiple bonding portions 322 extend in the first direction x from the multiple intermediate portions 323. The tip of each bonding portion 322 (the end opposite to the side connected to the intermediate portion 323) is located below the intermediate portion 323 in the thickness direction z (on the z1 side in the thickness direction z). The base end of each bonding portion 322 (the end connected to the intermediate portion 323) is bent in the thickness direction z so as to connect the tip of each bonding portion 322 and each intermediate portion 323, which are located at different positions in the thickness direction z.

[0114] 12 and 22 , the pair of joints 324 are individually joined to the conductors 123. The joining is, for example, solder joining. Alternatively, joining using a joining material containing a sintered body of metal particles, joining by laser welding, ultrasonic joining, or the like may be used. Each of the pair of joints 324 faces a corresponding one of the two conductors 123. Each of the pair of joints 324 is joined to the corresponding conductor 123 on the y1 side in the second direction y relative to the exposed region 123b.

[0115] 17 , the semiconductor module A10 further includes a conductive bonding layer 35. The conductive bonding layer 35 is interposed between the main surface electrodes 212 of the plurality of semiconductor elements 21 and the plurality of bonding portions 322. The conductive bonding layer 35 conductively bonds the main surface electrodes 212 of the semiconductor elements 21 to the plurality of bonding portions 322. The conductive bonding layer 35 is, for example, solder. Alternatively, the conductive bonding layer 35 may include a sintered body of metal particles.

[0116] The shapes of the two conductive members 31, 32 are not limited to the illustrated example. The conductive member 31 may be any member that electrically connects the conductor portion 121 to each of the main surface electrodes 222 of the plurality of semiconductor elements 22. The conductive member 32 may be any member that electrically connects the two conductor portions 123 to each of the main surface electrodes 212 of the plurality of semiconductor elements 21.

[0117] First Embodiment: Manufacturing Method of Semiconductor Module A10: Next, a manufacturing method of the semiconductor module A10 will be described with reference to FIGS. 26 to 32. FIG. 26 is a flowchart showing an example of a manufacturing method of the semiconductor module A10. FIGS. 27 to 30 and 32 are cross-sectional views showing one step of the manufacturing method of the semiconductor module A10. Each cross section in FIGS. 27 to 30 and 32 corresponds to the cross-sectional position in FIG. 25. FIG. 31 is a bottom view showing one step of the manufacturing method of the semiconductor module A10.

[0118] As shown in FIG. 26, the manufacturing method of the semiconductor module A10 according to this embodiment includes a substrate preparation step S101, a support substrate bonding step S102, an element bonding step S103, a signal substrate bonding step S104, a conductive member bonding step S105, a sleeve bonding step S106, a thermistor bonding step S107, a wire bonding step S108, a molding step S109, and a terminal connection step S110.

[0119] In the substrate preparation step S101, a support substrate 10 including an insulating substrate 11, a main surface metal layer 12, and a back surface metal layer 13 is prepared. In this embodiment, three support substrates 10 are prepared. In the support substrate bonding step S102, as shown in FIG. 27 , each of the multiple support substrates 10 is bonded to a heat dissipation member C10. For example, a bonding layer 109 is used to bond the back surface metal layer 13 of the support substrate 10 to the first surface 71 a of the base 71 of the heat dissipation member C10. In this embodiment, the support substrate bonding step S102 is an example of a "substrate bonding step" as defined in the claims.

[0120] 28 , in the element bonding step S103, for each support substrate 10, a plurality of semiconductor elements 21 are mounted on the conductor portion 121, and a plurality of semiconductor elements 22 are mounted on the conductor portion 122. For example, each of the plurality of semiconductor elements 21 is bonded to the conductor main surface 121 a of the conductor portion 121 by a conductive bonding layer 219, and each of the plurality of semiconductor elements 22 is bonded to the conductor main surface 122 a of the conductor portion 122 (partition portion 1221) by a conductive bonding layer 229.

[0121] In the signal substrate bonding process S104, two signal substrates 601, 602 are bonded to corresponding ones of the two conductor portions 121, 122 for each support substrate 10. In the conductive member bonding process S105, for each support substrate 10, a conductive member 31 is bonded to the plurality of semiconductor elements 22 and the conductor portion 121, and then a conductive member 32 is bonded to the plurality of semiconductor elements 21 and the two conductor portions 123. In the sleeve bonding process S106, for each support substrate 10, a plurality of sleeves 64 are bonded to the wiring layers 62 of the pair of signal substrates 601, 602 with a conductive bonding material (not shown). In the thermistor bonding process S107, a thermistor 23 is mounted on the signal substrate 601 for each support substrate 10. For example, the thermistor 23 is arranged so as to straddle two wiring portions 623, 624 of the signal substrate 601, and a conductive bonding material (not shown) is used to electrically connect the two wiring portions 623, 624 of the signal substrate 601 to the thermistor 23. The signal substrate bonding step S104, the conductive member bonding step S105, the sleeve bonding step S106, and the thermistor bonding step S107 result in the state shown in FIG.

[0122] In the wire bonding step S108, a plurality of connection members 41 to 45 are formed on each support substrate 10. In an example in which the plurality of connection members 41 to 45 are bonding wires, in the wire bonding step S108, the connection members 41 to 45 are formed sequentially by ball bonding using a capillary. Note that the order in which the plurality of connection members 41 to 45 are formed is not limited in any way. Alternatively, the connection members 41 to 45 may be formed sequentially by wedge bonding using a wedge tool.

[0123] In the molding process S109, the sealing resin 50 is formed by, for example, molding. In the molding process S109, a mold M10 shown in Figures 30 and 31 is used. The mold M10 includes an upper mold 81 and a lower mold 82. In the molding process S109, the first surface 71a and the second surface 71b of the base 71 are sandwiched between the upper mold 81 and the lower mold 82, respectively, in the thickness direction z.

[0124] The upper mold 81 presses the outer periphery 712 of the base 71 against the first surface 71a of the base 71 from above in the thickness direction z (the z2 side). As shown in FIG. 30 , the upper mold 81 has a recess 811 formed therein. When the upper mold 81 presses the base 71 from above in the thickness direction z, the recess 811 and the first surface 71a form a resin inlet cavity 801. The resin inlet cavity 801 is a void for forming the sealing resin 50. In the molding process S109, the material for the sealing resin 50 is injected into the resin inlet cavity 801 and cured. The recess 811 also has a plurality of protrusions 812 formed therein. The protrusions 812 include those for forming the main surface opening 56, those for forming the plurality of recesses 571 and 572, and those for exposing the upper surfaces of the plurality of sleeves 64 (for forming the insertion holes 58, described below).

[0125] The lower mold 82 presses the outer periphery 712 of the base 71 against the second surface 71b of the base 71 from below in the thickness direction z (z1 side). As shown in FIG. 30 , a recess 821 is formed in the lower mold 82. When the lower mold 82 presses the base 71 from below in the thickness direction z, the recess 821 and the second surface 71b form a fin avoidance cavity 802. The fin avoidance cavity 802 is a gap for accommodating the multiple heat dissipation fins 751. In other words, the multiple heat dissipation fins 751 are accommodated in the recess 821. A predetermined gap Δg is provided between the bottom surface of the recess 821 and the tips of the multiple heat dissipation fins 751 in the thickness direction z. This gap Δg is not necessary. When the sealing resin 50 is injected into the resin flow cavity 801, pressure is applied to the heat dissipation member C10, and even if the heat dissipation member C10 bends downward in the thickness direction z, the gap Δg prevents the tips of the multiple heat dissipation fins 751 from coming into contact with the lower mold 82.

[0126] 30 and 31 , the lower mold 82 includes an outer periphery support 822 and two intermediate supports 823. The outer periphery support 822 abuts against the outer periphery 712. The two intermediate supports 823 are each disposed between the plurality of recesses 821. The two intermediate supports 823 each abut against an area of ​​the main portion 711 where the plurality of heat dissipation fins 751 are not disposed, i.e., the non-disposition area 73. Therefore, when the sealing resin 50 is injected into the resin flow cavity 801 in the molding process S109, the two intermediate supports 823 overlap between adjacent sealing resin 50 in a plan view. The plurality of recesses 821 are recessed downward in the thickness direction z from the outer periphery support 822 and the two intermediate supports 823.

[0127] The molding process S109 forms the sealing resin 50 shown in FIG. 32 . The sealing resin 50 is formed on the first surface 71 a of the base 71 of the heat dissipation member C10 and covers the bonding layer 109 together with the support substrate 10 (and each component supported by the support substrate 10). The resin rear surface 52 of the sealing resin 50 contacts the first surface 71 a together with the underside of the bonding layer 109. As can be seen from FIGS. 30 to 32 , the sealing resin 50 formed by the molding process S109 has a main surface opening 56 (a plurality of openings 561, 562, 563) and a plurality of recesses 571, 572 formed in the resin main surface 51. As shown in FIG. 32 , the sealing resin 50 formed by the molding process S109 has a plurality of through holes 58 formed in the resin main surface 51. The plurality of through holes 58 individually overlap with a plurality of sleeves 64 in a plan view. Each of the plurality of through holes 58 exposes the upper surface of the corresponding sleeve 64 .

[0128] In the terminal connecting step S110, a plurality of power terminals 15, 16, 17 and a plurality of signal terminals 19 are connected. As shown in Fig. 26 , the terminal connecting step S110 includes a power terminal connecting step S1101 and a signal terminal connecting step S1102. The order of the power terminal connecting step S1101 and the signal terminal connecting step S1102 is not particularly limited.

[0129] In the power terminal connecting step S1101, the power terminal 15 is inserted through each of the two openings 562 and joined to a portion of the conductor principal surface 122a (each exposed region 122b) of the conductor portion 122 that is exposed through the two openings 562. The power terminal 16 is inserted through each of the two openings 563 and joined to a portion of the conductor principal surface 123a (each exposed region 123b) of the conductor portion 123 that is exposed through the two openings 563. The power terminal 17 is inserted through each of the two openings 561 and joined to a portion of the conductor principal surface 121a (each exposed region 121b) of the conductor portion 121 that is exposed through the two openings 561. The power terminals 15, 16, and 17 are joined by, for example, laser welding. Alternatively, ultrasonic bonding or other joining methods may be used. This electrically connects the power terminals 15, 16, and 17 to the multiple semiconductor elements 21 and the multiple semiconductor elements 22.

[0130] In the signal terminal connecting step S1102, each signal terminal 19 is press-fitted into a corresponding one of the plurality of sleeves 64. In the signal terminal connecting step, the plurality of signal terminals 19 are individually inserted into the plurality of insertion holes 58, and each signal terminal 19 is press-fitted into the sleeve 64 exposed from the inserted insertion hole 58. In this way, each signal terminal 19 is electrically connected to any one of the plurality of semiconductor elements 21, the plurality of semiconductor elements 22, and thermistor 23.

[0131] The semiconductor module A10 shown in FIGS. 1 to 25 can be manufactured through the above steps. The manufacturing method of the semiconductor module A10 shown in FIG. 26 is an example and is not limited to this. For example, the timing of the support substrate bonding step S102 is not limited as long as it is performed between the substrate preparation step S101 and the molding step S109. As an example, as shown in FIG. 33, the support substrate bonding step S102 may be performed between the wire bonding step S108 and the molding step S109. Note that in the manufacturing method of the semiconductor module A10, the order of the element bonding step S103, the signal substrate bonding step S104, the conductive member bonding step S105, the sleeve bonding step S106, the thermistor bonding step S107, and the wire bonding step S108 may be changed as appropriate. However, the element bonding step S103 must be performed before both the conductive member bonding step S105 and the wire bonding step S108, and the signal substrate bonding step S104 must be performed before the sleeve bonding step S106.

[0132] First embodiment: power conversion unit U10: Next, a power conversion unit U10 including a semiconductor module A10 will be described with reference to Fig. 34. The power conversion unit U10 includes the semiconductor module A10 and a control board E1.

[0133] As shown in FIG. 34 , the control substrate E1 is provided in common for the three semiconductor packages B10. Alternatively, multiple control substrates E1 may be provided individually for each of the three semiconductor packages B10. As can be seen from FIG. 34 , the signal terminals 19 of the three semiconductor packages B10 are inserted into the control substrate E1. The control substrate E1 is electrically connected to each of the signal terminals 19. The control substrate E1 includes, for example, a control circuit that controls the operation of the semiconductor elements 21 and 22 of the three semiconductor packages B10. In an example in which the semiconductor elements 21 and 22 are MOSFETs or IGBTs, the control substrate E1 is a gate driver. The control substrate E1 faces the upper surface (resin main surface 51) of the sealing resin 50 of each of the three semiconductor packages B10. The control substrate E1 is located on the opposite side of the three semiconductor packages B10 from the base 71 of the heat dissipation member C10. In a plan view, the control substrate E1 overlaps the sealing resin 50 of each of the three semiconductor packages B10. The control substrate E1 is held at a certain distance in the thickness direction z by a plurality of pedestals (not shown). The plurality of pedestals may be provided, for example, on the first surface 71 a of the base 71 of the heat dissipation member C10.

[0134] As shown in FIG. 35 , the control board E1 has a base material 91, main wiring 92, back wiring 93, and internal wiring 94. The base material 91 has a plurality of through holes 911 that penetrate in the thickness direction z. The main wiring 92 is formed on the upper surface of the base material 91 (the surface facing the z1 side in the thickness direction z). The back wiring 93 is formed on the lower surface of the base material 91 (the surface facing the z2 side in the thickness direction z). The internal wiring 94 is disposed on the inner surfaces of the plurality of through holes 911. The internal wiring 94 is connected to the main wiring 92 and the back wiring 93. The main wiring 92 forms a path for mutual conduction between the back wiring 93 and the internal wiring 94 and circuits provided on the control board E1.

[0135] Each signal terminal 19 of the three semiconductor packages B10 is inserted into a corresponding one of the multiple through holes 911 of the control board E1. Fig. 35 shows a state in which the signal terminal 19 of any one of the three semiconductor packages B10 is inserted into the through hole 911 of the base material 91. As can be seen from Fig. 35, all of the signal terminals 19 of the three semiconductor packages B10 are inserted into the through hole 911 of the base material 91.

[0136] As shown in Fig. 35 , each signal terminal 19 includes a tip portion 190. The tip portion 190 is an end portion of each signal terminal 19 that is far from the sealing resin 50. The tip portion 190 has a bulging portion 190A. As shown in Fig. 35 , the bulging portion 190A bulges out in a direction perpendicular to the thickness direction z in the signal terminal 19. In the illustrated example (e.g., Fig. 5 ), the bulging portion 190A of each signal terminal 19 is located higher in the thickness direction z than any of the multiple power terminals 15, 16, and 17.

[0137] As shown in FIG. 35 , the bulging portion 190A of each signal terminal 19 is press-fitted into one of the through-holes 911 of the control board E1. As a result, the internal wiring 94 arranged in one of the through-holes 911 is pressed against the bulging portion 190A of the signal terminal 19 inserted into that through-hole 911. Therefore, each signal terminal 19 is press-fitted into the through-hole 911 in the thickness direction z, thereby providing electrical continuity with the control board E1 (its control circuit). The control board E1 is supported by each signal terminal 19 by press-fitting each signal terminal 19 into a corresponding one of the through-holes 911. As can be seen from this configuration, the control board E1 is attached to the tip portion 190 of each signal terminal 19. Alternatively, each signal terminal 19 may not include a bulging portion 190A. That is, each signal terminal 19 may be a straight pin with no change in thickness. In this case, each signal terminal 19 is inserted into a through-hole 911 and then soldered to the control board E1.

[0138] The configuration of the power conversion unit U10 is not limited to the example shown in FIG. 34 . FIG. 36 shows a power conversion unit U11 according to a modified example. In the power conversion unit U11, the control board E1 includes two circuit boards E11 and E12. The two circuit boards E11 and E12 are spaced apart in the thickness direction z. The control board E1 of the power conversion unit U11 includes a plurality of interconnecting wires 96. The two circuit boards E11 and E12 are electrically connected to each other via the interconnecting wires 96. The configuration of the interconnecting wires 96 is not limited in any way, but may be configured as follows, for example. Each interconnecting wire 96 includes a plurality of connection pins provided on the circuit board E11 and a connector provided on the circuit board E12. In each interconnecting wire 96, the plurality of connection pins are connected to the connector, thereby electrically connecting the circuit board E11 and the circuit board E12. The power conversion unit U11 also includes a plurality of positioning pins 97. Each positioning pin 97 is interposed between the two circuit boards E11 and E12. Each positioning pin 97 determines the position of the circuit board E12 relative to the circuit board E11 and is used to support the circuit board E12.

[0139] First Embodiment: Vehicle F1: Next, a vehicle F1 equipped with a semiconductor module A10 will be described with reference to FIG. 37. The vehicle F1 is, for example, an electric vehicle (EV). In FIG. 37, the semiconductor module A10 is described as being equipped in the vehicle F1 as the power conversion unit U10, but the semiconductor module A10 may also be equipped in the vehicle F1 as the semiconductor module A10. In this case, a control board E1 is separately provided in the vehicle F1.

[0140] As shown in Fig. 37, the vehicle F1 includes an on-board charger F11, a storage battery F12, and a drive system F13. The on-board charger F11 is supplied with power wirelessly from a power supply facility (not shown) installed outdoors. Alternatively, power may be supplied from the power supply facility to the on-board charger F11 via a wired connection. The on-board charger F11 is configured with a step-up DC-DC converter. The voltage of the power supplied to the on-board charger F11 is stepped up by the converter and then supplied to the storage battery F12. The stepped-up voltage is, for example, 600 V.

[0141] The drive system F13 drives the vehicle F1. The drive system F13 includes an inverter F131 and a drive source F132. The power conversion unit U10 (semiconductor module A10) constitutes part of the inverter F131. Power stored in the storage battery F12 is supplied to the inverter F131. The power supplied from the storage battery F12 to the inverter F131 is DC power. Alternatively, unlike the power system shown in FIG. 37 , a step-up DC-DC converter may be further provided between the storage battery F12 and the inverter F131. The inverter F131 converts DC power into AC power. The inverter F131, including the power conversion unit U10 (semiconductor module A10), is electrically connected to the drive source F132. The drive source F132 includes an AC motor and a transmission. When AC power converted by the inverter F131 is supplied to the drive source F132, the AC motor rotates and the rotation is transmitted to the transmission. The transmission appropriately reduces the rotation speed transmitted from the AC motor and then rotates the drive shaft of the vehicle F1. This drives the vehicle F1. To drive the vehicle F1, it is necessary to freely control the rotation speed of the AC motor based on information such as the amount of fluctuation in the accelerator pedal. Therefore, the power conversion unit U10 (semiconductor module A10) in the inverter F131 is necessary to output AC power whose frequency has been appropriately changed to correspond to the required rotation speed of the AC motor.

[0142] The functions and effects of the semiconductor module A10 and the method for manufacturing the semiconductor module A10 are as follows.

[0143] The semiconductor module A10 includes a semiconductor package B10 and a heat dissipation member C10. The heat dissipation member C10 includes a base 71 and multiple heat dissipation fins 751. The base 71 has a first surface 71a to which the semiconductor package B10 is bonded and a second surface 71b to which the multiple heat dissipation fins 751 contact. The second surface 71b has an arrangement region 72 in which the multiple heat dissipation fins 751 are arranged. The arrangement region 72 on the second surface 71b overlaps the multiple semiconductor elements 21 and the multiple semiconductor elements 22 in the thickness direction z. With this configuration, the multiple heat dissipation fins 751 are arranged below the multiple semiconductor elements 21 and the multiple semiconductor elements 22 in the thickness direction z. Therefore, the semiconductor module A10 can efficiently dissipate heat from the multiple semiconductor elements 21 and the multiple semiconductor elements 22. In other words, the semiconductor module A10 can improve heat dissipation performance.

[0144] In the semiconductor module A10, the second surface 71b of the base 71 has a non-placement area 73 where the heat dissipation fins 751 are not arranged. The non-placement area 73 is located at both ends of the placement area 72 in the first direction x, i.e., between the two outermost edges 72a. With this configuration, the second surface 71b of the base 71 has an area where the heat dissipation fins 751 are not arranged (non-placement area 73) between the areas where the heat dissipation fins 751 are arranged (placement areas 72). Therefore, the semiconductor module A10 can reduce the number of heat dissipation fins 751 compared to when the heat dissipation fins 751 are evenly arranged. In other words, the semiconductor module A10 can reduce the cost of the heat dissipation member C10. In particular, the semiconductor module A10 reduces the number of heat dissipation fins 751, which contribute relatively little to heat dissipation. The semiconductor module A10 includes multiple semiconductor packages B10, each of which includes multiple semiconductor elements 21 and 22 and a sealing resin 50. The non-placement area 73 includes an intervening portion 731 that overlaps with a gap between the plurality of sealing resins 50. According to this configuration, in the heat dissipation member C10, the plurality of heat dissipation fins 751 are not disposed between the plurality of semiconductor packages B10 that make a relatively small contribution to heat dissipation (have a relatively small amount of heat storage) below each semiconductor package B10 in the thickness direction z. This allows the semiconductor module A10 to have a reduced number of heat dissipation fins 751. This allows the semiconductor module A10 to reduce the cost of the heat dissipation member C10 while ensuring heat dissipation performance.

[0145] In the manufacturing method of the semiconductor module A10, a lower mold 82 is used in the molding step S109. The lower mold 82 includes an intermediate support 823. The intermediate support 823 abuts against the non-placement region 73 of the second surface 71b. This configuration allows the heat dissipation member C10 to be stably supported in the molding step S109, compared to a configuration in which the lower mold 82 does not have the intermediate support 823. Furthermore, the intermediate support 823 can reduce downward deflection of the heat dissipation member C10 in the thickness direction z due to the load of each semiconductor package B10, etc. This allows the sealing resin 50 of the semiconductor module A10 to be properly formed.

[0146] The manufacturing method for the semiconductor module A10 includes a support substrate bonding step S102, an element bonding step S103, and a molding step S109. The molding step S109 is performed after the support substrate bonding step S102 and the element bonding step S103 are each completed. With this configuration, the support substrate bonding step S102 is completed when the molding step S109 is performed. Therefore, the semiconductor module A10 being manufactured is not placed in an environment with a temperature higher than the temperature at which the sealing resin 50 is formed in steps subsequent to the molding step S109. Therefore, with this manufacturing method for the semiconductor module A10, the shape of the sealing resin 50 can be more effectively maintained in the semiconductor module A10 in which the support substrate 10 is bonded to the heat dissipation member C10.

[0147] The semiconductor module A10 includes a semiconductor element 21, an insulating substrate 11, a conductor portion 123, and a sealing resin 50. The conductor portion 123 has a conductor principal surface 123a and is electrically connected to the semiconductor element 21. The insulating substrate 11 is located inward from the periphery of the sealing resin 50 in the thickness direction z. The sealing resin 50 has a resin principal surface 51 and a principal surface opening 56 formed in the resin principal surface 51. The principal surface opening 56 includes an opening 563 that exposes a portion of the conductor principal surface 123a from the resin principal surface 51. With this configuration, the conductor principal surface 123a (the conductor portion 123) is exposed from the resin principal surface 51 of the sealing resin 50 through the opening 563, making it possible to electrically connect a power terminal 16 to the conductor portion 123 after the sealing resin 50 is formed. In other words, the semiconductor module A10 allows for the placement of a power terminal for handling power supply voltage after the sealing resin 50 is formed.

[0148] The manufacturing method of the semiconductor module A10 includes a support substrate bonding process S102 in which a support substrate 10 including an insulating substrate 11 and a conductor portion 123 is bonded to a heat dissipation member C10, and a molding process S109 in which a sealing resin 50 covering the support substrate 10 is formed on the heat dissipation member C10. The manufacturing method of the semiconductor module A10 also includes an element bonding process S103 in which a semiconductor element 21 is mounted on the support substrate 10 before the molding process S109. The insulating substrate 11 has a substrate main surface 11a that faces the semiconductor element 21 in the thickness direction of the semiconductor element 21 (thickness direction z). The sealing resin 50 has a resin main surface 51 that faces the same direction as the substrate main surface 11a in the thickness direction z. The conductor portion 123 has a conductor main surface 123a that faces the same direction as the substrate main surface 11a in the thickness direction z. In the molding step S109, a main surface opening 56 that exposes a portion of the conductor main surface 123a is formed in the resin main surface 51. With this configuration, the terminal connection step S110 (e.g., a power terminal connection step S1101 in which the power terminal 16 is connected to a portion of the conductor main surface 123a through the main surface opening 56, thereby connecting the power terminal 16 that is electrically connected to the conductor portion 123) can be performed after the molding step S109. In other words, the manufacturing method for the semiconductor module A10 allows the power terminal that handles the power supply voltage to be arranged after the sealing resin 50 is formed.

[0149] In the semiconductor module A10, the opening 563 is rectangular in shape with its longer side extending in the second direction y as viewed in the thickness direction z. Furthermore, in the semiconductor module A10, the power terminal 16 includes a joint 161 and a suspension 162. The joint 161 is a portion joined to the exposed region 123b (the region of the conductor principal surface 123a exposed through the opening 563). The suspension 162 is a portion extending from the joint 161 as viewed in the thickness direction z. The suspension 162 extends from the joint 161 in the first direction x as viewed in the thickness direction z. In this configuration, the opening 563 is rectangular in shape with its shorter side extending in the direction (first direction x) in which the suspension 162 extends from the joint 161. In other words, the longer side of the opening 563 is in the direction (second direction y) perpendicular to the direction (first direction x) in which the suspension 162 extends from the joint 161. This configuration allows the size (width) of the power terminal 16 to be increased in the direction perpendicular to the direction of current flow, which means that the cross-sectional area of ​​the power terminal 16 can be increased relative to the flow of current, thereby reducing the wiring resistance of the power terminal 16.

[0150] The semiconductor module A10 includes an insulating substrate 11, conductor portions 121 and 123, and a conductive member 32. The conductor portions 121 and 123 are bonded to the main surface 11a of the insulating substrate 11. The semiconductor element 21 is mounted on the conductor portion 121. The conductor portion 123 is spaced from the conductor portion 121. The conductive member 32 is bonded to a main surface electrode 212 of the semiconductor element 21. The conductive member 32 is electrically connected to the conductor portion 123 and supported by the conductor portion 123. With this configuration, heat generated by the semiconductor element 21 is transferred to the conductive member 32. Furthermore, the conductive member 32 generates heat due to parasitic resistance (wiring resistance) when a current flows through it. The heat transferred to or generated by the conductive member 32 is then transferred to the conductor portion 123 and dissipated to the outside of the semiconductor module A10 via the insulating substrate 11. Therefore, the semiconductor module A10 can dissipate heat that may accumulate in the conductive member 32 more effectively than the semiconductor module described in Patent Document 1 by dissipating heat through the conductor portion 123. In other words, the semiconductor module A10 can improve heat dissipation. In particular, in the semiconductor module A10, some of the multiple heat dissipation fins 751 are arranged below each conductor portion 123 in the thickness direction z. This can improve the heat dissipation of each conductor portion 123. In other words, the semiconductor module A10 can further improve the heat dissipation of heat that may accumulate in the conductive member 32.

[0151] In the semiconductor module A10, the conductive member 32 forms a path through which a main current flows. The main current refers to a current corresponding to the power before or after conversion by the switching operations of the multiple semiconductor elements 21 and the multiple semiconductor elements 22. In this configuration, a large current flows through the conductive member 32, which can lead to increased heat generation due to the parasitic resistance (wiring resistance) of the conductive member 32. This means that the amount of heat that can accumulate in the conductive member 32 can be large. Therefore, improving the heat dissipation performance of the conductive member 32 is important for improving the heat dissipation performance of the semiconductor module A10. In particular, the main body 321 of the conductive member 32 is strip-shaped extending in the second direction y and has a small cross-sectional area relative to the main current. Therefore, the parasitic resistance of the main body 321 is large, and self-heat generation in the main body 321 can also be large. In other words, improving the heat dissipation performance of the conductive member 32 is particularly important in the semiconductor module A10. Therefore, in the semiconductor module A10, as described above, the heat dissipation properties of the conductive member 32 are improved by connecting the conductive member 32 to the conductor portion 123. In other words, the semiconductor module A10 has a preferable structure for improving the heat dissipation properties of the semiconductor module A10.

[0152] In the semiconductor module A10, the conductor portion 121 has a conductor principal surface 121a. Furthermore, in the semiconductor module A10, the principal surface opening 56 includes an opening 561 that exposes a portion of the conductor principal surface 121a from the resin principal surface 51. With this configuration, the conductor principal surface 121a (conductor portion 121) is exposed from the resin principal surface 51 of the sealing resin 50 through the opening 561, making it possible to electrically connect the power terminal 17 to the conductor portion 121 after the sealing resin 50 is formed. In other words, in the semiconductor module A10, it is possible to arrange a power terminal that handles power supply voltage after the sealing resin 50 is formed.

[0153] In the semiconductor module A10, the opening 561 is rectangular with its longer side extending in the first direction x as viewed in the thickness direction z. Furthermore, in the semiconductor module A10, the power terminal 17 includes a joint 171 and a suspension 172. The joint 171 is a portion joined to the exposed region 121b (a region of the conductor principal surface 121a exposed through the opening 561). The suspension 172 is a portion extending from the joint 171 as viewed in the thickness direction z. The end of the suspension 172 connected to the joint 171 extends from the joint 171 in the second direction y as viewed in the thickness direction z. In this configuration, the opening 561 is rectangular with its shorter side extending in the direction in which the suspension 172 extends from the joint 171 (the second direction y). That is, the long side of the opening 561 is in a direction (first direction x) perpendicular to the direction (second direction y) in which the suspension portion 172 extends from the joint portion 171. With this configuration, the size (width) of the power terminal 17 can be increased in the direction perpendicular to the direction of current flow. In other words, the cross-sectional area of ​​the power terminal 17 can be increased relative to the flowing current, thereby reducing the wiring resistance of the power terminal 17.

[0154] In the semiconductor module A10, the semiconductor element 22 is mounted on the conductor portion 122. The conductor portion 122 is electrically connected to the semiconductor element 22 (rear electrode 221). In the semiconductor module A10, the conductor portion 122 has a conductor principal surface 122a. Furthermore, in the semiconductor module A10, the principal surface opening 56 includes an opening 562 that exposes a portion of the conductor principal surface 122a from the resin principal surface 51. With this configuration, the conductor principal surface 122a (conductor portion 122) is exposed from the resin principal surface 51 of the sealing resin 50 through the opening 562, making it possible to electrically connect the power terminal 15 to the conductor portion 122 after the sealing resin 50 is formed. In other words, in the semiconductor module A10, it is possible to arrange a power terminal that handles power supply voltage after the sealing resin 50 is formed.

[0155] In the semiconductor module A10, the opening 562 is rectangular with a longer side extending in the second direction y as viewed in the thickness direction z. Also, in the semiconductor module A10, the power terminal 15 includes a joint 151 and a suspension 152. The joint 151 is a portion joined to the exposed region 122b (a region of the conductor principal surface 122a exposed through the opening 562). The suspension 152 is a portion extending from the joint 151 as viewed in the thickness direction z. An end of the suspension 152 connected to the joint 151 extends from the joint 151 in the first direction x as viewed in the thickness direction z. In this configuration, the opening 562 is rectangular with a shorter side extending in the direction in which the suspension 152 extends from the joint 151 (first direction x). That is, the long side of the opening 562 is in a direction (second direction y) perpendicular to the direction (first direction x) in which the suspension portion 152 extends from the joint portion 151. With this configuration, the size (width) of the power terminal 15 can be increased in the direction perpendicular to the direction of current flow. In other words, the cross-sectional area of ​​the power terminal 15 can be increased relative to the flowing current, thereby reducing the wiring resistance of the power terminal 15.

[0156] The semiconductor module A10 includes two conductor portions 123. In the semiconductor module A10, the main surface opening 56 includes two openings 563, which expose the two conductor portions 123 from the resin main surface 51. Furthermore, in the semiconductor module A10, the main surface opening 56 includes two openings 562. The two openings 562 are aligned in the first direction x between the two openings 563. Unlike this configuration, it is possible to connect the two openings 563 to form a single opening. However, if the two openings 563 are connected to form a single opening, regions on both sides of the single opening in the second direction y may be created where it is difficult to properly form the sealing resin 50. In contrast, if two openings 563 are provided, a flow path for the sealing resin 50 can be secured between the two openings 563. In other words, the semiconductor module A10 has a structure that is preferable for properly forming the sealing resin 50.

[0157] The semiconductor module A10 includes a heat dissipation member C10. With this configuration, heat transferred from either the plurality of semiconductor elements 21 or the plurality of semiconductor elements 22 to the main surface metal layer 12 (any of the conductor portion 121, the conductor portion 122, and the conductor portion 123) of the support substrate 10 is transferred to the heat dissipation member C10 via the support substrate 10. In other words, the semiconductor module A10 can improve the heat dissipation properties of the main surface metal layer 12 (the conductor portion 121, the conductor portion 122, and the conductor portion 123).

[0158] In the semiconductor module A10, the resin main surface 51 has a recess 571 recessed downward in the thickness direction z from the resin main surface 51. In a plan view, the recess 571 is located between the two openings 562 and 563 and the multiple signal terminals 192, 194, and 196. This configuration increases the creepage distance along the resin main surface 51 between the signal terminals 192, 194, and 196 and the power terminals 15 inserted through the two openings 562 and the power terminals 16 inserted through the two openings 563. In other words, the semiconductor module A10 can reduce unintended short circuits between the multiple signal terminals 192, 194, and 196 and the two power terminals 15 and 16.

[0159] In the semiconductor module A10, the resin main surface 51 has two recesses 572 that are recessed downward in the thickness direction z from the resin main surface 51. Each of the two recesses 572 is located between the corresponding opening 561 and the multiple signal terminals 191, 193, and 197. This configuration increases the creepage distance along the resin main surface 51 between the signal terminals 191, 193, and 197 and the power terminals 17 inserted through the two openings 561. In other words, the semiconductor module A10 can reduce unintended short circuits between the multiple signal terminals 191, 193, and 197 and the power terminals 17.

[0160] In the terminal connection step S110 of the manufacturing method for the semiconductor module A10, the power terminals 15, 16, and 17 are joined to the corresponding conductor portions 121, 122, and 123, for example, by laser welding. Alternatively, the power terminals 15, 16, and 17 may be joined to the corresponding conductor portions 121, 122, and 123 by, for example, soldering. However, in the manufacturing method for the semiconductor module A10, the terminal connection step S110 is performed after the molding step S109. Therefore, soldering may result in an environment with a temperature higher than that at which the encapsulating resin 50 is formed. On the other hand, when the power terminals 15, 16, and 17 are joined by laser welding, heating is localized and short, minimizing the thermal impact on the surrounding area. Therefore, thermal deformation of the encapsulating resin 50 can be suppressed. In other words, the manufacturing method for the semiconductor module A10 allows the encapsulating resin 50 to maintain its shape better.

[0161] Other embodiments and modifications of the semiconductor module A10 of the present disclosure will be described below. The configurations of the components in the embodiments and modifications can be combined with each other to the extent that no technical contradictions arise.

[0162] 38 shows a semiconductor module A11 according to a first modification of the first embodiment. The semiconductor module A11 differs from the semiconductor module A10 in the following respects: the arrangement of the plurality of heat dissipation fins 751 is different.

[0163] In the semiconductor module A11, the heat dissipation fins 751 are arranged in a square lattice pattern of a two-dimensional Bravais lattice in plan view. The square lattice pattern of the two-dimensional Bravais lattice is such that, with a certain heat dissipation fin 751 as a reference, the other heat dissipation fins 751 are arranged as follows: As shown in Figure 38, the magnitudes of two vectors a1 and a2 are equal, and the angle α formed by the two vectors a1 and a2 is 90°.

[0164] As can be seen from the semiconductor module A11, in the semiconductor module of the present disclosure, the arrangement of the multiple heat dissipation fins 751 in a planar view is not limited in any way, and as described above, may be a square lattice, rectangular lattice, diagonal lattice, or hexagonal lattice among the two-dimensional Bravais lattice.

[0165] 39 shows a semiconductor module A12 according to a second modification of the first embodiment. The semiconductor module A12 differs from the semiconductor module A11 in the following respect: the arrangement density of the plurality of heat dissipation fins 751 in the arrangement region 72 is partially different.

[0166] In the semiconductor module A12, the placement region 72 includes a portion where the plurality of heat dissipation fins 751 are sparsely arranged and a portion where the plurality of heat dissipation fins 751 are densely arranged. In the illustrated example, the plurality of heat dissipation fins 751 are densely arranged in an area that overlaps the plurality of semiconductor elements 21 and the plurality of semiconductor elements 22 in a plan view and in an area that overlaps two conductor portions 123 in a plan view. Thus, in the semiconductor module of the present disclosure, the area where the plurality of heat dissipation fins 751 are arranged at a predetermined arrangement density or higher is the placement region 72.

[0167] In the semiconductor module A12, the arrangement region 72 includes a portion where the plurality of heat dissipation fins 751 are sparsely arranged and a portion where the plurality of heat dissipation fins 751 are densely arranged. With this configuration, by densely arranging the plurality of heat dissipation fins 751 in an area that contributes greatly to heat dissipation, it is possible to further improve heat dissipation performance.

[0168] Furthermore, as can be seen from the semiconductor module A12 shown in Figure 39, the arrangement of the multiple heat dissipation fins 751 in a planar view is not limited to being arranged according to a single rule, but also includes being arranged according to multiple rules (in Figure 39, a square lattice shape and a face-centered rectangular lattice shape of a two-dimensional Bravais lattice).

[0169] 40 shows a semiconductor module A13 according to a third modification of the first embodiment. The semiconductor module A13 differs from the semiconductor module A10 in the following respect: the base 71 has a plurality of recesses 71c.

[0170] The plurality of recesses 71c are recessed from the second surface 71b in the thickness direction z. Some of the plurality of recesses 71c are arranged in the non-arrangement region 73. Some of the plurality of recesses 71c are arranged in the outer periphery 712. The plurality of recesses 71c correspond to regions pressed by the lower mold 82 when the sealing resin 50 is formed (molding process S109). In other words, the plurality of recesses 71c are formed by being pressed by the lower mold 82.

[0171] As can be seen from the semiconductor module A13, in the semiconductor module of the present disclosure, the base 71 may have a pressing mark (e.g., a depression 71c) formed by the lower mold 82. Note that, although the example shown in Fig. 40 shows an example in which the depression 71c is formed as the pressing mark, the pressing mark is not limited to the depression 71c as long as it is a mark indicating that the lower mold 82 has been in contact. For example, the pressing mark may be discoloration or a scratch.

[0172] The semiconductor modules A11 to A13 according to the modifications of the first embodiment also achieve the same effects as the semiconductor module A10.

[0173] 41 shows a semiconductor module A20 according to a second embodiment. The semiconductor module A20 differs from the semiconductor module A10 in the following respect: each intervening portion 731 in the non-placement area 73 is divided into multiple areas.

[0174] In the semiconductor module A20, the placement region 72 includes a plurality of main portions 721 and a plurality of connecting portions 722. In a plan view, the plurality of main portions 721 individually overlap the sealing resin 50 of the plurality of semiconductor packages B10. The connecting portions 722 connect adjacent main portions 721 in the first direction x. The connecting portions 722 divide each intervening portion 731 into a plurality of regions spaced apart in the second direction y. In the illustrated example, one of the two intervening portions 731 (the intervening portion 731 on the x2 side in the first direction x) is divided into four regions, and the other of the two intervening portions 731 (the intervening portion 731 on the x1 side in the first direction x) is divided into three regions. Note that the number of regions into which the two intervening portions 731 are divided may be the same.

[0175] Like the semiconductor module A10, the semiconductor module A20 can improve heat dissipation by using the placement area 72. Also, like the semiconductor module A10, the semiconductor module A20 can reduce the cost of the heat dissipation member C10 while ensuring heat dissipation by using the placement area 72. In addition, the semiconductor module A20 has a common configuration with the semiconductor module A10, and therefore achieves the same effects as the semiconductor module A10.

[0176] 42 shows a semiconductor module A30 according to a third embodiment. The semiconductor module A30 differs from the semiconductor module A10 in the following respect: the non-placement area 73 overlaps the sealing resin 50 in plan view and is surrounded by the placement area 72 in plan view.

[0177] In semiconductor module A30, non-placement area 73 includes multiple encapsulation sections 732. In plan view, each of the multiple encapsulation sections 732 individually overlaps with a multiple number of sealing resins 50. In plan view, each encapsulation section 732 is surrounded by multiple heat dissipation fins 751. That is, each encapsulation section 732 is surrounded by placement area 72. There are no limitations on the position of each encapsulation section 732 in plan view, but it is preferable that each encapsulation section 732 be located in an area of ​​each semiconductor package B10 that contributes little to heat dissipation (an area that accumulates little heat). In the example shown in FIG. 42 , the encapsulation sections 732 are located between multiple semiconductor elements 21 and multiple semiconductor elements 22.

[0178] In the manufacturing method of the semiconductor module A30, a lower mold 82 (mold M10) shown in Fig. 43 can be used in the molding step S109. That is, in the lower mold 82 shown in Fig. 43, each recess 821 overlaps with each sealing resin 50 in a plan view. Also, in the lower mold 82 shown in Fig. 43, the multiple intermediate supports 823 include those that overlap with the gaps in each sealing resin 50 and those that are surrounded by each recess 821.

[0179] Like the semiconductor module A10, the semiconductor module A30 can improve heat dissipation by using the placement area 72. Also, like the semiconductor module A10, the semiconductor module A30 can reduce the cost of the heat dissipation member C10 while ensuring heat dissipation by using the placement area 72. In addition, the semiconductor module A30 has a common configuration with the other semiconductor modules A10, A20, etc., and therefore achieves the same effects as the semiconductor modules A10, A20, etc.

[0180] In the semiconductor module A30, the area of ​​the non-placement region 73 is larger than that of the semiconductor module A10. With this configuration, the planar area of ​​the intermediate support 823 of the lower mold 82 can be increased in the molding step S109, making it possible to more stably support the heat dissipation member C10. Therefore, the sealing resin 50 can be formed more appropriately in the semiconductor module A30 than in the semiconductor module A10.

[0181] 44 shows a semiconductor module A31 according to a first modification of the third embodiment. The semiconductor module A31 differs from the semiconductor module A30 in the following respect: the non-placement area 73 includes two inner portions 732 for each of the plurality of semiconductor packages B10.

[0182] In semiconductor module A31, two inner container portions 732 for each semiconductor package B10 are each surrounded by multiple heat dissipation fins 751. In the illustrated example, there are two inner container portions 732 for each semiconductor package B10, but there may be three or more. In the illustrated example, the dimensions of the two inner container portions 732 for each semiconductor package B10 along the first direction x are the same, but these dimensions may be different. In the illustrated example, the inner container portions 732 have the same shape in a plan view, but these dimensions may be different.

[0183] 45 shows a semiconductor module A32 according to a second modification of the third embodiment. The semiconductor module A32 differs from the semiconductor module A31 in the following respect: the shapes of the two inner envelope portions 732 for each semiconductor package B10 are different.

[0184] In semiconductor module A32, non-placement area 73 includes two inner packet parts 732A, 732B for each semiconductor package B10. Inner packet part 732A has a rectangular ring shape in plan view, and inner packet part 732B is located inward of inner packet part 732A.

[0185] The semiconductor modules A31 and A32 according to the respective modifications of the third embodiment also achieve the same effects as the semiconductor module A30. Furthermore, as can be seen from the respective semiconductor modules A30 to A32, the ranges and shapes of the placement area 72 and the non-placement area 73 are not limited in any way and can be changed to preferred positions taking into consideration the heat-generating locations of each semiconductor package B10 and the locations that contribute little to heat dissipation.

[0186] 46 shows a semiconductor module A40 according to a fourth embodiment. The semiconductor module A40 differs from the semiconductor module A10 in the following respect: multiple support substrates 10 (and multiple semiconductor elements 21, 22, etc. mounted on each support substrate 10) are covered with a single sealing resin 50.

[0187] In the semiconductor module A40, a plurality of semiconductor elements 21, 22, etc. are mounted on each of a plurality of support substrates 10, and the above-mentioned half-bridge circuit is configured on each of the plurality of support substrates 10. In other words, in the semiconductor module A40, a plurality of half-bridge circuits are covered with a single sealing resin 50. In the illustrated example, three support substrates 10 are provided, but the number of support substrates 10 may be one. In this case, a plurality of main surface metal layers 12 are bonded to the substrate main surface 11a of the common insulating substrate 11, and three half-bridge circuits are formed on each main surface metal layer 12.

[0188] Like the semiconductor module A10, the semiconductor module A40 can improve heat dissipation by using the placement area 72. Also, like the semiconductor module A10, the semiconductor module A40 can reduce the cost of the heat dissipation member C10 while ensuring heat dissipation by using the placement area 72. In addition, the semiconductor module A40 has a common configuration with the other semiconductor modules A10, A20, A30, etc., and therefore achieves the same effects as the semiconductor modules A10, A20, A30, etc.

[0189] As can be seen from the semiconductor module A40, the semiconductor module of the present disclosure is not limited to a configuration in which multiple half-bridge circuits (such as multiple support substrates 10 and multiple semiconductor elements 21, 22 arranged on each of the multiple support substrates 10) are individually covered with the sealing resin 50, but also includes a configuration in which multiple half-bridge circuits are covered with a single sealing resin 50. However, considering the difference in thermal expansion coefficient between the heat dissipation member C10 and the sealing resin 50, a configuration in which multiple half-bridge circuits are individually covered with multiple sealing resins 50 is preferable.

[0190] 47 shows a semiconductor module A50 according to a fifth embodiment. The semiconductor module A50 differs from the semiconductor module A10 in the following respect: one semiconductor package B10 is bonded to a heat dissipation member C10.

[0191] 47 , in the semiconductor module A50, the non-placement area 73 overlaps the sealing resin 50 in a plan view. The non-placement area 73 of the semiconductor module A50 is configured similarly to the inner encapsulation portion 732 of the semiconductor module A30. In the semiconductor module A50, the non-placement area 73 is located between the two outermost edges 72 a and between the two outermost edges 72 b.

[0192] Like the semiconductor module A10, the semiconductor module A50 can improve heat dissipation by using the placement area 72. Also, like the semiconductor module A10, the semiconductor module A50 can reduce the cost of the heat dissipation member C10 while ensuring heat dissipation by using the placement area 72. In addition, the semiconductor module A50 has a common configuration with the other semiconductor modules A10, A20, A30, A40, etc., and therefore achieves the same effects as the semiconductor modules A10, A20, A30, A40, etc.

[0193] 48 and 49 show a semiconductor module A51 according to a modification of the fifth embodiment. The semiconductor module A51 differs from the semiconductor module A10 in the following respect: four semiconductor packages B10 are bonded to one heat dissipation member C10.

[0194] In the illustrated example, the four semiconductor packages B10 are arranged in two rows and two columns in the first direction x and the second direction y in a plan view. In the illustrated example, the semiconductor packages B10 on the y1 side in the second direction y are bonded to the heat dissipation member C10 in a position inverted from the semiconductor packages B10 on the y2 side in the second direction y in a plan view. In this configuration, the power terminals 17 of the semiconductor packages B10 are arranged close to each other. Alternatively, the semiconductor packages B10 on the y1 side in the second direction y and the semiconductor packages B10 on the y2 side in the second direction y may be arranged so that the power terminals 15, 16 are close to each other. Alternatively, the semiconductor packages B10 on the y1 side in the second direction y and the semiconductor packages B10 on the y2 side in the second direction y do not need to be inverted from each other.

[0195] In the semiconductor module A51, an intervening portion 731 is arranged between two semiconductor packages B10 (two sealing resins 50) aligned in the first direction x and between two semiconductor packages B10 (two sealing resins 50) aligned in the second direction y. In the non-alignment region 73 of the semiconductor module A51, as shown in FIG. 49 , the intervening portions 731 extending in the first direction x and the intervening portions 731 extending in the second direction y intersect with each other.

[0196] The semiconductor module A51 according to the modification of the fifth embodiment also achieves the same effects as the semiconductor module A50. Furthermore, as can be seen from the semiconductor modules A50 and A51, in the semiconductor module of the present disclosure, the number of semiconductor packages B10 per one heat dissipation member C10 is not limited in any way.

[0197] In a configuration different from the first to fifth embodiments (including their variations), the heat dissipation fins 751 of the heat dissipation member C10 may be plate fins or corrugated fins instead of pin fins. FIG. 50 shows a semiconductor module in which the heat dissipation fins 751 are plate fins. In the example shown in FIG. 50 , each of the heat dissipation fins 751 extends in a first direction x in a planar view. Unlike this example, each of the heat dissipation fins 751 may extend in a second direction y in a planar view. Furthermore, the extending direction may be different for each semiconductor package B10.

[0198] In the first to fifth embodiments (including their modified examples), the configuration of each semiconductor package B10 is not limited to the above example. Other configuration examples of each semiconductor package in the semiconductor module of the present disclosure (each semiconductor package B11 to B15) will be described below.

[0199] 51 and 52 show a semiconductor package B11 according to a first modified example. The semiconductor package B11 differs from the semiconductor package B10 in the following respects. First, the resin main surface 51 of the sealing resin 50 has a protrusion 573 instead of a recess 571. Second, the resin main surface 51 of the sealing resin 50 has two protrusions 574 instead of two recesses 572.

[0200] The protrusion 573 and the two protrusions 574 each protrude upward in the thickness direction z from the resin main surface 51. In plan view, the protrusion 573 and the two protrusions 574 are each interposed between the main surface opening 56 and one of the multiple signal terminals 19. Like the recess 571, the protrusion 573 is located between the two openings 562 and 563 and the multiple signal terminals 192, 194, and 196 in plan view. Like one of the two recesses 572, one of the two protrusions 574 is located between one of the two openings 561 and the multiple signal terminals 191, 193, and 197. Like the other of the two recesses 572, the other of the two protrusions 574 is located between the other of the two openings 561 and the multiple signal terminals 191, 193, and 197.

[0201] In each semiconductor package B11, a protrusion 573, instead of the recess 571, can increase the creeping distance along the resin main surface 51 between the multiple signal terminals 192, 194, 196 and the power terminal 15 inserted into the two openings 562 and the power terminal 16 inserted into the two openings 563. Also, in each semiconductor package B11, a protrusion 574, instead of the recess 572, can increase the creeping distance along the resin main surface 51 between the multiple signal terminals 191, 193, 197 and the power terminal 17 inserted into the two openings 561.

[0202] 53 shows a semiconductor package B12 according to a second modified example. The semiconductor package B12 differs from the semiconductor package B10 in the following respects. First, the sealing resin 50 has a recess 521 recessed in the thickness direction z from the resin rear surface 52. Second, the base 71 (heat dissipation member C10) has a protrusion 715 protruding in the thickness direction z from the first surface 71 a.

[0203] The protrusions 715 are fitted into the recesses 521. At least one recess 521 and one protrusion 715 are arranged around the periphery of the support substrate 10 in a plan view. The number of recesses 521 and protrusions 715 is not limited in any way. In the semiconductor package B12, the sealing resin 50 exhibits an anchoring effect with respect to the base 71 (heat dissipation member C10). This makes it possible to prevent the sealing resin 50 from peeling off from the first surface 71 a.

[0204] 54 shows a semiconductor package B13 according to a third modified example. The semiconductor package B13 differs from the semiconductor package B12 in the following respects. First, the base 71 (heat dissipation member C10) has a recess 716 recessed from the first surface 71a in the thickness direction z, instead of the protrusion 715. Second, the sealing resin 50 has a protrusion 522 protruding from the resin back surface 52 in the thickness direction z, instead of the recess 521.

[0205] The protrusion 522 is fitted into the recess 716. In the semiconductor package B13, as in the semiconductor package B12, the sealing resin 50 exhibits an anchoring effect with respect to the base 71 (heat dissipation member C10), thereby preventing the sealing resin 50 from peeling off from the first surface 71 a.

[0206] 55 shows a semiconductor package B14 according to a fourth modification. The semiconductor package B14 differs from the semiconductor package B10 in the following respects: the number and positions of the multiple signal terminals 19 are different. Note that in the semiconductor package B14, the arrangement, number, size, shape, etc. of each component of the semiconductor package can be changed as appropriate depending on the arrangement of the multiple signal terminals 19.

[0207] 55 , in the semiconductor package B14, the multiple signal terminals 19 are arranged at the end closer to the power terminal 17 in the second direction y, but are not arranged at the end closer to the two power terminals 15, 16. Unlike this example, the multiple signal terminals 19 may not be arranged at the end closer to the power terminal 17 in the second direction y, but may be arranged at the end closer to the two power terminals 15, 16. In the illustrated example, the semiconductor package B14 includes four signal terminals 19. The four signal terminals 19 are, for example, signal terminals 191 to 194, but are not limited to this combination.

[0208] 56 to 58 show a semiconductor package B15 according to a fifth modification. The semiconductor package B15 differs from the semiconductor package B10 in the configuration of the multiple power terminals 15, 16, and 17. The semiconductor package B15 includes one power terminal 15, two power terminals 16, and two power terminals 17. These power terminals 15, 16, and 17 are formed from blocks of metal (e.g., copper).

[0209] The power terminal 15 is joined to the conductor portion 122 inside the sealing resin 50. The power terminal 15 is exposed from the resin main surface 51 of the sealing resin 50. In a plan view, the power terminal 15 is surrounded by the periphery of the sealing resin 50 and is located inward from the periphery of the resin main surface 51. The power terminal 15 has a connection surface 155 exposed from the sealing resin 50. The connection surface 155 faces the same side as the first surface 71a of the base 71 of the heat dissipation member C10 in the thickness direction z. The power terminal 15 is exposed from an opening 562 in the sealing resin 50.

[0210] The two power terminals 16 are individually bonded to two conductor portions 123 inside the sealing resin 50. Each of the two power terminals 16 is exposed from the resin main surface 51 of the sealing resin 50. In a plan view, each of the two power terminals 16 is surrounded by the periphery of the sealing resin 50 and is located inward from the periphery of the resin main surface 51. Each of the two power terminals 16 has a connection surface 165 exposed from the sealing resin 50. The connection surface 165 faces the same side as the first surface 71a of the base 71 of the heat dissipation member C10 in the thickness direction z. The connection surfaces 165 of the two power terminals 16 are individually exposed from two openings 563 in the sealing resin 50. In the example shown in FIG. 58 , the joint portion 324 of the conductive member 32 is bonded to the corresponding power terminal 16 via a conductive bonding layer 39. Unlike this example, the joint portion 324 of the conductive member 32 may be joined to the corresponding conductor portion 123 .

[0211] Each of the two power terminals 17 is joined to the conductor portion 121 inside the sealing resin 50. Each of the two power terminals 17 is exposed from the resin main surface 51 of the sealing resin 50. In a plan view, each of the two power terminals 17 is surrounded by the periphery of the sealing resin 50 and is located inward from the periphery of the resin main surface 51. Each of the two power terminals 17 has a connection surface 175 exposed from the sealing resin 50. The connection surface 175 faces the same side as the first surface 71a of the base 71 of the heat dissipation member C10 in the thickness direction z. The connection surfaces 175 of the two power terminals 17 are individually exposed from two openings 561 in the sealing resin 50.

[0212] The semiconductor packages B11 to B15 described above can be applied to any of the semiconductor modules A10, A20, A30, A40, and A50 according to the first to fifth embodiments (including their modifications). Therefore, in the semiconductor module of the present disclosure, the configuration of the semiconductor package is not limited in any way.

[0213] The semiconductor device and semiconductor device manufacturing method according to the present disclosure are not limited to the above-described embodiment. The specific configuration of each part of the semiconductor device according to the present disclosure and the specific processing of each step of the semiconductor device manufacturing method according to the present disclosure can be freely designed and modified in various ways. For example, the semiconductor device and semiconductor device manufacturing method according to the present disclosure include embodiments related to the following appendices. Note that, although examples of each component in the following appendices are shown in parentheses using the symbols in the above-described embodiment (including modified examples), the present disclosure is not limited to these. Appendix 1. a semiconductor package (B10) including at least one semiconductor element (21, 22) and at least one sealing resin (50) covering the at least one semiconductor element (21, 22); and a heat dissipation member (C10) including a base (71) located on one side (z1 side) of the semiconductor package (B10) in a thickness direction (z) of the semiconductor package (B10), wherein the base (71) has a first surface (71a) to which the semiconductor package (B10) is joined and a second surface (71b) facing the opposite side to the first surface (71a) in the thickness direction (z), the at least one sealing resin (50) being in contact with the first surface (71a), and the heat dissipation member (C10) including a plurality of heat dissipation fins (751) in contact with the second surface (71b), a semiconductor module (A10) having a placement area (72) in which the plurality of heat dissipation fins (751) are placed and a non-placement area (73) in which the plurality of heat dissipation fins (751) are not placed, the placement area (72) being located in a range of the second surface (71b) that overlaps with the at least one semiconductor element (21, 22) as viewed in the thickness direction (z), and the non-placement area (73) being located between both ends (72a) of the placement area (72) in a first direction (x) perpendicular to the thickness direction (z).Supplementary Note 2. The semiconductor module (A10) according to Supplementary Note 1, wherein the at least one semiconductor element (21, 22) includes a plurality of semiconductor elements (21, 22), the at least one sealing resin (50) includes a plurality of sealing resins (50) covering at least one of each of the plurality of semiconductor elements (21, 22), the plurality of sealing resins (50) being arranged with gaps therebetween along the first direction (x), and the non-placement region (73) includes at least one intervening portion (731) that overlaps a gap between the plurality of sealing resins (50) adjacent in the first direction (x) when viewed in the thickness direction (z). Supplementary Note 3. The semiconductor module according to Supplementary Note 2, wherein the at least one intervening portion (731) is divided into a plurality of regions by the placement region (72). Supplementary Note 4. The semiconductor module (A30) according to any one of Supplementary Notes 1 to 3, wherein the non-placement area (73) overlaps with the at least one sealing resin (50) when viewed in the thickness direction (z). Supplementary Note 5: The semiconductor module (A30) according to Supplementary Note 4, wherein the non-placement area (73) is surrounded by the placement area (72) in an area of ​​the second surface (71b) that overlaps with the at least one sealing resin (50). Supplementary Note 6: The semiconductor module (A13) according to any one of Supplementary Notes 1 to 5, wherein the non-placement area (73) has a recess (71c) in the thickness direction (z). Supplementary Note 7: The semiconductor module (A10) according to any one of Supplementary Notes 1 to 6, wherein each of the plurality of heat dissipation fins (751) is a pin fin extending from the second surface (71b) in the thickness direction (z). Supplementary Note 8: The semiconductor module (A10) according to any one of Appendix 1 to Appendix 7, further comprising a support substrate (10) that supports the at least one semiconductor element (21, 22), wherein the at least one sealing resin (50) has a resin main surface (51) that faces the same direction as the first surface (71 a) in the thickness direction (z) and a resin back surface (52) that faces the opposite side to the resin main surface (51) in the thickness direction (z), the support substrate (10) is exposed from the resin back surface (52), and the first surface (71 a) is in contact with the support substrate (10) and the resin back surface (52).Supplementary Note 9. The semiconductor module (A10) according to Supplementary Note 8, further comprising a signal terminal (19) electrically connected to any one of the at least one semiconductor elements (21, 22), the signal terminal (19) protruding from the resin main surface (51) of the at least one sealing resin (50). Supplementary Note 10. The semiconductor module (A10) according to Supplementary Note 8 or Supplementary Note 9, further comprising a power terminal (15, 16, 17) electrically connected to any one of the at least one semiconductor elements (21, 22), the power terminal (15, 16, 17) being exposed at the resin main surface (51) of the at least one sealing resin (50). Supplementary Note 10-1. The semiconductor module (A10) according to any one of Supplementary Notes 1 to 10, wherein the at least one semiconductor element (21, 22) includes a semiconductor substrate. Supplementary Note 10-2. The semiconductor module (A10) according to Appendix 10-1, wherein the semiconductor substrate includes either silicon, a wide bandgap semiconductor having a bandgap wider than that of silicon (e.g., silicon carbide or gallium nitride), or an ultra-wide bandgap semiconductor having a bandgap wider than that of a wide bandgap semiconductor (e.g., gallium oxide, diamond, or aluminum nitride). Appendix 10-3. A power conversion unit (U10, U11) further comprising: the semiconductor module (A10) according to any of Appendixes 1 to 10, 10-1, and 10-2; and a control board (E1) for driving the at least one semiconductor element (21, 22). Appendix 10-4. A vehicle (F1) comprising: the semiconductor module (A10) according to any of Appendixes 1 to 10, 10-1, and 10-2; and a drive source (F132), wherein the semiconductor module is electrically connected to the drive source (F132).Supplementary Note 11. The method includes a substrate bonding step (S102) of bonding at least one substrate (10) to a heat dissipation member (C10), an element bonding step (S103) of bonding semiconductor elements (21, 22) to the at least one substrate (10), and a molding step (S109) of forming at least one sealing resin (50) covering the semiconductor elements (21, 22) by mold molding, wherein the heat dissipation member (C10) includes a base (71) having a first surface (71a) and a second surface (71b) spaced apart from each other in a thickness direction (z) of the at least one substrate (10), and a plurality of heat dissipation fins (751) in contact with the second surface (71b), and in the substrate bonding step (S102), the at least one substrate (10) is bonded to the first surface (71a), In the molding step (S109), the first surface (71a) and the second surface (71b) are sandwiched between an upper mold (81) and a lower mold (82), respectively, in the thickness direction (z), the lower mold (82) includes a recess (recess 821) that accommodates the plurality of heat dissipation fins (751) and an intermediate support (823) that contacts the second surface (71b) of the base (71), the intermediate support (823) being positioned between the plurality of heat dissipation fins (751). Supplementary Note 11-1. A manufacturing method for a semiconductor module (A10) according to Supplementary Note 11, in which the element bonding step (S103) is performed after the substrate bonding step (S102). Supplementary Note 11-2. A manufacturing method for a semiconductor module (A10) according to Supplementary Note 11, in which the element bonding step (S103) is performed before the substrate bonding step (S102). Supplementary Note 12. The method for manufacturing a semiconductor module (A10) according to Supplementary Note 11, wherein the at least one substrate (10) includes a plurality of substrates (10), the at least one sealing resin (50) includes a plurality of sealing resins (50) individually formed on the plurality of substrates (10), and in the molding step (S109), the intermediate support (823) overlaps between adjacent pieces of the sealing resins (50) as viewed in the thickness direction (z).Appendix 13. A method for manufacturing a semiconductor module (A10) according to Appendix 11 or Appendix 12, wherein each of the plurality of heat dissipation fins (751) is a pin fin extending from the second surface (71b) in the thickness direction (z). Appendix 13-1. A method for manufacturing a semiconductor module (A30) according to any one of Appendix 11 to Appendix 13, wherein, in the molding step (S109), the recess (821) overlaps with the at least one sealing resin (50) when viewed in the thickness direction (z). Appendix 13-2. A method for manufacturing a semiconductor module (A30) according to Appendix 13-1, wherein, in the molding step (S109), the intermediate support (823) is surrounded by the recess (821). Appendix 14. The method for manufacturing a semiconductor module (A10) according to any one of Appendix 11 to Appendix 13, wherein the at least one sealing resin (50) has a resin main surface (51) facing in the same direction as the first surface (71a) in the thickness direction (z) and a resin back surface (52) facing the opposite side to the resin main surface (51) in the thickness direction (z), and in the molding step (S109), the at least one sealing resin (50) is formed in a state where the at least one substrate (10) is bonded to the first surface (71a). Appendix 15. A method for manufacturing a semiconductor module (A10) according to Appendix 14, further comprising, after the molding step (S109), a signal terminal connecting step (S1102) of electrically connecting a signal terminal (19) to the semiconductor element (21, 22), wherein an insertion hole (58) is formed in the resin main surface (51) of the at least one sealing resin (50), and in the signal terminal connecting step (S1102), the signal terminal (19) is inserted into the insertion hole (58) to electrically connect the signal terminal (19) to the semiconductor element (21, 22).Supplementary Note 16. A method for manufacturing a semiconductor module (A10) according to Supplementary Note 14 or Supplementary Note 15, further comprising a power terminal connecting step (S1101) of electrically connecting power terminals (15, 16, 17) to the semiconductor elements (21, 22) after the molding step (S109), wherein openings (561, 562, 563) exposing a portion of the substrate (10) are formed in the resin main surface (51) of the at least one sealing resin (50), and in the power terminal connecting step (S1101), the power terminals (15, 16, 17) are connected to the substrate (10) exposed from the openings (S1101), thereby electrically connecting the power terminals (15, 16, 17) to the semiconductor elements (21, 22).

[0214] A10 to A13, A20, A30 to A32, A40, A50, A51: Semiconductor modules B10 to B15: Semiconductor packages 10: Support substrate 109: Bonding layer 11: Insulating substrate 11a: Substrate main surface 11b: Substrate back surface 12: Main surface metal layer 121: Conductor portion 121a: Conductor main surface 121b: Exposed area 122: Conductor portion 122a: Conductor main surface 122b: Exposed area 1221, 1222: Partition portion 123: Conductor portion 123a: Conductor main surface 123b: Exposed area 13: Back surface metal layer 15: Power terminal 151: Bonding portion 152: Suspension portion 153: Extension portion 155: Connection surface 16: Power terminal 161: Bonding portion 162: Suspension portion 165: Connection surface 17: Power terminal 171: Joint portion 172: Suspension portion 175: Connection surface 19: Signal terminal 191 to 194, 196, 197: Signal terminal 190: Tip portion 190A: Bulging portion 21: Semiconductor element 21a: Element main surface 21b: Element back surface 211: Back electrode 212, 213, 214: Principal surface electrode 219: Conductive bonding layer 22: Semiconductor element 22a: Element main surface 22b: Element back surface 221: Back electrode 222, 223, 224: Principal surface electrode 229: Conductive bonding layer 23: Thermistor 31: Conductive member 311: Main body portion 311a: Through hole 312: Joint portion 313: Joint portion 32: Conductive member 321: Main body portion 322: Joint portion 323: Intermediate portion 323a: Through hole 324: Bonding portion 33, 34, 35, 39: Conductive bonding layer 41 to 45: Connection member 50: Sealing resin 51: Resin main surface 52: Resin back surface 521: Recess 522: Protrusion 531 to 534: Resin side surface 56: Main surface opening 561, 562, 563: Opening 571, 572: Recess 573, 574: Convex portion 58: Insertion hole 601,602: Signal board 61: Insulating layer 62: Wiring layer 621 to 624: Wiring portion 63: Metal layer 64: Sleeve 71: Base 71a: First surface 71b: Second surface 71c: Recess 711: Main portion 712: Outer peripheral portion 712a: Through hole 715: Protrusion 716: Recess 72: Arrangement region 72a: Outermost edge 72b: Outermost edge 721: Main portion 722: Connecting portion 73: Non-arrangement region 731: Intervening portion 732, 732A, 732B: Encapsulated portion 75: Heat dissipation portion 751: Heat dissipation fin 801: Resin inflow cavity 802: Fin avoidance cavity 81: Upper mold 811: Recess 812: Protrusion 82: Lower mold 821: Recess 822: Periphery support 823: Intermediate support 91: Base material 911: Through hole 92: Main wiring 93: Back wiring 94: Internal wiring 96: Connecting wiring 97: Positioning pin C10: Heat dissipation member E1: Control board E11, E12: Circuit board F1: Vehicle F11: On-board charger F12: Storage battery F13: Drive system F131: Inverter F132: Drive source M10: Mold S101: Board preparation process S102: Support board bonding process S103: Element bonding process S104: Signal board bonding process S105: Conductive member bonding process S106: Sleeve bonding process S107: Thermistor bonding process S108: Wire bonding process S109: Molding process S110: Terminal connection process S1101: Power terminal connection process S1102: Signal terminal connection process U10, U11: power conversion unit,

Claims

1. A semiconductor module comprising: a semiconductor package comprising at least one semiconductor element and at least one sealing resin covering the at least one semiconductor element; and a heat dissipation member including a base located on one side of the semiconductor package in a thickness direction of the semiconductor package, wherein the base has a first surface to which the semiconductor package is bonded and a second surface facing the opposite side to the first surface in the thickness direction, the at least one sealing resin is in contact with the first surface, the heat dissipation member includes a plurality of heat dissipation fins in contact with the second surface, the second surface has a placement area where the plurality of heat dissipation fins are arranged and a non-placement area where the plurality of heat dissipation fins are not arranged, the placement area is located in an area of ​​the second surface that overlaps with the at least one semiconductor element when viewed in the thickness direction, and the non-placement area is located between both ends of the placement area in a first direction perpendicular to the thickness direction.

2. The semiconductor module according to claim 1, wherein the at least one semiconductor element includes a plurality of semiconductor elements, the at least one sealing resin includes a plurality of sealing resins that cover at least one of the plurality of semiconductor elements, the plurality of sealing resins are arranged with gaps along the first direction, and the non-arrangement area includes at least one intervening portion that overlaps a gap between the plurality of sealing resins adjacent in the first direction when viewed in the thickness direction.

3. The semiconductor module according to claim 2, wherein the at least one intervening portion is divided into a plurality of regions by the placement region.

4. The semiconductor module according to claim 1, wherein the non-placement area overlaps the at least one sealing resin when viewed in the thickness direction.

5. The semiconductor module according to claim 4, wherein the non-placement area is surrounded by the placement area in an area of ​​the second surface that overlaps with the at least one sealing resin.

6. The semiconductor module according to any one of claims 1 to 5, wherein the non-placement area has a recess in the thickness direction.

7. A semiconductor module according to any one of claims 1 to 6, wherein each of the plurality of heat dissipation fins is a pin fin extending from the second surface in the thickness direction.

8. A semiconductor module as described in any one of claims 1 to 7, further comprising a support substrate that supports the at least one semiconductor element, wherein the at least one sealing resin has a resin main surface that faces the same direction as the first surface in the thickness direction and a resin back surface that faces the opposite side to the resin main surface in the thickness direction, the support substrate is exposed from the resin back surface, and the first surface is in contact with the support substrate and the resin back surface.

9. The semiconductor module according to claim 8, further comprising a signal terminal electrically connected to any one of said at least one semiconductor element, said signal terminal protruding from said main resin surface of said at least one sealing resin.

10. The semiconductor module according to claim 8 or claim 9, further comprising a power terminal electrically connected to any one of said at least one semiconductor element, said power terminal being exposed on said main resin surface of said at least one sealing resin.

11. A method for manufacturing a semiconductor module, comprising: a substrate bonding process for bonding at least one substrate to a heat dissipation member; an element bonding process for bonding a semiconductor element to the at least one substrate; and a molding process for forming at least one sealing resin that covers the semiconductor element by mold molding, wherein the heat dissipation member includes a base having a first surface and a second surface that are spaced apart in the thickness direction of the at least one substrate, and a plurality of heat dissipation fins in contact with the second surface, wherein the substrate bonding process bonds the at least one substrate to the first surface, and wherein the molding process sandwiches the first surface and the second surface between an upper mold and a lower mold in the thickness direction, and the lower mold includes a recess that accommodates the plurality of heat dissipation fins and an intermediate support that contacts the second surface of the base, and the intermediate support is located between the plurality of heat dissipation fins.

12. A method for manufacturing a semiconductor module as described in claim 11, wherein the at least one substrate includes a plurality of substrates, the at least one sealing resin includes a plurality of sealing resins formed individually on the plurality of substrates, and in the molding process, the intermediate support overlaps between adjacent sealing resins when viewed in the thickness direction.

13. A method for manufacturing a semiconductor module according to claim 11 or 12, wherein each of the plurality of heat dissipation fins is a pin fin extending from the second surface in the thickness direction.

14. A method for manufacturing a semiconductor module described in any one of claims 11 to 13, wherein the at least one sealing resin has a resin main surface facing in the same direction as the first surface in the thickness direction and a resin back surface facing the opposite side to the resin main surface in the thickness direction, and in the molding process, the at least one sealing resin is formed with the at least one substrate bonded to the first surface.

15. A method for manufacturing a semiconductor module as described in claim 14, further comprising, after the molding step, a signal terminal connecting step of electrically connecting a signal terminal to the semiconductor element, wherein an insertion hole is formed in the resin main surface of the at least one sealing resin, and in the signal terminal connecting step, the signal terminal is inserted into the insertion hole to electrically connect the signal terminal to the semiconductor element.

16. A method for manufacturing a semiconductor module as described in claim 14 or claim 15, further comprising, after the molding step, a power terminal connecting step of electrically connecting a power terminal to the semiconductor element, wherein an opening is formed in the main resin surface of the at least one sealing resin to expose a portion of the substrate, and in the power terminal connecting step, the power terminal is connected to the substrate exposed from the opening, thereby electrically connecting the power terminal to the semiconductor element.

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