Magnetic memory element, storage device, and writing method

Abstract

This magnetic storage element is provided with: a magnetization fixed layer in which the direction of magnetization is fixed; and a storage layer in which the direction of magnetization can be reversed. The storage layer includes a first region containing a ferromagnetic material, and a second region containing an antiferromagnetic material or a ferrimagnetic material.

Description

Magnetic memory element, storage device and writing method

[0001] The present disclosure relates to a magnetic memory element, a storage device, and a writing method.

[0002] Magnetic memory elements are known, as disclosed in, for example, Patent Documents 1 and 2. Data is written by reversing the magnetization of a storage layer included in the magnetic memory element.

[0003] JP 2020-155445 A International Publication No. 2018 / 179961

[0004] Mark Fedorov et.al., "Phase stability and magnetic properties in fcc Fe-Cr-Mn-Ni alloys from first-principles modeling", PHYSICAL REVIEW B 101, 174416 (2020)Matsui et.al., "Magnetic Properties of fcc γ-Phase in the Ternary Co-Mn-Fe System", JOURNAL OF THE PHYSICAL SOCIETY OF JAPAN, Vol. 35, No.2, AUGUST, 1973Y. Sokolovskaya et al., "A Ternary Map of Ni-Mn-Ga Heusler Alloys from Ab Initio Calculations", Materials 11, 973(2021) D. Bandyopadhyay et al., "Magnetic phase transitions in Fe80-xNixCr20(14≦x≦30) alloy studied by using 57Fe "Mo¨ossbauer spectroscopy", Hyperfine Interactions, 122, 239 (1999) 239-252 Young K. Yoo and Frank Tsui, "Continuous Phase Diagramming of Epitaxial Films", MRS bulletin, p316, (2002) T. Newhouse-Illige et.al., "Voltage-controlled interlayer coupling in perpendicularly "magnetized magnetic tunnel junctions", NATURE COMMUNICATIONS 2017

[0005] Reducing the power consumption of magnetic memory elements is an important issue, and reducing the power consumption required for magnetization reversal in the storage layer can be an effective solution.

[0006] One aspect of the present disclosure is to reduce power consumption.

[0007] A magnetic memory element according to one aspect of the present disclosure includes a magnetization fixed layer in which the magnetization direction is fixed, and a memory layer in which the magnetization direction is reversible, and the memory layer includes a first region including a ferromagnetic material and a second region including an antiferromagnetic material or a ferrimagnetic material.

[0008] A memory device according to one aspect of the present disclosure includes a magnetic memory element and a control circuit that controls writing of data to the magnetic memory element, wherein the magnetic memory element includes a magnetization fixed layer in which the magnetization direction is fixed and a memory layer in which the magnetization direction is reversible, and the memory layer includes a first region including a ferromagnetic material and a second region including an antiferromagnetic material or a ferrimagnetic material.

[0009] A writing method according to one aspect of the present disclosure is a method for writing data to a magnetic memory element, the magnetic memory element including a magnetization fixed layer in which the magnetization direction is fixed and a memory layer in which the magnetization direction is reversible, the memory layer including a first region including a ferromagnetic material and a second region including an antiferromagnetic material or a ferrimagnetic material, the magnetic memory element having a resistance value according to the magnetization direction of the memory layer, and the writing method includes applying one of a positive voltage and a negative voltage to the magnetic memory element so that the magnetic memory element has one of a low resistance value and a high resistance value, and applying the other of the positive voltage and the negative voltage to the magnetic memory element so that the magnetic memory element has the other of the low resistance value and the high resistance value.

[0010] 1 is a diagram showing an example of a schematic configuration of a magnetic memory element 1 according to an embodiment. FIG. 1 is a diagram showing an example of a schematic configuration of a magnetic memory element 1. FIG. 2 is a diagram showing an example of a composition range of a material of a second region 32. FIG. 3 is a diagram showing an example of a composition range of a material of a second region 32. FIG. 4 is a diagram showing an example of a composition range of a material of a second region 32. FIG. 5 is a diagram showing an example of a composition range of a material of a second region 32. FIG. 6 is a diagram showing an example of a composition range of a material of a second region 32. FIG. 7 is a diagram showing an example of a composition range of a material of a second region 32. FIG. 8 is a diagram showing an example of a composition range of a material of a second region 32. FIG. 9 is a diagram showing an example of a composition range of a material of a second region 32. FIG. 10 is a diagram showing an example of a composition range of a material of a second region 32. FIG. 11 is a diagram showing an example of electric and magnetic properties of a magnetic memory element 1. FIG. 12 is a diagram showing an example of electric and magnetic properties of a magnetic memory element 1. FIG. 13 is a diagram showing a comparative example. FIG. 14 is a diagram showing a comparison of voltage dependence of hysteresis shift of RH loop characteristics. FIG. 15 is a diagram showing the effect of the second region 32 on the magnetization reversal of the first region 31. FIG. 16 is a diagram showing the effect of the second region 32 on the magnetization reversal of the first region 31. FIG. 17 is a diagram showing an example of a schematic configuration of a magnetic memory element 1. 1 is a diagram showing an example of a schematic configuration of a magnetic memory element 1. FIG. 1 is a diagram showing an example of a schematic configuration of a magnetic memory element 1. FIG. 1 is a diagram showing Example 1. FIG. 2 is a diagram showing Example 2. FIG. 2 is a diagram showing a comparative example. FIG. 3 is a diagram showing modified Example 11 and modified Example 12. FIG. 3 is a diagram showing Example 3, modified Example 21, and modified Example 22. FIG. 4 is a diagram showing modified Example 23 and modified Example 24. FIG. 4 is a diagram showing modified Example 13, modified Example 14, and modified Example 25. FIG. 5 is a diagram showing modified Example 15. FIG. 6 is a diagram showing an experimental example of the material of the second region 32. FIG. 7 is a diagram showing an experimental example of the material of the second region 32. FIG. 8 is a diagram showing modified Examples 41 to 45. FIG. 9 is a diagram showing modified Examples 46 and 47. FIG. 10 is a diagram showing modified Examples 51 and 52. FIG. 11 is a diagram showing modified Examples 61 and 62. FIG. 9 is a diagram showing the principle of writing data to a magnetic memory element 1. FIG. 10 is a diagram showing an example of a schematic configuration of a storage device 7 according to the first embodiment. FIG. 11 is a flowchart showing an example of a process (data writing method) executed when writing data. FIG. 12 is a diagram showing an example of a timing chart when writing data. FIG. 13 is a flowchart showing an example of a process (data reading method) executed when reading data.1 is a diagram showing an example of a timing chart when reading data. FIG. 2 is a flowchart showing an example of processing (data writing method) executed when writing data. FIG. 3 is a diagram showing an example of a timing chart when writing data. FIG. 4 is a flowchart showing an example of processing (data writing method) executed when writing data. FIG. 5 is a diagram showing an example of a timing chart when writing data. FIG. 6 is a diagram showing an example of a schematic configuration of a storage device 7 according to a second embodiment. FIG. 7 is a flowchart showing an example of processing executed when initializing. FIG. 8 is a diagram showing an example of a timing chart when initializing. FIG. 9 is a flowchart showing an example of processing (data writing method) executed when writing data. FIG. 10 is a diagram showing an example of a schematic configuration of a storage device 7 according to a third embodiment. FIG. 11 is a flowchart showing an example of processing executed in an AI chip 10. FIG. 12 is a flowchart showing an example of processing executed in an AI chip 10. FIG. 13 is a diagram showing a modified example. FIG. 14 is a flowchart showing an example of processing executed in an AI chip 10. FIG. 15 is a diagram showing an example of a schematic configuration of a storage device 7 according to a fourth embodiment. FIG. 16 is a flowchart showing an example of processing executed in a solid-state imaging device 14. FIG. 17 is a flowchart showing an example of processing executed in a solid-state imaging device 14. FIG. 18 is a diagram showing an example of a schematic configuration of a storage device 7 according to a fifth embodiment. FIG. 19 is a diagram showing a modified example. 13 is a diagram showing an example of a schematic configuration of a storage device 7 according to a sixth embodiment. FIG.

[0011] Hereinafter, embodiments of the present disclosure will be described in detail with reference to the drawings. In the following embodiments, the same elements are designated by the same reference numerals, and redundant description will be omitted.

[0012] The present disclosure will be described in the following order: 0. Introduction 1. Magnetic Memory Element Embodiments 2. Storage Device Embodiments 2.1 First Embodiment 2.2 Second Embodiment 2.3 Third Embodiment 2.4 Fourth Embodiment 2.5 Fifth Embodiment 2.6 Sixth Embodiment

[0013] 0. Introduction Magnetic memory elements are nonvolatile and do not require data refreshing, which can be useful for reducing the power consumption of storage devices, for example. Using storage devices for AI (Artificial Intelligence) calculations and various calculations within solid-state imaging devices increases the possibility of reducing power consumption during calculations and expanding calculation-related functions.

[0014] Patent Document 1 discloses a spin-polarized current-driven (STT: Spin Transfer Torque) magnetic memory element. The current applied to the magnetic memory element is bipolar current-driven, meaning it operates in both the positive and negative directions. However, to improve retention characteristics, the current used when writing data must also be increased, which leads to increased power consumption.

[0015] Patent Document 2 discloses a voltage-controlled (VC) magnetic memory element. Using voltage modulation of magnetic anisotropy (VCMA), the energy barrier between two states where the magnetization direction is reversed is removed, the magnetization precesses around the in-plane magnetic field, and the barrier is restored by cutting off the voltage at the right time, completing the magnetization reversal. Because it is voltage-driven, data can be written at high speed with low power consumption. However, because it is a unipolar voltage-driven toggle write, the initial state must always be read at the beginning of the write sequence. Furthermore, timing control on the order of 1 ns (nanosecond) is required when writing data. Issues remain, such as the difficulty of control.

[0016] According to the technology of the present application, the power consumption (voltage, current) required for magnetization reversal is reduced. As will be described in detail later, the storage layer of the magnetic memory element includes a first region containing a ferromagnetic material and a second region containing an antiferromagnetic material or a ferrimagnetic material. Due to their magnetic coupling, the magnetization reversal of the first region is assisted by the second region, reducing the power consumption required for magnetization reversal, i.e., data writing. Voltage writing by applying voltage in the positive and negative layer directions is also possible. Furthermore, when reversing the magnetization of the storage layer, asymmetry may exist between the reversal directions.

[0017] In a storage device using the above-described magnetic memory element, data is written to the magnetic memory element using a new method, which reduces power consumption compared to conventional methods and enables faster data writing. Data retention performance can also be improved.

[0018] In one embodiment, magnetic memory elements of different sizes are mixed and provided. Two types of memory areas, a memory area that does not require long-term data retention (e.g., working memory) and a memory area that requires long-term data retention (e.g., storage memory), can be realized within a single device, chip, etc. using the same process. For example, both short-term retention and long-term retention areas required in a chip for AI calculations (AI function chip) can be provided within the same chip. A similar method can also be applied to solid-state imaging devices such as CMOS image sensors. The functions of various types of memory that have been used conventionally, such as SRAM (Static Random Access Memory), DRAM (Dynamic Random Access Memory), and flash memory, can be realized using the disclosed magnetic memory elements.

[0019] 1 is a diagram showing an example of a schematic configuration of a magnetic memory element 1 according to an embodiment. The magnetic memory element 1 is an MTJ (magnetic tunnel junction) element and has a TMR (tunnel magnetoresistance) effect.

[0020] The magnetic memory element 1 includes a magnetization fixed layer 2 and a memory layer 3. An XYZ coordinate system is also shown. The X-axis direction and Y-axis direction (XY plane direction) correspond to the surface direction of the layer. The Z-axis direction corresponds to the thickness direction of the layer. The positive and negative Z-axis directions are also referred to as the upward and downward directions, vertical direction, etc. The magnetic memory element 1 is provided on a substrate such as a Si substrate, and in this sense, the negative Z-axis direction side can also be said to be the substrate side. The X-axis direction and Y-axis direction are also referred to as the horizontal direction, etc. Note that the term "layer" may be interpreted to include a "film," and the terms "layer" and "film" may be interpreted interchangeably as appropriate within the scope of no contradiction.

[0021] The magnetic memory element 1 may have a bottom-pin type configuration in which the magnetization fixed layer 2 is located below the memory layer 3, or may have a top-pin type configuration in which the magnetization fixed layer 2 is located above the memory layer 3. FIG. 1A shows a bottom-pin type magnetic memory element 1. The magnetization fixed layer 2 and memory layer 3 are stacked in this order in the positive direction of the Z axis. FIG. 1B shows a top-pin type magnetic memory element 1. The memory layer 3 and magnetization fixed layer 2 are stacked in this order in the positive direction of the Z axis. Unless otherwise specified, the magnetic memory element 1 is assumed to have a bottom-pin type configuration as shown in FIG. 1A.

[0022] The magnetization fixed layer 2 is a layer in which the magnetization direction is fixed (pinned layer), and is also referred to as a magnetization fixed layer, a fixed layer, etc. The magnetization fixed layer 2 may include a plurality of layers. FIG. 1 illustrates a fixed layer 21 and a reference layer 22 as examples of layers included in the magnetization fixed layer 2. For convenience, the reference layer 22 and the fixed layer 21 will be described in that order.

[0023] The reference layer 22 is a layer whose magnetization direction is fixed, and this magnetization direction corresponds to the magnetization direction of the magnetization fixed layer 2. Examples of materials for the reference layer 22 include Fe, Co, Ni, Mn, B, etc. At least one or two or more of these may be used as the material for the reference layer 22. It can also be said that a material including one selected from this group is used as the material for the reference layer 22.

[0024] The pinned layer 21 is a layer (pinning layer) that fixes the magnetization direction of the reference layer 22. Examples of materials for the pinned layer 21 include Fe, Co, FeCo, Ru, Ir, Pd, and Os. The pinned layer 21 may have an SAF (synthetic antiferromagnet) structure in which Fe, Co, FeCo, or the like is provided on opposite sides of Ru, Ir, Pd, Os, or the like. The pinned layer 21 may include a perpendicular magnetization film, and examples of materials for the perpendicular magnetization film include Ir, Pt (platinum), Pd, Ru, Ni, Fe, Co, Mn, and Cr. At least one or two or more of these may be used as the material for the pinned layer 21.

[0025] The memory layer 3 is a layer in which the direction of magnetization can be reversed, and is also called a free layer, etc. Data corresponding to the direction of magnetization of the memory layer 3, for example, bit data of "0" or "1", is stored (written) in the memory layer 3. Note that "data" may also be interpreted as meaning information, and data and information may be interpreted appropriately interchangeably within a consistent range.

[0026] The memory layer 3 includes a first region 31 and a second region 32. The first region 31 includes a ferromagnetic material. The second region 32 includes an antiferromagnetic material or a ferrimagnetic material. The first region 31 and the second region 32 are provided so as to be magnetically coupled to each other.

[0027] The second region 32 may include an antiferromagnetic layer, magnetic grains, magnetic domains, etc. in which microscopically adjacent magnetic moments are arranged antiparallel to each other rather than in the same direction. The second region 32 does not necessarily have to be an antiferromagnetic phase in which microscopically adjacent magnetic moments are of the same magnitude and compensate each other, but may be a ferrimagnetic phase in which adjacent antiparallel magnetic moments have different magnitudes.

[0028] Various arrangements of the first regions 31 and the second regions 32 are possible in the storage layer 3. This will be described with reference to FIG.

[0029] 2 is a diagram showing an example of a schematic configuration of the magnetic memory element 1. In this example, the memory layer 3 of the magnetic memory element 1 further includes a barrier layer 30 and a spacer region 33 in addition to a first region 31 and a second region 32.

[0030] 2A and 2B, the first region 31 and the second region 32 are stacked. Specifically, the first region 31, the second region 32, and the spacer region 33 are realized as layers containing their respective materials. The first region 31 is a layer containing a ferromagnetic material (ferromagnetic layer). The second region 32 is a layer containing an antiferromagnetic material or a ferrimagnetic material (antiferromagnetic layer or ferrimagnetic layer). The spacer region 33 is a layer containing a nonmagnetic material (spacer layer).

[0031] 2A, the magnetization fixed layer 2, the barrier layer 30, the second region 32, the spacer region 33, and the first region 31 are stacked in this order along the positive direction of the Z-axis. In the example shown in FIG. 2B, the magnetization fixed layer 2, the barrier layer 30, the first region 31, the spacer region 33, and the second region 32 are stacked in this order along the positive direction of the Z-axis.

[0032] The first region 31 may have a thickness of, for example, 0.1 nm to 1.5 nm. If the thickness is too large, it becomes difficult to obtain perpendicular magnetic anisotropy. If the thickness is too small, it becomes difficult to obtain stable magnetization (state).

[0033] The first region 31 may have a single crystal structure oriented in the (001) plane of a body-centered cubic structure, or a polycrystalline structure preferentially oriented in the (001) plane, so as to be crystalline oriented with the barrier layer 30 and obtain a good TMR ratio.

[0034] The second region 32 may have a thickness of, for example, 0.1 nm to 5 nm, which prevents magnetization reversal from becoming too difficult and makes it easier to obtain the necessary magnetization reversal assist effect.

[0035] 2C , the storage layer 3 includes a plurality of dispersed first regions 31 and second regions 32. The first regions 31 and second regions 32 are dispersed and arranged in the storage layer 3 in the form of, for example, grains, crystal grains, magnetic domains, etc. In this example, a spacer region 33 exists between the first regions 31 and the second regions 32, but the spacer region 33 may be omitted.

[0036] The barrier layer 30 is provided between the first region 31 and the second region 32 of the storage layer 3 and the magnetization fixed layer 2 so as to obtain the TMR effect. The barrier layer 30 is also called a tunnel barrier layer or a tunnel barrier layer.

[0037] An example of the material of the barrier layer 30 is an oxide such as MgO. Examples of materials that can be used as the source of an oxide include Mg, Ca, Li, Si, Al, Sr, Zr, Hf, Ti, Zn, Mo, Cu, Ba, Ta, W, V, Ni, Co, Mn, Cr, Fe, B, and C. An oxide containing at least one or two or more of these elements may be used as the material of the barrier layer 30.

[0038] As an example, an oxide containing Mg, i.e., MgO, may be used as the material of the barrier layer 30. Other materials may be added to stabilize the barrier performance (barrier resistance, etc.). Examples of other materials are Fe, Co, Mn, etc. The amount of Fe, Co, or Mn added may be, for example, 20 at% (atomic percent) or less. The lower limit may be greater than 0 at%. Examples of suitable amounts are 1 at%, 5 at%, 10 at%, etc. From the viewpoint of obtaining a stable TMR ratio (tunnel magnetoresistance ratio), the area resistance of the barrier layer 30 should be 1 mΩμm ２ It may be more than that.

[0039] Other examples of materials for the barrier layer 30 include Sc, Y, La, Ce, Pr, Nd, Pm, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb, Lu, etc. An oxide containing at least one or two or more of these elements may be used as the material for the barrier layer 30.

[0040] The spacer region 33 is provided between the first region 31 and the second region 32 so that the first region 31 and the second region 32 are magnetically coupled to each other. The magnetization of the second region 32 acts on the magnetization of the first region 31 via the spacer region 33. More specifically, the magnetization direction of the first region 31 changes in response to a change in the magnetization direction of the second region 32, thereby assisting the magnetization reversal of the first region 31.

[0041] The spacer region 33 includes a nonmagnetic material. Examples of nonmagnetic materials include Ta, Ru, Ir, W, Mo, Rh, Re, Nb, Cu, Cr, V, TiN, TaN, and WN. At least one or more of these may be used as the material of the spacer region 33. The spacer region 33 may have a thickness of, for example, 0.1 nm to 1.5 nm. If the thickness of the spacer region 33 is less than 0.1 nm, the effect of the spacer region 33 is reduced, and, for example, interdiffusion of the magnetic material components of the first region 31 or the second region 32 is more likely to occur. If the thickness of the spacer region 33 is greater than 1.5 nm, it is difficult to obtain interlayer coupling between the second region 32 and the first region 31.

[0042] The following describes more specific materials for the first region 31 and the second region 32. For example, the material for the first region 31 may be at least one or two or more of Co, Fe, Ni, Mn, Al, B, P, C, Zr, Hf, Ta, and Nb.

[0043] An example of a combination of multiple materials is CoFeB. The composition ratio of Co, Fe, and B is designed to obtain perpendicular magnetic anisotropy. For example, the composition ratio of Fe may be greater than the composition ratio of Co. The composition ratio of B may be 40 at% or less. The lower limit may be greater than 0 at%. Examples of the lower limit include 1 at%, 5 at%, and 10 at%.

[0044] The material of the second region 32 may be at least one or more of Mn, Cr, Ir, Pt, Pd, Ni, Sn, Fe, Ge, Co, Ga, and Si.

[0045] Examples of combinations of multiple materials, more specifically antiferromagnetic or ferrimagnetic alloys, include FeNiMn, CrNiMn, FeCrMn, FeCoMn, CoNiMn, FeNiCr, GaNiMn, CoPtMn, FePMn, FeMn, NiMn, FeNi, PtMn, PdMn, and CoGeMn, etc. An antiferromagnetic or ferrimagnetic phase derived from the alloy is obtained.

[0046] In one embodiment, the material of the second region 32 may include a rare earth material and a metallic material. Examples of rare earth materials include Sc, Y, La, Ce, Pr, Nd, Pm, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb, and Lu. Examples of metallic materials include Fe, Co, Ni, and Mn. A combination of at least one of the rare earth materials described herein and at least one of the metallic materials described herein, such as GdFeCo, GdFe, GdCo, TbFe, TbCo, DyFeCo, DyFe, and DyCo, may be used as the material of the second region 32.

[0047] In one embodiment, the material of the second region 32 may include Mn-chalcogenides, such as CuMnAs and MnPS3.

[0048] In one embodiment, the material of the second region 32 may include an oxide, such as NiO, Cr2O3, CoO, Fe2O3, and Mn2O3.

[0049] The composition ranges of some materials are described with reference to FIGS.

[0050] 3 to 9 are diagrams showing examples of the composition range of the material of the second region 32. Each diagram shows a ternary map of the composition range.

[0051] FIG. 3 shows the composition range when the material of the second region 32 is FeNiMn. ｘ Ni ｙ Mn ｚ The composition ranges of are expressed as follows: An antiferromagnetic phase or a ferrimagnetic phase as shown in Non-Patent Document 1 is obtained. 0 at%<x≦95 at% 0 at%<y≦80 at% 5 at%≦z≦80 at% The lower limit of x may be greater than 0 at%. Examples of the lower limit are 1 at%, 5 at%, 10 at%, etc. The same applies to the lower limit of y.

[0052] FIG. 4 shows the composition range when the material of the second region 32 is CrNiMn. ｘ Ni ｙ Mn ｚThe composition ranges of are expressed as follows: An antiferromagnetic phase or a ferrimagnetic phase as shown in Non-Patent Document 1 is obtained. 0 at%≦x≦65 at% 0 at%≦y≦75 at% 0 at%≦z≦80 at% The lower limit of x may be greater than 0 at%. Examples of the lower limit are 1 at%, 5 at%, 10 at%, etc. The lower limit of y and the lower limit of z may be similar.

[0053] FIG. 5 shows the composition range when the material of the second region 32 is FeCrMn. ｘ Cr ｙ Mn ｚ The composition ranges of are expressed as follows: An antiferromagnetic phase or a ferrimagnetic phase as shown in Non-Patent Document 1 is obtained. 0 at%<x≦95 at% 0 at%<y≦70 at% 5 at%≦z≦80 at% The lower limit of x may be greater than 0 at%. Examples of the lower limit are 1 at%, 5 at%, 10 at%, etc. The lower limit of y may be the same.

[0054] FIG. 6 shows the composition range when the material of the second region 32 is FeCoMn. ｘ Co ｙ Mn ｚ The composition range of x is expressed as follows: An antiferromagnetic phase as shown in Non-Patent Document 2 is obtained. 0 at%≦x≦95 at% 0 at%≦y≦50 at% 5 at%≦z≦80 at% The lower limit of x may be greater than 0 at%. Examples of the lower limit are 1 at%, 5 at%, 10 at%, etc. The lower limit of y may be the same.

[0055] FIG. 7 shows the composition range when the material of the second region 32 is GaNiMn. ｘ Ni ｙ Mn ｚ The composition range of the alloy is expressed as follows: A ferrimagnetic phase as shown in Non-Patent Document 3 is obtained. 0 at%≦x≦50 at% 5 at%≦y≦80 at% 5 at%≦z≦90 at% The lower limit of x may be greater than 0 at%. Examples of the lower limit are 1 at%, 5 at%, 10 at%, etc.

[0056] FIG. 8 shows the composition range when the material of the second region 32 is FeNiCr. ｘ Ni ｙ Cr ｚ The composition ranges of 60 at%≦x≦82 at% 15 at%≦y≦40 at% 10 at%≦z≦35 at% are expressed as follows: A ferrimagnetic phase as shown in Non-Patent Document 4 is obtained.

[0057] 9 shows the composition range when the material of the second region 32 is CoGeMn. ｘ Ge ｙ Mn ｚ The composition ranges of are expressed as follows: An antiferromagnetic phase as shown in Non-Patent Document 5 is obtained. 0 at%≦x≦20 at% 0 at%≦y≦95 at% 5 at%≦z≦100 at% The upper limit of z may be smaller than 100 at%. Examples of the upper limit are 99 at%, 95 at%, 90 at%, etc.

[0058] Each of the above alloys exhibits an antiferromagnetic or ferrimagnetic phase derived from the ordered alloy of the elements contained therein. For example, FeNiMn, CrNiMn, FeCrMn, FeCoMn, and GaNiMn exhibit an antiferromagnetic or ferrimagnetic phase derived from the ordered alloy of FeMn, NiMn, CoMn, CrFe, NiFe, etc. contained therein. The same can be said for the other materials mentioned above.

[0059] The features of the magnetic memory element 1 according to the embodiment are also apparent in its electrical and magnetic properties, which will be described with reference to FIGS.

[0060] 10 to 12 are diagrams showing examples of the electrical and magnetic characteristics of the magnetic memory element 1. The magnetic memory element 1 has an RH loop characteristic in which the resistance value changes with hysteresis depending on the magnitude of the applied magnetic field. The resistance value of the magnetic memory element 1 is also referred to as the resistance value R. The applied magnetic field is also referred to as the magnetic field H.

[0061] 10 is a graph showing the RH loop characteristics of the magnetic memory element 1. The horizontal axis of the graph represents the magnetic field H (magnitude). The vertical axis of the graph represents the resistance value R. The voltage applied to the magnetic memory element 1, more specifically, the voltage applied from the upper electrode (corresponding to the aforementioned Cap layer 6) side to the substrate side, is referred to as voltage V. Voltage V can also be called bias voltage, applied voltage, etc.

[0062] 10 shows multiple RH loop characteristics corresponding to different voltages V, more specifically, three types of RH loop characteristics, as graph lines C1, C2, and C3. Graph line C1 shows the RH loop characteristics when substantially no voltage V is applied to the magnetic memory element 1, i.e., when voltage V≈0 (e.g., 0 mV, several mV, or several tens of mV). Graph line C2 shows the RH loop characteristics when a positive voltage (voltage V>0) is applied to the magnetic memory element 1. Graph line C3 shows the RH loop characteristics when a negative voltage (voltage V<0) is applied to the magnetic memory element 1.

[0063] When no voltage V is applied to the magnetic memory element 1 (voltage V≈0), the magnetic memory element 1 can have either a low resistance value or a high resistance value in a state where no magnetic field is applied (magnetic field H=0), and can store information in either a high resistance state or a low resistance state. Furthermore, when a positive magnetic field is applied to the magnetic memory element 1 in the high resistance state, the magnetic memory element 1 switches to a low resistance state with the positive magnetic field H, and when a negative magnetic field H is applied to the magnetic memory element 1 in the low resistance state, the magnetic memory element 1 switches to a high resistance state.

[0064] On the other hand, as shown by graph lines C2 and C3, when one of a positive voltage and a negative voltage is applied to the magnetic memory element 1, the magnetic memory element 1 has one of a low resistance value and a high resistance value, and when the other voltage is applied, the magnetic memory element 1 has the other resistance value. More specifically, for example, when a sufficiently large positive voltage V is applied, as shown by graph line C2, the RH loop characteristics shift so that the magnetic field H at which the magnetic memory element 1 in the high resistance state switches to the low resistance state and the magnetic field H at which the magnetic memory element 1 in the low resistance state switches to the high resistance state are both negative. Therefore, even without applying a magnetic field H (external magnetic field), switching from high resistance to low resistance is possible by applying a positive voltage V to the magnetic memory element 1. Similarly, when a sufficiently large negative voltage V is applied, as shown by graph line C3, the RH loop characteristics shift so that the magnetic field H at which the magnetic memory element 1 in the low resistance state switches to the high resistance state and the magnetic field H at which the magnetic memory element 1 in the high resistance state switches to the low resistance state are both positive. Therefore, it is possible to switch from low resistance to high resistance by applying a negative voltage V to the magnetic memory element 1 without applying a magnetic field H. In other words, the resistance value of the magnetic memory element 1 can be switched depending on whether the voltage V applied to the magnetic memory element 1 is positive or negative.

[0065] In other words, as shown by graph line C2, when a positive voltage (voltage V>0) is applied to the magnetic memory element 1, the magnetic memory element 1 has a low resistance value. As shown by graph line C3, when a negative voltage (voltage V<0) is applied to the magnetic memory element 1, the magnetic memory element 1 has a high resistance value.

[0066] Please pay attention to the RH loop characteristics, and more particularly, the voltage dependence of its hysteresis. The hysteresis of the RH loop characteristics when a positive voltage is applied to the magnetic memory element 1 and the hysteresis of the RH loop characteristics when a negative voltage is applied are shifted in opposite directions from the hysteresis of the RH loop characteristics when substantially no voltage V is applied to the magnetic memory element 1 (voltage V≈0). The shift here means a shift on the horizontal axis of the graph, in other words, a shift in the direction of the magnitude of the magnetic field H.

[0067] More specifically, as shown by the graph line C1, the hysteresis of the RH loop characteristic when substantially no voltage is applied to the magnetic memory element 1 crosses the magnetic field H = 0. As described above, the resistance value of the magnetic memory element 1 can be either a high resistance value or a low resistance value.

[0068] In contrast, as shown by graph line C2, the hysteresis of the RH loop characteristic when a positive voltage (voltage V>0) is applied to the magnetic memory element 1 does not cross the magnetic field H=0. The resistance value of the magnetic memory element 1 is uniquely determined to be a low resistance value, and the resistance value can be switched. Furthermore, as shown by graph line C3, the hysteresis of the RH loop characteristic when a negative voltage (voltage V<0) is applied to the magnetic memory element 1 does not cross the magnetic field H=0. The resistance value of the magnetic memory element 1 is uniquely determined to be a high resistance value, and the resistance value can be switched.

[0069] As described above, in the magnetic memory element 1, the hysteresis of the RH loop characteristic shifts depending on whether the voltage V is positive or negative. This shift may be asymmetric between when the voltage V is positive and when the voltage V is negative. The hysteresis of the RH characteristic when one of a positive voltage and a negative voltage is applied to the magnetic memory element 1 is greater than the hysteresis of the RH loop characteristic when the voltage V is substantially not applied to the magnetic memory element 1. Conversely, the hysteresis of the RH characteristic when the other of a positive voltage and a negative voltage is applied to the magnetic memory element 1 is smaller than the hysteresis of the RH loop characteristic when the voltage V is substantially not applied. That is, the hysteresis of the RH characteristic when a negative voltage V is applied to the magnetic memory element 1 has a smaller difference in the magnitude of the magnetic field H required for switching from a high resistance state to a low resistance state or from a low resistance state to a high resistance state, i.e., a smaller coercive force Hc, than the hysteresis of the RH loop characteristic when a positive voltage V is applied to the magnetic memory element 1.

[0070] Specifically, in the example shown in Figure 10, as shown by graph line C2, the hysteresis of the RH characteristics when a positive voltage (voltage V > 0) is applied to the magnetic memory element 1 is greater than the hysteresis of the RH loop characteristics when substantially no voltage V is applied to the magnetic memory element 1 (voltage V ≒ 0) as shown by graph line C1, in that the switching magnetic field H shifts in the negative direction and the difference (coercive force Hc) in the magnetic field H that switches from a high resistance state to a low resistance state and from a low resistance state to a high resistance state becomes larger. Conversely, as shown by graph line C3, the hysteresis of the RH characteristics when a negative voltage (voltage V<0) is applied to the magnetic memory element 1 is greater than the hysteresis of the RH loop characteristics when substantially no voltage V is applied to the magnetic memory element 1 (voltage V≒0) as shown by graph line C1, in that the switching magnetic field H shifts in the positive direction and the difference in magnetic field (coercive force Hc) switching from a high resistance state to a low resistance state and from a low resistance state to a high resistance state becomes smaller.

[0071] As described above, in the magnetic memory element 1 according to the embodiment, by applying a positive or negative voltage V, the hysteresis of the RH loop characteristic can be shifted to the positive or negative side, thereby making the resistance value low or high.

[0072] 11 shows a number of RH loop characteristics corresponding to different voltages V. The voltage V gradually changes from positive to negative between the top graph line and the bottom graph line. It can be seen that the amount of shift in the RH loop characteristics changes depending on the applied voltage V. The amount of shift can be changed by specifically designing the material composition and film thickness of the memory layer of the magnetic memory element 1.

[0073] 12 shows the RV characteristics and IV characteristics (IV loop characteristics) of the magnetic memory element 1. The horizontal axis of the graph represents voltage V, and the vertical axis of the graph represents current value I. The magnetic field H is 0 (zero).

[0074] As indicated by arrow AR1, when a positive voltage V is applied, the resistance value switches from a high resistance value to a low resistance value, and the current value I increases sharply. Furthermore, as indicated by arrow AR2, when a negative voltage V is applied, the resistance value switches from a low resistance value to a high resistance value, and the current value I decreases sharply. The switch in resistance value indicates a reversal of the magnetization of the first region 31 of the storage layer 3 of the magnetic memory element 1. The current required for the reversal is, for example, on the order of several μA to several tens of μA, which enables lower power consumption compared to the tens of μA required when a similar element is fabricated using a conventional spin-transfer MRAM.

[0075] The above effects will be explained using a comparative example.

[0076] 13 and 14 are diagrams showing comparative examples. The magnetic memory element 1E according to the comparative example shown in FIG. 13 differs from the magnetic memory element 1 according to the embodiment (FIG. 1, etc.) in that the memory layer 3 does not include the second region 32. FIG. 14 shows several RH loop characteristics corresponding to different voltages V. Specifically, graph line C11 shows the RH loop characteristics when substantially no voltage V is applied to the magnetic memory element 1, i.e., when voltage V≈0. Graph line C12 shows the RH loop characteristics when a positive voltage (voltage V>0) is applied to the magnetic memory element 1. Graph line C13 shows the RH loop characteristics when a negative voltage (voltage V<0) is applied to the magnetic memory element 1.

[0077] As can be seen, no shift occurs as in the magnetic memory element 1 according to the embodiment shown in FIG. 10 described above, and magnetization reversal utilizing this shift is difficult to achieve in the magnetic memory element 1E.

[0078] 15A and 15B are diagrams comparing the voltage dependence of the hysteresis shift of the RH loop characteristics. The diagrams schematically show the change in the RH loop characteristics depending on the voltage V. In the magnetic memory element 1 according to the embodiment, as shown in FIGS. 15A and 15B, the hysteresis of the RH loop characteristics shifts in response to the application of the voltage V so that the hysteresis does not cross the magnetic field H=0. Therefore, magnetization reversal by the application of the voltage V is possible.

[0079] On the other hand, in the magnetic memory element 1E according to the comparative example, as shown in (C) and (D) of Figure 15, an increase or decrease in coercivity due to the VCMA effect (voltage-controlled magnetic anisotropy modulation effect) is observed in the RH loop characteristics in response to the application of voltage V, but the hysteresis shift is insufficient to perform switching by voltage. Therefore, it is difficult to perform magnetization reversal by applying voltage V alone. For example, as in Patent Document 2 mentioned above, it is necessary to cause magnetization to precess around the in-plane magnetic field and stop the application of voltage V at the appropriate time.

[0080] As described above, in the magnetic memory element 1 according to the embodiment, the magnetization reversal of the first region 31 of the storage layer 3 is assisted by the second region 32. This mechanism can be explained, for example, as follows.

[0081] When a voltage V is applied to the magnetic memory element 1, the polarization direction of the second region 32 changes due to spin-polarized carrier accumulation or spin injection. Thereafter, the magnetization of the first region 31 is reversed (the reversal is assisted) by the exchange bias between the second region 32 and the first region 31. This will be described with reference to FIGS. 16 to 18.

[0082] 16 to 18 are diagrams showing the effect of the second region 32 on the magnetization reversal of the first region 31. The magnetization directions of the magnetization fixed layer 2 and the first and second regions 31 and 32 of the memory layer 3 are also shown schematically by white arrows. It should be noted that the magnetization direction of the magnetization fixed layer 2 is fixed in the positive direction of the Z axis. The voltage applied to the magnetic memory element 1 will be referred to as voltage V as before. The voltage V is a voltage other than 0 (zero), a sufficiently large applied voltage in the positive or negative direction, and a voltage that can cause magnetization reversal in the first region 31.

[0083] The magnetic memory element 1 shown in Fig. 16 has the same configuration as that shown in Fig. 2A described above. Fig. 16A shows a state in which no voltage V is applied to the magnetic memory element 1. In this example, the magnetization direction of the first region 31 is the negative direction of the Z axis.

[0084] A voltage V is applied to the magnetic memory element 1 to reverse the magnetization direction of the first region 31. In response to this, first, the magnetization in the second region 32 is reversed, as shown in Fig. 16B. The exchange coupling between the second region 32, whose magnetization has been reversed, and the first region 31 assists (promotes) the reversal of the magnetization of the first region 31. Then, as shown in Fig. 16C, the magnetization of the first region 31 is reversed.

[0085] The magnetic memory element 1 shown in Fig. 17 has the same configuration as that shown in Fig. 2B described above. Fig. 17A shows a state in which no voltage V is applied to the magnetic memory element 1. In this example, the magnetization direction of the first region 31 is in the negative direction of the Z axis.

[0086] A voltage V is applied to the magnetic memory element 1 to reverse the magnetization direction of the first region 31. In response to this, first, the magnetization in the second region 32 is reversed, as shown in Fig. 17B. The exchange coupling between the second region 32, whose magnetization has been reversed, and the first region 31 assists in reversing the magnetization of the first region 31. Then, as shown in Fig. 17C, the magnetization of the first region 31 is reversed.

[0087] The magnetic memory element 1 shown in Fig. 18 has the same configuration as that shown in Fig. 2C described above. Fig. 18A shows a state in which no voltage V is applied to the magnetic memory element 1. In this example, the magnetization direction of the first region 31 is the negative direction of the Z axis.

[0088] A voltage V is applied to the magnetic memory element 1 to reverse the magnetization direction of the first region 31. In response to this, first, the magnetization in the second region 32 is reversed, as shown in Fig. 18B. The exchange coupling between the second region 32, whose magnetization has been reversed, and the first region 31 assists in reversing the magnetization of the first region 31. Then, as shown in Fig. 18C, the magnetization of the first region 31 is reversed.

[0089] In the magnetic memory element 1 described above, the memory layer 3 includes not only the first region 31 but also the second region 32. Magnetic coupling (interphase coupling, exchange coupling, etc.) between the first region 31 and the second region 32 provides an assist effect for magnetization reversal in the first region 31. This reduces the power consumption (voltage, current) required for magnetization reversal and also realizes faster reversal. Data writing by applying layer-wise voltages of positive and negative voltages to the magnetic memory element 1, i.e., voltage writing, becomes possible.

[0090] Furthermore, in the magnetic memory element 1 according to the embodiment, the magnetization of the first region 31 can be reversed by a novel method that shifts the RH loop characteristics, including their hysteresis, rather than changing the coercivity by applying a voltage as in the case of VCMA. This enables low-power operation by reversing the magnetization with a bidirectional voltage bias. For example, this can address issues such as the need for a large current for magnetization reversal as in the case of conventional SST, or the need for unidirectional 1 ns short pulse control as in the case of VCMA.

[0091] <Modifications> More specific configurations of the magnetic memory element 1 will be described as several modifications.

[0092] In one embodiment, the storage layer 3 of the magnetic memory element 1 may include an additional barrier layer in addition to the barrier layer 30. This can improve heat resistance, magnetization reversal efficiency, etc. This will be described with reference to FIGS.

[0093] 19 is a diagram showing an example of a schematic configuration of the magnetic memory element 1. Compared to the configuration of FIG.

[0094] The barrier layer 34 is a second barrier region (barrier layer) provided on the opposite side of the magnetization fixed layer 2 across the first region 31 and the second region 32. The material of the barrier layer 34 may be the same as the material of the barrier layer 30. An example is an oxide such as MgO. Examples of materials that can be used as oxides include Mg, Ca, Li, Si, Al, Sr, Zr, Hf, Ti, Zn, Mo, Cu, Ba, Ta, W, V, Ni, Co, Mn, Cr, Fe, B, and C. Oxides containing at least one or more of these elements may be used. As an example, Fe, Co, Mn, or the like may be added to MgO to stabilize barrier performance (such as barrier resistance). The amount of Fe, Co, or Mn added may be, for example, 20 at% (atomic percent) or less. The lower limit may be greater than 0 at%. Examples of suitable additive amounts are 1 at%, 5 at%, 10 at%, etc. From the viewpoint of obtaining a stable TMR ratio (tunneling magnetoresistance ratio), it is preferable that the sheet resistance of the barrier layer 34 be lower than that of the barrier layer 30. As an example, oxides of Sc, Y, La, Ce, Pr, Nd, Pm, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb, Lu, etc., or oxides containing at least one or more of these, may be used as the material for the barrier layer 34. For example, as shown in Non-Patent Document 6, it is expected that the memory layer 3 will obtain a reversal assist effect due to voltage application via the barrier layer 34. Furthermore, antiferromagnetic oxides such as NiO, Cr2O3, CoO, Fe2O3, and Mn2O3 may be used as the material for the barrier layer 34.

[0095] An additional ferromagnetic layer may be provided on the barrier layer 34, separate from the magnetization fixed layer 2. This will be described with reference to FIG.

[0096] 20 is a diagram showing an example of a schematic configuration of a magnetic memory element 1. Compared to the previously described FIG. 19 , the magnetic memory element 1 further includes a ferromagnetic layer 4. The ferromagnetic layer 4 is provided on the barrier layer 34 on the opposite side of the barrier layer 34 from the first region 31 and the second region 32. The material of the ferromagnetic layer 4 may be the same as the material of the magnetization fixed layer 2. The magnetization fixed layer 2 and the first region 31 sandwiching the barrier layer 30, and the first region 31 and the ferromagnetic layer 4 sandwiching the second region 32, provide the functions of two MTJ elements (dual MTJ).

[0097] In one embodiment, the magnetic memory element 1 may include a further spacer region, more specifically a spacer layer, apart from the spacer region 33. This will be described with reference to FIG.

[0098] 21 is a diagram showing an example of a schematic configuration of a magnetic memory element 1. The magnetic memory element 1 differs from the previously described FIG. 20 in that it does not include a barrier layer 34 but includes a spacer layer 35. The spacer layer 35 is provided on the opposite side of the magnetization fixed layer 2, with the first region 31 and the second region 32 sandwiched between them. The ferromagnetic layer 4 is provided on the spacer layer 35, on the opposite side of the spacer layer 35, with the first region 31 and the second region 32 sandwiched between them. The material of the spacer layer 35 may be the same as the material of the spacer region 33. A synthetic antiferromagnetic film (SAF) is obtained in which the memory layer 3 is antiferromagnetically coupled via the spacer layer 35.

[0099] Examples Several examples based on the embodiments and modifications of the magnetic memory element 1 described above will be described.

[0100] 22A and 22B are diagrams illustrating Example 1. As shown in Fig. 22A, the magnetic memory element 1 includes a lower electrode layer 5 (underlying layer), a magnetization fixed layer 2, a memory layer 3, and a cap layer 6 (upper electrode layer), which are stacked in this order in the positive direction of the Z axis.

[0101] The material and thickness of each layer (excluding the thickness of the immobilization layer 21) are also shown. Here, the unit of thickness is explained using Å (angstroms), but these may be converted to nm (nanometers) as appropriate. Note that a layer containing a certain material is referred to by adding the name of the layer to the name of the material. For example, a layer containing Ta is referred to as a Ta layer.

[0102] The lower electrode layer 5 has a laminated structure including a Ta layer and a Ru layer. The Ta layer has a thickness of 50 Å. The Ru layer has a thickness of 100 Å.

[0103] The magnetization fixed layer 2 includes a fixed layer 21 and a reference layer 22 stacked in this order in the positive direction of the Z axis. The fixed layer 21 has a stacked structure including a Co layer, an Ir layer, a Co layer, and a PtCo layer. The thicknesses of the layers are, for example, Co 6 Å / Ir 5 Å / Co 6 Å. The reference layer 22 is a CoFeB layer with a thickness of 10 Å.

[0104] The memory layer 3 includes a barrier layer 30, a first region 31, a spacer region 33, a second region 32, and a barrier layer 34, which are stacked in this order in the positive direction of the Z axis. The barrier layer 30 of the memory layer 3 is an MgFeO layer having a thickness of 20 Å. The first region 31 is a CoFeB layer having a thickness of 6 Å (which may be any thickness between 6 Å and 8 Å). The spacer region 33 is a Mo layer having a thickness of 2.5 Å. The second region 32 is an FeNiMn layer having a thickness of 10 Å (which may be any thickness between 7 Å and 10 Å). The barrier layer 34 is an MgO layer having a thickness of 6 Å.

[0105] The cap layer 6 has a laminated structure including a Ta layer and a Ru layer. The Ta layer has a thickness of 30 Å. The Ru layer has a thickness of 100 Å.

[0106] The magnetic memory element 1 was fabricated by depositing the materials for each of the layers described above on a Si substrate with a circuit, and then performing element processing processes such as photolithography patterning, hard mask formation, ion milling, electrode pad formation, etc. The magnetic memory element 1 has a circular shape with a diameter of approximately 80 nm when viewed in a plan view (when viewed in the Z-axis direction).

[0107] The RH loop characteristics obtained by the magnetic field tester are shown in Figure 22B. Graph line C1 shows the RH loop characteristics when the voltage V is +10 mV. Graph line C2 shows the RH loop characteristics when the voltage V is +1000 mV. Graph line C3 shows the RH loop characteristics when the voltage V is -1000 mV.

[0108] As explained above, a hysteresis shift in the RH loop characteristics in response to the applied voltage was confirmed. When the magnetic field H=0, the magnetic memory element 1 has a low resistance value when a positive voltage (voltage V>0) is applied. When a negative voltage (voltage V<0) is applied, the magnetic memory element 1 has a high resistance value.

[0109] 22C shows the IV characteristics. As indicated by the arrow AR1, when a positive voltage V, for example, about +300 mV, is applied, the resistance value switches from a high resistance value to a low resistance value, and the current value I increases sharply. The magnitude of the current required for magnetization reversal (reversal current) is about 5.5 μA. Furthermore, as indicated by the arrow AR2, when a negative voltage V, for example, about −300 mV, is applied, the resistance value switches from a low resistance value to a high resistance value, and the current value I decreases sharply. The magnitude of the reversal current is about 14 μA.

[0110] <Example 2> Figure 23 is a diagram showing Example 2. Only the main differences from Example 1 will be described. As shown in Figure 23A, the storage layer 3 of the magnetic memory element 1 includes a barrier layer 30, a second region 32, a spacer region 33, a second region 32, and a barrier layer 34, which are stacked in this order in the positive direction of the Z axis. The second region 32 is an FeCoMn layer having a thickness of 10 Å (or any thickness between 7 Å and 10 Å).

[0111] 23B shows the RH loop characteristics. Graph line C1 shows the RH loop characteristics when the voltage V is +10 mV. Graph line C2 shows the RH loop characteristics when the voltage V is +1200 mV. Graph line C3 shows the RH loop characteristics when the voltage V is -1200 mV.

[0112] As explained above, a hysteresis shift in the RH loop characteristics in response to the applied voltage was confirmed. When the magnetic field H=0, the magnetic memory element 1 has a low resistance value when a positive voltage (voltage V>0) is applied. When a negative voltage (voltage V<0) is applied, the magnetic memory element 1 has a high resistance value.

[0113] 23C shows the IV characteristics. As indicated by the arrow AR1, when a positive voltage V, for example, about +1200 mV, is applied, the resistance value switches from a high resistance value to a low resistance value, and the current value I increases sharply. The magnitude of the current required for magnetization reversal (reversal current) is about 30 μA. Furthermore, as indicated by the arrow AR2, when a negative voltage V, for example, about −800 mV, is applied, the resistance value switches from a low resistance value to a high resistance value, and the current value I decreases sharply. The magnitude of the reversal current is about 48 μA.

[0114] <Comparative Example> Fig. 24 is a diagram showing a comparative example. As shown in Fig. 24A, the magnetic memory element 1E according to the comparative example differs from Example 1 (Fig. 22) in that the memory layer 3 does not include the second region 32 and the spacer region 33 is a Mo layer having a thickness of 3 Å.

[0115] 24B shows the RH loop characteristics. Graph line C1 shows the RH loop characteristics when voltage V = +10 mV. Graph line C2 shows the RH loop characteristics when voltage V = +1200 mV. Graph line C3 shows the RH loop characteristics when voltage V = -1200 mV. As shown by graph line C2, when a positive voltage (voltage V > 0) is applied, the coercive force increases. As shown by graph line C3, when a negative voltage (voltage V < 0) is applied, the coercive force decreases. However, unlike Example 1, there is almost no hysteresis shift in the RH loop characteristics, and therefore there is almost no magnetization reversal due to voltage application.

[0116] The various laminated structures, materials, etc. described in the previous embodiments may be applied to the above-mentioned Example 1 and Example 2 (FIGS. 22 and 23). Some examples will be described as modified examples.

[0117] <Modifications 11 and 12> FIG. 25 shows Modifications 11 and 12. For simplicity, only the layers of the storage layer 3 of the magnetic memory element 1 and the fixed layer 21 of the magnetization fixed layer 2 are shown. The magnetic memory element 1 according to Modification 11 differs from the configuration of the previously described Example 2 ( FIG. 23 ) in that the barrier layer 30 of the storage layer 3 is an MnMgO layer. The magnetic memory element 1 according to Modification 12 differs from the configuration of Example 2 ( FIG. 23 ) in that the barrier layer 30 of the storage layer 3 is an MnMgO layer and the second region 32 is an FeCo layer. The second region 32 may be formed so that excess Mn diffuses from the barrier layer 30 into the second region 32.

[0118] <Example 3, Modified Example 21, Modified Example 22> Figure 26 is a diagram showing Example 3, Modified Example 21, and Modified Example 22. The magnetic memory element 1 according to Example 3 differs from the configuration of Example 2 (Figure 23) in that the positions of the first region 31 and the second region 32 are reversed. The magnetic memory element 1 according to Modified Example 21 differs from Example 3 in that the barrier layer 30 is an MgO layer and the barrier layer 34 is an FeMgO layer. In the magnetic memory element 1 according to Modified Example 22, both the barrier layer 30 and the barrier layer 34 are FeMgO layers.

[0119] The materials for the barrier layer 30 and the barrier layer 34 are as described in the previous embodiment. As described above, an additive element such as Fe, Co, or Mn may be added to MgO. An additive element other than Fe, Co, or Mn may also be added. Examples of other additive elements include Hf and Zr. The description will also refer to FIG. 27 .

[0120] <Modified Examples 23 and 24> Figure 27 is a diagram showing modified examples 23 and 24. The magnetic memory element 1 according to modified example 23 differs from the configuration of example 2 (Figure 23) in that the barrier layer 34 is an Hf-MgO layer, and also differs in this example in that the barrier layer 30 is an MgO layer. The magnetic memory element 1 according to modified example 24 differs from the configuration of example 2 (Figure 23) in that the barrier layer 34 is an HfZrO layer.

[0121] As mentioned above, the barrier layer 30 may be an oxide of, for example, Sc, Y, La, Ce, Pr, Nd, Pm, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb, Lu, etc. Some specific examples will be described with reference to FIG.

[0122] <Modifications 13, 14, and 25> FIG. 28 shows Modifications 13, 14, and 25. The magnetic memory element 1 according to Modification 13 differs from the configuration of Example 2 (FIG. 23) in that the barrier layer 34 is a Gd2O3 layer. The magnetic memory element 1 according to Modification 14 differs from the configuration of Example 2 (FIG. 23) in that the barrier layer 34 is a YO3 layer, and also differs in this example in that the second region 32 is a CoFe layer. The magnetic memory element 1 according to Modification 25 differs from the configuration of Example 3 (FIG. 26) in that the barrier layer 34 is a La2O3 layer. As shown in Non-Patent Document 6, it is expected that the magnetization reversal of the memory layer 3 is assisted by the application of a voltage via the barrier layer 34.

[0123] As mentioned above, antiferromagnetic oxides such as NiO, Cr2O3, CoO, Fe2O3, and Mn2O3 may be used as the material for the barrier layer 34. An example will be described with reference to FIG.

[0124] <Modified Example 15> Fig. 29 is a diagram showing modified example 15. The magnetic memory element 1 according to modified example 15 differs from the configuration of example 2 (Fig. 23) in that the barrier layer 34 is a Cr2O3 layer, and also differs in this example in that the barrier layer 30 is an MnMgO layer.

[0125] <Experimental Examples of Materials> As further study results, experimental examples of materials for the second region 32 will be described with reference to FIGS. 30 and 31. FIG.

[0126] 30 shows experimental examples in which the material of the second region 32 is FeNiMn. In a stacked structure similar to that of Example 2 (FIG. 23), the measured values ​​of the reversal voltage (the magnitude of the voltage V required for magnetization reversal) and the TMR ratio when the composition ratio of the material of the second region 32 of the memory layer 3 is changed are shown as experimental examples 101 to 116.

[0127] FIG. 30A shows a table of the measurement results of Experimental Examples 101 to 116. Among the Experimental Examples, those in which the intended effect was confirmed are listed as Examples, and the others are listed as Comparative Examples. The experimental results of the Examples can define the composition range of the material for the second region 32 of the memory layer 3 of the magnetic memory element 1 according to the embodiment. FIG. 30B shows a ternary map of the composition range. Plots corresponding to each Experimental Example are shown on the map.

[0128] Experimental Examples 101 to 105 confirm the composition dependency when the FE composition ratio is set to 0 at% and the NiMn composition ratio is changed from 20 at% to 85 at%. The TMR ratio is good, at 100% or more, up to a Ni composition ratio of less than 80 at%, but when the Ni composition ratio becomes too large, such as 85 at%, the TMR ratio drops to 62%. Therefore, it is desirable for the Ni composition ratio to be less than 80 at%.

[0129] Experimental Examples 107 to 112 confirm the composition dependency when the Ni composition ratio is set to 0 at% and the FeMn composition ratio is changed from 3 at% to 85 at%. In Experimental Example 107, where the Mn composition ratio is low at 3 at%, the reversal voltage increases to 1.8 V, while in Experimental Example 112, where the Mn composition ratio is too high at 85 at%, the reversal voltage is sufficiently low and favorable, but the TMR ratio drops to 65%, so a Mn composition ratio of 5 at% to 80 at% is more preferable.

[0130] Experimental Examples 108, 105, and 106 confirm the composition dependency when the composition ratio of Fe and Ni is changed with the Mn composition ratio set to 5 at %. In Experimental Example 106, where the Ni composition ratio is 40 at %, the reversal voltage tends to increase to 1.8 V. Therefore, when the Mn composition ratio is 5 at %, the Ni composition ratio is preferably up to 30 at %.

[0131] From the above-mentioned tendency, the preferable composition range of FeNiMn is the range shown by hatching in the ternary map of Fig. 30(B). This range is the same as that shown in Fig. 3 described above, and can coincide with the composition range in which an antiferromagnetic phase or a ferrimagnetic phase is obtained as shown in Non-Patent Document 1.

[0132] <Experimental Examples 201 to 216> Fig. 31 shows experimental examples in which the material of the second region 32 is FeCoMn. Fig. 31A shows a table of the measurement results of Experimental Examples 201 to 216. Fig. 31B shows a ternary map of the composition range.

[0133] Experimental Examples 201 to 204 confirm the composition dependency when the Fe composition ratio is set to 0 at% and the CoMn composition ratio is changed from 20 at% to 70 at%. In the range of Co greater than 50 at%, the reversal voltage increases to 1.8 V or more. This is thought to correspond to the fact that in a CoMn system, when the Mn composition ratio decreases, it becomes difficult to obtain an antiferromagnetic phase in CoMn, and it is desirable that the Co composition ratio be less than 50 at%.

[0134] Experimental Examples 205 to 210 confirm the composition dependency when the Ni composition ratio is set to 0 at% and the FeMn composition ratio is changed from 3 at% to 85 at%. In Experimental Example 107, where the Mn composition ratio is low at 3 at%, the reversal voltage increases to 1.8 V, while in Experimental Example 112, where the Mn composition ratio is too high at 85 at%, the reversal voltage is sufficiently low and favorable, but the TMR ratio drops to 65%, so a Mn composition ratio of 5 at% to 80 at% is more preferable.

[0135] Experimental Examples 209 and 210 confirm the composition dependency when the composition ratio of Fe and Ni is changed with the Mn composition ratio set to 5 at %. Even when the Co composition ratio is 50 at %, the reversal voltage is 1.55 V, which is relatively good.

[0136] Experimental Examples 201, 208, and 212 to 215 confirm the composition dependency when the Mn composition ratio is set to 25 at% and the CoFe composition ratio is changed. The larger the Co composition ratio, the higher the reversal voltage tends to be, with Experimental Example 201, where Co is 75 at%, and Experimental Example 212, where Co is 60 at%, showing high reversal voltages of 1.8 V and 1.83 V, respectively. A Co composition ratio of 50 at% or less is preferable because it significantly reduces the threshold voltage.

[0137] From the above-mentioned tendency, the preferable composition range of FeNiMn is the range shown by hatching in the ternary map of Fig. 31(B). This range is the same as that shown in Fig. 6 described above, and can coincide with the composition range in which an antiferromagnetic phase or a ferrimagnetic phase is obtained as shown in Non-Patent Document 1.

[0138] <Other Modified Examples> The range of composition in which an antiferromagnetic phase or a ferrimagnetic phase is obtained roughly coincides with the range of composition in which the effect of reducing the magnetization reversal voltage is obtained as the material of the second region 32. Therefore, it is considered that the same effect can be obtained, for example, with the ranges of composition shown in Figures 4, 5, and 7 to 9 described above.

[0139] <Modified Examples Regarding Spacer Region 33> Several modified examples regarding the spacer region 33 will be described. In the previous Example 2 (FIG. 23), an example was described in which the spacer region 33 contains Mo. Several examples in which materials other than Mo are used will be described as Modified Examples 41 to 45.

[0140] 32 is a diagram showing modified examples 41 to 45. For simplicity, only the first region 31, the second region 32, and the spacer region 33 of the memory layer 3 of the magnetic memory element 1 are shown.

[0141] In the magnetic memory elements 1 according to modified examples 41 to 43, the memory layer 3 includes a second region 32, a spacer region 33, and a first region 31, which are stacked in this order in the positive direction of the Z axis. In the magnetic memory element 1 according to modified example 41, the spacer region 33 of the memory layer 3 is a W layer having a thickness of 2.5 Å. In the magnetic memory element 1 according to modified example 42, the spacer region 33 of the memory layer 3 is a Ru layer having a thickness of 2.5 Å. In the magnetic memory element 1 according to modified example 43, the spacer region 33 of the memory layer 3 is a Ta layer having a thickness of 2.5 Å.

[0142] In the magnetic memory elements 1 according to modified examples 44 and 45, the memory layer 3 includes a first region 31, a spacer region 33, and a second region 32, which are stacked in this order in the positive direction of the Z axis. In the magnetic memory element 1 according to modified example 44, the spacer region 33 of the memory layer 3 is an Ir layer having a thickness of 2.5 Å. In the magnetic memory element 1 according to modified example 45, the spacer region 33 of the memory layer 3 is a W layer having a thickness of 2.5 Å.

[0143] It is also possible to have a configuration without the spacer region 33. This will be described with reference to FIG.

[0144] <Modified Examples 46 and 47> Figure 33 is a diagram showing modified examples 46 and 47. In the magnetic memory element 1 according to modified example 46, the memory layer 3 includes a second region 32 and a first region 31 that are stacked in this order in the positive direction of the Z-axis. There is no spacer region between the second region 32 and the first region 31. In the magnetic memory element 1 according to modified example 47, the memory layer 3 includes a first region 31 and a second region 32 that are stacked in this order in the positive direction of the Z-axis. There is no spacer region between the first region 31 and the second region 32.

[0145] <Modified Example of Top-Pin Type> As previously described with reference to Fig. 1, the magnetic memory element 1 may have a top-pin type configuration. This will be described with reference to Fig. 34 .

[0146] <Modified Examples 51 and 52> Figure 34 is a diagram showing modified examples 51 and 52. The magnetic memory element 1 according to modified example 51 is obtained by changing the configuration of example 2 (Figure 23) to a top-pin type. The magnetic memory element 1 according to modified example 52 is obtained by changing the configuration of example 3 (Figure 26) to a top-pin type. In either configuration, a lower electrode layer 5, a memory layer 3, a magnetization fixed layer 2, and a Cap layer 6 are stacked in this order in the positive direction of the Z axis.

[0147] In the magnetic memory element 1 according to the modified example 51, the storage layer 3 includes a barrier layer 34, a second region 32, a spacer region 33, a first region 31, and a barrier layer 30, which are stacked in this order in the positive direction of the Z axis. The barrier layer 34 is an MgO layer. The second region 32 is an FeCoMn layer having a thickness of 10 Å (which may be any thickness between 7 Å and 10 Å). The spacer region 33 is an Mo layer having a thickness of 2.5 Å. The first region 31 is a CoFeB layer having a thickness of 6 Å. The barrier layer 30 is an MgFeO layer.

[0148] In the magnetic memory element 1 according to the fifty-second modified example, the storage layer 3 includes a barrier layer 34, a first region 31, a spacer region 33, a second region 32, and a barrier layer 30, which are stacked in this order in the positive direction of the Z axis. The barrier layer 34 is an MgO layer. The first region 31 is a CoFeB layer having a thickness of any desired value between 6 Å and 8 Å. The spacer region 33 is an Mo layer having a thickness of 2.5 Å. The second region 32 is an FeCoMn layer having a thickness of any desired value between 7 Å and 10 Å.

[0149] 20 and 21, the magnetic memory element 1 may have a dual MTJ structure or an SAF configuration. This will be described with reference to FIG.

[0150] <Modified Embodiments 61 and 62> FIG. 35 is a diagram showing modified embodiments 61 and 62. In FIG.

[0151] The magnetic memory element 1 according to the modified example 61 is an example of the configuration shown in FIG. 20A described above. A magnetization fixed layer 2, a memory layer 3, a ferromagnetic layer 4, and a cap layer 6 are stacked in this order in the positive direction of the Z-axis. The magnetization fixed layer 2 and the ferromagnetic layer 4 are CoFeB layers. The memory layer 3 includes a barrier layer 30, a second region 32, a spacer region 33, a first region 31, and a barrier layer 34 stacked in this order in the positive direction of the Z-axis. The barrier layer 30 is an FeMgO layer. The second region 32 is an FeCoMn layer. The spacer region 33 is an Mo layer. The first region 31 is a CoFeB layer. The barrier layer 34 is an MgO layer. Two barrier layers, the barrier layer 30 and the barrier layer 34, are formed, and the barrier layer 34 is provided between the two ferromagnetic layers, the first region 31 and the ferromagnetic layer 4. A dual MTJ structure is obtained in which both the barrier layer 30 and the barrier layer 34 function as an MTJ.

[0152] The magnetic memory element 1 according to modified example 62 is an example of the configuration shown in FIG. 21A described above. A magnetization fixed layer 2, a memory layer 3, a ferromagnetic layer 4, and a cap layer 6 are stacked in this order in the positive direction of the Z axis. The magnetization fixed layer 2 and the ferromagnetic layer 4 are CoFeB layers. The memory layer 3 includes a barrier layer 30, a second region 32, a spacer region 33, a first region 31, and a spacer layer 35 stacked in this order in the positive direction of the Z axis. The barrier layer 30 is an FeMgO layer. The second region 32 is an FeCoMn layer. The spacer region 33 is an Mo layer. The first region 31 is a CoFeB layer. A synthetic antiferromagnetic film (SAF) is obtained in which the memory layer 3 is antiferromagnetically coupled via the spacer layer 35.

[0153] <Summary> The magnetic memory element 1 according to the embodiment described above is specified, for example, as follows. As described with reference to Figures 1 to 9, 19 to 23, and 25 to 35, the magnetic memory element 1 includes a magnetization fixed layer 2 in which the magnetization direction is fixed, and a memory layer 3 in which the magnetization direction is reversible. The memory layer 3 includes a first region 31 containing a ferromagnetic material and a second region 32 containing an antiferromagnetic material or a ferrimagnetic material.

[0154] According to the magnetic memory element 1, in the memory layer 3, the magnetization reversal of the first region 31 is assisted by the second region 32, and the power consumption required for the magnetization reversal is reduced accordingly. Therefore, the power consumption of the magnetic memory element 1 can be suppressed.

[0155] 1 and 2 , the first region 31 and the second region 32 may be arranged in a stacked manner. Alternatively, the memory layer 3 may include a plurality of first regions 31 and a plurality of second regions 32 that are distributed. The memory layer 3 may include a spacer region 33 that includes a nonmagnetic material and is provided between the first region 31 and the second region 32. The first region 31 and the second region 32 may be provided so as to be magnetically coupled to each other. For example, the first region 31 and the second region 32 can be arranged in the memory layer 3 in various ways like this.

[0156] As described with reference to FIGS. 1 and 2 , the first region 31 may include at least one of Co, Fe, Ni, Mn, Al, B, P, C, Zr, Hf, Ta, and Nb. The first region 31 may include CoFeB. In this case, the Fe composition ratio in CoFeB may be greater than the Co composition ratio. The B composition ratio in CoFeB may be 40 at% or less. The first region 31 may have a thickness of 0.1 nm or more and 1.5 nm or less. For example, a region configured in this manner can be used as the first region 31.

[0157] As described with reference to Figures 1 and 2, the second region 32 may include at least one of Mn, Cr, Ir, Pt, Pd, Ni, Sn, Fe, Ge, Co, Ga, and Si. The second region 32 may include a chalcogenide, such as CuMnAs or MnPS3. The second region 32 may include an oxide, such as NiO, Cr2O3, CoO, Fe2O3, or Mn2O3. The second region 32 may include an antiferromagnetic alloy or a ferrimagnetic alloy. The alloy may include FeNiMn, CrNiMn, FeCrMn, FeCoMn, CoNiMn, FeNiCr, GaNiMn, CoPtMn, FePtMn, FeMn, NiMn, FeNi, PtMn, PdMn, or CoGe. The second region 32 may have a thickness of 0.1 nm or more and 5 nm or less. For example, a region configured in this manner can be used as the second region 32.

[0158] As described with reference to FIG. 3 and the like, the alloy of the second region 32 is an Fe alloy having a composition ratio of Fe, Ni, and Mn of x, y, and z. ｘ Ni ｙ Mn ｚ The alloy may have a composition range of 0 at%<x≦95 at%; 0 at%<y≦80 at%; 5 at%≦z≦80 at%. An antiferromagnetic phase or a ferrimagnetic phase is obtained. An antiferromagnetic phase or a ferrimagnetic phase as shown in Non-Patent Document 1 is obtained.

[0159] As described with reference to FIG. 4 and the like, the alloy of the second region 32 is a Cr alloy having a composition ratio of Cr, Ni, and Mn of x, y, and z. ｘ Ni ｙ Mn ｚ The alloy may have a composition range of 0 at%<x≦65 at%; 0 at%<y≦75 at%; 0 at%<z≦80 at%. An antiferromagnetic phase or a ferrimagnetic phase as shown in Non-Patent Document 1 is obtained.

[0160] As described with reference to FIG. 5 and the like, the alloy of the second region 32 is an Fe alloy having a composition ratio of Fe, Cr, and Mn of x, y, and z. ｘ Cr ｙ Mn ｚThe alloy may have a composition range of 0 at%<x≦95 at%; 0 at%<y≦70 at%; 5 at%≦z≦80 at%. An antiferromagnetic phase or a ferrimagnetic phase as shown in Non-Patent Document 1 is obtained.

[0161] As described with reference to FIG. 6 and the like, the alloy of the second region 32 is an Fe alloy having a composition ratio of Fe, Co, and Mn of x, y, and z. ｘ Co ｙ Mn ｚ The alloy may have the composition ranges of 0 at%<x≦95 at%; 0 at%<y≦50 at%; and 5 at%≦z≦80 at%. An antiferromagnetic phase as shown in Non-Patent Document 2 is obtained.

[0162] As described with reference to FIG. 7 and the like, the second region 32 is a Ga-based semiconductor having a composition ratio of Ga, Ni, and Mn of x, y, and z. ｘ Ni ｙ Mn ｚ The alloy may have the composition ranges of 0 at%<x≦50 at%, 5 at%≦y≦80 at%, and 5 at%≦z≦90 at%, resulting in a ferrimagnetic phase as shown in Non-Patent Document 3.

[0163] As described with reference to FIG. 8 and the like, the second region 32 is an Fe-based alloy having a composition ratio of Fe, Ni, and Cr of x, y, and z. ｘ Ni ｙ Cr ｚ The alloy may have the composition ranges of 60 at%≦x≦82 at%, 15 at%≦y≦40 at%, and 10 at%≦z≦35 at%, resulting in a ferrimagnetic phase as shown in Non-Patent Document 4.

[0164] As described with reference to FIG. 9 and the like, the second region 32 is a Co, Ge, Mn alloy having a composition ratio of x, y, and z. ｘ , Ge ｙ , Mn ｚ The alloy may have the composition ranges of 0 at%<x≦20 at%, 0 at%<y≦95 at%, and 5 at%≦z<100 at%, and an antiferromagnetic phase as shown in Non-Patent Document 5 is obtained.

[0165] As described with reference to FIG. 2 and other figures, the spacer region 33 may include at least one of Ta, Ru, Ir, W, Mo, Rh, Re, Nb, Cu, Cr, V, TiN, TaN, and WN. The spacer region 33 is provided between the first region 31 and the second region 32 so that the first region 31 and the second region 32 are magnetically coupled to each other, and the magnetization of the second region 32 may affect the magnetization of the first region 31 via the spacer region 33. The spacer region 33 may have a thickness of 0.1 nm to 1.5 nm. For example, by providing such a spacer region 33, the first region 31 and the second region 32 can be magnetically coupled to each other, thereby assisting the magnetization reversal in the first region 31.

[0166] As described with reference to FIG. 2 and the like, the memory layer 3 includes a barrier layer 30 provided between the first region 31, the second region 32, and the magnetization fixed layer 2. The barrier layer may include an oxide of at least one of Mg, Ca, Li, Si, Al, Sr, Zr, Hf, Ti, Zn, Mo, Cu, Ba, Ta, W, V, Ni, Co, Mn, Cr, Fe, B, and C. The barrier layer 30 may include an oxide of at least one of Sc, Y, La, Ce, Pr, Nd, Pm, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb, and Lu. The barrier layer 30 may include MgO, and may further include Fe, Co, or Mn in addition to MgO. In this case, the amount of Fe, Co, or Mn added may be 20 at % or less. For example, by providing such a barrier layer 30 between the first region 31 and the second region 32 and the magnetization fixed layer 2, the TMR effect can be obtained.

[0167] 19 and 20 , the memory layer 3 may include a barrier layer 34 provided on the opposite side of the magnetization fixed layer 2 with the first region 31 and the second region 32 sandwiched therebetween. The material of the barrier layer 34 may be the same as the material of the barrier layer 30. That is, the barrier layer 34 may include at least one of Mg, Ca, Li, Si, Al, Sr, Zr, Hf, Ti, Zn, Mo, Cu, Ba, Ta, W, V, Ni, Co, Mn, Cr, Fe, B, and C. The barrier layer 34 may include an oxide of at least one of Sc, Y, La, Ce, Pr, Nd, Pm, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb, and Lu. The barrier layer 34 may include MgO, and may further include Fe, Co, or Mn in addition to MgO. In this case, the amount of Fe, Co, or Mn added may be 20 at % or less. The barrier layer 34 may also contain an antiferromagnetic oxide, such as NiO, Cr2O3, CoO, Fe2O3, or Mn2O3. Providing such a barrier layer 34 separately from the barrier layer 30 can improve heat resistance and magnetization reversal efficiency. The storage layer 3 may also include a ferromagnetic layer 4 provided on the opposite side of the barrier layer 34 from the first region 31 and the second region 32. This provides a magnetic memory element 1 with a dual MTJ structure.

[0168] 1 and the like, the magnetization fixed layer 2 includes a ferromagnetic layer including a reference layer 22 whose magnetization direction is fixed, and the reference layer 22 may include at least one of Fe, Co, Ni, Mn, and B. The magnetization fixed layer 2 may include a fixed layer 21 that fixes the magnetization direction of the reference layer 22. For example, a layer including such multiple layers can be used as the magnetization fixed layer 2.

[0169] 21 and other drawings, the memory layer 3 includes a spacer layer 35 provided on the opposite side of the magnetization fixed layer 2 with the first region 31 and the second region 32 sandwiched therebetween, and a ferromagnetic layer 4 provided on the opposite side of the spacer layer 35 with the first region 31 and the second region 32 sandwiched therebetween. This provides a magnetic memory element 1 with a synthetic ferrimagnetic structure (SAF).

[0170] 10 to 12, the magnetization direction of the memory layer 3 may be reversed depending on the positive or negative of the voltage V applied to the magnetic memory element 1. This allows magnetization reversal to be performed, rather than just changing the coercive force by applying a voltage as in the case of VCMA, for example.

[0171] 2. Storage Device Embodiment The magnetic memory element 1 can be used as a component of a storage device. That is, the magnetic memory element 1 has a resistance value corresponding to the magnetization direction of the storage layer 3. In a parallel state in which the magnetization direction of the storage layer 3 and the magnetization direction of the magnetization fixed layer 2 are the same, the magnetic memory element 1 has a low resistance value. In an antiparallel state in which the magnetization directions are opposite, the magnetic memory element 1 has a high resistance value. The two types of resistance values ​​correspond to bit data "0" and "1". Data can be written to the magnetic memory element 1 by controlling the magnetic memory element 1 to have a low resistance value or a high resistance value. Furthermore, data can be read from the magnetic memory element 1 by detecting the resistance value of the magnetic memory element 1.

[0172] One of the features of the magnetic memory element 1 is the principle of writing data to the magnetic memory element 1. Although some of the explanation will be repeated, it will be explained again with reference to FIG.

[0173] 36 is a diagram showing the principle of writing data to a magnetic memory element 1. As shown in (A) of FIG. 36, when a positive voltage (voltage V>0) having a certain magnitude and pulse length (pulse width) is applied to the magnetic memory element 1, the magnetization direction of the memory layer 3 of the magnetic memory element 1 is reversed so that the resistance value changes from a low resistance value to a high resistance value. Conversely, as shown in (B) of FIG. 36, when a positive voltage (voltage V>0) having a certain magnitude and pulse length is applied to the magnetic memory element 1, the magnetization direction of the memory layer 3 of the magnetic memory element 1 is reversed so that the resistance value changes from a high resistance value to a low resistance value.

[0174] Based on the above principle, a storage device is provided that includes an element (such as a control circuit) for writing data to the magnetic memory element 1 and reading data from the magnetic memory element 1. Several embodiments will be described.

[0175] 2.1 First Embodiment FIG. 37 is a diagram showing an example of a schematic configuration of a memory device 7 according to the first embodiment. The memory device 7 includes a memory array 70. The memory array 70 includes a plurality of memory cells 71 arranged two-dimensionally. The memory cells 71 include the magnetic memory elements 1 described above, and in this example, further include selection transistors 72. Bit lines BL, source lines SL, and word lines WL are indicated by symbols as signal lines / control lines for accessing the memory cells 71 for data reading and writing, etc. The word lines WL, bit lines BL, and source lines SL extend so as to intersect (for example, orthogonal to) each other.

[0176] The memory cell 71 is a unit for reading and writing data, and in this sense can be regarded as the same as the magnetic memory element 1. Within the scope of no contradiction, the memory cell 71 and the magnetic memory element 1 may be interpreted as appropriate.

[0177] The memory device 7 includes various peripheral circuits / elements provided around the memory cells 71. The peripheral circuits / elements shown in FIG. 37 include an I / O 730, a control circuit 731, a voltage generation circuit 732, a write circuit 733, a read circuit 734, a bit / source line address decoder 735, a bit / source line control circuit 736, a word line address decoder 737, a word line control circuit 738, and a sense amplifier 739. The bit / source line control circuit 736 is connected to the bit line BL and the source line SL. The word line control circuit 738 is connected to the word line WL. The sense amplifier 739 is connected to the bit line BL and the source line SL.

[0178] The basic operation of a storage device having the above configuration will be understood by those skilled in the art, and will be briefly explained below. Note that the configuration is not limited to that shown in Figure 37, and various known configurations may be adopted.

[0179] Commands relating to data write and data read, addresses of memory cells 71 to be accessed, write data, read data, etc. are exchanged between elements external to the storage device 7 and a control circuit 731 of the storage device 7 via the I / O 730. An example of an element external to the storage device 7 is a host computer such as a CPU.

[0180] The control circuit 731 controls other peripheral circuits / elements in response to commands. It can be said that the entire storage device 7 except for the I / O 730 is substantially controlled by the control circuit 731. The control by the control circuit 731 includes control of writing data to the magnetic memory element 1, control of reading data from the magnetic memory element 1, etc. The control circuit 731 is configured to include, for example, a state machine, etc.

[0181] The voltage generation circuit 732 generates a pulse voltage (data write voltage) used for writing data and a voltage (data read voltage) used for reading data. The data read voltage is lower than the data write voltage. Voltages required for circuit operation may be supplied separately.

[0182] The write circuit 733 uses the voltage generated by the voltage generating circuit 732 to control the pulse of the write voltage.

[0183] The read circuit 734 uses the voltage generated by the voltage generating circuit 732 to control the pulse of the read voltage.

[0184] The bit / source line address decoder 735 obtains the addresses of the bit lines BL and source lines SL corresponding to the addresses received at the I / O 730 described above.

[0185] The bit / source line control circuit 736 selects and controls the bit line BL and source line SL corresponding to the address of the word line address decoder 737. Writing data to the memory cell 71 using the data write voltage generated by the voltage generation circuit 732 and pulse-controlled by the read circuit 734, and reading data from the memory cell 71 using the data read voltage generated by the voltage generation circuit 732 and pulse-controlled by the read circuit 734 are performed via the bit / source line control circuit 736, etc.

[0186] The word line address decoder 737 obtains the address of the word line WL corresponding to the address received at the I / O 730 described above.

[0187] The word line control circuit 738 selects and controls the word line WL corresponding to the address of the word line address decoder 737 .

[0188] The sense amplifier 739 detects the data read from the memory cell 71 , specifically the resistance value of the magnetic memory element 1 .

[0189] The above-described control circuit 731 to sense amplifier 739 control writing of data to the magnetic memory element 1 and reading of data from the magnetic memory element 1. Unless otherwise specified, it may be understood that the control unit is the control circuit 731.

[0190] The memory cell 71 will now be described again. The magnetic memory element 1 of the memory cell 71 is electrically connected between a bit line BL and a source line SL. In this example, one end of the magnetic memory element 1 is connected to the bit line BL, and the other end is connected to the source line SL via a selection transistor 72.

[0191] The selection transistor 72 is an example of a selection element for selecting a memory cell 71 from among the multiple memory cells 71 to which data is to be written or read, and more specifically, is a FET switch. The function of the selection transistor 72 can also be called a selector function. The FET constituting the selection transistor 72 may be a MOSFET, and the MOSFET may be an N-type MOSFET or a P-type MOSFET. Here, the FET is assumed to be an N-type MOSFET.

[0192] The selection transistor 72 switches between a state that enables data access (reading and writing data) to the corresponding magnetic memory element 1 and a state that prevents data access. Specifically, in the example shown in FIG. 37 , one of the source and drain of the selection transistor 72 is connected to the magnetic memory element 1, and the other is connected to the source line SL. The gate of the selection transistor 72 is connected to the word line WL. When the selection transistor 72 is turned on (conductive state), data access to the magnetic memory element 1 to which the selection transistor 72 is connected becomes possible. When the selection transistor 72 is turned off (non-conductive state), data access to the magnetic memory element 1 to which the selection transistor 72 is connected is prevented.

[0193] A voltage corresponding to the potential difference between the bit line BL and the source line SL is applied to the magnetic memory element 1 in the memory cell 71, and this voltage corresponds to the voltage V described above. One of a positive voltage (voltage V>0) and a negative voltage (voltage V<0) is applied to the magnetic memory element 1 so that the magnetic memory element 1 has one of a low resistance value and a high resistance value. Furthermore, the other of a positive voltage and a negative voltage is applied to the magnetic memory element 1 so that the magnetic memory element 1 has the other of a low resistance value and a high resistance value. In the example shown in Figure 37, the voltage V applied to the magnetic memory element 1 is represented by the potential of the bit line BL when the source line SL is used as the reference potential.

[0194] When the potential of the bit line BL is higher than the potential of the source line SL, a positive voltage (V>0) is applied to the magnetic memory element 1. As previously described with reference to FIG.

[0195] When the potential of the source line SL is higher than the potential of the bit line BL, in other words, when the potential of the bit line BL is lower than the potential of the source line SL, a negative voltage (V<0) is applied to the magnetic memory element 1. As previously described with reference to FIG. 37B, the magnetic memory element 1 has a high resistance value.

[0196] The absolute values ​​(|V|) of the positive and negative voltages may be the same or different. By making one voltage smaller than the other, the possibility of reducing power consumption is further increased.

[0197] 37 may be applied to the magnetic memory element 1 in the opposite direction, in which case the potentials of the bit line BL and the source line SL will have the opposite relationship to that described above. However, hereinafter, unless otherwise specified, it is assumed that the voltage V in the direction shown in FIG. 37 is applied to the magnetic memory element 1.

[0198] The names of the bit lines BL and source lines SL, the circuit design of the memory device 7, etc. are not limited to the examples described here, and various other known names, circuit designs, etc. may be used.

[0199] The operations relating to data writing and data reading in the memory device 7 will be described with reference to Figure 38 onwards. The operations are controlled, for example, by a state machine included in the control circuit 731, and more particularly by a write circuit 733 and a read circuit 734 that operate under the control of the control circuit 731, as well as a bit / source line control circuit 736 and a word line control circuit 738.

[0200] 38 is a flowchart showing an example of a process (data write method) executed when writing data. This flow starts in response to input of a write command and write data. It is assumed that the memory cell 71 including the magnetic memory element 1 to which data is to be written has been selected, and the corresponding selection transistor 72 is turned on.

[0201] When the magnetic memory element 1 is to have a high resistance value (step S1: Yes), the source line SL of the bit line BL and the source line SL is set to a high potential (step S2), and a voltage is set to make the resistance value of the magnetic memory element 1 a high resistance value (step S3). That is, the voltage applied to the magnetic memory element 1 is set to a positive voltage (voltage V>0).

[0202] On the other hand, if the magnetic memory element 1 is to have the resistance value (step S1: No), the bit line BL of the bit line BL and the source line SL is set to a high potential (step S4), and a voltage is set to make the resistance value of the magnetic memory element 1 a low resistance value (step S5). That is, the voltage applied to the magnetic memory element 1 is set to a negative voltage (voltage V<0).

[0203] After the setting in step S3 or step S5, a pulse voltage having the set voltage is applied (step S6). The magnetic memory element 1 has a low resistance value or a high resistance value. In other words, the resistance value of the magnetic memory element 1 switches between the low resistance value and the high resistance value.

[0204] FIG. 39 is a diagram showing an example of a timing chart for writing data. The write start signal is generated by, for example, the control circuit 731 (FIG. 37). The write direction control signal indicates the direction of switching the resistance value of the magnetic memory element 1, i.e., from low resistance value to high resistance value, or from high resistance value to low resistance value. The word line voltage, bit line voltage, and source line voltage indicate voltages applied to the word line WL, bit line BL, and source line SL. The bit line BL, source line SL, and word line WL are selected by the bit / source line address decoder 735 and word line address decoder 737, and the word line voltage, bit line voltage, and source line voltage are generated by the bit / source line control circuit 736 and word line control circuit 738. The bit line voltage and source line voltage are detected by the sense amplifier 739.

[0205] 39A shows a timing chart for switching the resistance value of the magnetic memory element 1 from a high resistance value to a low resistance value, and FIG. 39B shows a timing chart for switching the resistance value of the magnetic memory element 1 from a low resistance value to a high resistance value.

[0206] A word line voltage is applied in response to a write start signal. At the same time, when the resistance value of the magnetic memory element 1 is switched from a high resistance value to a low resistance value, the bit line voltage is controlled to be higher than the source line voltage, as shown in (A) of FIG. 39. When the resistance value of the magnetic memory element 1 is switched from a low resistance value to a high resistance value, the source line voltage is controlled to be higher than the bit line voltage, as shown in (B) of FIG. This switches the resistance value of the magnetic memory element 1 from a high resistance value to a low resistance value, or from a low resistance value to a high resistance value.

[0207] 39, the word line voltage, bit line voltage, and source line voltage are depicted as having the same pulse width, but the pulse widths of these voltages may be different. For example, it is also possible to control the voltages so that the word line voltage rises first, then the bit line voltage or source line voltage rises, and then the word line voltage falls after the bit line voltage or source line voltage falls.

[0208] 40 is a flowchart showing an example of a process (data read method) executed when reading data. This flow starts in response to input of a read command. It is assumed that the memory cell 71 including the magnetic memory element 1 from which data is to be read has already been selected, and the corresponding selection transistor 72 is turned on.

[0209] One of the bit line BL and the source line SL is set to a high potential (step S11), and a read voltage is set (step S12). For example, the bit line BL is set to a high potential. The read voltage is a voltage that can read the resistance value of the magnetic memory element 1 without switching the resistance value of the magnetic memory element 1. The magnitude of the read voltage may be smaller than the voltage applied during writing (write voltage).

[0210] A pulse voltage having the set voltage is applied (step S13), and the voltage at that time is detected by the sense amplifier 739. Since this detected voltage differs depending on the resistance value of the magnetic memory element 1, it is determined based on the detection result whether the resistance value of the magnetic memory element 1 is a low resistance value or a high resistance value (step S14).

[0211] In step S11, it may be arbitrarily selected which of the bit line BL and the source line SL is set to the higher potential. For example, the one with the lower probability of erroneous writing due to application of a read voltage may be selected.

[0212] 41 is a diagram showing an example of a timing chart when reading data. The read start signal is generated by, for example, the control circuit 731 (FIG. 37). The sense amplifier enable signal is a signal for enabling the sense amplifier 739 to detect the voltage of the source line SL, and is generated by, for example, the control circuit 731 (FIG. 37).

[0213] In response to the read start signal, the word line voltage is applied, and in this example, the bit line voltage is controlled to be higher than the source line voltage, and the sense amplifier 739 operates effectively to determine whether the resistance value of the magnetic memory element 1 is a low resistance value or a high resistance value.

[0214] As shown in FIG. 41, the bit line voltage during read, i.e., the read voltage, can be smaller than the bit line voltage during write ((A) in FIG. 39), i.e., the write voltage. Although the word line voltage, bit line voltage, and sense amplifier enable signal are depicted as having the same pulse width, the pulse widths of these voltages or signals may be different. For example, control is also possible such that the word line voltage rises first, then the bit line voltage rises, and then the word line voltage falls after the bit line voltage falls. The sense amplifier 739 may be enabled after the bit line voltage is applied.

[0215] For example, in the manner described above, data can be written to and read from the magnetic memory element 1. A storage device 7 is provided that utilizes the magnetic memory element 1. The effects of the magnetic memory element 1, such as reduced power consumption, as described above, can also be enjoyed by the storage device 7.

[0216] <Modifications of First Embodiment> Several modifications based on the technology of the above-described first embodiment will be described. Descriptions of content that overlaps with the above will be omitted where appropriate.

[0217] <First Modification of First Embodiment> In one embodiment, a verify read may be performed during a write. The read value (resistance value, bit value, etc.) is compared with an expected value, which is the value to be written, and if they do not match, a write voltage is applied again. This will be described with reference to FIGS. 42 and 43 .

[0218] 42 is a flowchart showing an example of a process (data write method) executed when writing data. After the processes of steps S1 to S6 described above with reference to FIG. 38 are completed, a verify read is performed (step S7), and it is determined whether the read value matches the expected value (step S8). If the read value matches the expected value (step S8: Yes), the process of the flowchart ends. If they do not match (step S8: No), the process returns to step S6, where a pulse voltage is applied again.

[0219] By repeatedly applying the pulse voltage until the resistance value of the magnetic memory element 1 matches the expected value, data can be reliably written to the magnetic memory element 1. Note that a maximum value may be set for the number of times the processes of steps S6 to S8 are repeated. If the number of times the processes are repeated exceeds the maximum value, the process of the flowchart ends.

[0220] 43 is a diagram showing an example of a timing chart when writing data. The comparison result signal indicates whether the value read by the verify read matches the expected value (match or mismatch), and is generated by, for example, the sense amplifier 739 or a separately provided verify circuit (not shown). In the example shown in FIG. 43, the comparison result signal goes high when the read value matches the expected value.

[0221] As in the previously described Figure 39, a word line voltage is applied in response to a write start signal. At the same time, when the resistance value of the magnetic memory element 1 is switched from a high resistance value to a low resistance value, the bit line voltage is controlled to be higher than the source line voltage, as shown in Figure 43(A). When the resistance value of the magnetic memory element 1 is switched from a low resistance value to a high resistance value, the source line voltage is controlled to be higher than the bit line voltage, as shown in Figure 43(B). Here, it is assumed that this first data write was unsuccessful and the resistance value of the magnetic memory element 1 is not the expected value.

[0222] Then, a verify read is performed. In response to a read start signal, a word line voltage is applied, and in this example, the bit line voltage is controlled so as to apply the same voltage as the read voltage. Furthermore, the sense amplifier 739 is enabled, and it is determined whether the resistance value of the magnetic memory element 1 is a high resistance value or a low resistance value. It is determined whether the resistance value indicated in the determination result, i.e., the read value, matches the expected value.

[0223] The read value does not match the expected value (mismatch), so writing to the magnetic memory element 1 is performed again. In response to the second write start signal, the word line voltage is applied, and one of the bit line voltage and source line voltage is controlled so that it is higher than the other. Here, it is assumed that this second data write is successful, and the resistance value of the magnetic memory element 1 is the expected value. Then, a verify read is performed, and it is determined that the read value matches the expected value (match). Writing data to the magnetic memory element 1 is completed.

[0224] If the read value does not match the expected value even in the second verify read, further data writing and verify read are performed. As described above, the maximum number of repetitions may be set.

[0225] According to the first modification described above, a write error is determined by verify reading, and rewriting is performed, thereby reducing the write error rate.

[0226] <Modification 2 of First Embodiment> In one embodiment, when the write voltage is applied again depending on the result of the verify read, the voltage setting may be changed. For example, the write voltage may be gradually increased, or the pulse width (pulse length) may be gradually increased. The write error rate varies depending on the magnitude and pulse width of the write voltage. The magnitude and pulse width of the write voltage corresponding to a predetermined write error rate may differ among the magnetic memory elements 1 of the memory cells 71 in the memory array 70, and may have a distribution.

[0227] If the write voltage is set to match the magnetic memory elements 1 located at the tail of the distribution, in other words, the magnetic memory elements 1 that require the highest write voltage or the longest pulse width, the power consumption required to write data to the majority of the magnetic memory elements 1 will be unnecessarily large. By gradually changing the write voltage according to the results of the verify read, it is possible to suppress the power consumption. This will be explained with reference to Figures 44 and 45.

[0228] 44 is a flowchart showing an example of a process (data write method) executed when writing data. If the read value does not match the expected value in step S8 described above with reference to FIG. 42 (step S8: No), the voltage is reset (step S9). For example, the magnitude and pulse width of the read voltage are set to be greater than those set in the previous step S3, step S5, or the previous step S9. Then, the process returns to step S6, where the pulse voltage is applied again.

[0229] FIG. 45 is a diagram showing an example of a timing chart for writing data. Similar to FIG. 43 described above, the first write fails, a verify read is performed, and then the second write succeeds. However, in this example, the second write voltage is higher than the first write voltage. In the example shown in FIG. 45(A), as indicated by the dashed line, the bit line voltage during the second write is higher than the bit line voltage during the first write. In the example shown in FIG. 45(B), as indicated by the dashed line, the source line voltage during the second write is higher than the source line voltage during the first write. Note that instead of or in addition to the magnitude of the write voltage, the voltage may be reset so that the pulse width of the second write voltage is larger than that of the first write voltage.

[0230] According to the second modification described above, it is possible to increase the possibility of reducing power consumption while reducing the write error rate.

[0231] 2.2 Second Embodiment As previously described with reference to FIG. 10 and other figures, the magnetic memory element 1 has the characteristic that its characteristics differ depending on the write direction, i.e., switching from a low resistance value to a high resistance value and switching from a high resistance value to a low resistance value. On the other hand, it may be expected that a long voltage application (e.g., a voltage application with a large pulse width) will be necessary to reduce the write error rate. Since the write delay is determined by the length of the voltage application, the worst-case delay time is visible from the outside of the storage device 7. It is conceivable that by initializing unnecessary data in advance, the write time will appear to be short.

[0232] In the first embodiment described above, a write command is received and data is written to the magnetic memory element 1. In this second embodiment, the magnetic memory element 1 is initialized in advance so that it has one of a low resistance value and a high resistance value. After initialization, the resistance value of only those magnetic memory elements 1 whose resistance value needs to be changed from the initialized value is switched to the other of the low resistance value and the high resistance value.

[0233] In one embodiment, the time for applying a voltage to the magnetic memory element 1 to make the magnetic memory element 1 have one resistance value (initial value) may be shorter than the time for applying a voltage to the magnetic memory element 1 to make the magnetic memory element 1 have the other resistance value, thereby shortening the time required for writing data.

[0234] Unless otherwise specified, hereinafter, it is assumed that the resistance value of the magnetic memory element 1 after initialization is a high resistance value (that is, initial value=high resistance value).

[0235] 46 is a diagram showing an example of a schematic configuration of a storage device 7 according to the second embodiment. The storage device 7 includes a plurality of memory blocks 8 and an access control unit 9.

[0236] 46 shows three memory blocks 8, designated by the reference numerals memory block 8-1, memory block 8-2, and memory block 8-3, as the plurality of memory blocks 8. When no particular distinction is made between these, they will simply be referred to as memory blocks 8.

[0237] The memory block 8 includes the memory array 70, control circuit 731, and sense amplifier 739 described in the first embodiment. Although not shown in FIG. 46, the memory block 8 also includes bit lines BL, source lines SL, and word lines WL (FIG. 37).

[0238] One of the features of the second embodiment is that the storage device 7 includes a plurality of memory arrays 70 corresponding to a plurality of memory blocks 8. The plurality of memory blocks 8 can operate in parallel. For example, N memory blocks 8 operate in parallel for a number N of input bits (N is an integer equal to or greater than 2).

[0239] The access control unit 9 is configured to have the function of simultaneously controlling multiple memory blocks 8. The functions of the access control unit 9 may be realized by hardware design, and some of the functions may be realized by software design. In the example shown in FIG. 46 , the access control unit 9 includes a microcontroller 91 and an initialization table 92 in addition to the I / O 730 described in the first embodiment. The microcontroller 91 executes various controls / processes according to software design. An example of control is management control of initialized areas (storage areas within the memory array 70), and the initialization table 92 is also used for this control. Unless otherwise specified, the unit of the area to be initialized is assumed to be each memory block 8.

[0240] Commands, addresses, write data, read data, and the like are exchanged between the storage device 7 and an external device via the I / O 730. The initialization table 92 is a table for managing initialized areas, addresses, and the like, and describes such information. The initialization table 92 may be stored in a nonvolatile memory. The memory array 70 in one of the memory blocks 8 may be used as the nonvolatile memory, or another nonvolatile memory (not shown) may be used. When the memory block 8 is activated, the information in the initialization table 92 may be loaded from the nonvolatile memory into the SRAM and used, and when the memory block 8 is shut down, the information in the initialization table 92 may be stored in the nonvolatile memory.

[0241] The microcontroller 91 controls commands input from the I / O 730, manages updates to the initialization table 92, and controls the storage of information in the nonvolatile memory before shutdown.

[0242] 47 is a flowchart showing an example of processing executed during initialization. This flow starts in response to input of an initialization command.

[0243] The microcontroller 91 of the access control unit 9 determines whether initialization has been completed (step S21). If initialization has been completed (step S21: Yes), the processing of the flowchart ends. If initialization has not been completed (step S21: No), in each memory block 8, the resistance value of the magnetic memory element 1 in the initialization target area is initialized under the control of, for example, the control circuit 731.

[0244] Specifically, in this example, the source line SL of the bit line BL and the source line SL is set to a high potential (step S22), and a voltage is set to make the resistance value of the magnetic memory element 1 a high resistance value (step S23). This initialization voltage may be the same voltage as the write voltage set in step S3 (FIG. 38, etc.) of the previous first embodiment, or may be a voltage set separately for initialization.

[0245] As mentioned earlier, the resistance value of the magnetic memory element 1 after initialization may be a low resistance value (i.e., initial value = low resistance value), in which case the bit line BL may be set to a high potential in the above-mentioned step S22.

[0246] 48 is a diagram showing an example of a timing chart during initialization. The initialization start signal is generated by, for example, the control circuit 731 (FIG. 46).

[0247] In response to the initialization start signal, the word line voltage is applied. At the same time, in this example, the source line voltage is controlled to be higher than the bit line voltage. The resistance value of the magnetic memory element 1 is initialized to a high resistance value.

[0248] The pulse widths of the word line voltage and the source line voltage may be different. For example, it is possible to control the voltage so that the word line voltage rises first, then the source line voltage rises, and then the word line voltage falls after the source line voltage falls. Furthermore, these pulse widths may be the same as or different from the pulse widths during writing in the previously described FIG. 39 and the like.

[0249] 49 is a flowchart showing an example of a process (data write method) executed when writing data. This flow starts in response to input of a write command and write data.

[0250] The microcontroller 91 of the access control unit 9 determines whether the magnetic memory element 1 of the corresponding memory block 8 is to have a low resistance value (step S31). If the magnetic memory element 1 is to have a low resistance value (step S31: Yes), the process of steps S4 to S6 described above with reference to FIG. 38 is performed for the corresponding memory block 8. If not, that is, if the magnetic memory element 1 is to have a high resistance value (step S31: No), the process proceeds to steps S21 to S23 described above with reference to FIG. 47 for the corresponding memory block 8. If initialization has not been completed (step S21: No), the processes of steps S22 and S23 are performed, and then a pulse voltage is applied (step S6). Note that if initialization has been completed in step S21 (step S21: Yes), the process of the flowchart ends.

[0251] The timing chart is based on the previously described FIGS. 39 and 43 and can be explained in the same way, so detailed explanation will be omitted.

[0252] According to the storage device 7 of the second embodiment, it is possible to suppress write delays.

[0253] <Modification of the Second Embodiment> The retention characteristics of the magnetic memory element 1 can be changed by changing the size of the memory layer 3 ( FIG. 1 , etc.) of the magnetic memory element 1 in the memory block 8. The size of the memory layer 3 is determined by the thickness of the memory layer 3 when the magnetic memory element 1 is viewed from the side (length in the Z-axis direction), the area of ​​the memory layer 3 when the magnetic memory element 1 is viewed from above (when viewed in the Z-axis direction), etc. The size of the memory layer 3 may be interpreted to mean thickness, area, volume, etc. Unless otherwise specified, the size of the memory layer 3 refers to the volume of the memory layer 3. The larger the size of the magnetic memory element 1, the better the retention characteristics (performance) and the longer the data can be retained.

[0254] In one embodiment, a plurality of memory blocks 8 included in the storage device 7 may include magnetic memory elements 1 having different sizes. This will be described with reference to FIG.

[0255] FIG. 50 is a diagram showing an example of the schematic configuration of a memory device 7. Two memory blocks 8 are shown as examples of memory blocks 8 included in the memory device 7. The first memory block and the second memory block are referred to as memory block 8-1 and memory block 8-2 and are shown in the figure. When no particular distinction is made between them, they are simply referred to as memory blocks 8. Note that FIG. 50 schematically shows only the memory array 70 and the magnetic memory elements 1 therein, out of the components included in the memory block 8.

[0256] The magnetic memory elements 1 included in the memory block 8-1 and the magnetic memory elements 1 included in the memory block 8-2 have different sizes. In this example, the size of the magnetic memory elements 1 in the memory block 8-1 is larger than the size of the magnetic memory elements 1 in the memory block 8-2.

[0257] The magnetic memory elements 1 in memory block 8-1 have higher retention characteristics than the magnetic memory elements 1 in memory block 8-2. Memory block 8-1 can be used suitably for long-term data storage. The magnetic memory elements 1 in memory block 8-2 have lower retention characteristics than the magnetic memory elements 1 in memory block 8-1, but can shorten the time required to write data and reduce power (voltage, current). Memory block 8-2 can be used suitably for short-term data storage.

[0258] As described above, it is effective to use a plurality of memory blocks 8 each including a magnetic memory element 1 having different sizes (retention characteristics). Taking this into consideration, the storage device 7 described so far can be incorporated into various chips, devices, etc. These will be described as the third to fifth embodiments.

[0259] 51 is a diagram showing an example of the schematic configuration of a storage device 7 according to the third embodiment. The storage device 7 is incorporated into an AI chip 10. The AI ​​chip 10 is a semiconductor chip including, for example, a Si semiconductor, and includes an AI processing circuit 11 and a memory area 12.

[0260] The AI ​​processing circuit 11 executes various AI (Artificial Intelligence) processes. Examples of AI processes include recognition processes and inference processes. Examples of the objects of processing include, but are not limited to, text, images, videos, audio, and music.

[0261] The memory area 12 stores data used by the AI ​​chip 10. The technology of the storage device 7 is used for this memory area 12. Specifically, the memory area 12 includes a long-term storage area 121 and a short-term storage area 122.

[0262] In this example, learning data is stored in the long-term storage area 121. Since the learning data is updated infrequently, long-term data storage is required in the long-term storage area 121. Calculated values ​​are stored in the short-term storage area 122. Since the calculated values ​​are frequently updated (overwritten, etc.), the short-term storage area 122 only needs to store data for a short period of time, but low latency is required.

[0263] The long-term storage area 121 of the memory area 12 includes a memory block 8-1. As previously described with reference to Figure 50, the memory block 8-1 here includes a magnetic memory element 1 having a large size, and is suitable for long-term data storage.

[0264] The short-term storage area 122 of the memory area 12 includes a memory block 8-2. As previously described with reference to Figure 50, the memory block 8-2 here includes a magnetic memory element 1 having a small size. The time required for writing is short, which enables low delay.

[0265] 52 and 53 are flowcharts showing examples of processing executed in the AI ​​chip 10.

[0266] 52 shows a flow for updating learning data. When learning data is input (step S31), the data is stored in the long-term storage area 121 (step S32). Specifically, bit data is written to the magnetic memory element 1 of the memory block 8-1 included in the long-term storage area 121. The learning data may be generated and updated by the AI ​​processing circuit 11.

[0267] FIG. 53 shows a flow chart of AI processing. When data to be processed by AI is input (step S41), learning data is read from the long-term storage area 121 (step S42), and AI processing is executed (step S43). For example, the AI ​​processing circuit 11 executes a multiply-and-accumulate operation on the input data and learning data. The calculation value used in this operation is stored in the short-term storage area 122 (step S44). This can also be said to temporarily store intermediate calculation results. Calculations using the learning data and intermediate calculation results are repeatedly executed a predetermined number of times depending on the components of the AI ​​processing circuit 11, such as the number of networks and the number of layers (step S45: No, steps S42 to S44). When the predetermined number of times is reached (step S45: Yes), the AI ​​processing circuit 11 terminates the calculation and outputs the results (step S46).

[0268] The same techniques as those described above may be used to write data to the long-term retention area 121 and the short-term retention area 122. For example, writing data to the long-term retention area 121, i.e., updating learning data, does not require processing as fast as AI processing, so verify read may be performed to sufficiently reduce the write error rate. The flowcharts and timing charts may be similar to those of FIGS. 42 to 45 described above. When writing data to the short-term retention area 122, i.e., updating the calculation value, verify read may not be performed from the perspective of low-latency access. The flowcharts and timing charts may be similar to those of FIGS. 38 and 39 described above.

[0269] For example, as described above, the storage device 7 can be incorporated into the AI ​​chip 10. Note that the same application is possible for chips, devices, etc. configured to execute various known processes, not limited to AI processing. In this sense, the AI ​​chip 10 may be appropriately interpreted as a chip, device, etc. that is not limited to AI processing.

[0270] <Modifications of the Third Embodiment> Several modifications of the above-described third embodiment will be described.

[0271] <First Modification of Third Embodiment> Since the long-term storage area 121 stores learning data for a long period of time, there is a possibility that the error rate will increase over time. To address this, an error correction technique may be applied to the long-term storage area 121. Storing error-correction-coded data improves error tolerance. In one embodiment, error correction may be performed only on the long-term storage area 121 out of the long-term storage area 121 and the short-term storage area 122. This will be described with reference to FIG. 54 .

[0272] 54 is a diagram showing a modified example. The AI ​​chip 10 has an error correction function only for the long-term storage area 121 of the long-term storage area 121 and the short-term storage area 122. Specifically, the AI ​​chip 10 includes an error correction circuit 13. The error correction circuit 13 performs error correction encoding on the learning data stored in the long-term storage area 121, and error correction decoding on the learning data read out from the long-term storage area 121.

[0273] 55 and 56 are flowcharts showing examples of processing executed in the AI ​​chip 10.

[0274] Figure 55 shows a flow for updating learning data. This flow differs from the previously described flow of Figure 52 in that it includes step S33 between steps S31 and S32. When learning data is input (step S31), the data is error-correction coded (step S33) and stored in long-term storage area 121 (step S32).

[0275] Figure 56 shows a flow for AI processing. This flow differs from the previously described flow of Figure 53 in that it includes step S47 between step S42 and step S43. When data to be subjected to AI processing is input (step S41), learning data is read from the long-term storage area 121 (step S42) and error correction decoded (step S47). The subsequent processing of steps S44 to S46 is as previously described.

[0276] The error correction function described above may be used to refresh the data in the long-term retention area 121. This will be explained with reference to FIG.

[0277] FIG. 57 is a flowchart showing an example of processing executed by the AI ​​chip 10. This flow is initiated in response to receipt of a refresh command. Upon receipt of a refresh command, learning data is read from the long-term storage area 121 (step S51), and error detection is performed (step S52). If there is no error (step S53: No), the processing of the flowchart ends. If there is an error (step S53: Yes), it is determined whether or not correction is possible (step S54). If correctable (step S54: Yes), the error is corrected (step S55), the corrected learning data is stored in the long-term storage area 121 (step S56), and the processing of the flowchart ends. If correction is not possible (step S54: No), a notification is sent to the system (step S57), and the processing of the flowchart ends. The system may be, for example, a system operating on a device equipped with the AI ​​chip 10.

[0278] As described above, by using the error correction function, it is possible to improve the error tolerance of data, particularly data related to long-term storage such as learning data.

[0279] <Second Modification of Third Embodiment> Error correction technology may also be applied to the short-term retention area 122. The long-term retention area 121 and the short-term retention area 122 may be designed so that the correction capabilities of the error correction codes are different. From the viewpoint of low-latency readout, for example, a Hamming code or a 2-bit correction BCH code may be used in the short-term retention area 122. Since the long-term retention area 121 is more tolerant of low latency than the short-term retention area 122, a correction code with higher performance than the short-term retention area 122 may be used in the long-term retention area 121. The error tolerance can be improved for both the long-term retention area 121 and the short-term retention area 122.

[0280] 2.4 Fourth Embodiment Fig. 58 is a diagram showing an example of a schematic configuration of a storage device 7 according to a fourth embodiment. The storage device 7 is incorporated into a solid-state imaging device 14 (image sensor) for use. Fig. 58 shows, by way of example, the ADC 141, frame memory control unit 142, logic unit 143, memory control unit 144, I / F 145, and memory area 146, of the components of the solid-state imaging device 14, with reference numerals assigned thereto.

[0281] First, the memory area 146 will be described. The memory area 146 stores data used by the solid-state imaging device 14. Typical memory functions related to data processing of the solid-state imaging device 14 include a frame memory that stores image data for one frame, an image processing memory that stores data related to image processing, and a non-volatile memory for storing setting values ​​for image processing and data transmission, and the technology of the storage device 7 is used for some or all of these. Specifically, the memory area 146 includes a short-term storage area 147 and a long-term storage area 148.

[0282] Image data is stored in the short-term holding area 147. The short-term holding area 147 includes a memory block 8-2. As described above, the memory block 8-2 here includes a small-sized magnetic memory element 1, which requires a short time for writing and allows for low latency.

[0283] In this example, there are two short-term storage areas 147. One of the short-term storage areas 147 is referred to as short-term storage area 147-1 and is illustrated. The other short-term storage area 147 is referred to as short-term storage area 147-2 and is illustrated. Each of the short-term storage areas 147-1 and 147-2 includes a memory block 8-2. The memory block 8-2 included in the short-term storage area 147-1 is referred to as memory block 8-2-1 and is illustrated. The memory block 8-2 included in the short-term storage area 147-2 is referred to as memory block 8-2-2 and is illustrated. When there is no need to distinguish between the short-term storage areas 147-1 and 147-2, and the memory blocks 8-2-1 and 8-2-2, they are simply referred to as the short-term storage areas 147 and memory blocks 8-2.

[0284] The long-term retention area 148 stores program data, operational setting values, etc. The program data is, for example, a control program for controlling the entire solid-state imaging device 14. The operational setting values ​​are, for example, parameters for specifying the image processing in the solid-state imaging device 14, the operation of the I / F 145, etc. The long-term retention area 148 includes a memory block 8-1. As described above, the memory block 8-1 here includes a large-sized magnetic memory element 1 and is suitable for long-term data retention.

[0285] The ADC 141 converts analog pixel signals obtained from a pixel array unit (not shown) into digital signals. The frame memory control unit 142 stores one frame's worth of image data in a short-term holding area 147-1 of the memory area 146. The logic unit 143 executes image processing based on one frame's worth of image data. One example of image processing is image correction processing, but this is not limiting and various other known image processing may be executed. The memory control unit 144 stores the image data after logic processing in a short-term holding area 147-2 of the memory area 146. The I / F 145 outputs the image data to the outside.

[0286] The short-term holding area 147-1, which stores one frame of image data after AD conversion as described above, functions as a frame memory. The short-term holding area 147-2, which stores image data after image processing and before being output by the I / F 145, can also be called a buffer, a subsequent memory, or a main memory.

[0287] 59 to 61 are flowcharts showing examples of processing executed in the solid-state imaging device 14.

[0288] 59 shows the flow at startup. Operational setting values ​​are read from the long-term storage area 148 (step S61). By using the internal non-volatile memory, there is no need to load data from an external flash memory, for example, and startup speed can be increased accordingly.

[0289] A flow for updating program data is shown in Fig. 60. When program data is input (step S71), the data is stored in the long-term storage area 148 (step S72).

[0290] 61 shows the flow of image data processing. Pixel signals are AD converted (step S81), and the resulting image data is stored in short-term holding area 147-1 (step S82). The image data is read from short-term holding area 147-1 (step S83), image processing is performed, and the image data is stored in short-term holding area 147-2 (step S84). The image data is read from short-term holding area 147-2 and output from I / F 145 (step S85).

[0291] The same techniques as those described above may be used for writing data to the long-term retention area 148 and the short-term retention area 147. For example, writing data to the long-term retention area 148, i.e., updating program data, does not require processing as fast as image processing, so verify read may be performed to sufficiently reduce the write error rate. The flowcharts and timing charts may be similar to those shown in Figures 42 to 45 described above. Writing data to the short-term retention area 147, i.e., updating image data, does not require verify read from the perspective of low-latency access. The flowcharts and timing charts may be similar to those shown in Figures 38 and 39 described above.

[0292] <Modifications of the Fourth Embodiment> Several modifications of the above-described fourth embodiment will be described.

[0293] <First Modification of Fourth Embodiment> In the fourth embodiment, as in the third embodiment, an error correction code technique may be applied. In this case, the solid-state imaging device 14 may include, for example, a circuit similar to the error correction circuit 13 previously described with reference to FIG. 54 . The error correction circuit 13 may be provided only in the long-term retention area 148 of the short-term retention area 147 and the long-term retention area 148 of the memory area 146. This can improve the error tolerance of data related to long-term data retention.

[0294] <Modification 2 of Fourth Embodiment> Error correction technology may also be applied to the short-term retention area 147. The long-term retention area 148 and the short-term retention area 147 may be designed so that the correction capabilities of the error correction codes are different. The details are the same as those for the long-term retention area 121 and short-term retention area 122 ( FIG. 51 ) described above, and therefore will not be described again. The error tolerance of both the long-term retention area 148 and the short-term retention area 147 can be improved.

[0295] In one embodiment, the solid-state imaging device 14 may have a stacked structure in which a plurality of chips are stacked. This will be described as a fifth embodiment.

[0296] 2.5 Fifth Embodiment Fig. 62 is a diagram showing an example of the schematic configuration of a memory device 7 according to a fifth embodiment. The solid-state imaging device 14 includes multiple chips and has a stacked structure in which the chips are stacked. Examples of the multiple chips include chip CH1 and chip CH2. When stacked, chip CH1 and chip CH2 function as the solid-state imaging device 14. Fig. 62 shows chip CH1 and chip CH2 exploded in the stacking direction.

[0297] The chip CH1 is a pixel chip, and is provided with, for example, a plurality of pixels (pixel array portion) arranged in a two-dimensional array, a pixel circuit including transistors used for driving the pixels, and the like.

[0298] Chip CH2 is an image processing chip for processing pixel signals. In this example, chip CH2 includes a logic region R1 and a memory region R2. The logic region R1 includes the ADC 141, frame memory control unit 142, logic unit 143, memory control unit 144, I / F 145, and the like, which are previously described and shown in FIG. 58 . The memory region R2 includes the memory region 146, which is previously described and also includes the storage device 7.

[0299] For example, the memory device 7 can be applied to a solid-state imaging device 14 having the above-described stacked chip structure.

[0300] 63 is a diagram showing a modification of the fifth embodiment. In the chip CH2, an SRAM 15 is provided in an area separate from the logic area R1 and the memory area R2. The memory device 7 can also be applied to such a solid-state imaging device 14.

[0301] 2.6 Sixth Embodiment Fig. 64 is a diagram showing an example of a schematic configuration of a storage device 7 according to a sixth embodiment. The storage device 7 is incorporated into a CPU 16. The CPU 16 includes a CPU core 160, a primary cache 161, and a secondary cache 162.

[0302] The CPU core 160 executes various arithmetic processes while using a primary cache 161 and a secondary cache 162 .

[0303] The primary cache 161 includes a memory device 7 and an error correction circuit 13. The error correction circuit 13 has been described above with reference to the memory device 7. Although the error correction circuit 13 is shown as a separate element from the memory device 7 in FIG. 65 , the error correction circuit 13 may be included in the memory device 7 as a component of the memory device 7.

[0304] Like the primary cache 161 , the secondary cache 162 also includes a storage device 7 and an error correction circuit 13 .

[0305] The CPU 16 described above is suitable for use in systems requiring large-scale caches and high-speed processing, such as processors installed in servers in communication networks. SRAMs require large areas and suffer from significant leakage, so memory power consumption becomes an issue when the cache size increases. The magnetic memory element 1 included in the storage device 7 has a smaller area than SRAMs and can reduce leakage.

[0306] It is also possible to configure the device without the error correction circuit 13. If the error correction circuit 13 is provided, the possibility of reducing the write error rate increases accordingly.

[0307] <Modification of the Sixth Embodiment> Fig. 65 is a diagram showing a modification. Of the primary cache 161 and secondary cache 162 of the CPU 16, the primary cache 161 includes an SRAM 15. In this way, a configuration in which the storage device 7 and the SRAM 15 are mixed is also possible. Various designs are possible according to required specifications, etc.

[0308] <Summary> The storage device 7 described above is specified, for example, as follows. As described with reference to Figures 1 to 9, 19 to 23, and 25 to 45, the storage device 7 includes a magnetic memory element 1 and a control circuit 731 that controls writing of data to the magnetic memory element 1. The magnetic memory element 1 includes a magnetization fixed layer 2 in which the direction of magnetization is fixed, and a storage layer 3 in which the direction of magnetization is reversible. The storage layer 3 includes a first region 31 including a ferromagnetic material and a second region including an antiferromagnetic material or a ferrimagnetic material.

[0309] According to the storage device 7, the effects of the magnetic memory element 1 described above, such as reduced power consumption, can also be enjoyed by the storage device 7.

[0310] 10 and 36 to 39, the magnetic memory element 1 has a resistance value corresponding to the direction of magnetization of the memory layer 3, and the control by the control circuit 731 may include applying one of a positive voltage (voltage V>0) and a negative voltage (voltage V<0) to the magnetic memory element 1 so that the magnetic memory element 1 has one of a low resistance value and a high resistance value (steps S2, S3, and S6, or steps S4, S5, and S6), and applying the other of a positive voltage and a negative voltage to the magnetic memory element so that the magnetic memory element 1 has the other of a low resistance value and a high resistance value (steps S2, S3, and S6, or steps S4, S5, and S6). For example, in this way, data can be written to the magnetic memory element 1.

[0311] 10 and the like, in a state where no magnetic field H is applied to the magnetic memory element 1, when one of a positive voltage and a negative voltage is applied to the magnetic memory element 1, the magnetic memory element 1 may have a resistance value of one of a low resistance value and a high resistance value, and when the other of a positive voltage and a negative voltage is applied to the magnetic memory element 1, the magnetic memory element 1 may have a resistance value of the other of a low resistance value and a high resistance value. The magnetic memory element 1 has an RH loop characteristic in which the resistance value changes with hysteresis depending on the magnitude of the applied magnetic field (magnetic field H), and the hysteresis of the RH loop characteristic when a positive voltage (voltage V>0) is applied to the magnetic memory element 1 and the hysteresis of the RH loop characteristic when a negative voltage (voltage V<0) is applied may be shifted to opposite sides from the hysteresis of the RH loop characteristic when substantially no voltage is applied to the magnetic memory element 1 (voltage V≒0). The hysteresis of the RH loop characteristics when substantially no voltage is applied to the magnetic memory element 1 (V≒0) crosses the magnitude of the applied magnetic field = 0 (magnetic field H = 0), and the hysteresis of the RH loop characteristics when a positive voltage (voltage V>0) is applied to the magnetic memory element 1 and when a negative voltage (voltage V<0) is applied do not need to cross the magnitude of the applied magnetic field = 0 (magnetic field H = 0). The hysteresis of the RH loop characteristic when one of a positive voltage and a negative voltage (for example, voltage V>0) is applied to the magnetic memory element 1 may be larger than the hysteresis of the RH loop characteristic when substantially no voltage is applied to the magnetic memory element 1 (voltage V≒0), and the hysteresis of the RH loop characteristic when the other of a positive voltage and a negative voltage (for example, voltage V<0) is applied to the magnetic memory element 1 may be smaller than the hysteresis of the RH loop characteristic when substantially no voltage is applied to the magnetic memory element 1 (voltage V≒0). For example, data can be written to the magnetic memory element 1 by utilizing such electrical and magnetic characteristics.

[0312] As described with reference to Figures 46 to 49, the control by the control circuit 731 may include initializing the magnetic memory element 1 so that it has one of a low resistance value and a high resistance value (e.g., a high resistance value) (steps S22, S23, and S6), and switching the resistance value of the magnetic memory element 1 after initialization to the other of the low resistance value and the high resistance value (e.g., a low resistance value) (steps S4 to S6). The time for applying a voltage to the magnetic memory element 1 so that the magnetic memory element 1 has one resistance value may be shorter than the time for applying a voltage to the magnetic memory element 1 so that the magnetic memory element 1 has the other resistance value. This shortens the time required for writing data.

[0313] As described with reference to Figures 46 and 50, the storage device 7 may include memory blocks 8-1 and 8-2 (first and second memory blocks) that include magnetic memory elements 1 of different sizes. This allows the two types of memory blocks 8 to be used appropriately. For example, memory blocks 8 that include large-sized magnetic memory elements 1 can be used favorably for long-term data storage. Memory blocks 8 that include small-sized magnetic memory elements 1 can be used to shorten the time required to write data and reduce power (voltage, current).

[0314] The memory device 7 can be incorporated into various chips, devices, etc. For example, as described with reference to Figures 51 to 57, the memory device 7 can be incorporated into the AI ​​chip 10. As described with reference to Figures 58 to 63, etc., the memory device 7 can be incorporated into the solid-state imaging device 14. As described with reference to Figures 64 and 65, etc., the memory device 7 can be incorporated into the CPU 16.

[0315] Various processes executed in the storage device 7 can also be identified as method techniques. One of the methods is a data writing method. As described with reference to FIGS. 1 to 9 , 19 to 23 , and 25 to 45 , the writing method is a method for writing data to a magnetic memory element 1. The magnetic memory element 1 includes a magnetization fixed layer 2 in which the magnetization direction is fixed, and a memory layer 3 in which the magnetization direction is reversible. The memory layer 3 includes a first region 31 containing a ferromagnetic material and a second region 32 containing an antiferromagnetic material or a ferrimagnetic material. The magnetic memory element 1 has a resistance value corresponding to the magnetization direction of the memory layer 3. The writing method includes applying one of a positive voltage (voltage V>0) and a negative voltage (voltage V<0) to the magnetic memory element 1 so that the magnetic memory element 1 has one of a low resistance value and a high resistance value (steps S2, S3, and S6, or steps S4, S5, and S6), and applying the other of a positive voltage and a negative voltage to the magnetic memory element so that the magnetic memory element 1 has the other of a low resistance value and a high resistance value (steps S2, S3, and S6, or steps S4, S5, and S6). As explained above, this writing method also makes it possible to reduce power consumption.

[0316] The effects described in this disclosure are merely examples and are not limited to the disclosed contents. Other effects may also be obtained.

[0317] Although the embodiments of the present disclosure have been described above, the technical scope of the present disclosure is not limited to the above-described embodiments, and various modifications are possible within the scope of the gist of the present disclosure. Furthermore, components of different embodiments and modifications may be combined as appropriate.

[0318] The present technology may also have the following configurations. (1) A magnetic memory element including: a magnetization fixed layer having a fixed magnetization direction; and a memory layer having a reversible magnetization direction, wherein the memory layer includes: a first region including a ferromagnetic material; and a second region including an antiferromagnetic material or a ferrimagnetic material. (2) The magnetic memory element according to (1), wherein the first region and the second region are stacked. (3) The magnetic memory element according to (1), wherein the memory layer includes a plurality of the first regions and a plurality of the second regions that are dispersed. (4) The magnetic memory element according to any one of (1) to (3), wherein the memory layer includes a spacer region including a nonmagnetic material and provided between the first region and the second region. (5) The magnetic memory element according to any one of (1) to (3), wherein the first region includes at least one of Co, Fe, Ni, Mn, Al, B, P, C, Zr, Hf, Ta, and Nb. (6) The magnetic memory element according to (5), wherein the first region includes CoFeB. (7) The magnetic memory element according to (6), wherein the Fe composition ratio in the CoFeB of the first region is higher than the Co composition ratio. (8) The magnetic memory element according to (6) or (7), wherein the B composition ratio in the CoFeB of the first region is 40 at% or less. (9) The magnetic memory element according to any one of (1) to (8), wherein the first region has a thickness of 0.1 nm or more and 1.5 nm or less. (10) The magnetic memory element according to any one of (1) to (9), wherein the second region includes at least one of Mn, Cr, Ir, Pt, Pd, Ni, Sn, Fe, Ge, Co, Ga, and Si. (11) The magnetic memory element according to any one of (1) to (9), wherein the second region includes a chalcogenide. (12) The magnetic memory element according to (11), wherein the chalcogenide in the second region includes CuMnAs or MnPS3. (13) The magnetic memory element according to any one of (1) to (9), wherein the second region includes an oxide. (14) The magnetic memory element according to (13), wherein the oxide in the second region includes NiO, Cr2O3, CoO, Fe2O3, or Mn2O3.(15) The magnetic memory element according to (10), wherein the second region includes an antiferromagnetic alloy or a ferrimagnetic alloy. (16) The magnetic memory element according to (15), wherein the antiferromagnetic alloy or ferrimagnetic alloy of the second region includes FeNiMn, CrNiMn, FeCrMn, FeCoMn, CoNiMn, FeNiCr, GaNiMn, CoPtMn, FePtMn, FeMn, NiMn, FeNi, PtMn, PdMn, or CoGeMn. (17) The alloy of the second region is Fe with a composition ratio of Fe, Ni, and Mn of x, y, and z. ｘ Ni ｙ Mn ｚ (18) The magnetic memory element according to (16), wherein the alloy in the second region is a Cr alloy having a composition range of 0 at%<x≦95 at%; 0 at%<y≦80 at%; 5 at%≦z≦80 at%. (18) The alloy in the second region is a Cr alloy having a composition ratio of Cr, Ni, and Mn of x, y, and z. ｘ Ni ｙ Mn ｚ (19) The magnetic memory element according to (16), wherein the alloy in the second region is an Fe alloy having composition ranges of 0 at%<x≦65 at%; 0 at%<y≦75 at%; and 0 at%<z≦80 at%. ｘ Cr ｙ Mn ｚ (20) The magnetic memory element according to (16), wherein the alloy in the second region is an Fe alloy having composition ranges of 0 at%<x≦95 at%; 0 at%<y≦70 at%; and 5 at%≦z≦80 at%. ｘ Co ｙ Mn ｚ (21) The magnetic memory element according to (16), wherein the second region is an alloy having composition ranges of 0 at%<x≦95 at%; 0 at%<y≦50 at%; and 5 at%≦z≦80 at%. ｘ Ni ｙ Mn ｚ(22) The magnetic memory element according to (16), wherein the second region is an Fe alloy having composition ranges of 0 at%<x≦50 at%; 5 at%≦y≦80 at%; and 5 at%≦z≦90 at%. ｘ Ni ｙ Cr ｚ (23) The magnetic memory element according to (16), wherein the second region is an alloy having composition ranges of 60 at%≦x≦82 at%; 15 at%≦y≦40 at%; and 10 at%≦z≦35 at%. ｘ , Ge ｙ , Mn ｚ(16) The magnetic memory element according to (16), wherein the magnetic memory element is an alloy having a composition range of 0 at%<x≦20 at%; 0 at%<y≦95 at%; and 5 at%≦z<100 at%. (24) The magnetic memory element according to any one of (1) to (23), wherein the first region and the second region are provided so as to be magnetically coupled to each other. (25) The magnetic memory element according to any one of (1) to (24), wherein the second region has a thickness of 0.1 nm or more and 5 nm or less. (26) The magnetic memory element according to (4), wherein the spacer region includes at least one of Ta, Ru, Ir, W, Mo, Rh, Re, Nb, Cu, Cr, V, TiN, TaN, and WN. (27) The magnetic memory element according to (4) or (26), wherein the spacer region is provided between the first region and the second region so that the first region and the second region are magnetically coupled to each other, and the magnetization of the second region acts on the magnetization of the first region via the spacer region. (28) The magnetic memory element according to (4), (26), or (27), wherein the spacer region has a thickness of 0.1 nm or more and 1.5 nm or less. (29) The magnetic memory element according to any of (1) to (28), wherein the memory layer includes a barrier layer provided between the first region and the second region and the magnetization fixed layer, and the barrier layer includes an oxide of at least one of Mg, Ca, Li, Si, Al, Sr, Zr, Hf, Ti, Zn, Mo, Cu, Ba, Ta, W, V, Ni, Co, Mn, Cr, Fe, B, and C. (30) The magnetic memory element according to any one of (1) to (28), wherein the memory layer includes a barrier layer provided between the first region and the second region and the magnetization fixed layer, and the barrier layer includes an oxide of at least one of Sc, Y, La, Ce, Pr, Nd, Pm, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb, and Lu. (31) The magnetic memory element according to (29), wherein the barrier layer includes MgO. (32) The magnetic memory element according to (31), wherein the barrier layer further includes Fe, Co, or Mn in addition to the MgO. (33) The magnetic memory element according to (32), wherein an amount of the Fe, Co, or Mn added to the MgO of the barrier layer is 20 at % or less.(34) The magnetic memory element according to any one of (1) to (33), wherein the memory layer includes a barrier layer provided on the opposite side of the magnetization fixed layer with the first region and the second region interposed therebetween, and the barrier layer includes at least one of Mg, Ca, Li, Si, Al, Sr, Zr, Hf, Ti, Zn, Mo, Cu, Ba, Ta, W, V, Ni, Co, Mn, Cr, Fe, B, and C. (35) The magnetic memory element according to any one of (1) to (33), wherein the memory layer includes a barrier layer provided on the opposite side of the magnetization fixed layer with the first region and the second region interposed therebetween, and the barrier layer includes an oxide of at least one of Sc, Y, La, Ce, Pr, Nd, Pm, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb, and Lu. (36) The magnetic memory element according to (34), wherein the barrier layer contains MgO. (37) The magnetic memory element according to (36), wherein the barrier layer further contains Fe, Co, or Mn in addition to MgO. (38) The magnetic memory element according to (37), wherein the amount of Fe, Co, or Mn added to the MgO of the barrier layer is 20 at % or less. (39) The magnetic memory element according to (34), (36), (37), or (38), wherein the barrier layer contains an antiferromagnetic oxide. (40) The magnetic memory element according to (39), wherein the antiferromagnetic oxide of the barrier layer contains NiO, Cr2O3, CoO, Fe2O3, or Mn2O3. (41) The magnetic memory element according to any one of (1) to (40), wherein the magnetization fixed layer includes a reference layer whose magnetization direction is fixed, and the reference layer includes at least one of Fe, Co, Ni, Mn, and B. (42) The magnetic memory element according to (41), wherein the magnetization fixed layer includes a fixed layer that fixes the magnetization direction of the reference layer. (43) The magnetic memory element according to any one of (1) to (42), wherein the memory layer includes: a barrier layer provided between the first region and the second region and the magnetization fixed layer, a barrier layer provided on the opposite side of the magnetization fixed layer with the first region and the second region sandwiched between them, and a ferromagnetic layer provided on the opposite side of the barrier layer with the first region and the second region sandwiched between them.(44) The magnetic memory element according to any one of (1) to (42), wherein the memory layer includes: a spacer layer provided on the opposite side of the magnetization fixed layer with the first region and the second region sandwiched therebetween; and a ferromagnetic layer provided on the opposite side of the spacer layer with the first region and the second region sandwiched therebetween. (45) The magnetic memory element according to any one of (1) to (44), wherein the magnetization direction of the memory layer is reversed depending on the positive and negative of a voltage applied to the magnetic memory element. (46) A storage device comprising: a magnetic memory element; and a control circuit that controls writing of data to the magnetic memory element, wherein the magnetic memory element includes: a magnetization fixed layer whose magnetization direction is fixed; and a memory layer whose magnetization direction is reversible, and the memory layer includes: a first region including a ferromagnetic material; and a second region including an antiferromagnetic material or a ferrimagnetic material. (47) The storage device according to (46), wherein the magnetic memory element has a resistance value according to the direction of magnetization of the storage layer, and the control by the control circuit includes: applying one of a positive voltage and a negative voltage to the magnetic memory element so that the magnetic memory element has one of a low resistance value and a high resistance value, and applying the other of a positive voltage and a negative voltage to the magnetic memory element so that the magnetic memory element has the other of a low resistance value and a high resistance value. (48) The storage device according to (47), wherein, in a state where a magnetic field is not applied to the magnetic memory element, when one of a positive voltage and a negative voltage is applied to the magnetic memory element, the magnetic memory element has one of a low resistance value and a high resistance value, and when the other of a positive voltage and a negative voltage is applied to the magnetic memory element, the magnetic memory element has the other of a low resistance value and a high resistance value.(49) The storage device according to any one of (46) to (48), wherein the magnetic memory element has an RH loop characteristic in which a resistance value changes with hysteresis depending on the magnitude of an applied magnetic field, and the hysteresis of the RH loop characteristic when a positive voltage is applied to the magnetic memory element and the hysteresis of the RH loop characteristic when a negative voltage is applied are shifted to opposite sides from the hysteresis of the RH loop characteristic when substantially no voltage is applied to the magnetic memory element. (50) The storage device according to (49), wherein the hysteresis of the RH loop characteristic when substantially no voltage is applied to the magnetic memory element crosses the magnitude of the applied magnetic field = 0, and the hysteresis of the RH loop characteristic when a positive voltage is applied to the magnetic memory element and the hysteresis of the RH loop characteristic when a negative voltage is applied do not cross the magnitude of the applied magnetic field = 0. (51) The storage device according to (49) or (50), wherein the hysteresis of the RH loop characteristic when one of a positive voltage and a negative voltage is applied to the magnetic memory element is larger than the hysteresis of the RH loop characteristic when substantially no voltage is applied to the magnetic memory element, and the hysteresis of the RH loop characteristic when the other of a positive voltage and a negative voltage is applied to the magnetic memory element is smaller than the hysteresis of the RH loop characteristic when substantially no voltage is applied to the magnetic memory element. (52) The storage device according to any of (46) to (51), wherein the control by the control circuit includes initializing the magnetic memory element to have one of a low resistance value and a high resistance value, and switching the resistance value of the magnetic memory element after initialization to the other of the low resistance value and the high resistance value. (53) The storage device according to (52), wherein a time for applying a voltage to the magnetic memory element to make the magnetic memory element have the one resistance value is shorter than a time for applying a voltage to the magnetic memory element to make the magnetic memory element have the other resistance value. (54) The storage device according to any of (46) to (53), comprising a first memory block and a second memory block including magnetic memory elements having mutually different sizes.(55) The storage device according to any one of (46) to (53), which is incorporated into an AI chip for use. (56) The storage device according to any one of (46) to (53), which is incorporated into a solid-state imaging device for use. (57) The storage device according to any one of (46) to (53), which is incorporated into a CPU for use. (58) A method for writing data to a magnetic memory element, wherein the magnetic memory element includes: a magnetization fixed layer in which the magnetization direction is fixed; and a memory layer in which the magnetization direction is reversible; the memory layer includes: a first region including a ferromagnetic material; and a second region including an antiferromagnetic material or a ferrimagnetic material; the magnetic memory element has a resistance value according to the magnetization direction of the memory layer; and the writing method includes: applying one of a positive voltage and a negative voltage to the magnetic memory element so that the magnetic memory element has one of a low resistance value and a high resistance value; and applying the other of a positive voltage and a negative voltage to the magnetic memory element so that the magnetic memory element has the other of the low resistance value and the high resistance value. (59) The writing method according to (58), wherein, in a state where no magnetic field is applied to the magnetic memory element, when one of a positive voltage and a negative voltage is applied to the magnetic memory element, the magnetic memory element has one of a low resistance value and a high resistance value, and when the other of a positive voltage and a negative voltage is applied to the magnetic memory element, the magnetic memory element has the other of a low resistance value and a high resistance value. (60) The writing method according to (58) or (59), wherein the magnetic memory element has an RH loop characteristic in which the resistance value changes with hysteresis depending on the magnitude of the applied magnetic field, and the hysteresis of the RH loop characteristic when a positive voltage is applied to the magnetic memory element and the hysteresis of the RH loop characteristic when a negative voltage is applied are shifted to opposite sides from the hysteresis of the RH loop characteristic when substantially no voltage is applied to the magnetic memory element.(61) The writing method according to (60), wherein the hysteresis of the RH loop characteristic when substantially no voltage is applied to the magnetic memory element crosses the magnitude of the applied magnetic field = 0, and the hysteresis of the RH loop characteristic when a positive voltage is applied to the magnetic memory element and the hysteresis of the RH loop characteristic when a negative voltage is applied do not cross the magnitude of the applied magnetic field = 0. (62) The writing method according to (60) or (61), wherein the hysteresis of the RH loop characteristic when one of a positive voltage and a negative voltage is applied to the magnetic memory element is larger than the hysteresis of the RH loop characteristic when substantially no voltage is applied to the magnetic memory element, and the hysteresis of the RH loop characteristic when the other of a positive voltage and a negative voltage is applied to the magnetic memory element is smaller than the hysteresis of the RH loop characteristic when substantially no voltage is applied to the magnetic memory element. (63) The writing method according to any one of (58) to (62), comprising: initializing the magnetic memory element so that it has one of a low resistance value and a high resistance value; and switching the resistance value of the magnetic memory element after initialization to the other of the low resistance value and the high resistance value. (64) The writing method according to (63), wherein a time period for applying a voltage to the magnetic memory element so that the magnetic memory element has the one resistance value is shorter than a time period for applying a voltage to the magnetic memory element so that the magnetic memory element has the other resistance value.

[0319] 1 Magnetic memory element 2 Ferromagnetic layer 21 Fixed layer 22 Reference layer 3 Storage layer 30 Barrier layer 31 First region 32 Second region 33 Spacer region 34 Barrier layer 35 Spacer layer 4 Ferromagnetic layer 5 Lower electrode layer 6 Cap layer 7 Storage device 70 Memory array 71 Memory cell 72 Select transistor 730 I / O 731 Control circuit 732 Voltage generation circuit 733 Write circuit 734 Read circuit 735 Bit / source line address decoder 736 Bit / source line control circuit 737 Word line address decoder 738 Word line control circuit 739 Sense amplifier 8 Memory block 8-1 Memory block (first memory block) 8-2 Memory block (second memory block) 8-3 Memory block 9 Access control unit 91 Microcontroller 92 Initialization table 10 AI chip 11 AI processing circuit 12 Memory area 121 Long-term storage area 122 Short-term storage area 13 Error correction circuit 14 Solid-state imaging device 15 SRAM 16 CPU BL Bit line SL Source line WL Word line CH1 chip CH2 chip R1 Logic area R2 Memory area

Claims

1. A magnetic memory element comprising: a magnetization fixed layer in which the magnetization direction is fixed; and a memory layer in which the magnetization direction is reversible, wherein the memory layer comprises a first region containing a ferromagnetic material and a second region containing an antiferromagnetic material or a ferrimagnetic material.

2. The magnetic memory element according to claim 1, wherein the first region and the second region are arranged in a stacked manner.

3. The magnetic memory element according to claim 1, wherein the storage layer includes a plurality of the first regions and a plurality of the second regions that are distributed.

4. The magnetic memory element according to claim 1, wherein the storage layer includes a spacer region including a non-magnetic material and provided between the first region and the second region.

5. The magnetic memory element according to claim 1, wherein the first region includes at least one of Co, Fe, Ni, Mn, Al, B, P, C, Zr, Hf, Ta, and Nb.

6. The magnetic memory element according to claim 5, wherein the first region includes CoFeB.

7. The magnetic memory element according to claim 6, wherein the composition ratio of Fe in the CoFeB of the first region is greater than the composition ratio of Co.

8. The magnetic memory element according to claim 6, wherein the composition ratio of B in the CoFeB of the first region is 40 at % or less.

9. The magnetic memory element according to claim 1, wherein the first region has a thickness of 0.1 nm or more and 1.5 nm or less.

10. The magnetic memory element according to claim 1, wherein the second region includes at least one of Mn, Cr, Ir, Pt, Pd, Ni, Sn, Fe, Ge, Co, Ga, and Si.

11. The magnetic memory element of claim 1, wherein the second region includes a chalcogenide.

12. The magnetic memory element according to claim 11, wherein the chalcogenide of the second region includes CuMnAs or MnPS3.

13. The magnetic memory element of claim 1, wherein the second region comprises an oxide.

14. The magnetic memory element according to claim 13, wherein the oxide of the second region includes NiO, Cr2O3, CoO, Fe2O3, or Mn2O3.

15. The magnetic memory element according to claim 10, wherein the second region includes an antiferromagnetic alloy or a ferrimagnetic alloy.

16. The magnetic memory element of claim 15, wherein the antiferromagnetic or ferrimagnetic alloy of the second region comprises FeNiMn, CrNiMn, FeCrMn, FeCoMn, CoNiMn, FeNiCr, GaNiMn, CoPtMn, FePtMn, FeMn, NiMn, FeNi, PtMn, PdMn, or CoGeMn.

17. The alloy of the second region is Fe, Ni, Mn with a composition ratio of x, y, z. ｘ Ni ｙ Mn ｚ 17. The magnetic memory element according to claim 16, which is an alloy and has the composition ranges of 0 at%<x≦95 at%, 0 at%<y≦80 at%, and 5 at%≦z≦80 at%.

18. The alloy of the second region is a Cr alloy having a composition ratio of Cr, Ni, and Mn of x, y, and z. ｘ Ni ｙ Mn ｚ 17. The magnetic memory element according to claim 16, which is an alloy and has the composition ranges 0 at%<x≦65 at%, 0 at%<y≦75 at%, and 0 at%<z≦80 at%.

19. The alloy of the second region is Fe, Cr, Mn with a composition ratio of x, y, z. ｘ Cr ｙ Mn ｚ 17. The magnetic memory element according to claim 16, which is an alloy and has the composition ranges of 0 at%<x≦95 at%, 0 at%<y≦70 at%, and 5 at%≦z≦80 at%.

20. The alloy of the second region is Fe, Co, Mn with a composition ratio of x, y, z. ｘ Co ｙ Mn ｚ 17. The magnetic memory element according to claim 16, which is an alloy and has the composition ranges of 0 at%<x≦95 at%, 0 at%<y≦50 at%, and 5 at%≦z≦80 at%.

21. The second region is a Ga-based semiconductor having a composition ratio of Ga, Ni, and Mn of x, y, and z. ｘ Ni ｙ Mn ｚ 17. The magnetic memory element according to claim 16, which is an alloy and has the composition ranges of 0 at%<x≦50 at%, 5 at%≦y≦80 at%, and 5 at%≦z≦90 at%.

22. The second region is an Fe alloy having a composition ratio of Fe, Ni, and Cr of x, y, and z. ｘ Ni ｙ Cr ｚ 17. The magnetic memory element according to claim 16, which is an alloy and has the composition ranges 60 at%≦x≦82 at%, 15 at%≦y≦40 at%, and 10 at%≦z≦35 at%.

23. The second region is a Co, Ge, Mn layer having a composition ratio of x, y, z. ｘ , Ge ｙ , Mn ｚ 17. The magnetic memory element according to claim 16, which is an alloy and has the composition ranges of 0 at%<x≦20 at%; 0 at%<y≦95 at%; and 5 at%≦z<100 at%.

24. The magnetic memory element according to claim 1, wherein the first region and the second region are provided so as to be magnetically coupled to each other.

25. The magnetic memory element according to claim 1, wherein the second region has a thickness of 0.1 nm or more and 5 nm or less.

26. The magnetic memory element of claim 4, wherein the spacer region comprises at least one of Ta, Ru, Ir, W, Mo, Rh, Re, Nb, Cu, Cr, V, TiN, TaN, and WN.

27. The magnetic memory element according to claim 4, wherein the spacer region is provided between the first region and the second region so that the first region and the second region are magnetically coupled to each other, and the magnetization of the second region acts on the magnetization of the first region via the spacer region.

28. The magnetic memory element according to claim 4, wherein the spacer region has a thickness of 0.1 nm to 1.5 nm.

29. The magnetic memory element according to claim 1, wherein the storage layer includes a barrier layer provided between the first region and the second region and the magnetization fixed layer, and the barrier layer includes an oxide of at least one of Mg, Ca, Li, Si, Al, Sr, Zr, Hf, Ti, Zn, Mo, Cu, Ba, Ta, W, V, Ni, Co, Mn, Cr, Fe, B, and C.

30. The magnetic memory element according to claim 1, wherein the storage layer includes a barrier layer provided between the first region and the second region and the magnetization fixed layer, and the barrier layer includes an oxide of at least one of Sc, Y, La, Ce, Pr, Nd, Pm, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb, and Lu.

31. The magnetic memory element according to claim 29, wherein the barrier layer comprises MgO.

32. The magnetic memory element according to claim 31, wherein the barrier layer further contains Fe, Co, or Mn in addition to the MgO.

33. The magnetic memory element according to claim 32, wherein the amount of Fe, Co or Mn added to the MgO of the barrier layer is 20 at % or less.

34. The magnetic memory element according to claim 1, wherein the memory layer includes a barrier layer provided on the opposite side of the magnetization fixed layer with the first region and the second region interposed therebetween, and the barrier layer includes at least one of Mg, Ca, Li, Si, Al, Sr, Zr, Hf, Ti, Zn, Mo, Cu, Ba, Ta, W, V, Ni, Co, Mn, Cr, Fe, B, and C.

35. The magnetic memory element according to claim 1, wherein the storage layer includes a barrier layer provided on the opposite side of the magnetization fixed layer with the first region and the second region interposed therebetween, and the barrier layer includes an oxide of at least one of Sc, Y, La, Ce, Pr, Nd, Pm, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb, and Lu.

36. The magnetic memory element according to claim 34, wherein the barrier layer comprises MgO.

37. The magnetic memory element according to claim 36, wherein the barrier layer further contains Fe, Co, or Mn in addition to the MgO.

38. The magnetic memory element according to claim 37, wherein the amount of Fe, Co or Mn added to the MgO of the barrier layer is 20 at % or less.

39. The magnetic memory element of claim 34, wherein the barrier layer comprises an antiferromagnetic oxide.

40. The magnetic memory element according to claim 39, wherein the antiferromagnetic oxide of the barrier layer comprises NiO, Cr2O3, CoO, Fe2O3, or Mn2O3.

41. The magnetic memory element according to claim 1, wherein the magnetization fixed layer includes a reference layer in which the magnetization direction is fixed, and the reference layer includes at least one of Fe, Co, Ni, Mn, and B.

42. The magnetic memory element according to claim 41, wherein the magnetization fixed layer includes a fixed layer that fixes the magnetization direction of the reference layer.

43. A magnetic memory element according to claim 1, wherein the memory layer includes: a barrier layer provided between the first region, the second region, and the magnetization fixed layer; a barrier layer provided on the opposite side of the magnetization fixed layer with the first region and the second region interposed therebetween; and a ferromagnetic layer provided on the opposite side of the first region and the second region with the barrier layer interposed therebetween.

44. The magnetic memory element according to claim 1, wherein the memory layer includes: a spacer layer provided on the opposite side of the magnetization fixed layer with the first region and the second region interposed therebetween; and a ferromagnetic layer provided on the opposite side of the spacer layer with the first region and the second region interposed therebetween.

45. The magnetic memory element according to claim 1, wherein the direction of magnetization of the storage layer is reversed depending on whether a voltage applied to the magnetic memory element is positive or negative.

46. ​​A storage device comprising: a magnetic memory element; and a control circuit that controls writing of data to the magnetic memory element, wherein the magnetic memory element includes a magnetization fixed layer in which the magnetization direction is fixed, and a memory layer in which the magnetization direction is reversible, and the memory layer includes a first region including a ferromagnetic material, and a second region including an antiferromagnetic material or a ferrimagnetic material.

47. The storage device described in claim 46, wherein the magnetic memory element has a resistance value corresponding to the direction of magnetization of the memory layer, and the control by the control circuit includes: applying one of a positive voltage and a negative voltage to the magnetic memory element so that the magnetic memory element has one of a low resistance value and a high resistance value; and applying the other of a positive voltage and a negative voltage to the magnetic memory element so that the magnetic memory element has the other of a low resistance value and a high resistance value.

48. A storage device as described in claim 47, wherein, when no magnetic field is applied to the magnetic memory element, when one of a positive voltage and a negative voltage is applied to the magnetic memory element, the magnetic memory element has one of a low resistance value and a high resistance value, and when the other of a positive voltage and a negative voltage is applied to the magnetic memory element, the magnetic memory element has the other of a low resistance value and a high resistance value.

49. The storage device described in claim 46, wherein the magnetic memory element has an RH loop characteristic in which the resistance value changes with hysteresis depending on the magnitude of the applied magnetic field, and the hysteresis of the RH loop characteristic when a positive voltage is applied to the magnetic memory element and the hysteresis of the RH loop characteristic when a negative voltage is applied are shifted to opposite sides from the hysteresis of the RH loop characteristic when substantially no voltage is applied to the magnetic memory element.

50. A storage device as described in claim 49, wherein the hysteresis of the RH loop characteristic when substantially no voltage is applied to the magnetic memory element crosses the magnitude of the applied magnetic field = 0, and the hysteresis of the RH loop characteristic when a positive voltage is applied to the magnetic memory element and the hysteresis of the RH loop characteristic when a negative voltage is applied do not cross the magnitude of the applied magnetic field = 0.

51. A storage device as described in claim 49, wherein the hysteresis of the RH loop characteristics when one of a positive voltage and a negative voltage is applied to the magnetic memory element is greater than the hysteresis of the RH loop characteristics when substantially no voltage is applied to the magnetic memory element, and the hysteresis of the RH loop characteristics when the other of a positive voltage and a negative voltage is applied to the magnetic memory element is smaller than the hysteresis of the RH loop characteristics when substantially no voltage is applied to the magnetic memory element.

52. The storage device described in claim 46, wherein the control by the control circuit includes: initializing the magnetic memory element to have one of a low resistance value and a high resistance value; and switching the resistance value of the magnetic memory element after initialization to the other of the low resistance value and the high resistance value.

53. The storage device according to claim 52, wherein the time for which a voltage is applied to the magnetic memory element to cause the magnetic memory element to have the one resistance value is shorter than the time for which a voltage is applied to the magnetic memory element to cause the magnetic memory element to have the other resistance value.

54. The storage device of claim 46, comprising a first memory block and a second memory block including magnetic memory elements having different sizes.

55. The storage device according to claim 46, which is incorporated into an AI chip.

56. The storage device according to claim 46, which is incorporated into a solid-state imaging device.

57. The storage device according to claim 46, which is incorporated into a CPU.

58. A method for writing data to a magnetic memory element, wherein the magnetic memory element includes: a magnetization fixed layer in which the direction of magnetization is fixed; and a memory layer in which the direction of magnetization is reversible; the memory layer includes: a first region including a ferromagnetic material; and a second region including an antiferromagnetic material or a ferrimagnetic material; the magnetic memory element has a resistance value according to the direction of magnetization of the memory layer; and the writing method includes: applying one of a positive voltage and a negative voltage to the magnetic memory element so that the magnetic memory element has one of a low resistance value and a high resistance value; and applying the other of a positive voltage and a negative voltage to the magnetic memory element so that the magnetic memory element has the other of a low resistance value and a high resistance value.

59. A writing method as described in claim 58, wherein, in a state where no magnetic field is applied to the magnetic memory element, when one of a positive voltage and a negative voltage is applied to the magnetic memory element, the magnetic memory element has one of a low resistance value and a high resistance value, and when the other of a positive voltage and a negative voltage is applied to the magnetic memory element, the magnetic memory element has the other of a low resistance value and a high resistance value.

60. A writing method as described in claim 58, wherein the magnetic memory element has an RH loop characteristic in which the resistance value changes with hysteresis depending on the magnitude of the applied magnetic field, and the hysteresis of the RH loop characteristic when a positive voltage is applied to the magnetic memory element and the hysteresis of the RH loop characteristic when a negative voltage is applied are shifted to opposite sides from the hysteresis of the RH loop characteristic when substantially no voltage is applied to the magnetic memory element.

61. A writing method as described in claim 60, wherein the hysteresis of the RH loop characteristics when substantially no voltage is applied to the magnetic memory element crosses the magnitude of the applied magnetic field = 0, and the hysteresis of the RH loop characteristics when a positive voltage is applied to the magnetic memory element and the hysteresis of the RH loop characteristics when a negative voltage is applied do not cross the magnitude of the applied magnetic field = 0.

62. A writing method as described in claim 60, wherein the hysteresis of the RH loop characteristics when one of a positive voltage and a negative voltage is applied to the magnetic memory element is greater than the hysteresis of the RH loop characteristics when substantially no voltage is applied to the magnetic memory element, and the hysteresis of the RH loop characteristics when the other of a positive voltage and a negative voltage is applied to the magnetic memory element is smaller than the hysteresis of the RH loop characteristics when substantially no voltage is applied to the magnetic memory element.

63. A writing method according to claim 58, comprising: initializing the magnetic memory element to have one of a low resistance value and a high resistance value; and switching the resistance value of the magnetic memory element after initialization to the other of the low resistance value and the high resistance value.

64. A writing method as described in claim 63, wherein the time for which a voltage is applied to the magnetic memory element to cause the magnetic memory element to have the one resistance value is shorter than the time for which a voltage is applied to the magnetic memory element to cause the magnetic memory element to have the other resistance value.

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