Circuit board, and semiconductor package comprising same

Abstract

Disclosed in an embodiment of the present invention is a circuit board comprising: a first insulating layer; a second insulating layer disposed on the first insulating layer; a dielectric layer disposed on the second insulating layer; and a first via electrode passing through the dielectric layer and the second insulating layer, wherein the first via electrode includes a first extension portion extending in a horizontal direction at an interface between the dielectric layer and the second insulating layer.

Description

Circuit boards and semiconductor packages including the same

[0001] Embodiments according to the present invention relate to circuit boards and semiconductor packages.

[0002] As the performance of electrical and electronic products continues to improve, technologies are being proposed and researched to attach a greater number of packages to a limited-size substrate. However, because typical packages are based on mounting a single semiconductor chip, achieving the desired performance is limited.

[0003] A typical circuit board or package substrate consists of a processor package, which houses the processor chip, and a memory package, which houses the memory chips, all connected together. These package substrates integrate the processor and memory chips into a single package, reducing the chip footprint and enabling high-speed signal transmission through short paths. Due to these advantages, these package substrates are widely used in mobile devices and other devices.

[0004] Meanwhile, the recent advancements in electronic devices, such as mobile devices, and the adoption of High Bandwidth Memory (HBM) have led to larger package sizes. Furthermore, as the number of functions required for application processors increases, there is a growing demand for separate processor chips for each function, along with circuit boards capable of mounting these processor chips. Even when the application processor is split into two processor chips, the number of terminals (input / output) provided on each processor chip is increasing.

[0005] In addition, due to recent trends such as 5G, the Internet of Things (IoT), increased image quality, and increased communication speed, the number of terminals on processor chips is gradually increasing due to the increase in power and signal quantities. Accordingly, the area, thickness, and circuit pattern density of circuit boards are also increasing. When the area and thickness of circuit boards increase, it becomes difficult to miniaturize products, and there are problems such as reliability issues such as warpage of the circuit board, and product price increases. Therefore, increasing the density of circuit patterns is more advantageous in terms of product price, reliability issues such as warpage, and product miniaturization than increasing the area and thickness of the circuit board. Therefore, miniaturization of circuit patterns and through-holes is required.

[0006] In particular, to eliminate power transmission noise and droop phenomenon, it is required to form a capacitor layer within the substrate.

[0007] An embodiment of the present invention implements a circuit board and a semiconductor package including the same, in which a capacitor layer is formed within a desired insulating layer to reduce an electrical connection path for the capacitor layer and suppress droop and power transmission noise.

[0008] In addition, the embodiment can implement a circuit board and a semiconductor package including the same with improved integration and increased input / output count through an embedded capacitor layer.

[0009] In addition, the embodiment can implement a circuit board and a semiconductor package including the same with improved structural reliability by improving the brittle characteristics of the dielectric layer of the capacitor layer through the elastic seed layer.

[0010] The problem to be solved in the embodiment is not limited to this, and it can be said that the purpose or effect that can be understood from the solution or implementation form of the problem described below is also included.

[0011] A circuit board according to an embodiment of the present invention includes a first insulating layer; a second insulating layer disposed on the first insulating layer; and a dielectric layer disposed on the second insulating layer; a first via electrode penetrating the dielectric layer and the second insulating layer; wherein the first via electrode includes a first extension portion extending in a horizontal direction at an interface between the dielectric layer and the second insulating layer.

[0012] A protective layer disposed on the second insulating layer is further included, wherein the protective layer can penetrate the second via land and come into contact with the dielectric layer.

[0013] It may include a capacitor layer including a first via land disposed between the first insulating layer and the second insulating layer, the dielectric layer, and a second via land disposed on the dielectric layer.

[0014] It may further include a second via electrode disposed between the first via land and the second via land.

[0015] The width of the second via electrode may gradually decrease from the upper surface of the second insulating layer toward the lower surface of the second insulating layer, and the width of the first via electrode may gradually increase from the upper surface of the second insulating layer toward the lower surface of the second insulating layer.

[0016] The second via electrode and the first via electrode may overlap the dielectric layer in a horizontal direction.

[0017] The second via electrode and the first via electrode can penetrate the dielectric layer.

[0018] The first via electrode may have a vertical length greater than that of the second via electrode.

[0019] It may include a first seed layer and a second seed layer arranged and spaced apart from each other under the second vialand.

[0020] The first seed layer can penetrate the dielectric layer.

[0021] The above first seed layer can be in contact with the above first via land.

[0022] The second seed layer may be disposed on top of the first via electrode.

[0023] The second seed layer may be disposed on the dielectric layer and may not overlap with the dielectric layer in a horizontal direction.

[0024] The first seed layer may have a vertical length greater than that of the second seed layer.

[0025] The first insulating layer and the second insulating layer may have a vertical length greater than that of the dielectric layer.

[0026] The vertical length of the dielectric layer may be less than the vertical length of the first via land or the second via land.

[0027] A protective layer is further included, which is disposed on the second insulating layer, and the protective layer may overlap the second via land, at least a portion of the first seed layer, and the second seed layer in a horizontal direction.

[0028] It may include a third insulating layer disposed on the second insulating layer, and a second via electrode penetrating the third insulating layer and the dielectric layer.

[0029] The second via electrode may include a second extension portion extending in a horizontal direction at the interface between the dielectric layer and the third insulating layer.

[0030] The first extension portion and the second extension portion may be positioned adjacent to the dielectric layer.

[0031] An embodiment of the present invention provides a circuit board and a semiconductor package including the same, in which a capacitor layer is formed within a desired insulating layer to reduce an electrical connection path for the capacitor layer and suppress droop and power transmission noise.

[0032] Additionally, the embodiment can provide a circuit board and a semiconductor package including the same with improved integration and increased input / output count through an embedded capacitor layer.

[0033] In addition, the embodiment can provide a circuit board and a semiconductor package including the same with improved structural reliability by improving the brittle characteristics of a dielectric layer of a capacitor layer through an elastic seed layer.

[0034] The various advantageous and beneficial effects of the present invention are not limited to the above-described contents, and will be more easily understood in the course of explaining specific embodiments of the present invention.

[0035] Figure 1 is a plan view of a circuit board according to an embodiment of the present invention;

[0036] Figure 2 is a perspective view of a circuit board according to an embodiment of the present invention;

[0037] Figure 3 is a cross-sectional view of a circuit board according to the first embodiment of the present invention.

[0038] FIG. 4 is a side view of a circuit board according to the first embodiment of the present invention;

[0039] Figure 5 is an enlarged view of K3 of Figure 4,

[0040] Figure 6 is an enlarged view of K1 in Figure 3,

[0041] Figure 7 is an enlarged view of K2 in Figure 3,

[0042] Fig. 8 is a modified example of Fig. 6,

[0043] Figures 9a to 9x are drawings explaining a method for manufacturing a circuit board according to the first embodiment.

[0044] Fig. 10 is a cross-sectional view of a circuit board according to the second embodiment,

[0045] Fig. 11 is a perspective view of a first via electrode and a second via electrode in a circuit board according to a second embodiment.

[0046] Figure 12 is an enlarged view of K4 in Figure 10,

[0047] Figure 13 is an enlarged view of K5 in Figure 10,

[0048] Fig. 14 is an enlarged view of K6 in Fig. 10,

[0049] Figure 15 is a photograph of Figure 11,

[0050] Fig. 16 is a cross-sectional view of a circuit board according to a third embodiment;

[0051] Figure 17 is an enlarged view of K7 of Figure 16.

[0052] The present invention can be modified in various ways and has various embodiments, and specific embodiments are illustrated and described in the drawings. However, this is not to be construed as a specific embodiment of the present invention.

[0053] It is not intended to be limited to the embodiments, and should be understood to include all modifications, equivalents, or substitutes included in the spirit and technical scope of the present invention.

[0054] Terms including ordinal numbers, such as "second," "first," etc., may be used to describe various components, but the components are not limited by the terms. The terms are used solely to distinguish one component from another. For example, without departing from the scope of the present invention, a second component may be referred to as "first component," and similarly, a first component may also be referred to as "second component." The term "and / or" includes a combination of multiple related items described herein or any of multiple related items described herein.

[0055] When a component is referred to as being "connected" or "connected" to another component, it should be understood that it may be directly connected or connected to that other component, but that there may be other components intervening. Conversely, when a component is referred to as being "directly connected" or "connected" to another component, it should be understood that there are no other components intervening.

[0056] The terminology used in this application is only used to describe specific embodiments and is not intended to limit the present invention. The singular expression includes the plural expression unless the context clearly indicates otherwise. In this application, it should be understood that the terms "comprise" or "have" indicate the presence of a feature, number, step, operation, component, part, or combination thereof described in the specification, but do not preclude the possibility of the presence or addition of one or more other features, numbers, steps, operations, components, parts, or combinations thereof.

[0057] Unless otherwise defined, all terms used herein, including technical or scientific terms, have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. Terms defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant technology, and shall not be interpreted in an idealized or overly formal sense unless explicitly defined herein.

[0058] Hereinafter, embodiments will be described in detail with reference to the attached drawings. Regardless of the drawing numbers, identical or corresponding components are given the same reference numbers, and redundant descriptions thereof will be omitted.

[0059] Before describing the embodiments, an electronic device to which the circuit board and semiconductor package of the embodiments are applied will be briefly described. The electronic device includes a main board (not shown). The main board may be physically and / or electrically connected to various components. For example, the main board may be connected to the semiconductor package of the embodiments. The semiconductor package may further include a circuit board, a plurality of semiconductor elements arranged on the circuit board, and a connecting member electrically connecting the plurality of semiconductor elements.

[0060] The circuit board may include a plurality of laminated insulating layers, circuit patterns arranged within each of the plurality of laminated insulating layers, and via electrodes for connecting the circuit patterns arranged within each of the insulating layers.

[0061] The semiconductor device may be mounted on a circuit board, and may be a semiconductor chip in the form of an integrated circuit (IC) in which hundreds to millions or more active and / or passive devices are integrated into a single chip. For example, the semiconductor device may be a logic chip, a memory chip, etc. The logic chip may be a central processor (CPU), a graphics processor (GPU), etc. For example, the logic chip may be an application processor (AP) chip including at least one of a central processor (CPU), a graphics processor (GPU), a digital signal processor, an encryption processor, a microprocessor, a microcontroller, or an analog-to-digital converter, an application-specific IC (ASIC), a field programmable gate array (FPGA), etc., or a chip set including a specific combination of the above-mentioned. In addition, the semiconductor device may be a memory device such as a high bandwidth memory (HBM).

[0062] A connecting member is a component that functions to electrically connect a plurality of semiconductor elements, and can be placed between the semiconductor elements and the circuit board. For example, the connecting member can be embedded in the circuit board, or can be placed on the circuit board. When embedded in the circuit board, it can have the advantage of reducing the thickness of the semiconductor package. The connecting member can be formed of silicon, but is not limited thereto, and can be formed of an organic material, and since it functions to electrically interconnect a plurality of semiconductor elements, it can be referred to as a bridge.

[0063] Additionally, the connecting member may be placed on a circuit board. When placed on a circuit board, the connecting member may be covered with a molding member, and the circuit board, semiconductor element, and connecting member may be electrically interconnected through a Through Mold Via (TMV) penetrating the molding member. Additionally, a redistribution layer may be placed between the molding member and the semiconductor element.

[0064] Meanwhile, the product group to which the semiconductor package of the embodiment is applied may be any one of CSP (Chip Scale Package), FC-CSP (Flip Chip-Chip Scale Package), FC-BGA (Flip Chip Ball Grid Array), POP (Package On Package), and SIP (System In Package), but is not limited thereto.

[0065] Additionally, the electronic device may be a smart phone, a personal digital assistant, a digital video camera, a digital still camera, a vehicle, a high-performance server, a network system, a computer, a monitor, a tablet, a laptop, a netbook, a television, a video game, a smart watch, an automotive device, etc. However, the present invention is not limited thereto, and it is to be understood that the electronic device may be any other electronic device that processes data.

[0066] Hereinafter, a circuit board according to an embodiment of the present invention may include a first build-up layer and a second build-up layer disposed on the first build-up layer. In addition, the first build-up layer and the second build-up layer may each include a plurality of laminated insulating layers. That is, the circuit board may be formed of insulating layers of the first build-up layer and the second build-up layer (or the first build-up layer and / or the second build-up layer). In addition, the upper build-up layer and the lower build-up layer may be distinguished by a structure in which the expansion directions of via holes within the layers are opposite to each other. For example, the width or area of ​​the via hole may increase (increase) toward the upper side of the upper build-up layer. In addition, the width or area of ​​the via hole may decrease (increase) toward the upper side of the lower build-up layer. In addition, each build-up layer may correspond to an insulating layer other than the core layer. The first and second insulating layers described below may correspond to the first and second build-up layers. Furthermore, the build-up layer may be a different layer from the protective layer. A detailed description thereof will be provided below.

[0067] FIG. 1 is a plan view of a circuit board according to an embodiment of the present invention, FIG. 2 is a perspective view of a circuit board according to an embodiment of the present invention, and FIG. 3 is a cross-sectional view of a circuit board according to a first embodiment of the present invention.

[0068] Referring to FIGS. 1 to 3, a circuit board (100) according to an embodiment may include an insulating layer (110), an electrode portion (120), and a capacitor layer (CAL). Furthermore, the circuit board (100) may include a protective layer (SR) disposed on the electrode portion (120). In addition, a semiconductor chip connected to a via electrode may be further disposed on the upper portion of the circuit board (100).

[0069] First, the insulating layer (110) may include multiple insulating layers. As an example, the insulating layer (110) may include a first insulating layer (111) and a second insulating layer (112).

[0070] The second insulating layer (112) may be positioned on the upper side of the first insulating layer (111). The lower surface (BS2) of the second insulating layer (112) may be in contact with the upper surface (US1) of the first insulating layer (111), and may form the same surface. For example, the first insulating layer (111) and the second insulating layer (112) may be sequentially arranged along the stacking direction or the vertical direction (X-axis direction).

[0071] Each build-up layer includes an insulating layer. For example, if a core layer exists in a circuit board, an upper build-up layer may be positioned above the core layer, and a lower build-up layer may be positioned below the core layer. In this case, the upper build-up layer and the lower build-up layer each include multiple insulating layers.

[0072] In addition, as described above, the build-up layer is a different layer from the above-described protective layer (SR), and the uppermost / lowest surface of the build-up layer (or insulating layer) corresponds to the uppermost / lowest surface of the build-up layer (insulating layer) placed on the top, and does not mean the uppermost / lowest surface of the protective layer (SR). In other words, the uppermost surface of the insulating layer of the circuit board means the uppermost / lowest surface of the build-up layer, not the protective layer.

[0073] And the insulating layer (110) may include a thermosetting resin such as an epoxy resin or a thermoplastic resin such as a polyimide. In addition, the insulating layer (110) may further include a reinforcing material in the resin. The reinforcing material may be, for example, a fabric reinforcing material, an inorganic filler, etc. The fabric reinforcing material may be glass fiber, and the glass fiber may be impregnated into the resin to form a prepreg (PPG).

[0074] For example, the insulating layer (110) may be formed of any insulating resin, such as a thermosetting and / or photocurable resin. As the thermosetting resin, ABF (Ajinomoto Build-up Film), a product released by Ajinomoto, can be used, and a material such as prepreg (PPG) containing glass fiber can be used. As the photocurable resin, any insulating resin, such as PID (Photo Imageable Dielectric) resin, can be used. The above-described arbitrary insulating resin may be, for example, an epoxy resin, a bismaleimide triazine resin (BT resin), a phenol resin, etc., and may include an inorganic filler such as silica. When the insulating resin is used as a core, it may include a reinforcing material formed of glass fiber or aramid fiber. For example, the insulating layer (110) may use ABF (Ajinomoto Build-up Film), a product released by Ajinomoto Co., Ltd., as an example, and FR-4, BT (Bismaleimide Triazine), PID (Photo Imageable Dielectric resin), BT, etc. may be used. For example, the insulating layer (110) may include a plurality of layers composed of ABF.

[0075] Each insulating layer may be made of the same or different material. For example, the second insulating layer may be made of the same or different material from the other insulating layers.

[0076] And the electrode portion (120) may include a circuit pattern (or circuit pattern layer), a pad, and a via electrode. The wiring may correspond to an 'electrode pattern', a 'pattern', a 'line', etc.

[0077] As an example, the electrode portion (120) may include a wiring electrode and a via electrode. The wiring electrode may include a wiring (or circuit pattern, pattern) and a pad arranged on an insulating layer. The via electrode may be positioned within a through hole or a via (Vertical Interconnect Access) hole formed in the insulating layer. Through the via electrode, an electrical connection may be implemented within the insulating layer or above or below the insulating layer.

[0078] In addition, the pads arranged on the outside of the electrode portion (120) can be bonded to semiconductor elements, substrates, boards, etc. with solder, wires, conductive adhesives, etc., and can be arranged with a width larger than the width of the circuit pattern in order to solve problems such as securing yield. However, the present invention is not limited thereto, and may have the same width as the width of the circuit pattern depending on the technical limitations of the bonding process. In addition, the pads arranged on the inside function to connect the via electrodes and the circuit pattern. When the via electrodes are arranged with a width wider than the circuit pattern, pads having a width wider than the circuit pattern are provided for positional alignment during the manufacturing process of the via electrodes to be arranged on each circuit pattern. Accordingly, each via electrode may have an upper surface located on the same plane as the lower surface of the upper pad directly in contact with the via electrode, and a lower surface located on the same plane as the upper surface of the lower pad directly in contact with the lower surface of the via electrode. Here, the lower surface of the upper pad and the upper surface of the lower pad do not necessarily mean a flat surface, but should also be understood as a concave or convex surface that may appear depending on various processes.

[0079] As an example, the electrode portion (120) may include a first electrode portion (121), a second electrode portion (122), and a third electrode portion (123). The electrode portion may include a wiring portion and a via electrode.

[0080] The first electrode portion (121) may include a first via electrode (121a), a first wiring portion (121b), and an additional via electrode (121c). In addition, the second electrode portion (122) may include a second via electrode (122a). Furthermore, the second electrode portion (122) may include a second layer (L2) corresponding to the second wiring portion. The third electrode portion (123) may include a third via electrode (123a) and a third wiring portion (123b).

[0081] The first electrode portion (121) may be located on the second insulating layer (112). The first electrode portion (121) may include a first via electrode (121a) and a first wiring portion (121b). The second electrode portion (122) may include a second via electrode (122a) and may be located on the upper portion of the dielectric layer (DLL). The third electrode portion (123) may be located on the first insulating layer (111). The third electrode portion (123) may include a third via electrode (123a) and a third wiring portion (123b).

[0082] In an embodiment, the first via electrode (121a) may penetrate the dielectric layer (DLL) and an insulating layer (e.g., a second insulating layer) in contact with the dielectric layer (DLL). For example, the first via electrode (121a) may penetrate the dielectric layer (DLL) and the second insulating layer (112). In addition, the first via electrode (121a) may be positioned between the lower surface of the dielectric layer (DLL) and the lower surface (BS2) of the second insulating layer (112). In addition, the first via electrode (121a) may penetrate the upper surface (US2) and the lower surface (BS2) of the second insulating layer (112). Furthermore, the first via electrode (121a) may include an extension portion (or first extension portion, 121ab) extending in the horizontal direction (Y-axis direction) from the interface (IL) of the dielectric layer (DLL) and the second insulating layer (112). A description of this will be given later. In addition, the interface (IL) between the dielectric layer (DLL) and the second insulating layer (112) of the first via electrode (121a) may correspond to the upper surface (US2) of the second insulating layer (112).

[0083] An additional via electrode (121c) may be placed between the first via land (L1) and the first wiring portion (121b). The additional via electrode (121c) may penetrate the second insulating layer (112) to electrically connect the first via land (L1) and the first wiring portion (121b).

[0084] Furthermore, the additional via electrode (121c) may partially penetrate the second insulating layer (112) and be spaced apart from the dielectric layer (DLL) in the vertical direction.

[0085] The second via electrode (122a) can penetrate the dielectric layer (122a). And the second via electrode (122a) can be arranged between the first layer (L1) and the second layer (L2). In addition, the second via electrode (122a) can be positioned on the second insulating layer (112). And in the third electrode portion (123), the third via electrode (123a) is positioned between the upper surface (US1) and the lower surface (BS1) of the first insulating layer (111) and can penetrate at least a portion of the first insulating layer (111).

[0086] The capacitor layer (CAL) may be located on, under, or within the insulating layer (110). For example, the capacitor layer (CAL) may be located on the second insulating layer (112).

[0087] A capacitor layer (CAL) according to an embodiment may include a first layer (L1), a dielectric layer (DLL), and a second layer (L2). In the capacitor layer (CAL), the first layer (L1), the dielectric layer (DLL), and the second layer (L2) may be sequentially stacked or positioned along the vertical direction (X-axis direction). Accordingly, the dielectric layer (DLL) may be positioned between the first layer (L1) and the second layer (L2). A capacitance may be formed by the dielectric layer (DLL) between the first layer (L1) and the second layer (L2). The first layer (L1) may be positioned between the first insulating layer (111) and the second insulating layer (112). For example, the first layer (L1) may be positioned within the second insulating layer (112). The second layer (L2) may be positioned on the dielectric layer (DLL). Accordingly, the dielectric layer (DLL) may be located between the first layer (L1) and the second layer (L2).

[0088] The first and second layers (L1, L2) can be directly connected to the via electrode. Through the first and second layers (L1, L2), functions such as ensuring the positional alignment of the via electrode and the function of a circuit electrically connected to the via electrode can be implemented. In addition, the first and second layers here can function as electrodes of a capacitor.

[0089] The second layer (L2) may be positioned on the upper surface (US2) of the second insulating layer (112). Furthermore, the second layer (L2) may be positioned between the upper surface of the second protective layer (SR2) and the first layer (or dielectric layer). Furthermore, the capacitor layer (CAL) may be positioned on the second insulating layer (112). For example, at least a portion of the capacitor layer (CAL) may be embedded in the second insulating layer (112).

[0090] In addition, in the present embodiment, the capacitor layer (CAL) may be a layer or structure that is continuously or connected on the second insulating layer (112). However, the present invention is not limited thereto, and the dielectric layer (DLL) of the capacitor layer (CAL) may be discontinuously disposed on the second insulating layer (112). For example, the capacitor layer may be discontinuously disposed, or a plurality of capacitor layers may be spaced apart from each other, or may be disposed on the second insulating layer (112) or within a third insulating layer described below.

[0091] Furthermore, the first layer and the second layer may correspond to the first via land and the second via land described later. The first layer may be mixed with the first via land, the first via land layer, the first electrode layer, the first electrode, etc. The second layer may be mixed with the second via land, the second via land layer, the second electrode layer, the second electrode, etc. In addition, the capacitor structure may correspond to a capacitor, a capacitor layer, a capacitor region, etc.

[0092] In addition, the first layer and the second layer refer to one electrode (layer) and the other electrode (layer) of the capacitor layer that perform the function of a capacitor. Furthermore, although the via electrode connected to each of the first layer and the second layer of the capacitor is illustrated as a single electrode, it may be connected singly or in multiples depending on the circuit connection (e.g., series connection, parallel connection, etc.).

[0093] A circuit board according to an embodiment can suppress droop and power transmission noise by embedding a capacitor layer therein. More specifically, when a processor of an electronic device or a package board continues to draw more power, the first droop and power transmission noise can be obstacles. Specifically, the first droop can occur when a circuit within a die or semiconductor device pulls power. To improve this first droop, a capacitor can be added to a circuit board on which a die or semiconductor device is provided, as in the embodiment. In particular, it may be desirable to add the capacitor near the die or semiconductor device, which is the source of the droop. In this case, when the capacitor is placed on the die side or the side land of the board, the electrical path between the capacitor on the die and the land side (or the die side) becomes longer, which may reduce the additional effect of the capacitor due to additional parasitic inductance, etc. Additionally, the land-side capacitor may cause interference with the interface of the circuit board or package substrate. Thus, the above-described problems can be easily solved by the capacitor layer.

[0094] In addition, a high-k dielectric layer can be applied to form a large capacitance capacity. Furthermore, in the embodiment, the capacitor layer can have any suitable shape and dimension. For example, the capacitor layer can have a rectangular or circular shape in plan view. Furthermore, the capacitor layer can be arranged at any position within the circuit board. For example, in order to reduce the electrical path, the capacitor layer can be located in a layer adjacent to the upper die within the circuit board. That is, the capacitor layer is located in an area adjacent to the die in the insulating layer, so that electrical performance degradation can be suppressed.

[0095] The third via electrode (123a) may be disposed between the lower surface (BS1) of the first insulating layer (111) and the upper surface (US1) of the first insulating layer (111) or between the lower surface (BS1) of the first insulating layer (111) and the upper surface (US2) of the second insulating layer (112). In addition, the third via electrode (123a) may penetrate at least a portion of the first insulating layer (111).

[0096] Additionally, in this specification, the via electrode may be located within a via hole formed in each insulating layer, etc. This corresponds to the via electrode penetrating at least a portion of each insulating layer, etc. This is described as a reference in this specification.

[0097] And in the circuit board (100), among the plurality of via electrodes, the first via electrode (121a), the second via electrode (122a), and the third via electrode (123a) may have different positions in the vertical direction. Specifically, the first via electrode (121a), the second via electrode (122a), and the third via electrode (123a) penetrating the second insulating layer (112) may have different lengths in the vertical direction (X-axis direction). Alternatively, the first via electrode (121a), the second via electrode (122a), and the third via electrode (123a) may have different thicknesses. In addition, the first via electrode (121a), the second via electrode (122a), and the third via electrode (123a) may be spaced apart from each other in the horizontal direction (Y-axis direction).

[0098] In an embodiment, the thickness of the first via electrode (121a), the thickness of the second via electrode (122a), and the thickness of the third via electrode (123a) may be different from each other.

[0099] For example, the thickness of the first via electrode (121a) may be greater than the thickness of the second via electrode (122a). And the thickness of the third via electrode (123a) may be greater than the thickness of at least one of the first via electrode (121a) and the second via electrode (122a). For example, the thickness of the third via electrode (123a) may be greater than the thickness of the second via electrode (122a). By this configuration, at least one die (or semiconductor element) disposed on the upper portion of the circuit board (100) can be easily connected to the capacitor.

[0100] In addition, as an example, the third via electrode (123a) may not overlap with the first via electrode (121a) and the second via electrode (122a) in the horizontal direction (Y-axis direction). And the third via electrode (123a) may not overlap with the capacitor layer (CAL) in the horizontal direction (Y-axis direction).

[0101] Meanwhile, the first via electrode (121a) may overlap with at least a portion of the capacitor layer (CAL) in the horizontal direction (Y-axis direction). The first via electrode (121a) may overlap with the dielectric layer (DLL) and the first layer (L1) of the capacitor layer (CAL) in the horizontal direction (Y-axis direction).

[0102] In addition, the width of the body portion of the first via electrode (121a) may gradually decrease from the upper surface (US2) of the second insulating layer (112) toward the lower surface (BS2) of the second insulating layer (112). For example, the width (or diameter, etc.) of the first via electrode (121a) may increase in the vertical direction.

[0103] Additionally, the width of the second via electrode (122a) may gradually decrease from the upper surface (US2) of the second insulating layer (112) toward the lower surface (BS2) of the second insulating layer (112). Alternatively, the width of the second via electrode (122a) may gradually increase in the vertical direction.

[0104] In addition, the width of the third via electrode (123a) may gradually decrease from the upper surface (US2) of the second insulating layer (112) toward the lower surface (BS1) of the first insulating layer (111) (or from the upper surface (or lower surface) of the second insulating layer to the upper surface (or lower surface) of the first insulating layer). Alternatively, the width of the third via electrode (123a) may gradually increase in the vertical direction.

[0105] The protective layer (SR) may be further disposed on the uppermost or lowermost portion of the insulating layer (110). The protective layer (SR) may include a first protective layer (SR1) and a second protective layer (SR2). The first protective layer (SR1) may be positioned below the first insulating layer (111). And the second protective layer (SR2) may be positioned on the second insulating layer (112). In addition, the second protective layer (SR2) may be disposed on the capacitor layer (CAL) to cover the capacitor layer (CAL).

[0106] The outermost protective layer can penetrate the via land and come into contact with the dielectric layer. For example, the dielectric layer (DLL) can be located on the second insulating layer (112). And the second protective layer (SR2) can penetrate the second layer (L2), which is the second via land. And the second protective layer (SR2) can come into contact with the dielectric layer (DLL). The dielectric layer (DLL) can be located within the insulating layer (110) or on the outermost side of the insulating layer in the circuit board (100). Accordingly, when the protective layer (SR) is formed, a portion of the second layer (L2) may be opened to expose the outermost dielectric layer (DLL).

[0107] The protective layer (SR) can have the function of protecting the pad from external moisture or contaminants, and to prevent a short circuit problem when joining the semiconductor element and / or the main board and the circuit board, the protective layer (SR) can be provided with a solder resist, for example. Specifically, the semiconductor element and / or the main board, etc. have a plurality of terminals for connecting the circuit board. In addition, the plurality of terminals can be arranged at a high density. When the plurality of terminals and the pads of the circuit board are joined, solder can be used, for example. When solder is used, a solder short circuit problem may occur between terminals with a high density, and thus, a solder resist that does not have good wettability with the solder can be arranged to solve this short circuit problem. In addition, the protective layer (SR) can be formed of a material that has insulating properties for electrical connection. The protective layer (SR) can include a resin, a curing agent, a photoinitiator, a pigment, a solvent, a filler, an additive, an acrylic monomer, etc. Additionally, the third insulating layer (not shown) may include any one of a photo solder resist layer, a cover-lay, and a polymer material. Furthermore, the insulating layer or protective layer (SR) located in the outer laminated region of the circuit board may have an opening. Through the opening, it may be electrically connected to other semiconductor elements, circuit boards, etc.

[0108] Additionally, the protective layer (SR) may include connecting grooves for electrical connection with each electrode portion, chip, die, etc. For example, there may be a plurality of connecting grooves (CG1, CG2, CG3). The connecting groove (CG1) may include a first connecting groove (CG1), a second connecting groove (CG2), and a third connecting groove (CG3).

[0109] A first connection groove (CG1) may include a first connection terminal (PP1) and a second connection terminal (PP2). The first connection terminal (PP1) and the second connection terminal (PP2) may be connected to a first layer (L1) and a second layer (L2), respectively. Furthermore, a chip may be mounted in the first connection groove (CG1). Accordingly, the first connection terminal (PP1) and the second connection terminal (PP2) may be electrically connected to one terminal and the other terminal of the chip, respectively. Accordingly, since a capacitance is formed between the first layer (L1) and the second layer (L2), the chip may be electrically connected to the capacitor.

[0110] The second connection home (CG2) may include a third connection terminal (PP3) and a fourth connection terminal (PP4). The third connection terminal (PP3) and the fourth connection terminal (PP4) may perform the same functions as the first connection terminal and the second connection terminal described above.

[0111] Additionally, as described above, when a dielectric layer (DLL) is placed on the outermost side of the insulating layer or build-up layer, the electrical connection distance between the semiconductor chip and the capacitor layer can be reduced. As a result, improved electrical performance can be provided.

[0112] Additionally, as described below, even if a dielectric layer (DLL) is placed between stacked insulating layers, electrical performance can be improved by reducing the electrical connection path with the capacitor by placing the dielectric layer (DLL) adjacent to the outermost insulating layer.

[0113] Additionally, the third connection home (CG3) may be a home where various elements other than capacitor connections are placed.

[0114] FIG. 4 is a side view of a circuit board according to the first embodiment of the present invention.

[0115] Referring to Fig. 4, the outermost side of the protective layer may be located on the inner side of the outermost side of the dielectric layer (DLL) or the insulating layer (111, 112). However, this is not limited thereto, and the outermost side of the protective layer may be formed as the same surface as the outermost side of the insulating layer (111, 112) or the outermost side of the dielectric layer (DLL).

[0116] Furthermore, the first layer (L1) may be exposed on the outermost side of the circuit board (100). When the first layer (L1) is exposed on the outermost side of the circuit board (100), the first layer (L1) exposed on the outermost side may be a dummy. Alternatively, the first layer (L1) may be covered by the second insulating layer (112). Accordingly, the first layer (L1) may not be exposed on the circuit board (100).

[0117] Additionally, the first wiring portion (121b) may be exposed on the outermost side of the circuit board (100). When the first wiring portion (121b) is exposed on the outermost side of the circuit board (100), the first wiring portion (121b) exposed on the outermost side may be a dummy portion. Alternatively, the first wiring portion (121b) may be covered by the first insulating layer (11). Accordingly, the first wiring portion (121b) may not be exposed on the circuit board (100).

[0118] Fig. 5 is an enlarged view of K3 in Fig. 4, Fig. 6 is an enlarged view of K1 in Fig. 3, Fig. 7 is an enlarged view of K2 in Fig. 3, and Fig. 8 is a modified example of Fig. 6.

[0119] Referring further to FIG. 5, the first via electrode (121a) according to the embodiment can penetrate the dielectric layer (DLL) and the second insulating layer (112) as described above. The first via electrode (121a) can include a body portion (121aa) and an extension portion (121ab).

[0120] The body portion (121aa) may have a cylindrical or truncated cone shape. The extension portion (121ab) may extend in the horizontal direction (Y-axis direction) at the interface between the dielectric layer (DLL) and the second insulating layer (112). The extension portion (121ab) may be located on the outer surface of the body portion (121aa).

[0121] Furthermore, the extension portion (121ab) may be positioned adjacent to the dielectric layer (DLL). For example, the extension portion (121ab) may be positioned between the first bisector (HL1) and the dielectric layer (DLL). That is, the extension portion (121ab) may be positioned closer to the dielectric layer (DLL) among the dielectric layer (DLL) and the first insulating layer (111). The first bisector (HL1) may correspond to a line that vertically bisects the first via electrode (121a).

[0122] The extension portion (121ab) may overlap with the dielectric layer (DLL) and the second insulating layer (112) in the horizontal direction (Y-axis direction). The extension portion (121ab) may overlap with a portion of the dielectric layer (DLL) in the horizontal direction (Y-axis direction). In addition, the extension portion (121ab) may overlap with at least a portion of the second insulating layer (112) in the horizontal direction (Y-axis direction).

[0123] For example, the extension portion (121ab) may include a first extension region (EP1) that is in horizontal contact with the dielectric layer (DLL) and a second extension region (EP2) that is in horizontal contact with the second insulating layer (112). The second extension region (EP2) may be a region of the extension portion (121ab) other than the first extension region (EP1).

[0124] The length (d1) in the vertical direction (X-axis direction) of the first extension region (EP1) may be smaller than the length (d2) in the vertical direction (X-axis direction) of the second extension region (EP2). That is, the extension portions (121ab) may be formed in greater numbers in the second insulating layer (112) than in the brittle dielectric layer (DLL) at the interface between the dielectric layer (DLL) and the second insulating layer (112).

[0125] Additionally, the volume of the first extension region (EP1) may be smaller than the volume of the second extension region (EP2). However, the length in the horizontal direction of the first extension region (EP1) may be larger than the length in the horizontal direction of the second extension region (EP2). That is, the extension portion (121ab) may have a maximum length in the horizontal direction (Y-axis direction) in the first extension region (EP1).

[0126] The bonding area between the second insulating layer (112) and the first via electrode (121a) can be increased by the first extension portion (121ab). Accordingly, structural reliability can be improved.

[0127] Referring to FIG. 6, the first via electrode (121a) and the second via electrode (122a) may have opposite directions of diameter expansion. In other words, the directions of width increase in the first via electrode (121a) and the second via electrode (122a) may be opposite to each other. In an embodiment, the width of the second via electrode (122a) may gradually decrease from the upper surface of the second insulating layer (112) toward the lower surface of the second insulating layer (112). In contrast, the width of the first via electrode (121a) may gradually increase from the upper surface of the second insulating layer (112) toward the lower surface of the second insulating layer (112). In this case, the gradually increasing width is described based on the body portion (121aa) of the first via electrode (121a). Furthermore, the width (Wa) of the first via electrode (121a) may be maximum at the extension portion (121ab) or at the lower surface. For example, the first via electrode (121a) may have the maximum width (Wa') of the first via electrode (121a) at the extension portion (121ab). In particular, corresponding to the boundary between the dielectric layer (DLL) and the second insulating layer (112), the first via electrode (121a) may have the maximum width (Wa') between the first bisector (HL1) and the dielectric layer (DLL). Accordingly, the first via electrode (121a) may have a form in which the width increases from the upper surface to the lower surface of the second insulating layer (112), then decreases, and then increases again.

[0128] In contrast, the second via electrode (122a) may have a width (Wb) that decreases toward one side from the upper surface of the second insulating layer (112).

[0129] In addition, the first via electrode (121a) and the second via electrode (122a) can penetrate the dielectric layer (DLL). Accordingly, the second via electrode (122a) and the first via electrode (121a) can overlap the dielectric layer (DLL) in the horizontal direction (Y-axis direction). However, the first via electrode (121a) can also penetrate the second insulating layer (112) that is in contact with the dielectric layer (DLL).

[0130] The outer surfaces of the first via electrode (121a) and the second via electrode (122a) that horizontally overlap with the dielectric layer (DLL) may be arranged at different angles. For example, the angle formed by the first via electrode (121a) and the upper surface of the dielectric layer (DLL) may be different from the angle formed by the second via electrode (122a) and the upper surface of the dielectric layer (DLL). That is, even if the first via electrode (121a) and the second via electrode (122a) have the same minimum width (or area), the first via electrode (121a) and the second via electrode (122a) may have different maximum areas based on the same height.

[0131] And the first insulating layer (111) and the second insulating layer (112) may have a vertically longer length than the dielectric layer (DLL). For example, the vertically longer length of the first insulating layer (111) may be greater than the vertically longer length of the dielectric layer (DLL). In addition, the vertically longer length of the second insulating layer (112) may be greater than the vertically longer length of the dielectric layer (DLL).

[0132] Additionally, the length in the vertical direction (X-axis direction) of the dielectric layer (DLL) may be smaller than the length in the vertical direction of the first via land (L1) or the second via land (L2). By this configuration, capacitance formation can be achieved within the circuit board. Therefore, a circuit board with a thin thickness can be provided.

[0133] In addition, the circuit board (100) may include a first seed layer (SE1) and a second seed layer (SE2) that are disposed below the second via land (L2) and are spaced apart from each other. The first seed layer (SE1) may be positioned below the first via land (L2) and adjacent to the dielectric layer (DLL) at the second via electrode (122a). That is, the first seed layer (SE1) may be positioned in a lower region where the dielectric layer (DLL) is in contact with the second via land (L2) and the second via electrode (122a). The first seed layer (SE1) may penetrate the dielectric layer (DLL). In addition, the first seed layer (SE1) may be in contact with the first via land (L1) to form a capacitance.

[0134] The second seed layer (SE2) may be positioned on top of the first via electrode (121a). The second seed layer (SE2) may be horizontally misaligned with the first via electrode (121a).

[0135] In contrast, the first seed layer (SE1) may partially overlap the first via electrode (121a) in the horizontal direction.

[0136] Additionally, the second seed layer (SE2) may be disposed on the dielectric layer (DLL) and may not overlap with the dielectric layer (DLL) in the horizontal direction.

[0137] The first seed layer (SE1) and the second seed layer (SE2) may be made of a metal material. For example, the first seed layer (SE1) and the second seed layer (SE2) may include a first metal. The first metal may be made of nickel (Ni). The first metal may have greater ductility than the second metal described below. Accordingly, the first seed layer (SE1) and the second seed layer (SE2) are disposed on a brittle dielectric layer (DLL), thereby suppressing cracks or breakage in the dielectric layer (DLL). As a result, the durability of the circuit board (100) against bending, etc. may be further improved.

[0138] The upper regions of the first seed layer (SE1) and the second seed layer (SE2) in the second via land (L2) and the second via electrode (122a) may be formed of a second metal different from the first metal. For example, the second metal may be copper (Cu).

[0139] Additionally, the first seed layer (SE1) may have a longer length in the vertical direction than the second seed layer (SE2).

[0140] And, as described above, when the dielectric layer (DLL) is positioned on the outermost insulating layer (second insulating layer), the protective layer (second protective layer) can overlap the second via land (L2) in the horizontal direction.

[0141] Furthermore, the protective layer (second protective layer) may overlap not only the second via land (L2), but also at least a portion of the first seed layer (SE1) and the second seed layer (SE2) in the horizontal direction (Y-axis direction).

[0142] Referring to Fig. 7, a dielectric layer (DLL) may be interposed between the first layer (L1) and the second layer (L2) to form a storage capacity or capacitance. In other words, as described above, a capacitance may be formed by the dielectric layer (DLL) between the second via land (L2) and the first via land (L1). In addition, the capacitor layer (CAL) may function as a capacitor. The size of such a capacitor layer or capacitor needs to be further reduced in order to meet the needs of substrates and semiconductor devices requiring increased integration.

[0143] Methods for improving the storage capacity of such capacitors include increasing the effective area of ​​the first and second layers (via lands, electrodes), reducing the thickness of the dielectric film, and using a high-k material as the dielectric film. In particular, when the high-k material is used as the dielectric film, it is possible to sufficiently reduce the leakage current that frequently occurs between the first layer, which is the lower electrode, and the second layer, which is the upper electrode, while maintaining a thin equivalent oxide thickness. In an embodiment, a high-k material may be used as the dielectric film. For example, the high-k material may include, for example, tantalum oxide, aluminum oxide, zirconium oxide, hafnium oxide, titanium oxide, etc.

[0144] In addition, the circuit board according to the embodiment can solve the problems of reduced circuit board integration and input / output count due to the volume of the capacitor as described above when mounting a high-capacity capacitor. In other words, the capacitor layer according to the embodiment can increase the circuit board integration and input / output count while providing improved storage capacity.

[0145] A capacitance can be formed in a region where a first via land (L1), a dielectric layer (DLL), and a second via land (L2) overlap in a vertical direction (X-axis direction). Furthermore, a size of the capacitance can correspond to a size of a region where the first via land (L1), a dielectric layer (DLL), and a second via land (L2) overlap in a vertical direction (X-axis direction).

[0146] And the areas of the first layer (L1) and the second layer (L2) may be the same or different. For example, the area of ​​the first layer (L1) may be smaller than the area of ​​the second layer (L2). After the first layer (L1) and the dielectric layer (DLL) are formed, the second layer (L2) may be formed by etching. For example, the area of ​​the upper surface of the first layer (L1) may be smaller than the area of ​​the upper surface of the second layer (L2). In addition, the area of ​​the lower surface of the first layer (L1) may be smaller than the area of ​​the lower surface of the second layer (L2). In addition, the planar area of ​​the dielectric layer (DLL) may be larger than the area of ​​the first layer (L1) or the second layer (L2). Accordingly, capacitance can be formed by controlling the formation area of ​​the second layer (L2). In addition, a decrease in the size of the capacitance due to the dielectric layer can be easily prevented. Therefore, capacitance deviation and error occurrence can be suppressed depending on the difference in overlapping area.

[0147] In addition, the first via electrode (121a) may have a vertical length greater than that of the second via electrode (122a). The second via electrode (122a) may penetrate only the dielectric layer (DLL), and the first via electrode (121a) may penetrate both the dielectric layer (DLL) and the second insulating layer (112). Accordingly, the distance between the first via land (L1) and the second via land (L2) may be reduced, thereby forming a capacitance of a larger capacity.

[0148] Referring to FIG. 8, in a circuit board according to a modified example, the width of the extension portion (121ab) of the first via electrode (121a) may vary. For example, the width of the extension portion (121ab) of the first via electrode (121a) may vary at the interface between the dielectric layer (DLL) and the second insulating layer (112) or in a plane. The width (Wa1) of the extension portion (121ab) on one side may be different from the width (Wa2) of the extension portion (121ab) on the other side. As illustrated, for example, the width (Wa1) of the extension portion (121ab) on one side may be greater than the width (Wa2) of the extension portion (121ab) on the other side.

[0149] Additionally, the extension (121ab) may be positioned at the uppermost layer of the circuit board. That is, the extension (121ab) may horizontally overlap with the uppermost build-up layer or may be positioned on the uppermost build-up layer. With this configuration, the increased capacitance of the capacitor layer (CAL) may be brought closer to the upper semiconductor element. Accordingly, the electrical connection distance may be reduced, thereby improving electrical performance.

[0150] FIGS. 9A to 9X are drawings explaining a method for manufacturing a circuit board according to the first embodiment.

[0151] Referring to FIG. 9A, a carrier board (310) may be prepared. The carrier board (310) may be a copper clad laminate (CCL). Accordingly, the carrier board (310) may include a carrier insulating layer (311) and a copper foil layer (312) disposed on both sides of the carrier insulating layer (311). The carrier insulating layer (311) may be made of PPG.

[0152] Additionally, an additional insulating layer (320) may be placed on both sides or one side of the carrier board (310). The structure in which each layer is placed on both sides will be described below.

[0153] In addition, a dielectric layer (DLL'), a first base layer (LL1), and a second base layer (LL2) for a capacitor layer, which will be described later, may be arranged on both sides or one side of the carrier board (310). The dielectric layer (DLL') may correspond to the above-described dielectric layer. The first base layer (LL1) may correspond to the above-described 'first layer' or 'first via land'. The second base layer (LL2) may correspond to the above-described 'second layer' or 'second via land'.

[0154] And a separation layer (330) for separation may be arranged on the first base layer (LL1) and the second base layer (LL2). The separation layer (330) may be a copper foil. Accordingly, the bonding force between the dielectric layer and the first base layer (LL1) and the second base layer (LL2) may be greater than the bonding force between the dielectric layer and the separation layer (330).

[0155] Referring to FIG. 9b, a carrier board (310), an additional insulating layer (320), a separation layer (330), a second base layer (LL2), a dielectric layer (DLL'), and a first base layer (LL1) can be laminated and pressed. At this time, pressing can be performed with the outermost separation layer (330) removed. Accordingly, an additional insulating layer (320), a separation layer (330), a second base layer (LL2), a dielectric layer (DLL'), and a first base layer (LL1) can be sequentially laminated on both sides of the carrier board (310).

[0156] Referring to FIG. 9c, a mask (350) can be formed on the first base layer (LL1). For example, the mask (350) can be a dry film. Then, exposure and development, etc. can be performed on the mask (350).

[0157] Referring to FIG. 9D, an open area (OP) may be formed in the mask (350) on the first base layer (LL1) by exposure and development of the mask (350). In other words, patterning of the dry film may be performed. The mask (350) may be positioned in an area other than a location where the first via land is formed. Furthermore, a curing process of the mask may be performed after the formation of the open area by exposure or the like. This mask formation may be applied to other mask formations in the same manner.

[0158] Referring to FIG. 9e, plating can be performed on the open area of ​​the mask (350). That is, a plating layer (EE1) can be formed corresponding to the position of the first via land. For example, various processes such as chemical plating can be applied to the plating layer (EE1).

[0159] Referring to FIG. 9f, the mask (350) can be removed. The mask (350) can be removed by various etching methods.

[0160] Referring to FIG. 9g, etching may be performed on the plating layer and the first base layer. Etching may be performed on a portion or the entire area corresponding to the first via land. Etching on a portion of the area may be performed using an additional mask, etc. In addition, when etching on the entire area is performed, both the plating layer and the first base layer may be etched. By such etching, the plating layer and the first base layer may remain at a desired location. That is, the first via land (L1) may be formed.

[0161] Referring to FIG. 9h, a second insulating layer (112) can be formed. The second insulating layer (112) can be formed on the first via land and the dielectric layer. In addition, a plating layer (EE2) for the third electrode portion can be formed on the second insulating layer (112).

[0162] Referring to FIG. 9i, a first via (V1) in which a first via electrode is provided may be formed. In addition, a second via (V2) penetrating the second insulating layer (112) to expose the first via land (L1) may also be formed. The first via (V1) may penetrate the dielectric layer (DLL) and the second insulating layer (112). In addition, the first via (V1) may also penetrate the plating layer (EE2) on the second insulating layer (112).

[0163] At this time, the first via (V1) and the second via (V2) can be formed by various methods. For example, via formation can be performed by a laser. For example, the first via (V1) and the second via (V2) can be formed by a carbon dioxide (CO2) laser drill.

[0164] Referring to FIG. 9j, a desmear process may be performed on the formed first via (V1) and second via (V2). For example, a groove (GV) corresponding to an extension may be formed at the boundary between the second insulating layer (112) and the dielectric layer (DLL) by the desmear process due to penetration of the desmear solution.

[0165] Referring to FIG. 9k, a plating layer (EE3) may be formed on the first via (V1) and the second via (V2). The plating layer formed on the first via (V1) and the second via (V2) may be connected to the plating layer and the second base layer (LL2) located on the upper surface of the second insulating layer (112). At this time, the plating layer may be located on the outer side of the first via electrode as a seed layer. Furthermore, the seed layer may be disposed on the outer side of the above-described extension portion (the first extension portion) or may be located on the entire extension portion. That is, the above-described seed layer may be located on the outermost side of the first via electrode, and the plating layer described in FIG. 9n may be located on the inner side of the first via electrode or the inner side of the seed layer. At this time, the seed layer and the plating layer may be made of different metal materials, such as the above-described first metal and second metal. In this way, by using a more elastic metal as the seed layer, the reliability of the brittle properties of the dielectric layer can be improved more effectively.

[0166] Referring to FIGS. 9l and 9m, a mask (350') may be formed on the second insulating layer (112) and the aforementioned plating layer. For example, the mask (350') may be a dry film. Then, exposure and development, etc. may be performed on the mask (350') to form an open area. In other words, patterning may be performed on the dry film. The mask (350') may be placed in an area other than a position where the first electrode portion is formed. Furthermore, a curing process of the mask may be performed after the open area is formed by exposure, etc.

[0167] Referring to FIG. 9n, plating may be performed on the open area (OP1) of the mask (350'). That is, a plating layer (EE4) may be formed corresponding to the position of the first electrode portion. For example, various processes such as chemical plating may be applied to the plating layer.

[0168] Referring to FIG. 9o, the mask (350') can be removed.

[0169] And referring to FIG. 9p, etching can be performed on the plating layer. Accordingly, the connected plating layers (EE3, EE4) formed on the second insulating layer (112) can be electrically separated corresponding to the position of the first electrode portion (121).

[0170] Referring to FIG. 9q, a first insulating layer (111) can be formed on the first electrode portion. In addition, a plating layer (EE5) can be formed on the first insulating layer (111).

[0171] Referring to FIG. 9r, the second base layer (LL2) and the layer above the second base layer (LL2) can be separated from the aforementioned carrier board (310) and additional insulating layer (320).

[0172] Referring to FIG. 9s, a third via (V3) corresponding to the third via electrode can be formed in the first insulating layer (111). The third via (V3) can be formed by etching or etching.

[0173] And, corresponding to the second via electrode, a fourth via (V4) can be formed. The fourth via (V4) can penetrate the dielectric layer (DLL) and the second base layer (LL2).

[0174] Referring to FIG. 9t, a plating layer can be formed on the second base layer (LL2) and the fourth via. Here, the plating layer formed on the second base layer (LL2) and the fourth via can correspond to the first seed layer (SE1) and the second seed layer (SE2).

[0175] Referring to FIGS. 9u and 9v, a mask (350'') can be formed on the plating layer formed on the second base layer (LL2) and the fourth via. In addition, a mask (350'') can also be formed under the third via and the first insulating layer (111).

[0176] For example, the mask (350'') may be a dry film. Then, exposure and development, etc. may be performed on the mask (350'') to form an open area. In other words, patterning may be performed on the dry film. The mask (350'') may be positioned in an area other than where the second electrode portion and the third electrode portion are formed. Furthermore, a curing process of the mask may be performed after the open area is formed by exposure and development, etc.

[0177] Referring to FIG. 9w, plating may be performed on the open area of ​​the mask (350''). Etching (e.g., flash etching) may be performed. That is, the plating layer may be removed by etching. By this configuration, a second electrode portion and a third electrode portion may be formed. Due to etching, electrical separation of the second electrode portion (122) and the third electrode portion (123) may be achieved.

[0178] Referring to FIG. 9x, a protective layer (SR) can be formed on the second electrode portion and the third electrode portion. Furthermore, an opening area can be formed in the protective layer (SR) for electrical connection with a chip or substrate, etc.

[0179] FIG. 10 is a cross-sectional view of a circuit board according to a second embodiment, FIG. 11 is a perspective view of a first via electrode and a second via electrode in a circuit board according to the second embodiment, FIG. 12 is an enlarged view of K4 in FIG. 10, FIG. 13 is an enlarged view of K5 in FIG. 10, FIG. 14 is an enlarged view of K6 in FIG. 10, and FIG. 15 is a photograph of FIG. 11.

[0180] Referring to FIG. 10, a circuit board (100A) according to the second embodiment may include an insulating layer (110), an electrode portion (120), and a capacitor layer (CAL). Furthermore, the circuit board (100A) may also include a protective layer disposed on the electrode portion (120). Furthermore, the configuration described in the embodiments of the present invention may be applied in the same manner, except for the contents described below.

[0181] In this embodiment, the insulating layer (110) in the circuit board (100A) may include a third insulating layer (113) disposed on the second insulating layer (112). The third insulating layer (113) may be disposed on the capacitor layer (CAL). In addition, a third electrode portion may be further disposed on the third insulating layer (113).

[0182] Additionally, the fourth electrode portion (125) may be located on the third insulating layer (113). The fourth electrode portion (125) may include a fourth via electrode (125a) and a fourth wiring portion (125b). The fourth wiring portion (125b) may be disposed on an upper surface of the third insulating layer (113). And the fourth via electrode (125a) may penetrate at least a portion of the third insulating layer (113). The fourth via electrode (125a) may electrically connect the fourth wiring portion (125b) and the second layer (L2).

[0183] Furthermore, the second via electrode (122b) may be placed between the fourth wiring portion (125b) and the first layer (L1). And the second via electrode (122b) may connect the fourth wiring portion (125b) and the first layer (L1) to each other.

[0184] Fig. 11(a) is a perspective view of the first via electrode, and Fig. 11(b) is a perspective view of the second via electrode.

[0185] Referring further to FIGS. 11 to 13, and in the present embodiment, the second via electrode (122b) may be disposed on the third insulating layer (113). And the second via electrode (122b) may penetrate the third insulating layer (113) and the dielectric layer (DLL). The second via electrode (122b) may include an extension portion (or a second extension portion) extending along the horizontal direction (Y-axis direction) at the interface between the dielectric layer (DLL) and the third insulating layer (113). This will be described later.

[0186] The first via electrode (121a) described above may include a body portion (121aa) and an extension portion (121ab). Here, the body portion (121aa) of the first via electrode (121a) may be the first body portion. And the extension portion (121ab) of the first via electrode (121a) may be the first extension portion.

[0187] The second via electrode (122b) according to the embodiment can penetrate the dielectric layer (DLL) and the third insulating layer (113) as described above. The second via electrode (122b) can include a second body portion (122ba) and a second extension portion (122bb).

[0188] The second body portion (122ba) may have a cylindrical or truncated cone shape. The second extension portion (122bb) may extend in the horizontal direction (Y-axis direction) at the interface between the dielectric layer (DLL) and the second insulating layer (112). The second extension portion (122bb) may be located on the outer surface of the second body portion (122ba).

[0189] Furthermore, the second extension portion (122bb) may be positioned adjacent to the dielectric layer (DLL). For example, the second extension portion (122bb) may be positioned between the second bisector (HL2) and the dielectric layer (DLL). That is, the second extension portion (122bb) may be positioned closer to the dielectric layer (DLL) among the dielectric layer (DLL) and the first insulating layer (111). The second bisector (HL2) may correspond to a line that vertically bisects the first via electrode (121a).

[0190] The second extension portion (122bb) may overlap the dielectric layer (DLL) and the second insulating layer (112) in the horizontal direction (Y-axis direction). The second extension portion (122bb) may overlap a portion of the dielectric layer (DLL) in the horizontal direction (Y-axis direction). In addition, the second extension portion (122bb) may overlap at least a portion of the second insulating layer (112) in the horizontal direction (Y-axis direction).

[0191] For example, the second extension portion (122bb) may include a third extension region (EP3) that is in horizontal contact with the dielectric layer (DLL) and a fourth extension region (EP4) that is in horizontal contact with the second insulating layer (112). The fourth extension region (EP4) may be a region other than the third extension region (EP3) in the second extension portion (122bb).

[0192] The length (d3) in the vertical direction (X-axis direction) of the third extension region (EP3) may be smaller than the length (d4) in the vertical direction (X-axis direction) of the fourth extension region (EP4). That is, the second extension portions (122bb) may be formed in greater numbers in the second insulating layer (112) than in the brittle dielectric layer (DLL) at the interface between the dielectric layer (DLL) and the second insulating layer (112).

[0193] Additionally, the volume of the third extension area (EP3) may be smaller than the volume of the fourth extension area (EP4). However, the horizontal length of the third extension area (EP3) may be larger than the horizontal length of the fourth extension area (EP4). That is, the second extension portion (122bb) may have a maximum length in the horizontal direction (Y-axis direction) in the third extension area (EP3).

[0194] The bonding area between the second insulating layer (112) and the first via electrode (121a) can be increased by this second extension portion (122bb). Accordingly, structural reliability can be improved.

[0195] The first via electrode (121a) and the second via electrode (122b) may have their respective body portions extend in different directions. Furthermore, the first via electrode (121a) and the second via electrode (122b) may overlap with the dielectric layer (DLL) in the horizontal direction. In addition, the first via electrode (121a) and the second via electrode (122b) may overlap with each other in the horizontal direction.

[0196] Furthermore, both the first extension and the second extension may be positioned adjacent to the dielectric layer (DLL) in each insulating layer.

[0197] And the first extension and the second extension may extend in different directions. For example, the first extension may extend outward from an outer surface of the first via electrode, the width of which increases toward the bottom. The second extension may extend outward from an outer surface of the second via electrode, the width of which decreases toward the bottom. Furthermore, the first extension and the second extension may be located in an area adjacent to the dielectric layer (DLL). For example, the first extension may be located above the first via electrode, and the second extension may be located below the second via electrode. Furthermore, the first extension may have a structure in which the width decreases from the top to the bottom, while the second extension may have a structure in which the width increases from the top to the bottom. By this configuration, the structural reliability may be improved.

[0198] In addition, the width (Wc) of the second via electrode (122b) may be maximum at the extension portion (122bb) or the upper surface. For example, the second via electrode (122b) may have the maximum width (Wc') of the second via electrode (122b) at the extension portion (122bb). In particular, the second via electrode (122b) may have the maximum width (Wc') between the second bisector (HL2) and the dielectric layer (DLL) corresponding to the boundary between the dielectric layer (DLL) and the second insulating layer (112). The width of the second via electrode (122b) may increase from the lower surface of the second insulating layer (112) toward the upper surface, and then increase along a greater slope at the extension portion. In addition, the second via electrode (122b) may have the maximum width at the extension portion and then decrease toward the upper surface of the second insulating layer (112).

[0199] Additionally, the first via electrode (121a) and the second via electrode (122b) may have a longer vertical length than a via electrode penetrating one insulating layer that is vertically overlapped with the wiring or pad.

[0200] Referring further to Fig. 14, the number of the lower insulating layers (111, 112) and the upper insulating layers (113) based on the dielectric layer (DLL) may be different. In addition, the number of the lower insulating layers (111, 112) of the dielectric layer (DLL) may be 2n (n is a natural number). In addition, the number of the upper insulating layers (113) of the dielectric layer (DLL) may be 2m-1 (m is a natural number). That is, the upper and lower insulating layers may be formed in different numbers based on the dielectric layer (DLL), and if one of the upper and lower insulating layers is formed in an even number of insulating layers, the other may be formed in an odd number of insulating layers. In this way, according to the above-described manufacturing method, the upper and lower insulating layers of the dielectric layer (DLL) can be easily set to a desired number.

[0201] Referring to FIG. 15, in the first via electrode, the first extension portion (121ab) is disposed on the side surface of the first body portion (121aa) and may extend in a horizontal direction at the interface between the dielectric layer and the second insulating layer. In addition, in the second via electrode, the second extension portion (122bb) is disposed on the side surface of the second body portion (122ba) and may extend in a horizontal direction at the interface between the dielectric layer and the third insulating layer.

[0202] Fig. 16 is a cross-sectional view of a circuit board according to the third embodiment, and Fig. 17 is an enlarged view of K7 of Fig. 16.

[0203] Referring to FIGS. 16 and 17, a circuit board (100B) according to the third embodiment may include an insulating layer (110), an electrode portion (120), and a capacitor layer (CAL). Furthermore, the circuit board (100A) may include a protective layer disposed on the electrode portion (120). Furthermore, the configuration described in the embodiments of the present invention may be applied in the same manner, except for the contents described below.

[0204] In this embodiment, the insulating layer (110) in the circuit board (100A) may include a fourth insulating layer (114) disposed on a third insulating layer (113). The third insulating layer (113) may be disposed on a capacitor layer (CAL). In addition, a fifth electrode portion (126) may be further disposed on the fourth insulating layer (114). A protective layer (second protective layer) may be positioned on the fifth electrode portion (126).

[0205] In addition, the fifth electrode portion (126) may be located in the fourth insulating layer (114). The fifth electrode portion (126) may include a fifth via electrode (126a) and a fifth wiring portion (126b). The fifth wiring portion (126b) may be disposed on an upper surface of the fourth insulating layer (114). And, the fifth via electrode (126a) may penetrate at least a portion of the fourth insulating layer (114). The fifth via electrode (126a) may electrically connect the fifth wiring portion (126b) and the fourth wiring portion (125b). However, as described above, each via electrode may also penetrate at least one insulating layer to perform electrical connection between adjacent or spaced insulating layers.

[0206] And, with respect to the dielectric layer (DLL), the number of the lower insulating layers (111, 112) and the upper insulating layers (113, 114) may be different or the same. In addition, the number of the lower insulating layers (111, 112) of the dielectric layer (DLL) may be 2n (n is a natural number). In addition, the number of the upper insulating layers (113) of the dielectric layer (DLL) may be 2m (m is a natural number). That is, with respect to the dielectric layer (DLL), the upper and lower insulating layers may be formed in the same or different numbers, and when one of the upper and lower insulating layers is formed in an even (odd) number of insulating layers, the other may be formed in an even (odd) number of insulating layers. Accordingly, the upper and lower insulating layers of the dielectric layer (DLL) can be easily set to a desired number based on the dielectric layer (DLL).

[0207] In addition, the semiconductor package may include a connecting member. The connecting member may be referred to as a bridge substrate. For example, the connecting member may include a redistribution layer. The connecting member may function to horizontally electrically connect a plurality of semiconductor devices to each other. For example, since the area that a semiconductor device must have is generally very large, the connecting member may include a redistribution layer. Since the semiconductor package and the semiconductor device have a large difference in the width or width of the circuit pattern, etc., a buffering function of the circuit pattern for electrical connection is required. The buffering function may mean having a size between the width or width of the circuit pattern of the semiconductor package and the width or width of the circuit pattern of the semiconductor device, and the redistribution layer may have a function of performing a buffering function.

[0208] In an embodiment, the connecting member may be an organic bridge. For example, the connecting member may comprise an organic material. For example, the connecting member may comprise an organic substrate instead of a silicon substrate. The connecting member may be embedded within the circuit board.

[0209] To this end, the circuit board may include a cavity, and a connecting member may be positioned within the cavity of the circuit board. The connecting member may horizontally connect a plurality of semiconductor elements positioned on the circuit board.

[0210] Furthermore, the circuit board according to the embodiment can be divided into a package substrate and an interposer corresponding to the lower substrate according to the function of the circuit board, and applied thereto. The package substrate functions to mount semiconductor devices and / or interposers. As data increases, the area of ​​the circuit board increases or the number of laminated insulating layers increases, which can significantly reduce the yield of the circuit board. Therefore, in order to improve the yield of a circuit board with a high number of laminated layers, the yield of the circuit board can be improved by separating it into an interposer and a package substrate. In addition, as the density of terminals of semiconductor devices increases, it may be difficult to implement pads of the package substrate having an area corresponding to the terminals of the semiconductor devices. Therefore, the pad size of the package substrate and the fine pattern size of the terminals of the semiconductor devices can act as a buffer.

[0211] The package substrate and interposer described above can be classified into core substrates and coreless substrates, depending on the composition of the insulating layer. In the case of a core substrate, the insulating layer may include a core layer, and the core layer may refer to a layer among the laminated insulating layers that includes a reinforcing member. The reinforcing member may refer to glass fiber. The core layer may have the function of preventing warpage of the circuit board during the process by being arranged thicker than other insulating layers. However, the core layer may cause problems such as voltage drop and signal loss, or may be difficult to thin. Therefore, depending on the application, the insulating layer of the circuit board may use a coreless substrate that does not include a core layer.

[0212] In various semiconductor packages, circuit boards according to the various embodiments described above may be located in some areas or correspond to one substrate.

[0213] Meanwhile, when a circuit board having the characteristics of the invention described above is used in IT devices such as smartphones, server computers, TVs, or home appliances, it can stably perform functions such as signal transmission or power supply. For example, when a circuit board having the characteristics of the invention performs a semiconductor package function, it can safely protect semiconductor chips from external moisture or contaminants, and can solve problems such as leakage current or electrical shorts between terminals, or electrical open circuits in terminals supplying semiconductor chips. Furthermore, when it performs a signal transmission function, it can solve noise problems. Through this, the circuit board having the characteristics of the invention described above can maintain the stable function of IT devices or home appliances, thereby enabling the entire product and the circuit board to which the invention is applied to achieve functional integration or technical interoperability with each other.

[0214] When a circuit board having the characteristics of the invention described above is used in a transportation device such as a vehicle, it can solve the problem of signal distortion transmitted to the transportation device, safely protect the semiconductor chip controlling the transportation device from external sources, and solve the problem of leakage current or electrical short circuit between terminals, or electrical open of the terminal supplying the semiconductor chip, thereby further improving the stability of the transportation device. Accordingly, the transportation device and the circuit board to which the present invention is applied can achieve functional integration or technical interoperability with each other.

[0215] The features, structures, effects, etc. described in the embodiments above are included in at least one embodiment, and are not necessarily limited to just one embodiment. Furthermore, the features, structures, effects, etc. exemplified in each embodiment can be combined or modified in other embodiments by those skilled in the art to which the embodiments pertain. Therefore, the contents related to such combinations and modifications should be construed as being included within the scope of the embodiments.

[0216] Although the above description focuses on examples, these are merely examples and are not intended to limit the examples. Those skilled in the art will appreciate that various modifications and applications not exemplified above are possible without departing from the essential characteristics of the present examples. For example, each component specifically shown in the examples can be modified and implemented. In addition, differences related to such modifications and applications should be interpreted as being included within the scope of the embodiments set forth in the appended claims.

Claims

1. First insulation layer; A second insulating layer disposed on the first insulating layer; and A dielectric layer disposed on the second insulating layer; A first via electrode penetrating the dielectric layer and the second insulating layer; A circuit board including a first extension portion extending in a horizontal direction at the interface between the dielectric layer and the second insulating layer, wherein the first via electrode is a first via electrode.

2. In paragraph 1, Further comprising a protective layer disposed on the second insulating layer; The above protective layer is a circuit board that penetrates the second via land and comes into contact with the dielectric layer.

3. In paragraph 1, A circuit board comprising a capacitor layer including a first via land disposed between the first insulating layer and the second insulating layer, the dielectric layer, and a second via land disposed on the dielectric layer.

4. In paragraph 3, A circuit board further comprising a second via electrode disposed between the first via land and the second via land.

5. In paragraph 4, The width of the second via electrode gradually decreases from the upper surface of the second insulating layer toward the lower surface of the second insulating layer, A circuit board in which the width of the first via electrode gradually increases from the upper surface of the second insulating layer toward the lower surface of the second insulating layer.

6. In paragraph 4, A circuit board in which the second via electrode and the first via electrode overlap horizontally with the dielectric layer.

7. In paragraph 4, A circuit board in which the second via electrode and the first via electrode penetrate the dielectric layer.

8. In paragraph 4, A circuit board in which the first via electrode has a vertical length greater than that of the second via electrode.

9. In paragraph 4, A circuit board comprising a first seed layer and a second seed layer arranged and spaced apart from each other under the second via land.

10. In paragraph 9, The circuit board wherein the first seed layer penetrates the dielectric layer.

11. In paragraph 9, The above first seed layer is a circuit board in contact with the above first via land.

12. In paragraph 9, A circuit board in which the second seed layer is disposed on top of the first via electrode.

13. In paragraph 9, A circuit board in which the second seed layer is disposed on the dielectric layer and does not overlap with the dielectric layer in a horizontal direction.

14. In paragraph 9, A circuit board wherein the first seed layer has a vertical length greater than that of the second seed layer.

15. In paragraph 3, A circuit board in which the first insulating layer and the second insulating layer have a vertical length greater than that of the dielectric layer.

16. In paragraph 9, A circuit board having a length in the vertical direction of the dielectric layer that is shorter than a length in the vertical direction of the first via land or the second via land.

17. In paragraph 9, Further comprising a protective layer disposed on the second insulating layer; A circuit board in which the protective layer horizontally overlaps the second via land, at least a portion of the first seed layer, and the second seed layer.

18. In paragraph 1, A third insulating layer disposed on the second insulating layer; A circuit board including a second via electrode penetrating the third insulating layer and the dielectric layer.

19. In paragraph 18, A circuit board including a second extension portion extending in a horizontal direction at the interface between the dielectric layer and the third insulating layer, wherein the second via electrode is a circuit board.

20. In paragraph 19, A circuit board in which the first extension portion and the second extension portion are positioned adjacent to the dielectric layer.

Images