Diagnosis coverage and performance enhancement

Abstract

A fault partition node system is created for a circuit design based on fault simulation for each of a plurality of test patterns. Based on the fault partition node system, a diagnosis coverage contribution value for each of the plurality of test patterns is determined. Test patterns in the plurality of test patterns are then reordered based on the diagnosis coverage contribution value. The above operations of creating, determining, and reordering can be repeated. The fault partition node system can also be used for selective chain diagnosis for performance improvement.

Description

[0001] DIAGNOSIS COVERAGE AND PERFORMANCE ENHANCEMENT

[0002] FIELD OF THE DISCLOSED TECHNOLOGY

[0003]

[0001] The present disclosed technology relates to the field of circuit test and diagnosis. Various implementations of the disclosed technology may be particularly useful for diagnosis coverage and performance enhancement.

[0004] BACKGROUND OF THE DISCLOSED TECHNOLOGY

[0005]

[0002] Modem integrate circuits are complex. At leading technology nodes, feature sizes have shrunk to a few nm wide. Non-planar or “three-dimensional” transistors (FinFET and GAA (gate-all-around)) are being used to achieve higher performance with lower power consumption. The non-planar transistors and transistor connections have more complicated structures with more layers and thus require more process steps. More process steps and smaller feature sizes can result in more root causes of defects. For these integrate circuits to be commercially viable, the manufacture yield needs to reach and maintain above a certain threshold. Therefore, accurately identifying yield-limiting root causes becomes highly critical. In the past, bitmapping static random-access memories (SRAMs) has been employed as a “yield learning vehicle”. For leading technology nodes, however, being capable of manufacturing these regular structures does not guarantee that a product with irregular structures can be successfully manufactured.

[0006]

[0003] Software-based diagnosis of scan test failures has proven to be of enormous value for yield learning. Scan testing is commonly used in a manufacture process to ensure that integrated circuits are fabricated correctly. Diagnosis uses failure data from scan testing along and circuit design information to determine the most likely defect locations and mechanisms for failing circuits (dies). The diagnosis results can guide physical failure analysis (PF A) to focus on a much smaller area in a failing circuit, leading to higher success rates of PFA with reduced turnaround time and costs. Based on the yield loss mechanism obtained by PF A, circuit design or manufacture process can be adjusted to improve manufacture yields.

[0007]

[0004] The PFA process is destructive to integrated circuits. It is thus important for diagnosis to provide a target area for PFA as precise as possible. Fault simulation has been employed to help solve test quality problems. In a similar way, fault simulation may be used to improve diagnosis quality. Diagnosis quality can be affected by insufficient data collected by a tester, low-quality test pattern sets, or circuit design issues. If the problems are identified earlier, remedies to improve diagnosis resolution could be applied before silicon tape-out or manufacture testing.

[0008] BRIEF SUMMARY OF THE DISCLOSED TECHNOLOGY

[0009]

[0005] Various aspects of the present disclosed technology relate to techniques for test pattern reordering for improving diagnosis coverage and selective chain diagnosis for improving diagnosis performance. In one aspect, there is a method comprising: receiving a circuit design, a plurality of faults, and a plurality of test patterns; creating a fault partition node system for the circuit design based on fault simulation for each of the plurality of test patterns; determining a diagnosis coverage contribution value for each of the plurality of test patterns based on the fault partition node system; reordering test patterns in the plurality of test patterns based on the diagnosis coverage contribution value; and storing the reordered plurality of test patterns. The operations of generating, deriving and reordering may be repeated by using the plurality of reordered test patterns. The repetition may continue until diagnosis coverage cannot be improved. The diagnosis coverage contribution value may be a number of diagnosis care bits or a number of fault partition nodes.

[0010]

[0006] The fault simulation may be performed for each of the plurality of test patterns in a sequence to determine test response bits from each of one or more test response output channels of the circuit design, the sequence being the same as a sequence in which the plurality of test patterns would be used to test a circuit fabricated according to the circuit design, the test response bits comprising passing bits and failing bits, and the creating a fault partition node system and the expanding the fault partition node system may be based on the test response bits determined by the fault simulation, the fault partition node system comprising fault partition nodes and equivalent fault groups, each of the fault partition nodes being associated with one of the equivalent fault groups, each of the equivalent fault groups comprising one or more faults in the plurality of faults, the generating comprising: creating (TV - 1) new fault partition nodes for an existing fault partition node if an existing equivalent fault group associated with the existing fault partition node is separated into N new equivalent fault groups based on one or more test response bits at an observation clock cycle, associating the N new equivalent fault groups with the (TV - 1) new fault partition nodes and the existing fault partition node, respectively, and removing the association of the existing equivalent fault group with the existing fault partition node.

[0011]

[0007] The fault partition node system may be created for each of the one or more test response output channels, a number of fault partition node systems generated being equal to a number of the one or more test response output channels, wherein TV = 2 and the creating comprising: creating a new fault partition node for an existing fault partition node if an existing equivalent fault group associated with the existing fault partition node is separated into two new equivalent fault groups based on a failing bit at an observation clock cycle; associating the two new equivalent fault groups with the new fault partition node and the existing fault partition node, respectively; and removing the association of existing equivalent fault group with the existing fault partition node. One of the two new equivalent fault groups having the failing bit may be associated with the new fault partition node.

[0012]

[0008] In another aspect, there is a method comprising: receiving a circuit design, a plurality of faults, and a plurality of test patterns; generating a fault partition node system for the circuit design based on fault simulation for each of the plurality of test patterns; determining equivalent fault group information for each of scan chains in the circuit design based on the fault partition node system; and performing a chain diagnosis process only on scan chains that can meet a diagnosis resolution threshold based on the equivalent fault group information..

[0013]

[0009] Certain inventive aspects are set out in the accompanying independent and dependent claims. Features from the dependent claims may be combined with features of the independent claims and with features of other dependent claims as appropriate and not merely as explicitly set out in the claims.

[0014]

[0010] Certain objects and advantages of various inventive aspects have been described herein above. Of course, it is to be understood that not necessarily all such objects or advantages may be achieved in accordance with any particular embodiment of the disclosed technology. Thus, for example, those skilled in the art will recognize that the disclosed technology may be embodied or carried out in a manner that achieves or optimizes one advantage or group of advantages as taught herein without necessarily achieving other objects or advantages as may be taught or suggested herein.

[0015] BRIEF DESCRIPTION OF THE DRAWINGS

[0016]

[0011] Figure 1 illustrates an example of a computing device that may be used to implement various embodiments of the disclosed technology.

[0017]

[0012] Figure 2 illustrates an example of a test pattern reordering tool that may be implemented according to various embodiments of the disclosed technology.

[0018]

[0013] Figure 3 illustrates a flowchart showing a process of test pattern reordering for improving diagnosis coverage that may be implemented according to various examples of the disclosed technology.

[0019]

[0014] Figure 4A illustrates an example of test response output channels that are coupled to outputs of scan chains.

[0020]

[0015] Figure 4B illustrates an example of test response output channels in a test compression environment.

[0016] Figure 5 illustrates a flowchart showing a process of fault partition node system generation that may be implemented according to various examples of the disclosed technology.

[0021]

[0017] Figure 6 illustrates a flowchart showing an example process for creating new fault partition nodes for an observation-clock-cycle-based fault partition node system for a circuit design that may be implemented according to various examples of the disclosed technology.

[0022]

[0018] Figure 7 uses a diagram as an example to illustrate a process for creating new fault partition nodes for an observation-clock-cycle-based fault partition node system for a circuit design that may be implemented according to various examples of the disclosed technology.

[0023]

[0019] Figure 8 uses a diagram as an example to illustrate a process for creating new fault partition nodes for an observation-clock-cycle-based fault partition node system for one test response output channel that may be implemented according to various examples of the disclosed technology.

[0024]

[0020] Figure 9 illustrates a flowchart showing a process of selective chain diagnosis for performance improvement that may be implemented according to various examples of the disclosed technology.

[0025] DETAILED DESCRIPTION OF THE DISCLOSED TECHNOLOGY

[0026] General Considerations

[0027]

[0021] Various aspects of the present disclosed technology relate to techniques for test pattern reordering for improving diagnosis coverage and selective chain diagnosis for improving diagnosis performance. In the following description, numerous details are set forth for the purpose of explanation. However, one of ordinary skill in the art will realize that the disclosed technology may be practiced without the use of these specific details. In other instances, well-known features have not been described in detail to avoid obscuring the present disclosed technology.

[0028]

[0022] Some of the techniques described herein can be implemented in software instructions stored on a computer-readable medium, software instructions executed on a computer, or some combination of both. Some of the disclosed techniques, for example, can be implemented as part of an electronic design automation (EDA) tool. Such methods can be executed on a single computer or on networked computers.

[0029]

[0023] Although the operations of the disclosed methods are described in a particular sequential order for convenient presentation, it should be understood that this manner of description encompasses rearrangements, unless a particular ordering is required by specific language set forth below. For example, operations described sequentially may in some cases be rearranged or performed concurrently. The detailed description sometimes uses terms like “create,” “determine,” and “reorder” to describe the disclosed methods / systems. Such terms are high-level descriptions of the actual operations that are performed. The actual operations that correspond to these terms will vary depending on the particular implementation and are readily discernible by one of ordinary skill in the art.

[0030]

[0024] As used in this disclosure, the singular forms “a,” “an,” and “the” include the plural forms unless the context clearly dictates otherwise. Additionally, the term “includes” means “comprises.” Moreover, unless the context dictates otherwise, the term “coupled” means electrically or electromagnetically connected or linked and includes both direct connections or direct links and indirect connections or indirect links through one or more intermediate elements not affecting the intended operation of the circuit.

[0031]

[0025] Also, as used herein, the term “design” is intended to encompass data describing an entire integrated circuit device. This term also is intended to encompass a smaller group of data describing one or more components of an entire device, however, such as a portion of an integrated circuit device. Still further, the term “design” also is intended to encompass data describing more than one microdevice, such as data to be used to form multiple microdevices on a single wafer.

[0032] Design For Test, Test Pattern Generation, And Testing

[0033]

[0026] The reduction in feature size increases the probability that a manufacture defect in an integrated circuit will result in a faulty chip. A very small defect can result in a faulty transistor or interconnecting wire. Even a single faulty transistor or wire can cause the entire chip to function improperly. Manufacture defects are unavoidable nonetheless, no matter whether the manufacturing process is at the prototype stage or the high-volume manufacturing stage. It is thus necessary to test chips during the manufacturing process. Diagnosing faulty chips is also needed to ramp up and to maintain the manufacturing yield.

[0034]

[0027] Testing typically includes applying a set of test stimuli (test patterns) to the circuit-under- test and then analyzing responses generated by the circuit-under-test. Functional testing attempts to validate that the circuit-under-test operates according to its functional specification while structural testing tries to ascertain that the circuit-under-test has been assembled correctly from some low-level building blocks as specified in a structural netlist and that these low-level building blocks and their wiring connections have been manufactured without defect. For structural testing, it is assumed that if functional verification has shown the correctness of the netlist and structural testing has confirmed the correct assembly of the structural circuit elements, then the circuit should function correctly. Structural testing has been widely adopted at least in part because it enables the test (test pattern) generation to focus on testing a limited number of relatively simple circuit elements rather than having to deal with an exponentially exploding multiplicity of functional states and state transitions.

[0035]

[0028] To make it easier to develop and apply test patterns, certain testability features are added to circuit designs, which is referred to as design for test or design for testability (DFT). Scan testing is the most common DFT method. In a basic scan testing scheme, all or most of internal sequential state elements (latches, flip-flops, et al.) in a circuit design are made controllable and observable via a serial interface. These functional state elements are usually replaced with dual-purpose state elements called scan cells. Scan cells are connected together to form scan chains - serial shift registers for shifting in test patterns and shifting out test responses. A scan cell can operate as originally intended for functional purposes (functional / mission mode) and as a unit in a scan chain for scan testing (scan mode). A widely used type of scan cell includes an edge-trigged flip-flop with two-way multiplexer for the data input. The two-way multiplexer is typically controlled by a single control signal called scan enable, which selects the input signal for a scan cell from either a scan signal input port or a system signal input port. The scan signal input port is typically connected to an output of another scan cell while the system signal input port is connected to the functional logic. Scan cells can serve as both a control point and an observation point. Control points can be used to set certain logic values at some locations of the circuit-under-test, exciting (activating) a fault and propagating the incorrect value to an observation point. Scan testing allows the test equipment to access gates deeply embedded through the primary inputs / outputs and / or some physical test points and can remove the need for complicated state transition sequences when trying to control or observe what is happening at some internal circuit element.

[0036]

[0029] In a typical scan test, a series of known values (test stimuli or test pattern) are shifted-in (or loaded into) scan cells through their sequential inputs. The shifting-in occurs by placing the integrated circuit in a special mode, known as shift mode, and then applying a series of clock pulses, called “shift pulses” or “shift clock pulses.” Each shift clock pulse pushes a bit of test stimuli into a scan cell in each of the scan chains. This continues until all scan cells in the scan chains are filled with test pattern bits. Then, one or more clock pulses, called “capture pulses” or “capture clock pulses,” are applied to the circuit as they would be in normal operation. This is referred to as capture mode. After the test pattern bits are injected into the circuit, the results of the test (test responses) are “captured” and stored in the scan cells. The circuit then returns to shift mode, and with each additional clock pulse, a bit of the test responses is pushed or shifted out as each bit of new test pattern is pushed or shifted in. The shifted-out test responses are then compared with expected results to determine and locate any errors. Shift mode and capture mode together may be called as test mode.

[0037]

[0030] Test patterns for scan testing are typically generated through an automatic test pattern generation (ATPG) process. ATPG usually focuses on a set of faults derived from a gatelevel fault model. A defect is a flaw or physical imperfection caused in a device during the manufacturing process. A fault model (or briefly a fault) is a description of how a defect alters design behavior. For a given target fault, ATPG comprises two phases: fault activation and fault propagation. Fault activation establishes a signal value at the fault site opposite that produced by the fault (e.g., for a stuck-at-0 fault, the fault activation process will try to establish a logic T at that site). Fault propagation propagates the fault effect (e.g., stuck at 0) forward by sensitizing a path from a fault site to a scan cell or a primary output. A fault at a site is said to be detected by a test pattern if a test response value captured by a scan cell or a primary output is different than the expected value. The objective of ATPG is to find a test pattern that, when applied to the circuit, enables testers to distinguish between the correct circuit behavior and the faulty circuit behavior caused by one or more particular faults. Effectiveness of ATPG is measured by the fault coverage achieved for the fault model and the number of generated vectors (test pattern counts), which should be directly proportional to test application time. Here, the fault coverage is defined as a ratio of the number of detected faults vs. the total number of faults.

[0038]

[0031] A popular fault model used in practice is the single stuck-at fault model. In this model, one of the signal lines in a circuit is assumed to be stuck at a fixed logic value, regardless of what inputs are supplied to the circuit. The stuck-at fault model is a logical fault model because no delay information is associated with the fault definition. Delay faults cause errors in the functioning of a circuit based on its timing. They are caused by the finite rise and fall time periods of the signals in the gates, as well as the propagation delay of interconnects between the gates. Transition faults are used for their simplicity in modeling spot defects that affect delays at inputs or outputs of gates. Under scan-based tests, the transition faults are associated with an extra delay that is large enough to cause the delay of any path through the fault site to exceed the clock period. Cell internal fault models can be derived using transistor-level circuit simulations (analog simulations). This approach can pinpoint the defect location within a cell for various cell internal defects.

[0039]

[0032] During the circuit design and manufacturing process, a manufacturing test screens out chips (dies) containing defects. The test itself, however, does not identify the reason for the unacceptable low or fluctuating yield that may be observed. Physical failure analysis (PF A) can inspect the faulty chip to locate the defect location(s) and to discover the root cause. The process usually includes etching away certain layers and then imaging the silicon surface by scanning electronic microscopy or focused ion beam systems. This PFA process is laborious and time consuming. To facilitate the PFA process, diagnosis (also referred to as scan diagnosis) is often employed to narrow down possible locations of the defect(s) based on analyzing the fail log (fail file, failure file). The fail log typically contains information about when (e.g., tester cycle), where (e.g., at what tester channel), and how (e.g., at what logic value) the test failed and which test patterns generate expected test responses. The layout information of the circuit design may also be employed to further reduce the number of defect suspects.

[0040]

[0033] Diagnosis includes logic diagnosis (sometimes referred to as scan diagnosis) and chain diagnosis. Logic diagnosis may employ a fault dictionary or directly examine the syndrome (i.e., the effect) of the failing chip to determine likely defect locations (defect suspects). The latter approach may include structural pruning (back tracing), fault injection and evaluation (fault simulation for both failing and passing test patterns).

[0041]

[0034] Chain diagnosis determines scan cells that are likely to be defective. Scan elements and related clocking circuitry can take up about 30% of silicon area of an IC chip. It has been reported that scan chain failures account for almost 50% of chip failure in some cases. Chain diagnosis is thus important to guide physical failure analysis and yield learning process. In a chain diagnosis process, two types of test patterns may be used. The first type is called chain patterns. A chain pattern is a pattern used in a process comprising shift-in and shift-out without pulsing capture clocks. The other type is often referred to as scan patterns. A scan pattern is a pattern used in a process comprising shift-in, one or multiple capture clock cycles, and shift-out, and the scan patterns include patterns generated by ATPG for testing system logic, special chain diagnostic patterns generated only for scan chain diagnosis purpose and some special functional patterns. Chain patterns can be used to test the integrity of scan chains and / or determine fault models associated with faulty scan chains while scan patterns can be used to inject certain values to some scan cells for locating defective scan cells.

[0042]

[0035] The quality of diagnosis can be measured by diagnostic resolution (the number of the real defects vs. the number of the defect suspects). Diagnostic resolution is linked not only to the algorithm used for diagnosis but also to the test patterns used for the manufacturing test (manufacturing test patterns). The quality of diagnosis can also be measured by diagnosis coverage. Diagnosis coverage may be determined in several ways. A simple way is to divide the number of equivalent fault groups by the number of faults. Faults in an equivalent fault group cannot be separated or distinguished under a certain condition by a diagnosis technique. To enhance the quality of diagnosis, a diagnostic test pattern generation process may be employed. This process generates test patterns that can increase the number of equivalent fault groups or reduce the average number of faults in the equivalent fault groups.

[0043]

[0036] Test application in chip manufacturing test is normally performed by automatic test equipment (ATE) (a type of testers). Scan-based tests consume significant amounts of storage and test time on ATE. The data volume increases with the number of logic gates on the chip and the same holds for the number of scan cells. Yet, practical considerations and ATE specifications often limit both the number of pins available for scan in / out and the maximum scan frequency. It is highly desirable to reduce the amount of test data that need to be loaded onto ATE and ultimately to the circuit under test. Fortunately, test patterns are compressible mainly because only 1% to 5% of test pattern bits are typically specified bits (care bits) while the rest are unspecified bits (don't-care bits). Unspecified bits can take on any values with no impact on the fault coverage. Test compression may also take advantage of the fact that test cubes tend to be highly correlated. A test cube is a deterministic test pattern in which the don't-care bits are not filled by ATPG. The correlation exists because faults are structurally related in the circuit.

[0044]

[0037] Various test compression techniques have been developed. In general, additional on-chip hardware before and after scan chains is inserted. The hardware (decompressor) added before scan chains is configured to decompress test stimulus coming from ATE, while the hardware (compactor) added after scan chains is configured to compact test responses captured by the scan chains. The decompressor expands the data from n tester channels to fill greater than n scan chains. The increase in the number of scan chains shortens each scan chain and thus reduces the number of clock cycles needed to shift in each test pattern. Thus, test compression can not only reduce the amount of data stored on the tester but also reduce the test time for a given test data bandwidth.

[0045] Illustrative Operating Environment

[0046]

[0038] Various examples of the disclosed technology may be implemented through the execution of software instructions by a computing device, such as a programmable computer. Accordingly, Fig. 1 shows an illustrative example of a computing device 101. As seen in this figure, the computing device 101 includes a computing unit 103 with a processing unit 105 and a system memory 107. The processing unit 105 may be any type of programmable electronic device for executing software instructions, but it will conventionally be a microprocessor. The system memory 107 may include both a readonly memory (ROM) 109 and a random access memory (RAM) 111. As will be appreciated by those of ordinary skill in the art, both the read-only memory (ROM) 109 and the random access memory (RAM) 111 may store software instructions for execution by the processing unit 105.

[0047]

[0039] The processing unit 105 and the system memory 107 are connected, either directly or indirectly, through a bus 113 or alternate communication structure, to one or more peripheral devices. For example, the processing unit 105 or the system memory 107 may be directly or indirectly connected to one or more additional memory storage devices, such as a “hard” magnetic disk drive 115, a removable magnetic disk drive 117, an optical disk drive 119, or a flash memory card 121. The processing unit 105 and the system memory 107 also may be directly or indirectly connected to one or more input devices 123 and one or more output devices 125. The input devices 123 may include, for example, a keyboard, a pointing device (such as a mouse, touchpad, stylus, trackball, or joystick), a scanner, a camera, and a microphone. The output devices 125 may include, for example, a monitor display, a printer and speakers. With various examples of the computer 101, one or more of the peripheral devices 115-125 may be internally housed with the computing unit 103. Alternately, one or more of the peripheral devices 115-125 may be external to the housing for the computing unit 103 and connected to the bus 113 through, for example, a Universal Serial Bus (USB) connection.

[0048]

[0040] With some implementations, the computing unit 103 may be directly or indirectly connected to one or more network interfaces 127 for communicating with other devices making up a network. The network interface 127 translates data and control signals from the computing unit 103 into network messages according to one or more communication protocols, such as the transmission control protocol (TCP) and the Internet protocol (IP). Also, the interface 127 may employ any suitable connection agent (or combination of agents) for connecting to a network, including, for example, a wireless transceiver, a modem, or an Ethernet connection. Such network interfaces and protocols are well known in the art, and thus will not be discussed here in more detail.

[0049]

[0041] It should be appreciated that the computer 101 is illustrated as an example only, and it is not intended to be limiting. Various embodiments of the disclosed technology may be implemented using one or more computing devices that include the components of the computer 101 illustrated in Fig. 1, which include only a subset of the components illustrated in Fig. 1, or which include an alternate combination of components, including components that are not shown in Fig. 1. For example, various embodiments of the disclosed technology may be implemented using a multi-processor computer, a plurality of single and / or multiprocessor computers arranged into a network, or some combination of both.

[0050] Test Pattern Reordering Tool

[0051]

[0042] Fig. 2 illustrates an example of a test pattern reordering tool 200 that may be implemented according to various embodiments of the disclosed technology. As seen in this figure, the test pattern reordering tool 200 includes a fault partition node system creation unit 210, a diagnosis coverage contribution determination unit 220, and a reordering unit 230. Various implementations of the test pattern reordering tool 200 may cooperate with (or incorporate) one or both of an input database 205 and an output database 255.

[0052]

[0043] As will be discussed in more detail below, the test pattern reordering tool 200 can receive, from the input database 205, a circuit design, a plurality of faults, and a plurality of test patterns. The circuit design has one or more test response output channels. The fault partition node system creation unit 210 can create a fault partition node system for the circuit design based on fault simulation for each of the plurality of test patterns. Based on the fault partition node system, the diagnosis coverage contribution determination unit 220 can determine a diagnosis coverage contribution value for each of the plurality of test patterns based on the fault partition node system. The reordering unit 230 can reorder test patterns in the plurality of test patterns based on the diagnosis coverage contribution value. The above operations of creating, determining and reordering can be repeated. The test pattern reordering tool 200 can store information of the reordered test patterns in the output database 255.

[0053]

[0044] As previously noted, various examples of the disclosed technology may be implemented by one or more computing systems, such as the computing system illustrated in Fig. 1. Accordingly, one or more of the fault partition node system creation unit 210, the diagnosis coverage contribution determination unit 220, and the reordering unit 230 may be implemented by executing programming instructions on one or more processors in one or more computing systems, such as the computing system illustrated in Fig. 1. Correspondingly, some other embodiments of the disclosed technology may be implemented by software instructions, stored on a non-transitory computer-readable medium, for instructing one or more programmable computer s / computer systems to perform the functions of one or more of the fault partition node system creation unit 210, the diagnosis coverage contribution determination unit 220, and the reordering unit 230. As used herein, the term “non-transitory computer-readable medium” refers to computer- readable medium that are capable of storing data for future retrieval, and not propagating electro-magnetic waves. The non-transitory computer-readable medium may be, for example, a magnetic storage device, an optical storage device, or a solid state storage device.

[0054]

[0045] It also should be appreciated that, while the fault partition node system creation unit 210, the diagnosis coverage contribution determination unit 220, and the reordering unit 230 are shown as separate units in Fig. 1, a single computer (or a single processor within a master computer) or a single computer system may be used to implement some or all of these units at different times, or components of these units at different times.

[0055]

[0046] With various examples of the disclosed technology, the input database 205 and the output database 255 may be implemented using any suitable computer readable storage device. That is, either of the input database 205 and the output database 255 may be implemented using any combination of computer readable storage devices including, for example, microcircuit memory devices such as read-write memory (RAM), read-only memory (ROM), electronically erasable and programmable read-only memory (EEPROM) or flash memory microcircuit devices, CD-ROM disks, digital video disks (DVD), or other optical storage devices. The computer readable storage devices may also include magnetic cassettes, magnetic tapes, magnetic disks or other magnetic storage devices, holographic storage devices, or any other non-transitory storage medium that can be used to store desired information. While the input database 205 and the output database 255 are shown as separate units in Fig. 2, a single data storage medium may be used to implement some or all of these databases. Test Pattern Reordering For Improving Diagnosis Coverage

[0056]

[0047] Fig. 3 illustrates a flowchart 300 showing a process of test pattern reordering for improving diagnosis coverage that may be implemented according to various examples of the disclosed technology. For ease of understanding, methods of test pattern reordering for improving diagnosis coverage that may be employed according to various embodiments of the disclosed technology will be described with reference to the test pattern reordering tool 200 in Fig. 2 and the flow chart 300 illustrated in Fig. 3. It should be appreciated, however, that alternate implementations of a test pattern reordering tool may be used to perform the methods of test pattern reordering for improving diagnosis coverage illustrated by the flow chart 300 according to various embodiments of the disclosed technology. Likewise, the test pattern reordering tool 200 may be employed to perform other methods of test pattern reordering for improving diagnosis coverage according to various embodiments of the disclosed technology.

[0057]

[0048] In operation 310 of the flow chart 300, the test pattern reordering tool 200 receives, from the input database 205, a circuit design, a plurality of faults, and a plurality of test patterns. The plurality of test patterns may be test patterns used for test chips during the manufacturing process. According to some embodiments of the disclosed technology, the plurality of faults may be separated into a number of equivalent fault groups. Faults in an equivalent fault group are faults that cannot be distinguished under a certain condition. The certain condition can be related to a group of test patterns. Equivalent fault groups can be changed with the condition. When additional test patterns are used, for example, some or all of the existing equivalent fault groups may be divided into new equivalent fault groups, resulting in more equivalent fault groups. On the other hand, when some of the test patterns are removed from being considered, some or all of the existing equivalent fault groups may be merged into new equivalent fault groups, resulting in fewer equivalent fault groups.

[0058]

[0049] The received circuit design has one or more test response output channels. Test response output channels, sometimes referred to as output pins, may be coupled to outputs of scan chains in the circuit design. Fig. 4A illustrates an example of test response output channels 400 that are coupled to outputs of scan chains 410. As described previously, the scan chains 410, formed by connecting scan cells in serial, can be used not only to shift in and launch test stimuli but also to capture and shift out test response bits. As also described previously, various test compression techniques are often employed to address challenges related to the continuously increasing volume of test data. Thus, test response output channels may be coupled to outputs of a test response compactor rather than directly to scan chains. Fig. 4B illustrates an example of test response output channels 420 in a test compression environment. In this setup, the test response output channels 420 are coupled to outputs of a test response compactor 430. The test response compactor 430 is configured to compact test responses captured by scan chains 440. The scan chains 440 is configured to load decompressed test patterns from a decompressor 450. The embedded deterministic test (EDT) is one example test compression technique. If this technique is employed, the decompressor 450 comprises a ring generator and an associated phase shifter, and the test response compactor 430 comprises one or more XOR gate networks. In some cases where an on-chip comparator is used to compare captured test response bits with good-machine test response bits, test response output channels may be coupled to outputs of the on-chip comparator.

[0059]

[0050] Referring back to Fig. 3, in operation 320, the fault partition node system creation unit 210 creates a fault partition node system for the circuit design based on fault simulation for each of the plurality of test patterns. The creation will be discussed in detail later.

[0060]

[0051] In operation 330, the diagnosis coverage contribution determination unit 220 determines a diagnosis coverage contribution value for each of the plurality of test patterns based on the fault partition node system. As discussed previously, a test pattern contains specified bits (care bits) while the rest are unspecified bits (don't-care bits). Test pattern care bits are those with values needed for detecting a fault (activating the fault and propagating the fault effect to be observed). In a similar fashion, the test response bits that can be used to distinguish a fault from another are referred to as diagnosis care bits. Just like the don’t care bits, a huge number of test response bits observed do not contribute to diagnosis. Even a large number of failing bits cannot distinguish known faults. For two faults A and B, a test response bit outputted from a test response output channel at a specific clock cycle can be called as a diagnosis care bit if it is a passing bit for the fault A but a failing bit for the fault B. If a test pattern M have more diagnosis care bits than a test pattern N, then the test pattern M can contribute to the diagnosis coverage more than the test pattern N. Therefore, the number of diagnosis care bits associated with a test pattern can be used as the diagnosis coverage contribution value for this test pattern. During the creation of the fault partition node system, which will be described in detail below, the number of diagnosis care bits for each test pattern can be collected and recorded.

[0061]

[0052] Alternatively, the number of fault partition nodes associated with a test pattern can be used as the diagnosis coverage contribution value for this test pattern. A fault partition node system can comprise a set of connected fault partition nodes, which is also referred to as an asymmetric partition tree. As will be described in detail below, one or more new fault partition nodes are created in an observation-clock-cycle-based fault partition node system if an existing equivalent fault group associated with the existing fault partition node is separated into two or more new equivalent fault groups based on one or more test response bits at an observation clock cycle. The more fault partition nodes, the more equivalent fault groups for a given set of faults, and thus the higher diagnosis coverage. It should be noted that a diagnosis care bit can be associated with more than one fault partition nodes. It should also be noted that one fault partition node in a fault partition node system for a circuit design having multiple test response output channels can be associated with more than one diagnosis case bit.

[0062]

[0053] In operation 340, the reordering unit 230 reorders test patterns in the plurality of test patterns based on the diagnosis coverage contribution value. In a circuit test, a tester applies test patterns to a chip in a sequence, one test pattern at a time. The tester usually only store failing bits and its failing bit buffer has a limited size. It is thus advantageous to apply the test patterns having high impact on diagnosis coverage first. This can ensure that the important data for diagnosis like diagnosis care bits can be stored for analysis. Many test patterns may not contain any diagnostic care bits but can still contribute to test coverage. These patterns can be placed toward the end of the sequence. The test patterns having the largest diagnosis coverage contribution values can be move to the front of the sequence.

[0063]

[0054] A fault partition node system is created based on the sequence of the test patterns applied to testing the circuit. Once the sequence is changed, a different fault partition node system may be created, and the diagnosis coverage contribution value for each of the plurality of test patterns may be changed. In some embodiments of the disclosed technology, the operations 320, 330 and 340 are repeated. The process may continue for a predetermined number of times or until the new sequence does not vary much from the old sequence.

[0064]

[0055] In operation 350, the test pattern reordering tool 200 can store information of the reordered test patterns in the output database 255.

[0065] Fault Partition Node System Creation

[0066]

[0056] Fig. 5 illustrates a flowchart 500 showing a process of fault partition node system creation that may be implemented according to various examples of the disclosed technology. A fault partition node system can be an observation-clock-cycle-based fault partition node system or a test-pattern-based fault partition node system. The following description will focus on generating an observation-clock-cycle-based fault partition node system. Generating an observation-clock-cycle-based fault partition node system can follow a similar process.

[0067]

[0057] In operation 510, a circuit design, a plurality of faults, and one or more test patterns are received. According to some embodiments of the disclosed technology, the plurality of faults may be in a big group or separated into a number of equivalent fault groups. Faults in an equivalent fault group are faults that cannot be distinguished under a certain condition. The certain condition can be test response bits for a group of test patterns which, when used, cannot differentiate one fault in an equivalent fault group from another one in the same equivalent fault group. Equivalent fault groups can be changed with the condition. When additional test response bits for another group of test patterns are employed, some or all of the existing equivalent fault groups can be divided into new equivalent fault groups. The received circuit design has one or more test response output channels. Test response output channels, sometimes referred to as output pins, may be coupled to outputs of scan chains in the circuit design.

[0068]

[0058] In operation 520, fault simulation is performed for each of the one or more test patterns in a sequence to determine a test response bit at each of observation clock cycles from each of the one or more test response output channels. In a typical fault simulation process, a fault is injected into the circuit, and then a test pattern is applied to the fault- injected circuit by launching bits of the test pattern from scan cells to functional circuitry of the circuit. Test response bits generated by the functional circuitry of the circuit are captured by the scan cells and are shifted out either directly from the scan chains or from a compactor after being compacted. The test response bits shifted out of the test response output channels are referred to as observed test response bits, or simply test response bits. The test response bits can comprise passing bits (the same as the corresponding goodmachine bits) and failing bits (different from the corresponding good-machine bits). During the shift-out operation, the test response bits come out of each test response output channel one bit per observation clock cycle.

[0069]

[0059] As noted previously, test patterns are shifted into scan chains and applied to the circuit one at a time. After test response bits for the current test pattern are captured, they are being shifted out while the next test pattern is being shifted in. As such, test patterns are applied to the circuit in a particular sequence during scan testing. The sequence in which the one or more test patterns is used for the fault simulation in the operation 520 is the same as the one in which the one or more test patterns would be used to test a circuit fabricated according to the circuit design.

[0070]

[0060] In operation 530, a fault partition node system for the circuit design is created / expanded based on the test response bits. The fault partition node system comprises fault partition nodes and equivalent fault groups. Each of the fault partition nodes is associated with one of the equivalent fault groups. Here, the fault partition nodes include a root node. Each of the equivalent fault groups comprises one or more faults in the plurality of faults. When the circuit design has more than one test response output channels, the fault partition node system can be a fault partition node system for the whole circuit design or a fault partition node system for each of the test response output channels. The fault partition node systems generated for individual test response output channels can be combined into the fault partition node system for the whole circuit design.

[0071]

[0061] The operation 530 can comprise a series of suboperations for creating new fault partition nodes and for associating new equivalent fault groups with the new fault partition nodes and the existing fault partition nodes. Fig. 6 illustrates a flowchart 600 showing an example process for creating new fault partition nodes that may be implemented according to various examples of the disclosed technology. In operation 610, whether an existing equivalent fault group can be separated into N (N > 1) equivalent fault groups based on one or more test response bits at the current observation clock cycle is determined. If two faults in the existing equivalent fault group have different test response bits, then they can be placed into two new equivalent fault groups. This shows a major difference between fault simulation for test and fault simulation for diagnosis. The former focuses on whether a fault is detectable by comparing test response bits with good-machine test response bits, while the latter focuses on whether faults can be separated by comparing test response bits among themselves (these test response bits may be ones that are derived by comprising with good-machine test response bits). Another difference is about fault list updating. For test purposes, a fault that can be detected by one or more test patterns may be removed from the group of faults and would not be involved in further fault simulation for other test patterns. For diagnosis purposes, on the other hand, a fault that is alone in an equivalent fault group may be removed from the group of faults and would not be involved in further fault simulation for other test patterns. This may be leveraged to speed up the process of fault partition node system generation as will be discussed in more detail below.

[0072]

[0062] If the operation 610 determines that the existing equivalent fault group can be separated into N (N > 1) equivalent fault groups based on the one or more test response bits at the current observation clock cycle, the flow chart 600 will proceed to an operation 620.

[0073] Otherwise, the flow chart 600 will proceed to an operation 650.

[0074]

[0063] In operation 620, (TV - 1) new fault partition nodes are created for an existing fault partition node associated with the existing equivalent fault group. In operation 630, the N new equivalent fault groups are associated with the (TV - 1) new fault partition nodes and the existing fault partition node, respectively. According to various embodiments of the disclosed technology, the new equivalent fault group to be associated with the existing fault partition node is the one having the number of failing bits smaller than any of the other new equivalent fault groups. In operation 640, the association of the existing equivalent fault group with the existing fault partition node is removed.

[0075]

[0064] In operation 650, which can also be reached directly from the operation 610 as noted previously, the process moves to the next observation clock cycle at which the test response bits include at least a failing bit. The operations 610-650 can be repeated for each of the new equivalent fault groups by treating it as an existing equivalent fault groups unless a new equivalent fault group has only one fault. The reason to skip observation clock cycles at which the test response bits include no failing bit is because that faults cannot be separated based on the test response bits that are all passing bits. The process illustrated by the flow chart 600 may be terminated when the test response bits for all of the test patterns (i.e., for all of the observation clock cycles) are analyzed or each fault in the existing equivalent fault group is placed alone in a new equivalent fault group.

[0076]

[0065] It should be noted that, for each existing equivalent fault group, the process illustrated by the flow chart 600 can be performed independently. Therefore, the process illustrated by the flow chart 600 may be performed for multiple existing fault partition nodes in parallel, which can significantly increase the overall processing speed.

[0077]

[0066] Fig. 7 uses a diagram 700 as an example to illustrate a process for creating new fault partition nodes that may be implemented according to various examples of the disclosed technology. In the diagram 700, an existing fault partition node 710 is initially associated with an equivalent fault group 730. Based on one or more test response bits 705 at an observation clock cycle, the equivalent fault group 730 is divided into (TV - 1) new equivalent fault groups 740 and a new equivalent fault group 750. Accordingly, (N - 1) new fault partition nodes 720 are created. Each of the (N - 1) new equivalent fault groups 740 is associated with one of the (A - I ) new fault partition nodes 720. The new equivalent fault group 750 is associated with the existing fault partition node 710, replacing the equivalent fault group 730. This can be repeated to further create new fault partition nodes for the newly-created fault partition nodes. According to various embodiments of the disclosed technology, the new equivalent fault group 750 can be the one that has the number of failing bits smaller than any of the new equivalent fault groups 740.

[0078]

[0067] The term “fault partition node system” is a high-level description of a set of related equivalent fault groups derived based on test response bits derived by fault simulation up to a certain observation clock cycle or a test pattern. Accordingly, a process of the fault partition node system generation can be used to derive equivalent fault groups under a particular condition for a particular circuit design. Moreover, a created / expanded fault partition node system can show the family relationship between its equivalent fault groups. Some faults are separated from each other at an early stage while others are separated from each other at a late stage. The fault partition node system can also include other information such as the failing bit information, the observation clock cycle information, or both. Combining the family relationship information with the additional information, the fault partition node system can be shrunk or grown further to a new fault partition node system that takes account of some constraint such as the tester storage limit and the number of test patterns applied without redoing the generation process. This is useful for predicting diagnosis coverage values under various constraints.

[0079]

[0068] As noted above, a fault partition node and its associated equivalent fault group may further be associated with failing bit information, observation clock cycle information, or both. Fig. 7 shows failing bit information and observation clock cycle information 760 can be associated with the existing fault partition node 710 and each of the new fault partition nodes 720. Each new equivalent fault group is derived based on a unique combination of failing and passing bits. With this associated failing bit information, the fault partition node system can be used to perform dictionary-based diagnosis. Additionally or alternatively, the failing bit information may include cumulative failing bit counts for a particular fault partition node. This can allow generation of a new fault partition node system for predicting the diagnosis coverage under a constraint associated with a tester. For example, a tester usually only store failing bits and its failing bit buffer has a limited size. To generate a new fault partition node system meeting the constraint, the fault partition nodes having cumulated failing bit counts above a threshold can be merged recursively with corresponding parent fault partition nodes. Using the above process, a profile of diagnosis coverage vs failing bit limit can be derived.

[0080]

[0069] The observation clock cycle information with which the fault partition nodes can be associated shows observation clock cycles at which the fault partition nodes are created. This can allow generation of a new fault partition node system for predicting the diagnosis coverage under a constraint associated with a threshold observation clock cycle or a subgroup of test patterns in the one or more test patterns. To generate the new fault partition node system, the fault partition nodes with which observation clock cycles associated are greater than the threshold observation clock cycle or a largest observation clock cycle for the subgroup of test patterns can be merged recursively with corresponding parent fault partition nodes. Using the above process, a profile of diagnosis coverage vs number of test patterns can be derived.

[0081]

[0070] As noted previously, a fault partition node system can be generated for each of the one or more test response output channels. Fig. 8 uses a diagram 800 as an example to illustrate a process for creating new fault partition nodes for one test response output channel that may be implemented according to various examples of the disclosed technology. In the diagram 800, an existing fault partition node 810 is initially associated with an equivalent fault group 830. A single test response output channel can output only one test response bit per observation clock cycle. Only a failing test response bit may separate faults in an existing equivalent fault group into two new equivalent fault groups. In Fig. 8, a single failing test response bit 805 at an observation clock cycle divides the equivalent fault group 830 is divided into two new equivalent fault groups 840 and 850. Accordingly, a new fault partition node 820 is created. The new equivalent fault group 840 is associated with the new fault partition node 820 and the new equivalent fault group 850 is associated with the existing fault partition node 810, replacing the equivalent fault group 830. This can be repeated to further create new fault partition nodes for the newly- created fault partition nodes. In this process, the new equivalent fault group to be associated with the existing fault partition node can be set to be the one that has a passing bit according to some embodiments of the disclosed technology. Under this rule, it is the new equivalent fault group 840 in Fig. 8 that has the failing bit since it is associated with the new fault partition node 820. Similar to Fig. 7, failing bit information and observation clock cycle information 860 can be associated with the existing fault partition node 810 and the new fault partition node 820.

[0082]

[0071] It should be noted that the equivalent fault groups derived for a test response output channel may not be the final equivalent fault groups if the circuit design has more than one test response output channel. The final equivalent fault groups can be obtained by comparing faults in an equivalent fault group in one fault partition node system for one test response output channel with faults in other equivalent fault groups in other fault partition node systems for other test response output channels. This may further separate faults in the equivalent fault groups derived for individual test response output channels.

[0083]

[0072] Referring back to Fig. 5, it should be noted that the operations 520 and 530 do not need to be performed in serial for all of the one or more test patterns. In another word, fault simulation does not need to be performed for all of the one or more test patterns before starting to create / expand the fault partition node system. The two operations may be performed “concurrently.”

[0073] A fault partition node system can be an observation-clock-cycle-based fault partition node system or a test-pattern-based fault partition node system. The above description focuses on generating an observation-clock-cycle-based fault partition node system. Generating a test-pattern-based fault partition node system can follow a similar process. Rather than checking whether faults in an equivalent fault group can be distinguished based on test response bits at a particular observation clock cycle, a test-pattern-based fault partition node system generation tool checks whether faults in an equivalent fault group can be distinguished based on test response bits for a test pattern.

[0084] Selective Chain Diagnosis For Performance Improvement

[0085]

[0074] Fig. 9 illustrates a flowchart 900 showing a process of selective chain diagnosis for performance improvement that may be implemented according to various examples of the disclosed technology. In operation 910, a circuit design, a plurality of faults, and a plurality of test patterns are received. The plurality of test patterns are test patterns used for test chips during the manufacturing process. According to some embodiments of the disclosed technology, the plurality of faults may be separated into a number of equivalent fault groups.

[0086]

[0075] In operation 920, a fault partition node system for the circuit design is created based on fault simulation for each of the plurality of test patterns. The creation is discussed in the previous section.

[0087]

[0076] In operation 930, equivalent fault group information for each of scan chains in the circuit design is determined based on the fault partition node system. The equivalent fault group information may include the number of equivalent faults in the largest equivalent fault group for the scan chain at issue. In the fault partition node system, each fault partition node is associated with an equivalent fault group. For chain diagnosis, faults in an equivalent fault group typically are associated with a single scan chain. As such, it would not be difficult to determine the number of equivalent faults in the largest equivalent fault group for a scan chain for a particular fault type.

[0077] In operation 940, a chain diagnosis process is performed only on scan chains that can meet a diagnosis resolution threshold based on the equivalent fault group information. After a circuit test, some scan chains may be identified as having defects using chain patterns. Subsequently, test response bits collected after applying test patterns (scan patterns) to the circuit are analyzed in a chain diagnosis process to determine defective scan cell candidates. Such a chain diagnosis process involves fault simulation and many scan chains and thus can be time consuming. However, diagnosis results for some of these defective scan chains may not be suitable for guiding physical failure analysis (PF A) due to poor diagnosis resolution. The poor diagnosis resolution leads to too many fault candidates which mean too many scan cells and thus too large physical areas for physical failure analysis. Therefore, the chain diagnosis process can be speeded up by not diagnosing these scan chains. Users of the chain diagnosis software tool can set a diagnosis resolution threshold. If a chain diagnosis process performed on a particular faulty chain cannot reach a resolution below the threshold, the chain diagnosis software tool will not perform it for this faulty scan chains. Focusing only on scan chains that can meet a diagnosis resolution threshold can significantly improve the performance of the overall chain diagnosis process.

[0088] Conclusion

[0089]

[0078] Having illustrated and described the principles of the disclosed technology, it will be apparent to those skilled in the art that the disclosed embodiments can be modified in arrangement and detail without departing from such principles. In view of the many possible embodiments to which the principles of the disclosed technologies can be applied, it should be recognized that the illustrated embodiments are only preferred examples of the technologies and should not be taken as limiting the scope of the disclosed technology. Rather, the scope of the disclosed technology is defined by the following claims and their equivalents. We therefore claim as our disclosed technology all that comes within the scope and spirit of these claims.

Claims

What is claimed is:

1. A method, executed by at least one processor of a computer, comprising: receiving a circuit design, a plurality of faults, and a plurality of test patterns; creating a fault partition node system for the circuit design based on fault simulation for each of the plurality of test patterns; determining a diagnosis coverage contribution value for each of the plurality of test patterns based on the fault partition node system; reordering test patterns in the plurality of test patterns based on the diagnosis coverage contribution value; and storing the reordered plurality of test patterns.

2. The method recited in claim 1 , wherein the fault simulation is performed for each of the one or more test patterns in a sequence to determine test response bits from each of one or more test response output channels of the circuit design, the sequence being the same as a sequence in which the one or more test patterns would be used to test a circuit fabricated according to the circuit design, the test response bits comprising passing bits and failing bits, and wherein the generating a fault partition node system and the expanding the fault partition node system are based on the test response bits determined by the fault simulation, the fault partition node system comprising fault partition nodes and equivalent fault groups, each of the fault partition nodes being associated with one of the equivalent fault groups, each of the equivalent fault groups comprising one or more faults in the plurality of faults, the generating comprising:creating (N - 1) new fault partition nodes for an existing fault partition node if an existing equivalent fault group associated with the existing fault partition node is separated into N new equivalent fault groups based on one or more test response bits at an observation clock cycle, associating the N new equivalent fault groups with the (N - 1) new fault partition nodes and the existing fault partition node, respectively, and removing the association of the existing equivalent fault group with the existing fault partition node.

3. The method recited in claim 2, wherein the fault partition node system is generated for each of the one or more test response output channels, a number of fault partition node systems generated being equal to a number of the one or more test response output channels, wherein N = 2 and the generating comprising: creating a new fault partition node for an existing fault partition node if an existing equivalent fault group associated with the existing fault partition node is separated into two new equivalent fault groups based on a failing bit at an observation clock cycle; associating the two new equivalent fault groups with the new fault partition node and the existing fault partition node, respectively; and removing the association of existing equivalent fault group with the existing fault partition node.

4. The method recited in claim 3, wherein one of the two new equivalent fault groups having the failing bit is associated with the new fault partition node.

5. The method recited in claim 1, further comprising: repeating the generating, the deriving and the reordering by using the plurality of reordered test patterns.

6. The method recited in claim 5, wherein the repeating continues until diagnosis coverage cannot be improved.

7. The method recited in claim 1, wherein the diagnosis coverage contribution value is a number of diagnosis care bits or a number of fault partition nodes.

8. A method, executed by at least one processor of a computer, comprising: receiving a circuit design, a plurality of faults, and a plurality of test patterns; generating a fault partition node system for the circuit design based on fault simulation for each of the plurality of test patterns; determining equivalent fault group information for each of scan chains in the circuit design based on the fault partition node system; and performing a chain diagnosis process only on scan chains that can meet a diagnosis resolution threshold based on the equivalent fault group information.

9. The method recited in claim 8, wherein the fault simulation is performed for each of the one or more test patterns in a sequence to determine test response bits from each of one or more test response output channels of the circuit design, the sequence being the same as a sequence in which the one or more test patterns would be used to test a circuit fabricated according to the circuit design, the test response bits comprising passing bits and failing bits, and wherein the generating a fault partition node system and the expanding the fault partition node system are based on the test response bits determined by the fault simulation, the fault partition node system comprising fault partition nodes and equivalent fault groups, each of the fault partition nodes being associated with one of the equivalent fault groups, each of the equivalent fault groups comprising one or more faults in the plurality of faults, the generating comprising: creating (N - 1) new fault partition nodes for an existing fault partition node if an existing equivalent fault group associated with the existing fault partition node is separated into N new equivalent fault groups based on one or more test response bits at an observation clock cycle, associating the N new equivalent fault groups with the (N - 1) new fault partition nodes and the existing fault partition node, respectively, and removing the association of the existing equivalent fault group with the existing fault partition node.

10. The method recited in claim 9, wherein the fault partition node system is generated for each of the one or more test response output channels, a number of fault partition nodesystems generated being equal to a number of the one or more test response output channels, wherein N= 2 and the generating comprising: creating a new fault partition node for an existing fault partition node if an existing equivalent fault group associated with the existing fault partition node is separated into two new equivalent fault groups based on a failing bit at an observation clock cycle; associating the two new equivalent fault groups with the new fault partition node and the existing fault partition node, respectively; and removing the association of existing equivalent fault group with the existing fault partition node.

11. The method recited in claim 10, wherein one of the two new equivalent fault groups having the failing bit is associated with the new fault partition node.

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