Decoding forward error correction codewords using combinatorial logic circuits performing finite field operations

WO2025184566A1PCT designated stage Publication Date: 2025-09-04KANDOU LABS SA +1

Patent Information

Application Number
PCT/US2025/017936
Authority / Receiving Office
WO · WO
Patent Type
Applications
Current Assignee / Owner
Priority Date
2024-09-27
Filing Date
2025-02-28
Publication Date
2025-09-04

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Abstract

Receiving a codeword of a forward error correction (FEC) code, each codeword in the FEC code having a minimum distance of at least seven to any other codeword in the FEC code, calculating multi-bit syndromes by applying columns of a check matrix to the received codeword using combinatorial logic, and responsively determining the received codeword comprises at least three errors, determining coefficients of an error locator polynomial using a coefficient combinatorial logic circuit by combining the multi-bit syndromes using non-iterative combinatorial logic performing arithmetic operations in a finite field F(2 n ), determining respective error positions for each error of the at least three errors by determining roots of the error locator polynomial using a non-iterative root-finding combinatorial logic circuit, the non-iterative root-finding combinatorial logic circuit performing arithmetic operations in the finite field F(2 n ), and correcting each of the at least three errors in the received codeword.
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Description

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Claims

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