Voltage subtraction cell

Abstract

A conventional haptic feedback system includes a voltage converter circuit, which applies a high-voltage signal to a piezoelectric transducer, allowing it to generate a mechanical movement sufficient to give a haptic sensation to a user. Conversely, when a force is applied to the piezoelectric transducer by the user, a sensing circuit generates a sensed voltage signal, which enables the piezoelectric transducer to act as a switch. A voltage subtraction cell is added to the existing voltage converter circuits to improve efficiency at a required operating condition for virtual texture generation.

Description

VOLTAGE SUBTRACTION CELLTECHNICAL FIELD

[0001] The present disclosure relates to a voltage subtraction (VS) cell, and in particular to a voltage subtraction cell for use with a voltage converter circuit.BACKGROUND

[0002] Virtual textures on flat surfaces, such as touch screens on electronic devices, e.g. computer monitors and smart devices, which also can provide haptic feedback to the user, can be achieved using friction modulation techniques; however, these techniques require piezoelectric transducers, e.g. lOnF, operated using high voltage amplitudes, e.g. tens of volts, and ultrasonic frequencies, e.g. about 40 to 100 kHz. To implement this kind of haptic feedback into portable electronic devices, a compact and efficient piezoelectric controller and voltage converter circuit is required for converting a low DC voltage, commonly available via a battery, into a high AC voltage needed to drive the piezoelectric transducers.

[0003] A known voltage converter circuit topology is disclosed in United States Patent No. 10,199,555, issued February 5, 2019, to Simon Chaput, which is incorporated herein by reference. However, there is a constant need to reduce energy consumption, to reduce the electronic device autonomy and the overall heat the electronic device must dissipate.

[0004] In conventional haptic feedback systems, which use the piezoelectric effect, a voltage converter (driver) circuit applies a high-voltage signal to the piezoelectric transducer, and in response to the applied high-voltage signal, the piezoelectric transducer generates a mechanical movement sufficient to give a haptic sensation to a user. In addition, when a force is applied to the piezoelectric transducer by the user, a sensing circuit generates a sensed voltage signal, which enables the piezoelectric transducer to act as a switch. When the driver circuit and the sensing circuit are the same circuit, many limitations exist on the accuracy of the sensing.

[0005] An object of the present disclosure is to provide a voltage subtraction cell, which can be added to existing voltage converter circuits to improve efficiency at a required operating condition for virtual texture generation.SUMMARY

[0006] Accordingly, a first apparatus includes an apparatus for operating a piezoelectric transducer, configured for coupling to an input voltage source, which provides an input voltage, and configured to transmit a drive voltage across the piezoelectric transducer, the apparatus comprising:

[0007] a voltage converter circuit configured to convert the input voltage to a higher peak, AC driver voltage;

[0008] a first voltage subtraction cell comprising a first capacitor and a first plurality of switches, including a first switch and a second switch; and

[0009] a controller configured to add the capacitor in series to the voltage converter circuit or bypass the capacitor based on which of the first plurality of switches is turned on.

[0010] In any of the above embodiments the voltage converter circuit may comprise a forward- boost / reverse-buck converter configured to enable current flows from the input voltage source to the piezoelectric transducer, then back to the input voltage source using a same electrical path, whereby a voltage on the capacitor remains substantially stable.

[0011] In any of the above embodiments the capacitor may have a first capacitance at least lOx larger than a second capacitance of the piezoelectric transducer to prevent excessive voltage swings on the capacitor.

[0012] In any of the above embodiments the first switch may be configured in parallel to the second switch, and the first capacitor configured in series with the second switch.

[0013] In any of the above embodiments the first switch may be configured in series with the second switch and the first capacitor.

[0014] In any of the above embodiments the first capacitor may be positioned between the first switch and the second switch.

[0015] In any of the above embodiments the first capacitor may be positioned between the voltage converter circuit and the first and second switches.

[0016] In any of the above embodiments the voltage converter circuit may comprise an inductor and a second plurality of switches, including a third switch and a fourth switch.

[0017] In any of the above embodiments the first voltage subtraction cell may be positioned between the third switch and the fourth switch.

[0018] In any of the above embodiments a shared node may be provided between a source of the second switch and a source of the fourth switch; and the apparatus may further comprise a single first bootstrapped capacitor for gate drivers of the second switch and the fourth switch.

[0019] In any of the above embodiments the first voltage subtraction cell may be positioned between the fourth switch and the piezoelectric transducer.

[0020] In any of the above embodiments the first voltage subtraction cell may be positioned in parallel to the fourth switch.

[0021] In any of the above embodiments the voltage converter circuit may comprise: the inductor connected to the voltage source; the third switch connected between the inductor and a ground, and the fourth switch connected between the inductor and the piezoelectric transducer; wherein the controller is configured to turn the third switch on, whereby current in the inductor increases a driver voltage to a desired output voltage; and then to subsequently turn the third switch off enabling current to flow from the inductor through the fourth switch to the piezoelectric transducer.

[0022] In any of the above embodiments the voltage converter circuit may be configured to amplify the input voltage by greater than 5x.

[0023] In any of the above embodiments, the apparatus may further comprise a second voltage subtraction cell comprising a second capacitor and a third plurality of switches, including a fifth switch and a sixth switch.

[0024] In any of the above embodiments the second voltage subtraction cell may be in series with the first voltage subtraction cell.

[0025] In any of the above embodiments the second voltage subtraction cell may be in parallel with the first voltage subtraction cell.

[0026] In any of the above embodiments the apparatus can further comprise a low voltage switch between the piezoelectric transducer and a reference voltage thereof configured to prevent unwanted resonance cycles.BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Some example embodiments will be described in greater detail with reference to the accompanying drawings, wherein:

[0028] FIG. l is a schematic diagram of a driver circuit for a piezoelectric transducer in accordance with an example of the present disclosure;

[0029] FIG. 2 is a schematic diagram of a driver circuit for a piezoelectric transducer in accordance with another example of the present disclosure;

[0030] FIG. 3 is a schematic diagram of a driver circuit for a piezoelectric transducer in accordance with another example of the present disclosure;

[0031] FIG. 4 is a schematic diagram of a driver circuit for a piezoelectric transducer in accordance with another example of the present disclosure; and

[0032] FIG. 5 is a schematic diagram of a driver circuit for a piezoelectric transducer in accordance with another example of the present disclosure.DETAILED DESCRIPTION

[0033] While the present teachings are described in conjunction with various embodiments and examples, it is not intended that the present teachings be limited to such embodiments. On the contrary, the present teachings encompass various alternatives and equivalents, as will be appreciated by those of skill in the art.

[0034] With reference to FIG. 1, the present disclosure relates to a piezoelectric transducer circuit 1 comprising a voltage converter circuit 2, a voltage subtraction cell 3, an input voltage source 6, and an output stage 4, e.g. for a piezoelectric transducer 5.

[0035] The voltage converter circuit 2 may be coupled to the input voltage source 6, such as a battery, typically with an input voltage Vinof between 2 V and 20 V, preferably 3.6V to 5V, whereby the voltage converter circuit 2 is configured to convert the input voltage Vinto a higher peak, e.g. 5x or more, preferably 5x to 30x or 25V-120V, AC driver voltage Vtopto be transmitted to the piezoelectric transducer 5 at the output stage 4. The voltage converter circuit 2 may comprise a plurality of switches, e.g. power converting transistors, and other electrical components, such as inductors and capacitors for amplifying the input voltage Vin to the desired driver voltage Vtop.

[0036] The voltage converter circuit 2 may comprise any suitable power converter circuit, but in some embodiments comprises one of the power converter circuits disclosed in United States Patent No. 10,199,555, issued February 5, 2019, to Simon Chaput, which is incorporated herein by reference.

[0037] In some exemplary embodiments, the voltage converter circuit 2 comprises a forward- boost / reverse-buck converter that generates a clean sine waveform. In the illustrated non-limiting example, the voltage converter circuit 2 may include an inductor Li connected to the voltage source Vin, and driver stage switches comprising or ideally consisting of a first low side switch, e.g. transistor, Mi connected between the inductor Li and ground, and a second driver switch, e.g. transistor, M2 connected between the inductor Li and the output stage 4, i.e. the piezoelectric transducer 5. The control terminal, e.g. gate, of the transistor in the first switch Mi may be connected to a controller 11, and the control terminal, e.g. gate, of the transistor in the second switch M2 may be connected to the controller 11. The controller 11 is configured to send control signals to the first and second switches Mi and M2 to control operation of the first and second switches Mi and M2. The control terminal, e.g. gate, of the transistor in the first switch Mi may be connected to a first gate driver 12, and the control terminal, e.g. gate, of the transistor in the second switch M2 may be connected to a second gate driver 13. Both the first gate driver 12 and the second gate driver 13 may be connected to the controller 11, which sends control signals to the first and second gate drivers 12 and 13 to control operation of the first and second switches Mi and M2, respectively. The controller 11 can be any suitable computer hardware executing computer software stored on non-transitory memory.

[0038] While the aforementioned embodiment is described being used for sine waveforms, persons having ordinary skill in the art will appreciate the embodiments described herein may operate upon arbitrary and complex analogue waveforms, for example, square, triangular, AM modulated, FM modulated, and are not limited to operating upon sine waveforms.

[0039] The second switch M2 may be an N-type transistor including a first conducting terminal, e.g. source, connected to the switching node SW and referenced to the switching node voltage Vswi, a second conducting terminal, e.g. drain, connected to the output stage 4, and a third control terminal, e.g. gate, connected to the controller 11. In some alternative embodiments, a different type of switch, e.g. a P-type transistor, may be used.

[0040] The first and second switches Mi and M2 may be of the same type, which may be the most practical choice for an integrated circuit (IC) implementation, although embodiments with mixed switches may be used. The first and second switches Mi and M2 may comprise, for example, GaN, PMOS, among other possible switches.

[0041] The inductor Li, may have an inductance between 10 nH and 10 pH, preferably between 100 nH and 1 pH. The inductor Li value may be selected in order to: (1) achieve a target distortion, e.g. lower inductance increases switching frequency and decreases distortion / THD+N, and / or (2) minimize the switching frequency, e.g. in general, a lower switching frequency corresponds to lower power consumption.

[0042] In the piezoelectric transducer circuit 1 illustrated in Figure 1, the conversion ratio, e.g. voltage amplification, of the voltage conversion circuit 2 may be greater than 5x, and preferably between 5x and 30x for a 25 to 120 VAC drive voltage VDR from a, e.g. 2.5-6 VDC input voltage Vin.

[0043] Initially, the controller 11 turns the first switch Mi on and the current in the inductor Li, which is connected to reference node 8, e.g. ground, ramps up linearly. The output stage 4 may be referenced to the input voltage Vin instead of GND. When the controller 11 turns the first switch Mi off, the voltage Vswi at the switching node 9 increases until it reaches an output driver voltage Vtop. Here, a body diode of the second switch M2 may turn on or the second switch M2 may turn on connecting the switching node 9 to the piezoelectric transducer 5. Current then flows from theinductor Li through the second switch M2 to increment the output driver voltage Vtopby charging the piezoelectric transducer 5. When the inductor Li current reaches 0, the second switch M2 is subsequently turned off by the controller 11 and the switching node voltage Vswigoes back to 0 V. The controller 11 alternates the states of the first switch Mi and the second switch M2 to control the amount of energy sent or extracted from the piezoelectric transducer 5. In the voltage converter circuit 2, since the boost converter voltage gain is most of the time larger than 2x, the switching node voltage Vswi, due to LC resonance, may decrease to a little bit less than 0 V and turn on the body diode of the first switch Mi. Thereupon, the first switch Mi is turned on again under zero voltage switching condition (ZVS), thus reducing the switching losses associated to the parasitic capacitance at the switching node 9.

[0044] When the second switch M2 turns off, the first switch Mi turns on in ZVS condition. Then the first switch Mi stays on until the inductor Li accumulates enough energy to charge the switch node voltage Vswi to the drive voltage Vtop. When the first switch Mi turns off, the switch node voltage Vswi rings to the drive voltage Vtopand the second switch M2 is turned on under ZVS condition thus reducing switching losses.

[0045] The VS cell 3 comprises two additional switches, e.g. transistors, i.e. a third switch M3 and a fourth switch M4 along with one capacitor Ci. In some embodiments, the third switch M3 is positioned in parallel to the fourth switch M4, with the capacitor Ci in series with the third switch M3 or the fourth switch M4, whereby turning the switch M3 or M4 in series with the capacitor Ci on and the switch M3 or M4 in parallel with the capacitor Ci off activates the capacitor Ci, and turning the switch M3 or M4 in series with the capacitor Ci off and the switch M3 or M4 in parallel with the capacitor Ci on, bypasses the capacitor CL Alternatively, in some embodiments, the third switch M3, the fourth switch M4 and the capacitor Ci are all positioned in series, with the third switch M3 and the fourth switch M4 enabling the capacitor Ci to be bypassed, depending on the direction of the current and the configuration of the voltage conversion circuit 2.

[0046] When the VS cell 3 is applied to a bidirectional voltage converter, such as the voltage converter circuit 2, i.e. where current flows from the input voltage source 6 to the output stage 4, then back to the input voltage source 6 using the same electrical path, which uses a mostly capacitive output load, such as the piezoelectric transducer 5, a voltage on the VS cell’s capacitorCi remains substantially stable. Contrary to most switched capacitor-based topologies, the capacitor voltage Vci on the capacitor Ci does not substantially vary with the output (piezo) driver voltage Vtop nor the input voltage Vinand remains substantially constant throughout charge and discharge cycles, where each cycle constitutes a single attempt by the voltage conversion circuit 2 to modify the output driver voltage Vtop. Thus, the capacitor Ci does not contribute to the total output load. The VS cell 3 uses the bidirectional properties of the voltage converter circuit 2 to maintain a high voltage on the capacitor Ci. As such, this single capacitor Ci, acting as an intermediate energy source, can have a major impact on overall converter performances.

[0047] The controller 11 or a separate controller (not shown) is electrically connected and configured to send control signals to the third and fourth switches M3 and M4 to control operation of the third and fourth switches M3 and M4. The control terminal, e.g. gate, of the transistor in the third switch M3 may be connected to a third gate driver 14, and the control terminal, e.g. gate, of the transistor in the fourth switch M4 may be connected to a fourth gate driver 15. Based on which switch, i.e. the third switch M3 or the fourth switch M4, is turned on by the controller 11, the capacitor Ci is either added in series to the voltage converter circuit 2 or completely bypassed, which is also uncommon amongst switched capacitor techniques.

[0048] Applying the VS cell 3 to the voltage converter circuit 2 may decrease the voltage amplitudes that must be generated by the inductor Li for a given output gain, which leads to reduced energy transfers to and from the inductor Li, and thus decreases the total amount of electrical charge carriers that need to be displaced each charge or discharge cycle via the first switch Mi, and thereby results in considerable efficiency gains. The output driver voltage Vtoprepresents the voltage sum (in reference to GND) of Vin+ VLI + Vci (where Vci represents a null voltage whenever it is bypassed) seen by the “top” connection of the piezoelectric transducer 5, i.e. Vtop equals the voltage seen by the piezoelectric transducer 5 + any offset to which the “lower” connection of the piezoelectric transducer 5 may be referenced (Vin / GND). The VS cell 3 also reduces the maximum stress applied to most semiconductor components, which enables the use of more efficient yet compact transistors, i.e. the first, second, third and / or fourth switch Mi to M4, further contributing to efficiency gains.

[0049] In some embodiments, the capacitance of the capacitor Ci is at least an order of magnitude, e.g. lOx, bigger than that of the piezoelectric transducer 5, which prevents excessive voltage swings on the capacitor Ci during exchanges of electrical charge carriers with the piezoelectric transducer 5. The efficiency gains allowed by the VS cell 3 will be diminished if the capacitor voltage Vci varies significantly while charging or discharging the piezoelectric transducer 5.

[0050] While the VS cell 3 may be applied to a variety of topologies, the analysis below mostly refers to the application to the voltage converter circuit 2, i.e. including the first switch Mi, the second switch M2 and the inductor Li. The main principles regarding the use of the VS cell 3 should remain the same with other voltage converter topologies.

[0051] Adding the VS cell 3 to a given voltage converter circuit only minimally impacts standard operation. For instance, when applied to the voltage converter circuit 2, the two transistors usually present, i.e. the first switch Mi and the second switch M2, may operate using roughly the same logic, although the required duty cycles will change for a given output voltage gain. Techniques such as zero current or zero voltage switching can still be used, and the VS cell 3 does not affect the required switching sequence for the first switch Mi or the second switch M2.

[0052] In some embodiments, the VS cell 3 has two modes of operation. A first, low-voltage mode, in which the third switch M3 is turned on by the controller 11, and the fourth switch M4 is turned off by the controller 11, which bypasses the capacitor Ci and enables the selected voltage converter circuit 2, e.g. boost in the case of FIG. 1, to operate as if the VS cell 3 was not present. The operating principles of the piezoelectric transducer circuit 1 are then identical to the voltage converter circuit 2, but with the slight inconvenience that the third switch M3 adds to the total resistance of the output current path.

[0053] In a second, high-voltage mode, the third switch M3 is turned off by the controller 11, the fourth switch M4 is turned on by the controller 11, whereby the capacitor Ci is added in series with the inductor Li during transfers with the output stage 4, e.g. the piezoelectric transducer 5. This considerably reduces the voltage which the inductor Li must generate for electric charges to be transferred towards the output stage 4 during charge cycles. Similarly, the second, high-voltage mode also reduces the voltage applied on the inductor Li during discharge cycles. In both cases, the voltage reduction is equal to the capacitor voltage Vci. The maximum stress on the standardactive components, e.g. the first switch Mi and the second switch M2 in the case of the Boost voltage converter circuit 2, is also reduced by the voltage capacitor Vci. The multiple implications are described hereinafter.

[0054] Once the first, low-voltage mode or the second, high-voltage mode of the VS cell 3 is selected by the controller 11, the selected mode can be kept for multiple charge or discharge cycles of the voltage converter circuit 2. The appropriate mode depends mostly on the driver voltage Vtop(see fig. 1), for reasons explained hereinafter. As such, the third switch M3 and the fourth switch M4 may keep their state, i.e. on or off, for multiple charge / discharge cycles, and thus usually switch at much lower frequencies than either the first switch Mi or the second switch M2. The switching of the third switch M3 and the fourth switch M4 happens preferably around the same time as the second switch M2, which helps to prevent the start of a resonance cycle, see below, at an inappropriate moment. The third switch M3 and the fourth switch M4 should never be turned on simultaneously, as the terminals of the capacitor Ci would be shorted together.

[0055] Since charge carriers on the capacitor Ci are only displaced in series with the output stage 4 while in the second, high-voltage mode, the capacitor voltage Vci can be increased by ending the second, high-voltage mode at a lower driver voltage Vtopthan the one at which it was initiated, i.e. the percentage of the total load discharge happening in the second, high-voltage mode is thus higher than the percentage of total load charge, and thus the capacitor Ci is further polarized. Conversely, ending a second, high-voltage mode at a higher control voltage Vtopthan the one at which it was initiated will lower the capacitor voltage Vci. Although the capacitor voltage Vci can usually be maintained at any voltage between 0 V and more than half the peak output amplitude, e.g. 12 to 60 VAC, an optimal voltage for efficiency and stress reduction, when using a single voltage subtraction cell 3, will usually remain around half the target peak amplitude, e.g. 12 to 60 VAC, on the output stage 4, e.g. the piezoelectric transducer 5. This may vary slightly depending on the exact topology used.

[0056] In general, using the second, high-voltage mode as much as possible results in a more efficient operation and limits the voltage stress applied to the components of the voltage converter circuit 2, e.g. the inductor Li, the first switch Mi and the second switch M2. However, using the second, high-voltage mode when the driver voltage Vtopminus the capacitor voltage Vci is lessthan 0 V, i.e. the capacitor voltage Vci is greater than the driver voltage Vtop, may result in forward biasing the body diode of the first switch Mi and result in a current rush from the capacitor Ci towards the output stage 4. Initiating the second, high-voltage mode when the driver voltage Vtop minus the capacitor voltage Vci is greater or equal to 0 V yet less than the input voltage Vinmay be used, if desired, to force an LC resonance between the inductor Li and the output (capacitive) stage 4. In this scenario, current coming from the inductor Li and through the capacitor Ci will charge the output stage 4 while enabling the inductor Li to accumulate energy until the driver voltage Vtop minus the capacitor voltage Vci equals the input voltage Vin. The equilibrium of the inductor Li occurs when the switching node voltage Vswiequals the input voltage Vin. Neglecting non-idealities, the inductor Li will then discharge its energy towards the output stage 4, allowing the driver voltage Vtopminus the capacitor voltage Vci (which put together correspond to the switching node voltage Vswi) to reach a maximum value of 2 times the input voltage Vin. The exact voltage Vswi reached by the switching node 9 depends on the initial voltage delta between the control voltage Vtopand the capacitor voltage Vci. This represents the most efficient way to use the VS cell 3, as it minimizes the use of the first switch Mi and the overall average currents. In many cases, using the second, high-voltage mode only when the driver voltage Vtopminus the capacitor voltage Vci is greater than or equal to the input voltage Vin, which eliminates the use of resonance cycles, may be preferable in order to minimize output distortion. By symmetry, the same logic applies for discharge cycles, where resonance can be used to discharge at most the output stage 4 so that the driver voltage Vtopminus the capacitor voltage Vci goes from two times the input voltage Vin down to 0 V or more before switching back to the first, low-voltage mode.

[0057] When the output stage 4 is referenced to GND or any other voltage lower than the input voltage Vin, a resonance strategy similar to the one described above can be used to allow the complete discharge of the piezoelectric transducer 5, i.e. when the driver voltage Vtopnears (or is substantially) the reference voltage of the output stage’s 4. Without this strategy, the voltage converter circuit 2 may limit the driver voltage Vtopto a minimal voltage equivalent to the input voltage Vin. As above, the fourth switch M4 is responsible for preventing any unwanted resonance cycle when the driver voltage Vtopminus the capacitor voltage Vci is less than the input voltage Vin. When using a resonance cycle to fully discharge the piezoelectric transducer 5, a low voltage switch MR (shown in FIG. 1, but can be provided in any of the embodiments), e.g. NMOS, placed between the “lower” connection of the piezoelectric transducer 5 and the reference voltage of theoutput stage’s 4 can achieve the same purpose, e.g. prevent unwanted resonance cycles. In this context, all charges going to or coming from the piezoelectric transducer 5 must pass through the low voltage switch MR. Hence, once the piezoelectric transducer 5 is fully discharged, the controller 11 is configured to turn the low voltage switch MR off to prevent the immediate return of a large amount of charge carriers towards the piezoelectric transducer 5. The charge carriers are thus accumulated on the low voltage switch MR’ S drain capacitance. The driver voltage Vtopwill then return to a voltage, e.g. Vin, which allows an equilibrium on the inductor Li, without the piezoelectric transducer 5 being significantly charged. The next resonance cycle, this time in order to charge the piezoelectric transducer 5, will be initiated once the low voltage switch MR is turned on again by the controller 11. This low voltage switch MR may be left turned on except when needed to prevent or delay a resonance cycle. If a Full-Bridge is used at the output stage 4 to allow bipolar voltages on the piezoelectric transducer 5, the Full-Bridge can by itself prevent or delay a resonance cycle, eliminating the need for a low voltage switch MR.

[0058] In the first, low-voltage mode, the voltage converter circuit 2 can mostly ignore the presence of the VS cell 3. However, the presence of an additional transistor, e.g. the third switch M3, in the current path towards the output stage 4 may lead to slightly worse performance, while in the first, low-voltage mode than if the VS cell 3 wasn’t present.

[0059] In the second, high-voltage mode, the voltage which the inductor Li generates (charge cycles) or perceives (discharge cycles) during the transfer of charge carriers with the output stage 4 is reduced by the capacitor voltage Vci. Since for a given transfer of charge carriers the energy withdrawn from or accumulated on the inductor Li is proportional to its generated / perceived voltage, the VS cell 3 greatly reduces the overall amount of energy that is transferred between the inductor Li and the output stage 4. This in turn reduces the amount of energy that must come from (and be recycled to) the input voltage source 6. Since the purpose of the first switch Mi is to transfer energy between the input voltage source 6 and the inductor Li, the current through the first switch Mi is considerably reduced, resulting into lower conduction losses for the first switch Mi as well as the inductor Li.

[0060] Similarly, the rate of change of current of the inductor Li is also proportional to the voltage generated / perceived by the inductor L 1. As such, in the second, high-voltage mode, a given transferof charge carriers with the piezoelectric transducer 5 will last longer but require lower peak currents. On average, this reduces the RMS current perceived along the current path to the output stage 4, once again contributing to lower conduction losses. This also limits the need to turn on transistors, such as the second switch M2, for very short amounts of time, which may simplify the design and / or the requirements of the second switch M2’s gate driver.

[0061] The second, high-voltage mode reduces the perceived voltage stress on the semiconductor components in the voltage converter circuit 2. In the Boost case, the maximum perceived stress on the first switch Mi and the second switch M2 will be reduced by the capacitor voltage Vci. This enables the use of transistors, e.g. MOSFETs, for the first switch Mi and / or the second switch M2 rated for lower breakdown voltages, which in turn greatly improves their resistivity. Combined with the RMS and peak current reductions, the first switch Mi and / or the second switch M2 can have a much smaller area, and thus be more affordable, without presenting higher conduction losses. This compensates for the addition of the transistors in the VS cell 3, which typically require breakdown voltages above the maximum value anticipated for the capacitor voltage Vci.

[0062] Transistor switching losses are highly dependent on peak voltages and peak currents within the voltage converter circuit 2. Since the second, high-voltage mode helps reduce both the peak voltages and the peak currents, switching losses are greatly reduced. The third switch M3 and the fourth switch M4 may switch while perceiving no current and since their switching frequencies are much lower than those of the first switch Mi and the second switch M2, they contribute minimally to overall switching losses.

[0063] Magnetic losses originating from the inductor Li mostly depend on the magnetic flux’s density and rate of change. Since the second, high-voltage mode helps to reduce both the peak currents and the current’s maximum rate of change, the VS cell 3 reduces overall magnetic losses. This may also help reduce electromagnetic interference (EMI).

[0064] As a reference point, experimental tests indicate that over a variety of operating conditions (focusing on virtual texture generation), the addition of a VS cell 3 to a Boost voltage converter circuit 2 improved efficiency by about 25 % while also reducing by around 25 % the total semiconductor area used. The performance gap is further increased by solely using high voltage gains at the output stage 4.

[0065] While capacitors are commonly used within voltage converters to reduce component stress, their charge level is most often a function of the input or output voltage. For most topologies, when the capacitor’s voltage remains low, multiple stages are required to make a significant difference, increasing their complexity. When the capacitor’s voltage is high, it most often is because it is kept at a fraction, i.e. half, of the output voltage. For applications where the output must constantly be charged and discharged, the added capacitor then contributes significantly to the total amount of charges that need to be displaced, minimizing its potential benefits to the topology’s efficiency by incrementing conduction losses.

[0066] The VS cell 3 is specifically developed for voltage converter circuits utilizing a bidirectional displacement of charge carriers between their input and output. While remaining simple to implement, it allows for a high capacitor voltage between the input of the voltage converter circuit and the output which significantly reduces component stress and required energy transfers from the inductor Li.

[0067] While the above analysis focuses on the application of the VS cell 3 to a standard voltage converter, e.g. voltage converter circuit 2, the VS cell 3 may be used with a variety of voltage boosting topologies. This would likely include most direct derivatives of the Boost voltage converter circuit. The VS cell 3 might in some instances be able to improve the performances of converters which do not use magnetic components, such as switched capacitor voltage converters. For such instances, the analysis presented above would at least remain partly applicable. If required, multiple VS cells 3 may be used in series or parallel.

[0068] The optimal way to implement the VS cell 3 will vary by topology. Examples given below refer mostly to their use with a basic voltage converter circuit, e.g. the voltage converter circuit 2. The VS cell 3 can usually be applied in a similar way to derivatives of the basic Boost voltage converter circuit.

[0069] FIG. 1 illustrates the base configuration (config. A) of the transducer circuit 1, while FIGS. 2-5 illustrate other possible variations (configs. B-E). An advantage of the first configuration (config. A) is the shared node between the source S2 of the second switch M2 and the source S4 of the fourth switch M4. In the first configuration of the transducer circuit 1, the second switch M2 and the fourth switch M4 still need independent gate drivers 13 and 15, but may share a single firstbootstrapped capacitor CBI for the two gate drivers 13 and 15. The first bootstrapped capacitor CBI may be charged by the input voltage Vinvia a diode 16 when a second switching node voltage Vsw2 reaches 0 V, i.e. when the first switch Mi and the third switch M3 are on. Then the voltage VCBI from the bootstrapped capacitor CBI is used to drive both the second switch M2 and the fourth switch M4 via two independent gate drivers. If using discrete bootstrapped capacitors, this helps limit the bill of materials (BOM). Config. A’s main disadvantage is that the second switch M2 may switch multiple times while in the second, high-voltage mode, during which its bootstrap capacitor CBI cannot be charged. This implies that the shared first bootstrap capacitor CBI needs a high capacitance to supply the charge carriers required to switch the second switch M2 multiple times without a significant voltage drop.

[0070] A piezoelectric transducer circuit 21 (FIG. 2), with like elements having the same reference numbers as in FIG. 1, solves this problem by having the source S2 of the second switch M2 directly connected to the drain Di of the first switch Mi. Each transistor then has a unique reference node for its gate driver’s bootstrap capacitor. The reference node of each transistor is the electrical node connected to the transistor’s, e.g. MOSFET’s, source pin. Accordingly, for the piezoelectric transducer circuit 21 (Fig. 2): the reference node for the first switch Mi is GND 8, i.e. the reference node of the first switch Mi is thus constant; the reference node for the second switch M2 is S2; the reference node for the third switch M3 is D2; and the reference node for the fourth switch M4is the node Vtop. In contrast, for the piezoelectric transducer circuit 1 in Fig.1, the second switch M2 and the fourth switch M4 share the second switch node Vsw2 as their reference node as their source pins are directly connected. With slight adjustments to the controller logic, each bootstrap capacitor may now be charged in between each of its associated transistor’s turn-ons. This allows the use of smaller capacitances, which are easier to integrate into a system-on-chip or system-in- package controller. In this configuration, the bootstrapped capacitors of the third switch M3 and the fourth switch M4 are charged when the piezoelectric transducer 5 is fully discharged, i.e. when the driver voltage Vtopnears (or is substantially) 0 V. If the output stage 4 is referenced to the input voltage Vin instead of GND, charge pumps may be used within the gate drivers of the third switch M3 and the fourth switch M4 to ensure appropriate gate control voltages.

[0071] Two other possible configurations, a piezoelectric transducer circuit 31 and piezoelectric transducer circuit 41, are shown respectively in Figs. 3 and 4. The distinctions betweenpiezoelectric transducer circuit 31 and piezoelectric transducer circuit 41 are similar to those existing between piezoelectric transducer circuit 1 and piezoelectric transducer circuit 21. For piezoelectric transducer circuit 31 and piezoelectric transducer circuit 41, the second switch M2 may not benefit from the voltage stress reductions seen with piezoelectric transducer circuit 1 and piezoelectric transducer circuit 21.

[0072] For piezoelectric transducer circuit 31 and piezoelectric transducer circuit 41, (FIGS. 3 and 4), the third switch M3, the fourth switch M4 and the capacitor Ci are in series. The second switch M2 is only turned on by the controller 11 during the first, low-voltage mode, using the same logic that the standard voltage converter circuit 2 would require, i.e. the third switch M3 and / or the fourth switch M4 are turned off bypassing the capacitor Ci, whereby the first low voltage mode behaves like the basic voltage converter circuit 2, ignoring the presence of the VS cell 33 / 43 in parallel with the second switch M2. While in the second, high-voltage mode, the second switch M2 is always turned off by the controller 11, and the third switch M3 is used by the controller 11 in a similar way that the second switch M2 is used during the first, low-voltage mode. The fourth switch M4 may remain turned on for the duration of the second, high-voltage mode as with other configurations.

[0073] For piezoelectric transducer circuit 31 (FIG. 3), a VS cell 33 comprising the capacitor Ci is disposed between the third switch M3 and the fourth switch M4, which are all in parallel with the second switch M2.

[0074] For piezoelectric transducer circuit 41 (FIG. 4), a VS cell 43, comprising the capacitor Ci, is disposed between the switch node 9 and the fourth switch M4 in series with the third switch M3. As above, the capacitor Ci, the third switch M3 and the fourth switch M4 are in parallel with the second switch M2. The third switch M3, while the second switch M2 is turned on and the fourth switch M4 is turned off by the controller 11, may be left turned on during at least part of the first, low-voltage mode to help the bootstrap capacitors of the third switch M3 and the fourth switch M4 reach their optimal voltages. While in the second, high-voltage mode, the second switch M2 is never turned on, and it is then that the third switch M3 switches using a similar logic to the second switch M2 in the first, low-voltage mode, i.e. is switched on by the controller 11 while the inductor Li (and the capacitor Ci) transfers charges to the output node stage 4, and is switched off while thefirst switch Mi is turned on. As mentioned above, the fourth switch M4 remains turned on for the duration of the second, high-voltage mode as with all configurations. The main advantage of the C and D configurations is that in the first, low-voltage mode the current going to the output stage 4 flows through a single transistor, i.e. the second switch M2, instead of two, i.e. the second switch M2 and the third switch M3, which helps to reduce the total resistance of this current path.

[0075] Some embodiments may include a plurality of VS cells 3, 33 and / or 43, i.e. any of the aforementioned piezoelectric transducer circuits 1, 21, 31 or 41, within a given circuit topology, increasing the design’s complexity, but further reducing RMS currents and voltage stress on components. Figure 5 illustrates an example of a piezoelectric transducer circuit 51 using two VS cells 3 in series, thus comprising a fifth switch M3 and a sixth switch M4 with a second capacitor Ci.

[0076] Based on the piezoelectric transducer circuits 31 and 41, something similar to FIG. 5 can be achieved by implementing multiple VS cells 33 and / or 43 in parallel. However, each VS cell 33 or 43 would require a capacitor charged at a different voltage, and some transistors in the third switch M3 and / or the fourth switch M4 would be exposed to voltage stresses higher than in the cases of piezoelectric transducer circuits 1 and 21. The main advantage would remain a minimal number of components in series for the current path to the output stage 4.

[0077] The VS cell 3, 33 or 43 does not prevent the implementation of a Full-Bridge at the output of the voltage converter circuit 2, similar to what is done for the voltage converters illustrated in US Patent No. 10,199,555 B2 .

[0078] The foregoing description of one or more example embodiments has been presented for the purposes of illustration and description. It is not intended to be exhaustive or to limit the invention to the precise form disclosed. Many modifications and variations are possible in light of the above teaching. It is intended that the scope of the disclosure be limited not by this detailed description.

Claims

WE CLAIM:

1. An apparatus for operating a piezoelectric transducer, configured for coupling to an input voltage source, which provides an input voltage, and configured to transmit a drive voltage across the piezoelectric transducer, the apparatus comprising: a voltage converter circuit configured to convert the input voltage to a higher peak, AC driver voltage; a first voltage subtraction cell comprising a first capacitor and a first plurality of switches, including a first switch and a second switch; and a controller configured to add the capacitor in series to the voltage converter circuit or bypass the capacitor based on which of the first plurality of switches is turned on.

2. The apparatus according to claim 1, wherein the voltage converter circuit comprises a forward-boost / reverse-buck converter configured to enable current flows from the input voltage source to the piezoelectric transducer, then back to the input voltage source using a same electrical path, whereby a voltage on the capacitor remains substantially stable.

3. The apparatus according to claim 1, wherein the capacitor has a first capacitance at least lOx larger than a second capacitance of the piezoelectric transducer to prevent excessive voltage swings on the capacitor.

4. The apparatus according to claim 1, wherein the first switch is configured in parallel to the second switch, and the first capacitor configured in series with the second switch.

5. The apparatus according to claim 1, wherein the first switch is configured in series with the second switch and the first capacitor.

6. The apparatus according to claim 5, wherein the first capacitor is positioned between the first switch and the second switch.

7. The apparatus according to claim 5, wherein the first capacitor is positioned between the voltage converter circuit and the first and second switches.

8. The apparatus according to claim 2, wherein the voltage converter circuit comprises an inductor and a second plurality of switches, including a third switch and a fourth switch.

9. The apparatus according to claim 8, wherein the first voltage subtraction cell is positioned between the third switch and the fourth switch.

10. The apparatus according to claim 9, wherein a shared node is provided between a source of the second switch and a source of the fourth switch; and further comprising a single first bootstrapped capacitor for gate drivers of the second switch and the fourth switch.

11. The apparatus according to claim 8, wherein the first voltage subtraction cell is positioned between the fourth switch and the piezoelectric transducer.

12. The apparatus according to claim 8, wherein the first voltage subtraction cell is positioned in parallel to the fourth switch.

13. The apparatus according to claim 8, wherein the voltage converter circuit comprises: the inductor connected to the voltage source; the third switch connected between the inductor and a ground, and the fourth switch connected between the inductor and the piezoelectric transducer;wherein the controller is configured to turn the third switch on, whereby current in the inductor increases a driver voltage to a desired output voltage; and then to subsequently turn the third switch off enabling current to flow from the inductor through the fourth switch to the piezoelectric transducer.

14. The apparatus according to claim 13, wherein the voltage converter circuit is configured to amplify the input voltage by greater than 5x.

15. The apparatus according to claim 1, further comprising a second voltage subtraction cell comprising a second capacitor and a third plurality of switches, including a fifth switch and a sixth switch.

16. The apparatus according to claim 15, wherein the second voltage subtraction cell is in series with the first voltage subtraction cell.

17. The apparatus according to claim 15, wherein the second voltage subtraction cell is in parallel with the first voltage subtraction cell.

18. The apparatus according to claim 1, further comprising a low voltage switch between the piezoelectric transducer and a reference voltage thereof configured to prevent unwanted resonance cycles.