Display substrate and display device

Abstract

Provided is a display substrate, comprising: a base substrate; a first conductive layer, comprising a plurality of first power signal lines, wherein the plurality of first power signal lines are arranged in a first direction and extend in a second direction, and the first direction intersects with the second direction; a first electrode layer, comprising a plurality of first electrode portions; and a pixel define layer, located on the side of the first electrode layer away from the base substrate and provided with a plurality of openings, wherein one opening exposes part of one first electrode portion. The plurality of first power signal lines comprise a plurality of first power signal line groups arranged in the first direction, one first power signal line group comprises two adjacent first power signal lines, and in each first power signal line group, the two first power signal lines are spaced in the first direction and the signal transmitted by one of the first power signal lines is different from the signal transmitted by the other of the first power signal lines; and the minimum distance between the two first power signal lines in the first direction is smaller than the size of the opening in the first direction.

Description

Display substrate and display device Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to a display substrate and a display device. Background Art

[0002] With the continuous advancement of display technology, organic light-emitting diode (OLED) displays have become a research hotspot and a key area of ​​technological development for major manufacturers due to their advantages, including wide color gamut, high contrast, thin and lightweight design, self-luminescence, and wide viewing angle. Further reducing the power consumption of OLED displays is a key concern for display product developers.

[0003] The above information disclosed in this section is only for understanding the background of the inventive concept of the present disclosure and therefore the above information may contain information that does not constitute prior art.

[0004] Summary of the Invention

[0005] In one aspect, a display substrate is provided, comprising:

[0006] substrate;

[0007] a first conductive layer located on the base substrate, the first conductive layer comprising a plurality of first power signal lines arranged along a first direction and extending along a second direction, the first direction intersecting the second direction;

[0008] a first electrode layer, located on a side of the first conductive layer away from the base substrate, the first electrode layer comprising a plurality of first electrode portions; and

[0009] a pixel defining layer, located on a side of the first electrode layer away from the base substrate, and having a plurality of openings, wherein each opening exposes a portion of the first electrode portion;

[0010] The plurality of first power signal lines include a plurality of first power signal line groups arranged along the first direction, one first power signal line group includes two adjacent first power signal lines, in each first power signal line group, the two first power signal lines are spaced apart along the first direction, and a signal transmitted by one first power signal line is different from a signal transmitted by another first power signal line; and

[0011] A minimum distance between two first power signal lines along the first direction is smaller than a size of the opening along the first direction.

[0012] According to some exemplary embodiments, the first power signal line group includes two main power lines and a plurality of first signal blocks located between the two main power lines, wherein the plurality of first signal blocks are arranged at intervals along the second direction;

[0013] Among them, any one of the first signal blocks is directly connected to one of the main power lines and is spaced apart from another of the main power lines along the first direction, and the distance between the first signal block and the spaced main power lines along the first direction is smaller than the size of the opening along the first direction.

[0014] According to some exemplary embodiments, in the first power signal line group, each of the first signal blocks is directly connected to the same main power line.

[0015] According to some exemplary embodiments, in the first power signal line group, a portion of the first signal blocks are directly connected to one of the main power lines, and the remaining portion of the first signal blocks are directly connected to another of the main power lines.

[0016] According to some exemplary embodiments, the plurality of first power signal lines include a plurality of first sub-power lines, a plurality of second sub-power lines, and a plurality of third sub-power lines, the first sub-power lines being used to transmit a first signal, the second sub-power lines being used to transmit a second signal, and the third sub-power lines being used to transmit a third signal, and any two of the first signal, the second signal, and the third signal being different from each other; and

[0017] The multiple first electrode parts include multiple first sub-electrode parts, multiple second sub-electrode parts and multiple third sub-electrode parts, the first sub-electrode part is electrically connected to the first sub-power line, the second sub-electrode part is electrically connected to the second sub-power line, and the third sub-electrode part is electrically connected to the third sub-power line.

[0018] According to some exemplary embodiments, the plurality of first power signal lines include a plurality of first power signal units arranged along the first direction;

[0019] The first power signal unit includes a first sub-power line, two second sub-power lines and a third sub-power line, the first sub-power line is located on one side of the two second sub-power lines along the first direction, and the third sub-power line is located between the two second sub-power lines.

[0020] According to some exemplary embodiments, in the first power signal unit, the first sub-power line and the adjacent second sub-power line include a first main power line, a second main power line, and a plurality of first signal blocks located between the first main power line and the second main power line, a portion of the first signal blocks are directly connected to the first main power line, and a remaining portion of the first signal blocks are directly connected to the second main power line, and the plurality of first signal blocks connected to the first main power line and the plurality of first signal blocks connected to the second main power line are alternately arranged along the second direction;

[0021] In the first power signal unit, the third sub-power line and the adjacent second sub-power line have a third main power line, a second main power line, and a plurality of first signal blocks located between the third main power line and the second main power line, a portion of the first signal blocks are directly connected to the third main power line, and the remaining portion of the first signal blocks are directly connected to the second main power line, and the plurality of first signal blocks connected to the third main power line and the plurality of first signal blocks connected to the second main power line are alternately arranged along the second direction.

[0022] According to some exemplary embodiments, in the first power signal unit, the first sub-power line and the adjacent second sub-power line have a first main power line, a second main power line, and a plurality of first signal blocks located between the first main power line and the second main power line, and each of the first signal blocks is directly connected to the first main power line; and

[0023] In the first power signal unit, the third sub-power line and the adjacent second sub-power line have a third main power line, a second main power line and a plurality of first signal blocks located between the third main power line and the second main power line, and each first signal block is directly connected to the third main power line.

[0024] According to some exemplary embodiments, the display substrate further includes a second conductive layer located on a side of the first conductive layer close to the base substrate, the second conductive layer including a plurality of first auxiliary signal lines, the plurality of first auxiliary signal lines being arranged along the second direction and extending along the first direction;

[0025] Among them, the multiple first auxiliary signal lines include multiple first sub-auxiliary lines, multiple second sub-auxiliary lines and multiple third sub-auxiliary lines, the first sub-auxiliary lines are electrically connected to the multiple first sub-power lines, the second sub-auxiliary lines are electrically connected to the multiple second sub-power lines, and the third sub-auxiliary lines are electrically connected to the multiple third sub-power lines.

[0026] According to some exemplary embodiments, the second conductive layer further includes a plurality of second signal blocks, where one second signal block and one first signal block form a signal block unit;

[0027] In the signal block unit, the orthographic projection of the second signal block on the base substrate at least partially overlaps with the orthographic projection of the first signal block on the base substrate, and the second signal block and the first signal block are electrically connected to the same main power line.

[0028] According to some exemplary embodiments, the display substrate further includes a first active layer located on a side of the second conductive layer close to the display substrate, and a material of the first active layer includes a metal oxide semiconductor material;

[0029] wherein the orthographic projection of the first active layer on the base substrate at least partially overlaps with the orthographic projection of the first signal block on the base substrate; and / or

[0030] An orthographic projection of the first active layer on the base substrate at least partially overlaps with an orthographic projection of the second signal block on the base substrate.

[0031] According to some exemplary embodiments, the orthographic projection of the second signal block on the substrate covers the orthographic projection of the first signal block on the substrate.

[0032] According to some exemplary embodiments, the plurality of first auxiliary signal lines include a plurality of first auxiliary signal units arranged along the second direction;

[0033] The first auxiliary signal unit includes a first sub-auxiliary line, two second sub-auxiliary lines and a third sub-auxiliary line. The first sub-auxiliary line is located on one side of the two second sub-auxiliary lines along the second direction, and the third sub-auxiliary line is located between the two second sub-auxiliary lines.

[0034] According to some exemplary embodiments, the plurality of second signal blocks include a plurality of second signal block groups arranged along the second direction, the second signal block groups include a plurality of second signal blocks arranged along the first direction, and one second signal block group is adjacent to one first auxiliary signal line along the second direction;

[0035] In a group of the first auxiliary sub-line and the adjacent second signal blocks, a portion of the second signal blocks is electrically connected to the first auxiliary sub-line, and a remaining portion of the second signal blocks is spaced apart from the first auxiliary sub-line, and a plurality of the second signal blocks electrically connected to the first auxiliary sub-line and a plurality of the second signal blocks spaced apart from the first auxiliary sub-line are alternately arranged along the first direction;

[0036] In the second auxiliary sub-line and the adjacent second signal block group, each second signal block is electrically connected to the second auxiliary sub-line;

[0037] In the third sub-auxiliary line and the adjacent second signal block group, a portion of the second signal blocks is electrically connected to the third sub-auxiliary line, and the remaining portion of the second signal blocks is spaced apart from the third sub-auxiliary line, and a plurality of second signal blocks electrically connected to the third sub-auxiliary line and a plurality of second signal blocks spaced apart from the third sub-auxiliary line are alternately arranged along the first direction.

[0038] According to some exemplary embodiments, the plurality of second signal blocks include a plurality of second signal block groups arranged along the second direction, the second signal block groups include a plurality of second signal blocks arranged along the first direction, and the plurality of second signal block groups are respectively located on one side of the plurality of first auxiliary signal lines along the second direction;

[0039] In a group of the first auxiliary sub-line and the adjacent second signal blocks, a portion of the second signal blocks is electrically connected to the first auxiliary sub-line, and a remaining portion of the second signal blocks is spaced apart from the first auxiliary sub-line, and a plurality of the second signal blocks electrically connected to the first auxiliary sub-line and a plurality of the second signal blocks spaced apart from the first auxiliary sub-line are alternately arranged along the first direction;

[0040] In the second auxiliary sub-line and the adjacent second signal block group, each second signal block is spaced apart from the second auxiliary sub-line;

[0041] In the third sub-auxiliary line and the adjacent second signal block group, a portion of the second signal blocks is electrically connected to the third sub-auxiliary line, and the remaining portion of the second signal blocks is spaced apart from the third sub-auxiliary line, and a plurality of second signal blocks electrically connected to the third sub-auxiliary line and a plurality of second signal blocks spaced apart from the third sub-auxiliary line are alternately arranged along the first direction.

[0042] According to some exemplary embodiments, the display substrate further includes a driving circuit layer located on a side of the first electrode layer close to the base substrate, the driving circuit layer including a plurality of driving circuit columns, the plurality of driving circuit columns including a plurality of first driving circuit columns, a plurality of second driving circuit columns, and a plurality of third driving circuit columns;

[0043] The first driving circuit column includes a plurality of first pixel driving circuit units arranged along the second direction, the second driving circuit column includes a plurality of second pixel driving circuit units arranged along the second direction, and the third driving circuit column includes a plurality of third pixel driving circuit units arranged along the second direction;

[0044] The first sub power line is electrically connected to each of the first pixel driving circuit units in the first driving circuit column, the second sub power line is electrically connected to each of the second pixel driving circuit units in the second driving circuit column, and the third sub power line is electrically connected to each of the third pixel driving circuit units in the third driving circuit column; and

[0045] The first sub-electrode portion is electrically connected to the first sub-power line through the first pixel driving circuit unit, the second sub-electrode portion is electrically connected to the second sub-power line through the second pixel driving circuit unit, and the third sub-electrode portion is electrically connected to the third sub-power line through the third pixel driving circuit unit.

[0046] According to some exemplary embodiments, the display substrate further includes a plurality of data signal lines, wherein a layer where the plurality of data signal lines are located is located between the base substrate and the first electrode layer, the plurality of data signal lines are arranged along the first direction and extend along the second direction, and the plurality of data signal lines include a plurality of first data lines, a plurality of second data lines, and a plurality of third data lines;

[0047] The first data line is electrically connected to each of the first pixel driving circuit units in the first driving circuit column, the second data line is electrically connected to each of the second pixel driving circuit units in the second driving circuit column, and the third data line is electrically connected to each of the third pixel driving circuit units in the third driving circuit column; and

[0048] The first sub-electrode portion is electrically connected to the first data line through the first pixel driving circuit unit, the second sub-electrode portion is electrically connected to the second data line through the second pixel driving circuit unit, and the third sub-electrode portion is electrically connected to the third data line through the third pixel driving circuit unit.

[0049] According to some exemplary embodiments, the first sub-electrode portion includes a first sub-electrode main portion and a first connecting line, and the first sub-electrode main portion is electrically connected to the first pixel driving circuit unit through the first connecting line;

[0050] The second sub-electrode portion includes a second sub-electrode main portion and a second connecting line, and the second sub-electrode main portion is electrically connected to the second pixel driving circuit unit through the second connecting line; and

[0051] The third sub-electrode portion includes a third sub-electrode main portion and a third connecting line, and the third sub-electrode main portion is electrically connected to the third pixel driving circuit unit through the third connecting line;

[0052] Wherein, the extension lengths of any two of the first connecting lines are substantially equal; and / or

[0053] The extension lengths of any two of the second connecting lines are substantially equal; and / or

[0054] The extension lengths of any two of the third connecting lines are substantially equal.

[0055] According to some exemplary embodiments, the first electrode layer includes a plurality of first electrode groups arranged along a first direction, the first electrode groups include a first electrode column, two second electrode columns, and a third electrode column arranged along the first direction, the first electrode column is located on one side of the two second electrode columns along the first direction, and the third electrode column is located between the two second electrode columns;

[0056] The first electrode array includes a plurality of the first sub-electrode portions and a plurality of the third sub-electrode portions arranged alternately along the second direction, the second electrode array includes a plurality of the second sub-electrode portions arranged along the second direction, and the third electrode array includes a plurality of the third sub-electrode portions and a plurality of the first sub-electrode portions arranged alternately along the second direction;

[0057] The driving circuit layer includes a plurality of driving circuit groups arranged along the first direction, the driving circuit groups including one first driving circuit column, two second driving circuit columns, and one third driving circuit column arranged along the first direction, the first driving circuit column being located on one side of the two second driving circuit columns along the first direction, and the third driving circuit column being located between the two second driving circuit columns;

[0058] One first electrode group is electrically connected to one drive circuit group, and in the electrically connected first electrode group and drive circuit group, the orthographic projection of the first electrode column on the base substrate partially overlaps with the orthographic projection of the first drive circuit column on the base substrate, the orthographic projection of the second electrode column on the base substrate partially overlaps with the orthographic projection of the second drive circuit column on the base substrate, and the orthographic projection of the third electrode column on the base substrate partially overlaps with the orthographic projection of the third drive circuit column on the base substrate; and

[0059] The multiple first sub-electrode main bodies in the first electrode group are electrically connected to the multiple first pixel driving circuit units in the first driving circuit column through the multiple first connecting lines, the multiple second sub-electrode main bodies in the first electrode group are electrically connected to the multiple second pixel driving circuit units in the second driving circuit column through the multiple second connecting lines, and the multiple third sub-electrode main bodies in the first electrode group are electrically connected to the multiple third pixel driving circuit units in the third driving circuit column through the multiple third connecting lines.

[0060] According to some exemplary embodiments, in the electrically connected first electrode group and the driving circuit group:

[0061] In the first electrode column, one end of the first sub-electrode main portion along the second direction is electrically connected to the first pixel driving circuit unit in the first driving circuit column through the first connecting line, and one end of the third sub-electrode main portion close to the third electrode column is electrically connected to the third pixel driving circuit unit in the third driving circuit column through the third connecting line; and / or

[0062] In the third electrode column, one end of the first sub-electrode main body close to the first electrode column is electrically connected to the first pixel driving circuit unit in the first driving circuit column through the first connecting line, and one end of the third sub-electrode main body close to the first electrode column is electrically connected to the third pixel driving circuit unit in the third driving circuit column through the third connecting line.

[0063] According to some exemplary embodiments, an orthographic projection of the second sub-electrode portion on the base substrate at least partially overlaps with an orthographic projection of the first signal block on the base substrate.

[0064] According to some exemplary embodiments, the plurality of openings include a plurality of first openings, a plurality of second openings, and a plurality of third openings, the first openings exposing a portion of the first sub-electrode portion, the second openings exposing a portion of the second sub-electrode portion, and the third openings exposing a portion of the third sub-electrode portion;

[0065] The orthographic projection of the first opening on the substrate partially overlaps with the orthographic projections of two adjacent first power signal lines on the substrate, the two first power signal lines are located on either side of a geometric center of the first opening, and the geometric center of the orthographic projection of the first opening on the substrate is approximately equidistant from the orthographic projections of the two adjacent first power signal lines on the substrate; and / or

[0066] The orthographic projection of the third opening on the substrate partially overlaps with the orthographic projections of two adjacent first power signal lines on the substrate, the two first power signal lines are located on both sides of the geometric center of the third opening, and the geometric center of the orthographic projection of the third opening on the substrate is approximately equidistant from the orthographic projections of the two adjacent first power signal lines on the substrate.

[0067] In yet another aspect, a display device is provided, comprising the display substrate as described in any one of the above items. BRIEF DESCRIPTION OF THE DRAWINGS

[0068] Features and advantages of the present disclosure will become more apparent by describing in detail exemplary embodiments of the present disclosure with reference to the accompanying drawings.

[0069] FIG. 1 is a plan view schematically illustrating a display substrate according to some embodiments of the present disclosure.

[0070] FIG2 schematically shows an enlarged schematic diagram of the first conductive layer, the first electrode layer, and the pixel defining layer in the display substrate according to some embodiments of the present disclosure, located in the B1 area in FIG1 .

[0071] FIG3 schematically shows an enlarged schematic diagram of the B2 area in FIG2 .

[0072] FIG. 4 schematically shows an enlarged schematic diagram of a first conductive layer in a display substrate located in area B1 in FIG. 1 according to some embodiments of the present disclosure.

[0073] FIG. 5 schematically shows an enlarged schematic diagram of the first conductive layer in the display substrate according to some embodiments of the present disclosure being located in the B1 area in FIG. 1 .

[0074] FIG6 schematically shows an enlarged schematic diagram of the second conductive layer in the display substrate according to some embodiments of the present disclosure being located in the B1 area in FIG1 .

[0075] FIG7 schematically shows an enlarged schematic diagram of the first conductive layer, the second conductive layer, and the first active layer in the display substrate according to some embodiments of the present disclosure, located in the B1 area in FIG1 .

[0076] FIG8 schematically shows an enlarged schematic diagram of the first conductive layer, the second conductive layer, and the first active layer in the display substrate according to some embodiments of the present disclosure, located in the B1 area in FIG1 .

[0077] FIG. 9 schematically shows an enlarged schematic diagram of the second conductive layer in the display substrate according to some embodiments of the present disclosure being located in the B1 area in FIG. 1 .

[0078] FIG10 schematically shows an enlarged schematic diagram of the first conductive layer, the second conductive layer, and the first active layer in the display substrate according to some embodiments of the present disclosure, located in the B1 area in FIG1 .

[0079] FIG. 11 schematically shows an enlarged schematic diagram of a second conductive layer in a display substrate according to some embodiments of the present disclosure located in area B1 in FIG. 1 .

[0080] FIG12 schematically shows an enlarged schematic diagram of the first conductive layer, the second conductive layer, and the first active layer in the display substrate according to some embodiments of the present disclosure, located in the B1 area in FIG1 .

[0081] FIG13 schematically shows an enlarged schematic diagram of a light-emitting device layer and a driving circuit layer in a display substrate according to some embodiments of the present disclosure, located in the B1 area in FIG1 .

[0082] FIG. 14 is a schematic diagram of an equivalent circuit of a pixel driving circuit in a display substrate according to some exemplary embodiments of the present disclosure.

[0083] 15A to 15I are plan views of some film layers in a display substrate located in a display area according to some exemplary embodiments of the present disclosure;

[0084] 15A schematically illustrates a blocking layer, FIG15B schematically illustrates a combination of a blocking layer and a second active layer, FIG15C schematically illustrates a combination of a blocking layer, a second active layer and a first gate metal layer, FIG15D schematically illustrates a combination of a blocking layer, a second active layer, a first gate metal layer and a second gate metal layer, FIG15E schematically illustrates a combination of a blocking layer, a second active layer, a first gate metal layer, a second gate metal layer, a first active layer and a third gate metal layer, FIG15F schematically illustrates a combination of a blocking layer, a second active layer, a first gate metal layer, a second gate metal layer, a first active layer, a third gate metal layer, an interlayer insulating layer and a first source / drain metal layer, and FIG15G schematically illustrates a blocking layer, a second active layer, a first gate metal layer, a second gate metal layer, a first active layer, a third gate metal layer, a first source / drain metal layer, and a first source / drain metal layer. 15H illustrates a combination of a blocking layer, a second active layer, a first gate metal layer, a second gate metal layer, a first active layer, a third gate metal layer, an interlayer insulating layer, the first source-drain metal layer, a passivation layer, a first flat layer and a second source-drain metal layer, and FIG15I illustrates a combination of a blocking layer, a second active layer, a first gate metal layer, a second gate metal layer, a first active layer, a third gate metal layer, an interlayer insulating layer, the first source-drain metal layer, a passivation layer, a first flat layer, the second source-drain metal layer, the third source-drain metal layer and the first electrode layer. DETAILED DESCRIPTION

[0085] To make the purpose, technical solutions, and advantages of the embodiments of the present disclosure more clear, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the accompanying drawings. Obviously, the described embodiments are part of the embodiments of the present disclosure, not all of the embodiments. Based on the described embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present disclosure.

[0086] It should be noted that in the drawings, the sizes and relative sizes of elements may be exaggerated for clarity and / or descriptive purposes. Thus, the sizes and relative sizes of the individual elements are not necessarily limited to those shown in the drawings. In the specification and drawings, the same or similar reference numerals indicate the same or similar parts.

[0087] When an element is described as being "on" another element, "connected to" another element, or "bound to" another element, the element may be directly on the other element, directly connected to the other element, or directly bound to the other element, or there may be an intermediate element. However, when an element is described as being "directly on" another element, "directly connected to" another element, or "directly bound to" another element, there is no intermediate element. Other terms and / or expressions used to describe the relationship between elements should be interpreted in a similar manner, for example, "between" versus "directly between", "adjacent" versus "directly adjacent", or "on" versus "directly on", etc. In addition, the term "connected" may refer to a physical connection, an electrical connection, a communication connection, and / or a fluid connection. In addition, the X-axis, Y-axis, and Z-axis are not limited to the three axes of a rectangular coordinate system, and may be interpreted in a broader sense. For example, the X-axis, Y-axis, and Z-axis may be perpendicular to each other, or may represent different directions that are not perpendicular to each other. For the purposes of this disclosure, “at least one of X, Y, and Z” and “at least one selected from the group consisting of X, Y, and Z” may be interpreted as only X, only Y, only Z, or any combination of two or more of X, Y, and Z, such as XYZ, XY, YZ, and XZ. As used herein, the term “and / or” includes any and all combinations of one or more of the associated listed items.

[0088] It should be noted that although the terms "first," "second," etc. may be used herein to describe various parts, components, elements, regions, layers, and / or portions, these parts, components, elements, regions, layers, and / or portions should not be limited by these terms. Rather, these terms are used to distinguish one part, component, element, region, layer, and / or portion from another. Thus, for example, the first part, first member, first element, first region, first layer, and / or first portion discussed below may be referred to as a second part, second member, second element, second region, second layer, and / or second portion without departing from the teachings of the present disclosure.

[0089] For ease of description, spatially relative terms, such as "upper," "lower," "left," "right," etc., may be used herein to describe the relationship of one element or feature to another element or feature as shown in the figures. It should be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements described as "below" or "beneath" other elements or features would then be oriented "above" or "over" the other elements or features.

[0090] As used herein, the terms "substantially," "about," "approximately," "roughly," and other similar terms are used as terms of approximation rather than as terms of degree, and are intended to account for the inherent deviations in measured or calculated values ​​that would be recognized by one of ordinary skill in the art. To account for factors such as process fluctuations, measurement problems, and errors associated with the measurement of a particular quantity (i.e., limitations of the measurement system), "about" or "approximately" as used herein are inclusive of the stated value and mean within an acceptable range of deviation for the particular value as determined by one of ordinary skill in the art. For example, "approximately" can mean within one or more standard deviations, or within ±30%, ±20%, ±10%, ±5% of the stated value.

[0091] It should be noted that, in this article, the term "the same layer" refers to a layer structure formed by using the same film-forming process to form a film layer used to form a specific pattern, and then patterning the film layer using the same mask through a single patterning process. Depending on the specific pattern, a single patterning process may include multiple exposure, development, or etching processes, and the specific pattern in the resulting layer structure may be continuous or discontinuous. In other words, multiple elements, components, structures, and / or parts located in the "same layer" are composed of the same material and are formed through the same patterning process. Typically, multiple elements, components, structures, and / or parts located in the "same layer" have approximately the same thickness.

[0092] Those skilled in the art should understand that, in this article, unless otherwise specified, the expression "height" or "thickness" refers to the dimension of the surface of each film layer arranged perpendicular to the display substrate, that is, the dimension along the light emitting direction of the display substrate, or the dimension along the normal direction of the display device.

[0093] In this document, the term "transistor" may refer to a triode, a thin-film transistor, a field-effect transistor, or other device with similar characteristics. In the embodiments of the present disclosure, to distinguish the two electrodes of a transistor other than the control electrode, one electrode is referred to as the first electrode, and the other electrode is referred to as the second electrode. In actual operation, when the transistor is a thin-film transistor or a field-effect transistor, the first electrode may be the drain electrode, and the second electrode may be the source electrode; alternatively, the first electrode may be the source electrode, and the second electrode may be the drain electrode.

[0094] Figure 1 is a schematic plan view of a display substrate according to some embodiments of the present disclosure, wherein Figure 1 schematically illustrates a base substrate and a light-emitting device layer within the display substrate. Figure 2 schematically illustrates an enlarged schematic view of a first conductive layer, a first electrode layer, and a pixel-defining layer within the display substrate according to some embodiments of the present disclosure, located in region B1 of Figure 1. Figure 3 schematically illustrates an enlarged schematic view of region B2 of Figure 2.

[0095] According to some exemplary embodiments, referring to FIG. 1 , a display substrate includes a display area AA and a peripheral area NA located around the display area AA. The display substrate includes a base substrate 100 and a light-emitting device layer 200 located on the base substrate 100. At least a portion of the light-emitting device layer 200 is located within the display area AA. The light-emitting device layer 200 includes at least a first electrode layer located on the base substrate 100, a light-emitting layer located on a side of the first electrode layer away from the base substrate 100, and a second light-emitting layer located on a side of the light-emitting layer away from the base substrate 100. The display substrate also includes a first conductive layer located between the base substrate 100 and the light-emitting device layer 200, and a pixel defining layer located between the first electrode layer and the light-emitting layer.

[0096] Referring to Figure 2 , the first electrode layer includes multiple first electrode portions 90, which are located in the display area of ​​the display substrate. The pixel defining layer has multiple openings K, each opening K exposing a portion of a first electrode portion 90. The light-emitting layer includes multiple light-emitting sections, each of which is located within the multiple openings K and in contact with the multiple first electrode portions 90. The second electrode layer contacts the multiple light-emitting sections through the multiple openings K. A first electrode section 90, a light-emitting section, and the portion of the second electrode layer in contact with the light-emitting section constitute a light-emitting device. That is, the first electrode layer, the light-emitting layer, and the second light-emitting layer constitute multiple light-emitting devices, and the multiple light-emitting devices are arrayed on the base substrate 100.

[0097] 2 and 3 , the first conductive layer includes a plurality of first power signal lines 71. The plurality of first power signal lines 71 are arranged along a first direction X and extend along a second direction Y, with the first direction X intersecting the second direction Y. The first power signal lines 71 are used to transmit a first power signal, which serves as a power signal connected to the first electrode portion 90 of the light-emitting device. The plurality of first power signal lines 71 include a plurality of first power signal line groups 71A arranged along the first direction X. Each first power signal line group 71A includes two adjacent first power signal lines 71. Within each first power signal line group 71A, the two first power signal lines 71 are spaced apart along the first direction X. The signal transmitted by one first power signal line 71 is different from the signal transmitted by the other first power signal line 71. The minimum spacing W1 between the two first power signal lines 71 along the first direction X is less than the dimension W2 of the opening K along the first direction X.

[0098] It should be understood that the spacing between the two first power signal lines 71 along the first direction X may be different at different positions along the second direction Y. The minimum spacing W1 refers to the spacing between the two first power signal lines 71 at their closest locations along the first direction X. The dimension W2 of the opening K along the first direction X refers to the spacing between the two ends of the opening K along the first direction X.

[0099] The display substrate is provided with first power signal lines 71 that transmit different signals, thereby providing different first power signals to different light-emitting devices. Compared to an arrangement in which different light-emitting devices share the same first power signal, the display substrate provided by the present embodiment avoids the problem of wasted power consumption by the remaining light-emitting devices when some light-emitting devices are emitting light, thereby reducing the power consumption of the display substrate. Furthermore, the minimum spacing W1 between two first power signal lines 71 along the first direction X is set to be smaller than the dimension W2 of the opening K along the first direction X. This means that the multiple first power signal lines 71 are arranged more densely, thereby increasing the pixel density of the display panel, that is, improving the display resolution of the display panel.

[0100] According to some exemplary embodiments, referring to FIG. 2 , the plurality of openings K in the pixel defining layer include a plurality of first openings K1, a plurality of second openings K2, and a plurality of third openings K3. The plurality of first electrode portions 90 include a plurality of first sub-electrode portions 901, a plurality of second sub-electrode portions 902, and a plurality of third sub-electrode portions 903. The first openings K1 expose at least a portion of the first sub-electrode portions 901, the second openings K2 expose at least a portion of the second sub-electrode portions 902, and the third openings K3 expose at least a portion of the third sub-electrode portions 903.

[0101] According to some exemplary embodiments, a minimum distance W1 between two first power signal lines 71 along the first direction X is smaller than a dimension of the first opening K1 along the first direction X.

[0102] According to some exemplary embodiments, a minimum distance W1 between two first power signal lines 71 along the first direction X is smaller than a dimension of the second opening K2 along the first direction X.

[0103] According to some exemplary embodiments, a minimum distance W1 between two first power signal lines 71 along the first direction X is smaller than a dimension of the third opening K3 along the first direction X.

[0104] FIG. 4 schematically shows an enlarged schematic diagram of a first conductive layer in a display substrate located in area B1 in FIG. 1 according to some embodiments of the present disclosure.

[0105] According to some exemplary embodiments, referring to FIG. 4 , the first power signal line group 71A includes two main power lines 714 and a plurality of first signal blocks 715 located between the two main power lines 714 . The plurality of first signal blocks 715 are arranged at intervals along the second direction Y. Any first signal block 715 is directly connected to one main power line 714 and is spaced apart from another main power line 714 along the first direction X. The spacing between the first signal block 715 and the spaced main power lines 714 along the first direction X is less than the size of the opening along the first direction X.

[0106] That is, a main power line 714 and one or more connected first signal blocks 715 form a first power signal line 71, or a main power line 714 directly forms a first power signal line 71. The first power signal line 71 provided with the first signal block 715 has a lower resistance than the first power signal line 71 without the first signal block 715. By providing the first signal block 715, the resistance of the first power signal line 71 can be reduced, thereby alleviating the voltage drop (IR drop) phenomenon of the voltage signal transmitted in the first power signal line 71, thereby improving the display brightness uniformity of the display substrate.

[0107] According to some exemplary embodiments, referring to FIG. 4 , the main power line 714 is a zigzag line extending from the main portion along the second direction Y. The first signal block 715 is rectangular in shape, and one side of the first signal block 715 is directly connected to the main power line 714. The connected first signal block 715 and the main power line 714 form an integral structure. The width of the first signal block 715 along the first direction X is greater than the width of the main power line 714 along the first direction X. For example, the width of the first signal block 715 along the first direction X is greater than five times the width of the main power line 714 along the first direction X.

[0108] According to some exemplary embodiments, with reference to FIG2 and FIG4 , the orthographic projection of the second opening K2 on the substrate substrate is located between the orthographic projections of the two main power lines 714 in the first power signal line group 71A on the substrate substrate, and the minimum spacing W1 between the two first power signal lines 71 along the first direction X is smaller than the size of the second opening K2 along the first direction X, that is, the spacing between the first signal block 715 and the spaced main power lines 714 along the first direction X is smaller than the size of the second opening K2 along the first direction X.

[0109] According to some exemplary embodiments, with reference to FIG2 and FIG4 , the orthographic projection of the second opening K2 on the base substrate is located between the orthographic projections of two main power lines 714 in the first power signal line group 71A on the base substrate, and the minimum spacing W1 between the two first power signal lines 71 along the first direction X is smaller than the size of any opening K along the first direction X.

[0110] According to some exemplary embodiments, the plurality of light-emitting devices includes a plurality of first light-emitting devices, a plurality of second light-emitting devices, and a plurality of third light-emitting devices. Referring to FIG2 , the plurality of first electrode portions 90 includes a plurality of first sub-electrode portions 901, a plurality of second sub-electrode portions 902, and a plurality of third sub-electrode portions 903, wherein the first sub-electrode portion 901 serves as the first electrode portion 90 of the first light-emitting device, the second sub-electrode portion 902 serves as the first electrode portion 90 of the second light-emitting device, and the third sub-electrode portion 903 serves as the first electrode portion 90 of the third light-emitting device.

[0111] Accordingly, referring to FIG4 , the plurality of first power signal lines 71 include a plurality of first sub-power lines 711, a plurality of second sub-power lines 712, and a plurality of third sub-power lines 713. The first sub-power lines 711 are used to transmit a first signal, the second sub-power lines 712 are used to transmit a second signal, and the third sub-power lines 713 are used to transmit a third signal, wherein any two of the first, second, and third signals are different from each other. Referring to FIG4 in conjunction with FIG2 , the first sub-electrode portion 901 is electrically connected to the corresponding first sub-power line 711 to receive the first signal, the second sub-electrode portion 902 is electrically connected to the corresponding second sub-power line 712 to receive the second signal, and the third sub-electrode portion 903 is electrically connected to the corresponding third sub-power line 713 to receive the third signal.

[0112] For example, the first light-emitting device emits red light, the second light-emitting device emits green light, and the third light-emitting device emits blue light. Because the light-emitting currents of the first light-emitting device emitting red light, the second light-emitting device emitting green light, and the third light-emitting device emitting blue light are different, different first power signal lines are provided to provide different first power signals to the different light-emitting devices in order to match the light-emitting currents required by the different light-emitting devices.

[0113] According to some exemplary embodiments, referring to FIG2 , in addition to transmitting the first power signal, the first signal block 715 also serves as a planarization structure for flattening a portion of the first electrode portion 90. The orthographic projections of the plurality of first signal blocks 715 on the substrate overlap with the orthographic projections of a portion of the first electrode portion 90 on the substrate.

[0114] According to some exemplary embodiments, referring to FIG2 and FIG4 , considering that the second light-emitting device emitting green light is more susceptible to color shift due to unevenness compared to the first and third light-emitting devices, the first signal block 715 is correspondingly disposed below the second sub-electrode portion 902 of the second light-emitting device to level the second light-emitting device. Specifically, the orthographic projection of the second sub-electrode portion 902 on the substrate at least partially overlaps with the orthographic projection of the first signal block 715 on the substrate. Referring to FIG2 and FIG3 , the orthographic projection of the gap on the substrate at which the minimum spacing W1 between the two first power signal lines 71 is located along the first direction X does not overlap with the orthographic projection of the second opening K2 on the substrate that exposes at least a portion of the second sub-electrode portion 902. Specifically, the orthographic projection of the gap on the substrate at which the minimum spacing W1 is located is spaced apart from the orthographic projection of the second opening K2 on the substrate.

[0115] According to some exemplary embodiments, referring to FIG. 2 , the plurality of openings K in the pixel defining layer include a plurality of first openings K1, a plurality of second openings K2, and a plurality of third openings K3. The first openings K1 expose at least a portion of the first sub-electrode portion 901, the second openings K2 expose at least a portion of the second sub-electrode portion 902, and the third openings K3 expose at least a portion of the third sub-electrode portion 903. The orthographic projection of the second openings K2 on the base substrate at least partially overlaps with the orthographic projection of the first signal block 715 on the base substrate. Alternatively, the orthographic projection of the second openings K2 on the base substrate is located within the orthographic projection of the first signal block 715 on the base substrate.

[0116] According to some exemplary embodiments, with reference to FIG2 , in order to ensure the flatness of the first light-emitting device, the relative positional relationship between the first opening K1 exposing the first sub-electrode portion 901 and the first conductive layer is set accordingly. Specifically, the orthographic projection of the first opening K1 on the substrate partially overlaps with the orthographic projections of two adjacent first power signal lines 71 on the substrate, and the two adjacent first power signal lines 71 are respectively located on both sides of the geometric center of the first opening K1. The distance between the geometric center of the orthographic projection of the first opening K1 on the substrate and the orthographic projection of one of the first power signal lines 71 on the substrate is D1, and the distance between the geometric center of the orthographic projection of the first opening K1 on the substrate and the orthographic projection of the other first power signal line 71 on the substrate is D2, and D1 and D2 are approximately equal. That is, the two first power signal lines 71 are arranged approximately symmetrically on both sides of the first opening K1 to improve the flatness of the first light-emitting device as much as possible.

[0117] It should be understood that the spacing D1 is defined as the distance between the geometric center of the orthographic projection of the first opening K1 on the substrate and the edge of the orthographic projection of a first power signal line 71 (the first power signal line 71 located to the left of the geometric center shown in Figure 2) on the substrate close to the geometric center (the right edge of the orthographic projection of the first power signal line 71 on the substrate shown in Figure 2); the spacing D2 is defined as the distance between the geometric center of the orthographic projection of the first opening K1 on the substrate and the edge of the orthographic projection of another first power signal line 71 (the first power signal line 71 located to the right of the geometric center shown in Figure 2) on the substrate close to the geometric center (the left edge of the orthographic projection of the first power signal line 71 on the substrate shown in Figure 2).

[0118] It should be noted that due to factors such as the accuracy of the composition process, it is difficult for D1 and D2 to be completely equal. D1 and D2 being roughly equal should be understood as 0.9*D2≤D1≤1.1*D2.

[0119] According to some exemplary embodiments, referring to FIG. 2 , the first conductive layer further includes a plurality of data signal lines 72 extending along the second direction Y, with at least two data signal lines 72 disposed between two adjacent first power signal lines 71. To ensure the flatness of the first light-emitting device, the data signal lines 72 may be disposed with reference to the first power signal lines 71. Specifically, the orthographic projection of the first opening K1 on the substrate partially overlaps with the orthographic projections of the two adjacent data signal lines 72 on the substrate, and the two adjacent data signal lines 72 are located on either side of the geometric center of the first opening K1. The distance between the geometric center of the orthographic projection of the first opening K1 on the substrate and the orthographic projection of one of the data signal lines 72 on the substrate is approximately equal to the distance between the geometric center of the orthographic projection of the first opening K1 on the substrate and the orthographic projection of another of the data signal lines 72 on the substrate.

[0120] According to some exemplary embodiments, referring to FIG. 2 , the first conductive layer further includes a plurality of first transfer signal lines 73 extending along the second direction Y, with at least one first transfer signal line 73 disposed between two adjacent data signal lines 72. The orthographic projection of the first opening K1 on the substrate partially overlaps with the orthographic projection of a corresponding first transfer signal line 73 on the substrate. To ensure the flatness of the first light-emitting device, the relative positions of the first transfer signal line 73 and the first opening K1 are set so that the geometric center of the orthographic projection of the first opening K1 on the substrate is located within the orthographic projection of the first transfer signal line 73 on the substrate.

[0121] According to some exemplary embodiments, with reference to FIG2 , to ensure the flatness of the third light-emitting device, the relative positional relationship between the third opening K3 exposing the third sub-electrode portion 903 and the first conductive layer is set accordingly. Specifically, the orthographic projection of the third opening K3 on the substrate partially overlaps with the orthographic projections of two adjacent first power signal lines 71 on the substrate, and the two adjacent first power signal lines 71 are located on either side of the geometric center of the third opening K3. The geometric center of the orthographic projection of the third opening K3 on the substrate is spaced D3 from the orthographic projection of one of the first power signal lines 71 on the substrate, and the geometric center of the orthographic projection of the third opening K3 on the substrate is spaced D4 from the orthographic projection of the other first power signal line 71 on the substrate, with D3 and D4 being approximately equal. That is, the two first power signal lines 71 are arranged approximately symmetrically on either side of the third opening K3, thereby maximizing the flatness of the third light-emitting device.

[0122] It should be noted that, due to factors such as patterning process accuracy, it is difficult for D3 and D4 to be completely equal. D3 and D4 being roughly equal should be understood as 0.9*D4≤D3≤1.1*D4.

[0123] According to some exemplary embodiments, referring to FIG. 2 , the first conductive layer further includes a plurality of data signal lines 72, with at least two data signal lines 72 disposed between two adjacent first power signal lines 71. To ensure the flatness of the third light-emitting device, the data signal lines 72 may be disposed with reference to the first power signal lines 71. Specifically, the orthographic projection of the third opening K3 on the substrate partially overlaps with the orthographic projections of the two adjacent data signal lines 72 on the substrate, and the two adjacent data signal lines 72 are located on either side of the geometric center of the third opening K3. The distance between the geometric center of the orthographic projection of the third opening K3 on the substrate and the orthographic projection of one of the data signal lines 72 on the substrate is approximately equal to the distance between the geometric center of the orthographic projection of the third opening K3 on the substrate and the orthographic projection of the other data signal line 72 on the substrate.

[0124] According to some exemplary embodiments, referring to FIG. 2 , the first conductive layer further includes a plurality of first transfer signal lines 73 extending along the second direction Y, with at least one first transfer signal line 73 disposed between two adjacent data signal lines 72. The orthographic projection of the third opening K3 on the substrate partially overlaps with the orthographic projection of a corresponding first transfer signal line 73 on the substrate. To ensure the flatness of the first light-emitting device, the relative positions of the first transfer signal line 73 and the third opening K3 are set so that the geometric center of the orthographic projection of the third opening K3 on the substrate is located within the orthographic projection of the first transfer signal line 73 on the substrate.

[0125] According to some exemplary embodiments, referring to FIG4 , in the first power signal line group 71A, a portion of the first signal blocks 715 are directly connected to one main power line 714, and the remaining portion of the first signal blocks 715 are directly connected to another main power line 714. Exemplarily, the plurality of first signal blocks 715 directly connected to the same main power line 714 and the plurality of first signal blocks 715 directly connected to another main power line 714 are alternately arranged along the second direction Y.

[0126] According to some exemplary embodiments, referring to FIG4 , the plurality of first power signal lines 71 include a plurality of first power signal units 71B arranged along a first direction X. The first power signal unit 71B includes a first sub-power line 711 , two second sub-power lines 712 , and a third sub-power line 713 . The first sub-power line 711 is located on one side of the two second sub-power lines 712 along the first direction X, and the third sub-power line 713 is located between the two second sub-power lines 712 .

[0127] According to some exemplary embodiments, in the first power signal unit 71B, the first sub-power line 711 and the adjacent second sub-power line 712 include a first main power line 714A, a second main power line 714B, and a plurality of first signal blocks 715 located between the first main power line 714A and the second main power line 714B. A portion of the first signal blocks 715 are directly connected to the first main power line 714A, while the remaining portion of the first signal blocks 715 are directly connected to the second main power line 714B. The plurality of first signal blocks 715 connected to the first main power line 714A and the plurality of first signal blocks 715 connected to the second main power line 714B are alternately arranged along the second direction Y. In the partial area shown in FIG. 4 , the first signal blocks 715 in the first and third rows are connected to the first main power line 714A on the left to form the first sub-power line 711, and the first signal blocks 715 in the second and fourth rows are connected to the second main power line 714B on the right to form the second sub-power line 712. The first sub-power line 711 and the second sub-power line 712 are both provided with first signal blocks 715 , and the number of first signal blocks 715 on the first sub-power line 711 and the number of first signal blocks 715 on the second sub-power line 712 are substantially equal.

[0128] In the first power signal unit 71B, the third sub-power line 713 and the adjacent second sub-power line 712 include a third main power line 714C, a second main power line 714B, and a plurality of first signal blocks 715 located between the third main power line 714C and the second main power line 714B. A portion of the first signal blocks 715 are directly connected to the third main power line 714C, while the remaining portion of the first signal blocks 715 are directly connected to the second main power line 714B. The plurality of first signal blocks 715 connected to the third main power line 714C and the plurality of first signal blocks 715 connected to the second main power line 714B are arranged alternately along the second direction Y. In the partial area shown in FIG. 4 , the first signal blocks 715 in the first and third rows are connected to the third main power line 714C on the left to form the third sub-power line 713, while the first signal blocks 715 in the second and fourth rows are connected to the second main power line 714B on the right to form the second sub-power line 712. The third sub-power line 713 and the second sub-power line 712 are both provided with first signal blocks 715 , and the number of first signal blocks 715 on the third sub-power line 713 and the number of first signal blocks 715 on the second sub-power line 712 are substantially equal.

[0129] According to some exemplary embodiments, in a first power signal unit 71B, the first sub-power line 711 and the adjacent second sub-power line 712 form a first power signal line group 71A, and the third sub-power line 713 and the adjacent second sub-power line 712 form another first power signal line group 71A. That is, a first power signal unit 71B includes two adjacent first power signal line groups 71A. Each first power signal line group 71A includes a second sub-power line 712, and the multiple first signal blocks 715 in each second sub-power line 712 are located in fixed rows. For example, the multiple first signal blocks 715 in each second sub-power line 712 are located in odd-numbered rows. Alternatively, the multiple first signal blocks 715 in each second sub-power line 712 are located in even-numbered rows.

[0130] FIG. 5 schematically shows an enlarged schematic diagram of the first conductive layer in the display substrate according to some embodiments of the present disclosure being located in the B1 area in FIG. 1 .

[0131] According to some exemplary embodiments, referring to FIG. 5 , in the first power signal line group 71A, each first signal block 715 is directly connected to the same main power line 714 .

[0132] According to some exemplary embodiments, referring to FIG. 5 , in the first power signal unit 71B, the first sub-power line 711 and the adjacent second sub-power line 712 include a first main power line 714A, a second main power line 714B, and a plurality of first signal blocks 715 located between the first main power line 714A and the second main power line 714B. Each first signal block 715 is directly connected to the first main power line 714A to form the first sub-power line 711. That is, the first sub-power line 711 includes the plurality of first signal blocks 715, and the second sub-power line 712 includes only the second main power line 714B.

[0133] Similarly, in the first power signal unit 71B, the third sub-power line 713 and the adjacent second sub-power line 712 include a third main power line 714C, a second main power line 714B, and a plurality of first signal blocks 715 located between the third main power line 714C and the second main power line 714B. Each first signal block 715 is directly connected to the third main power line 714C to form the third sub-power line 713. In other words, the third sub-power line 713 includes a plurality of first signal blocks 715, while the second sub-power line 712 includes only the second main power line 714B.

[0134] In the display substrate provided by the embodiments of the present disclosure, considering that the second light-emitting device emitting green light has a lower emission current than the first light-emitting device emitting red light and the third light-emitting device emitting blue light, the voltage value of the second signal transmitted by the second sub-power line 712 is lower than the voltage values ​​of the first and third signals. Consequently, the voltage drop generated by the second sub-power line 712 when transmitting the second signal is also smaller. Based on this, the first signal block 715 is provided in the first sub-power line 711 and the third sub-power line 713, while the first signal block 715 is not provided in the second sub-power line 712. This effectively reduces the voltage drop that occurs when the first sub-power line 711 and the third sub-power line 713 transmit signals.

[0135] Figure 6 schematically shows an enlarged schematic diagram of the second conductive layer in the display substrate according to some embodiments of the present disclosure located in region B1 in Figure 1. Figure 7 schematically shows an enlarged schematic diagram of the first conductive layer, the second conductive layer, and the first active layer in the display substrate according to some embodiments of the present disclosure located in region B1 in Figure 1.

[0136] According to some exemplary embodiments, referring to FIG. 6 , the display substrate further includes a second conductive layer located on a side of the first conductive layer close to the base substrate. The second conductive layer includes a plurality of first auxiliary signal lines 61. The plurality of first auxiliary signal lines 61 are arranged along the second direction Y and extend along the first direction X.

[0137] 6 and 7 , the plurality of first auxiliary signal lines 61 include a plurality of first sub-auxiliary lines 611, a plurality of second sub-auxiliary lines 612, and a plurality of third sub-auxiliary lines 613. The first sub-auxiliary lines 611 and the first sub-power lines 711 both transmit first signals. The first sub-auxiliary lines 611 are configured to transmit the first signal along a first direction X. At least one first sub-auxiliary line 611 is electrically connected to each of the plurality of first sub-power lines 711. The plurality of first sub-auxiliary lines 611 and the plurality of first sub-power lines 711 are electrically connected to each other to form a first grid of signal lines. This allows for a more uniform distribution of the first signal within the display area, thereby improving display uniformity across the display substrate.

[0138] The second sub-auxiliary lines 612 and the second sub-power lines 712 both transmit second signals. The second sub-auxiliary lines 612 are used to transmit the second signals along the first direction X. At least one second sub-auxiliary line 612 is electrically connected to multiple second sub-power lines 712, respectively. Multiple second sub-auxiliary lines 612 and multiple second sub-power lines 712 are electrically connected to each other to form a second grid-like signal line. This can make the second signal in the display area more evenly distributed, thereby improving the display uniformity of the display substrate.

[0139] The third sub-auxiliary lines 613 and the third sub-power lines 713 both transmit third signals. The third sub-auxiliary lines 613 are used to transmit the third signals along the first direction X. At least one third sub-auxiliary line 613 is electrically connected to multiple third sub-power lines 713, respectively. Multiple third sub-auxiliary lines 613 and multiple third sub-power lines 713 are electrically connected to each other to form a third grid of signal lines. This can make the third signal more evenly distributed in the display area, thereby improving the display uniformity of the display substrate.

[0140] According to some exemplary embodiments, referring to FIG6 and FIG7 , the plurality of first auxiliary signal lines 61 include a plurality of first auxiliary signal units 61A arranged along the second direction Y. The first auxiliary signal unit 61A includes a first sub-auxiliary line 611, two second sub-auxiliary lines 612, and a third sub-auxiliary line 613. The first sub-auxiliary line 611 is located on one side of the two second sub-auxiliary lines 612 along the second direction Y, and the third sub-auxiliary line 613 is located between the two second sub-auxiliary lines 612. That is, the first auxiliary signal unit 61A includes the first sub-auxiliary line 611, the second sub-auxiliary line 612, the third sub-auxiliary line 613, and the second sub-auxiliary line 612 arranged in sequence along the second direction Y.

[0141] According to some exemplary embodiments, the second conductive layer also includes a plurality of first connection portions 64, the first connection portion 64 is located on one side of the first auxiliary signal line 61 along the second direction Y (for example, the upper side shown in Figure 6), the first sub-auxiliary line 611 is electrically connected to the first sub-power line 711 through the corresponding first connection portion 64, the second sub-auxiliary line 612 is electrically connected to the second sub-power line 712 through the corresponding first connection portion 64, and the third sub-auxiliary line 613 is electrically connected to the third sub-power line 713 through the corresponding first connection portion 64.

[0142] In addition, the remaining first connection parts 64 are only electrically connected to the first power signal line 71 and are separated from the first auxiliary signal line 61. This design is to make the first connection parts 64 evenly distributed in the display area to avoid uneven display.

[0143] According to some exemplary embodiments, the second conductive layer further includes a plurality of second transfer signal lines 63 arranged along the second direction Y and extending along the first direction X. A portion of the second transfer signal lines 63 is electrically connected to a portion of the first transfer signal lines 73 for transferring data signals, typically for transferring data signals to drive circuit columns located on both sides along the first direction. This eliminates the need for fan-out wiring in the peripheral area, thereby narrowing the bezel width of the display substrate. Furthermore, the remaining portion of the first transfer signal lines 73 and the remaining portion of the second transfer signal lines 63 can be used to transmit constant voltage signals required by the display substrate, such as a second power supply signal provided to the second electrode portion of the light-emitting device.

[0144] As needed, the first transfer signal line 73 may be provided with one or more breaks, and the second transfer signal line 63 may be provided with one or more breaks, which is not limited in the embodiment of the present disclosure.

[0145] According to some exemplary embodiments, referring to Figures 6 and 7, the second conductive layer further includes a plurality of second connection portions 65 and a plurality of third connection portions 66, the second connection portions 65 are electrically connected to the first electrode connection portions 74 located in the first conductive layer, and the third connection portions 66 are electrically connected to the data signal lines 72 located in the first conductive layer.

[0146] According to some exemplary embodiments, the display substrate further includes a first active layer located on a side of the second conductive layer proximal to the display substrate. For example, the material of the first active layer includes a metal oxide semiconductor material. The orthographic projection of the first active layer on the base substrate at least partially overlaps with the orthographic projection of the first signal block 715 on the base substrate. For example, the first active layer includes a plurality of second active portions 12, each of which includes a channel region 12A and first and second regions located on either side of the channel region. The orthographic projection of the channel region 12A on the base substrate is located within the orthographic projection of the first signal block 715 on the base substrate, and the first signal block 715 provides light shielding for the channel region 12A.

[0147] According to some exemplary embodiments, a plurality of first signal blocks 715 are respectively provided in the first sub-power line 711 , the second sub-power line 712 , and the third sub-power line 713 .

[0148] FIG8 schematically shows an enlarged schematic diagram of the first conductive layer, the second conductive layer, and the first active layer in the display substrate according to some embodiments of the present disclosure, located in the B1 area in FIG1 .

[0149] 6 and 8 , the plurality of first auxiliary signal lines 61 include a plurality of first sub-auxiliary lines 611, a plurality of second sub-auxiliary lines 612, and a plurality of third sub-auxiliary lines 613. The first sub-auxiliary lines 611 and the first sub-power lines 711 both transmit first signals. The first sub-auxiliary lines 611 are configured to transmit the first signal along a first direction X. At least one first sub-auxiliary line 611 is electrically connected to each of the plurality of first sub-power lines 711. The plurality of first sub-auxiliary lines 611 and the plurality of first sub-power lines 711 are electrically connected to each other to form a first grid of signal lines. This allows for a more uniform distribution of the first signal within the display area, thereby improving display uniformity across the display substrate.

[0150] The second sub-auxiliary lines 612 and the second sub-power lines 712 both transmit second signals. The second sub-auxiliary lines 612 are used to transmit the second signals along the first direction X. At least one second sub-auxiliary line 612 is electrically connected to multiple second sub-power lines 712, respectively. Multiple second sub-auxiliary lines 612 and multiple second sub-power lines 712 are electrically connected to each other to form a second grid-like signal line. This can make the second signal in the display area more evenly distributed, thereby improving the display uniformity of the display substrate.

[0151] The third sub-auxiliary lines 613 and the third sub-power lines 713 both transmit third signals. The third sub-auxiliary lines 613 are used to transmit the third signals along the first direction X. At least one third sub-auxiliary line 613 is electrically connected to multiple third sub-power lines 713, respectively. Multiple third sub-auxiliary lines 613 and multiple third sub-power lines 713 are electrically connected to each other to form a third grid of signal lines. This can make the third signal more evenly distributed in the display area, thereby improving the display uniformity of the display substrate.

[0152] According to some exemplary embodiments, a plurality of first signal blocks 715 are respectively provided in the first sub-power line 711 and the third sub-power line 713 , while no first signal block 715 is provided in the second sub-power line 712 .

[0153] Figure 9 schematically shows an enlarged schematic diagram of the second conductive layer in the display substrate according to some embodiments of the present disclosure located in region B1 in Figure 1. Figure 10 schematically shows an enlarged schematic diagram of the first conductive layer, the second conductive layer, and the first active layer in the display substrate according to some embodiments of the present disclosure located in region B1 in Figure 1.

[0154] According to some exemplary embodiments, referring to Figures 9 and 10 , the second conductive layer further includes a plurality of second signal blocks 62. Each second signal block 62 and a first signal block 715 form a signal block unit 62A. In signal block unit 62A, the orthographic projection of the second signal block 62 on the substrate at least partially overlaps with the orthographic projection of the first signal block 715 on the substrate, and the second signal block 62 and the first signal block 715 are electrically connected to the same main power line 714. This means that the overlapping second signal blocks 62 and first signal blocks 715 transmit the same signal, thus avoiding signal crosstalk. Furthermore, the provision of the second signal block 62 can further reduce the voltage drop that occurs when the first power signal line connected to the second signal block 62 transmits a signal.

[0155] According to some exemplary embodiments, referring to FIG. 10 , the display substrate further includes a first active layer located on a side of the second conductive layer proximal to the display substrate. For example, the material of the first active layer includes a metal oxide semiconductor material. The orthographic projection of the first active layer on the base substrate at least partially overlaps with the orthographic projection of the second signal block 62 on the base substrate. For example, the first active layer includes a plurality of second active portions 12, each of which includes a channel region 12A and first and second regions located on either side of the channel region. The orthographic projection of the channel region 12A on the base substrate is located within the orthographic projection of the second signal block 62 on the base substrate, and the second signal block 62 provides light shielding for the channel region 12A.

[0156] According to some exemplary embodiments, referring to FIG10 , the orthographic projection of the second signal block 62 on the substrate overlaps the orthographic projection of the first signal block 715. That is, when the second signal block 62 already meets the light shielding requirements for the channel region 12A, the first signal block 715 can be appropriately smaller, thereby alleviating the problem of limited wiring space in the first conductive layer.

[0157] According to some exemplary embodiments, referring to Figures 9 and 10, the plurality of second signal blocks 62 include a plurality of second signal block groups 62G arranged along the second direction Y, the second signal block group 62G includes a plurality of second signal blocks 62 arranged along the first direction X, and one second signal block group 62G is arranged adjacent to one first auxiliary signal line 61 along the second direction Y.

[0158] In the first sub-auxiliary line 611 and the adjacent second signal block group 62G, a portion of the second signal blocks 62 are electrically connected to the first sub-auxiliary line 611, while the remaining portion of the second signal blocks 62 are spaced apart from the first sub-auxiliary line 611. The plurality of second signal blocks 62 electrically connected to the first sub-auxiliary line 611 and the plurality of second signal blocks 62 spaced apart from the first sub-auxiliary line 611 are alternately arranged along the first direction X. The second signal blocks 62 electrically connected to the first sub-auxiliary line 611 and the first signal blocks 715 located in the same signal block unit 62A are both electrically connected to the first main power line 714A, and the second signal blocks 62 spaced apart from the first sub-auxiliary line 611 and the first signal blocks 715 located in the same signal block unit 62A are both electrically connected to the third main power line 714C.

[0159] In the second sub-auxiliary line 612 and the adjacent second signal block group 62G, each second signal block 62 is electrically connected to the second sub-auxiliary line 612, wherein the second signal block 62 and the first signal block 715 located in the same signal block unit 62A are electrically connected to the second main power line 714B.

[0160] In the third auxiliary sub-line 613 and the adjacent second signal block group 62G, a portion of the second signal blocks 62 are electrically connected to the third auxiliary sub-line 613, while the remaining portion of the second signal blocks 62 are spaced apart from the third auxiliary sub-line 613. The plurality of second signal blocks 62 electrically connected to the third auxiliary sub-line 613 and the plurality of second signal blocks 62 spaced apart from the third auxiliary sub-line 613 are alternately arranged along the first direction X. The second signal blocks 62 electrically connected to the third auxiliary sub-line 613 and the first signal blocks 715 located in the same signal block unit 62A are both electrically connected to the third main power line 714C, and the second signal blocks 62 spaced apart from the third auxiliary sub-line 613 and the first signal blocks 715 located in the same signal block unit 62A are both electrically connected to the first main power line 714A.

[0161] It should be understood that whether the second signal block 62 is electrically connected to the adjacent first auxiliary signal line 61 depends on the signal transmitted by the main power line 714 electrically connected to the second signal block 62. If the signal transmitted by the main power line 714 is the same as the signal transmitted by the adjacent first auxiliary signal line 61, the second signal block 62 is electrically connected to the adjacent first auxiliary signal line 61; otherwise, no electrical connection is made.

[0162] Figure 11 schematically shows an enlarged schematic diagram of a second conductive layer in a display substrate according to some embodiments of the present disclosure located in region B1 in Figure 1. Figure 12 schematically shows an enlarged schematic diagram of a first conductive layer, a second conductive layer, and a first active layer in a display substrate according to some embodiments of the present disclosure located in region B1 in Figure 1.

[0163] According to some exemplary embodiments, referring to Figures 9 and 10, the plurality of second signal blocks 62 include a plurality of second signal block groups 62G arranged along the second direction Y, the second signal block groups 62G include a plurality of second signal blocks 62 arranged along the first direction X, and the plurality of second signal block groups 62G are respectively located on one side of the plurality of first auxiliary signal lines 61 along the second direction Y.

[0164] In the first sub-auxiliary line 611 and the adjacent second signal block group 62G, a portion of the second signal blocks 62 are electrically connected to the first sub-auxiliary line 611, while the remaining portion of the second signal blocks 62 are spaced apart from the first sub-auxiliary line 611. The plurality of second signal blocks 62 electrically connected to the first sub-auxiliary line 611 and the plurality of second signal blocks 62 spaced apart from the first sub-auxiliary line 611 are alternately arranged along the first direction X. The second signal blocks 62 electrically connected to the first sub-auxiliary line 611 and the first signal blocks 715 located in the same signal block unit 62A are both electrically connected to the first main power line 714A, and the second signal blocks 62 spaced apart from the first sub-auxiliary line 611 and the first signal blocks 715 located in the same signal block unit 62A are both electrically connected to the third main power line 714C.

[0165] In the second auxiliary sub-line 612 and the adjacent second signal block group 62G, each second signal block 62 is spaced apart from the second auxiliary sub-line 612. A portion of the second signal blocks 62 and the first signal blocks 715 within the same signal block unit 62A are electrically connected to the third main power line 714C, while the remaining portion of the second signal blocks 62 and the first signal blocks 715 within the same signal block unit 62A are electrically connected to the first main power line 714A. The first signal blocks 715 electrically connected to the first main power line 714A and the first signal blocks 715 electrically connected to the third main power line 714C are arranged alternately along the first direction X. Two adjacent second signal blocks 62 along the second direction Y are electrically connected to the same main power line 714.

[0166] In the third auxiliary sub-line 613 and the adjacent second signal block group 62G, a portion of the second signal blocks 62 are electrically connected to the third auxiliary sub-line 613, while the remaining portion of the second signal blocks 62 are spaced apart from the third auxiliary sub-line 613. The plurality of second signal blocks 62 electrically connected to the third auxiliary sub-line 613 and the plurality of second signal blocks 62 spaced apart from the third auxiliary sub-line 613 are alternately arranged along the first direction X. The second signal blocks 62 electrically connected to the third auxiliary sub-line 613 and the first signal blocks 715 located in the same signal block unit 62A are both electrically connected to the third main power line 714C, and the second signal blocks 62 spaced apart from the third auxiliary sub-line 613 and the first signal blocks 715 located in the same signal block unit 62A are both electrically connected to the first main power line 714A.

[0167] FIG13 schematically shows an enlarged schematic diagram of a light-emitting device layer and a driving circuit layer in a display substrate according to some embodiments of the present disclosure, located in the B1 area in FIG1 .

[0168] According to some exemplary embodiments, referring to FIG. 13 , the display substrate further includes a driving circuit layer located on a side of the first electrode layer closer to the base substrate. The driving circuit layer includes a plurality of driving circuit columns 310. The plurality of driving circuit columns 310 include a plurality of first driving circuit columns 310A, a plurality of second driving circuit columns 310B, and a plurality of third driving circuit columns 310C. The first driving circuit columns 310A include a plurality of first pixel driving circuit units 311 arranged along a second direction Y, the second driving circuit columns 310B include a plurality of second pixel driving circuit units 312 arranged along the second direction Y, and the third driving circuit columns 310C include a plurality of third pixel driving circuit units 313 arranged along the second direction Y.

[0169] 4 and 13 , the first sub-power line 711 is electrically connected to each first pixel driving circuit unit 311 in the first driving circuit column 310A, the second sub-power line 712 is electrically connected to each second pixel driving circuit unit 312 in the second driving circuit column 310B, and the third sub-power line 713 is electrically connected to each third pixel driving circuit unit 313 in the third driving circuit column 310C.

[0170] 2 , 4 and 13 , the first sub-electrode portion 901 in the first light-emitting device 210 is electrically connected to the first sub-power line 711 through the first pixel driving circuit unit 311, the second sub-electrode portion 902 in the second light-emitting device 220 is electrically connected to the second sub-power line 712 through the second pixel driving circuit unit 312, and the third sub-electrode portion 903 in the third light-emitting device 230 is electrically connected to the third sub-power line 713 through the third pixel driving circuit unit 313.

[0171] According to some exemplary embodiments, referring to FIG. 2 and FIG. 12 , the display substrate further includes a plurality of data signal lines 72. The plurality of data signal lines 72 are located in a layer between the base substrate and the first electrode layer, for example, in the second conductive layer. The plurality of data signal lines 72 are arranged along a first direction X and extend along a second direction Y. The plurality of data signal lines 72 include a plurality of first data lines 721, a plurality of second data lines 722, and a plurality of third data lines 723. A first data line 721 is adjacent to a first sub-power line 711 along the first direction X, a second data line 722 is adjacent to a second sub-power line 712 along the first direction X, and a third data line 723 is adjacent to a third sub-power line 713 along the first direction X.

[0172] The first data line 721 is electrically connected to each first pixel driving circuit unit 311 in the first driving circuit column 310A to provide a first data signal to each first pixel driving circuit unit 311 in the column. The second data line 722 is electrically connected to each second pixel driving circuit unit 312 in the second driving circuit column 310B to provide a second data signal to each second pixel driving circuit unit 312 in the column. The third data line 723 is electrically connected to each third pixel driving circuit unit 313 in the third driving circuit column 310C to provide a third data signal to each third pixel driving circuit unit 313 in the column. The first sub-electrode portion 901 is electrically connected to the first data line 721 via the first pixel driving circuit unit 311, the second sub-electrode portion 902 is electrically connected to the second data line 722 via the second pixel driving circuit unit 312, and the third sub-electrode portion 903 is electrically connected to the third data line 723 via the third pixel driving circuit unit 313. That is, only one type of light-emitting device is connected to a data signal line 72. Specifically, the first data line 721 controls only the first light-emitting device 210, the second data line 722 controls only the second light-emitting device 220, and the third data line 723 controls only the third light-emitting device 230. Therefore, when displaying certain characteristic images, such as a solid red or blue image, the data signals on the corresponding data signal lines no longer need to jump, thereby reducing the power consumption of the display substrate.

[0173] According to some exemplary embodiments, referring to FIG. 2 and FIG. 13 , the first sub-electrode portion 901 includes a first sub-electrode main portion 901A and a first connecting line 901B. The first sub-electrode main portion 901A is electrically connected to the first pixel driving circuit unit 311 via the first connecting line 901B. The shape of the first sub-electrode main portion 901A is substantially the same as that of the first opening K1. For example, the shape of the first sub-electrode main portion 901A can be a rectangle with rounded corners. The width of the first sub-electrode main portion 901A is significantly greater than the width of the first connecting line 901B. The boundary between the first sub-electrode main portion 901A and the first connecting line 901B is the location where the width of the first sub-electrode portion 901 suddenly decreases, as indicated by the dotted line in FIG. 2 .

[0174] The second sub-electrode portion 902 includes a second sub-electrode main portion 902A and a second connecting line 902B. The second sub-electrode main portion 902A is electrically connected to the second pixel driving circuit unit 312 via the second connecting line 902B. The shape of the second sub-electrode main portion 902A is substantially the same as that of the second opening K2. For example, the shape of the second sub-electrode main portion 902A can be a rectangle with rounded corners. The width of the second sub-electrode main portion 902A is significantly greater than the width of the first connecting line 901B. The boundary between the second sub-electrode main portion 902A and the second connecting line 902B is the location where the width of the second sub-electrode portion 902 suddenly decreases, as indicated by the dotted line in FIG. 2 .

[0175] The third sub-electrode portion 903 includes a third sub-electrode main portion 903A and a third connecting line 903B. The third sub-electrode main portion 903A is electrically connected to the third pixel driving circuit unit 313 via the third connecting line 903B. The shape of the third sub-electrode main portion 903A is substantially the same as that of the third opening K3. For example, the shape of the third sub-electrode main portion 903A can be a rectangle with rounded corners. The width of the third sub-electrode main portion 903A is significantly greater than the width of the first connecting line 901B. The boundary between the third sub-electrode main portion 903A and the third connecting line 903B is the location where the width of the third sub-electrode portion 903 suddenly decreases, as indicated by the dotted line in FIG. 2 .

[0176] According to some exemplary embodiments, referring to FIG. 2 , the extension lengths of any two first connection lines 901B are substantially equal, so as to improve the display uniformity of each first light-emitting device.

[0177] According to some exemplary embodiments, referring to FIG. 2 , the extension lengths of any two second connection lines 902B are substantially equal, so as to improve the display uniformity of each second light-emitting device.

[0178] According to some exemplary embodiments, referring to FIG. 2 , the extension lengths of any two third connection lines 903B are substantially equal, so as to improve the display uniformity of each third light-emitting device.

[0179] It should be understood that "substantially equal extension lengths" means a deviation of ±10% between the extension lengths of the two. The pixel driving circuit unit includes multiple transistors, and the light emitting device is electrically connected to the pixel driving circuit unit in particular by the light emitting device being electrically connected to a specific transistor in the pixel driving circuit unit.

[0180] According to some exemplary embodiments, referring to FIG. 2 , the first electrode layer includes a plurality of first electrode groups 90G arranged along a first direction X. The first electrode group 90G includes a first electrode column 90A, two second electrode columns 90B, and a third electrode column 90C arranged along the first direction X. The first electrode column 90A is located to one side of the two second electrode columns 90B along the first direction X, and the third electrode column 90C is located between the two second electrode columns 90B. That is, as shown in FIG. 2 , the first electrode group 90G includes the first electrode column 90A, the second electrode column 90B, the third electrode column 90C, and the second electrode column 90B, arranged sequentially from left to right.

[0181] The first electrode array 90A includes a plurality of first sub-electrode portions 901 and a plurality of third sub-electrode portions 903 arranged alternately along the second direction Y. The second electrode array 90B includes a plurality of second sub-electrode portions 902 arranged along the second direction Y. The third electrode array 90C includes a plurality of third sub-electrode portions 903 and a plurality of first sub-electrode portions 901 arranged alternately along the second direction Y. The first sub-electrode portions 901 in the first electrode array 90A and the third sub-electrode portions 903 in the third electrode array 90C are located in the same row along the first direction X, and the third sub-electrode portions 903 in the first electrode array 90A and the first sub-electrode portions 901 in the third electrode array 90C are located in the same row along the first direction X.

[0182] 13 , the driving circuit layer includes a plurality of driving circuit groups 310G arranged along a first direction X. The driving circuit group 310G includes a first driving circuit column 310A, two second driving circuit columns 310B, and a third driving circuit column 310C arranged along the first direction X. The first driving circuit column 310A is located to one side of the two second driving circuit columns 310B along the first direction X, and the third driving circuit column 310C is located between the two second driving circuit columns 310B.

[0183] 2 and 13 , a first electrode group 90G is electrically connected to a drive circuit group 310G. In the electrically connected first electrode group 90G and drive circuit group 310G, the orthographic projection of the first electrode column 90A on the substrate partially overlaps with the orthographic projection of the first drive circuit column 310A on the substrate, the orthographic projection of the second electrode column 90B on the substrate partially overlaps with the orthographic projection of the second drive circuit column 310B on the substrate, and the orthographic projection of the third electrode column 90C on the substrate partially overlaps with the orthographic projection of the third drive circuit column 310C on the substrate.

[0184] 2 and 13 , in a first electrode group 90G and a driver circuit group 310G that are electrically connected, the plurality of first sub-electrode main bodies 901A in the first electrode group 90G are electrically connected to the plurality of first pixel driver circuit units 311 in the first driver circuit column 310A via the plurality of first connection lines 901B, thereby electrically connecting the first light-emitting device 210 to the first pixel driver circuit units 311. Specifically, the plurality of first sub-electrode main bodies 901A in the first electrode column 90A are electrically connected to the plurality of first pixel driver circuit units 311 in the first driver circuit column 310A via the plurality of first connection lines 901B, and the plurality of first sub-electrode main bodies 901A in the third electrode column 90C are electrically connected to the plurality of first pixel driver circuit units 311 in the first driver circuit column 310A via the plurality of first connection lines 901B.

[0185] The multiple second sub-electrode main bodies 902A in the first electrode group 90G are electrically connected to the multiple second pixel driving circuit units 312 in the second driving circuit column 310B through multiple second connecting lines 902B, thereby realizing the electrical connection between the second light-emitting device 220 and the second pixel driving circuit unit 312. Specifically, the second electrode column 90B located between the first electrode column 90A and the third electrode column 90C is electrically connected to the second drive electrode column 310B located between the first drive circuit column 310A and the third drive circuit column 310C, and the multiple second sub-electrode main bodies 902A in the second electrode column 90B are respectively electrically connected to the multiple second pixel drive circuit units 312 in the second drive circuit column 310B through multiple second connection lines 902B; in addition, the second electrode column 90B located on the side of the third electrode column 90C away from the first electrode column 90A is electrically connected to the second drive electrode column 310B located on the side of the third drive circuit column 310C away from the first drive circuit column 310A, and the multiple second sub-electrode main bodies 902A in the second electrode column 90B are respectively electrically connected to the multiple second pixel drive circuit units 312 in the second drive circuit column 310B through multiple second connection lines 902B.

[0186] The plurality of third sub-electrode main bodies 903A in the first electrode group 90G are electrically connected to the plurality of third pixel driving circuit units 313 in the third driving circuit column 310C via the plurality of third connecting wires 903B, thereby electrically connecting the third light-emitting device 230 to the third pixel driving circuit units 313. Specifically, the plurality of third sub-electrode main bodies 903A in the first electrode column 90A are electrically connected to the plurality of third pixel driving circuit units 313 in the third driving circuit column 310C via the plurality of third connecting wires 903B, and the plurality of third sub-electrode main bodies 903A in the third electrode column 90C are electrically connected to the plurality of third pixel driving circuit units 313 in the third driving circuit column 310C via the plurality of third connecting wires 903B.

[0187] According to some exemplary embodiments, in combination with Figure 2 and Figure 13, the first conductive layer also includes a plurality of first electrode connection portions 74, the first connection line 901B is electrically connected to the first pixel driving circuit unit 311 through the corresponding first electrode connection portion 74, the second connection line 902B is electrically connected to the second pixel driving circuit unit 312 through the corresponding first electrode connection portion 74, and the third connection line 903B is electrically connected to the third pixel driving circuit unit 313 through the corresponding first electrode connection portion 74.

[0188] According to some exemplary embodiments, with reference to FIG. 2 and FIG. 13 , in the electrically connected first electrode group 90G and the driving circuit group 310G:

[0189] The distance between the first sub-electrode main portion 901A in the first electrode column 90A and the corresponding first electrode connecting portion 74 is significantly smaller than the distance between the first sub-electrode main portion 901A in the third electrode column 90C and the corresponding first electrode connecting portion 74. In order to make the extension lengths of each first connecting line 901B roughly equal to each other, the first connecting line 901B in the first electrode column 90A needs to be wound to extend the extension length of the first connecting line 901B.

[0190] Specifically, in the third electrode column 90C, the first sub-electrode main body 901A is electrically connected to the corresponding first electrode connection portion 74 through the first connecting line 901B at one end close to the first electrode column 90A (the left end shown in Figure 13), and the corresponding first electrode connection portion 74 is connected to the third sub-electrode main body 903A in the first electrode column 90A, that is, the extension length of the first connecting line 901B is made as short as possible; in addition, in the first electrode column 90A, the first sub-electrode main body 901A is electrically connected to the adjacent first electrode connection portion 74 through the first connecting line 901B at one end along the second direction Y (the upper end shown in Figure 13), so that the extension length of the first connecting line 901B in the first electrode column 90A is approximately equal to the extension length of the first connecting line 901B in the third electrode column 90C. Of course, in the first electrode array 90A, the connection position between the first connection line 901B and the first sub-electrode main body 901A and the extension method of the first connection line 901B are set according to actual needs and are not particularly limited.

[0191] The distance between the third sub-electrode main portion 903A in the first electrode column 90A and the corresponding first electrode connecting portion 74 is significantly greater than the distance between the third sub-electrode main portion 903A in the third electrode column 90C and the corresponding first electrode connecting portion 74. In order to make the extension lengths of each third connecting line 903B roughly equal to each other, the third connecting line 903B in the first electrode column 90A needs to be wound to extend the extension length of the third connecting line 903B.

[0192] Specifically, in the first electrode column 90A, the end of the third sub-electrode main body 903A close to the third electrode column 90C (the right end shown in Figure 13) is electrically connected to the corresponding first electrode connection portion 74 through the third connection line 903B, and the first electrode connection portion 74 is located on the side of the first sub-electrode main body 901A in the third electrode column 90C away from the first electrode column 90A, that is, the extension length of the third connection line 903B is as short as possible; in addition, in the third electrode column 90C, the end of the third sub-electrode main body 903A close to the first electrode column 90A (the left end shown in Figure 13) is electrically connected to the adjacent first electrode connection portion 74 through the third connection line 903B, and the first electrode connection portion 74 is located on the side of the third sub-electrode main body 903A away from the first electrode column 90A, so that the extension length of the third connection line 903B in the first electrode column 90A is approximately equal to the extension length of the third connection line 903B in the third electrode column 90C. Of course, in the third electrode array 90C, the connection position between the third connection line 903B and the third sub-electrode main portion 903A and the extension method of the third connection line 903B are set according to actual needs and are not particularly limited.

[0193] Figure 14 is a schematic diagram of an equivalent circuit of a pixel driving circuit in a display substrate according to some exemplary embodiments of the present disclosure. In an exemplary embodiment, the pixel driving circuit may be a 3T1C, 4T1C, 5T1C, 5T2C, 6T1C, 7T1C, or 8T1C structure. As shown in Figure 12, the pixel driving circuit may include 8 transistors (a first transistor T1 to an eighth transistor T8) and a storage capacitor C, and the pixel driving circuit is electrically connected to 10 signal lines (a first scan signal line S1, a second scan signal line S2, a third scan signal line S3, a fourth scan signal line S4, a light emitting signal line EM, a first initial signal line INIT1, a second initial signal line INIT2, a third initial signal line INIT3, a data signal line DATA, and a first power line VDD).

[0194] In an exemplary embodiment, the pixel driving circuit may include a first node N1, a second node N2, a third node N3, and a fourth node N4. The first node N1 is electrically connected to the first electrode of the second transistor T2, the gate electrode of the third transistor T3, and the first end of the storage capacitor C, respectively. The second node N2 is electrically connected to the first electrode of the third transistor T3, the second electrode of the fourth transistor T4, the second electrode of the fifth transistor T5, and the second electrode of the eighth transistor T8, respectively. The third node N3 is electrically connected to the second electrode of the first transistor T1, the second electrode of the second transistor T2, the second electrode of the third transistor T3, and the first electrode of the sixth transistor T6, respectively. The fourth node N4 is electrically connected to the second electrode of the sixth transistor T6 and the second electrode of the seventh transistor T7, respectively. The fourth node N4 is also electrically connected to the anode of the light emitting device EL.

[0195] In an exemplary embodiment, a first end of the storage capacitor C is electrically connected to the first node N1 , and a second end of the storage capacitor C is electrically connected to the first power line VDD.

[0196] In an exemplary embodiment, the first transistor T1 may be referred to as a first initialization transistor. A gate electrode of the first transistor T1 is electrically connected to the third scan signal line S3, a first electrode of the first transistor T1 is electrically connected to the first initial signal line INIT1, and a second electrode of the first transistor T1 is electrically connected to the third node N3. The second transistor T2 may be referred to as a compensation transistor. A gate electrode of the second transistor T2 is electrically connected to the fourth scan signal line S4, a first electrode of the second transistor T2 is electrically connected to the first node N1, and a second electrode of the second transistor T2 is electrically connected to the third node N3. The third transistor T3 may be referred to as a driving transistor. A gate electrode of the third transistor T3 is electrically connected to the first node N1, that is, a gate electrode of the third transistor T3 is electrically connected to the first end of the storage capacitor C, a first electrode of the third transistor T3 is electrically connected to the second node N2, and a second electrode of the third transistor T3 is electrically connected to the third node N3. The fourth transistor T4 may be referred to as a data write transistor. A gate electrode of the fourth transistor T4 is electrically connected to the first scan signal line S1, a first electrode of the fourth transistor T4 is electrically connected to the data signal line DATA, and a second electrode of the fourth transistor T4 is electrically connected to the second node N2. The fifth transistor T5 can be referred to as a first emission control transistor. A gate electrode of the fifth transistor T5 is electrically connected to the emission signal line EM, a first electrode of the fifth transistor T5 is electrically connected to the first power supply line VDD, and a second electrode of the fifth transistor T5 is electrically connected to the second node N2. The sixth transistor T6 can be referred to as a second emission control transistor. A gate electrode of the sixth transistor T6 is electrically connected to the emission signal line EM, a first electrode of the sixth transistor T6 is electrically connected to the third node N3, and a second electrode of the sixth transistor T6 is electrically connected to the fourth node N4. The seventh transistor T7 can be referred to as a second initialization transistor. A gate electrode of the seventh transistor T7 is electrically connected to the second scan signal line S2, a first electrode of the seventh transistor T7 is electrically connected to the second initialization signal line INIT2, and a second electrode of the seventh transistor T7 is electrically connected to the fourth node N4. The eighth transistor T8 can be referred to as a third initialization transistor. A gate electrode of the eighth transistor T8 is electrically connected to the second scan signal line S2, a first electrode of the eighth transistor T8 is electrically connected to the third initialization signal line INIT3, and a second electrode of the eighth transistor T8 is electrically connected to the second node N2.

[0197] In an exemplary embodiment, the light-emitting device EL can be an OLED, including a stacked anode (first pole), an organic light-emitting layer and a cathode (second pole), or can be a QLED, including a stacked anode (first pole), a quantum dot light-emitting layer and a cathode (second pole).

[0198] In an exemplary embodiment, the first electrode of the light emitting device EL is electrically connected to the fourth node N4, the second electrode of the light emitting device EL is electrically connected to the second power line VSS, the signal of the second power line VSS is a continuously provided low level signal, and the signal of the first power line VDD is a continuously provided high level signal.

[0199] In an exemplary embodiment, the first transistor T1 to the eighth transistor T8 may be a P-type transistor or an N-type transistor. Using the same type of transistors in the pixel driving circuit can simplify the process flow, reduce the manufacturing difficulty of the display panel, and improve the product yield. In some possible implementations, the first transistor T1 to the eighth transistor T8 may include P-type transistors and N-type transistors.

[0200] In an exemplary embodiment, the first transistor T1 to the eighth transistor T8 may be low-temperature polysilicon transistors, or oxide transistors, or both low-temperature polysilicon transistors and metal oxide transistors. The active layer of the low-temperature polysilicon transistor is made of low-temperature polysilicon (LTPS), and the active layer of the metal oxide transistor is made of metal oxide semiconductor (Oxide). Low-temperature polysilicon transistors have advantages such as high mobility and fast charging, while oxide transistors have advantages such as low leakage current. Integrating low-temperature polysilicon transistors and metal oxide transistors on a display substrate to form a low-temperature polycrystalline oxide (LTPO) display substrate can leverage the advantages of both, enabling low-frequency driving, reducing power consumption, and improving display quality.

[0201] In an exemplary embodiment, the second transistor T2 may be a metal oxide transistor, and the first transistor T1 and the third transistor T3 to the eighth transistor T8 may be low temperature polysilicon transistors.

[0202] According to some exemplary embodiments, a display substrate includes a base substrate, and a blocking layer, an isolation layer, a second active layer, a first gate insulating layer, a first gate metal layer, a second gate insulating layer, a second gate metal layer, a third gate insulating layer, a first active layer, a fourth gate insulating layer, a third gate metal layer, an interlayer insulating layer, a first source-drain metal layer, a passivation layer, a first planarizing layer, a second source-drain metal layer, a second planarizing layer, a third source-drain metal layer, a third planarizing layer, a first electrode layer, a pixel defining layer, a spacer layer, a light-emitting layer, a second electrode layer, and an encapsulation layer, sequentially disposed on the base substrate in a direction away from the base substrate. The driving circuit layer may include the second active layer, the first gate metal layer, the second gate metal layer, the first active layer, the third gate metal layer, the first source-drain metal layer, the second source-drain metal layer, and the third source-drain metal layer, wherein the second source-drain metal layer is a second conductive layer, and the third source-drain metal layer is a first conductive layer.

[0203] 15A to 15I are plan views of some film layers in a display substrate located in a display area according to some exemplary embodiments of the present disclosure;

[0204] 15A schematically illustrates a blocking layer, FIG15B schematically illustrates a combination of a blocking layer and a second active layer, FIG15C schematically illustrates a combination of a blocking layer, a second active layer and a first gate metal layer, FIG15D schematically illustrates a combination of a blocking layer, a second active layer, a first gate metal layer and a second gate metal layer, FIG15E schematically illustrates a combination of a blocking layer, a second active layer, a first gate metal layer, a second gate metal layer, a first active layer and a third gate metal layer, FIG15F schematically illustrates a combination of a blocking layer, a second active layer, a first gate metal layer, a second gate metal layer, a first active layer, a third gate metal layer, an interlayer insulating layer and a first source / drain metal layer, and FIG15G schematically illustrates a blocking layer, a second active layer, a first gate metal layer, a second gate metal layer, a first active layer, a third gate metal layer, a first source / drain metal layer, and a first source / drain metal layer. 15H illustrates a combination of a blocking layer, a second active layer, a first gate metal layer, a second gate metal layer, a first active layer, a third gate metal layer, an interlayer insulating layer, the first source-drain metal layer, a passivation layer, a first flat layer and a second source-drain metal layer, and FIG15I illustrates a combination of a blocking layer, a second active layer, a first gate metal layer, a second gate metal layer, a first active layer, a third gate metal layer, an interlayer insulating layer, the first source-drain metal layer, a passivation layer, a first flat layer, the second source-drain metal layer, the third source-drain metal layer and the first electrode layer.

[0205] In an exemplary embodiment, referring to FIG. 15A , the shielding layer of each pixel driving circuit may include at least a first shielding connection line 91 , a second shielding connection line 92 , a third shielding connection line 93 , and a shielding electrode 94 .

[0206] In an exemplary embodiment, the shielding electrode 94 may be rectangular in shape, and the corners of the rectangle may be chamfered. The first shielding connection line 91 may be a straight line extending along the first direction X. The first shielding connection line 91 may be arranged on one side of the shielding electrode 94 in the first direction X and connected to the shielding electrode 94. The second shielding connection line 92 may be shaped like a zigzag extending along the second direction Y. The second shielding connection line 92 may be arranged on one side of the shielding electrode 94 in the second direction Y and connected to the shielding electrode 94. The third shielding connection line 93 may be shaped like a zigzag extending along the second direction Y. The third shielding connection line 93 may be arranged on the side of the shielding electrode 94 opposite to the second direction Y and connected to the shielding electrode 94.

[0207] In an exemplary embodiment, the first shielding connection line 91 of each pixel driving circuit is connected to the shielding electrode 94 of the adjacent pixel driving circuit in the first direction X, so that the shielding layers in one unit row are connected as a whole to form an interconnected integrated structure.

[0208] In an exemplary embodiment, the second shielding connection line 92 of each pixel driving circuit is connected to the third shielding connection line 93 of the adjacent pixel driving circuit in the second direction Y, so that the second shielding connection line 92, the third shielding connection line 93 and the shielding electrode 94 in a unit column are connected into one, forming an interconnected integrated structure.

[0209] In an exemplary embodiment, the shielding layers in the unit rows and unit columns are connected as one, which can ensure that the shielding layers in the display substrate have the same potential, which is beneficial to improving the uniformity of the panel, avoiding poor display of the display substrate, and ensuring the display effect of the display substrate.

[0210] In an exemplary embodiment, referring to FIG. 15B , the second active layer of each pixel driving circuit may include at least the first active portion 11 of the first transistor T1, the third active portion 13 of the third transistor T3 to the eighth active portion 18 of the eighth transistor T8, and the third active portion 13 to the seventh active portion 17 are an integrated structure connected to each other, and the first active portion 11 and the eighth active portion 18 are separately provided.

[0211] In an exemplary embodiment, an orthographic projection of the third active portion 13 on the base substrate at least partially overlaps with an orthographic projection of the shielding electrode 94 on the base substrate.

[0212] In the first direction X, the first active portion 11 and the sixth active portion 16 may be located on one side of the third active portion 13 in the present pixel driving circuit in the first direction X, and the fourth active portion 14 and the fifth active portion 15 may be located on a side of the third active portion 13 in the present pixel driving circuit in the opposite direction to the first direction X. In the second direction Y, the fourth active portion 14 may be located on a side of the third active portion 13 in the present pixel driving circuit in the opposite direction to the second direction Y, and the first active portion 11, the fifth active portion 15, the sixth active portion 16, the seventh active portion 17, and the eighth active portion 18 may be located on one side of the third active portion 13 in the present pixel driving circuit in the second direction Y.

[0213] In an exemplary embodiment, the third active portion 13 may have an inverted Ω shape, the first active portion 11, the fourth active portion 14, the fifth active portion 15, and the sixth active portion 16 may have an I shape, and the seventh active portion 17 and the eighth active portion 18 may have an L shape.

[0214] In an exemplary embodiment, the first active portion 11 and the third active portion 13 to the eighth active portion 18 may each include a first region, a second region, and a channel region located between the first and second regions. In an exemplary embodiment, the first region 13-1 of the third active portion may simultaneously serve as the second region 14-2 of the fourth active portion and the second region 15-2 of the fifth active portion, the second region 13-2 of the third active portion may serve as the first region 16-1 of the sixth active portion, and the second region 16-2 of the sixth active portion may serve as the second region 17-2 of the seventh active portion. The first region 11-1 of the first active portion, the second region 11-2 of the first active portion, the first region 14-1 of the fourth active portion, the first region 15-1 of the fifth active portion, the first region 17-1 of the seventh active portion, the first region 18-1 of the eighth active portion, and the second region 18-2 of the eighth active portion may be provided separately.

[0215] In an exemplary embodiment, the second active layer may be made of polycrystalline silicon (p-Si), meaning the third to seventh transistors are LTPS transistors. In an exemplary embodiment, patterning the first semiconductor film through a patterning process may include: first forming an amorphous silicon (a-Si) film on the first insulating film, performing a dehydrogenation treatment on the amorphous silicon film, and then crystallizing the dehydrogenated amorphous silicon film to form a polycrystalline silicon film. Subsequently, patterning the polycrystalline silicon film to form the second active layer.

[0216] In an exemplary embodiment, referring to FIG. 15C , the first gate metal layer of each pixel driving circuit includes at least a first scan signal line 21 , a second scan signal line 22 , a third scan signal line 23 , a light emitting signal line 24 and a first plate 25 of a storage capacitor.

[0217] In an exemplary embodiment, referring to FIG. 15C and FIG. 15B , the first electrode plate 25 may be rectangular, with chamfered corners. The orthographic projection of the first electrode plate 25 on the substrate at least partially overlaps the orthographic projection of the third active portion of the third transistor T3 on the substrate. In an exemplary embodiment, the first electrode plate 25 may serve as both a plate of the storage capacitor and a gate electrode of the third transistor T3.

[0218] In an exemplary embodiment, referring to Figures 15C and 15B, the shape of the first scan signal line 21 can be a zigzag shape with the main portion extending along the first direction X. The first scan signal line 21 can be located on the side of the first electrode 25 in the opposite direction of the second direction Y, and the area where the first scan signal line 21 overlaps with the fourth active portion can serve as the gate electrode of the fourth transistor T4.

[0219] In an exemplary embodiment, referring to Figures 15C and 15B, the shape of the second scan signal line 22 can be a zigzag shape with the main portion extending along the first direction X. The second scan signal line 22 can be located on one side of the first electrode 25 in the second direction Y. The area where the second scan signal line 22 overlaps with the seventh active portion can serve as the gate electrode of the seventh transistor T7, and the area where the second scan signal line 22 overlaps with the eighth active portion can serve as the gate electrode of the eighth transistor T8.

[0220] In an exemplary embodiment, referring to FIG. 15C and FIG. 15B , the shape of the third scan signal line 23 can be a zigzag shape in which the main portion extends along the first direction X. The third scan signal line 23 can be located on a side of the second scan signal line 22 away from the first electrode plate 25 , and the area where the third scan signal line 23 overlaps with the first active portion can serve as the gate electrode of the first transistor T1.

[0221] In an exemplary embodiment, referring to Figures 15C and 15B, the shape of the light-emitting signal line 24 can be a broken line with the main portion extending along the first direction X. The light-emitting signal line 24 can be located on the side of the second scanning signal line 22 close to the first electrode 25. The area where the light-emitting signal line 24 overlaps with the fifth active portion can serve as the gate electrode of the fifth transistor T5, and the area where the light-emitting signal line 24 overlaps with the sixth active portion can serve as the gate electrode of the sixth transistor T6.

[0222] In an exemplary embodiment, the first scanning signal line 21, the second scanning signal line 22, the third scanning signal line 23 and the light-emitting signal line 24 can be designed with non-equal widths, and the width is the dimension in the second direction Y, which not only facilitates the layout of the pixel structure, but also reduces the parasitic capacitance between the signal lines. The present disclosure does not limit this.

[0223] In an exemplary embodiment, after forming the first gate metal layer pattern, the first gate metal layer can be used as a shield to perform conductorization on the second active layer. The second active layer in the area shielded by the first gate metal layer forms the channel region of the first transistor T1 and the third transistor T3 to the eighth transistor T8, and the second active layer in the area not shielded by the first gate metal layer is conductorized, that is, the first region and the second region of the first transistor T1 and the third transistor T3 to the eighth transistor T8 are all conductorized.

[0224] In an exemplary embodiment, referring to FIG. 15D , the second gate metal layer of each pixel driving circuit includes at least a shielding line 31 and a second plate 32 of a storage capacitor.

[0225] In an exemplary embodiment, with reference to Figures 15C and 15D, the shape of the shielding line 31 can be a line shape in which the main portion extends along the first direction X. The shielding line 31 can be located between the first scanning signal line 21 and the first electrode 25. The shielding line 31 is configured as a shielding layer of the second transistor T2, shielding the channel region of the second transistor T2, ensuring the electrical performance of the oxide second transistor T2, and at the same time being configured as a bottom gate electrode of the second transistor T2.

[0226] In an exemplary embodiment, the shielding lines 31 may be designed with unequal widths, which not only facilitates the layout of the pixel structure but also reduces the parasitic capacitance between the signal lines.

[0227] In an exemplary embodiment, with reference to Figures 15C and 15D, the outline of the second plate 32 can be rectangular, the corners of the rectangle can be chamfered, the orthographic projection of the second plate 32 on the substrate at least partially overlaps with the orthographic projection of the first plate 25 on the substrate, the second plate 32 can serve as another plate of the storage capacitor, and the first plate 25 and the second plate 32 constitute the storage capacitor of the pixel driving circuit.

[0228] In an exemplary embodiment, referring to Figures 15C and 15D , an opening 33 is provided on the second electrode plate 32. Opening 33 can be rectangular and located in the middle of the second electrode plate 32, forming a ring-shaped structure. Opening 33 exposes the third insulating layer covering the first electrode plate 25, and the orthographic projection of the first electrode plate 25 on the base substrate includes the orthographic projection of opening 33 on the base substrate. In an exemplary embodiment, opening 33 is configured to accommodate a thirteenth via hole to be formed later. The thirteenth via hole is located within opening 33 and exposes the first electrode plate 25, allowing a first connecting electrode to be formed later to be connected to the first electrode plate 25.

[0229] In an exemplary embodiment, referring to FIG. 15E , the first active layer of each pixel driving circuit includes at least a second active portion 12 of a second transistor T2 .

[0230] In an exemplary embodiment, referring to FIG. 15E and FIG. 15D , the second active portion 12 may be in an “L” shape, and the orthographic projection of the second active layer 12 on the base substrate at least partially overlaps with the orthographic projection of the shielding line 31 on the base substrate.

[0231] In an exemplary embodiment, referring to Figures 15E and 15D, the first region 12-1 of the second active portion can be located on the side of the shielding line 31 away from the second electrode plate 32, and the second region 12-2 of the second active portion can be located on the side of the shielding line 31 close to the second electrode plate 32.

[0232] In an exemplary embodiment, the first active layer may be made of an oxide semiconductor material, that is, the eighth transistor T8 is an oxide transistor. For example, the second semiconductor film may be made of indium gallium zinc oxide (IGZO), which has higher electron mobility than amorphous silicon.

[0233] In an exemplary embodiment, referring to FIG. 15E , the third gate metal layer of each pixel driving circuit includes at least a first initial signal line 41 , a second initial signal line 42 , a third initial signal line 43 and a fourth scan signal line 44 .

[0234] In an exemplary embodiment, referring to Figures 15E and 15C, the shape of the first initial signal line 41 can be a broken line with the main portion extending along the first direction X. The first initial signal line 41 can be located between the third scanning signal line 23 and the light-emitting signal line 24. A first initial connection block 41-1 is provided on the first initial signal line 41 of each pixel driving circuit. The first initial connection block 41-1 is configured to be connected to the first area of ​​the first active portion through a seventh connection electrode formed subsequently.

[0235] In an exemplary embodiment, referring to Figures 15E and 15D, the shape of the second initial signal line 42 can be a broken line with the main portion extending along the first direction X. The second initial signal line 42 can be located on the side of the first initial signal line 41 away from the second electrode plate 32. A second initial connection block 42-1 is provided on the second initial signal line 42 of each pixel driving circuit. The second initial connection block 42-1 is configured to be connected to the first area of ​​the seventh active portion through the subsequently formed eighth connection electrode.

[0236] In an exemplary embodiment, referring to Figures 15E and 15D, the shape of the third initial signal line 43 can be a broken line with the main portion extending along the first direction X. The third initial signal line 43 can be located on the side of the first initial signal line 41 close to the second electrode 32. A third initial connection block 43-1 is provided on the third initial signal line 43 of each pixel driving circuit. The third initial connection block 43-1 is configured to be connected to the first area of ​​the eighth active portion through a ninth connection electrode formed subsequently.

[0237] In an exemplary embodiment, referring to Figures 15E, 15C and 15D, the shape of the fourth scan signal line 44 can be a line shape in which the main portion extends along the first direction X, the fourth scan signal line 44 can be located between the first scan signal line 21 and the first electrode 25, the orthographic projection of the fourth scan signal line 44 on the base substrate and the orthographic projection of the shielding line 31 on the base substrate at least partially overlap, and the area where the fourth scan signal line 44 overlaps with the second active portion can serve as the gate electrode of the second transistor T2.

[0238] In an exemplary embodiment, referring to Figures 15E and 15D, the fourth scan signal line 44 and the shielding line 31 can be connected to the same signal source, so that the shielding line 31 can serve as the bottom gate electrode of the second transistor T2, and the fourth scan signal line 44 can serve as the top gate electrode of the second transistor T2, forming a second transistor T2 with a top-gate and bottom-gate structure.

[0239] In an exemplary embodiment, referring to Figure 15F, a plurality of via holes are provided on the interlayer insulating layer, and the plurality of via holes of each pixel driving circuit include at least a first via hole V1, a second via hole V2, a third via hole V3, a fourth via hole V4, a fifth via hole V5, a sixth via hole V6, a seventh via hole V7, an eighth via hole V8, a ninth via hole V9, a tenth via hole V10, an eleventh via hole V11, a twelfth via hole V12, a thirteenth via hole V13, a fourteenth via hole V14, a fifteenth via hole V15, a sixteenth via hole V16 and a seventeenth via hole V17.

[0240] In an exemplary embodiment, referring to Figure 15F, the first source-drain metal layer of each pixel driving circuit includes at least: a first connection electrode 51, a second connection electrode 52, a third connection electrode 53, a fourth connection electrode 54, a fifth connection electrode 55, a sixth connection electrode 56, a seventh connection electrode 57, an eighth connection electrode 58 and a ninth connection electrode 59.

[0241] In an exemplary embodiment, referring to Figures 15F and 15C , the first connection electrode 51 may be shaped like a zigzag line with a main portion extending along the second direction Y. A first end of the first connection electrode 51 is connected to the first region of the second active portion via a third via hole V3. A second end of the first connection electrode 51 extends along the second direction Y and is connected to the first electrode plate 25 via a thirteenth via hole V13. In an exemplary embodiment, because the first electrode plate 25 also serves as the gate electrode of the third transistor T3, the first connection electrode 51 causes the first electrode of the second transistor T2, the gate electrode of the third transistor T3, and the first electrode plate 25 to have the same potential, forming a first node N1 of the pixel driving circuit.

[0242] In an exemplary embodiment, referring to FIG. 15F and FIG. 15B , the second connection electrode 52 may be in the shape of a strip with a main portion extending along the second direction Y. A first end of the second connection electrode 52 is connected to the second region of the first active portion via a second via V2. A second end of the second connection electrode 52, after extending along the second direction Y, is connected to the second region of the third active portion (also the first region of the sixth active portion) via a fifth via V5. A portion between the first and second ends of the second connection electrode 52 is connected to the second region of the second active portion via a fourth via V4. In an exemplary embodiment, the second connection electrode 52 causes the second electrodes of the first transistor T1, the second electrodes of the second transistor T2, the second electrodes of the third transistor T3, and the first electrode of the sixth transistor T6 to have the same potential, forming a third node N3 of the pixel driving circuit.

[0243] 15F and 15B , the third connection electrode 53 may be a block shape (e.g., a rectangle) and connected to the first region of the fourth active portion through the sixth via hole V6. The third connection electrode 53 is configured to connect to a subsequently formed third connection portion.

[0244] In an exemplary embodiment, referring to Figures 15F, 15B and 15D, the shape of the fourth connection electrode 54 can be a zigzag shape with the main portion extending along the second direction Y, the first end of the fourth connection electrode 54 is connected to the first area of ​​the fifth active portion through the seventh via V7, and the second end of the fourth connection electrode 54 extends in the opposite direction of the second direction Y and is connected to the second electrode plate 32 through the fourteenth via V14, thereby achieving the same potential as the first electrode of the fifth transistor T5 and the second electrode plate 32 of the storage capacitor in the pixel driving circuit.

[0245] In an exemplary embodiment, a power connection block 54 - 1 is provided on the fourth connection electrode 54 , and the power connection block 54 - 1 is configured to be connected to a fourth connection portion formed subsequently.

[0246] In an exemplary embodiment, referring to FIG. 15F and FIG. 15B , the fifth connection electrode 55 may be shaped like a zigzag line with a main portion extending along the second direction Y. A first end of the fifth connection electrode 55 is connected to the second region of the fifth active portion via an eighth via hole V8. A second end of the fifth connection electrode 55 extends along the second direction Y and is connected to the second region of the eighth active portion via a twelfth via hole V12. In an exemplary embodiment, because the second region of the fifth active portion serves as both the first region of the third active portion and the second region of the fourth active portion, the fifth connection electrode 55 causes the first electrode of the third transistor T3, the second electrode of the fourth transistor T4, the second electrode of the fifth transistor T5, and the second electrode of the eighth transistor T8 to have the same potential, forming a second node N2 of the pixel driving circuit.

[0247] In an exemplary embodiment, referring to FIG. 15F and FIG. 15B , the sixth connection electrode 56 may be in a block shape (e.g., a rectangular shape) and is connected to the second region of the sixth active portion (also the second region of the seventh active portion) through a ninth via hole V9. The sixth connection electrode 56 is configured to be connected to a second connection portion formed subsequently.

[0248] In an exemplary embodiment, referring to Figures 15F, 15E, and 15B, the seventh connection electrode 57 may be in the shape of a bar with a main portion extending along the second direction Y. A first end of the seventh connection electrode 57 is connected to the first region of the first active portion via a first via V1, and a second end of the seventh connection electrode 57 is connected to the first initial connection block 41-1 via a fifteenth via V15. Thus, the seventh connection electrode 57 writes the first initial signal transmitted by the first initial signal line 41 into the first electrode of the first transistor T1.

[0249] In an exemplary embodiment, referring to Figures 15F, 15E, and 15B, the eighth connection electrode 58 may be in the shape of a strip with a main portion extending along the second direction Y. A first end of the eighth connection electrode 58 is connected to the first region of the seventh active portion via a tenth via hole V10, and a second end of the eighth connection electrode 58 is connected to the second initial connection block 42-1 via a sixteenth via hole V16. In an exemplary embodiment, the eighth connection electrode 58 may serve as the first electrode of the seventh transistor T7. Since the second initial connection block 42-1 is connected to the second initial signal line 42, the eighth connection electrode 58 causes the second initial signal transmitted by the second initial signal line 42 to be written into the first electrode of the seventh transistor T7.

[0250] In an exemplary embodiment, referring to Figures 15F, 15E, and 15B, the ninth connection electrode 59 may be shaped like a zigzag line with a main portion extending along the second direction Y. A first end of the eighth connection electrode 58 is connected to the first region of the eighth active portion via an eleventh via hole V11, and a second end of the eighth connection electrode 58 is connected to the third initial connection block 43-1 via a seventeenth via hole V17. In an exemplary embodiment, the ninth connection electrode 59 may serve as the first electrode of the eighth transistor T8. Since the third initial connection block 43-1 is connected to the third initial signal line 43, the ninth connection electrode 59 allows the third initial signal transmitted by the third initial signal line 43 to be written into the first electrode of the eighth transistor T8.

[0251] In an exemplary embodiment, referring to FIG. 15G , the interlayer insulating layer and the first planar layer have a plurality of via holes, and the plurality of via holes in each pixel driving circuit include at least an eighteenth via hole V18 , a nineteenth via hole V19 , and a twentieth via hole V20 .

[0252] In an exemplary embodiment, referring to FIG. 15G , the second source-drain metal layer of each pixel driving circuit includes at least a first auxiliary signal line 61 , a second signal block 62 , a second transfer signal line 63 , a first connection portion 64 , a second connection portion 65 and a third connection portion 66 .

[0253] In an exemplary embodiment, referring to Figures 15G and 15F, the shape of the first connection portion 64 can be a line shape in which the main portion extends along the first direction X, the fourth connection portion 64 is connected to the power connection block 54-1 through the nineteenth via V19, and the fourth connection portion 64 is configured to be connected to the first power signal line formed subsequently.

[0254] In an exemplary embodiment, referring to Figures 15G and 15F, the shape of the second connection portion 65 can be a strip shape in which the main portion extends along the second direction Y, the second connection portion 65 is connected to the sixth connection electrode 56 through the twentieth via V20, and the second connection portion 65 is configured to be connected to the first electrode connection portion formed subsequently.

[0255] In an exemplary embodiment, referring to Figures 15G and 15F, the shape of the third connection portion 66 can be a strip shape with the main portion extending along the second direction Y. The third connection portion 66 is connected to the third connection electrode 53 through the eighteenth via hole V18, and the third connection portion 66 is configured to be connected to a data signal line formed subsequently.

[0256] In an exemplary embodiment, referring to Figure 15G, the shape of the first auxiliary signal line 61 can be a line shape in which the main part extends along the first direction X, the first auxiliary signal line 61 is connected to the corresponding first connection portion 64, and the first auxiliary signal line 61 is connected to the first power signal line formed subsequently through the first connection portion 64.

[0257] In an exemplary embodiment, referring to FIG. 15G , the second signal block 62 may be rectangular in shape, connected to the corresponding first connection portion 64 , and connected to a subsequently formed first power signal line through the first connection portion 64 .

[0258] 15G , the second transfer signal line 63 may be in the shape of a line having a main portion extending along the first direction X. The second transfer signal line 63 may have a plurality of breaks, and the second transfer signal line 63 includes a plurality of spaced second transfer signal segments.

[0259] In an exemplary embodiment, referring to FIG. 15H , the third source-drain metal layer of each pixel driving circuit includes at least a first power signal line 71 , a first signal block 715 , a data signal line 72 , a first transfer signal line 73 and a first electrode connection portion 74 .

[0260] In an exemplary embodiment, referring to Figures 15H and 15G , the first power signal line 71 may be shaped like a zigzag line with a main portion extending along the second direction Y. The first power signal line 71 is connected to the first connection portion 64. Since the first connection portion 64 is connected to the fourth connection electrode 54, and the fourth connection electrode 54 is respectively connected to the first region of the fifth active portion and the second plate of the storage capacitor, the first power signal line 71 writes the first power signal to the fifth transistor and the second plate of the storage capacitor.

[0261] In an exemplary embodiment, referring to Figure 15H, the first power signal line 71 may include a first signal block 715, which may be located on one side of the first direction X of the first power signal line 71 or on the side opposite to the first direction X. The orthographic projection of the first signal block 715 on the substrate at least partially overlaps with the orthographic projection of the second signal block 62 on the substrate, and the first signal block 715 is configured to improve the planarization structure of the first electrode portion.

[0262] In an exemplary embodiment, referring to FIG15H , the first power signal line 71 is connected to the first auxiliary signal line 61 , thereby achieving mutual connection between the first auxiliary signal line 61 of the main body extending along the first direction X and the first power signal line 71 of the main body extending along the second direction Y, so that the first power signal line 71 and the first auxiliary signal line 61 form a grid connection structure for transmitting the first power signal on the display substrate, which can not only effectively reduce the resistance of the first power signal line 71 and reduce the voltage drop of the first power signal, but also effectively improve the uniformity of the first power signal in the display substrate, effectively improve the display uniformity, and improve the display quality and display quality.

[0263] In an exemplary embodiment, referring to FIG. 15H , the data signal line 72 may be in the shape of a line having a main portion extending along the second direction Y. The data signal line 72 is connected to the third connection portion 66. Since the third connection portion 66 is also connected to the third connection electrode 53, and the third connection electrode 53 is connected to the first region of the fourth active portion, the data signal line 72 is connected to the first electrode of the fourth transistor T4. Thus, the data signal line 72 can write a data signal to the first electrode of the fourth transistor T4.

[0264] 15H , the third transfer signal line 73 may be in the shape of a line with a main portion extending along the second direction Y. The third transfer signal line 73 may have a plurality of breaks, and the third transfer signal line 73 includes a plurality of spaced third transfer signal segments.

[0265] In an exemplary embodiment, referring to Figures 15H and 15G , the first electrode connecting portion 74 may be in a block shape (e.g., a rectangle), and is connected to the third connecting portion 65. The first electrode connecting portion 74 is configured to be connected to a subsequently formed first electrode portion. Since the third connecting portion 65 is also connected to the sixth connecting electrode 56, and the sixth connecting electrode 56 is connected to the second region of the sixth active portion and the second region of the seventh active portion, the subsequently formed first electrode portion can be connected to the second electrode of the sixth transistor T6 and the second electrode of the seventh transistor T7, allowing the pixel driving circuit to drive the light-emitting device to emit light.

[0266] 15I , the first electrode layer includes a plurality of first electrode portions 90 . Referring to FIG. 15H , the first electrode portion 90 includes a first electrode body portion and a connection line, one end of the connection line being connected to the first electrode body portion and the other end being connected to the first electrode connection portion 74 .

[0267] In an exemplary embodiment, the first electrode layer may have a single-layer structure, such as indium tin oxide (ITO) or indium zinc oxide (IZO), or may have a multi-layer composite structure, such as ITO / Ag / ITO.

[0268] In an exemplary embodiment, the substrate substrate may be a flexible substrate substrate, or may be a rigid substrate substrate. The rigid substrate substrate may include, but is not limited to, one or more of glass and quartz, and the flexible substrate may be, but is not limited to, one or more of polyethylene terephthalate, polyethylene terephthalate, polyetheretherketone, polystyrene, polycarbonate, polyarylate, polyarylate, polyimide, polyvinyl chloride, polyethylene, and textile fiber. In an exemplary embodiment, the flexible substrate substrate may include a first flexible material layer, a first inorganic material layer, a semiconductor layer, a second flexible material layer, and a second inorganic material layer stacked. The materials of the first and second flexible material layers may be polyimide (PI), polyethylene terephthalate (PET), or a surface-treated polymer soft film, and the materials of the first and second inorganic material layers may be silicon nitride (SiNx) or silicon oxide (SiOx), etc., to improve the water and oxygen resistance of the substrate substrate. The first and second inorganic material layers are also called barrier layers, and the material of the semiconductor layer may be amorphous silicon (a-Si).

[0269] In an exemplary embodiment, the first gate metal layer, the second gate metal layer, the third gate metal layer, the first source / drain metal layer, the second source / drain metal layer, and the third source / drain metal layer may be made of metal materials such as any one or more of silver (Ag), copper (Cu), aluminum (Al), and molybdenum (Mo), or alloys of the above metals, such as aluminum-neodymium alloy (AlNd) or molybdenum-niobium alloy (MoNb), and may be single-layer structures or multi-layer composite structures, such as Mo / Cu / Mo. The isolation layer, the first gate insulating layer, the second gate insulating layer, the third gate insulating layer, the fourth gate insulating layer, the interlayer insulating layer, and the passivation layer may be made of any one or more of silicon oxide (SiOx), silicon nitride (SiNx), and silicon oxynitride (SiON), and may be single-layer, multi-layer, or composite layers. The first planarization layer, the second planarization layer, and the third planarization layer may be made of organic materials, such as resin.

[0270] At least some embodiments of the present disclosure further provide a display device. The display device includes a display substrate as described above. The display device may include any device or product having a display function. For example, the display device may be a smart phone, a mobile phone, an e-book reader, a desktop computer (PC), a laptop PC, a netbook PC, a personal digital assistant (PDA), a portable multimedia player (PMP), a digital audio player, a mobile medical device, a camera, a wearable device (such as a head-mounted device, an electronic clothing, an electronic bracelet, an electronic necklace, an electronic accessory, an electronic tattoo, or a smart watch), a television, etc.

[0271] It should be understood that the display device according to the embodiment of the present disclosure has all the features and advantages of the display substrate described above. For details, please refer to the above description and will not be repeated here. Although some embodiments of the overall technical concept of the present disclosure have been shown and described, those skilled in the art will understand that changes can be made to these embodiments without departing from the principles and spirit of the overall technical concept. The scope of the present disclosure is defined by the claims and their equivalents.

Claims

1. A display substrate, wherein: The display substrate comprises: substrate; a first conductive layer located on the base substrate, the first conductive layer comprising a plurality of first power signal lines arranged along a first direction and extending along a second direction, the first direction intersecting the second direction; a first electrode layer, located on a side of the first conductive layer away from the base substrate, the first electrode layer comprising a plurality of first electrode portions; and a pixel defining layer, located on a side of the first electrode layer away from the base substrate, and having a plurality of openings, wherein each opening exposes a portion of the first electrode portion; The plurality of first power signal lines include a plurality of first power signal line groups arranged along the first direction, one first power signal line group includes two adjacent first power signal lines, in each first power signal line group, the two first power signal lines are spaced apart along the first direction, and a signal transmitted by one first power signal line is different from a signal transmitted by another first power signal line; and A minimum distance between two first power signal lines along the first direction is smaller than a size of the opening along the first direction.

2. The display substrate according to claim 1, wherein The first power signal line group includes two main power lines and a plurality of first signal blocks located between the two main power lines, wherein the plurality of first signal blocks are arranged at intervals along the second direction; Among them, any one of the first signal blocks is directly connected to one of the main power lines and is spaced apart from another of the main power lines along the first direction, and the distance between the first signal block and the spaced main power lines along the first direction is smaller than the size of the opening along the first direction.

3. The display substrate according to claim 2, wherein: In the first power signal line group, each of the first signal blocks is directly connected to the same main power line.

4. The display substrate according to claim 2, wherein: In the first power signal line group, a portion of the first signal blocks are directly connected to one of the main power lines, and the remaining portion of the first signal blocks are directly connected to another of the main power lines.

5. The display substrate according to claim 2, wherein: The plurality of first power signal lines include a plurality of first sub-power lines, a plurality of second sub-power lines, and a plurality of third sub-power lines, wherein the first sub-power lines are used to transmit a first signal, the second sub-power lines are used to transmit a second signal, and the third sub-power lines are used to transmit a third signal, and any two of the first signal, the second signal, and the third signal are different from each other; and The multiple first electrode parts include multiple first sub-electrode parts, multiple second sub-electrode parts and multiple third sub-electrode parts, the first sub-electrode part is electrically connected to the first sub-power line, the second sub-electrode part is electrically connected to the second sub-power line, and the third sub-electrode part is electrically connected to the third sub-power line. The display substrate according to claim 5 , wherein: The plurality of first power signal lines include a plurality of first power signal units arranged along the first direction; The first power signal unit includes a first sub-power line, two second sub-power lines and a third sub-power line, the first sub-power line is located on one side of the two second sub-power lines along the first direction, and the third sub-power line is located between the two second sub-power lines.

7. The display substrate according to claim 6, wherein: In the first power signal unit, the first sub-power line and the adjacent second sub-power line include a first main power line, a second main power line, and a plurality of first signal blocks located between the first main power line and the second main power line, a portion of the first signal blocks are directly connected to the first main power line, and a remaining portion of the first signal blocks are directly connected to the second main power line, and the plurality of first signal blocks connected to the first main power line and the plurality of first signal blocks connected to the second main power line are alternately arranged along the second direction; In the first power signal unit, the third sub-power line and the adjacent second sub-power line have a third main power line, a second main power line, and a plurality of first signal blocks located between the third main power line and the second main power line, a portion of the first signal blocks are directly connected to the third main power line, and the remaining portion of the first signal blocks are directly connected to the second main power line, and the plurality of first signal blocks connected to the third main power line and the plurality of first signal blocks connected to the second main power line are alternately arranged along the second direction.

8. The display substrate according to claim 6, wherein: In the first power signal unit, the first sub-power line and the adjacent second sub-power line have a first main power line, a second main power line, and a plurality of first signal blocks located between the first main power line and the second main power line, and each of the first signal blocks is directly connected to the first main power line; and In the first power signal unit, the third sub-power line and the adjacent second sub-power line have a third main power line, a second main power line and a plurality of first signal blocks located between the third main power line and the second main power line, and each first signal block is directly connected to the third main power line.

9. The display substrate according to claim 5 or 6, wherein: The display substrate further includes a second conductive layer located on a side of the first conductive layer close to the base substrate, the second conductive layer including a plurality of first auxiliary signal lines, the plurality of first auxiliary signal lines being arranged along the second direction and extending along the first direction; Among them, the multiple first auxiliary signal lines include multiple first sub-auxiliary lines, multiple second sub-auxiliary lines and multiple third sub-auxiliary lines, the first sub-auxiliary lines are electrically connected to the multiple first sub-power lines, the second sub-auxiliary lines are electrically connected to the multiple second sub-power lines, and the third sub-auxiliary lines are electrically connected to the multiple third sub-power lines.

10. The display substrate according to claim 9, wherein: The second conductive layer further includes a plurality of second signal blocks, wherein one second signal block and one first signal block form a signal block unit; In the signal block unit, the orthographic projection of the second signal block on the base substrate at least partially overlaps with the orthographic projection of the first signal block on the base substrate, and the second signal block and the first signal block are electrically connected to the same main power line.

11. The display substrate according to claim 10, wherein: The display substrate further comprises a first active layer located on a side of the second conductive layer close to the display substrate, wherein the material of the first active layer comprises a metal oxide semiconductor material; wherein the orthographic projection of the first active layer on the base substrate at least partially overlaps with the orthographic projection of the first signal block on the base substrate; and / or An orthographic projection of the first active layer on the base substrate at least partially overlaps with an orthographic projection of the second signal block on the base substrate.

12. The display substrate according to claim 10 or 11, wherein: The orthographic projection of the second signal block on the base substrate covers the orthographic projection of the first signal block on the base substrate.

13. The display substrate according to any one of claims 10 to 12, wherein: The plurality of first auxiliary signal lines include a plurality of first auxiliary signal units arranged along the second direction; The first auxiliary signal unit includes a first sub-auxiliary line, two second sub-auxiliary lines and a third sub-auxiliary line. The first sub-auxiliary line is located on one side of the two second sub-auxiliary lines along the second direction, and the third sub-auxiliary line is located between the two second sub-auxiliary lines.

14. The display substrate according to claim 13, wherein: The plurality of second signal blocks include a plurality of second signal block groups arranged along the second direction, the second signal block groups include a plurality of second signal blocks arranged along the first direction, and one second signal block group is adjacent to one first auxiliary signal line along the second direction; In a group of the first auxiliary sub-line and the adjacent second signal blocks, a portion of the second signal blocks is electrically connected to the first auxiliary sub-line, and a remaining portion of the second signal blocks is spaced apart from the first auxiliary sub-line, and a plurality of the second signal blocks electrically connected to the first auxiliary sub-line and a plurality of the second signal blocks spaced apart from the first auxiliary sub-line are alternately arranged along the first direction; In the second auxiliary sub-line and the adjacent second signal block group, each second signal block is electrically connected to the second auxiliary sub-line; In the third sub-auxiliary line and the adjacent second signal block group, a portion of the second signal blocks is electrically connected to the third sub-auxiliary line, and the remaining portion of the second signal blocks is spaced apart from the third sub-auxiliary line, and a plurality of second signal blocks electrically connected to the third sub-auxiliary line and a plurality of second signal blocks spaced apart from the third sub-auxiliary line are alternately arranged along the first direction.

15. The display substrate according to claim 13, wherein: The plurality of second signal blocks include a plurality of second signal block groups arranged along the second direction, the second signal block groups include a plurality of second signal blocks arranged along the first direction, and the plurality of second signal block groups are respectively located on one side of the plurality of first auxiliary signal lines along the second direction; In the group of the first auxiliary sub-line and the adjacent second signal blocks, a portion of the second signal blocks is electrically connected to the first auxiliary sub-line, and the remaining portion of the second signal blocks is spaced apart from the first auxiliary sub-line. A plurality of second signal blocks electrically connected to the first sub-auxiliary line and a plurality of second signal blocks spaced apart from the first sub-auxiliary line are alternately arranged along the first direction; In the second auxiliary sub-line and the adjacent second signal block group, each second signal block is spaced apart from the second auxiliary sub-line; In the third sub-auxiliary line and the adjacent second signal block group, a portion of the second signal blocks is electrically connected to the third sub-auxiliary line, and the remaining portion of the second signal blocks is spaced apart from the third sub-auxiliary line, and a plurality of second signal blocks electrically connected to the third sub-auxiliary line and a plurality of second signal blocks spaced apart from the third sub-auxiliary line are alternately arranged along the first direction.

16. The display substrate according to any one of claims 5 to 15, wherein: The display substrate further comprises a driving circuit layer located on a side of the first electrode layer close to the base substrate, the driving circuit layer comprising a plurality of driving circuit columns, the plurality of driving circuit columns comprising a plurality of first driving circuit columns, a plurality of second driving circuit columns and a plurality of third driving circuit columns; The first driving circuit column includes a plurality of first pixel driving circuit units arranged along the second direction, the second driving circuit column includes a plurality of second pixel driving circuit units arranged along the second direction, and the third driving circuit column includes a plurality of third pixel driving circuit units arranged along the second direction; The first sub power line is electrically connected to each of the first pixel driving circuit units in the first driving circuit column, the second sub power line is electrically connected to each of the second pixel driving circuit units in the second driving circuit column, and the third sub power line is electrically connected to each of the third pixel driving circuit units in the third driving circuit column; and The first sub-electrode portion is electrically connected to the first sub-power line through the first pixel driving circuit unit, the second sub-electrode portion is electrically connected to the second sub-power line through the second pixel driving circuit unit, and the third sub-electrode portion is electrically connected to the third sub-power line through the third pixel driving circuit unit.

17. The display substrate according to claim 16, wherein: The display substrate further includes a plurality of data signal lines, wherein a layer where the plurality of data signal lines are located is located between the base substrate and the first electrode layer, the plurality of data signal lines are arranged along the first direction and extend along the second direction, and the plurality of data signal lines include a plurality of first data lines, a plurality of second data lines, and a plurality of third data lines; The first data line is electrically connected to each of the first pixel driving circuit units in the first driving circuit column, and the second data line is electrically connected to each of the second pixel driving circuit units in the second driving circuit column. The third data line is electrically connected to each of the third pixel driving circuit units in the third driving circuit column; and The first sub-electrode portion is electrically connected to the first data line through the first pixel driving circuit unit, the second sub-electrode portion is electrically connected to the second data line through the second pixel driving circuit unit, and the third sub-electrode portion is electrically connected to the third data line through the third pixel driving circuit unit.

18. The display substrate according to claim 16 or 17, wherein: The first sub-electrode portion includes a first sub-electrode main portion and a first connecting line, and the first sub-electrode main portion is electrically connected to the first pixel driving circuit unit through the first connecting line; The second sub-electrode portion includes a second sub-electrode main portion and a second connecting line, and the second sub-electrode main portion is electrically connected to the second pixel driving circuit unit through the second connecting line; and The third sub-electrode portion includes a third sub-electrode main portion and a third connecting line, and the third sub-electrode main portion is electrically connected to the third pixel driving circuit unit through the third connecting line; Wherein, the extension lengths of any two of the first connecting lines are substantially equal; and / or The extension lengths of any two of the second connecting lines are substantially equal; and / or The extension lengths of any two of the third connecting lines are substantially equal.

19. The display substrate according to claim 18, wherein: The first electrode layer includes a plurality of first electrode groups arranged along a first direction, the first electrode groups including a first electrode column, two second electrode columns, and a third electrode column arranged along the first direction, the first electrode column being located on one side of the two second electrode columns along the first direction, and the third electrode column being located between the two second electrode columns; The first electrode array includes a plurality of the first sub-electrode portions and a plurality of the third sub-electrode portions arranged alternately along the second direction, the second electrode array includes a plurality of the second sub-electrode portions arranged along the second direction, and the third electrode array includes a plurality of the third sub-electrode portions and a plurality of the first sub-electrode portions arranged alternately along the second direction; The driving circuit layer includes a plurality of driving circuit groups arranged along the first direction, the driving circuit groups including one first driving circuit column, two second driving circuit columns, and one third driving circuit column arranged along the first direction, the first driving circuit column being located on one side of the two second driving circuit columns along the first direction, and the third driving circuit column being located between the two second driving circuit columns; One of the first electrode groups is electrically connected to one of the drive circuit groups. In the drive circuit group, the orthographic projection of the first electrode column on the base substrate partially overlaps with the orthographic projection of the first drive circuit column on the base substrate, the orthographic projection of the second electrode column on the base substrate partially overlaps with the orthographic projection of the second drive circuit column on the base substrate, and the orthographic projection of the third electrode column on the base substrate partially overlaps with the orthographic projection of the third drive circuit column on the base substrate; as well as The multiple first sub-electrode main bodies in the first electrode group are electrically connected to the multiple first pixel driving circuit units in the first driving circuit column through the multiple first connecting lines, the multiple second sub-electrode main bodies in the first electrode group are electrically connected to the multiple second pixel driving circuit units in the second driving circuit column through the multiple second connecting lines, and the multiple third sub-electrode main bodies in the first electrode group are electrically connected to the multiple third pixel driving circuit units in the third driving circuit column through the multiple third connecting lines.

20. The display substrate according to claim 19, wherein In the electrically connected first electrode group and the driving circuit group: In the first electrode column, one end of the first sub-electrode main portion along the second direction is electrically connected to the first pixel driving circuit unit in the first driving circuit column through the first connecting line, and one end of the third sub-electrode main portion close to the third electrode column is electrically connected to the third pixel driving circuit unit in the third driving circuit column through the third connecting line; and / or In the third electrode column, one end of the first sub-electrode main body close to the first electrode column is electrically connected to the first pixel driving circuit unit in the first driving circuit column through the first connecting line, and one end of the third sub-electrode main body close to the first electrode column is electrically connected to the third pixel driving circuit unit in the third driving circuit column through the third connecting line.

21. The display substrate according to any one of claims 5 to 20, wherein: The orthographic projection of the second sub-electrode portion on the base substrate at least partially overlaps with the orthographic projection of the first signal block on the base substrate.

22. The display substrate according to any one of claims 5 to 20, wherein: The plurality of openings include a plurality of first openings, a plurality of second openings, and a plurality of third openings, wherein the first openings expose a portion of the first sub-electrode portion, the second openings expose a portion of the second sub-electrode portion, and the third openings expose a portion of the third sub-electrode portion; The orthographic projection of the first opening on the substrate partially overlaps with the orthographic projections of two adjacent first power signal lines on the substrate, the two first power signal lines are located on either side of a geometric center of the first opening, and the geometric center of the orthographic projection of the first opening on the substrate is approximately equidistant from the orthographic projections of the two adjacent first power signal lines on the substrate. and / or The orthographic projection of the third opening on the substrate partially overlaps with the orthographic projections of two adjacent first power signal lines on the substrate, the two first power signal lines are located on both sides of the geometric center of the third opening, and the geometric center of the orthographic projection of the third opening on the substrate is approximately equidistant from the orthographic projections of the two adjacent first power signal lines on the substrate.

23. A display device, wherein: The display device comprises the display substrate according to any one of claims 1 to 22.

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