Operational amplifier circuit and operating method thereof

Abstract

An operational amplifier circuit and an operating method thereof. The operational amplifier circuit comprises: a first operational amplifier, which is used for outputting a regulating signal on the basis of a first signal, wherein the first operational amplifier comprises a chopper circuit, the chopper circuit being used for regulating an offset voltage and noise of the regulating signal; and a second operational amplifier, which is used for regulating an offset voltage and noise of the first signal on the basis of the regulating signal, in order to output a second signal. Thus, a second operational amplifier is integrated into an operational amplifier circuit, the second operational amplifier being used for outputting a regulating signal to a first operational amplifier, so as to regulate an offset voltage and noise of a first signal.

Description

Operational amplifier circuit and operating method thereof

[0001] This application claims priority to the Chinese patent application filed with the China Patent Office on March 5, 2024, with application number 202410251856.X and invention name “Operational Amplifier Circuit and Working Method Thereof”, the entire contents of which are incorporated by reference into this application. Technical Field

[0002] The present application relates to the field of operational amplifiers, and in particular to an operational amplifier circuit and an operating method thereof. Background Art

[0003] Operational amplifiers (OPA) are devices that amplify the voltage or power of input signals and are widely used in communications, PCs, consumer electronics, automotive, and industrial applications. To suppress common-mode signals, differential circuits are often used to implement the amplifier function. For differential circuits, including differential buffers, differential amplifiers, and push-pull differential amplifiers, it may be necessary to adjust the common-mode differential voltage to achieve optimal performance or meet overall circuit requirements.

[0004] The existence of offset voltage and 1 / f noise in current operational amplifier circuits affects the performance of the operational amplifier circuits.

[0005] Summary of the Invention

[0006] The technical problem solved by the present application is to provide an operational amplifier circuit and a working method thereof, so as to improve the performance of the operational amplifier circuit.

[0007] To solve the above technical problems, an embodiment of the present application provides an operational amplifier circuit, including: a first operational amplifier, used to output an adjustment signal according to a first signal, the first operational amplifier including a chopping circuit, the chopping circuit being used to adjust the offset voltage and noise of the adjustment signal; a second operational amplifier, used to adjust the offset voltage and noise of the first signal according to the adjustment signal to output a second signal.

[0008] Optionally, the first operational amplifier includes: a first gain stage, wherein the first input end of the first gain stage is used to obtain the first signal; a second gain stage, wherein the input end of the second gain stage is connected to the output end of the first gain stage; and a first common-mode feedback unit, wherein the input end of the first common-mode feedback unit is connected to the output end of the second gain stage, and the output end of the first common-mode feedback unit is connected to the output end of the first gain stage.

[0009] Optionally, the second operational amplifier includes: a folded cascode amplifier unit, the input end of the folded cascode amplifier unit being connected to the first input end of the first gain stage; an output stage, the input end of the output stage being connected to the output end of the folded cascode amplifier unit; the output end of the output stage being connected to the second input end of the first gain stage; and a second common-mode feedback unit, the input end of the second common-mode feedback unit being connected to the output end of the output stage, and the output end of the second common-mode feedback unit being connected to the output end of the folded cascode amplifier unit.

[0010] Optionally, the operational amplifier circuit further includes: a first resistor, a second resistor, a third resistor, and a fourth resistor, for controlling the amplification factor of the first operational amplifier.

[0011] Optionally, the operational amplifier circuit further includes a first signal input terminal and a second signal input terminal; the first gain stage includes a first NMOS tube, a second NMOS tube, a third NMOS tube, a second PMOS tube, a third PMOS tube, a fourth PMOS tube and a fifth PMOS tube, the drain of the first NMOS tube is connected to the drain of the second NMOS tube, the source of the first NMOS tube is connected to the source of the second NMOS tube and the drain of the third NMOS tube, the gate of the first NMOS tube is connected to the second signal input terminal, and the gate of the second NMOS tube is connected to the first signal input terminal. An input end, back gates of the first NMOS transistor and the second NMOS transistor are connected to the output stage of the second operational amplifier, the source of the third NMOS transistor is grounded, the source of the second PMOS transistor is connected to the source of the third PMOS transistor, the drain of the second PMOS transistor is connected to the drain of the third PMOS transistor, the source of the fourth PMOS transistor is connected to the source of the fifth PMOS transistor, the drain of the fourth PMOS transistor is connected to the drain of the fifth PMOS transistor, the gate of the third PMOS transistor is connected to the drain of the fourth PMOS transistor, and the gate of the fourth PMOS transistor is connected to the drain of the third PMOS transistor.

[0012] Optionally, the second gain stage includes: a first PMOS tube, a sixth PMOS tube, a fifth NMOS tube, a sixth NMOS tube, a first capacitor and a second capacitor, the source of the first PMOS tube and the sixth PMOS tube are connected to the power supply voltage end, the gate of the first PMOS tube and the second PMOS tube are connected, the drain of the first PMOS tube and the second PMOS tube are connected, the gate of the sixth PMOS tube and the fifth PMOS tube are connected, the drain of the sixth PMOS tube and the fifth PMOS tube are connected, the first capacitor is connected between the gate of the first PMOS tube and the drain of the first PMOS tube, and the second capacitor is connected between the gate of the sixth PMOS tube and the drain of the sixth PMOS tube.

[0013] Optionally, the operational amplifier circuit further includes a first signal output terminal and a second signal output terminal; the first common-mode feedback unit includes: a seventh PMOS transistor, an eighth PMOS transistor, a ninth PMOS transistor, a tenth PMOS transistor, an eleventh PMOS transistor, a twelfth PMOS transistor, a thirteenth PMOS transistor, a seventh NMOS transistor, an eighth NMOS transistor, and a fourth NMOS transistor, wherein the source electrodes of the seventh PMOS transistor, the eighth PMOS transistor, and the ninth PMOS transistor are connected, the gate electrodes of the seventh PMOS transistor, the eighth PMOS transistor, and the ninth PMOS transistor are connected, the source electrodes of the tenth PMOS transistor and the eleventh PMOS transistor are connected, and the gate electrodes of the tenth PMOS transistor and the eleventh PMOS transistor are connected. The S transistor is connected to the drain of the eleventh PMOS transistor, the source of the tenth PMOS transistor and the eleventh PMOS transistor is connected to the drain of the seventh PMOS transistor, the gate of the tenth PMOS transistor is connected to the first signal output terminal, the source of the twelfth PMOS transistor and the thirteenth PMOS transistor are connected, the drain of the twelfth PMOS transistor and the thirteenth PMOS transistor are connected, the gate of the twelfth PMOS transistor is connected to the gate of the eleventh PMOS transistor, the gate of the thirteenth PMOS transistor is connected to the second signal input terminal, and the drain of the twelfth PMOS transistor and the thirteenth PMOS transistor is connected to the drain of the tenth PMOS transistor and the eleventh PMOS transistor.

[0014] Optionally, the folded common-source and common-gate amplifier unit includes: a first current mirror, a second current mirror, a third current mirror, a fourth current mirror, a fourteenth PMOS tube, a twenty-first PMOS tube and a twenty-second PMOS tube, the first current mirror, the second current mirror, the third current mirror and the fourth current mirror are connected in series, the source of the fourteenth PMOS tube is connected to the power supply voltage end, the gate of the fourteenth PMOS tube is connected to the first current mirror, the source of the twenty-first PMOS tube and the twenty-second PMOS tube are connected, and the drain of the twenty-first PMOS tube and the twenty-second PMOS tube is connected.

[0015] Optionally, the chopping circuit includes a second chopping unit, which is connected between the third current mirror and the fourth current mirror.

[0016] Optionally, the chopping circuit further includes: a first chopping unit connected to the gates of the twenty-first PMOS tube and the twenty-second PMOS tube; and a third chopping unit connected between the first current mirror and the second current mirror.

[0017] Optionally, the first current mirror includes a fifteenth PMOS tube and a sixteenth PMOS tube, the second current mirror includes a seventeenth PMOS tube and an eighteenth PMOS tube, the third current mirror includes a ninth NMOS tube and a tenth NMOS tube, and the fourth current mirror includes an eleventh NMOS tube and a twelfth NMOS tube.

[0018] Optionally, the output stage includes: a nineteenth PMOS tube, a twentieth PMOS tube, a fifth current mirror, a third capacitor and a fourth capacitor, the source of the nineteenth PMOS tube and the twentieth PMOS tube are connected, the gate of the nineteenth PMOS tube and the twentieth PMOS tube are connected to the second current mirror, the drain of the nineteenth PMOS tube and the twentieth PMOS tube is connected to the fifth current mirror, the third capacitor is connected between the gate of the nineteenth PMOS tube and the second current mirror, and the fourth capacitor is connected between the gate of the twentieth PMOS tube and the second current mirror.

[0019] Optionally, the fifth current mirror includes: a fifteenth NMOS tube and a sixteenth NMOS tube, and the output stage also includes: a first adjustment signal output end and a second adjustment signal output end, the first adjustment signal output end is connected between the third capacitor and the drain of the fifteenth NMOS tube, and the second adjustment signal output end is connected between the fourth capacitor and the drain of the sixteenth NMOS tube.

[0020] Optionally, the second common-mode feedback unit includes: a thirteenth NMOS tube, a fourteenth NMOS tube, a seventeenth NMOS tube, a fifth resistor and a sixth resistor, the source of the thirteenth NMOS tube is connected to the source of the fourteenth NMOS tube, the drain of the thirteenth NMOS tube is connected to the drain of the fourteenth NMOS tube, the drain of the seventeenth NMOS tube is connected to the gate of the fifteenth NMOS tube and the sixteenth NMOS tube, the source of the seventeenth NMOS tube is connected to the source of the fifteenth NMOS tube and the sixteenth NMOS tube, the fifth resistor is connected between the gate and the drain of the fifteenth NMOS tube, and the sixth resistor is connected between the gate and the drain of the sixteenth NMOS tube.

[0021] Optionally, the first to seventeenth NMOS transistors and the first to twenty-second PMOS transistors are all silicon-on-insulator devices.

[0022] Correspondingly, the technical solution of the present application also provides a working method of an operational amplifier circuit, including: obtaining an adjustment signal based on a first signal; and adjusting the offset voltage and noise of the first signal based on the adjustment signal to output a second signal.

[0023] Compared with the prior art, the technical solution of the embodiment of the present application has the following beneficial effects:

[0024] The operational amplifier circuit provided by the technical solution of the present application connects a second operational amplifier in the operational amplifier circuit, and the second operational amplifier is used to output an adjustment signal to the first operational amplifier to adjust the offset voltage and noise of the first signal, so that the output of the first signal is more accurate, thereby ensuring the accuracy of the amplified second signal and improving the performance of the operational amplifier circuit; in addition, the technical solution of the present application connects a chopper circuit in the second operational amplifier to achieve low-impedance output of the adjustment signal, thereby increasing the bandwidth of the first operational amplifier and increasing the gain of the second operational amplifier, and then utilizing the high gain of the second operational amplifier to attenuate the offset voltage and noise of the first signal, thereby improving the performance of the operational amplifier circuit.

[0025] Furthermore, the transistor in the first operational amplifier in the technical solution of the present application adopts a silicon-on-insulator device, so that the first operational amplifier can receive the adjustment signal through the back gate of the transistor, thereby reducing the area of ​​the first operational amplifier and improving the integration of the operational amplifier circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] FIG1 is a structural diagram 1 of an operational amplifier circuit according to an embodiment of the present application;

[0027] FIG2 is a second structural diagram of an operational amplifier circuit according to an embodiment of the present application;

[0028] FIG3 is a third structural diagram of an operational amplifier circuit in an embodiment of the present application. DETAILED DESCRIPTION

[0029] As mentioned in the background art, the performance of current operational amplifier circuits still needs to be improved.

[0030] The existence of offset voltage and 1 / f noise in the operational amplifier circuit affects the performance of the operational amplifier circuit.

[0031] Currently, offset voltage and noise are reduced by inserting a chopper circuit into an operational amplifier. However, the high gain of the chopper circuit affects the bandwidth of the operational amplifier, thereby reducing the performance of the operational amplifier.

[0032] In order to solve the above problems, the technical solution of the present application provides an operational amplifier circuit, a working method thereof, and an operational amplifier. By connecting a second operational amplifier in the operational amplifier circuit, the second operational amplifier is used to output an adjustment signal to the first operational amplifier to adjust the offset voltage and noise of the first signal, so that the output of the first signal is more accurate, thereby ensuring the accuracy of the amplified second signal and improving the performance of the operational amplifier circuit; in addition, the technical solution of the present application connects a chopper circuit in the second operational amplifier to achieve low-impedance output of the adjustment signal, thereby increasing the bandwidth of the first operational amplifier and increasing the gain of the second operational amplifier, and then utilizing the high gain of the second operational amplifier to attenuate the offset voltage and noise of the first signal, thereby improving the performance of the operational amplifier circuit.

[0033] In order to make the above-mentioned objectives, features and beneficial effects of the present application more obvious and easy to understand, the specific embodiments of the present application are described in detail below with reference to the accompanying drawings.

[0034] FIG1 is a first structural diagram of an operational amplifier circuit in an embodiment of the present application.

[0035] Please refer to Figure 1. The technical solution of the present application provides an operational amplifier circuit, including: a first operational amplifier OPM1, used to output an adjustment signal according to a first signal, the first operational amplifier OPM1 including a chopping circuit, and the chopping circuit is used to adjust the offset voltage and noise of the adjustment signal; a second operational amplifier OPM2, used to adjust the offset voltage and noise of the first signal according to the adjustment signal to output a second signal.

[0036] The operational amplifier circuit further includes a first resistor R1 , a second resistor R2 , a third resistor R3 and a fourth resistor R4 , which are used to control the amplification factor of the first operational amplifier OPM1 .

[0037] In this embodiment, the gain of the operational amplifier circuit is adjusted by adjusting the ratio R2 / R1 of the second resistor R2 to the first resistor R1 and the ratio R4 / R3 of the fourth resistor R4 to the third resistor R3.

[0038] In this embodiment, the first to seventeenth NMOS transistors N1 to N17 and the first to twenty-second PMOS transistors P1 to P22 are all silicon-on-insulator devices.

[0039] Specifically, the operational amplifier circuit in the above scheme has a dual-loop feedback structure, wherein the first operational amplifier OPM1 and the second operational amplifier OPM2 are connected in parallel to achieve both high bandwidth and low noise, and the operational amplifier circuit operates in continuous mode. The offset voltage and 1 / f noise of the first operational amplifier OPM1 are attenuated by the high gain of the second operational amplifier OPM2. The second operational amplifier OPM2 is designed to be low-speed and high-gain, and utilizes a negative feedback structure to attenuate the offset voltage and 1 / f noise of the first operational amplifier OPM1. Since the offset voltage and 1 / f noise are primarily at low frequencies, the second operational amplifier OPM2 constitutes a low-speed, high-gain operational amplifier that can effectively attenuate the offset voltage and 1 / f noise.

[0040] In the above scheme, by connecting the second operational amplifier OPM2 in the operational amplifier circuit, the second operational amplifier OPM2 is used to output an adjustment signal to the first operational amplifier OPM1 to adjust the offset voltage and noise of the first signal, so that the output of the first signal is more accurate, thereby ensuring the accuracy of the amplified second signal and improving the performance of the operational amplifier circuit; in addition, the technical solution of the present application realizes low-impedance output of the adjustment signal by connecting a chopper circuit in the second operational amplifier OPM2, thereby increasing the bandwidth of the first operational amplifier OPM1 and increasing the gain of the second operational amplifier OPM2, and then utilizing the high gain of the second operational amplifier OPM2 to attenuate the offset voltage and noise of the first signal, thereby improving the performance of the operational amplifier circuit.

[0041] FIG2 is a second structural diagram of an operational amplifier circuit in an embodiment of the present application.

[0042] Referring to FIG2 , the first operational amplifier OPM1 includes: a first gain stage 101, wherein a first input terminal of the first gain stage 101 is used to obtain a first signal; a second gain stage 102, wherein an input terminal of the second gain stage 102 is connected to an output terminal of the first gain stage 101; and a first common-mode feedback unit 103, wherein an input terminal of the first common-mode feedback unit 103 is connected to an output terminal of the second gain stage 102, and an output terminal of the first common-mode feedback unit 103 is connected to an output terminal of the first gain stage 101.

[0043] The first gain stage 101 is used to amplify the first signal to obtain a second signal.

[0044] The second gain stage 102 is configured to output a second signal.

[0045] The first common-mode feedback unit 103 is configured to output an output common-mode voltage of a second signal.

[0046] The operational amplifier circuit further includes: a first signal input terminal INP and a second signal input terminal INN; the first gain stage 101 includes a first NMOS transistor N1, a second NMOS transistor N2, a third NMOS transistor N3, a second PMOS transistor P2, a third PMOS transistor P3, a fourth PMOS transistor P4 and a fifth PMOS transistor P5, the drain of the first NMOS transistor N1 is connected to the drain of the second NMOS transistor N2, the source of the first NMOS transistor N1 is connected to the source of the second NMOS transistor N2 and the drain of the third NMOS transistor N3, the gate of the first NMOS transistor N1 is connected to the second signal input terminal INN, the gate of the second NMOS transistor N2 is connected to the first signal input terminal INN, and the gate of the second NMOS transistor N2 is connected to the first signal input terminal INN. The first NMOS transistor N1 and the second NMOS transistor have back gates connected to the output stage of the second operational amplifier OPM2. The source of the third NMOS transistor N3 is grounded. The sources of the second PMOS transistor P2 and the third PMOS transistor P3 are connected. The drains of the second PMOS transistor P2 and the third PMOS transistor P3 are connected. The sources of the fourth PMOS transistor P4 and the fifth PMOS transistor P5 are connected. The drains of the fourth PMOS transistor P4 and the fifth PMOS transistor P5 are connected. The gate of the third PMOS transistor P3 is connected to the drain of the fourth PMOS transistor P4. The gate of the fourth PMOS transistor P4 is connected to the drain of the third PMOS transistor P3.

[0047] The second gain stage 102 includes: a first PMOS transistor P1, a sixth PMOS transistor P6, a fifth NMOS transistor N5, a sixth NMOS transistor N6, a first capacitor C1, and a second capacitor C2. The sources of the first PMOS transistor P1 and the sixth PMOS transistor P6 are connected to the power supply voltage terminal VCC, the gates of the first PMOS transistor P1 and the second PMOS transistor P2 are connected, the drains of the first PMOS transistor P1 and the second PMOS transistor P2 are connected, the gates of the sixth PMOS transistor P6 and the fifth PMOS transistor P5 are connected, and the drains of the sixth PMOS transistor P6 and the fifth PMOS transistor P5 are connected. The first capacitor C1 is connected between the gate of the first PMOS transistor P1 and the drain of the first PMOS transistor P1, and the second capacitor C2 is connected between the gate of the sixth PMOS transistor P6 and the drain of the sixth PMOS transistor P6.

[0048] The operational amplifier circuit further includes a first signal output terminal OUTP and a second signal output terminal OUTN; the first common-mode feedback unit 103 includes: a seventh PMOS transistor P7, an eighth PMOS transistor P8, a ninth PMOS transistor P9, a tenth PMOS transistor P10, an eleventh PMOS transistor P11, a twelfth PMOS transistor P12, a thirteenth PMOS transistor P13, a seventh NMOS transistor N7, an eighth NMOS transistor N8 and a fourth NMOS transistor N4, the source electrodes of the seventh PMOS transistor P7, the eighth PMOS transistor P8 and the ninth PMOS transistor P9 are connected, the gate electrodes of the seventh PMOS transistor P7, the eighth PMOS transistor P8 and the ninth PMOS transistor P9 are connected, the source electrodes of the tenth PMOS transistor P10 and the eleventh PMOS transistor P11 are connected, and the tenth PMOS transistor P12 is connected. The first PMOS transistor P10 is connected to the drain of the eleventh PMOS transistor P11, the sources of the tenth PMOS transistor P10 and the eleventh PMOS transistor P11 are connected to the drain of the seventh PMOS transistor P7, the gate of the tenth PMOS transistor P10 is connected to the first signal output terminal OUTP, the sources of the twelfth PMOS transistor P12 and the thirteenth PMOS transistor P13 are connected, the drains of the twelfth PMOS transistor P12 and the thirteenth PMOS transistor P13 are connected, the gate of the twelfth PMOS transistor P12 is connected to the gate of the eleventh PMOS transistor P11, the gate of the thirteenth PMOS transistor P13 is connected to the second signal input terminal INN, and the drains of the twelfth PMOS transistor P12 and the thirteenth PMOS transistor P13 are connected to the drains of the tenth PMOS transistor P10 and the eleventh PMOS transistor P11.

[0049] The second gain stage 102 is further used to increase the driving capability of the output signal.

[0050] The first common-mode feedback unit 103 is used to stabilize the output common-mode voltage of the output voltage.

[0051] Specifically, the gates of the first NMOS transistor N1 and the second NMOS transistor N2 are respectively connected to the first signal input terminal INP and the second signal input terminal INN of the first operational amplifier OPM1, and the back gates of the first NMOS transistor N1 and the second NMOS transistor N2 are connected to the output stage of the second operational amplifier OPM2; the back gate of the silicon-on-insulator device is used to adjust the threshold voltage VTH to act as the second operational amplifier OPM2. The gain of the second operational amplifier OPM2 is attenuated relative to the gate, and therefore a high gain of the second operational amplifier OPM2 is required to compensate for the attenuation of the back gate adjustment.

[0052] FIG3 is a third structural diagram of an operational amplifier circuit in an embodiment of the present application.

[0053] Please refer to Figure 3. The second operational amplifier OPM2 includes: a folded cascode amplifier unit, the input end of the folded cascode amplifier unit is connected to the first input end of the first gain stage 101; an output stage, the input end of the output stage is connected to the output end of the folded cascode amplifier unit; the output end of the output stage is connected to the second input end of the first gain stage 101; a second common-mode feedback unit, the input end of the second common-mode feedback unit is connected to the output end of the output stage, and the output end of the second common-mode feedback unit is connected to the output end of the folded cascode amplifier unit.

[0054] The folded cascode amplifier unit is used to obtain a regulation signal according to the first signal.

[0055] The second common-mode feedback unit is configured to output an output common-mode voltage of the adjustment signal.

[0056] The output stage is used to output a regulating signal to the first operational amplifier.

[0057] The folded cascode amplifier unit includes: a first current mirror 201, a second current mirror 202, a third current mirror 203, a fourth current mirror, a fourteenth PMOS transistor P14, a twenty-first PMOS transistor P21, and a twenty-second PMOS transistor P22. The first current mirror 201, the second current mirror 202, the third current mirror 203, and the fourth current mirror are connected in series. The source of the fourteenth PMOS transistor P14 is connected to the power supply voltage terminal VCC, and the gate of the fourteenth PMOS transistor P14 is connected to the first current mirror 201. The sources of the twenty-first PMOS transistor P21 and the twenty-second PMOS transistor P22 are connected, and the drains of the twenty-first PMOS transistor P21 and the twenty-second PMOS transistor P22 are connected.

[0058] The chopping circuit includes a second chopping unit CH2 , which is connected between the third current mirror 203 and the fourth current mirror.

[0059] The second chopping unit CH2 is used to achieve low-impedance output and increase the bandwidth of the operational amplifier.

[0060] The chopping circuit further includes: a first chopping unit CH1 connected to the gates of the twenty-first PMOS transistor P21 and the twenty-second PMOS transistor P22; and a third chopping unit CH3 connected between the first current mirror 201 and the second current mirror 202.

[0061] The third chopping unit CH3 is used to reduce the offset voltage and 1 / f noise of the second operational amplifier OPM2 while increasing the gain.

[0062] The first current mirror 201 includes a fifteenth PMOS transistor P15 and a sixteenth PMOS transistor P16, the second current mirror 202 includes a seventeenth PMOS transistor P17 and an eighteenth PMOS transistor P18, the third current mirror 203 includes a ninth NMOS transistor N9 and a tenth NMOS transistor N10, and the fourth current mirror includes an eleventh NMOS transistor N11 and a twelfth NMOS transistor N12.

[0063] The output stage includes: a nineteenth PMOS transistor P19, a twentieth PMOS transistor P20, a fifth current mirror, a third capacitor C3, and a fourth capacitor C4. The source of the nineteenth PMOS transistor P19 is connected to the source of the twentieth PMOS transistor P20, the gate of the nineteenth PMOS transistor P20 is connected to the second current mirror 202, the drain of the nineteenth PMOS transistor P20 is connected to the fifth current mirror, the third capacitor C3 is connected between the gate of the nineteenth PMOS transistor and the second current mirror 202, and the fourth capacitor C4 is connected between the gate of the twentieth PMOS transistor P20 and the second current mirror 202.

[0064] The fifth current mirror includes: a fifteenth NMOS transistor N15 and a sixteenth NMOS transistor N16. The output stage also includes: a first adjustment signal output end and a second adjustment signal output end. The first adjustment signal output end is connected between the third capacitor C3 and the drain of the fifteenth NMOS transistor N15, and the second adjustment signal output end is connected between the fourth capacitor C4 and the drain of the sixteenth NMOS transistor N16.

[0065] The second common-mode feedback unit includes: a thirteenth NMOS transistor N13, a fourteenth NMOS transistor N14, a seventeenth NMOS transistor N17, a fifth resistor, and a sixth resistor. The source of the thirteenth NMOS transistor N13 is connected to the source of the fourteenth NMOS transistor N14, the drain of the thirteenth NMOS transistor N13 is connected to the drain of the fourteenth NMOS transistor N14, the drain of the seventeenth NMOS transistor N17 is connected to the gates of the fifteenth NMOS transistor N15 and the sixteenth NMOS transistor N16, the source of the seventeenth NMOS transistor N17 is connected to the source of the fifteenth NMOS transistor N15 and the sixteenth NMOS transistor N16, the fifth resistor is connected between the gate and the drain of the fifteenth NMOS transistor N15, and the sixth resistor is connected between the gate and the drain of the sixteenth NMOS transistor N16.

[0066] Specifically, the architecture of the second operational amplifier OPM2 adopts a folded cascode structure, and the output stage adopts a class A structure.

[0067] In the above scheme, the transistor in the first operational amplifier OPM1 in the technical scheme of this application adopts a silicon-on-insulator device (FDSOI), so that the first operational amplifier OPM1 can receive the adjustment signal through the back gate of the transistor, thereby reducing the area of ​​the first operational amplifier OPM1 and improving the integration of the operational amplifier circuit.

[0068] Accordingly, the technical solution of the present application also provides a working method of an operational amplifier circuit, comprising: obtaining an adjustment signal according to a first signal; and adjusting the offset voltage and noise of the first signal according to the adjustment signal to output a second signal.

[0069] Although the present application is disclosed as above, the present application is not limited thereto. Any person skilled in the art may make various changes and modifications without departing from the spirit and scope of the present application. Therefore, the scope of protection of the present application shall be based on the scope defined by the claims.

Claims

1. An operational amplifier circuit, characterized in that: include: a first operational amplifier, configured to output a regulation signal according to the first signal, wherein the first operational amplifier comprises a chopper circuit, and the chopper circuit is configured to adjust an offset voltage and noise of the regulation signal; The second operational amplifier is configured to adjust the offset voltage and noise of the first signal according to the adjustment signal to output a second signal.

2. The operational amplifier circuit according to claim 1, wherein: The first operational amplifier includes: a first gain stage, wherein a first input end of the first gain stage is used to obtain the first signal; a second gain stage, wherein an input end of the second gain stage is connected to an output end of the first gain stage; and a first common-mode feedback unit, wherein an input end of the first common-mode feedback unit is connected to an output end of the second gain stage, and an output end of the first common-mode feedback unit is connected to an output end of the first gain stage.

3. The operational amplifier circuit according to claim 2, wherein: The second operational amplifier includes: a folded cascode amplifier unit, wherein the input end of the folded cascode amplifier unit is connected to the first input end of the first gain stage; an output stage, wherein the input end of the output stage is connected to the output end of the folded cascode amplifier unit; the output end of the output stage is connected to the second input end of the first gain stage; and a second common-mode feedback unit, wherein the input end of the second common-mode feedback unit is connected to the output end of the output stage, and the output end of the second common-mode feedback unit is connected to the output end of the folded cascode amplifier unit.

4. The operational amplifier circuit according to claim 3, wherein: Also includes: The first resistor, the second resistor, the third resistor and the fourth resistor are used to control the amplification factor of the first operational amplifier.

5. The operational amplifier circuit according to claim 4, wherein: The first gain stage includes a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, a second PMOS transistor, a third PMOS transistor, a fourth PMOS transistor, and a fifth PMOS transistor. The drain of the first NMOS transistor is connected to the drain of the second NMOS transistor, the source of the first NMOS transistor is connected to the source of the second NMOS transistor and the drain of the third NMOS transistor, the gate of the first NMOS transistor is connected to the second signal input terminal, the gate of the second NMOS transistor is connected to the first signal input terminal, the back gates of the first NMOS transistor and the second NMOS transistor are connected to the output stage of the second operational amplifier, the source of the third NMOS transistor is grounded, the source of the second PMOS transistor is connected to the source of the third PMOS transistor, the drain of the second PMOS transistor is connected to the drain of the third PMOS transistor, the source of the fourth PMOS transistor is connected to the source of the fifth PMOS transistor, the drain of the fourth PMOS transistor is connected to the drain of the fifth PMOS transistor, the gate of the third PMOS transistor is connected to the drain of the fourth PMOS transistor, and the gate of the fourth PMOS transistor is connected to the drain of the third PMOS transistor.

6. The operational amplifier circuit according to claim 5, wherein: The second gain stage includes: a first PMOS transistor, a sixth PMOS transistor, a fifth NMOS transistor, a sixth NMOS transistor, a first capacitor, and a second capacitor. The sources of the first PMOS transistor and the sixth PMOS transistor are connected to a power supply voltage terminal, the gates of the first PMOS transistor and the second PMOS transistor are connected, the drains of the first PMOS transistor and the second PMOS transistor are connected, the gates of the sixth PMOS transistor and the fifth PMOS transistor are connected, and the drains of the sixth PMOS transistor and the fifth PMOS transistor are connected. The first capacitor is connected between the gate of the first PMOS transistor and the drain of the first PMOS transistor, and the second capacitor is connected between the gate of the sixth PMOS transistor and the drain of the sixth PMOS transistor.

7. The operational amplifier circuit according to claim 6, wherein: The first common-mode feedback unit includes: a seventh PMOS tube, an eighth PMOS tube, a ninth PMOS tube, a tenth PMOS tube, an eleventh PMOS tube, a twelfth PMOS tube, a thirteenth PMOS tube, a seventh NMOS tube, an eighth NMOS tube and a fourth NMOS tube, wherein the source of the seventh PMOS tube, the eighth PMOS tube and the ninth PMOS tube are connected, the gate of the seventh PMOS tube, the eighth PMOS tube and the ninth PMOS tube are connected, the source of the tenth PMOS tube and the eleventh PMOS tube are connected, and the gate of the tenth PMOS tube and the eleventh PMOS tube are connected. The drains of the tenth PMOS transistor and the eleventh PMOS transistor are connected, the sources of the tenth PMOS transistor and the eleventh PMOS transistor are connected to the drain of the seventh PMOS transistor, the gate of the tenth PMOS transistor is connected to the first signal output end, the sources of the twelfth PMOS transistor and the thirteenth PMOS transistor are connected, the drains of the twelfth PMOS transistor and the thirteenth PMOS transistor are connected, the gate of the twelfth PMOS tube is connected to the gate of the eleventh PMOS tube, the gate of the thirteenth PMOS tube is connected to the second signal input end, and the drains of the twelfth PMOS transistor and the thirteenth PMOS tube are connected to the drains of the tenth PMOS tube and the eleventh PMOS tube.

8. The operational amplifier circuit according to claim 7, wherein: The folded cascode amplifier unit includes: a first current mirror, a second current mirror, a third current mirror, a fourth current mirror, a fourteenth PMOS tube, a twenty-first PMOS tube and a twenty-second PMOS tube, the first current mirror, the second current mirror, the third current mirror and the fourth current mirror are connected in series, the source of the fourteenth PMOS tube is connected to the power supply voltage terminal, the gate of the fourteenth PMOS tube is connected to the first current mirror, the sources of the twenty-first PMOS tube and the twenty-second PMOS tube are connected, and the drains of the twenty-first PMOS tube and the twenty-second PMOS tube are connected.

9. The operational amplifier circuit according to claim 8, wherein: The chopping circuit includes a second chopping unit, which is connected between the third current mirror and the fourth current mirror.

10. The operational amplifier circuit according to claim 9, wherein: The chopping circuit further includes: a first chopping unit connected to the gates of the twenty-first PMOS transistor and the twenty-second PMOS transistor; and a third chopping unit connected between the first current mirror and the second current mirror.

11. The operational amplifier circuit according to claim 10, wherein: The first current mirror includes a fifteenth PMOS tube and a sixteenth PMOS tube, the second current mirror includes a seventeenth PMOS tube and an eighteenth PMOS tube, the third current mirror includes a ninth NMOS tube and a tenth NMOS tube, and the fourth current mirror includes an eleventh NMOS tube and a twelfth NMOS tube.

12. The operational amplifier circuit according to claim 11, wherein: The output stage includes: a nineteenth PMOS transistor, a twentieth PMOS transistor, a fifth current mirror, a third capacitor, and a fourth capacitor. The source of the nineteenth PMOS transistor is connected to the source of the twentieth PMOS transistor, the gate of the nineteenth PMOS transistor and the twentieth PMOS transistor is connected to the second current mirror, the drain of the nineteenth PMOS transistor and the twentieth PMOS transistor is connected to the fifth current mirror, the third capacitor is connected between the gate of the nineteenth PMOS transistor and the second current mirror, and the fourth capacitor is connected between the gate of the twentieth PMOS transistor and the second current mirror.

13. The operational amplifier circuit according to claim 12, wherein: The fifth current mirror includes: a fifteenth NMOS transistor and a sixteenth NMOS transistor, and the output stage also includes: a first adjustment signal output end and a second adjustment signal output end, the first adjustment signal output end is connected between the third capacitor and the drain of the fifteenth NMOS transistor, and the second adjustment signal output end is connected between the fourth capacitor and the drain of the sixteenth NMOS transistor.

14. The operational amplifier circuit according to claim 13, wherein: The second common-mode feedback unit includes: a thirteenth NMOS transistor, a fourteenth NMOS transistor, a seventeenth NMOS transistor, a fifth resistor and a sixth resistor, the thirteenth NMOS transistor is connected to the source of the fourteenth NMOS transistor, the thirteenth NMOS transistor is connected to the drain of the fourteenth NMOS transistor, the drain of the seventeenth NMOS transistor is connected to the gates of the fifteenth NMOS transistor and the sixteenth NMOS transistor, the source of the seventeenth NMOS transistor is connected to the source of the fifteenth NMOS transistor and the sixteenth NMOS transistor, the fifth resistor is connected between the gate and drain of the fifteenth NMOS transistor, and the sixth resistor is connected between the gate and drain of the sixteenth NMOS transistor.

15. The operational amplifier circuit according to claim 14, wherein: The first to seventeenth NMOS transistors and the first to twenty-second PMOS transistors are all silicon-on-insulator devices.

16. A method for operating an operational amplifier circuit, characterized in that: include: obtaining a regulating signal according to the first signal; The offset voltage and noise of the first signal are adjusted according to the adjustment signal to output a second signal.

Images