Access method, access apparatus, processor system and electronic device

Abstract

The present application relates to the technical field of chips. Provided in the embodiments of the present application are an access method, an access apparatus, a processor system and an electronic device, which can implement with fewer instructions inter-core data synchronization of multiple processor cores, so as to improve the performance of processor systems. The specific solution comprises: acquiring a first access request sent by a processor core when executing a first atomic instruction, the first access request carrying address information, and the address information being used for indicating the address of a first cache line in a cache; in response to the first access request and on the basis of the address information, accessing the first cache line, and acquiring the address of a second cache line in the cache; and on the basis of the address of the second cache line, accessing the second cache line. The embodiments of the present application are used for the processes of processor cores accessing the cache.

Description

Access method, access device, processor system and electronic device

[0001] This application claims priority to the Chinese patent application filed with the State Intellectual Property Office on March 5, 2024, with application number 202410253540.4 and application name “Access Method, Access Device, Processor System and Electronic Device”, the entire contents of which are incorporated by reference into this application. Technical Field

[0002] The embodiments of the present application relate to the field of chip technology, and in particular to an access method, an access device, a processor system, and an electronic device. Background Art

[0003] Currently, processor systems can include multiple processor cores, all of which can be active simultaneously. As application workloads scale and the processing power of a single processor core is limited, to improve application execution, parallel portions of an application can be distributed across multiple cores. However, data distributed across multiple cores presents the challenge of data synchronization between them.

[0004] In order to achieve inter-core data synchronization, methods such as non-shared memory and shared memory can be used. Among them, the non-shared memory method can use the message passing interface (MPI) and other forms to synchronize data in a cross-process scenario. The shared memory method can include synchronization based on atomic instructions, synchronization based on hardware transactional memory (HTM), and synchronization based on locks. However, the HTM-based method is relatively complex and will bring greater design complexity to the processor system. The lock-based synchronization method is more programming-friendly, but still has a large time overhead. Summary of the Invention

[0005] The embodiments of the present application provide an access method, an access device, a processor system, and an electronic device, which can realize inter-core data synchronization of multiple processor cores with fewer instructions, thereby improving the performance of the processor system.

[0006] To achieve the above objectives, the embodiments of the present application adopt the following technical solutions.

[0007] In a first aspect, an embodiment of the present application provides an access method, which includes: obtaining a first access request issued by a processor core to execute a first atomic instruction, the first access request carrying address information, and the address information being used to indicate the address of a first cache line in a cache; in response to the first access request, accessing the first cache line based on the address information to obtain the address of a second cache line in the cache; and accessing the second cache line based on the address of the second cache line.

[0008] Therefore, in the access method provided by the embodiment of the present application, the address of the second cache line will be stored in the first cache line, and the first cache line will be accessed first based on the first access request to obtain the address of the second cache line, and then the second cache line will be accessed based on the address of the second cache line, that is, the processor core can complete the atomic access of the two cache lines in one atomic instruction such as the first atomic instruction. Compared with the operation that requires at least two atomic instructions to complete the access operation of two cache lines, the access method provided by the embodiment of the present application is changed from multiple instructions to a single instruction. In the scenario of inter-core data synchronization, the first cache line can be regarded as a "lock variable" and the second cache line can be regarded as a "data variable in the critical section". This method concentrates the operations on the lock variable and the data variable in the same atomic instruction, reduces the number of atomic instructions, and can also achieve inter-core data synchronization of multiple processor cores with fewer atomic instructions, thereby improving the performance of the processor system.

[0009] In one possible design, the first cache line and the second cache line are located in the same cache queue, and the first cache line stores a first address offset, which is the offset between the address of the second cache line and the address of the first cache line. Thus, the first address offset can be obtained by accessing the first cache line. The first address offset is the address offset of the second cache line relative to the first cache line. The address of the second cache line is then calculated based on the address of the first cache line and the first address offset. The processor core can then access the first cache line and the second cache line based on the first atomic instruction, reducing the number of instructions.

[0010] In one possible design, in response to a first access request, accessing the first cache line based on the address information to obtain the address of a second cache line in the cache includes: in response to the first access request, accessing the first cache line based on the address information to obtain a first address offset. Obtaining the address of the second cache line in the cache based on the address information and the first address offset. Thus, while ensuring cache coherence, only one first atomic instruction is required to access two cache lines, reducing the number of atomic instructions.

[0011] In one possible design, the method further includes: updating a first address offset in the first cache line to obtain a second address offset, where the second address offset is the offset between the address of a third cache line in the cache and the address of the first cache line, and the first cache line, the second cache line, and the third cache line are located in the same cache queue. Thus, when the processor core executes the next atomic instruction, it can access the cache line data using only one atomic instruction while ensuring cache coherence, thereby reducing the number of atomic instructions.

[0012] In one possible design, the method further includes: obtaining a second access request issued by the processor core to execute the second atomic instruction, the second access request carrying address information. In response to the second access request, the first cache line is accessed based on the address information, and the address of the third cache line is obtained. The third cache line is accessed based on the address of the third cache line. Thus, each atomic instruction can access two cache lines, and multiple instructions that access two cache lines become a single instruction. At this time, the first cache line can be regarded as a "lock variable" and the third cache line can be regarded as a "data variable in the critical section". The operations on the lock variable and the data variable are concentrated in the same atomic instruction, which is easy to use. In addition, the position of the processor core's access request to the shared memory is fixed, which can reduce data transmission and improve the performance of the processor system.

[0013] In a second aspect, an embodiment of the present application provides an access device, comprising: an acquisition unit and an access unit. The acquisition unit is configured to acquire a first access request issued by a processor core to execute a first atomic instruction, the first access request carrying address information, the address information being used to indicate the address of a first cache line in a cache. The access unit is configured to access the first cache line based on the address information in response to the first access request and acquire the address of a second cache line in the cache. The access unit is further configured to access a second cache line based on the address of the second cache line.

[0014] In one possible design, the first cache line and the second cache line are located in the same cache queue, and the first cache line stores a first address offset, which is an offset between an address of the second cache line and an address of the first cache line.

[0015] In one possible design, the access unit is specifically configured to, in response to the first access request, access the first cache line based on the address information to obtain a first address offset, and obtain an address of a second cache line in the cache based on the address information and the first address offset.

[0016] In one possible design, the access unit is also used to update the first address offset in the first cache line to obtain a second address offset, where the second address offset is the offset between the address of the third cache line in the cache and the address of the first cache line, and the first cache line, the second cache line, and the third cache line are located in the same queue of the cache.

[0017] In one possible design, the acquisition unit is further configured to acquire a second access request issued by the processor core when executing the second atomic instruction, the second access request carrying address information. The access unit is further configured to, in response to the second access request, access the first cache line based on the address information to acquire the address of the third cache line. The access unit is further configured to access the third cache line based on the address of the third cache line.

[0018] The beneficial effects of the second aspect can be found in the description of the first aspect.

[0019] In a third aspect, an embodiment of the present application provides a processor system comprising a memory manager and multiple processor cores. One of the multiple processor cores is configured to execute an atomic instruction and obtain an access request, the access request carrying address information, the address information being configured to indicate an address of a first cache line in a cache. The memory manager is configured to, in response to the access request, access the first cache line based on the address information and obtain the address of a second cache line in the cache. The memory manager is further configured to access a second cache line based on the address of the second cache line.

[0020] In a fourth aspect, an embodiment of the present application provides an electronic device, which includes one or more interface circuits and one or more processor systems of the third aspect, and the interface circuits and the processor systems are interconnected via lines.

[0021] In a fifth aspect, an embodiment of the present application provides a computer-readable storage medium, comprising computer instructions. When the computer instructions are executed on an electronic device, the electronic device executes the access method in a possible implementation of the first aspect described above.

[0022] In a sixth aspect, an embodiment of the present application provides a computer program product, which, when running on a computer or a processor, enables the computer or the processor to execute the access method in a possible implementation of the first aspect described above.

[0023] It can be understood that any of the access devices, processor systems, electronic devices, computer-readable storage media or computer program products provided above can be applied to the corresponding methods provided above. Therefore, the beneficial effects that can be achieved can refer to the beneficial effects in the corresponding methods and will not be repeated here.

[0024] These and other aspects of the present application will become more readily apparent from the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] FIG1 is a schematic diagram of the structure of a processor system provided in an embodiment of the present application;

[0026] FIG2 is a flow chart of an access method provided in an embodiment of the present application;

[0027] FIG3 is a schematic diagram of a cache queue provided in an embodiment of the present application;

[0028] FIG4 is a flowchart of another access method provided in an embodiment of the present application;

[0029] FIG5 is a schematic diagram of the composition of an access device provided in an embodiment of the present application;

[0030] FIG6 is a schematic diagram of the structure of another processor system provided in an embodiment of the present application. DETAILED DESCRIPTION

[0031] For ease of understanding, some examples of concepts related to the embodiments of this application are provided for reference as follows:

[0032] 1. Shared memory: Multiple processes can map a block of memory to their own process space, enabling data sharing and transmission. For example, the same block of physical memory is mapped to the address spaces of process A and process B. Process A can receive real-time updates to the shared memory from process B, and vice versa.

[0033] 2. Atomic instruction refers to a single, indivisible and uninterruptible machine instruction that is directly executed by hardware.

[0034] 3. A cache line, also known as a cache block, is the minimum granularity for cache operations. The cache can be divided into multiple cache groups, each of which can be divided into multiple cache lines. A cache line is the basic unit of cache, and data migrated from main memory to the cache is replaced in cache lines.

[0035] The technical solutions in the embodiments of the present application will be described below in conjunction with the accompanying drawings in the embodiments of the present application. In the description of the embodiments of the present application, unless otherwise specified, " / " means or, for example, A / B can mean A or B; "and / or" in this article is merely a description of the association relationship of associated objects, indicating that three relationships can exist, for example, A and / or B can mean: A exists alone, A and B exist at the same time, and B exists alone. In addition, in the description of the embodiments of the present application, "multiple" means two or more than two.

[0036] In the following, the terms "first" and "second" are used for descriptive purposes only and should not be understood to indicate or imply relative importance or implicitly specify the number of the technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of this embodiment, unless otherwise specified, "plurality" means two or more.

[0037] Currently, in multi-core processor systems, a large memory capacity that can be accessed by different processor cores can be set up. This large memory capacity is called shared memory. Because multiple processor cores need to quickly access memory, the memory needs to be cached. When any cached data is updated, other processor cores may also need to read it. Therefore, the data in the shared memory must be updated immediately. Otherwise, different processor cores may read different data. Therefore, data distributed across multiple processor cores faces the problem of data synchronization between the processor cores.

[0038] Specifically, data synchronization between multiple processor cores in a shared memory system may be implemented in the following ways.

[0039] In one possible implementation, the processor system can achieve inter-core data synchronization based on atomic instructions. Atomic instructions can conveniently optimize data transmission by relying on execution units distributed in the system on chip (SoC), thereby reducing the serial transmission of data in the system on chip. However, since the data movement of the cache-level system is at the granularity of cache lines, operations across cache lines are more complicated, that is, atomic instructions are limited to the granularity of a cache line, and an atomic instruction can only operate on one cache line. In one possible example, if an atomic instruction is used to operate a cache line, then an atomic instruction corresponding to the address of the lock variable and an atomic instruction corresponding to the address of the data variable are required, that is, at least two atomic instructions are required to complete the operation on two cache lines.

[0040] In another possible implementation, the processor system can synchronize data between cores using hardware transactional memory. Hardware transactional memory allows only one thread to update data at a time. Specifically, all threads can execute simultaneously. When a thread updates data, it broadcasts the updated data. Other threads check whether the modified data conflicts with the currently updated data. If a conflict occurs, the thread is re-executed. However, hardware transactional memory commands are complex, and hardware and software adaptation requires significant overhead.

[0041] In another possible implementation, the processor system can implement inter-core data synchronization based on locks. Locks can be used to convert parallel access to shared memory by multiple processor cores into serial access to shared memory. Specifically, the processor system can lock the memory bus. For example, when a processor core accesses shared memory via the memory bus, a lock instruction can lock the memory bus, temporarily preventing other processor cores from accessing the shared memory. Alternatively, the processor system can lock cache lines. For example, when a processor core accesses a cache line, other processor cores cannot access the cache line because the cache line is locked.

[0042] However, the critical section of a lock (i.e., the code section that needs to be executed serially) must be implemented in software, which generally requires multiple instructions and a long execution time. This creates a serious serial access bottleneck in scenarios where multiple processor cores are running in parallel. Because direct operations on the lock are performed within the processor core, when multiple processor cores manipulate the same lock, lock data may be "ping-ponged" between the multiple processor cores, resulting in unnecessary bandwidth waste. Furthermore, lock programming is complex, and software is sometimes required to use instruction ordering to ensure correct processor system behavior and avoid deadlock.

[0043] Therefore, the embodiment of the present application provides an access method, in which the address of the second cache line is stored in the first cache line, and the first cache line is first accessed based on the first access request to obtain the address of the second cache line, and then the second cache line is accessed based on the address of the second cache line, that is, the processor core can complete the atomic access of the two cache lines in one atomic instruction such as the first atomic instruction. Compared with requiring at least two atomic instructions to complete the access operation of two cache lines, the access method provided by the embodiment of the present application changes from multiple instructions to a single instruction. In the scenario of inter-core data synchronization, the first cache line can be regarded as a "lock variable" and the second cache line can be regarded as a "data variable in the critical section". The operations on the lock variable and the data variable are concentrated in the same atomic instruction, which reduces the number of atomic instructions and can also achieve inter-core data synchronization of multiple processor cores with fewer atomic instructions, thereby improving the performance of the processor system.

[0044] For ease of understanding, the following first introduces the access device or processor system used in the access method provided in the embodiment of the present application. The device used by the access device or processor system provided in the embodiment of the present application can be an execution device, which can be a terminal such as a mobile phone terminal, a tablet computer, a laptop computer, an augmented reality (AR) device, a virtual reality (VR) device, and an in-vehicle terminal, etc. It can also be a server cluster, etc. The access device or processor system provided in the embodiment of the present application can be applied to the field of memory-based data communication in the execution device.

[0045] In some embodiments, the processor system provided by the embodiments of the present application may be a system-on-chip, a terminal chip, or a server chip, etc. As shown in Figure 1, Figure 1 is a schematic structural diagram of a processor system provided by an embodiment of the present application. The processor system may include multiple processor core clusters, each processor core cluster may include multiple processor cores, and two processor core clusters are shown in Figure 1, namely processor core cluster 0 and processor core cluster 1, wherein processor core cluster 0 may include processor core 0 and processor core 1, and processor core cluster 1 may include processor core 2 and processor core 3. The processor system also includes a multi-level cache, and Figure 1 only shows the last level cache (LLC). Multiple processor cores in the same processor core cluster share the same last level cache, wherein processor core 0 and processor core 1 correspond to last level cache 0, and processor core 2 and processor core 3 correspond to last level cache 1. In addition, the processor system also includes a home agent (HA), which stores a consistency directory to manage the consistency state of multiple last level caches.

[0046] Specifically, assuming that processor core 0 needs to access data, processor core 0 first searches in the last-level cache 0. Since the last-level cache 0 does not hit, the local agent queries the consistency directory and finds that the data accessed by processor core 0 is in the last-level cache 1. Then processor core 0 accesses the data in the last-level cache 1.

[0047] Applied to the above scenario, the access method provided by the embodiment of the present application will be described in detail below with reference to the accompanying drawings.

[0048] As shown in Figure 2, Figure 2 is a flow chart of an access method provided by an embodiment of the present application. The method includes the following steps S201 to S203.

[0049] S201: Obtain a first access request issued by a processor core when executing a first atomic instruction.

[0050] The first access request carries address information, and the address information is used to indicate the address of the first cache line in the cache.

[0051] Exemplarily, atomic instructions, which may also be referred to as hardware atomic instructions, are instructions that cannot be split by other execution threads, processes, interrupts, or signals, such as compare and swap (CAS) instructions, also known as conditional store instructions, which are known in the art and defined in some existing instruction sets. The CAS instruction allows atomic read and atomic write operations on shared memory. Specifically, the CAS instruction compares the value in the shared memory with the expected value, and performs a write operation if the value in the shared memory is equal to the expected value, and does not perform a write operation if the value in the shared memory is not equal to the expected value. One use of the CAS instruction is to filter data structures, such as linked lists and stacks.

[0052] Exemplarily, the processor core executing the first atomic instruction can implement an atomic operation, i.e., an operation that will not be interrupted during execution. An atomic operation can be understood as an indivisible operation that does not involve any context switching during execution, thereby ensuring thread serialization. The execution of the first atomic instruction can include one or more operations, such as a store operation, a compare-and-store operation, a compare-and-swap operation, a swap operation, a logical operation, an arithmetic operation, and a sorting barrier operation. Because atomic operations can ensure thread serialization, data synchronization between cores of a multi-core processor can be guaranteed.

[0053] For example, after the processor core issues a first access request, if the first access request is a request to read data, the processor core will first search in the local memory of the processor core (such as the first-level cache, the second-level cache, and the third-level cache). If the data corresponding to the first access request is not stored in the local memory, the local agent will obtain the first access request, and the local agent can query the consistency directory to obtain the destination of the first access request.

[0054] S202 : In response to the first access request, access the first cache line based on the address information, and obtain an address of a second cache line in the cache.

[0055] Exemplarily, the local agent may query the consistency directory based on the address information to determine that the destination of the first access request is the first cache line in the cache, wherein the first cache line may store data related to the address of the second cache line, and the local agent may obtain the address of the second cache line. In one example, the first cache line and the second cache line may form a stack, wherein the stack is a first in last out (FILO) data structure, and the first cache line may store a tail pointer of the stack. Thus, the local agent may obtain the address of the second cache line based on the address of the first cache line and the tail pointer.

[0056] S203 : Access the second cache line based on the address of the second cache line.

[0057] Exemplarily, the local agent may initiate an access request for the second cache line based on the address of the second cache line, where the access request carries the address of the second cache line, so that the local agent can operate on the second cache line, such as writing data to the second cache line or reading data in the second cache line.

[0058] Thus, the processor core can complete atomic access to two cache lines in a single atomic instruction, the first atomic instruction. Compared to requiring at least two atomic instructions to complete the access operation of two cache lines, the access method provided in the embodiment of the present application reduces the number of atomic instructions, can achieve data synchronization between multiple processor cores with fewer atomic instructions, and improve the performance of the processor system.

[0059] The first cache line and the second cache line are located in the same cache queue. The first cache line stores a first address offset, which is an offset between an address of the second cache line and an address of the first cache line.

[0060] Exemplarily, as shown in Figure 3, Figure 3 is a schematic diagram of a cache queue provided by an embodiment of the present application. Among them, the queue can adopt a first-in first-out (FIFO) mode, that is, the data that enters first goes out first, and the data that enters later goes out last. In addition, the queue can also adopt a stack mode. If the queue adopts the FIFO mode, and the first access request is an access request to write data to the second cache line, the first address offset stored in the first cache line can be understood as the tail element offset. If the queue adopts the FIFO mode, and the first access request is an access request to read data from the second cache line, the first address offset stored in the first cache line can be understood as the head element offset. In addition, the first cache line can also store the control mode of the queue, etc. Among them, the tail element offset, the head element offset and the control mode of the queue can be collectively referred to as the control information of the queue.

[0061] It is understandable that FIG3 also shows i data elements, namely data element 1, data element 2, data element 3, ..., data element i, where data element 1 is the head element and data element i is the tail element. Each data element can be a cache line, and each data element can also be a data block. In a specific example, the first cache line corresponds to the control information in FIG3, and the second cache line corresponds to data element i in FIG3. In another specific example, the first cache line corresponds to the control information in FIG3, and the second cache line corresponds to data element 1 in FIG3.

[0062] Optionally, as shown in FIG4 , FIG4 is a flow chart of another access method provided by an embodiment of the present application. S202 may include:

[0063] S2021 . In response to a first access request, access a first cache line based on address information to obtain a first address offset.

[0064] S2022: Obtain an address of a second cache line in the cache based on the address information and the first address offset.

[0065] For example, assuming that the address of the first cache line is X, the address of the second cache line can be X+first address offset. Thus, the first atomic instruction can first access the control information stored in the first cache line, index the address of the second cache line according to the first address offset in the control information, and then operate on the second cache line, such as writing data to the second cache line or reading data from the second cache line. Thus, under the premise of ensuring cache consistency, only one first atomic instruction is needed to access two cache lines. The first cache line can be regarded as a "lock variable" and the second cache line as a "data variable". The processing of the lock variable and the data variable is concentrated in the same atomic instruction, reducing the number of atomic instructions.

[0066] Optionally, the method may further include: updating the first address offset in the first cache line to obtain a second address offset, the second address offset being the offset between the address of the third cache line in the cache and the address of the first cache line, the first cache line, the second cache line and the third cache line being located in the same queue of the cache.

[0067] For example, continuing with the example of the queue in FIFO mode, if the first access request is a request to write data to the second cache line, and the second cache line is at the tail of the queue, then after the processor core executes the first access request issued by the first atomic instruction to write data to the second cache line, the third cache line is used as the new tail of the queue, and the updated second address offset is the tail element offset. If the first access request is a request to read data from the second cache line, and the second cache line is at the head of the queue, then after the processor core executes the first access request issued by the first atomic instruction to read data from the second cache line, the third cache line is used as the new head of the queue, and the updated second address offset is the head element offset.

[0068] For example, assuming the address of the first cache line is X, the address of the third cache line can be X + the second address offset. Thus, when the processor core executes the next atomic instruction, it can obtain the address of the third cache line when accessing the first cache line. In other words, each atomic instruction can achieve atomic access by first accessing the first cache line and then the target cache line.

[0069] Optionally, the method may also include: obtaining a second access request issued by the processor core to execute a second atomic instruction, the second access request carrying address information, accessing the first cache line based on the address information in response to the second access request, obtaining the address of the third cache line, and accessing the third cache line based on the address of the third cache line.

[0070] For example, after a processor core issues a second access request, if the second access request is a request to read data, the processor core will first search its local memory. If the local memory does not store the data corresponding to the second access request, the local agent will obtain the second access request and query the coherence directory to obtain the destination of the second access request. If the local agent determines that the destination of the second access request is a third cache line in the cache, the local agent will obtain the address of the third cache line and access the third cache line to obtain the data in the third cache line.

[0071] Thus, in the access method provided by the embodiments of the present application, each atomic instruction can access two cache lines, reducing multiple instructions that access two cache lines to a single instruction. This consolidates operations on lock variables and data variables into a single atomic instruction, making it easier to use. Furthermore, the location for processing shared memory access requests is fixed, reducing data transmission and improving processor system performance.

[0072] It is understandable that in order to implement the above functions, the electronic device includes hardware and / or software modules corresponding to the execution of each function. In combination with the algorithm steps of each example described in the embodiments disclosed herein, the present application can be implemented in the form of hardware or a combination of hardware and computer software. Whether a function is executed in the form of hardware or computer software driving hardware depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application in combination with the embodiments, but such implementation should not be considered to be beyond the scope of this application.

[0073] In this embodiment, the electronic device can be divided into functional modules according to the above-mentioned method example. For example, each functional module can be divided according to each function, or two or more functions can be integrated into a single processing module. The above-mentioned integrated modules can be implemented in the form of hardware. It should be noted that the module division in this embodiment is illustrative and is only a logical functional division. In actual implementation, other division methods may be used.

[0074] In the case of dividing the functional modules according to their functions, FIG5 shows a possible composition diagram of the access device 500 involved in the above embodiment. As shown in FIG5 , the access device 500 may include: an acquisition unit 501 and an access unit 502 .

[0075] The acquisition unit 501 may be used to support the access device 500 in executing the above-mentioned step S201 and / or other processes of the technology described herein.

[0076] The access unit 502 may be used to support the access device 500 in executing the above-mentioned steps S202 and S203 , and / or other processes of the technology described herein.

[0077] It should be noted that all relevant contents of each step involved in the above method embodiment can be referred to the functional description of the corresponding functional module and will not be repeated here.

[0078] The access device 500 provided in this embodiment is used to execute the above access method, and thus can achieve the same effect as the above implementation method.

[0079] In the case of an integrated unit, the access device 500 may include a processing module and a storage module. The processing module may be used to control and manage the operations of the access device 500, for example, to support the access device 500 in executing the steps performed by the acquisition unit 501 and the access unit 502. The storage module may be used to support the access device 500 in storing program code and data.

[0080] The processing module may be a processor or a controller. It may implement or execute the various exemplary logic blocks, modules, and circuits described in conjunction with the disclosure of this application. The processor may also be a combination that implements computing functions, such as a combination of one or more microprocessors, a combination of digital signal processing (DSP) and a microprocessor, and so on. The storage module may be a memory. The communication module may specifically be a device that interacts with other electronic devices, such as a radio frequency circuit, a Bluetooth chip, or a Wi-Fi chip.

[0081] As shown in Figure 6, Figure 6 is a schematic diagram of the structure of another processor system provided by an embodiment of the present application. The processor system 600 includes a memory manager 601 and multiple processor cores 602. Figure 6 shows processor cores 602_1, 602_2, ..., and 602_n. The outputs of the multiple processor cores 602 can be coupled to the memory manager 601, and the outputs of the memory manager 601 can also be coupled to a memory.

[0082] Optionally, one of the multiple processor cores 602 is configured to: execute an atomic instruction to obtain an access request, where the access request carries address information, where the address information is used to indicate an address of a first cache line in the cache. The memory manager 601 is configured to respond to the access request, access the first cache line based on the address information, obtain an address of a second cache line in the cache, and access the second cache line based on the address of the second cache line.

[0083] For example, the address of the second cache line is stored in the first cache line. The first cache line is first accessed based on the first access request to obtain the address of the second cache line, and then the second cache line is accessed based on the address of the second cache line. That is, the processor core can complete atomic access to two cache lines in one atomic instruction. Compared with the operation that requires at least two atomic instructions to complete the access operation of two cache lines, the processor system provided by the embodiment of the present application changes from multiple instructions to a single instruction, and concentrates the operations on lock variables and data variables in the same atomic instruction, reducing the number of atomic instructions. It can also achieve data synchronization between multiple processor cores with fewer atomic instructions, thereby improving the performance of the processor system.

[0084] An embodiment of the present application also provides an electronic device, which includes one or more interface circuits and one or more processor systems, and the interface circuits and the processor systems are interconnected via lines.

[0085] The present application also provides a chip system including one or more processors and one or more memories. The one or more memories are coupled to the one or more processors and are used to store computer program code. The computer program code includes computer instructions. When the one or more processors execute the computer instructions, the electronic device executes the above-mentioned related method steps to implement the access method in the above-mentioned embodiment.

[0086] An embodiment of the present application further provides a computer storage medium storing computer instructions. When the computer instructions are executed on an electronic device, the electronic device executes the above-mentioned related method steps to implement the access method in the above-mentioned embodiment.

[0087] An embodiment of the present application further provides a computer program product. When the computer program product is run on a computer, the computer is caused to execute the above-mentioned related steps to implement the access method executed by the electronic device in the above-mentioned embodiment.

[0088] Among them, the access device, processor system, electronic device, computer storage medium, computer program product or chip provided in this embodiment are all used to execute the corresponding methods provided above. Therefore, the beneficial effects that can be achieved can refer to the beneficial effects in the corresponding methods provided above, and will not be repeated here.

[0089] Through the description of the above implementation methods, technical personnel in the relevant field can understand that for the convenience and simplicity of description, only the division of the above-mentioned functional modules is used as an example. In actual applications, the above-mentioned functions can be distributed and completed by different functional modules as needed, that is, the internal structure of the device can be divided into different functional modules to complete all or part of the functions described above.

[0090] In the several embodiments provided in this application, it should be understood that the disclosed devices and methods can be implemented in other ways. For example, the device embodiments described above are merely schematic. For example, the division of the modules or units is merely a logical function division. In actual implementation, there may be other division methods, such as multiple units or components can be combined or integrated into another device, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of devices or units, which can be electrical, mechanical or other forms.

[0091] The units described as separate components may or may not be physically separate, and the components shown as units may be one physical unit or multiple physical units, that is, they may be located in one place or distributed in multiple places. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0092] In addition, the functional units in the various embodiments of the present application may be integrated into a single processing unit, or each unit may exist physically separately, or two or more units may be integrated into a single unit. The aforementioned integrated units may be implemented in the form of hardware or software functional units.

[0093] If the integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a readable storage medium. Based on this understanding, the technical solution of the embodiment of the present application is essentially or the part that contributes to the prior art or all or part of the technical solution can be embodied in the form of a software product, which is stored in a storage medium and includes several instructions for enabling a device (which can be a single-chip microcomputer, chip, etc.) or a processor (processor) to execute all or part of the steps of the method described in each embodiment of the present application. The aforementioned storage medium includes: various media that can store program codes, such as a USB flash drive, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk or an optical disk.

[0094] The above content is merely a specific embodiment of the present application, but the scope of protection of the present application is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in this application should be included in the scope of protection of the present application. Therefore, the scope of protection of the present application should be based on the scope of protection of the claims.

Claims

1. An access method, characterized in that: The method comprises: Obtaining a first access request issued by a processor core executing a first atomic instruction, where the first access request carries address information, where the address information is used to indicate an address of a first cache line in a cache; In response to the first access request, access the first cache line based on the address information to obtain an address of a second cache line in the cache; The second cache line is accessed based on the address of the second cache line.

2. The method according to claim 1, characterized in that The first cache line and the second cache line are located in the same queue of the cache. The first cache line stores a first address offset, which is an offset between an address of the second cache line and an address of the first cache line.

3. The method according to claim 2, characterized in that The step of accessing the first cache line based on the address information in response to the first access request to obtain an address of a second cache line in the cache includes: In response to the first access request, access the first cache line based on the address information to obtain the first address offset; An address of the second cache line in the cache is obtained based on the address information and the first address offset.

4. The method according to claim 3, characterized in that The method further comprises: The first address offset in the first cache line is updated to obtain a second address offset, where the second address offset is an offset between an address of a third cache line in the cache and an address of the first cache line, and the first cache line, the second cache line, and the third cache line are located in a same queue of the cache.

5. The method according to claim 4, characterized in that The method further comprises: Obtaining a second access request issued by the processor core when executing the second atomic instruction, where the second access request carries the address information; In response to the second access request, access the first cache line based on the address information to obtain the address of the third cache line; The third cache line is accessed based on the address of the third cache line.

6. An access device, characterized in that: include: an acquiring unit, configured to acquire a first access request issued by a processor core executing a first atomic instruction, wherein the first access request carries address information, and the address information is used to indicate an address of a first cache line in a cache; an access unit, configured to access the first cache line based on the address information in response to the first access request, and obtain an address of a second cache line in the cache; The access unit is further configured to access the second cache line based on the address of the second cache line.

7. The access device according to claim 6, characterized in that The first cache line and the second cache line are located in the same queue of the cache. The first cache line stores a first address offset, which is an offset between an address of the second cache line and an address of the first cache line.

8. The access device according to claim 7, characterized in that The access unit is specifically used for: In response to the first access request, access the first cache line based on the address information to obtain the first address offset; An address of the second cache line in the cache is obtained based on the address information and the first address offset.

9. The access device according to claim 8, characterized in that The access unit is further configured to: The first address offset in the first cache line is updated to obtain a second address offset, where the second address offset is an offset between an address of a third cache line in the cache and an address of the first cache line, and the first cache line, the second cache line, and the third cache line are located in a same queue of the cache.

10. The access device according to claim 9, characterized in that The acquiring unit is further configured to: acquire a second access request issued by the processor core when executing the second atomic instruction, wherein the second access request carries the address information; The access unit is further configured to: in response to the second access request, access the first cache line based on the address information to obtain the address of the third cache line; The access unit is further configured to access the third cache line based on the address of the third cache line.

11. A processor system, characterized in that: include: Memory manager and multiple processor cores; One of the plurality of processor cores is configured to: execute an atomic instruction to obtain an access request, where the access request carries address information, and the address information is configured to indicate an address of a first cache line in a cache; The memory manager is used to: In response to the access request, access the first cache line based on the address information to obtain an address of a second cache line in the cache; The second cache line is accessed based on the address of the second cache line.

12. An electronic device, characterized in that: The system comprises one or more interface circuits and one or more processor systems according to claim 11, wherein the interface circuits and the processor systems are interconnected via lines.

13. A computer-readable storage medium, characterized in that When the computer instructions are executed on an electronic device, the electronic device is caused to execute the method according to any one of claims 1 to 5.

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