Delta-sigma modulator and associated electromagnetic radiation detection system

Abstract

The invention relates to a delta-sigma modulator (10a) for modulating an electric current (Idet) received on a charge transfer node (NT) for an integration period, wherein a phase generator (12a) is configured so as to obtain, each time the voltage (Vint) of the charge transfer node exceeds the constant threshold voltage (Vth), multiple cycles of at least two phases:  a first phase of charging an elementary charge into an injection capacitor (Ci); and  a second phase of transferring the elementary charge from the injection capacitor (Ci) to a storage capacitor (Cint); all of the elementary charges transferred into the storage capacitor (Cint) in each cycle forming a predetermined quantity of charges.

Description

[0001] DELTA-SIGMA MODULATOR AND ASSOCIATED ELECTROMAGNETIC RADIATION DETECTION SYSTEM

[0002] TECHNICAL FIELD

[0003] The invention relates to a Delta-Sigma modulator, i.e. a system configured to convert an analog signal into a digital signal using a charge transfer circuit based on an injection capacitor. The structure of a Delta-Sigma modulator is conventionally designed to be integrated into a small silicon area, typically a pixel of a matrix.

[0004] Thus, the invention can be used to form an electromagnetic radiation detection system, for example making it possible to measure the intensity of the current received at a charge transfer node.

[0005] STATE OF THE ART

[0006] To read the pixels of a matrix, it is classic to integrate a current measured on each pixel and to store the result of this integration in an analog storage source, typically a storage capacitor.

[0007] However, due to the limitation of the pixel pitch of detectors, it may be difficult for some applications to integrate a storage capacitor to store all the integrated charges in each pixel. To address this technical problem, one solution is to convert the integrated charge into a digital value.

[0008] Typically, this numerical value can be constructed by counting several predetermined charges in a storage capacitor so that the sum of the accumulated predetermined charges represents the integrated current.

[0009] To do this, as illustrated in Figure 1 of the prior art, the predetermined charges can be accumulated in an injection capacitor Ci and transferred at each activation of a comparator 13 into the storage capacitor Cint. For example, in the Delta-Sigma modulator 100 illustrated in Figure 1 of the prior art, the current Idet received on the charge transfer node NT is integrated into the storage capacitor Cint. When the storage capacitor Cint is not capable of integrating all the charges coming from the current Idet, the storage capacitor Cint must be charged by predetermined charges to avoid its overflow. To do this, the voltage Vint across the storage capacitor is compared to a reference value Vth in the comparator 13 and, when the voltage Vint exceeds the reference value Vth, a transfer of predetermined charges is carried out into the storage capacitor Cint.To do this, the output s of the comparator 13 feeds a phase generator 12, configured to generate two phases PHI1 and PHI2. The two phases feed a charging circuit 14 of the injection capacitor Ci and a charge transfer circuit 15 between the injection capacitor Ci and the storage capacitor Cint.

[0010] The phase generator 12 controls the charging circuit 14 and the charge transfer circuit 15 so as to carry out at least two phases at each activation, that is to say when the current Idet exceeds the threshold value: a phase of charging the injection capacitor Ci and a phase of transferring the charges from the injection capacitor Ci into the storage capacitor Cint.

[0011] As illustrated in Figure 2, the injection capacitor Ci can be made from a MOS T2 type transistor of CMOS technology. Indeed, to obtain an implementation of an electronic circuit with a limited surface, it is known to use CMOS technology, for "Complementary metal-oxide-semiconductor" in the English literature.

[0012] This injection capacitor T2 comprises a gate supplied by a bias voltage VBIAS. In addition, the charging circuit 14 also comprises a transistor T1 whose gate is supplied by a bias voltage VBIAS 1 while the other terminals, the source and the drain, are connected to the phase PHI1 and to the injection capacitor Ci.

[0013] A transistor T3 realizes the charge transfer circuit 15. Thus, the gate of the transistor T3 is powered by the phase PHI2 while the other terminals, the source and the drain, are connected to the injection capacitor Ci and to the charge transfer node NT. In the example of Figure 2, the Delta-Sigma modulator 101 integrates a phase generator 12a configured to perform a cycle of three phases at each activation, that is to say when the current Idet exceeds the threshold value.

[0014] In a first precharge phase, the injection capacitor Ci is charged by placing phases PHI1 and PHI2 in the high state. In this first phase, transistor T1 is on and transistor T3 is off, so that the injection capacitor Ci is charged to the high state of phase PHI1.

[0015] In a second discharge phase, phase PHI1 is placed in the low state and the injection capacitor Ci discharges until the voltage across the injection capacitor Ci is substantially equal to VBIAS1 plus the threshold voltage of transistor Tl.

[0016] In a third transfer phase, phase PHI2 is placed in the low state and transistor T3 becomes conductive, so that a predetermined charge stored in the injection capacitor Ci is transferred into the storage capacitor Cint.

[0017] These three phases can be repeated several times during the integration phase, during which the current Idet continues to be integrated on the charge transfer node NT. At the end of this integration process and the multiple predetermined charges transferred, the residual charge on the charge transfer node NT can also be measured and associated with the number of predetermined charges transferred into the storage capacitor Cint.

[0018] In the example of figures 1 and 2, the storage capacitor Cint is connected between the charge transfer node NT and the ground GND while the injection capacitor Ci is connected between the charge and charge transfer circuits 14, 15 and a bias voltage VBIAS.

[0019] Thus, in these examples, the charge transfer node NT also receives the current to be integrated and therefore performs the function of an integration node. Alternatively, as illustrated in Figure 3 and described in US Patent 9,628,105, it is possible to place the storage capacitor Cint between the bias voltage VBIAS and a charge transfer node NT, also receiving the current Idet to be integrated.

[0020] In this example, the signal PHI1 controls a controlled switch placed in parallel with the injection capacitor Ci so as to form the charging circuit 14 while the charge transfer circuit 15 is produced by a switch controlled by the signal PHI2, associated with a dynamic resistor 16.

[0021] With the Delta-Sigma modulator 102 of Figure 3, the phase generator 12 performs a cycle of two phases at each activation: a charging phase and a charge transfer phase. These two phases also allow predetermined charges to be transferred into the storage capacitor Cint, at each activation of the comparator 13.

[0022] These embodiments of figures 1 to 3 of the state of the art effectively make it possible to limit the capacity of the storage capacitor Cint to integrate high current levels on the charge transfer node NT.

[0023] However, to transmit sufficiently large predetermined charges, it is necessary to use a large surface area to realize the injection capacitor Ci. By combining the surface area necessary to realize the injection capacitor Ci and the storage capacitor Cint, it can be difficult to integrate the charge transfer circuit 100-102 into the pixels of a matrix.

[0024] The technical problem of the invention is to propose a charge transfer circuit with a reduced implantation surface.

[0025] STATEMENT OF THE INVENTION

[0026] To address this technical problem, the invention proposes to carry out several cycles of at least two phases at each activation of the comparator. Thus, the predetermined charges transmitted at each activation of the comparator correspond to the sum of several elementary charges transmitted at each cycle of at least two phases of the Delta-Sigma modulator. These elementary charges being reduced, it becomes possible to limit the implantation surface of the injection capacitor and, thus, of the Delta-Sigma modulator.

[0027] To this end, according to a first aspect, the invention relates to a Delta-Sigma modulator of an electric current received on a charge transfer node during an integration time, said Delta-Sigma modulator comprising: a storage capacitor connected to said charge transfer node; a comparator whose output voltage is dependent on the voltage difference between the voltage of the charge transfer node and a constant threshold voltage; an injection capacitor; a charging circuit configured to charge elementary charges in the injection capacitor; a charge transfer circuit configured to transfer the elementary charges from the injection capacitor to the storage capacitor; and a phase generator connected to the output voltage of the comparator and configured to generate charging and transfer signals which control the charging circuit and the charge transfer circuit.

[0028] The invention is characterized in that the phase generator is configured so as to obtain, at each activation of the comparator, several cycles of at least two phases:

[0029] ■ a first phase of charging an elementary charge in the injection capacitor; and

[0030] ■ a second phase of transfer of said elementary charge from the injection capacitor to the storage capacitor; all of the elementary charges transferred into the storage capacitor at each cycle forming a predetermined quantity of charges.

[0031] The invention therefore proposes to consecutively transfer several elementary charges at each activation of the comparator to obtain an overall transfer of a predetermined quantity of charges. This strategy makes it possible to reduce the size and therefore the implantation surface of the injection capacitor. For the purposes of the invention, the expression "at each activation of the comparator" means "each time the voltage of the charge transfer node exceeds the constant threshold voltage". In other words, each activation of the comparator corresponds to the state in which the voltage of the charge transfer node exceeds the constant threshold voltage, this state inducing the triggering of several cycles composed of at least two phases. This so-called "active" state corresponds to an "activation signal" triggering the cycles via the phase generator.In practice and depending on the configuration of the comparator, the output signal of the comparator can be at a voltage corresponding to a low state when the voltage of the charge transfer node exceeds the constant threshold voltage.

[0032] Furthermore, to reduce the implantation surface, the storage capacitor and / or the injection capacitor are preferably made of a MOS transistor.

[0033] To carry out the different cycles of the phase generator, it is possible to use a specific phase generator or to reuse a phase generator from the state of the art by using a circuit for multiplying the activation signal transmitted by the comparator which is therefore representative of the signal at the output of the comparator when the voltage of the charge transfer node exceeds the constant threshold voltage. This multiplication circuit is for example a circuit for memorizing the active state of the activation signal with a clock configured so that the phase generator produces several cycles at each activation of the comparator.

[0034] In this embodiment, the Delta-Sigma modulator also integrates a circuit for storing the state of the output voltage connected between the comparator and the phase generator, the storage duration of the storage circuit being adapted so that the phase generator generates several cycles.

[0035] Furthermore, the comparator may also correspond to a comparator of the prior art, typically a comparator having two inputs and one output; a first input being connected to said charge transfer node and a second input being brought to said constant threshold voltage; the output voltage being dependent on the sign of the voltage difference between the voltage of the charge transfer node and said constant threshold voltage. Furthermore, the comparator may also correspond to a comparator controlled by one or more clocks; the clock(s) defining the time of evaluation of the inputs, and the duration of holding the result at the output. The duration of holding the result at the output allowing the phase generator to generate several cycles.

[0036] As for the charge and charge transfer circuits, they can correspond to all known circuits.

[0037] For example, according to the embodiment of Figure 2 of the prior art, the charging circuit consists of a single MOS transistor whose gate is supplied by a bias voltage and the other terminals, the source and the drain, are connected to the charging signal and to the injection capacitor.

[0038] In this same embodiment, the charge transfer circuit consists of a single MOS transistor whose gate is powered by the transfer signal and the other terminals, the source and the drain, are connected to the injection capacitor and the charge transfer node.

[0039] With this embodiment, the phase generator is configured so as to obtain, at each activation of the comparator, several cycles of three phases:

[0040] ■ a first phase of charging the injection capacitor to a first charge level controlled by the charge signal;

[0041] ■ a second phase of discharging the injection capacitor to a second charge level controlled by the charge signal; and

[0042] ■ a third phase of transfer of charges from the injection capacitor controlled by the transfer signal.

[0043] For the purposes of the invention, the charge signal "controls" the first and second phases while the bias voltage and the transfer signal "control" the third phase because the amount of elementary charge transferred depends on the voltage level of the bias voltage and the transfer signal. This term is applied for the different aspects of the invention. For the purposes of the invention, "at each activation of the comparator" means "at each exceedance of the voltage of the charge transfer node with respect to the constant threshold voltage".

[0044] Alternatively, according to the embodiment of figure 3 of the state of the art, the charging circuit consists of a switch controlled by the charging signal, said switch being short-circuited across the terminals of the injection capacitor, one of these terminals being connected to a bias voltage; the storage capacitor being connected between said bias voltage and said charge transfer node.

[0045] With this embodiment, the charge transfer circuit consists of a dynamic resistor connected in series with a switch controlled by the transfer signal, the dynamic resistor and the switch controlled by the transfer signal being connected between the charge transfer node and the terminal of the injection capacitor which is not connected to said bias voltage.

[0046] This embodiment makes it possible in particular to use only two phases, charging and transfer, in each elementary charge transfer cycle.

[0047] According to a second aspect, the invention relates to an electromagnetic radiation detection system comprising: an array of detection elements producing an electric current as a function of the electromagnetic radiation; and a Delta-Sigma modulator according to the first aspect of the invention, associated with each detection element, the electric current generated by said detection element being collected on said charge transfer node.

[0048] SUMMARY DESCRIPTION OF THE FIGURES

[0049] The manner of carrying out the invention as well as the advantages which result therefrom will emerge clearly from the following embodiments, given for informational but non-limiting purposes, supported by figures 1 to 7 in which:

[0050] Figure 1 is a schematic representation of a state-of-the-art Delta-Sigma modulator; Figure 2 is a schematic representation of a first implementation of the state-of-the-art Delta-Sigma modulator of Figure 1;

[0051] Figure 3 is a schematic representation of a second implementation of the Delta-Sigma modulator of Figure 1 of the prior art;

[0052] Figure 4 is a schematic representation of a Delta-Sigma modulator according to a first embodiment of the invention;

[0053] Figure 5 is a schematic representation of a Delta-Sigma modulator according to a second embodiment of the invention;

[0054] Figure 6 is a schematic representation of the signals of the Delta-Sigma modulator of Figure 4 according to a first time scale; and

[0055] Figure 7 is a schematic representation of the Delta-Sigma modulator signals of Figure 4 on a second time scale.

[0056] DETAILED DESCRIPTION OF THE INVENTION

[0057] Figure 4 illustrates an embodiment of a Delta-Sigma modulator 10a according to the invention. This Delta-Sigma modulator 10a makes it possible to accumulate and transfer predetermined charges between an injection capacitor Ci and a storage capacitor Cint, each time a comparator 13a is activated.

[0058] As illustrated in Figure 1 of the prior art, the current Idet received on the charge transfer node NT is integrated into the storage capacitor Cint. When the storage capacitor Cint is not capable of integrating all the charges coming from the current Idet, the storage capacitor Cint must be charged by predetermined charges to avoid its overflow. To do this, the voltage Vint across the storage capacitor is compared with a reference value Vth in the comparator 13a and, when the voltage Vint exceeds the reference value Vth, a transfer of predetermined charges is carried out in the storage capacitor Cint.

[0059] According to the invention, to carry out this transfer of predetermined charges, a phase generator 12a is implemented so as to obtain, each time the voltage Vint exceeds the reference value Vth, several cycles of at least two phases. In a first charging phase, an elementary charge is charged into the injection capacitor Ci. In a second transfer phase, the elementary charge stored in the injection capacitor Ci is transferred into the storage capacitor Cint. All of the elementary charges transferred into the storage capacitor Cint at each cycle form the predetermined quantity of charges.

[0060] To do this, the output s of the comparator 13a feeds the phase generator 12a, configured to generate two phases PHI1 and PHI2. The two phases feed a charging circuit 14 of the injection capacitor Ci and a charge transfer circuit 15 between the injection capacitor Ci and the storage capacitor Cint.

[0061] The phase generator 12 controls the charging circuit 14 and the charge transfer circuit 15 so as to produce at least two phases at each activation of the comparator 13a, that is to say when the current Idet exceeds the threshold value: a charging phase of the injection capacitor Ci and a charge transfer phase of the injection capacitor Ci into the storage capacitor Cint. As illustrated in Figure 2, the injection capacitor Ci can be produced from a MOS T2 type transistor of CMOS technology. Indeed, to obtain an implementation of an electronic circuit with a limited surface, it is known to use CMOS technology, for "Complementary metal-oxide-semiconductor" in the English literature.

[0062] This injection capacitor T2 comprises a gate supplied by a bias voltage VBIAS. Furthermore, the charging circuit 14 and the charge transfer circuit 15 of FIG. 4 can also be produced as illustrated in FIG. 2. In this embodiment, the charging circuit 14 also comprises a transistor T1 whose gate is supplied by a bias voltage VBIAS1 while the other terminals, the source and the drain, are connected to the phase PHI1 and to the injection capacitor Ci.

[0063] A transistor T3 realizes the charge transfer circuit 15. Thus, the gate of the transistor T3 is supplied by the phase PHI2 while the other terminals, the source and the drain, are connected to the injection capacitor Ci and to the charge transfer node NT.

[0064] In this example, the Delta-Sigma modulator 10a can integrate a phase generator 12a configured to perform several cycles of three phases each time the comparator 13a is activated, i.e. when the current Idet exceeds the threshold value. In a first precharge phase, the injection capacitor Ci is charged by placing the phases PHI1 and PHI2 in the high state. In this first phase, the transistor T1 is on and the transistor T3 is off, so that the injection capacitor Ci is therefore charged to the high state of the phase PHI1.

[0065] In a second discharge phase, phase PHI1 is placed in the low state and the injection capacitor Ci discharges until the voltage across the injection capacitor Ci is substantially equal to VBIAS1 plus the threshold voltage of transistor Tl.

[0066] In a third transfer phase, phase PHI2 is placed in the low state, transistor T3 becomes conductive and injection capacitor Ci discharges until the voltage across injection capacitor Ci is substantially equal to the low state voltage of phase PHI2 plus the threshold voltage of transistor T3, so that an elementary charge stored in injection capacitor Ci is transferred to storage capacitor Cint.

[0067] The voltage Vout at the output of comparator 13a, the phases PHI1 and PHI2, as well as the voltage on the charge transfer node NT are represented in Figures 6 and 7 with two different time scales. These figures allow us to observe that several consecutive elementary charge transfers are carried out at each activation of comparator 13a, when the voltage Vout at the output of comparator 13a goes to the low state.

[0068] In the embodiment of figures 6 and 7, whatever the state of the voltage Vout at the output of the comparator 13a, the phase PHI1 has a constant cycle making it possible to carry out the precharge and discharge phases of the injection capacitor Ci. Alternatively, the phase PHI1 can be activated only when the comparator 13a is activated.

[0069] The elementary charges stored in the injection capacitor Ci at the end of the discharge phase are only transferred to the storage capacitor Cint when the voltage Vout at the output of the comparator 13a is in the low state, placing the signal PHI2 in the low state. This voltage Vout remains in the low state for several cycles, causing several cycles of the signal PHI2, typically four cycles in the example of figures 6 and 7. Thus, to form the predetermined charge, four elementary charges are transferred at each activation of the comparator 13a, when the voltage Vout at the output of the comparator 13a goes to the low state.

[0070] As illustrated in Figure 6, these four cycles of three phases can be repeated several times during the integration phase, during which the current Idet continues to be integrated on the charge transfer node NT. At the end of this integration process and the multiple predetermined charges transferred, the residual charge on the charge transfer node NT can also be measured and associated with the number of predetermined charges transferred into the storage capacitor Cint.

[0071] To maintain the activation of the phase generator 12a over several cycles, it is possible to use a comparator 13a controlled by one or more clocks H1, as illustrated in FIG. 4. In this embodiment, the period H1 is determined so that the time of evaluation of the inputs e+, e-, and the duration of maintaining the result on said output s allow the phase generator 12a to generate several cycles.

[0072] Alternatively, as illustrated in Figure 5, it is possible to use an asynchronous comparator 13 by storing the state of the output voltage Vout. To do this, this storage circuit 17 can correspond to a simple D flip-flop. As in the example of Figure 4, this storage circuit 17 is controlled by a clock H2 determined so as to generate several cycles at each activation of the comparator 13.

[0073] In addition to the modification of the means for activating the phase generator 12 over several cycles, the embodiment of Figure 5 also differs from the embodiment of Figure 4 by the realization of the charging and transfer circuits and the connection of the storage capacitor Cint.

[0074] In the example of Figure 4, the storage capacitor Cint is connected between the charge transfer node NT and the ground GND while the injection capacitor Ci is connected between the charge and charge transfer circuits 14, 15 and a bias voltage VBIAS. Alternatively, as illustrated in Figure 5, it is possible to place the storage capacitor Cint between the bias voltage VBIAS and a charge transfer node NT, also receiving the current Idet to be integrated. Indeed, it is possible to connect the storage capacitor Cint and the injection capacitor Ci to different voltage sources VBIAS, GND without changing the invention. It is even possible to use variable voltage sources.

[0075] In the example of Figure 5, as illustrated in the embodiment of Figure 3 of the prior art, the signal PHI1 can control a controlled switch placed in parallel with the injection capacitor Ci so as to form the charging circuit 14 while the charge transfer circuit 15 can be produced by a switch controlled by the signal PHI2, associated with a dynamic resistor 16.

[0076] With the Delta-Sigma modulator 10b of Figure 5, the phase generator 12 performs several two-phase cycles at each activation of the comparator 13: a charging phase and a charge transfer phase. These multiple two-phase cycles also make it possible to transfer predetermined charges into the storage capacitor Cint, at each activation of the comparator 13.

[0077] These embodiments of Figures 4 and 5 make it possible to reduce the capacitance and therefore the implantation surface of the injection capacitor Ci, and thus to reduce the size of the pixel integrating the Delta-Sigma modulator 10a-10b. Similarly, the gain in implantation surface of the injection capacitor Ci can be used in the same pixel size to improve the performance of the Delta-Sigma modulator 10a-10b by allocating more surface area to the storage capacitor Cint, which makes it possible to increase the storable charge and reduce consumption.

[0078] In doing so, the Delta-Sigma modulator 10a-10b can more easily be integrated into the pixels of a matrix, for example to form an electromagnetic radiation detection system. This electromagnetic radiation detection system can conventionally comprise a matrix of detection elements producing an electric current Idet as a function of the electromagnetic radiation. A Delta-Sigma modulator 10a-10b according to the invention is then associated with each detection element, the electric current generated by each detection element Idet being collected on the charge transfer node NT.

[0079] The invention therefore also makes it possible to more simply produce a reading circuit integrated into the surface of each pixel of an electromagnetic radiation detection system.

Claims

CLAIMS 1. Delta-Sigma modulator (10a- 10b) of an electric current (Idet) received on a charge transfer node (NT) during an integration time, said Delta-Sigma modulator (10a- 10b) comprising: a storage capacitor (Cint) connected to said charge transfer node (NT); a comparator (13, 13a) of which an output voltage (Vout) is dependent on the voltage difference between the voltage of the charge transfer node (Vint) and a constant threshold voltage (Vth); an injection capacitor (Ci); a charging circuit (14) configured to charge elementary charges in the injection capacitor (Ci); a charge transfer circuit (15) configured to transfer the elementary charges from the injection capacitor (Ci) to the storage capacitor (Cint);and a phase generator (12, 12a) connected to the output voltage (Vout) of the comparator (13, 13a) and configured to generate charge (PHI1) and transfer (PHI2) signals which control the charge circuit (14) and the charge transfer circuit (1); characterized in that the phase generator (12, 12a) is configured so as to obtain, each time the voltage of the charge transfer node (Vint) exceeds the constant threshold voltage (Vth), several cycles of at least two phases:; ■ a first phase of charging an elementary charge in the injection capacitor (Ci); and ■ a second phase of transfer of said elementary charge from the injection capacitor (Ci) to the storage capacitor (Cint); all of the elementary charges transferred into the storage capacitor (Cint) at each cycle forming a predetermined quantity of charges.

2. Delta-Sigma modulator according to claim 1, in which the Delta-Sigma modulator (10a-10b) also integrates a storage circuit (17) for the state of the output voltage (Vout) connected between the comparator (13, 13a) and the phase generator (12, 12a), the storage duration (H2) of the storage circuit (17) being adapted so that the phase generator (12, 12a) generates several cycles.

3. Delta-Sigma modulator according to claim 1 or 2, wherein the storage capacitor (Cint) and / or the injection capacitor (Ci) consist of a MOS transistor.

4. Delta-Sigma modulator according to one of claims 1 to 3, wherein the comparator (13, 13 a) has two inputs (e+, e-) and one output (s); a first input (e+, e-) being connected to said charge transfer node (NT) and a second input (e+, e-) being brought to said constant threshold voltage (Vth); the output voltage (Vout) being dependent on the sign of the voltage difference between the voltage of the charge transfer node (Vint) and said constant threshold voltage (Vth).

5. Delta-Sigma modulator according to claim 4, wherein the comparator (13a) corresponds to a comparator controlled by one or more clocks (Hl); the clock(s) (Hl) defining the time of evaluation of the inputs (e+, e-), and the duration of maintaining the result on said output (s) so that the duration of maintaining the result on said output (s) allows the phase generator (12, 12a) to generate several cycles.

6. Delta-Sigma modulator according to one of claims 1 to 5, in which the charging circuit (14) consists of a single MOS transistor (Tl) whose gate is supplied by a bias voltage (VBIAS1) and the other terminals, the source and the drain, are connected to the charging signal (PHI1) and to the injection capacitor (Ci).

7. Delta-Sigma modulator according to one of claims 1 to 6, in which the charge transfer circuit (15) consists of a single MOS transistor (T3) whose gate is supplied by the transfer signal (PHI2) and the other terminals, the source and the drain, are connected to the injection capacitor (Ci) and to the charge transfer node (NT).

8. Delta-Sigma modulator according to claims 6 and 7, wherein the phase generator (12, 12a) is configured so as to obtain, each time the voltage of the charge transfer node (Vint) exceeds the constant threshold voltage (Vth), several cycles of three phases: ■ a first phase of charging the injection capacitor (Ci) to a first charging level controlled by the charging signal (PHI1); ■ a second phase of discharging the injection capacitor (Ci) to a second charge level controlled by the charge signal (PHI1); and ■ a third phase of transfer of charges from the injection capacitor (Ci) controlled by the transfer signal (PHI2).

9. Delta-Sigma modulator according to one of claims 1 to 7, in which the charging circuit (14) consists of a switch controlled by the charging signal (PHI1), said switch being short-circuited across the terminals of the injection capacitor (Ci), one of the terminals being connected to a bias voltage (VBIAS); the storage capacitor (Cint) being connected between said bias voltage (VBIAS) and said charge transfer node (NT).

10. Delta-Sigma modulator according to claim 9, wherein the charge transfer circuit (15) consists of a dynamic resistor (16) connected in series with a switch controlled by the transfer signal (PHI2), the dynamic resistor (16) and the switch controlled by the transfer signal (PHI2) being connected between the charge transfer node (NT) and the terminal of the injection capacitor (Ci) which is not connected to said bias voltage (VBIAS).

11. Electromagnetic radiation detection system comprising: a matrix of detection elements producing an electric current (Idet) as a function of the electromagnetic radiation; and a Delta-Sigma modulator (10a-10b) according to one of claims 1 to 10, associated with each detection element, the electric current generated by said detection element (Idet) being collected on said charge transfer node (NT).

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