Semiconductor device

Abstract

Provided is a transistor having favorable electrical characteristics. This semiconductor device includes a transistor. The transistor has an oxide semiconductor layer. The oxide semiconductor layer has an indium oxide film. The indium oxide film has a transistor channel formation region and has crystal grains. No crystal grain boundary is observed in the channel formation region. The concentration of a first element in the channel formation region is 0.1 atomic percent or less. The first element is at least one of boron, aluminum, and gallium.

Description

Semiconductor Devices

[0001] 1. Field of the Invention One embodiment of the present invention relates to a semiconductor device, a memory device, a display device, and an electronic device. Another embodiment of the present invention relates to a manufacturing method of a semiconductor device.

[0002] One embodiment of the present invention is not limited to the above technical field, and examples of the technical field of one embodiment of the present invention include semiconductor devices, display devices, light-emitting devices, power storage devices, memory devices, electronic devices, lighting devices, input devices (e.g., touch sensors), input / output devices (e.g., touch panels), driving methods thereof, and manufacturing methods thereof.

[0003] In this specification and the like, a semiconductor device is a device that utilizes semiconductor characteristics, and refers to a circuit including a semiconductor element (transistor, diode, photodiode, etc.), a device having such a circuit, etc. Also, it refers to any device that can function by utilizing semiconductor characteristics. For example, an integrated circuit, a chip including an integrated circuit, and an electronic component in which a chip is housed in a package are examples of semiconductor devices. Furthermore, a memory device, a display device, a light-emitting device, a lighting device, and an electronic device may themselves be semiconductor devices and each may have a semiconductor device.

[0004] In recent years, the development of semiconductor devices has progressed, and semiconductor devices mainly use LSIs (Large Scale Integration), CPUs (Central Processing Units), memories (storage devices), etc. A CPU is an aggregate of semiconductor elements that have integrated circuits (including transistors and memories) formed into chips by processing a semiconductor wafer and on which electrodes serving as connection terminals are formed.

[0005] 2. Description of the Related Art Integrated circuits (ICs) such as LSIs, CPUs, or memories are mounted on circuit boards, such as printed wiring boards, and are used as components of various electronic devices.

[0006] Furthermore, a technology for constructing a transistor using a semiconductor thin film formed on a substrate having an insulating surface has attracted attention. Such transistors are widely applied to electronic devices such as integrated circuits (ICs) and display devices. While silicon-based semiconductor materials are widely known as semiconductor materials applicable to transistors, oxide semiconductors have also attracted attention as other materials.

[0007] Furthermore, it is known that a transistor using an oxide semiconductor has an extremely small leakage current in an off state. For example, Patent Document 1 discloses a CPU with low power consumption that utilizes the property of a transistor using an oxide semiconductor having a small leakage current. Furthermore, Patent Document 2 discloses a memory device that can retain stored data for a long period of time by utilizing the property of a transistor using an oxide semiconductor having a small leakage current.

[0008] In addition, with the recent trend toward smaller and lighter electronic devices, there is an increasing demand for higher density integrated circuits. There is also a demand for improved productivity of semiconductor devices including integrated circuits. For example, Patent Document 3 and Non-Patent Document 1 disclose a technique for increasing the density of integrated circuits by stacking a first transistor using an oxide semiconductor film and a second transistor using an oxide semiconductor film to provide multiple memory cells in an overlapping manner. Patent Document 4 discloses a technique for increasing the density of integrated circuits by vertically arranging the channel of a transistor using an oxide semiconductor film.

[0009] JP 2012-257187 A JP 2011-151383 A WO 2021 / 053473 JP 2013-211537 A

[0010] M. Oota et al. , “3D-Stacked CAAC-In-Ga-Zn Oxide FETs with Gate Length of 72nm”, IEDM Tech. Dig. , 2019, pp. 50-53C. Chen, S. P. Ong, “A universal graph deep learning interatomic potential for the periodic table”, Nat. Compute. Sci. , 2, 2022, pp. 718-728

[0011] An object of one embodiment of the present invention is to provide a transistor with favorable electrical characteristics.An object of one embodiment of the present invention is to provide a transistor with high on-state current.An object of one embodiment of the present invention is to provide a transistor with low parasitic capacitance.An object of one embodiment of the present invention is to provide a highly reliable transistor, semiconductor device, memory device, or display device.An object of one embodiment of the present invention is to provide a transistor, semiconductor device, or memory device that can be miniaturized or highly integrated.An object of one embodiment of the present invention is to provide a semiconductor device, memory device, or display device with low power consumption.An object of one embodiment of the present invention is to provide a memory device with high operating speed.An object of one embodiment of the present invention is to provide a display device with high definition or a high aperture ratio.An object of one embodiment of the present invention is to provide a manufacturing method of the transistor, semiconductor device, memory device, or display device.

[0012] Note that the description of these problems does not preclude the existence of other problems. One embodiment of the present invention does not necessarily have to solve all of these problems. Problems other than these can be extracted from the description in the specification, drawings, and claims.

[0013] One embodiment of the present invention is a semiconductor device including an oxide semiconductor layer. The oxide semiconductor layer includes an indium oxide film. The indium oxide film has a channel formation region of a transistor and has crystal grains. No grain boundaries are observed in the channel formation region. The concentration of a first element in the channel formation region is 0.1 atomic % or less. The first element is at least one of boron, aluminum, and gallium.

[0014] One embodiment of the present invention is a semiconductor device including an oxide semiconductor layer. The oxide semiconductor layer includes an indium oxide film. The indium oxide film includes a channel formation region of a transistor. The indium oxide film in the channel formation region is single crystalline. The concentration of a first element in the channel formation region is 0.1 atomic % or less. The first element is at least one of boron, aluminum, and gallium.

[0015] One embodiment of the present invention is a semiconductor device including an oxide semiconductor layer. The oxide semiconductor layer includes an indium oxide film. The indium oxide film has a channel formation region of a transistor, and the channel formation region includes first crystal grains and second crystal grains. The crystal orientation of the first crystal grains and the crystal orientation of the second crystal grains are the same or substantially the same. The concentration of a first element in the channel formation region is 0.1 atomic % or less. The first element is at least one of boron, aluminum, and gallium.

[0016] In the above semiconductor device, the band gap of the indium oxide film is preferably 2.5 eV or more and 3.7 eV or less.

[0017] In the above semiconductor device, the indium oxide film preferably has a region with a film thickness of 5 nm or more and 10 nm or less.

[0018] In the above semiconductor device, the indium oxide film is preferably a film formed by atomic layer deposition (ALD).

[0019] In the semiconductor device, the off-state current of the transistor is 1×10 per 1 μm of channel width at 85° C. −１８It is preferably less than A / μm.

[0020] In the semiconductor device, the cutoff frequency of the transistor is preferably 100 GHz or higher in a room temperature environment.

[0021] In the above semiconductor device, the indium oxide film is preferably provided on an oxide film having cubic crystal grains.

[0022] In the semiconductor device, it is preferable that the lattice mismatch between the crystal grains of the indium oxide film and the crystal grains of the oxide film be greater than or equal to 0% and less than or equal to 10%.

[0023] In the above semiconductor device, the oxide film preferably contains yttrium, zirconium, and oxygen.

[0024] In the above semiconductor device, the oxide film is preferably a film formed by a sputtering method.

[0025] In the semiconductor device, the oxide film preferably has a smaller thickness than the indium oxide film.

[0026] In the above semiconductor device, it is preferable that the oxide semiconductor layer include an In—Ga—Zn oxide film over an indium oxide film, and that the indium oxide film have higher permeability to either or both of oxygen atoms and hydrogen atoms than the In—Ga—Zn oxide film.

[0027] One embodiment of the present invention is a semiconductor device including an oxide semiconductor layer, a conductive layer, and an insulating layer having a portion located between the oxide semiconductor layer and the conductive layer. The conductive layer has a region functioning as a gate electrode of a transistor. The insulating layer has a region functioning as a gate insulating layer of the transistor. The oxide semiconductor layer includes an indium oxide film. The indium oxide film has crystal grains. No crystal grain boundaries are observed in a region of the indium oxide film that overlaps with the conductive layer and is at a depth of 1 nm or less from the surface on the insulating layer side.

[0028] One embodiment of the present invention is a semiconductor device including an oxide semiconductor layer, a conductive layer, and an insulating layer having a portion located between the oxide semiconductor layer and the conductive layer. The conductive layer has a region functioning as a gate electrode of a transistor. The insulating layer has a region functioning as a gate insulating layer of the transistor. The oxide semiconductor layer includes an indium oxide film. The indium oxide film overlaps with the conductive layer and includes first crystal grains and second crystal grains in a region at a depth of 1 nm or less from the surface on the insulating layer side. The crystal orientation of the first crystal grains and the crystal orientation of the second crystal grains are aligned or substantially aligned.

[0029] In the above semiconductor device, it is preferable that an oxide film overlap with the insulating layer with the oxide semiconductor layer sandwiched therebetween, and the oxide film have cubic crystal grains.

[0030] In the semiconductor device, it is preferable that the lattice mismatch between the crystal grains of the indium oxide film and the crystal grains of the oxide film be greater than or equal to 0% and less than or equal to 10%.

[0031] In the above semiconductor device, the oxide film preferably contains yttrium, zirconium, and oxygen.

[0032] In the semiconductor device, the oxide film preferably has a smaller thickness than the indium oxide film.

[0033] According to one embodiment of the present invention, a transistor with favorable electrical characteristics can be provided. According to one embodiment of the present invention, a transistor with large on-state current can be provided. According to one embodiment of the present invention, a transistor with small parasitic capacitance can be provided. According to one embodiment of the present invention, a highly reliable transistor, semiconductor device, memory device, or display device can be provided. According to one embodiment of the present invention, a transistor, semiconductor device, or memory device that can be miniaturized or highly integrated can be provided. According to one embodiment of the present invention, a semiconductor device, memory device, or display device with low power consumption can be provided. According to one embodiment of the present invention, a memory device with high operating speed can be provided. According to one embodiment of the present invention, a display device with high definition or a high aperture ratio can be provided. According to one embodiment of the present invention, a manufacturing method of the above transistor, semiconductor device, memory device, or display device can be provided.

[0034] Note that the description of these effects does not preclude the existence of other effects. One embodiment of the present invention does not necessarily have all of these effects. Effects other than these can be extracted from the description in the specification, drawings, and claims.

[0035] FIGS. 1A to 1F are cross-sectional views showing an example of a semiconductor device. FIGS. 1G and 1H are perspective views showing an example of a semiconductor device. FIGS. 2A and 2B are perspective views showing an example of a semiconductor device. FIG. 3A is a plan view showing an example of a semiconductor device. FIGS. 3B to 3D are cross-sectional views showing an example of a semiconductor device. FIGS. 4A and 4B are cross-sectional views showing an example of a semiconductor device. FIGS. 5A and 5B are cross-sectional views showing an example of a semiconductor device. FIGS. 6A to 6D are cross-sectional views showing an example of a semiconductor device. FIGS. 7A and 7B are cross-sectional views showing an example of a semiconductor device. FIGS. 8A and 8B are cross-sectional views showing an example of a semiconductor device. FIGS. 9A and 9B are cross-sectional views showing an example of a semiconductor device. FIG. 10A is a plan view showing an example of a semiconductor device. FIGS. 10B and 10C are cross-sectional views showing an example of a semiconductor device. FIGS. 11A and 11B are cross-sectional views showing an example of a semiconductor device. FIG. 12A is a plan view showing an example of a semiconductor device. FIGS. 12B to 12D are cross-sectional views showing an example of a semiconductor device. FIGS. 13A and 13B are cross-sectional views showing an example of a semiconductor device. 14A and 14B are cross-sectional views showing an example of a semiconductor device. FIG. 15 is a cross-sectional view showing an example of a semiconductor device. FIGS. 16A and 16B are cross-sectional views showing an example of a semiconductor device. FIGS. 17A and 17B are cross-sectional views showing an example of a semiconductor device. FIG. 18A is a plan view showing an example of a semiconductor device. FIGS. 18B to 18D are cross-sectional views showing an example of a semiconductor device. FIGS. 19A and 19B are cross-sectional views showing an example of a semiconductor device. FIG. 20A is a plan view showing an example of a semiconductor device. FIGS. 20B to 20D are cross-sectional views showing an example of a semiconductor device. FIG. 21A is a plan view showing an example of a semiconductor device. FIGS. 21B and 21C are cross-sectional views showing an example of a semiconductor device. FIG. 22A is a plan view showing an example of a semiconductor device. FIGS. 22B to 22D are cross-sectional views showing an example of a semiconductor device. FIG. 23A is a plan view showing an example of a semiconductor device. FIGS. 23B and 23C are cross-sectional views showing an example of a semiconductor device. FIG. 24A is a plan view showing an example of a semiconductor device. FIGS. 24B and 24C are cross-sectional views showing an example of a semiconductor device. FIG. 25A is a plan view showing an example of a semiconductor device.25B to 25D are cross-sectional views showing an example of a semiconductor device. FIGS. 26A and 26B are cross-sectional views showing an example of a semiconductor device. FIGS. 27A to 27C are cross-sectional views showing an example of a semiconductor device. FIG. 28A is a plan view showing an example of a semiconductor device. FIGS. 28B to 28D are cross-sectional views showing an example of a semiconductor device. FIG. 29A is a plan view showing an example of a semiconductor device. FIGS. 29B to 29D are cross-sectional views showing an example of a semiconductor device. FIGS. 30A to 30C are cross-sectional views showing an example of a semiconductor device. FIG. 31A is a plan view showing an example of a semiconductor device. FIGS. 31B to 31D are cross-sectional views showing an example of a semiconductor device. FIG. 32 is a cross-sectional view showing an example of a semiconductor device. FIG. 33A is a plan view showing an example of a memory device. FIGS. 33B and 33C are cross-sectional views showing an example of a memory device. FIG. 34A is a plan view showing an example of a memory device. FIGS. 34B and 34C are cross-sectional views showing an example of a memory device. FIGS. 35A to 35C are cross-sectional views showing an example of a memory device. FIGS. 36A and 36B are cross-sectional views showing an example of a memory device.

[0073] Fig. 37A is a plan view showing an example of a memory device. Fig. 37B is a cross-sectional view showing an example of a memory device. Fig. 38 is a cross-sectional view showing an example of a memory device. Fig. 39 is a cross-sectional view showing an example of a memory device. Fig. 40 is a block diagram illustrating a configuration example of a semiconductor device. Figs. 41A to 41G are diagrams illustrating an example of a circuit configuration of a memory cell. Figs. 42A and 42B are perspective views illustrating an example of a configuration of a semiconductor device. Fig. 43 is a block diagram illustrating a CPU. Figs. 44A and 44B are perspective views of a semiconductor device. Figs. 45A and 45B are perspective views of a semiconductor device. Figs. 46A and 46B are perspective views showing an example of a display device. Fig. 47 is a cross-sectional view showing an example of a display device. Fig. 48 is a cross-sectional view showing an example of a display device. Figs. 49A and 49B are diagrams illustrating an example of an electronic component. Figs. 50A to 50C are diagrams illustrating an example of a mainframe computer. Fig. 50D is a diagram illustrating an example of space equipment. Fig. 50E is a diagram illustrating an example of a storage system applicable to a data center. Figs. 51A to 51F are diagrams illustrating an example of electronic equipment. 52A to 52G are diagrams showing an example of an electronic device.53A to 53F are diagrams showing an example of an electronic device. FIG. 54 is a diagram showing band dispersion of indium oxide. FIGS. 55A to 55D are diagrams explaining electron density. FIGS. 56A to 56D are diagrams explaining electron density. FIGS. 57A to 57D are diagrams explaining a calculation model. FIGS. 58A to 58C are diagrams explaining a calculation model. FIGS. 59A and 59B are diagrams explaining HAADF-STEM images of a sample according to an example. FIG. 60 is a diagram explaining HAADF-STEM images of a sample according to an example. FIGS. 61A to 61E are results of SIMS analysis of a sample according to an example. FIGS. 62A to 62E are results of SIMS analysis of a sample according to an example. FIGS. 63A to 63E are results of SIMS analysis of a sample according to an example. FIGS. 64A to 64E are results of SIMS analysis of a sample according to an example. 65A1 to 65C2 are diagrams illustrating TEM images of samples according to an example. FIGS. 66A1 to 66B2 are diagrams illustrating TEM images of samples according to an example. FIG. 67 is a diagram illustrating evaluation results of a transistor. FIGS. 68A and 68B are diagrams illustrating evaluation results of a transistor. FIGS. 69A and 69B are diagrams illustrating crystal structures. FIGS. 70A and 70B are diagrams illustrating calculation results.

[0036] The embodiments will be described in detail with reference to the drawings. However, the present invention is not limited to the following description, and it will be readily understood by those skilled in the art that various changes can be made in form and detail without departing from the spirit and scope of the present invention. Therefore, the present invention should not be interpreted as being limited to the description of the embodiments shown below.

[0037] In the configuration of the invention described below, the same parts or parts having similar functions are denoted by the same reference numerals in different drawings, and repeated explanations thereof will be omitted. Furthermore, when referring to similar functions, the same hatching pattern may be used and no particular reference numeral may be assigned.

[0038] Furthermore, for ease of understanding, the position, size, range, etc. of each component shown in the drawings may not represent the actual position, size, range, etc. Therefore, the disclosed invention is not necessarily limited to the position, size, range, etc. disclosed in the drawings.

[0039] In this specification, the ordinal numbers "first" and "second" are used for convenience and do not limit the number of components or the order of the components (for example, the order of processes or stacking order). Furthermore, the ordinal numbers assigned to components in one part of this specification may not match the ordinal numbers assigned to the same components in other parts of this specification or in the claims.

[0040] A transistor is a type of semiconductor element that can amplify current or voltage, and perform a switching operation to control conduction or non-conduction. The term "transistor" used in this specification includes an insulated gate field effect transistor (IGFET) and a thin film transistor (TFT).

[0041] In this specification and the like, a transistor using an oxide semiconductor or a metal oxide for a semiconductor layer and a transistor having an oxide semiconductor or a metal oxide for a channel formation region may be referred to as an OS (oxide semiconductor) transistor. A transistor having silicon for a channel formation region may be referred to as a Si transistor.

[0042] In this specification and the like, a transistor is an element having at least three terminals including a gate, a drain, and a source. A transistor has a region (also referred to as a channel formation region) where a channel is formed between the drain (drain terminal, drain region, or drain electrode) and the source (source terminal, source region, or source electrode), and current can flow between the source and the drain through the channel formation region. Note that in this specification and the like, the channel formation region refers to a region through which current mainly flows.

[0043] Furthermore, the functions of "source" and "drain" may be interchanged when transistors of different polarities are used, or when the direction of current flow changes during circuit operation, etc. For this reason, the terms "source" and "drain" may be used interchangeably in this specification.

[0044] Note that impurities in a semiconductor refer to, for example, elements other than the main components constituting the semiconductor. For example, an element with a concentration of less than 0.1 atomic % can be considered an impurity. The presence of impurities may increase the density of defect states in the semiconductor or reduce the crystallinity, for example. When the semiconductor is an oxide semiconductor, impurities that change the characteristics of the semiconductor include, for example, Group 1 elements, Group 2 elements, Group 13 elements, Group 14 elements, Group 15 elements, and transition metals other than the main components of the oxide semiconductor. Specific examples include hydrogen, lithium, sodium, silicon, boron, phosphorus, carbon, and nitrogen. Note that water may also function as an impurity. For example, the inclusion of impurities may cause oxygen deficiency (V) in the oxide semiconductor. Ｏ In some cases, a nucleus (also referred to as a nucleus) may be formed.

[0045] In this specification and the like, an oxynitride refers to a material whose composition contains more oxygen than nitrogen. A nitride oxide refers to a material whose composition contains more nitrogen than oxygen. For example, silicon oxynitride refers to a material whose composition contains more oxygen than nitrogen, and silicon nitride oxide refers to a material whose composition contains more nitrogen than oxygen.

[0046] To analyze the content of elements such as hydrogen, oxygen, carbon, or nitrogen contained in a film, for example, secondary ion mass spectrometry (SIMS) or X-ray photoelectron spectroscopy (XPS) or electron spectroscopy for chemical analysis (ESCA) can be used. XPS is suitable when the content of the target element is high (e.g., 0.5 atomic% or more, or 1 atomic% or more). On the other hand, SIMS is suitable when the content of the target element is low (e.g., 0.5 atomic% or less, or 1 atomic% or less). When comparing the content of elements, it is more preferable to perform a combined analysis using both SIMS and XPS analytical methods.

[0047] In this specification and the like, the term "content" refers to the ratio of a component contained in a film. For example, when an oxide semiconductor layer contains a metal element X, a metal element Y, and a metal element Z, the number of atoms of each of the metal elements X, Y, and Z contained in the oxide semiconductor layer is expressed as A Ｘ , A Ｙ , A Ｚ When the content of the metal element X is Ｘ / (A Ｘ +A Ｙ +A Ｚ In addition, the ratio of the number of atoms of the metal element X, the metal element Y, and the metal element Z in the oxide semiconductor layer (atomic ratio) can be expressed as follows: Ｘ : B Ｙ : B Ｚ When the content of the metal element X is expressed as B Ｘ / (B Ｘ +B Ｙ +B Ｚ ) can be shown as

[0048] It should be noted that the terms "film" and "layer" can be interchangeable depending on the circumstances. For example, the term "conductive layer" can be changed to the term "conductive film." Or, for example, the term "insulating film" can be changed to the term "insulating layer."

[0049] Furthermore, in this specification, "parallel" refers to a state in which two straight lines are arranged at an angle of -10 degrees or more and 10 degrees or less. Therefore, it also includes cases in which the angle is -5 degrees or more and 5 degrees or less. Furthermore, "substantially parallel" refers to a state in which two straight lines are arranged at an angle of -20 degrees or more and 20 degrees or less. Furthermore, "perpendicular" refers to a state in which two straight lines are arranged at an angle of 80 degrees or more and 100 degrees or less. Therefore, it also includes cases in which the angle is 85 degrees or more and 95 degrees or less. Furthermore, "substantially perpendicular" refers to a state in which two straight lines are arranged at an angle of 70 degrees or more and 110 degrees or less.

[0050] In this specification, "connection" includes, as an example, "electrical connection." Note that the term "electrical connection" is sometimes used to define the connection relationship between circuit elements as a physical entity. Furthermore, "electrical connection" includes "direct connection" and "indirect connection." "A and B are directly connected" means that A and B are connected without the intervention of a circuit element (e.g., a transistor, a switch, etc.; wiring is not considered a circuit element). On the other hand, "A and B are indirectly connected" means that A and B are connected via one or more circuit elements.

[0051] For example, assuming that a circuit including A and B is operating, if there is a time during the operation of the circuit when an electrical signal is exchanged or an interaction of electrical potential occurs between A and B, then it can be defined that "A and B are indirectly connected" as objects. Note that even if there is a time during the operation of the circuit when no electrical signal is exchanged or an interaction of electrical potential occurs between A and B, it can still be defined that "A and B are indirectly connected" as long as there is a time during the operation of the circuit when an electrical signal is exchanged or an interaction of electrical potential occurs between A and B.

[0052] An example of a case where "A and B are indirectly connected" is when A and B are connected via the source and drain of one or more transistors. On the other hand, an example of a case where it cannot be said that "A and B are indirectly connected" is when an insulator is present in the path from A to B. Specifically, there are cases where a capacitive element is connected between A and B, and cases where a gate insulating film of a transistor is present between A and B. Therefore, it cannot be said that "the gate (A) of a transistor and the source or drain (B) of the transistor are indirectly connected."

[0053] Another example of a case where it cannot be said that "A and B are indirectly connected" is when multiple transistors are connected via their sources and drains to the path from A to B, and a constant potential V is supplied to a node between one transistor and another transistor from a power supply, GND, etc.

[0054] In this specification and the like, unless otherwise specified, the off-state current refers to the leakage current between the source and drain when the transistor is in an off state (also referred to as a non-conducting state or a cut-off state). Unless otherwise specified, the off-state current refers to the leakage current between the source and the gate when the voltage V ｇｓ is the threshold voltage V ｔｈ (For p-channel transistors, V ｔｈ This refers to a state of being (higher than)

[0055] In this specification, "normally on" refers to a state in which a channel exists and a current flows through a transistor even when no voltage is applied to the gate, and "normally off" refers to a state in which no current flows through a transistor when no potential is applied to the gate or when a ground potential is applied to the gate.

[0056] In this specification and the like, a tapered shape refers to a shape in which at least a portion of the side surface of a structure is inclined with respect to the substrate surface or the surface to be formed. For example, it is preferable to have a region in which the angle (also called the taper angle) between the inclined side surface and the substrate surface or the surface to be formed is greater than 0 degrees and less than 90 degrees. Note that the side surface of the structure, the substrate surface, and the surface to be formed do not necessarily need to be completely flat, and may be approximately planar with a slight curvature or approximately planar with a slight unevenness.

[0057] In this specification, when it is stated that A is located on B, at least a portion of A is located on B. Therefore, for example, it can be rephrased as "A has a region located on B." Similarly, when it is stated that A contacts B or A overlaps B, at least a portion of A contacts B or overlaps B. Therefore, it can be rephrased as "A has a region contacting B" or "A has a region overlapping B," respectively. Similarly, in this specification, when it is stated that A covers B, at least a portion of A covers B. Therefore, for example, it can be rephrased as "A has a region covering B."

[0058] In this specification, etc., a device fabricated using a metal mask or an FMM (fine metal mask, high-resolution metal mask) may be referred to as a device with an MM (metal mask) structure. Also, in this specification, etc., a device fabricated without using a metal mask or an FMM may be referred to as a device with an MML (metal maskless) structure.

[0059] In this specification and the like, a structure in which different light-emitting layers are formed for light-emitting elements (also referred to as light-emitting devices) with different emission wavelengths is sometimes referred to as an SBS (Side By Side) structure. The SBS structure allows the materials and configuration to be optimized for each light-emitting element, increasing the degree of freedom in selecting materials and configurations and making it easier to improve brightness and reliability.

[0060] In this specification and the like, holes or electrons may be referred to as "carriers." Specifically, a hole injection layer or an electron injection layer may be referred to as a "carrier injection layer," a hole transport layer or an electron transport layer may be referred to as a "carrier transport layer," and a hole block layer or an electron block layer may be referred to as a "carrier block layer." Note that the above-mentioned carrier injection layer, carrier transport layer, and carrier block layer may not be clearly distinguishable. Furthermore, one layer may have two or three functions among the carrier injection layer, carrier transport layer, and carrier block layer.

[0061] In this specification and the like, a light-emitting element has an EL layer between a pair of electrodes. The EL layer has at least a light-emitting layer. Here, examples of layers (also referred to as functional layers) included in the EL layer include a light-emitting layer, a carrier injection layer (a hole injection layer and an electron injection layer), a carrier transport layer (a hole transport layer and an electron transport layer), and a carrier block layer (a hole block layer and an electron block layer). In this specification and the like, one of the pair of electrodes may be referred to as a pixel electrode, and the other may be referred to as a common electrode.

[0062] In this specification and the like, the sacrificial layer (which may also be referred to as a mask layer) is located above at least the light-emitting layer (more specifically, a layer that is processed into an island shape among the layers that make up the EL layer), and has the function of protecting the light-emitting layer during the manufacturing process.

[0063] In this specification and the like, a step disconnection refers to a phenomenon in which a layer, a film, or an electrode is separated due to the shape of the surface on which it is formed (for example, a step or the like).

[0064] In the drawings and the like relating to this specification, arrows indicating the X direction, Y direction, and Z direction may be used. In this specification and the like, the "X direction" refers to the direction along the X axis, and there may be no distinction between the forward direction and the reverse direction unless explicitly stated. The same applies to the "Y direction" and the "Z direction." The X direction, Y direction, and Z direction are directions that intersect with each other. For example, the X direction, Y direction, and Z direction are directions that are perpendicular to each other.

[0065] Embodiment 1 In this embodiment, a semiconductor device of one embodiment of the present invention will be described with reference to FIGS. 1A to 1H.

[0066] 1A is a schematic cross-sectional view of a semiconductor device of one embodiment of the present invention. The semiconductor device illustrated in FIG. 1A includes an oxide semiconductor layer 30 over an insulating layer 20, an insulating layer 50, and a conductive layer 60. A transistor included in the semiconductor device of one embodiment of the present invention includes the oxide semiconductor layer 30, the insulating layer 50, and the conductive layer 60. The insulating layer 50 has a portion located between the oxide semiconductor layer 30 and the conductive layer 60.

[0067] In the transistor according to one embodiment of the present invention, the conductive layer 60 functions as a gate electrode, and the insulating layer 50 functions as a gate insulating layer. The oxide semiconductor layer 30 includes a channel formation region 31. The oxide semiconductor layer 30 includes a region that overlaps with the conductive layer 60 with the insulating layer 50 interposed therebetween. At least part of the region functions as the channel formation region 31. Note that the source and drain of the transistor are omitted in FIG. 1A .

[0068] The transistor according to one embodiment of the present invention includes a metal oxide (also referred to as an oxide semiconductor) that functions as a semiconductor in the oxide semiconductor layer 30 including a channel formation region. That is, the transistor can be referred to as an OS transistor.

[0069] An OS transistor has an oxygen vacancy (V Ｏ ) and impurities, the electrical characteristics are likely to fluctuate and reliability may be reduced. Ｏ H) and generate electrons that serve as carriers. Therefore, if oxygen vacancies are present in the channel formation region of the oxide semiconductor, the OS transistor is likely to be normally on. Therefore, it is preferable that oxygen vacancies and impurities are reduced as much as possible in the channel formation region of the oxide semiconductor. In other words, it is preferable that the carrier concentration of the channel formation region of the oxide semiconductor is reduced and the channel formation region of the oxide semiconductor is made i-type (intrinsic) or substantially i-type.

[0070] Furthermore, when an excessive amount of oxygen is supplied to the oxide semiconductor layer 30, electron traps due to the excess oxygen are formed in the insulating layer 50. As a result, the OS transistor is more susceptible to positive drift degradation in a +GBT (gate bias-temperature) stress test. In other words, the amount of positive drift degradation in the +GBT stress test increases.

[0071] Therefore, in the semiconductor device of one embodiment of the present invention, the hydrogen concentration in the oxide semiconductor layer 30 is preferably low. Furthermore, an appropriate amount of oxygen is preferably supplied to the oxide semiconductor layer 30. Furthermore, it is preferable to reduce the amount of excess oxygen in the oxide semiconductor layer 30.

[0072] Indium oxide is preferably used as the metal oxide used for the oxide semiconductor layer 30. For example, the oxide semiconductor layer 30 preferably includes an indium oxide film. The indium oxide film preferably includes a channel formation region 31. The higher the ratio of the number of indium atoms to the sum of the numbers of atoms of all metal elements included in the metal oxide, the higher the field-effect mobility of the transistor can be. Therefore, by using indium oxide for the oxide semiconductor layer 30, the transistor can have high on-state current and high frequency characteristics.

[0073] Furthermore, the indium oxide film preferably has crystallinity. For example, the indium oxide film preferably has crystal grains in the channel formation region 31. Specifically, the indium oxide film is preferably a single-crystal film or a polycrystalline film. Note that the indium oxide film may be an amorphous film containing crystal grains.

[0074] In a crystalline film, for example, crystal grains can be confirmed in a high-resolution transmission electron microscope (TEM) image. Furthermore, in a crystalline film, for example, crystal grain boundaries can sometimes be confirmed in a high-resolution TEM image. That is, crystal grains and crystal grain boundaries can sometimes be observed in a high-resolution TEM image of a crystalline film. The total magnification when acquiring a TEM image is preferably 2,000,000 times or more, and more preferably 4,000,000 times or more.

[0075] 1A illustrates a structure in which the oxide semiconductor layer 30 includes a single-crystal indium oxide film. When the indium oxide film is a single-crystal film, the indium oxide film has one crystal grain, and no crystal grain boundary is observed throughout the oxide semiconductor layer 30. In other words, no crystal grain boundary is observed in the channel formation region. With such a structure, carrier scattering at the crystal grain boundary can be suppressed, and a transistor with high field-effect mobility can be realized. In addition, a transistor with high reliability can be realized.

[0076] 1B shows an example of a configuration in which the oxide semiconductor layer 30 has a polycrystalline indium oxide film. In FIG. 1B, the indium oxide film has a plurality of crystal grains 32, and crystal grain boundaries 33 are observed between the crystal grains 32. In FIG. 1B, the crystal grain boundaries are indicated by dashed lines.

[0077] When the indium oxide film is a polycrystalline film, it is preferable that one of the crystal grains 32 has a portion located in the channel formation region 31, and further, no crystal grain boundary is observed in the channel formation region 31. Even in such a configuration, it is possible to achieve the same effect as in the configuration in which the indium oxide film is a single crystal film.

[0078] When the channel formation region 31 is contained in one crystal grain 32, the indium oxide in the channel formation region 31 can be said to be a single crystal.

[0079] 1C shows another example of a configuration in which the oxide semiconductor layer 30 has a polycrystalline indium oxide film. In Fig. 1C, the indium oxide film has a plurality of crystal grains 32, and two crystal grains 32 (a first crystal grain and a second crystal grain) are located in the channel formation region 31.

[0080] Here, it is preferable that the crystal orientation of the first crystal grains and the crystal orientation of the second crystal grains are identical or substantially identical. When the crystal orientation of the first crystal grains and the crystal orientation of the second crystal grains are identical or substantially identical, a crystal grain boundary may not be observed at the boundary between the first crystal grains and the second crystal grains (dotted line shown in FIG. 1C ). By making the crystal orientation of the first crystal grains and the crystal orientation of the second crystal grains identical or substantially identical, the formation of a crystal grain boundary between the first crystal grains and the second crystal grains can be suppressed. Therefore, even with this configuration, the same effect as a configuration in which the indium oxide film is a single crystal film can be achieved. Incidentally, the fact that the crystal orientation of the first crystal grains and the crystal orientation of the second crystal grains are identical or substantially identical can sometimes be confirmed, for example, by a high-resolution TEM image. Specifically, in a high-resolution TEM image, it can be confirmed that the lattice fringes of the first crystal grains and the lattice fringes of the second crystal grains are continuously connected at the boundary between the first crystal grains and the second crystal grains.

[0081] In this specification, the term "grain boundary" refers to, for example, a boundary between adjacent crystal grains with different crystal orientations. Therefore, in this specification, the term "grain boundary" does not include a boundary between adjacent crystal grains with the same crystal orientation. For example, even if a boundary between two crystal grains is observed in a high-resolution TEM image, if the crystal orientations of the two crystal grains are the same or nearly the same, the boundary may not be called a grain boundary.

[0082] The crystal orientation can be evaluated by a diffraction pattern (also called a nanobeam electron diffraction pattern) observed by nanobeam electron diffraction (NBED). Alternatively, it can be evaluated by a pattern (also called an FFT pattern) obtained by performing fast Fourier transform (FFT) processing on a TEM image. The FFT pattern reflects the same reciprocal lattice space information as the diffraction pattern.

[0083] For example, when the difference in angle between the FFT patterns of the first crystal grain and the second crystal grain is between -5 degrees and 5 degrees, preferably between -3 degrees and 3 degrees, and more preferably between -2 degrees and 2 degrees, the crystal orientation of the first crystal grain and the crystal orientation of the second crystal grain can be said to be consistent or approximately consistent. For example, the angle of the FFT pattern in the

[111] orientation refers to the acute angle between the approximate line between the central spot and one or both of the spots resulting from the (222) plane or the (-2-2-2) plane and the reference line (e.g., a line extending in the vertical direction). In a thin film, due to the influence of the processed shape or surface roughness of the base film, the orientation of the crystal axis or the orientation of the crystal orientation may continuously change from a first position to a second position within the crystal grain, with a certain crystal axis or a certain crystal orientation as the axis of rotation. For example, there is a case where the direction of the crystal orientation perpendicular to the

[111] direction changes continuously from a first position to a second position within a crystal grain, with the

[111] direction as the axis of rotation. In this case, if no grain boundary is observed within the crystal grain, the crystal grain is regarded as one crystal grain in this specification.

[0084] The thickness of the oxide semiconductor layer 30 is preferably 2 nm to 50 nm, more preferably 2.5 nm to 30 nm, even more preferably 2.5 nm to 20 nm, still more preferably 5 nm to 20 nm, and even more preferably 5 nm to 10 nm. It is sufficient that at least a portion of the oxide semiconductor layer 30 has a region with the above-described thickness. For example, the channel formation region of the oxide semiconductor layer 30 may have a region with the above-described thickness.

[0085] Increasing the thickness of the oxide semiconductor layer 30 can increase the on-state current of the transistor. On the other hand, if the thickness of the oxide semiconductor layer 30 is too thick (for example, thicker than 50 nm), the grain boundaries become longer, which may result in a decrease in the on-state current of the transistor due to carrier scattering at the grain boundaries. Furthermore, reducing the thickness of the oxide semiconductor layer 30 can prevent the threshold voltage from decreasing, resulting in a normally-off transistor. On the other hand, if the thickness of the oxide semiconductor layer 30 is too thin (for example, thinner than 2 nm), the crystallinity of the oxide semiconductor layer 30 may vary across the substrate, resulting in variations in the electrical characteristics of the transistor. Furthermore, discontinuities or local thinning may occur. Therefore, by setting the thickness of the oxide semiconductor layer 30 within the above range, the crystallinity of the oxide semiconductor layer 30 can be improved. By increasing the crystallinity of the oxide semiconductor layer 30, the oxide semiconductor layer 30 can have crystal grains.

[0086] When a metal oxide contains indium and zinc, the metal oxide may have high crystallinity, for example, a c-axis aligned crystalline (CAAC) structure. The CAAC structure has fewer grain boundaries in the a-b plane than a polycrystalline structure. Examples of metal oxides containing indium and zinc include indium zinc oxide (In-Zn oxide, also referred to as IZO (registered trademark)) and indium gallium zinc oxide (In-Ga-Zn oxide, also referred to as IGZO).

[0087] In an oxide semiconductor layer with high crystallinity, an indium oxide film is a film through which one or both of hydrogen and oxygen move more easily than, for example, an IGZO film. Therefore, it can be said that an indium oxide film is a film through which one or both of hydrogen and oxygen are more easily supplied and from which one or both of hydrogen and oxygen are more easily discharged than, for example, an IGZO film. Note that it can be said that an indium oxide film is a film with high permeability to one or both of hydrogen and oxygen compared to, for example, an IGZO film. In other words, it can be said that an indium oxide film is a film with low barrier properties against one or both of hydrogen and oxygen compared to, for example, an IGZO film.

[0088] Furthermore, when indium oxide is used for the oxide semiconductor layer 30, the oxide semiconductor layer 30 can have a polycrystalline structure. When the oxide semiconductor layer 30 has a polycrystalline structure, oxygen and hydrogen may diffuse through crystal grain boundaries.

[0089] The crystallinity of the oxide semiconductor layer 30 can be analyzed by, for example, X-ray diffraction (XRD), transmission electron microscopy (TEM), or electron diffraction (ED). Alternatively, a combination of these techniques may be used for analysis.

[0090] The content of the first element in the oxide semiconductor layer 30 is preferably low. Furthermore, the concentration of the first element in the oxide semiconductor layer 30 is preferably low. In particular, the concentration of the first element in the channel formation region is preferably low. Here, the first element is at least one of boron, aluminum, and gallium. That is, in the oxide semiconductor layer 30, the concentration of any one of boron, aluminum, and gallium is preferably low, the concentrations of two selected from boron, aluminum, and gallium are more preferably low, and the concentrations of all of boron, aluminum, and gallium are even more preferably low. The concentration of the first element in the oxide semiconductor layer 30 is preferably 1 atomic % or less, more preferably 0.1 atomic % or less, and even more preferably 0.01 atomic % (100 ppm) or less, for example. The preferred concentration of the first element in the oxide semiconductor layer 30 can also be said to be the preferred concentration of the first element in the channel formation region.

[0091] In indium oxide, the above-mentioned first element is mainly present as a trivalent cation, similar to indium. That is, it is presumed that the first element in indium oxide is located at the cation site. Therefore, it is preferable that the first element in indium oxide is reduced to a concentration that can be considered an impurity. For example, it is preferable that the concentration of the first element in indium oxide is 0.1 atomic % or less. This reduces scattering resulting from the random arrangement of metal atoms at the cation site (so-called cation disorder), thereby realizing a transistor with high field-effect mobility. Furthermore, it is possible to realize a transistor with high reliability.

[0092] By reducing the concentrations of boron and aluminum in the oxide semiconductor layer 30, the crystallinity of the oxide semiconductor layer 30 can be improved.

[0093] When the oxide semiconductor layer 30 contains gallium atoms, the gallium atoms bond with excess oxygen atoms to form a Ga—O structure. The Ga—O structure functions as an acceptor that traps electrons. Therefore, in a transistor having an oxide semiconductor layer 30 containing gallium atoms and excess oxygen atoms, the amount of variation in threshold voltage in a positive bias temperature stress (PBTS) test is large. Therefore, by reducing the gallium concentration in the oxide semiconductor layer 30, the amount of variation in threshold voltage in the PBTS test can be reduced. This allows the transistor to have high reliability against positive bias application.

[0094] The concentration of the first element can be measured by, for example, inductively coupled plasma mass spectrometry (ICP-MS), XPS, SIMS, time-of-flight secondary ion mass spectrometry (ToF-SIMS), Auger electron spectroscopy (AES), energy dispersive X-ray spectroscopy (EDX), or inductively coupled plasma optical emission spectroscopy (ICP-AES). The evaluation can be performed using plasma-atomic emission spectroscopy or the like.

[0095] The band gap of indium oxide having the concentration of the first element in the above range is 2.5 eV or more and 3.7 eV or less. If the band gap of the material used for the oxide semiconductor layer 30 is small, for example, smaller than that of silicon, the off-state current of the transistor increases. Therefore, by using indium oxide, which has a band gap larger than that of silicon, for the oxide semiconductor layer 30, the off-state current of the transistor can be reduced and the power consumption of the semiconductor device can be sufficiently reduced. Furthermore, the band gap of gallium oxide is 4.5 eV or more, and the band gap of aluminum oxide is even larger than that of gallium oxide. Therefore, if the concentration of the first element in indium oxide is high, the band gap may become larger than necessary. If the band gap of the material used for the oxide semiconductor layer 30 is too large, a high voltage is required to turn on the transistor, which increases the power consumption of the semiconductor device including the transistor. Therefore, by setting the concentration of the first element in the above range, the power consumption of the semiconductor device can be reduced.

[0096] An OS transistor is an accumulation-type transistor in which electrons serve as majority carriers. That is, the carriers in an OS transistor are electrons. Assuming that the relaxation time of carriers is constant, the smaller the effective mass of electrons (carriers), the higher the electron mobility (carrier mobility). That is, by using a metal oxide film with a small effective mass of electrons for the semiconductor layer of a transistor, the on-state current or field-effect mobility of the transistor can be increased.

[0097] Indium oxide has a small effective mass of electrons. Therefore, by using indium oxide having a small effective mass of electrons for the oxide semiconductor layer 30, a transistor with a large on-state current, a transistor with high field-effect mobility, and a transistor with high frequency characteristics (also referred to as f characteristics) can be realized. Furthermore, the effective mass of electrons in indium oxide is smaller than the effective mass of electrons in, for example, silicon. Therefore, in terms of the effective mass of electrons, the f characteristics of a transistor using indium oxide in a channel formation region are higher than the f characteristics of a Si transistor.

[0098] Indium oxide has a large effective mass of holes. Therefore, by using indium oxide, which has a large effective mass of holes, for the oxide semiconductor layer 30, a transistor with extremely small off-state current can be realized. Furthermore, the effective mass of holes in indium oxide is larger than the effective mass of holes in, for example, silicon. Therefore, in terms of the effective mass of holes, the off-state current of a transistor using indium oxide for a channel formation region is sufficiently smaller than the off-state current of a Si transistor.

[0099] In a transistor using indium oxide for the oxide semiconductor layer 30, the off-state current per 1 μm of channel width at room temperature is 1×10 −１７ A / μm or less, preferably 1×10 −１８ A / μm or less, more preferably 1×10 −１９ The off-state current value at 85° C. per 1 μm of channel width can be reduced to 1×10 −１６ A / μm or less, preferably 1×10 −１７ A / μm or less, more preferably 1×10 −１８ It is possible to make it less than A / μm.

[0100] Furthermore, miniaturization of an OS transistor can improve the high-frequency characteristics of the transistor. For example, the cutoff frequency of the transistor can be increased. Specifically, the cutoff frequency of the transistor can be set to 50 GHz or higher, preferably 100 GHz or higher, and more preferably 150 GHz or higher at room temperature.

[0101] Carriers tend to flow in a region of the oxide semiconductor layer 30 that is 1 nm deep from the surface on the insulating layer 50 side. Therefore, the channel formation region 31 is a region of the oxide semiconductor layer 30 that overlaps with the conductive layer 60 and is 1 nm deep or less from the surface on the insulating layer 50 side. The channel formation region 31 is also a region of the oxide semiconductor layer 30 that overlaps with the conductive layer 60 and is 1 nm deep or less from the interface with the insulating layer 50.

[0102] The interface between the oxide semiconductor layer 30 and the insulating layer 50 can be confirmed by, for example, a cross-sectional TEM image, a cross-sectional scanning transmission electron microscope (STEM) image, etc. The interface between the oxide semiconductor layer 30 and the insulating layer 50 can sometimes be confirmed by using SIMS or by performing line analysis of the composition by EDX on the interface between the oxide semiconductor layer 30 and the insulating layer 50 and its surroundings.

[0103] For example, EDX line analysis is performed on the interface and its periphery, with the direction perpendicular to the surface on which the oxide semiconductor layer 30 is formed as the depth direction. Next, in the profile of the quantitative values ​​of each element in the depth direction obtained by this analysis, the depth at which the quantitative value of a metal (e.g., aluminum) that is the main component of the insulating layer 50 but is not the main component of the oxide semiconductor layer 30 becomes half-value can be defined as the interface. Alternatively, in the profile of the quantitative values ​​of each element in the depth direction obtained by this analysis, the depth at which the quantitative value of a metal (e.g., indium) that is the main component of the oxide semiconductor layer 30 but is not the main component of the insulating layer 50 becomes half-value can be defined as the interface.

[0104] The indium oxide film may contain one or more metal elements having a large period number in the periodic table, provided that the film has crystallinity. The greater the overlap of the orbitals of the metal elements, the greater the carrier conduction. Therefore, by including a metal element having a large period number in the periodic table, the field-effect mobility of the transistor may be improved. Examples of metal elements having a large period number in the periodic table include metal elements belonging to the fifth period and the sixth period. Specific examples of such metal elements include yttrium, zirconium, silver, cadmium, tin, antimony, barium, lead, bismuth, and light rare earth elements (lanthanum, cerium, praseodymium, neodymium, promethium, samarium, and europium).

[0105] For example, the indium oxide film preferably contains antimony. For example, the antimony concentration in the indium oxide film is 1×10 １７ atoms / cm ３ 8 x 10 or more ２１ atoms / cm ３ Preferably, 1×10 １７ atoms / cm ３ 3x10 or more ２０ atoms / cm ３ The indium oxide content is preferably 0.0002 atomic % or more and 10 atomic % or less, and more preferably 0.0002 atomic % or more and 0.5 atomic % or less. The above-mentioned preferable ranges also apply to the case where the indium oxide film contains any of the above metal elements other than antimony.

[0106] Here, one of the insulating layer 20 and the insulating layer 50 is called a first insulating layer, and the other of the insulating layer 20 and the insulating layer 50 is called a second insulating layer.

[0107] The first insulating layer preferably has a function of supplying oxygen to the oxide semiconductor layer 30. The first insulating layer preferably has a region containing oxygen that is desorbed by heating (hereinafter, may be referred to as excess oxygen), for example. When the insulating layer having the region containing excess oxygen is in contact with the oxide semiconductor layer 30, oxygen can be supplied to the oxide semiconductor layer 30. The oxygen supplied to the oxide semiconductor layer 30 repairs oxygen vacancies, and the amount of oxygen vacancies in the oxide semiconductor layer 30 can be reduced. Examples of insulating materials that easily form a region containing excess oxygen include silicon oxide, silicon oxynitride, and silicon oxide having vacancies.

[0108] The second insulating layer preferably has a function of capturing or fixing (also referred to as gettering) oxygen. As described above, an indium oxide film is a film through which oxygen easily moves. Therefore, when the second insulating layer has the function of capturing or fixing oxygen, excess oxygen in the oxide semiconductor layer 30 can be diffused to the second insulating layer and the oxygen can be captured or fixed. Therefore, the OS transistor can suppress positive drift degradation in a +GBT stress test caused by excess oxygen. Examples of insulating materials having a function of capturing or fixing oxygen include aluminum oxide, hafnium oxide, hafnium zirconium oxide, and an oxide containing hafnium and silicon (hafnium silicate).

[0109] Note that an aluminum oxide film, a hafnium oxide film, a hafnium zirconium oxide film, and a hafnium silicate film have the function of capturing or fixing hydrogen. As described above, an indium oxide film is a film through which hydrogen easily moves. Therefore, when the second insulating layer has the function of capturing or fixing hydrogen, hydrogen in the oxide semiconductor layer 30 diffuses into the second insulating layer, and the hydrogen can be captured or fixed. Therefore, the hydrogen concentration in the oxide semiconductor layer 30 (particularly, the hydrogen concentration in the channel formation region 31) can be reduced. Therefore, the V in the channel formation region Ｏ By reducing H, the channel forming region can be made i-type or substantially i-type.

[0110] The conductive layer 60 is preferably made of a highly conductive material such as tungsten. Furthermore, it is also preferable to use a conductive material that is resistant to oxidation or a conductive material that has the function of suppressing oxygen diffusion as the conductive layer 60. Examples of such conductive materials include conductive materials containing nitrogen (e.g., titanium nitride or tantalum nitride) and conductive materials containing oxygen (e.g., ruthenium oxide). This can prevent the conductivity of the conductive layer 60 from decreasing.

[0111] The conductive layer 60 is preferably made of a conductive material containing oxygen and a metal element contained in the metal oxide in which the channel is formed. Alternatively, a conductive material containing nitrogen (e.g., titanium nitride or tantalum nitride) may be used. Alternatively, one or more selected from indium tin oxide (In—Sn oxide, also referred to as ITO), indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, In—Zn oxide, and indium tin oxide containing silicon oxide (also referred to as ITSO) may be used. Alternatively, indium gallium zinc oxide containing nitrogen may be used. Using such a material may allow hydrogen contained in the metal oxide in which the channel is formed to be captured. Alternatively, hydrogen introduced from an outer insulating layer or the like may be captured.

[0112] 1D , an oxide layer 27 can be provided between the insulating layer 20 and the oxide semiconductor layer 30. The oxide semiconductor layer 30 is provided on the oxide layer 27 and has a region in contact with the oxide layer 27. The oxide layer 27 also has a region overlapping with the insulating layer 50 with the oxide semiconductor layer 30 sandwiched therebetween. The oxide layer 27 is a layer that allows crystal grains contained in the oxide semiconductor layer 30 to grow from below, or a layer that does not inhibit the crystal grains contained in the oxide semiconductor layer 30 from growing from above.

[0113] Indium oxide has a cubic (bixbyite) crystal structure, and the lattice constant of this crystal structure is 1.0117 nm (see ICSD (Inorganic Crystal Structure Database) coll.code.14387).

[0114] When indium oxide is used for the oxide semiconductor layer 30, it is preferable to use an oxide having a cubic crystal for the oxide layer 27. When the crystal of the oxide layer 27 has the same crystal structure as the crystal of the oxide semiconductor layer 30, the oxide semiconductor layer 30 can grow epitaxially using the oxide layer 27 as a nucleus, thereby improving the crystallinity of the oxide semiconductor layer 30. For example, zirconium oxide or yttria-stabilized zirconia (YSZ) can be used for the oxide layer 27. The crystal structure of zirconium oxide and YSZ is a cubic system. Note that when the crystal of the oxide semiconductor layer 30 and the crystal of the oxide layer 27 have the same crystal structure, the crystal orientation of the surface of the oxide layer 27 is not particularly limited. For example, it may be

[100] ,

[110] , or

[111] .

[0115] In this specification, space groups are expressed using short notation in international notation (or Hermann-Mauguin notation). Crystal planes and crystal orientations are expressed using Miller indices. In crystallography, space groups, crystal planes, and crystal orientations are expressed by adding a superscript bar to the numbers. However, due to formatting restrictions, in this specification, instead of adding a bar above the numbers, they may be expressed by adding a minus sign (-) before the numbers. Furthermore, individual orientations indicating directions within a crystal are expressed with [ ], collective orientations indicating all equivalent orientations are expressed with < >, individual planes indicating crystal planes are expressed with ( ), and collective planes with equivalent symmetry are expressed with {}.

[0116] It is preferable that the difference (also referred to as lattice mismatch) between the lattice constant or unit lattice vector of the crystal of the oxide layer 27 and the lattice constant or unit lattice vector of the crystal of the oxide semiconductor layer 30 be small. By using an oxide that reduces the lattice mismatch for the oxide layer 27, the crystallinity of the oxide semiconductor layer 30 can be improved.

[0117] One method for evaluating the degree of lattice mismatch is the lattice mismatch. The lattice mismatch Δa [%] of the crystals of the forming film with respect to the crystals of the forming film is calculated by the following formula (1). Hereinafter, the lattice mismatch Δa of the crystals of the forming film with respect to the crystals of the forming film may be simply referred to as the lattice mismatch Δa of the forming film with respect to the forming film.

[0118]

[0119] In formula (1), L １ is the lattice constant or unit lattice vector of the crystal of the formed film, and L ２ is the lattice constant or unit lattice vector of the crystal of the film to be formed.

[0120] The lattice mismatch Δa of the crystal grains of the oxide semiconductor layer 30 with respect to the crystal grains of the oxide layer 27 is preferably 0% to 10%, more preferably 0% to 5%, and even more preferably 0% to 3%. By using a material that reduces the lattice mismatch with the oxide semiconductor layer 30 for the oxide layer 27, the crystallinity of the oxide semiconductor layer 30 can be improved.

[0121] For example, Zr ０．９ Y ０．１ O １．９５ The lattice constant of the crystal (fluorite type) is 0.51481 nm (see ICSD coll.code.248790). Therefore, the lattice mismatch between the crystal grains of the indium oxide film and the crystal grains of YSZ is 1.74%. Therefore, when indium oxide is used for the oxide semiconductor layer 30, YSZ can be suitably used as the oxide layer 27. Note that YSZ contains yttrium, zirconium, and oxygen. The content of yttrium in YSZ is 2 atomic % to 15 atomic %, preferably 5 atomic % to 10 atomic %.

[0122] When YSZ is used as the oxide layer 27 and indium oxide is used as the oxide semiconductor layer 30, a buffer layer containing indium and zirconium may be formed at the interface between the oxide layer 27 and the oxide semiconductor layer 30. Since the ionic radii of indium and zirconium are different, it is presumed that the lattice constant or unit lattice vector of the buffer layer will be a value between the lattice constant or unit lattice vector of the YSZ crystal and the lattice constant or unit lattice vector of the indium oxide crystal. Therefore, by forming the buffer layer, it is possible to reduce the lattice mismatch between the oxide layer 27 and the oxide semiconductor layer 30, and to improve the crystallinity of the oxide semiconductor layer 30.

[0123] Note that the crystal orientation of the oxide layer 27 and the crystal orientation of the oxide semiconductor layer 30 may not necessarily be the same. For example, the oxide layer 27 having a layered crystal structure may be provided under indium oxide having a cubic crystal structure. Specifically, when a film having hexagonal or trigonal crystal structure is used as the oxide layer 27, the crystal orientation of the surface of the oxide layer 27 may be set to

[001] and the crystal orientation of the lower surface of the oxide semiconductor layer 30 may be set to

[111] , thereby satisfying the above-mentioned certain crystal orientation relationship. Examples of hexagonal or trigonal crystal structures include wurtzite, YbFe ２ O ４ Type, Yb ２ Fe ３ O ７ The above structure can be considered as a structure in which an oxide semiconductor layer having cubic crystals is formed on an oxide layer having layered crystals. That is, it can also be considered as a stacked structure manufactured by heteroepitaxial growth technology or a technology similar to heteroepitaxial growth.

[0124] Specifically, zinc oxide, indium gallium oxide (In—Ga oxide), gallium zinc oxide (Ga—Zn oxide, also referred to as GZO), aluminum zinc oxide (Al—Zn oxide, also referred to as AZO), indium aluminum zinc oxide (In—Al—Zn oxide, also referred to as IAZO), In—Ga—Zn oxide, indium tin zinc oxide (In—Sn—Zn oxide), or the like can be used for the oxide layer 27. When In—Ga—Zn oxide is used for the oxide layer 27, the oxide layer 27 contains indium, gallium, and zinc.

[0125] There are no particular limitations on the material that can be used for the oxide layer 27. The oxide layer 27 may be made of an insulating material or a semiconductor material. When an insulating material is used for the oxide layer 27, the oxide layer 27 may be considered to be part of the insulating layer 20. When a semiconductor material is used for the oxide layer 27, the oxide layer 27 may be considered to be part of the oxide semiconductor layer 30.

[0126] The oxide layer 27 preferably has a small thickness. For example, the oxide layer 27 is preferably thinner than the oxide semiconductor layer 30. When the oxide semiconductor layer 30 is in contact with the source electrode or the drain electrode via the oxide layer 27, an increase in the contact resistance between the oxide semiconductor layer 30 and the source electrode or the drain electrode can be suppressed. Specifically, the oxide layer 27 preferably has a region with a thickness of 0.1 nm or more and less than 2 nm, and more preferably has a region with a thickness of 0.5 nm or more and less than 2 nm.

[0127] 1A shows an example in which the oxide semiconductor layer 30 has a single layer structure. The oxide semiconductor layer 30 can have a stacked structure of two or more layers. FIG. 1E shows an example in which the oxide semiconductor layer 30 has a two-layer structure of an oxide semiconductor layer 30a and an oxide semiconductor layer 30b on the oxide semiconductor layer 30a. The oxide semiconductor layer 30a is in contact with the insulating layer 20, and the oxide semiconductor layer 30b is in contact with the insulating layer 50.

[0128] 1E , it is preferable to use a metal oxide (typically indium oxide) applicable to the oxide semiconductor layer 30 described above as the oxide semiconductor layer 30a, and an oxide semiconductor whose conduction band minimum is located closer to the vacuum level than the conduction band minimum of the oxide semiconductor layer 30a as the oxide semiconductor layer 30b. In this case, the oxide semiconductor layer 30a can mainly function as a current path (channel). That is, the oxide semiconductor layer 30a has a channel formation region 31 on the surface on the oxide semiconductor layer 30b side and in the vicinity thereof.

[0129] The above-described structure can reduce carriers trapped at the interface of the oxide semiconductor layer 30a and in the vicinity thereof. Furthermore, the channel can be located away from the surface of the insulating layer 50, reducing the influence of surface scattering. This can increase the field-effect mobility of the transistor.

[0130] Furthermore, when the oxide layer 27 is formed using a semiconductor material, the oxide semiconductor layer 30a is sandwiched between the oxide layer 27 and the oxide semiconductor layer 30b, both of which have a large band gap, and the oxide semiconductor layer 30a functions mainly as a current path (channel). By sandwiching the oxide semiconductor layer 30a between the oxide layer 27 and the oxide semiconductor layer 30b, it is possible to reduce trap states at the interface of the oxide semiconductor layer 30a and in its vicinity. This makes it possible to realize a buried channel transistor in which the channel is spaced away from the insulating layer interface, thereby increasing the field-effect mobility. Furthermore, the influence of interface states that may form on the back channel side is reduced, which suppresses photodegradation of the transistor (e.g., photodegradation due to negative bias current), thereby improving the reliability of the transistor.

[0131] Furthermore, it is preferable that the oxide semiconductor layer 30b be made of a material with high oxygen permeability. This configuration allows excess oxygen in the oxide semiconductor layer 30a to be discharged to the insulating layer 50. By reducing the thickness of the oxide semiconductor layer 30b, the oxygen permeability of the oxide semiconductor layer 30b increases. Therefore, the same effect can be achieved even when the thickness of the oxide semiconductor layer 30b is reduced. The thickness of the oxide semiconductor layer 30b is, for example, 0.1 nm to 3 nm, preferably 0.1 nm to 2 nm, more preferably 0.1 nm to 1 nm, and even more preferably 0.1 nm to 0.5 nm.

[0132] Examples of metal oxides that can be used for the oxide semiconductor layer 30b include In—Ga oxide, In—Zn oxide, ITO, indium titanium oxide (In—Ti oxide), In—Al—Zn oxide, In—Ga—Zn oxide, In—Sn—Zn oxide, indium titanium zinc oxide (In—Ti—Zn oxide), ITSO, etc. Alternatively, zinc oxide, aluminum zinc oxide (Al—Zn oxide, also referred to as AZO), aluminum tin oxide (Al—Sn oxide), etc. can be used.

[0133] The In-Zn oxide used in the oxide semiconductor layer 30b can have a composition of In:Zn=1:1 (atomic ratio) or thereabouts, In:Zn=2:1 (atomic ratio) or thereabouts, or In:Zn=4:1 (atomic ratio) or thereabouts. The IGZO used in the oxide semiconductor layer 30b can have a composition of In:Ga:Zn=1:1:1 (atomic ratio) or thereabouts, In:Ga:Zn=1:3:2 (atomic ratio) or thereabouts, or In:Ga:Zn=1:3:4 (atomic ratio) or thereabouts. The term "nearby" includes a range of ±30% of the desired atomic ratio.

[0134] The crystallinity of the metal oxide contained in the oxide semiconductor layer 30b is not particularly limited. For example, the oxide semiconductor layer 30b may contain one or more of an amorphous semiconductor (a semiconductor having an amorphous structure), a single-crystal semiconductor (a semiconductor having a single-crystal structure), or a semiconductor having crystallinity other than single crystal (a microcrystalline semiconductor, a polycrystalline semiconductor, or a semiconductor having a crystalline region in part).

[0135] 1A shows an example in which the insulating layer 20 has a single layer structure. The insulating layer 20 can have a stacked structure of two or more layers. When the insulating layer 20 has a stacked structure of two or more layers, it is preferable to use the insulating material (typically silicon oxide) applicable to the insulating layer 20 described above as a layer in contact with the oxide semiconductor layer 30 among the two or more layers included in the insulating layer 20. With such a structure, oxygen can be supplied to the oxide semiconductor layer 30.

[0136] Furthermore, when the insulating material (typically silicon oxide) applicable to the insulating layer 20 described above is used as a layer that is not in contact with the oxide semiconductor layer 30 among the two or more layers included in the insulating layer 20, it is preferable that the oxygen permeability of the layer in contact with the oxide semiconductor layer 30 is high. In other words, it is preferable that the oxygen barrier property of the layer in contact with the oxide semiconductor layer 30 is low. With such a configuration, oxygen contained in the layer that is not in contact with the oxide semiconductor layer 30 can be supplied to the oxide semiconductor layer 30.

[0137] Note that by reducing the thickness of the layer in contact with the oxide semiconductor layer 30, the oxygen permeability of the layer in contact with the oxide semiconductor layer 30 increases. Therefore, the same effect can be achieved even when the thickness of the layer in contact with the oxide semiconductor layer 30 is reduced. The thickness of the layer in contact with the oxide semiconductor layer 30 is, for example, 0.1 nm to 3 nm, preferably 0.1 nm to 2 nm, more preferably 0.1 nm to 1 nm, and even more preferably 0.1 nm to 0.5 nm. In this case, the insulating material described in the "Insulating Layer" section below can be used for the layer in contact with the oxide semiconductor layer 30. For example, gallium oxide can be used.

[0138] FIG. 1A shows an example in which the insulating layer 50 has a single-layer structure. Note that the insulating layer 50 can have a stacked structure of two or more layers. When the insulating layer 50 has a stacked structure of two or more layers, it is preferable to use the insulating material (typically, aluminum oxide) applicable to the insulating layer 50 described above as a layer in contact with the oxide semiconductor layer 30 among the two or more layers included in the insulating layer 50. With such a structure, excess oxygen in the oxide semiconductor layer 30 can be discharged to the insulating layer 50. Furthermore, hydrogen in the oxide semiconductor layer 30 can be captured or fixed.

[0139] As described above, oxygen is pushed into the oxide semiconductor layer 30 from the insulating layer 20 side, reducing the amount of oxygen vacancies in the oxide semiconductor layer 30, and excess oxygen in the oxide semiconductor layer 30 is pulled from the insulating layer 50 side, reducing the amount of excess oxygen in the oxide semiconductor layer 30. Therefore, a semiconductor device with excellent reliability can be provided.

[0140] 1A shows a configuration in which the insulating layer 20, the oxide semiconductor layer 30, the insulating layer 50, and the conductive layer 60 are stacked in a direction perpendicular or substantially perpendicular to the substrate surface (not shown). However, the present invention is not limited to this. For example, as shown in FIG. 1F, the insulating layer 20, the oxide semiconductor layer 30, the insulating layer 50, and the conductive layer 60 can be stacked in a direction parallel or substantially parallel to the substrate surface (not shown).

[0141] 1G , for example, an opening 90 can be provided in the insulating layer 20, and the oxide semiconductor layer 30, the insulating layer 50, and the conductive layer 60 can be provided concentrically in the opening 90. Note that FIG. 1G is a perspective view in which a part of the semiconductor device of one embodiment of the present invention is cut away.

[0142] 1H , for example, a groove 91 can be provided in the insulating layer 20, and the oxide semiconductor layer 30, the insulating layer 50, and the conductive layer 60 can be provided in the groove 91. Note that FIG. 1H is a perspective view in which a part of the semiconductor device of one embodiment of the present invention is cut away.

[0143] [Example of Manufacturing Method of Semiconductor Device] The insulating layer 20, the oxide semiconductor layer 30, the insulating layer 50, and the conductive layer 60 can be formed by a sputtering method, a chemical vapor deposition (CVD) method, a vacuum evaporation method, a pulsed laser deposition (PLD) method, an ALD method, etc. In particular, the insulating layer 20, the oxide semiconductor layer 30, and the insulating layer 50 are preferably formed by an ALD method.

[0144] Unlike film formation methods in which particles emitted from a target or the like are deposited, the ALD method is a film formation method in which a film is formed by a reaction on the surface of a workpiece. Therefore, it is a film formation method that is less affected by the shape of the workpiece and has good step coverage. In particular, the ALD method has excellent step coverage and excellent thickness uniformity, making it suitable for coating the surfaces of openings or grooves with high aspect ratios.

[0145] Some precursors used in the ALD method contain elements such as carbon or chlorine. Therefore, films formed by the ALD method may contain more elements such as carbon or chlorine than films formed by other film formation methods. Quantitative determination of these elements can be performed using XPS or SIMS. When the ALD method is used, the amount of carbon and chlorine contained in the film may be lower by adopting a high substrate temperature during film formation and / or by performing an impurity removal process, compared to when the ALD method is used without these procedures.

[0146] Examples of the ALD method include a thermal ALD method in which a precursor and a reactant are reacted using only thermal energy, and a plasma enhanced ALD (PEALD) method in which a plasma-excited reactant is used.

[0147] In a film forming apparatus using the ALD method, a first source gas (sometimes called a precursor, precursor, or metal precursor) and a second source gas (sometimes called a reactant, reactant, oxidizer, or non-metal precursor) for the reaction are alternately introduced into a chamber, and film formation is performed by repeating the introduction of these source gases. Note that the introduction of the source gases can be switched by, for example, switching the respective switching valves (sometimes called high-speed valves). In addition, when introducing the source gases, nitrogen (N ２ An inert gas such as argon (Ar), argon (Ar), or helium (He) may be introduced into the chamber together with the source gas as a carrier gas. By using a carrier gas, even if the source gas has low volatility or a low vapor pressure, it is possible to suppress the source gas from being adsorbed inside the piping and the valve, and to introduce the source gas into the chamber. This also improves the uniformity of the film formed, which is preferable.

[0148] In addition, in the ALD method, a film of any composition can be formed by simultaneously introducing multiple different precursors, or by controlling the number of cycles of each precursor when multiple different precursors are introduced.

[0149] First, an insulating layer 20 is formed on a structure (not shown). That is, the structure includes a surface on which the insulating layer 20 is to be formed. The surface may have a flat shape, or may have a convex portion, a convex curved surface, a concave curved surface, a recess, an opening, or the like. For example, when the surface has a flat shape, the semiconductor device shown in FIG. 1A can be formed.

[0150] The insulating layer 20 is preferably formed using an ALD method. A first precursor and a first oxidizing agent can be used to form the insulating layer 20. The first precursor preferably contains silicon. In this case, a silicon oxide film is formed as the insulating layer 20. That is, an oxide film containing a single element other than oxygen is formed. Note that when the first precursor contains silicon, a PEALD method can be used as the ALD method.

[0151] Examples of the silicon-containing precursor that can be used include trisilylamine, bis(diethylamino)silane, tris(dimethylamino)silane, bis(tert-butylamino)silane, and bis(ethylmethylamino)silane.

[0152] As the first oxidant, ozone (O ３ ), oxygen (O ２ ), water (H ２ By using ozone, oxygen, or the like that does not contain hydrogen as the first oxidizing agent, the amount of hydrogen that gets mixed into the insulating layer 20 can be reduced.

[0153] In this specification and the like, unless otherwise specified, when ozone, oxygen, or water is used as an oxidizing agent, it is not limited to the gas or molecular state, but also includes the plasma state, radical state, or ion state.

[0154] The insulating layer 20 can be formed by sputtering in an atmosphere containing oxygen. By using a sputtering method that does not require the use of hydrogen-containing molecules in the deposition gas, the hydrogen concentration in the insulating layer 20 can be reduced. Furthermore, by forming the insulating layer 20 by sputtering in an atmosphere containing oxygen, oxygen can be added to the insulating layer 20. Oxygen is supplied from the insulating layer 20 to the channel formation region of the oxide semiconductor layer 30 by heat or the like applied after the formation of the oxide semiconductor layer 30, and oxygen vacancies and V Ｏ H can be reduced.

[0155] Heat treatment is preferably performed before forming the oxide semiconductor layer 30. The heat treatment is performed at a temperature of, for example, 250° C. or higher and 650° C. or lower, preferably 300° C. or higher and 500° C. or lower, and more preferably 320° C. or higher and 450° C. or lower.

[0156] The heat treatment is performed in an atmosphere of nitrogen gas or an inert gas, or an atmosphere containing an oxidizing gas at 10 ppm or more, 1% or more, or 10% or more. For example, when the heat treatment is performed in a mixed atmosphere of nitrogen gas and oxygen gas, the oxygen gas concentration is preferably about 20%. The heat treatment may be performed under reduced pressure. Alternatively, after the heat treatment in the nitrogen gas or inert gas atmosphere, the heat treatment may be performed in an atmosphere containing an oxidizing gas at 10 ppm or more, 1% or more, or 10% or more to compensate for the desorbed oxygen. By performing the above-described heat treatment, impurities such as hydrogen or water contained in the insulating layer 20 or the like can be reduced before the formation of the oxide semiconductor layer 30.

[0157] Furthermore, the gas used in the heat treatment is preferably highly purified. For example, the amount of moisture contained in the gas used in the heat treatment is preferably 1 ppb or less, more preferably 0.1 ppb or less, and even more preferably 0.05 ppb or less. By performing the heat treatment using a highly purified gas, it is possible to prevent moisture and the like from being absorbed into the insulating layer 20 and the like as much as possible.

[0158] Furthermore, it is preferable to perform a process of supplying oxygen before forming the oxide semiconductor layer 30. As a result, oxygen is supplied to the insulating layer 20, and oxygen can be supplied from the insulating layer 20 to the oxide semiconductor layer 30 by heat or the like applied after the formation of the oxide semiconductor layer 30.

[0159] Examples of the treatment for supplying oxygen include heat treatment in an oxygen-containing atmosphere and plasma treatment (including microwave plasma treatment) in an oxygen-containing atmosphere. Alternatively, oxygen may be supplied to the insulating layer 20 by depositing an oxide film (preferably a metal oxide film) in an oxygen-containing atmosphere by sputtering. The deposited oxide film may be removed immediately after deposition or may be left as it is. In the case where the deposited oxide film is left as it is, the oxide film can be used as part of the oxide semiconductor layer 30. Note that the oxygen-containing atmosphere may be oxygen gas (O ２ ) as well as ozone (O ３ ) or nitrous oxide (N ２The atmosphere includes a gas containing a compound containing oxygen such as oxygen (O). The substrate temperature during the plasma treatment is set to be equal to or higher than room temperature (25° C.) and equal to or lower than 450° C.

[0160] Furthermore, an opening 90 may be formed in the insulating layer 20 before the oxide semiconductor layer 30 is formed. By forming the opening 90, the semiconductor device shown in FIG. 1G can be formed. Alternatively, a groove 91 may be formed in the insulating layer 20 before the oxide semiconductor layer 30 is formed. By forming the groove 91, the semiconductor device shown in FIG. 1H can be formed.

[0161] Next, the oxide semiconductor layer 30 is formed on the insulating layer 20. The oxide semiconductor layer 30 is preferably formed by ALD. A second precursor and a second oxidizing agent can be used to form the oxide semiconductor layer 30. The second precursor preferably contains indium. In this case, an indium oxide film is formed as the oxide semiconductor layer 30. That is, an oxide film containing a single element other than oxygen is formed. Note that when the second precursor contains indium, a thermal ALD method can be used as the ALD method.

[0162] In the method for forming the oxide semiconductor layer 30, it is preferable to use a material with a low impurity concentration. In other words, it is preferable to use a high-purity material in the method for forming the oxide semiconductor layer 30. For example, the purity of the second precursor is preferably 3N (99.9%) or higher, more preferably 4N (99.99%) or higher, more preferably 5N (99.999%) or higher, and even more preferably 6N (99.9999%) or higher. By using a high-purity material, it is possible to reduce impurities in the oxide semiconductor layer 30.

[0163] The gallium content in the second precursor is preferably 1000 ppm or less, more preferably 500 ppm or less, even more preferably 100 ppm or less, still more preferably 50 ppm or less, still more preferably 10 ppm or less, and still more preferably 1 ppm or less. By using a precursor with a low gallium content, it is possible to form an oxide semiconductor layer 30 with a low gallium concentration.

[0164] The aluminum content in the second precursor is preferably 1000 ppm or less, more preferably 500 ppm or less, even more preferably 100 ppm or less, still more preferably 50 ppm or less, still more preferably 10 ppm or less, and still more preferably 1 ppm or less. By using a precursor with a low aluminum content, the aluminum concentration in the oxide semiconductor layer 30 can be reduced, and the crystallinity of the oxide semiconductor layer 30 can be improved.

[0165] Examples of precursors that can be used that contain indium include trimethylindium, triethylindium, ethyldimethylindium, tris(1-methylethyl)indium, tris(2,2,6,6-tetramethyl-3,5-heptanedionate)indium, cyclopentadienylindium, indium(III) acetylacetonate, (3-(dimethylamino)propyl)dimethylindium, (diethylphosphino)dimethylindium, chlorodimethylindium, bromodimethylindium, and dimethyl(2-propanolato)indium.

[0166] Alternatively, an inorganic precursor containing no hydrocarbon may be used as the indium-containing precursor. Examples of the inorganic precursor containing indium include halogen-based indium compounds such as trifluoroindium (indium(III) fluoride), indium trichloride (indium(III) chloride), indium tribromide (indium(III) bromide), and indium triiodide (indium(III) iodide). Indium trichloride has a decomposition temperature of approximately 500°C to 700°C. Therefore, by using indium trichloride, film formation can be performed by the ALD method while heating the substrate at approximately 400°C to 600°C, for example, at 500°C.

[0167] The second oxidizing agent preferably contains ozone. Note that the above-described materials that can be used for the first oxidizing agent can be used for the second oxidizing agent. By using ozone, oxygen, or the like that does not contain hydrogen as the second oxidizing agent, the amount of hydrogen mixed into the oxide semiconductor layer 30 can be reduced.

[0168] Here, the temperature to which the substrate is heated when the second precursor is introduced into the reaction chamber is defined as a first temperature, and the temperature to which the substrate is heated when the second oxidizing agent is introduced into the reaction chamber is defined as a second temperature.

[0169] The first temperature is preferably set to a temperature corresponding to the decomposition temperature of the second precursor. In the case of a thermal ALD method using triethylindium as the indium-containing precursor, the first temperature is, for example, 100° C. or higher and 350° C. or lower, preferably 150° C. or higher and 300° C. or lower. By providing the oxide layer 27, the oxide semiconductor layer 30 can be formed with crystallinity even if the first temperature is lower than the above-mentioned temperature. When the oxide layer 27 is provided, the first temperature can be set to a temperature ranging from room temperature (25° C.) to 300° C. or lower, preferably from room temperature to 200° C. or lower, and more preferably from room temperature to 150° C. or lower.

[0170] The second temperature is preferably higher than the first temperature. For example, when the second oxidizing agent contains ozone, the second temperature is preferably higher than 200°C and lower than 450°C, more preferably 250°C or higher and 400°C or lower, and even more preferably 300°C or higher and 350°C or lower. This configuration can reduce the hydrogen concentration in the oxide semiconductor layer. Furthermore, setting the first temperature lower than the second temperature can suppress particles generated by decomposition of the second precursor. The second temperature may be the same as the first temperature. This configuration can maintain a constant substrate heating temperature during deposition of the oxide semiconductor layer 30, thereby improving productivity.

[0171] It is preferable that the reaction chamber into which the second precursor is introduced and the reaction chamber into which the second oxidizing agent is introduced are the same. This configuration allows for film formation without the need to load and unload the substrate, thereby improving productivity. It is also possible to use different reaction chambers for the introduction of the second precursor and the introduction of the second oxidizing agent. By providing a first reaction chamber set to the first temperature and a second reaction chamber set to the second temperature, the first temperature and the second temperature can be maintained, respectively. This facilitates temperature control, improving work efficiency and safety.

[0172] When the indium oxide film included in the oxide semiconductor layer 30 is formed by the ALD method, the edges of the indium oxide are presumably passivated because they are terminated with oxygen. It is presumed that the passivation of the edges results in fewer defects in the edges of the indium oxide film. Therefore, it is presumed that a highly reliable transistor can be realized.

[0173] Note that the oxide semiconductor layer 30 can be formed by a sputtering method in an atmosphere containing oxygen. Furthermore, by using a sputtering method that does not require the use of hydrogen-containing molecules in a deposition gas, the hydrogen concentration in the oxide semiconductor layer 30 can be reduced. For example, oxygen or a mixed gas of oxygen and a noble gas may be used as a sputtering gas.

[0174] The oxide semiconductor layer 30 can be formed using, for example, a sputtering method or an ALD method. For example, when the oxide semiconductor layer 30 has a two-layer structure of an oxide semiconductor layer 30a and an oxide semiconductor layer 30b (see FIG. 1E), the oxide semiconductor layer 30a can be formed by an ALD method, and the oxide semiconductor layer 30b can be formed by a sputtering method. Because the ALD method provides superior coverage compared to the sputtering method, forming the oxide semiconductor layer 30a by the ALD method can improve the coverage of the oxide semiconductor layer 30. Therefore, the oxide semiconductor layer can be well coated on steps, openings, and the like with a high aspect ratio. Furthermore, because the ALD method causes minimal damage to the surface on which the oxide layer 27 is formed, forming the oxide semiconductor layer 30a by the ALD method can promote epitaxial growth of the oxide semiconductor layer 30a. Furthermore, forming the oxide semiconductor layer 30b by the sputtering method can improve productivity. Moreover, the oxide semiconductor layer 30 having high crystallinity or high film density can be formed.

[0175] Alternatively, the oxide semiconductor layer 30a may be formed by sputtering, and the oxide semiconductor layer 30b may be formed by ALD. An oxide semiconductor layer formed by sputtering tends to have crystallinity. Therefore, by providing a crystalline oxide semiconductor layer as the oxide semiconductor layer 30a, the crystallinity of the oxide semiconductor layer 30b can be improved. Even if pinholes or discontinuities are formed in the oxide semiconductor layer 30a formed by sputtering, the overlapping portions can be filled with the oxide semiconductor layer 30b formed by ALD, which has good coverage.

[0176] Note that sputtering is a deposition method that causes relatively large damage to the surface on which the oxide semiconductor layer 30a is formed, and therefore, when the oxide semiconductor layer 30a is formed by sputtering, a mixed layer with low crystallinity may be formed between the insulating layer 20 and the oxide semiconductor layer 30a or in the oxide semiconductor layer 30a near the insulating layer 20. However, in the present invention, it is sufficient that the channel formation region 31 located on the upper side (the insulating layer 50 side) of the oxide semiconductor layer 30a has high crystallinity. Therefore, by increasing the thickness of the oxide semiconductor layer 30 within the above-mentioned range, a configuration can be achieved in which a mixed layer is not formed in the channel formation region 31. Therefore, the crystallinity of the channel formation region 31 can be improved.

[0177] Note that, before forming the oxide semiconductor layer 30, the oxide layer 27 may be formed on the insulating layer 20. The oxide layer 27 can be formed by a sputtering method, a CVD method, a vacuum deposition method, a PLD method, an ALD method, or the like.

[0178] The oxide layer 27 is preferably formed using an ALD method. By forming the oxide layer 27 using an ALD method, the coverage of the oxide layer 27 can be improved. Furthermore, when the oxide layer 27 and the oxide semiconductor layer 30 are formed using the same film formation method, the oxide layer 27 and the oxide semiconductor layer 30 are preferably formed successively without being exposed to the atmosphere. By forming the two types of films successively without being exposed to the atmosphere, productivity can be improved. Furthermore, impurities (typically moisture, etc.) that are introduced into the interface between the two types of films and the vicinity thereof can be reduced.

[0179] The oxide layer 27 can also be formed by a sputtering method. Forming the oxide layer 27 by a sputtering method can improve the crystallinity of the oxide semiconductor layer 30. Furthermore, forming the oxide layer 27 by a sputtering method in an atmosphere containing oxygen can add oxygen to the insulating layer 20.

[0180] When the oxide layer 27 is provided and the oxide semiconductor layer 30 has a two-layer structure of the oxide semiconductor layer 30a and the oxide semiconductor layer 30b, it is preferable to form the oxide layer 27 by a sputtering method, the oxide semiconductor layer 30a by an ALD method, and the oxide semiconductor layer 30b by a sputtering method. With this configuration, the oxide semiconductor layer 30a can be epitaxially grown from the oxide layer 27, thereby improving the crystallinity of the oxide semiconductor layer 30a. For example, the oxide layer 27 can be formed using a YSZ film deposited by a sputtering method, the oxide semiconductor layer 30a can be formed using an indium oxide film deposited by an ALD method, and the oxide semiconductor layer 30b can be formed using an IGZO film deposited by a sputtering method. In this case, for example, it is preferable that the oxide layer 27 has a region with a film thickness of 1 nm or more and 5 nm or less, the oxide semiconductor layer 30a has a region with a film thickness of 5 nm or more and 7 nm or less, and the oxide semiconductor layer 30b has a region with a film thickness of 3 nm or more and 5 nm or less.

[0181] After the oxide semiconductor layer 30 is formed, a process of supplying oxygen to the oxide semiconductor layer 30 may be performed. This allows oxygen to be supplied to the oxide semiconductor layer 30 by heat or the like applied after this process. Note that the above description can be referred to for details of the process of supplying oxygen.

[0182] Next, heat treatment is preferably performed. By performing the heat treatment, impurities such as hydrogen or water contained in the oxide semiconductor layer 30 can be reduced. The temperature of the heat treatment is preferably 100° C. to 650° C., more preferably 250° C. to 600° C., and still more preferably 300° C. to 500° C. or 350° C. to 550° C. For details of the heat treatment, refer to the above description.

[0183] The gas used in the heat treatment is preferably highly purified. By performing the heat treatment using a highly purified gas, moisture and the like can be prevented from being introduced into the oxide semiconductor layer 30 as much as possible.

[0184] The heat treatment can reduce impurities such as carbon, hydrogen, or water in the oxide semiconductor layer 30. Reducing the impurities in the film in this manner improves the crystallinity of the oxide semiconductor layer 30, resulting in a denser and more compact structure. This increases the crystalline regions in the oxide semiconductor layer 30, reducing in-plane variations in the crystalline regions in the oxide semiconductor layer 30. This reduces in-plane variations in the electrical characteristics of the transistor.

[0185] In addition, in the case where the insulating layer 20 contains oxygen, the heat treatment preferably supplies oxygen from the insulating layer containing oxygen to the channel formation region of the oxide semiconductor layer 30. As a result, oxygen vacancies and V Ｏ H can be reduced.

[0186] Note that microwave plasma treatment may be performed after the formation of the oxide semiconductor layer 30. By performing the microwave plasma treatment, the concentration of impurities such as hydrogen or water contained in the oxide semiconductor layer 30 can be reduced. Furthermore, a crystalline region of the oxide semiconductor layer 30 may grow.

[0187] In this specification, microwaves refer to electromagnetic waves having a frequency of 300 MHz to 300 GHz. Microwave plasma treatment refers to treatment using a device with a power source that generates high-density plasma using microwaves. Microwave plasma treatment can also be called microwave-excited high-density plasma treatment.

[0188] By performing microwave plasma treatment in an atmosphere containing oxygen, the impurity concentration in the oxide semiconductor layer 30 can be reduced. Examples of impurities include hydrogen and carbon. While the above example illustrates a configuration in which microwave plasma treatment is performed on the oxide semiconductor layer 30 in an atmosphere containing oxygen, the present invention is not limited to this. For example, microwave plasma treatment may be performed on an insulating film, more specifically, a silicon oxide film, provided near the oxide semiconductor layer 30 in an atmosphere containing oxygen. Furthermore, the heat generated by the microwave plasma treatment may enhance the crystallinity of the oxide semiconductor layer 30.

[0189] The microwave plasma treatment is preferably carried out under reduced pressure, and the pressure is preferably from 10 to 1000 Pa, more preferably from 50 to 700 Pa, and even more preferably from 100 to 400 Pa. The treatment temperature is preferably from room temperature (25°C) to 750°C, more preferably from 300 to 500°C, and can be from 400 to 450°C.

[0190] When microwave plasma treatment is performed, the substrate may be heated. The substrate is preferably heated to a temperature above room temperature (e.g., 25°C), above 100°C, above 200°C, above 300°C, or above 400°C, and below 500°C or below 450°C. For example, the substrate is preferably heated to a temperature above room temperature and below 500°C, more preferably above 100°C and below 450°C, more preferably above 200°C and below 450°C, even more preferably above 300°C and below 450°C, and even more preferably above 400°C and below 450°C.

[0191] The microwave plasma treatment can be performed using, for example, oxygen gas and argon gas. The oxygen flow rate ratio (O ２ / (O ２ If the oxygen flow rate ratio (O + Ar) is too high, the discharge becomes unstable. ２ / (O ２ +Ar)) is preferably greater than 0% and less than 50%, more preferably greater than 0% and less than 40%, and even more preferably greater than 0% and less than 30%. In microwave plasma treatment using oxygen gas and argon gas, the main oxygen radical is triplet oxygen (O( ３ P ｊ )), singlet oxygen (O( １ D ２ )), and oxygen ions (O ２ ＋) can take three states. Note that oxygen ions act effectively in reducing the hydrogen concentration in the oxide film by microwave plasma processing. The amount of oxygen radicals in each state varies depending on the oxygen flow rate ratio or pressure in microwave plasma processing. For example, under conditions where the oxygen flow rate ratio is low and the pressure is low, the amount of oxygen ions tends to increase. On the other hand, if the oxygen flow rate ratio or pressure is excessively low, there is a concern that the control of the oxygen flow rate becomes unstable, making it difficult to stabilize the discharge, and that the oxide film may be etched. Therefore, for example, when the oxygen flow rate ratio (O ２ / (O ２ +Ar)) is preferably greater than 0% and not greater than 10%, more preferably 0.5% to 5%, more preferably 0.5% to 3%, and typically more preferably 1%.

[0192] The shorter the processing time of the microwave plasma treatment, the higher the productivity. Therefore, for example, the processing time of the microwave plasma treatment is preferably from 1 minute to 60 minutes, more preferably from 1 minute to 30 minutes, and even more preferably from 1 minute to 10 minutes.

[0193] By performing microwave plasma treatment in an atmosphere containing oxygen, oxygen gas is converted into plasma using microwaves or high frequency waves such as RF, and oxygen radicals generated by converting the oxygen gas into plasma can act on the oxide semiconductor layer. Ｏ By splitting H into oxygen vacancies and hydrogen, it is possible to remove hydrogen as an impurity from the oxide semiconductor layer. Ｏ H can be reduced. At this time, carbon bonded to oxygen, hydrogen, or the like can also be removed in some cases. In this way, impurities such as carbon or hydrogen can be reduced by performing microwave plasma treatment. Furthermore, by supplying the oxygen radicals to oxygen vacancies formed in the oxide semiconductor layer, the oxygen vacancies in the oxide semiconductor layer can be further reduced.

[0194] Furthermore, a reaction occurs between part of oxygen in the oxide semiconductor that exists before the microwave plasma treatment and hydrogen in the oxide semiconductor. In other words, the reaction proceeds as follows: 2H + O → H ２ O↑” reaction occurs, converting the hydrogen to H ２ O (also called dehydration or dehydrogenation). ２ Since O is one of the factors that hinder improvement of crystallinity, it is preferable to remove O from the oxide semiconductor. ２ The hydrogen concentration in the oxide semiconductor can be reduced by removing the hydrogen as O, which can also promote improvement in crystallinity. Note that the hydrogen concentration in the oxide semiconductor can be further reduced by increasing the temperature during the microwave plasma treatment.

[0195] Note that after the microwave plasma treatment, a heat treatment may be performed consecutively without exposure to the open air. The temperature of the heat treatment is, for example, preferably 100° C. to 750° C., more preferably 300° C. to 500° C., and even more preferably 400° C. to 450° C. By setting the temperature within the above range, deformation (distortion or warpage) of the substrate can be significantly reduced even when the heat treatment is performed.

[0196] It should be noted that the crystallinity can be improved by plasma treatment containing oxygen gas instead of microwave plasma treatment.

[0197] Oxygen supplied to the oxide semiconductor layer can be in various forms, such as oxygen atoms, oxygen molecules, oxygen ions (charged oxygen atoms or oxygen molecules), and oxygen radicals (oxygen atoms, oxygen molecules, or oxygen ions with an unpaired electron). Note that the oxygen injected into the oxide semiconductor layer is preferably in one or more of the above forms, and is particularly preferably in the form of oxygen radicals.

[0198] In this manner, it is possible to reduce impurities in the oxide semiconductor layer 30. Furthermore, it is possible to improve the crystallinity of the oxide semiconductor layer 30.

[0199] Subsequently, the insulating layer 50 is formed on the oxide semiconductor layer 30. The insulating layer 50 is preferably formed by ALD. A third precursor and a third oxidizing agent can be used to form the insulating layer 50. The third precursor preferably contains one of aluminum and hafnium. In this case, an aluminum oxide film or a hafnium oxide film is formed as the insulating layer 50. In other words, an oxide film containing a single element other than oxygen is formed. Note that when the third precursor contains one of aluminum and hafnium, a thermal ALD method can be used as the ALD method.

[0200] Examples of precursors that can be used include aluminum chloride and trimethylaluminum, and examples of precursors that can be used include hafnium tetrachloride and tetrakis(ethylmethylamido)hafnium (TEMAHf).

[0201] The third oxidizing agent may be any of the materials that can be used for the first oxidizing agent.

[0202] In the ALD process, a precursor is introduced into a chamber and adsorbed onto the substrate surface. The adsorption of the precursor onto the substrate surface activates a self-limiting mechanism for the surface chemical reaction, preventing further adsorption of the precursor onto the precursor layer on the substrate. The appropriate substrate temperature range within which the self-limiting mechanism for the surface chemical reaction operates is also referred to as the ALD window. The ALD window is determined by the precursor's temperature characteristics, vapor pressure, decomposition temperature, and other factors. In other words, the ALD window varies depending on the precursor. Therefore, when depositing an oxide film containing multiple elements other than oxygen, it is necessary to adjust the film formation conditions taking into account the ALD window of each precursor. On the other hand, when depositing an oxide film containing a single element other than oxygen, such as indium oxide or aluminum oxide, the film formation conditions can be adjusted by considering only the ALD window of one precursor, which facilitates the adjustment of the film formation conditions and allows for the formation of a high-quality oxide film.

[0203] The first oxidizing agent, the second oxidizing agent, and the third oxidizing agent may all be the same oxidizing agent, or at least one of them may be a different oxidizing agent.

[0204] Furthermore, when the insulating layer 20 and the oxide semiconductor layer 30 are formed using the same film formation method, it is preferable to form the insulating layer 20 and the oxide semiconductor layer 30 consecutively without exposing them to the atmosphere. Alternatively, when the oxide semiconductor layer 30 and the insulating layer 50 are formed using the same film formation method, it is preferable to form the oxide semiconductor layer 30 and the insulating layer 50 consecutively without exposing them to the atmosphere. Alternatively, when the insulating layer 20, the oxide semiconductor layer 30, and the insulating layer 50 are formed using the same film formation method, it is preferable to form the insulating layer 20, the oxide semiconductor layer 30, and the insulating layer 50 consecutively without exposing them to the atmosphere. By forming two or more types of films consecutively without exposing them to the atmosphere, it is possible to increase productivity. Furthermore, it is possible to reduce impurities (typically moisture, etc.) that are introduced into the interface between the two types of films and its vicinity.

[0205] As an example, it is preferable to form the oxide semiconductor layer 30 by thermal ALD, and then continuously form the insulating layer 50 by thermal ALD without exposing the process to the atmosphere. In this case, by using the same oxidizing agent for the second oxidizing agent and the third oxidizing agent and using a reaction chamber into which the second precursor and the third precursor can be introduced, the oxide semiconductor layer 30 and the insulating layer 50 can be formed without carrying in and out the substrate, thereby improving productivity.

[0206] Microwave plasma treatment is preferably performed after the insulating layer 50 is formed. By performing the microwave plasma treatment, the concentration of impurities such as hydrogen or water contained in the oxide semiconductor layer 30 can be reduced. For details of the microwave plasma treatment, refer to the above description.

[0207] Subsequently, the conductive layer 60 is formed on the insulating layer 50 .

[0208] Through the above steps, a semiconductor device of one embodiment of the present invention can be manufactured.

[0209] This embodiment mode can be combined with other embodiment modes or examples as appropriate. In addition, in this specification, when a plurality of configuration examples are shown in one embodiment mode, the configuration examples can be combined as appropriate.

[0210] Second Embodiment In this embodiment, a semiconductor device to which the configuration described in the first embodiment is applied will be described.

[0211] <Structural Example 1 of Semiconductor Device> A structural example of a semiconductor device of one embodiment of the present invention will be described with reference to FIGS. 2A to 24C.

[0212] 2A and 2B are schematic perspective views of a semiconductor device having a transistor 200A. Fig. 2B is a perspective view in which a part of Fig. 2A is cut away. In Fig. 2A and 2B, only the outlines of some components (such as interlayer insulating layers) are indicated by dashed lines.

[0213] 2A and 2B, the X, Y, and Z directions are indicated by arrows. Note that although the same X, Y, and Z symbols are used in both FIGS. 2A and 2B, the directions do not necessarily have to match.

[0214] Fig. 3A is a plan view of a semiconductor device having a transistor 200A. Fig. 3B is a cross-sectional view taken along dashed dotted line A1-A2 in Fig. 3A. Fig. 3C is a cross-sectional view taken along dashed dotted line A3-A4 in Fig. 3A. Fig. 3D is a cross-sectional view taken along dashed dotted line A5-A6 in Fig. 3B. Note that some elements are omitted in the plan view of Fig. 3A for clarity. Some elements may also be omitted in the subsequent plan views.

[0215] 4A is a cross-sectional view taken along dashed lines A1-A2 in FIG. 3A. FIG. 4B is a cross-sectional view taken along dashed lines A5-A6 in FIG. 3B. FIG. 4A and FIG. 4B correspond to examples of enlarged views of FIG. 3B and FIG. 3D, respectively.

[0216] The semiconductor device shown in FIGS. 3A to 3D includes an insulating layer 210 on a substrate (not shown), a transistor 200A on the insulating layer 210, and an insulating layer 280 on the insulating layer 210.

[0217] [Transistor 200A] The transistor 200A includes a conductive layer 220, a conductive layer 240 over an insulating layer 280, an oxide semiconductor layer 230, an insulating layer 250 over the oxide semiconductor layer 230, and a conductive layer 260 over the insulating layer 250. The insulating layer 280 is located over the conductive layer 220.

[0218] 3B and 3C show an example in which the conductive layer 220 has a two-layer structure of a conductive layer 220_1 and a conductive layer 220_2 on the conductive layer 220_1, the conductive layer 240 has a two-layer structure of a conductive layer 240_1 and a conductive layer 240_2 on the conductive layer 240_1, and the conductive layer 260 has a two-layer structure of a conductive layer 260_1 and a conductive layer 260_2 on the conductive layer 260_1.

[0219] In the transistor 200A, the oxide semiconductor layer 230 functions as a semiconductor layer, the conductive layer 260 functions as a gate electrode, the insulating layer 250 functions as a gate insulating layer, the conductive layer 220 functions as one of a source electrode and a drain electrode, and the conductive layer 240 functions as the other of the source electrode and the drain electrode. The conductive layer 260 has a region that functions as a gate wiring.

[0220] The oxide semiconductor layer 230, the insulating layer 280, the insulating layer 250, and the conductive layer 260 included in the transistor 200A correspond to the oxide semiconductor layer 30, the insulating layer 20, the insulating layer 50, and the conductive layer 60, respectively, described in Embodiment 1. Therefore, the structures, materials, and the like of the oxide semiconductor layer 30, the insulating layer 20, the insulating layer 50, and the conductive layer 60 described in Embodiment 1 can be referred to for the structures, materials, and the like of the oxide semiconductor layer 230, the insulating layer 280, the insulating layer 250, and the conductive layer 260.

[0221] As shown in FIGS. 3B and 3C, an opening 290 is provided in the insulating layer 280 and the conductive layer 240, reaching the conductive layer 220.

[0222] The openings 290 include an opening in the insulating layer 280 and an opening in the conductive layer 240. The shape and size of the openings 290 in a plan view may differ depending on the layer. When the top surface shape of the openings 290 is circular, the openings in each layer may or may not be concentric.

[0223] The oxide semiconductor layer 230, the insulating layer 250, and the conductive layer 260 are each arranged so that at least a portion thereof is located within the opening 290. Furthermore, the portions of the oxide semiconductor layer 230, the insulating layer 250, and the conductive layer 260 that are arranged within the opening 290 are provided so as to reflect the shape of the opening 290.

[0224] The oxide semiconductor layer 230 is provided so as to cover the bottom and sidewalls of the opening 290. The oxide semiconductor layer 230 has a recess that reflects the shape of the opening 290. The oxide semiconductor layer 230 has a portion that contacts the top surface of the conductive layer 240 and a portion that contacts the top surface of the conductive layer 220 within the opening 290.

[0225] The insulating layer 250 is provided to cover the oxide semiconductor layer 230. The insulating layer 250 is provided on the insulating layer 280 to cover the top surface and side surfaces of the oxide semiconductor layer 230 and the side surfaces of the conductive layer 240. The insulating layer 250 has a recess that reflects the shape of the recess that the oxide semiconductor layer 230 has.

[0226] The conductive layer 260 is provided so as to fill at least a part of the recessed portion of the insulating layer 250. In addition, the conductive layer 260 has a region in the opening 290 that overlaps with the oxide semiconductor layer 230 with the insulating layer 250 sandwiched therebetween.

[0227] The oxide semiconductor layer 230 has a region overlapping with the conductive layer 260 with the insulating layer 250 interposed therebetween. At least part of the region functions as a channel formation region of the transistor 200A. One of a region of the oxide semiconductor layer 230 near the conductive layer 220 and a region of the oxide semiconductor layer 230 near the conductive layer 240 functions as a source region, and the other functions as a drain region. That is, the channel formation region is sandwiched between the source region and the drain region.

[0228] The oxide semiconductor layer 230 is provided inside the opening 290. The transistor 200A has a structure in which one of the source electrode and the drain electrode (the conductive layer 220 here) is located below and the other of the source electrode and the drain electrode (the conductive layer 240 here) is located above, and thus current flows vertically. That is, a channel is formed along the side surface of the opening 290. This allows the transistor 200A to occupy a smaller area than a planar transistor in which a channel formation region, a source region, and a drain region are separately provided on the XY plane. Therefore, the semiconductor device can be highly integrated. Furthermore, when the semiconductor device of one embodiment of the present invention is used in a memory device, the memory capacity per unit area can be increased. Note that the channel length direction of the transistor 200A can be said to have a component in the height direction (vertical direction); therefore, the transistor 200A can be called a VFET (Vertical Field Effect Transistor), a vertical transistor, a vertical channel transistor, a vertical channel transistor, or the like.

[0229] The transistor 200A includes a metal oxide functioning as a semiconductor in the oxide semiconductor layer 230 including a channel formation region. That is, the transistor 200A can be said to be an OS transistor.

[0230] As shown in FIG. 4A , the conductive layer 220 has a recess overlapping the opening 290. Specifically, the recess is provided in the conductive layer 220_2 at a position overlapping the opening 290. By having the recess overlapping the opening 290 in the conductive layer 220_2, the height of the bottom surface of the insulating layer 250 and the height of the bottom surface of the conductive layer 260 in the opening 290 can be lower than the height of the top surface of the conductive layer 220_2 that is in contact with the insulating layer 280, relative to the top surface of the insulating layer 210, compared to when the recess is not provided. Here, the height of each surface can be determined based on the surface on which the transistor is to be formed. Here, the top surface of the insulating layer 210 is used as the reference. The surface used as the reference is not limited to the surface on which the transistor is to be formed. For example, the top surface of a substrate on which a transistor or a semiconductor device is provided may be used as the reference.

[0231] The oxide semiconductor layer 230 is in contact with the bottom and side surfaces of the recessed portion of the conductive layer 220_2. The recessed portion in the conductive layer 220_2 can increase the area where the oxide semiconductor layer 230 and the conductive layer 220_2 are in contact with each other. Therefore, the contact resistance between the oxide semiconductor layer 230 and the conductive layer 220_2 can be reduced.

[0232] 3C illustrates a structure in which the end of the conductive layer 240 and the end of the oxide semiconductor layer 230 are aligned or substantially aligned outside the opening 290. The conductive layer 240 and the oxide semiconductor layer 230 can be manufactured by processing using the same mask. This is preferable because the number of masks required for manufacturing a semiconductor device can be reduced. Note that the present invention is not limited to this. For example, a structure may be employed in which any one of the end of the oxide semiconductor layer 230, the end of the conductive layer 240_1, and the end of the conductive layer 240_2 is located inside or outside the other in the X direction or Y direction.

[0233] It is preferable that the side surface of the conductive layer 240 and the side surface of the insulating layer 280 coincide or substantially coincide within the opening 290. With such a configuration, the opening 290 can be formed simultaneously in the conductive layer 240 and the insulating layer 280. Furthermore, the film thickness distribution of the oxide semiconductor layer 230 and the like provided within the opening 290 can be made uniform. Furthermore, it is possible to prevent the oxide semiconductor layer 230 and the like from being divided by a step or the like between the conductive layer 240 and the insulating layer 280.

[0234] 3A, the transistor 200A is provided at the intersection of a conductive layer 260 extending in the X direction and a conductive layer 240 extending in the Y direction. As shown in FIG. 3A, the diameter of the opening 290 can be made smaller than both the width of the short side of the conductive layer 240 and the width of the short side of the conductive layer 260. In this way, the transistor 200A can be said to have a structure that allows for high integration and miniaturization.

[0235] As shown in FIG. 4B , by forming the opening 290 to have a circular shape in a plan view, the oxide semiconductor layer 230, the insulating layer 250, and the conductive layer 260 are arranged concentrically. Therefore, the side surface of the conductive layer 260 provided at the center of the opening 290 faces the side surface of the oxide semiconductor layer 230 with the insulating layer 250 interposed therebetween. That is, in a plan view, the entire periphery of the oxide semiconductor layer 230 becomes a channel formation region. In this case, for example, the channel width of the transistor 200A is determined by the periphery length of the oxide semiconductor layer 230. That is, the channel width of the transistor 200A can be determined by the width of the opening 290 (or the diameter when the opening 290 is circular in a plan view). In FIGS. 4A and 4B , the width D of the opening 290 is shown, and in FIG. 4B , the channel width W of the transistor 200A is shown.

[0236] Furthermore, by providing the oxide semiconductor layer 230, the insulating layer 250, and the conductive layer 260 concentrically, the distance between the conductive layer 260 and the oxide semiconductor layer 230 becomes approximately uniform, and therefore a gate electric field can be applied to the oxide semiconductor layer 230 approximately uniformly.

[0237] Increasing the width D of the opening 290 increases the channel width per unit area, thereby increasing the on-state current. Meanwhile, the area occupied by the transistor 200A, for example, the area of ​​the transistor 200A in a plan view, is roughly determined by the width of the opening 290. Reducing the width D of the opening 290 reduces the area occupied by the transistor 200A, thereby enabling a semiconductor device to be highly integrated.

[0238] The width D of the opening 290 may vary in the depth direction. Here, the shortest distance between the two side surfaces of the conductive layer 240 on the opening side in a cross-sectional view is used as the width D. In other words, the minimum width of the opening in the conductive layer 240 is used as the width D of the opening 290. Alternatively, the width of the opening at the highest position in the conductive layer 240, the width of the opening at the lowest position, the width of the opening at a midpoint between these, or the average value of these three widths may be used as the width D. Here, an example is shown in which the width D of the opening 290 is determined using the width of the opening in the conductive layer 240, but the method for determining the width D is not particularly limited. For example, the shortest distance between the two side surfaces of the insulating layer 280 on the opening side may be used as the width D. Alternatively, the width of the opening at the highest position in the insulating layer 280, the width of the opening at the lowest position, the width of the opening at a midpoint between these, or the average value of these three widths may be used as the width D of the opening 290.

[0239] The width D of the opening 290 is set depending on the film thickness of each of the oxide semiconductor layer 230, the insulating layer 250, and the conductive layer 260 provided in the opening 290. The width D of the opening 290 is, for example, 5 nm or more, 10 nm or more, or 20 nm or more, and is preferably 100 nm or less, 60 nm or less, 50 nm or less, 40 nm or less, or 30 nm or less. When the opening 290 has a circular shape in a plan view, the width D of the opening 290 corresponds to the diameter of the opening 290, and the channel width W can be calculated as "D × π".

[0240] In this embodiment, an example is shown in which the opening 290 is circular in plan view. By using a circular shape, the processing accuracy during the formation of the opening can be improved, allowing for the formation of openings of minute sizes. However, the present invention is not limited to this. In plan view, the opening 290 can be, for example, a circle or a substantially circular shape such as an ellipse, a polygonal shape such as a triangle, a quadrangle (including a rectangle, a diamond, and a square), a pentagon, or a star-shaped polygon, or a polygonal shape with rounded corners. Note that the circle is not limited to a perfect circle. Furthermore, the polygon may be either a concave polygon (a polygon with at least one interior angle exceeding 180 degrees) or a convex polygon (a polygon with all interior angles less than 180 degrees).

[0241] The channel length of the transistor 200A is the distance between the source region and the drain region. In other words, the channel length of the transistor 200A is determined by the thickness of the insulating layer 280 on the conductive layer 220. Therefore, the channel length of the transistor 200A does not affect the area occupied by the transistor 200A, for example, the area of ​​the transistor 200A in a planar view. In FIG. 4A , the channel length L of the transistor 200A is indicated by a dashed double-headed arrow. Note that the channel length L can be considered as the distance between the edge of the region where the oxide semiconductor layer 230 and the conductive layer 220 contact each other and the edge of the region where the oxide semiconductor layer 230 and the conductive layer 240 contact each other in a cross-sectional view. In this case, the channel length L corresponds to the length of the side surface of the insulating layer 280 on the opening 290 side in a cross-sectional view.

[0242] The channel length of the transistor 200A can be set by the film thickness of the insulating layer 280. Therefore, the channel length of the transistor 200A can be, for example, 500 nm or less, 300 nm or less, 100 nm or less, 60 nm or less, 50 nm or less, 40 nm or less, 30 nm or less, 20 nm or less, or 10 nm or less, and can be 0.1 nm or more, 1 nm or more, or 5 nm or more. Typically, the channel length can be 1 nm or more and 300 nm or less, preferably 5 nm or more and 100 nm or less. This can improve productivity and yield in forming the insulating layer 280, forming the opening 290 in the insulating layer 280, and the like. Furthermore, the on-state current of the transistor 200A can be increased, thereby improving frequency characteristics.

[0243] The channel length L of the transistor 200A is preferably at least shorter than the channel width W of the transistor 200A. The channel length L of the transistor 200A is preferably 0.1 to 0.99 times, more preferably 0.5 to 0.8 times, the channel width W of the transistor 200A. With such a structure, a transistor with good electrical characteristics and high reliability can be realized.

[0244] Since the insulating layer 210 functions as an interlayer film, it is preferable to use a material with a low relative dielectric constant. By using a material with a low relative dielectric constant for the interlayer film, parasitic capacitance occurring between wirings can be reduced.

[0245] The insulating layer 210 preferably has a barrier property against hydrogen. When the insulating layer 210 provided below the oxide semiconductor layer 230 has a barrier property against hydrogen, diffusion of hydrogen from below the transistor 200A to the oxide semiconductor layer 230 can be suppressed.

[0246] The insulating layer 210 preferably has a function of capturing or fixing hydrogen. When the insulating layer 210 has a function of capturing or fixing hydrogen, hydrogen in the oxide semiconductor layer 230 diffuses into the insulating layer 210 through the conductive layer 220, and the hydrogen can be captured or fixed. Therefore, the hydrogen concentration in the oxide semiconductor layer 230 can be reduced.

[0247] The concentration of impurities such as hydrogen or water in the insulating layer 210 is preferably reduced, which can prevent impurities such as hydrogen or water from entering the channel formation region of the oxide semiconductor layer 230.

[0248] 4A shows an example in which the insulating layer 210 has a single-layer structure. The insulating layer 210 can have a stacked structure of two or more layers. For example, the insulating layer 210 can have a two-layer structure of a first insulating layer and a second insulating layer on the first insulating layer. In this case, for example, it is preferable that the first insulating layer has a barrier property against hydrogen, and the second insulating layer has a function of capturing or fixing hydrogen. Specifically, it is preferable to use silicon nitride as the first insulating layer and aluminum oxide, hafnium oxide, hafnium zirconium oxide, or hafnium silicate as the second insulating layer.

[0249] 5A , an oxide layer 227 can be provided below an oxide semiconductor layer 230. The oxide layer 227 corresponds to the oxide layer 27 described in Embodiment 1. Therefore, the structure, material, and the like of the oxide layer 227 can be referred to the structure, material, and the like of the oxide layer 27 described in Embodiment 1.

[0250] FIG. 4A illustrates an example in which the oxide semiconductor layer 230 has a single-layer structure. Note that the oxide semiconductor layer 230 can have a stacked structure of two or more layers. As illustrated in FIG. 5B , the oxide semiconductor layer 230 can have a two-layer structure including an oxide semiconductor layer 230_1 and an oxide semiconductor layer 230_2 over the oxide semiconductor layer 230_1. The oxide semiconductor layer 230_1 and the oxide semiconductor layer 230_2 correspond to the oxide semiconductor layer 30a and the oxide semiconductor layer 30b, respectively, described in Embodiment 1. Therefore, the structures, materials, and the like of the oxide semiconductor layer 30a and the oxide semiconductor layer 30b described in Embodiment 1 can be referred to for the structures, materials, and the like of the oxide semiconductor layer 30a and the oxide semiconductor layer 30b.

[0251] 4A shows an example in which the insulating layer 250 has a single-layer structure. Note that the insulating layer 250 can have a stacked structure of two or more layers. In this case, the insulating layer 250 is preferably formed using two or more types of films. By using two or more types of films as the insulating layer 250, the insulating layer 250 can have multiple functions. Examples of the functions of the insulating layer 250 include a function of extracting excess oxygen from the oxide semiconductor layer 230, a function of extracting hydrogen from the oxide semiconductor layer 230, and a function of suppressing diffusion of hydrogen into the oxide semiconductor layer 230.

[0252] 6A to 6D are enlarged views of the insulating layer 250 and its vicinity, which are also enlarged views of the region P surrounded by the dashed line in FIG. 4A.

[0253] 6A illustrates an example in which the insulating layer 250 has a three-layer structure including an insulating layer 250_1, an insulating layer 250_2 over the insulating layer 250_1, and an insulating layer 250_3 over the insulating layer 250_2. In this case, the insulating layer 250_1 is in contact with the oxide semiconductor layer 230.

[0254] The insulating layer 250_1 can be formed using a material that can be used for the second insulating layer described in Embodiment 1. For example, the insulating layer 250_1 preferably has a function of capturing or fixing oxygen. With such a structure, an excess amount of oxygen in the oxide semiconductor layer 230 can be reduced. Furthermore, an insulating layer that has a function of capturing or fixing oxygen might also have a function of capturing or fixing hydrogen, which might reduce the hydrogen concentration in the oxide semiconductor layer 230. Therefore, a highly reliable transistor can be provided.

[0255] Furthermore, it is preferable to use a high-k (high-dielectric-constant) material for the insulating layer 250_1. An example of a high-k material is an oxide containing one or both of aluminum and hafnium. Using a high-k material for the insulating layer 250_1 makes it possible to reduce the gate potential applied during transistor operation while maintaining the physical thickness of the gate insulator. Furthermore, it makes it possible to reduce the equivalent oxide thickness (EOT) of the insulator functioning as the gate insulator.

[0256] From the above, it is preferable to use an oxide containing one or both of aluminum and hafnium as the insulating layer 250_1, and it is more preferable to use an oxide having an amorphous structure and containing one or both of aluminum and hafnium. Aluminum oxide having an amorphous structure is more preferable because an amorphous film of aluminum oxide can be formed relatively easily by using an ALD method. In this embodiment, aluminum oxide is used as the insulating layer 250_1. Aluminum oxide has a function of capturing or fixing oxygen and hydrogen, and is therefore suitable for the insulating layer 250_1.

[0257] For example, the insulating layer 250_2 preferably includes a material with a low dielectric constant, such as a silicon oxide film or a silicon oxynitride film.

[0258] Silicon oxide or silicon nitride is an insulating material with high dielectric strength. This can reduce the leakage current of a transistor. Furthermore, a silicon oxide film or a silicon oxynitride film is also a film with high hydrogen permeability. Therefore, as shown in FIG. 6B , the insulating layer 250 may have a three-layer structure including an insulating layer 250_2, an insulating layer 250_1 on the insulating layer 250_2, and an insulating layer 250_3 on the insulating layer 250_1. With this structure, hydrogen in the oxide semiconductor layer 230 can diffuse into the insulating layer 250_1 through the insulating layer 250_2 and be captured or fixed. Therefore, the hydrogen concentration in the oxide semiconductor layer 230 can be reduced.

[0259] The insulating layer 250_3 preferably has a barrier property against hydrogen. With such a structure, diffusion of hydrogen into the oxide semiconductor layer 230 can be suppressed. Furthermore, the insulating layer 250_3 preferably has a barrier property against oxygen. The insulating layer 250_3 is provided between the channel formation region of the oxide semiconductor layer 230 and the conductive layer 260. With such a structure, oxygen contained in the channel formation region of the oxide semiconductor layer 230 can be prevented from diffusing into the conductive layer 260 and forming oxygen vacancies in the channel formation region of the oxide semiconductor layer 230. Furthermore, oxygen contained in the oxide semiconductor layer 230 can be prevented from diffusing into the conductive layer 260 and oxidizing the conductive layer 260. The insulating layer 250_3 is preferably at least less permeable to oxygen than the insulating layer 250_2. Furthermore, the insulating layer 250_3 preferably has a function of suppressing diffusion of hydrogen. This can prevent impurities such as hydrogen contained in the conductive layer 260 from diffusing into the oxide semiconductor layer 230. For example, silicon nitride is preferably used as the insulating layer 250_3.

[0260] 6C , a structure in which an insulating layer 250_4 is provided over the insulating layer 250_2 may be used. The insulating layer 250_4 can be formed using an insulating material that can be used for the insulating layer 250_1. For example, the insulating layer 250_4 preferably has a function of capturing or fixing hydrogen. By providing the insulating layer 250_4 between the insulating layer 250_3 and the insulating layer 250_2, hydrogen contained in the insulating layer 250_2 and the like can be more effectively captured or fixed.

[0261] Specifically, the insulating layer 250 preferably has a four-layer structure in which an aluminum oxide film, a silicon oxide film, a hafnium oxide film, and a silicon nitride film are stacked in this order from the oxide semiconductor layer 230 side. With such a structure, hydrogen in the oxide semiconductor layer 230 can diffuse to the insulating layer 250_1 or the insulating layer 250_4 and be captured or fixed. Therefore, the hydrogen concentration in the oxide semiconductor layer 230 can be reduced.

[0262] The insulating layer 250 is preferably a thin film. For example, the subthreshold swing value (also referred to as S value) can be reduced by setting the thickness of the insulating layer 250 to 1 nm or more and 20 nm or less, preferably 3 nm or more and 10 nm or less. Note that the S value refers to the amount of change in gate voltage when the drain current is changed by one order of magnitude with the drain voltage held constant in the subthreshold region.

[0263] The thickness of each layer constituting the insulating layer 250 is preferably 0.1 nm to 10 nm, more preferably 0.1 nm to 5 nm, more preferably 0.5 nm to 5 nm, more preferably 1 nm to less than 5 nm, and even more preferably 1 nm to 3 nm. Note that it is sufficient that each layer constituting the insulating layer 250 has a region with the above-mentioned thickness in at least a portion thereof.

[0264] Typically, the thicknesses of the insulating layer 250_1, the insulating layer 250_2, the insulating layer 250_4, and the insulating layer 250_3 are 1 nm, 2 nm, 2 nm, and 1 nm, respectively. With such a structure, the transistor can have favorable electrical characteristics even when miniaturized or highly integrated.

[0265] Note that the insulating layer 250 having a four-layer structure may not include the insulating layer 250_3 (see FIG. 6D ). For example, an insulating layer having a function of capturing or fixing oxygen can be used as the insulating layer 250_1, an insulating layer containing a material with a low dielectric constant can be used as the insulating layer 250_2, and an insulating layer having a function of capturing or fixing hydrogen can be used as the insulating layer 250_4. Specifically, the insulating layer 250 can have a three-layer structure in which an aluminum oxide film, a silicon oxide film, and a hafnium oxide film are stacked in this order from the oxide semiconductor layer 230 side.

[0266] In order to thin the insulating layers 250_1 to 250_4 as described above, the insulating layers 250_1 to 250_4 are preferably deposited by an ALD method. In addition, in order to form the insulating layers 250_1 to 250_4 in the opening 290 with good coverage, the insulating layers 250_1 to 250_4 are preferably deposited by an ALD method.

[0267] It is preferable to use the ALD process two or more times in forming the insulating layer 250 having a stacked structure of multiple insulating films. For example, it is preferable that two or more of the multiple insulating films included in the insulating layer 250 are formed using the ALD process. By forming at least two or more types of insulating films using the ALD process, it is possible to improve the coverage and film thickness uniformity of the insulating layer 250. Furthermore, for example, it is possible to increase productivity by successively forming two or more types of insulating films using the ALD process.

[0268] Although the above description has been given of a structure in which the insulating layer 250 has a three-layer structure of insulating layers 250_1 to 250_3 or a four-layer structure of insulating layers 250_1 to 250_4, the present invention is not limited to this. The insulating layer 250 can have a structure including at least one of the insulating layers 250_1 to 250_4. By forming the insulating layer 250 using one, two, or three of the insulating layers 250_1 to 250_4, the manufacturing process of the semiconductor device can be simplified and productivity can be improved.

[0269] Since the insulating layer 280 functions as an interlayer film, it is preferable to use a material with a low dielectric constant. By using a material with a low dielectric constant for the interlayer film, parasitic capacitance generated between wirings can be reduced. For example, silicon oxide or silicon oxynitride can be used as the insulating layer 280.

[0270] The concentration of impurities such as hydrogen or water in the insulating layer 280 is preferably reduced. This can prevent impurities such as hydrogen or water from entering the channel formation region of the oxide semiconductor layer 230.

[0271] FIG. 4A illustrates an example in which the insulating layer 280 has a single-layer structure. The insulating layer 280 can have a stacked structure of two or more layers. For example, as shown in FIG. 7A , the insulating layer 280 can have a three-layer structure including an insulating layer 280_1, an insulating layer 280_2 on the insulating layer 280_1, and an insulating layer 280_3 on the insulating layer 280_2. In this case, it is preferable to use a material with a low dielectric constant as the insulating layer 280_2, and to use oxygen barrier insulating layers as the insulating layers 280_1 and 280_3. This can prevent the conductive layer 220 and the conductive layer 240 from being oxidized and thus prevent high resistance. In the configuration shown in FIG. 7A , the insulating layer 280_2 corresponds to the insulating layer 20 described in embodiment 1.

[0272] For example, it is preferable to use silicon nitride or aluminum oxide for the insulating layer 280_1 and the insulating layer 280_3, and to use silicon oxide for the insulating layer 280_2. Note that each of the insulating layer 280_1 and the insulating layer 280_3 may have a stacked structure of two or more layers.

[0273] The conductive layer 220 and the conductive layer 240 are conductive layers in contact with the oxide semiconductor layer 230, and therefore, it is preferable to use a conductive material that is resistant to oxidation, a conductive material that maintains low electrical resistance even when oxidized, a metal oxide having conductivity (also referred to as an oxide conductor), or a conductive material that has a function of suppressing oxygen diffusion, for each of them. Examples of the conductive material include a conductive material containing nitrogen and a conductive material containing oxygen. This can suppress a decrease in the conductivity of the conductive layer 220 and the conductive layer 240.

[0274] By using a conductive material containing oxygen for the conductive layer 220, the conductive layer 220 can maintain its conductivity even if it absorbs oxygen. Similarly, by using a conductive material containing oxygen for the conductive layer 240, the conductive layer 240 can maintain its conductivity even if it absorbs oxygen. Furthermore, even when an insulator containing oxygen such as hafnium oxide is used for the insulating layer 210, the conductive layer 220 is preferable because it can maintain its conductivity. For each of the conductive layer 220 and the conductive layer 240, it is preferable to use, for example, ITO, ITSO, In—Zn oxide, or the like.

[0275] When the conductive layer 220 and the conductive layer 240 each have a stacked structure, by using a conductive material containing oxygen for a layer in the stacked structure that has the largest contact area with the oxide semiconductor layer 230, the contact resistance between the conductive layer 220 and the oxide semiconductor layer 230 and between the conductive layer 240 and the oxide semiconductor layer 230 can be reduced.

[0276] 7A shows an example in which the conductive layer 220_1 has a two-layer structure including a conductive layer 220_11 and a conductive layer 220_12 over the conductive layer 220_11. In other words, the conductive layer 220 shown in FIG. 7A has a three-layer structure including a conductive layer 220_11, a conductive layer 220_12 over the conductive layer 220_11, and a conductive layer 220_2 over the conductive layer 220_12. In this case, for example, it is preferable to use a conductive material that is difficult to oxidize or a conductive material that has a function of suppressing oxygen diffusion as the conductive layer 220_11, a material with high conductivity as the conductive layer 220_12, and a conductive material containing oxygen (more preferably an oxide conductor) as the conductive layer 220_2. Specifically, it is preferable to use titanium nitride for the conductive layer 220_11, tungsten for the conductive layer 220_12, and an oxide conductor (e.g., ITO, ITSO, or In—Zn oxide) for the conductive layer 220_2. In this case, the titanium nitride film is in contact with the insulating layer 210, and the oxide conductive film is in contact with the oxide semiconductor layer 230. Furthermore, the oxide conductor is used in the layer closest to the channel formation region of the oxide semiconductor layer 230. Compared to tungsten, the oxide conductor has lower contact resistance with the oxide semiconductor layer 230, so that the current path between the source and drain can be shortened and the on-state current of the transistor 200A can be increased. With such a structure, the conductive layer 220 can maintain conductivity even when in contact with the oxide semiconductor layer 230. Furthermore, when an oxide insulating layer is used for the insulating layer 210, excessive oxidation of the conductive layer 220 by the insulating layer 210 can be suppressed. Furthermore, when a metal material (tungsten here) having higher conductivity than an oxide conductor and titanium nitride is used for the conductive layer 220_12, the conductivity of the conductive layer 220 can be increased.

[0277] 4A has a two-layer structure including a conductive layer 240_1 and a conductive layer 240_2 over the conductive layer 240_1. In this case, for example, it is preferable to use a conductive material containing oxygen for the conductive layer 240_2 and a material having higher conductivity than the conductive layer 240_2 for the conductive layer 240_1. Specifically, it is preferable to use an oxide conductor (e.g., ITO, ITSO, or In—Zn oxide) for the conductive layer 240_2 and tungsten for the conductive layer 240_1. Ruthenium, titanium nitride, tantalum nitride, or the like may also be used for the conductive layer 240_1. By using an oxide conductor for the conductive layer 240_2 that is mainly in contact with the oxide semiconductor layer 230, the contact resistance with the oxide semiconductor layer 230 can be reduced. Furthermore, by using a material having higher conductivity than an oxide conductor for the layers constituting the conductive layer 240, the conductivity of the conductive layer 240 can be increased.

[0278] Note that a conductive material containing oxygen can be used for the conductive layer 240_1, and a material having higher conductivity than that of the conductive layer 240_2 can be used for the conductive layer 240_2. In this case, an oxide conductor is used for the layer of the conductive layer 240 that is closest to the channel formation region of the oxide semiconductor layer 230. Therefore, the current path between the source and the drain can be shortened, and the on-state current of the transistor 200A can be increased.

[0279] 4A has a two-layer structure including a conductive layer 260_1 and a conductive layer 260_2 over the conductive layer 260_1. In this case, for example, it is preferable to use titanium nitride for the conductive layer 260_1 and tungsten for the conductive layer 260_2. Alternatively, it is preferable to use tantalum nitride for the conductive layer 260_1 and copper for the conductive layer 260_2. Such a structure can increase the conductivity of the conductive layer 260.

[0280] The conductive layer 260 may also have a stacked structure of three or more layers, such as a tantalum nitride film, a titanium nitride film on the tantalum nitride film, and a tungsten film on the titanium nitride film.

[0281] 7A , the semiconductor device of one embodiment of the present invention may include an insulating layer 283 over the transistor 200A. Specifically, the insulating layer 283 may be provided over the conductive layer 260 and the insulating layer 250.

[0282] A barrier insulating layer against hydrogen is preferably used for the insulating layer 283. With such a structure, diffusion of hydrogen from above the transistor 200A to the oxide semiconductor layer 230 can be suppressed.

[0283] 4A , both the conductive layer 260_1 and the conductive layer 260_2 are located in the opening 290. Depending on the width of the opening 290 and the thicknesses of the oxide semiconductor layer 230, the insulating layer 250, and the conductive layer 260_1, the conductive layer 260_1 may be provided in the opening 290, and the conductive layer 260_2 may be provided so as to overlap with the opening 290 (see FIG. 7B ).

[0284] 7A shows a configuration in which the side surface of the conductive layer 240 and the side surface of the insulating layer 280 are flush or substantially flush with each other within the opening 290, but the present invention is not limited to this. For example, the side surface of the conductive layer 240 and the side surface of the insulating layer 280 may be discontinuous within the opening 290. Furthermore, the inclination of the side surface of the conductive layer 240 and the inclination of the side surface of the insulating layer 280 within the opening 290 may differ from each other. In this case, part of the side wall of the opening 290 has a tapered shape.

[0285] 8A and 8B show examples in which at least a portion of the sidewall of the opening 290 is tapered. Fig. 8A shows an example in which the side surface of the conductive layer 240 in the opening 290 is tapered, and Fig. 8B shows an example in which the side surface of the conductive layer 240 and the side surface of the insulating layer 280 in the opening 290 are both tapered.

[0286] By tapering the sidewall of the opening 290, the coverage of the oxide semiconductor layer 230, the insulating layer 250, and the like can be improved, and defects such as voids can be reduced. When the sidewall of the opening 290 is tapered, for example, the taper angle (angle θ240) of the side surface of the conductive layer 240 in the opening 290 and the taper angle (angle θ280) of the side surface of the insulating layer 280 in the opening 290 are preferably 45 degrees or more and less than 90 degrees. Specifically, a taper angle of 80 degrees or more and less than 90 degrees is preferable, as described above, because this allows for miniaturization or high integration of the semiconductor device. Furthermore, a taper angle of 45 degrees or more or 50 degrees or more and less than 80 degrees, 75 degrees or less, 70 degrees or less, 65 degrees or less, or 60 degrees or less is preferable, because this improves the coverage of the film formed in the opening 290.

[0287] Furthermore, for example, it is preferable that angle θ240 is smaller than angle θ280. With such a configuration, coverage of the oxide semiconductor layer 230 and the like on the side surface of the conductive layer 240 in the opening 290 is improved, and defects such as voids can be reduced. Furthermore, when the insulating layer 280 has a stacked structure, the inclination of the side surface of each layer in the opening 290 may be different. Similarly, when the conductive layer 240 has a stacked structure, the inclination of the side surface of each layer in the opening 290 may be different.

[0288] 9A , the oxide semiconductor layer 230 may have a different ratio between the film thickness (hereinafter referred to as the first film thickness) of a portion where the top surface of the conductive layer 240 or the conductive layer 220 is to be formed and the film thickness (hereinafter referred to as the second film thickness) of a portion where the sidewall of the opening 290 is to be formed. For example, when a portion of the oxide semiconductor layer 230 is formed by sputtering, the oxide semiconductor layer 230 may have a different ratio between the first film thickness and the second film thickness. For example, as shown in FIG. 9A , the ratio of the second film thickness to the first film thickness may be less than 1, less than 0.8, or less than 0.5. In particular, the closer the angle θ 280 is to 90 degrees, the smaller the ratio of the second film thickness to the first film thickness in the oxide semiconductor layer 230 tends to be.

[0289] 9B , the recess of the conductive layer 220_2 preferably has a curved portion. When the recess has a curved portion, the portions of the oxide semiconductor layer 230, the insulating layer 250, and the like provided on the recess near the recess may also have a curved portion. In other words, the portions may have a curved or concave surface in cross-sectional view. Furthermore, the portions may not have corners (right angles or acute angles) in cross-sectional view. This reduces electric field concentration on the insulating layer 250 near the recess, improves the withstand voltage of the transistor 200A, and suppresses electrostatic breakdown of the transistor 200A. Therefore, the reliability of the semiconductor device can be improved.

[0290] 10A to 24C, examples of transistor configurations that are partially different from the transistor 200A will be described. Note that descriptions of parts that overlap with the above will be omitted, and only the differences will be described in detail. Furthermore, even if components differ in position or shape, if their functions are the same, they may be assigned the same reference numerals and their descriptions may be omitted.

[0291] [Transistor 200B] Fig. 10A is a plan view of a semiconductor device having transistor 200B. Fig. 10B is a cross-sectional view taken along dashed dotted line A1-A2 in Fig. 10A. Fig. 10C is a cross-sectional view taken along dashed dotted line A3-A4 in Fig. 10A. Note that Fig. 3D can be referred to for a cross-sectional view taken along dashed dotted line A5-A6 in Fig. 10B. Fig. 11A shows an enlarged view of Fig. 10B.

[0292] The semiconductor device shown in Figures 10A to 10C includes an insulating layer 210 on a substrate (not shown), a transistor 200B on the insulating layer 210, an insulating layer 280 on the insulating layer 210, an insulating layer 284, an insulating layer 285 on the insulating layer 284, and a conductive layer 265 on the transistor 200B, the insulating layer 284, and the insulating layer 285.

[0293] The semiconductor device shown in FIGS. 10A to 10C differs from the semiconductor device shown in FIGS. 3A to 3D in that it includes a conductive layer 265, an insulating layer 284, and an insulating layer 285.

[0294] The conductive layer 265 functions as a gate wiring. The conductive layer 265 can be formed using a material that can be used for the conductive layer 260. For example, a high-melting-point material that has both heat resistance and conductivity, such as tungsten or molybdenum, can be used for the conductive layer 265. Alternatively, a low-resistance conductive material, such as aluminum or copper, can be used. By using a low-resistance conductive material, wiring resistance can be reduced.

[0295] The transistor 200B includes a conductive layer 220, a conductive layer 240, an oxide semiconductor layer 230, an insulating layer 250, and a conductive layer 260. In the transistor 200B, the stacked structure from the conductive layer 220 to the insulating layer 250 is similar to that of the transistor 200A described above, and therefore detailed description thereof will be omitted.

[0296] 10B and 10C , insulating layer 284 is provided so as to be located on insulating layer 250. Furthermore, insulating layer 284 is provided with openings 270 that reach insulating layer 250 at positions that overlap openings 290.

[0297] The conductive layer 260 is provided to fill the openings 290 and 270. The conductive layer 260 is provided on the insulating layer 250 and is in contact with the insulating layer 250 in the opening 270. The conductive layer 260 has a portion that faces the oxide semiconductor layer 230 in the opening 290 with the insulating layer 250 interposed therebetween, and a portion that is located in the opening 270.

[0298] 10B and 10C show an example in which both the conductive layer 260_1 and the conductive layer 260_2 are provided in the opening 290. Note that when the width of the opening 290 and the width of the opening 270 are small, only the conductive layer 260_1 may be provided in the opening 290, and the conductive layer 260_1 and the conductive layer 260_2 may be provided in the opening 270. Alternatively, only the conductive layer 260_1 may be provided in the opening 270.

[0299] The portion of the conductive layer 265 that does not overlap with the opening 290 is mainly located on the insulating layer 285. Therefore, the conductive layer 265 mainly overlaps with the conductive layer 240 via the insulating layers 284 and 285. This makes it possible to increase the physical distance between the conductive layer 265 and the conductive layer 240, and to reduce the parasitic capacitance that occurs between the conductive layer 265 and the conductive layer 240. Note that the conductive layer 240 and the conductive layer 265 may have an overlapping portion without the insulating layer 285 being therebetween.

[0300] 11A shows an example in which the width of the opening 270 is smaller than the width D of the opening 290. The smaller the width of the opening 270, the greater the physical distance between the conductive layer 240 and the conductive layer 260 can be, and the smaller the parasitic capacitance that occurs between the conductive layer 240 and the conductive layer 260 can be, which is preferable. For example, the width of the opening 270 is preferably the same as or smaller than the width of the opening 290.

[0301] The conductive layer 265 is provided over the conductive layer 260 and is in contact with the top surface of the conductive layer 260. It can also be said that the conductive layer 260 and the conductive layer 265 are connected to each other. The conductive layer 265 may be considered a component of the transistor 200B. The height of the top surface of the conductive layer 260 and the height of the top surface of the insulating layer 285 are the same or approximately the same.

[0302] The transistor 200B has a structure in which parasitic capacitance generated between the other of the source electrode and the drain electrode and the gate wiring is reduced, thereby improving the frequency characteristics of a circuit including the transistor.

[0303] In this embodiment, an example in which the opening 270 is circular in plan view has been shown, but the present invention is not limited to this. Shapes that can be applied to the opening 270 are the same as the shapes that can be applied to the opening 290 described above.

[0304] The width of the opening 270 may vary in the depth direction. In particular, the width of the opening 270 used here is the maximum width of the opening 270 provided in the insulating layer 284 in a cross-sectional view.

[0305] The insulating layer 284 preferably has a function of capturing or fixing hydrogen. With such a structure, diffusion of hydrogen from above the insulating layer 284 to the oxide semiconductor layer 230 can be suppressed, and further, hydrogen contained in the oxide semiconductor layer 230 can be captured or fixed. Therefore, the hydrogen concentration in the oxide semiconductor layer 230 can be reduced. The insulating layer 284 can be formed using aluminum oxide, hafnium oxide, hafnium zirconium oxide, hafnium silicate, or the like.

[0306] The insulating layer 284 can also serve as a barrier insulating layer against hydrogen, which can suppress diffusion of hydrogen from above the insulating layer 284 to the oxide semiconductor layer 230. Silicon nitride and silicon nitride oxide are suitable for the insulating layer 284 because they are less permeable to oxygen and hydrogen, respectively.

[0307] When the insulating layer 284 includes a silicon nitride film, the silicon nitride film is preferably formed by a sputtering method. The sputtering method does not require the use of hydrogen-containing molecules in the film formation gas, and therefore can reduce the hydrogen concentration in the insulating layer 284. Furthermore, by forming the insulating layer 284 by a sputtering method, a silicon nitride film with high density can be formed.

[0308] Alternatively, the insulating layer 284 may have a stacked structure of an insulating layer having a function of capturing or fixing hydrogen and a barrier insulating layer against hydrogen. For example, the insulating layer 284 may have a stacked structure of an aluminum oxide film and a silicon nitride film over the aluminum oxide film.

[0309] The insulating layer 285 functions as an interlayer film, and therefore is preferably made of the above-mentioned material having a low relative dielectric constant. For example, the insulating layer 285 preferably includes a silicon oxide film.

[0310] Note that a structure similar to that of the transistor 200A can also be applied to the transistor 200B. An example in which the structure shown in FIG. 7A is applied to the semiconductor device shown in FIG. 11A is shown in FIG. 11B. In FIG. 11B, the insulating layer 283 is provided over the insulating layer 285 and the conductive layer 265.

[0311] [Transistor 200C] Fig. 12A is a plan view of a semiconductor device including transistor 200C. Fig. 12B is a cross-sectional view taken along dashed dotted line A1-A2 in Fig. 12A. Fig. 12C is a cross-sectional view taken along dashed dotted line A3-A4 in Fig. 12A. Fig. 12D is a cross-sectional view taken along dashed dotted line A5-A6 in Fig. 12B.

[0312] 12B is shown in FIG. 13A, and an enlarged view of FIG. 12D is shown in FIG. 13B. Also, FIGS. 14A and 14B are cross-sectional views taken along dashed line A1-A2 in FIG. 12A. Each of FIGS. 14A and 14B corresponds to an example of an enlarged view of FIG. 12B, and shows an example of the configuration of each layer in more detail.

[0313] The semiconductor device shown in FIGS. 12A to 12D includes an insulating layer 210 on a substrate (not shown), a transistor 200C on the insulating layer 210, and an insulating layer 280 on the insulating layer 210.

[0314] The transistor 200C includes a conductive layer 220 , a conductive layer 240 , an insulating layer 225 , an oxide semiconductor layer 230 , an insulating layer 250 , and a conductive layer 260 .

[0315] The transistor 200C shown in FIGS. 12A to 12D differs from the transistor 200A shown in FIGS. 3A to 3D in that it includes an insulating layer 225.

[0316] The oxide semiconductor layer 230, the insulating layer 225, the insulating layer 250, and the conductive layer 260 included in the transistor 200C correspond to the oxide semiconductor layer 30, the insulating layer 20, the insulating layer 50, and the conductive layer 60, respectively, described in Embodiment 1. Therefore, the structures, materials, and the like of the oxide semiconductor layer 30, the insulating layer 20, the insulating layer 50, and the conductive layer 60 described in Embodiment 1 can be referred to for the structures, materials, and the like of the oxide semiconductor layer 230, the insulating layer 225, the insulating layer 250, and the conductive layer 260.

[0317] As shown in FIG. 12D, the transistor 200C has a configuration in which an insulating layer 225 is disposed between the insulating layer 280 and the oxide semiconductor layer 230 in a plan view.

[0318] The insulating layer 225 is preferably formed by a CVD method or an ALD method, and more preferably by an ALD method, since it is a layer provided in the opening 290. This allows the insulating layer 225 to be provided with good coverage.

[0319] As shown in FIG. 12B and other figures, the conductive layer 220_2 has a first recess and a second recess located outside the first recess. The first recess is deeper than the second recess. In other words, the bottom surface of the first recess is located lower (closer to the insulating layer 210) than the bottom surface of the second recess. When forming the opening 290, the second recess is provided in the conductive layer 220_2, and then, when processing the insulating layer 225, the first recess is provided in the conductive layer 220_2. Therefore, in FIG. 12B and other figures, the side surface of the second recess and the side surface of the insulating layer 280 in the opening 290 coincide or approximately coincide, and the side surface of the first recess and the surface of the insulating layer 225 facing the oxide semiconductor layer 230 coincide or approximately coincide. Hereinafter, the first recess and the second recess may be collectively referred to as recesses.

[0320] 12B and other figures, the insulating layer 225 is in contact with the bottom surface and side surfaces of the second recessed portion of the conductive layer 220, and is in contact with the side surfaces of the insulating layer 280 and the conductive layer 240 within the opening 290. The oxide semiconductor layer 230 is in contact with the bottom surface and side surfaces of the first recessed portion of the conductive layer 220, the insulating layer 225, and the top surface of the conductive layer 240_2. The insulating layer 250 is located inside the oxide semiconductor layer 230 within the opening 290, and the conductive layer 260 is located inside the insulating layer 250 within the opening 290.

[0321] 13A , the shortest distance Tc from the top surface of the insulating layer 210 to the top surface of the conductive layer 220_2 that is in contact with the insulating layer 280 is preferably longer than the shortest distance Ta from the top surface of the insulating layer 210 to the bottom surface of the insulating layer 250. This increases the area where the side surface of the conductive layer 220_2 is in contact with the oxide semiconductor layer 230, thereby reducing the contact resistance between the conductive layer 220_2 and the oxide semiconductor layer 230. Therefore, a decrease in the on-state current of the transistor 200C due to the contact resistance between the conductive layer 220_2 and the oxide semiconductor layer 230 can be suppressed. Note that the shortest distance Ta can be determined based on the bottom surface of the insulating layer 250 in the opening 290.

[0322] 13A , the shortest distance Tc is preferably equal to or greater than the shortest distance Tb from the top surface of the insulating layer 210 to the bottom surface of the conductive layer 260, and more preferably longer than the shortest distance Tb. This makes it easier to apply a gate electric field to the channel formation region of the oxide semiconductor layer 230, thereby improving the electrical characteristics of the transistor 200C. Furthermore, since the gate electric field is also easier to apply to a region of the oxide semiconductor layer 230 in contact with the conductive layer 220_2, the on-state current of the transistor 200C can be increased. Furthermore, regardless of whether the conductive layer 220 or the conductive layer 240 is used as the drain electrode, the electrical characteristics of the transistor 200C can be improved. Note that the shortest distance Tb can be determined based on the bottom surface of the conductive layer 260 in the opening 290.

[0323] Here, as shown in FIG. 13A, the width (film thickness) of the insulating layer 225 is set to width T ＳＷ Width T ＳＷ It is preferable that the width T ＳＷ By reducing the width T ＳＷ By increasing the width T ＳＷ is, for example, preferably 1 nm or more and 20 nm or less, more preferably 2 nm or more and 15 nm or less, and even more preferably 3 nm or more and 10 nm or less.

[0324] 13B also shows the channel width W of the transistor 200C. When the opening 290 is circular in plan view, the width D of the opening 290 corresponds to the diameter of the opening 290, and the channel width W is "(D-2×T ＳＷ ) × π”.

[0325] The channel length of transistor 200C can be considered to be the distance between the source region and the drain region. In other words, the channel length of transistor 200C can be said to be determined by the height of insulating layer 225. Furthermore, the channel length of transistor 200C can be said to be determined by the depth of the recess (specifically, the second recess) in conductive layer 220, the thickness of insulating layer 280 on conductive layer 220, and the thickness of conductive layer 240. When the channel length of transistor 200C is considered to be the distance between the source region and the drain region, the channel length of transistor 200C can be considered to be the length L shown in FIG. 13A .

[0326] 13A illustrates a configuration in which the conductive layer 220_2 has a first recess and a second recess, but the present invention is not limited to this. For example, as illustrated in FIG. 14A , the transistor 200C may have a configuration in which only the first recess is provided in the conductive layer 220_2.

[0327] A recess can be formed in the conductive layer 220_2 in one or both of the steps of forming the opening 290 and forming the insulating layer 225. The transistor 200C illustrated in Figure 13A illustrates an example in which a recess is formed in the conductive layer 220_2 in both steps, whereas the transistor 200C illustrated in Figure 14A illustrates an example in which a recess is not formed in the conductive layer 220_2 in the step of forming the opening 290, but is formed in the step of forming the insulating layer 225.

[0328] 14A , the insulating layer 225 is in contact with the side surface of the insulating layer 280, the side surface of the conductive layer 240, and the top surface of the conductive layer 220_2 in the opening 290. The oxide semiconductor layer 230 is in contact with the bottom surface and side surface of the recess of the conductive layer 220_2.

[0329] When a recess is formed in the conductive layer 220_2 in at least one of the steps of forming the opening 290 and forming the insulating layer 225, the height of the bottom surface of the conductive layer 260 in the opening 290 can be lowered, making it easier for a gate electric field to be applied to the channel formation region of the oxide semiconductor layer 230, thereby improving the electrical characteristics of the transistor 200C.

[0330] When a recess is formed in the conductive layer 220_2 in the process of forming the insulating layer 225, the oxide semiconductor layer 230 can be in contact with the bottom and side surfaces of the recess of the conductive layer 220_2, the area of ​​contact between the oxide semiconductor layer 230 and the conductive layer 220_2 is increased, and the contact resistance between the oxide semiconductor layer 230 and the conductive layer 220 can be reduced, which is preferable.

[0331] For example, as shown in FIG. 14B, a transistor 200C may have a structure in which the insulating layer 225 does not cover the side surfaces of the conductive layer 240_2.

[0332] 14B is in contact with the bottom and side surfaces of the recess of the conductive layer 220, and is in contact with the side surface of the insulating layer 280 within the opening 290. The insulating layer 225 is in contact with part of the side surface of the conductive layer 240_1, but is not in contact with the side surface of the conductive layer 240_2. The insulating layer 225 may be in contact with one or more of the side surface of the insulating layer 280, the side surface of the conductive layer 240_1, and the side surface of the conductive layer 240_2 within the opening 290, or may cover part or all of each side surface.

[0333] When at least a part of the side surface of the conductive layer 240_2 is not covered with the insulating layer 225, the part is in contact with the oxide semiconductor layer 230. This increases the area where the oxide semiconductor layer 230 and the conductive layer 240 are in contact, and the contact resistance between the oxide semiconductor layer 230 and the conductive layer 240 can be reduced. Similarly, when the insulating layer 225 does not cover the side surface of the conductive layer 240_2 and also does not cover at least a part of the side surface of the conductive layer 240_1, the part is in contact with the oxide semiconductor layer 230. This increases the area where the oxide semiconductor layer 230 and the conductive layer 240 are in contact, and the contact resistance between the oxide semiconductor layer 230 and the conductive layer 240 can be reduced.

[0334] 13A shows an example in which the insulating layer 225 has a single-layer structure. Note that the insulating layer 225 can have a stacked structure of two or more layers. For example, as shown in FIG. 15, the insulating layer 225 can have a two-layer structure of an insulating layer 225_1 and an insulating layer 225_2.

[0335] 15 illustrates an example in which the insulating layer 225 has a two-layer structure including an insulating layer 225_1 in contact with the insulating layer 280 and an insulating layer 225_2 between the insulating layer 225_1 and the oxide semiconductor layer 230. The insulating layer 225 illustrated in FIG. 15 can be said to have a two-layer structure including the insulating layer 225_1 and the insulating layer 225_2 over the insulating layer 225_1.

[0336] The insulating layer 225_1 provided in contact with the side surface of the insulating layer 280 in the opening 290 can be a barrier insulating layer against hydrogen, and the insulating layer 225_2 provided in contact with the oxide semiconductor layer 230 can be an insulating layer having a region containing excess oxygen. With such a structure, one or both of oxygen vacancies and hydrogen in the oxide semiconductor layer 230 can be reduced. Therefore, the electrical characteristics of the transistor can be improved, and the reliability of the transistor can be improved. For example, it is preferable to use silicon nitride for the insulating layer 225_1 and silicon oxide or silicon oxynitride for the insulating layer 225_2. The thicknesses of the insulating layers 225_1 and 225_2 are 2 nm and 2 nm, respectively.

[0337] As described above, by surrounding the oxide semiconductor layer 230 with a barrier insulating layer against hydrogen in a ring shape and providing an insulating layer having a region containing excess oxygen near the oxide semiconductor layer 230, it is possible to reduce one or both of oxygen vacancies and impurities in the oxide semiconductor layer 230. Therefore, the electrical characteristics of the transistor can be improved, and the reliability of the transistor can be improved.

[0338] Note that the insulating layer 225_1 can be made of an insulating material described in [Insulating Layer] in embodiment 1, and the insulating layer 225_2 can be made of a material applicable to the insulating layer 20 described in embodiment 1.

[0339] Here, another example of the configuration of the insulating layer 225 shown in FIG. 15 is shown in FIGS. 16A and 16B.

[0340] In the transistor 200C shown in Figure 16A, an example is shown in which the insulating layer 225_1 is provided in contact with a portion of the bottom surface and the side surface of the recess formed by the conductive layer 220_2, and the insulating layer 225_2 is located inside the insulating layer 225_1 in the opening 290 and is provided in contact with another portion of the bottom of the recess formed by the conductive layer 220_2.

[0341] 16B , the conductive layer 220_2 has a first recess, a second recess located outside the first recess, and a third recess located outside the second recess. The first recess is deeper than the second recess, and the second recess is deeper than the third recess. The third recess is provided in the conductive layer 220_2 when forming the opening 290. Then, the second recess is provided in the conductive layer 220_2 when processing the insulating layer 225_1. Then, the first recess is provided in the conductive layer 220_2 when processing the insulating layer 225_2. Therefore, in FIG. 16B, the side surface of the third recess and the side surface of the insulating layer 280 in the opening 290 are aligned or approximately aligned, the side surface of the second recess and the surface of the insulating layer 225_1 facing the insulating layer 225_2 are aligned or approximately aligned, and the side surface of the first recess and the surface of the insulating layer 225_2 facing the oxide semiconductor layer 230 are aligned or approximately aligned.

[0342] In the transistor 200C shown in Figure 16B, the insulating layer 225_1 is provided in contact with the bottom and side surfaces of the third recess of the conductive layer 220_2, and the insulating layer 225_2 is provided in contact with the bottom and side surfaces of the second recess of the conductive layer 220_2.

[0343] 16A or 16B can be formed by providing the insulating layer 225_1 on the sidewall of the opening 290 and then forming and processing an insulating film to be the insulating layer 225_2. Compared to the transistor 200C shown in FIG. 15, the region where the insulating layer 225_1 is in contact with the oxide semiconductor layer 230 is reduced, and a structure in which the insulating layer 225_2 is in contact with the oxide semiconductor layer 230 can be realized.

[0344] Note that the same structure as at least one of the transistors 200A and 200B can also be applied to the transistor 200C. Fig. 17A shows an example in which the structure shown in Fig. 7A is applied to the semiconductor device shown in Fig. 13A. Fig. 17B shows an example in which the structure shown in Fig. 7A is applied to the semiconductor device shown in Fig. 15.

[0345] [Transistor 200D] Fig. 18A is a plan view of a semiconductor device having transistor 200D. Fig. 18B is a cross-sectional view taken along dashed dotted line A1-A2 in Fig. 18A. Fig. 18C is a cross-sectional view taken along dashed dotted line A3-A4 in Fig. 18A. Fig. 18D is a cross-sectional view taken along dashed dotted line A5-A6 in Fig. 18B. Fig. 19A shows an enlarged view of Fig. 18B.

[0346] The semiconductor device shown in Figures 18A to 18D has an insulating layer 210 on a substrate (not shown), a transistor 200D on the insulating layer 210, an insulating layer 280 on the insulating layer 210, and an insulating layer 281 on the insulating layer 280.

[0347] The transistor 200D includes a conductive layer 220 , a conductive layer 255 , a conductive layer 240 , an insulating layer 225 , an oxide semiconductor layer 230 , an insulating layer 250 , and a conductive layer 260 .

[0348] 18A to 18D differs from the semiconductor device shown in Figures 3A to 3D mainly in that it includes an insulating layer 225, a conductive layer 255, and an insulating layer 281. Furthermore, the transistor 200D shown in Figures 18A to 18D differs from the transistor 200C shown in Figures 12A to 12D mainly in that it includes the conductive layer 255 and the insulating layer 281.

[0349] The conductive layer 255 is located over the insulating layer 280, and the insulating layer 281 is located over the conductive layer 255 and the insulating layer 280. In addition, the conductive layer 240_1 is located over the insulating layer 281.

[0350] As shown in FIG. 19A, an opening 290 reaching the conductive layer 220 is provided in the insulating layer 280 , the conductive layer 255 , the insulating layer 281 , and the conductive layer 240 .

[0351] In transistor 200D, the oxide semiconductor layer 230 functions as a semiconductor layer, the conductive layer 260 functions as a first gate electrode, the insulating layer 250 functions as a first gate insulating layer, the conductive layer 220 functions as one of a source electrode and a drain electrode, the conductive layer 240 functions as the other of the source electrode and the drain electrode, the conductive layer 255 functions as a second gate electrode, and the insulating layer 225 functions as a second gate insulating layer.

[0352] The oxide semiconductor layer 230, the insulating layer 225, the insulating layer 250, and the conductive layer 260 included in the transistor 200D correspond to the oxide semiconductor layer 30, the insulating layer 20, the insulating layer 50, and the conductive layer 60, respectively, described in Embodiment 1. Therefore, for the structures, materials, and the like of the oxide semiconductor layer 230, the insulating layer 225, the insulating layer 250, and the conductive layer 260, the structures, materials, and the like of the oxide semiconductor layer 30, the insulating layer 20, the insulating layer 50, and the conductive layer 60 described in Embodiment 1 can be referred to.

[0353] Alternatively, the oxide semiconductor layer 230, the insulating layer 250, the insulating layer 225, and the conductive layer 255 included in the transistor 200D may correspond to the oxide semiconductor layer 30, the insulating layer 20, the insulating layer 50, and the conductive layer 60, respectively, described in Embodiment 1. In this case, the structures, materials, and the like of the oxide semiconductor layer 30, the insulating layer 20, the insulating layer 50, and the conductive layer 60, described in Embodiment 1, can be referred to for the structures, materials, and the like of the oxide semiconductor layer 230, the insulating layer 250, the insulating layer 225, and the conductive layer 255.

[0354] The oxide semiconductor layer 230 has a region that overlaps with the conductive layer 255 with the insulating layer 225 interposed therebetween and with the conductive layer 260 with the insulating layer 250 interposed therebetween. At least part of the region functions as a channel formation region of the transistor 200D.

[0355] Since the transistor 200D includes a conductive layer that functions as a backgate electrode, the threshold voltage of the transistor 200D can be controlled by the potential applied to the conductive layer. Therefore, by controlling the threshold voltage, a normally-off transistor can be easily realized.

[0356] In the transistor 200D, one of the conductive layer 255 and the conductive layer 260 can be used as a gate electrode and the other can be used as a back gate electrode. The transistor 200D may have a particularly preferable structure in which the conductive layer 260 is used as a gate electrode and the conductive layer 255 is used as a back gate electrode. By using the conductive layer 260, which has a wider region facing the oxide semiconductor layer 230 than the conductive layer 255, as the gate electrode, a gate electric field can be applied to the oxide semiconductor layer 230 more efficiently, which may improve the electrical characteristics of the transistor. When the conductive layer 260 functions as a gate electrode and the conductive layer 255 functions as a back gate electrode, the insulating layer 250 functions as a gate insulating layer and the insulating layer 225 functions as a back gate insulating layer.

[0357] The conductive layer 255 can be made of a conductive material that can be used for the conductive layer 260 .

[0358] The insulating layer 281 functions as an interlayer film. The insulating layer 281 can be formed using an insulating material that can be used for the insulating layer 280.

[0359] Note that the same structure as at least one of the transistors 200A to 200C can also be applied to the transistor 200D. An example in which the structure shown in FIG. 7A is applied to the semiconductor device shown in FIG. 19A is shown in FIG.

[0360] 19A shows an example in which the insulating layer 281 has a single-layer structure. Note that the insulating layer 281 can have a stacked structure of two or more layers. For example, as shown in FIG. 19B, the insulating layer 281 can have a three-layer structure including an insulating layer 281_1, an insulating layer 281_2 on the insulating layer 281_1, and an insulating layer 281_3 on the insulating layer 281_2. In this case, it is preferable to use the above-described material with a low relative dielectric constant for the insulating layer 281_2, and to use barrier insulating layers against oxygen for the insulating layers 281_1 and 281_3. This can prevent the conductive layer 255 and the conductive layer 240 from being oxidized and prevent high resistance.

[0361] Although the transistors 200A to 200D each have a configuration in which at least some of the components of the transistor are provided in the opening 290 that is circular in plan view, the present invention is not limited to this. At least some of the components of the transistor can be provided in a groove that is formed to extend.

[0362] In this specification and the like, a groove can be rephrased as a slit or a trench. Also, a groove portion can be rephrased as a slit portion or a trench portion. Note that a groove portion may also be rephrased as a slit or a trench.

[0363] [Transistor 200E] Fig. 20A is a plan view of a semiconductor device including transistor 200E. Fig. 20B is a cross-sectional view taken along dashed dotted line A1-A2 in Fig. 20A. Fig. 20C is a cross-sectional view taken along dashed dotted line A3-A4 in Fig. 20A. Fig. 20D is a cross-sectional view taken along dashed dotted line A5-A6 in Fig. 20B.

[0364] 20A to 20D includes an insulating layer 210 over a substrate (not shown), a transistor 200E over the insulating layer 210, and an insulating layer 280 over the insulating layer 210. The semiconductor device also includes a conductive layer 243a, a conductive layer 243b, and a conductive layer 246. Similarly to the semiconductor device shown in FIG. 7A, the semiconductor device also includes an insulating layer 283 over the transistor 200E. Similarly to the semiconductor device shown in FIGS. 10A to 10C, the semiconductor device also includes an insulating layer 285. The insulating layer 285 is provided over the insulating layer 283.

[0365] The transistor 200E includes a conductive layer 220 , a conductive layer 240 a and a conductive layer 240 b over an insulating layer 280 , an oxide semiconductor layer 230 , an insulating layer 250 , and a conductive layer 260 .

[0366] In the transistor 200E, the oxide semiconductor layer 230 functions as a semiconductor layer, the conductive layer 260 functions as a gate electrode, the insulating layer 250 functions as a gate insulating layer, the conductive layer 220 functions as one of a source electrode and a drain electrode, and the conductive layer 240a and the conductive layer 240b function as the other of the source electrode and the drain electrode.

[0367] 20A to 20D, the insulating layer 280 is provided with a groove 291 that reaches the conductive layer 220. The groove 291 extends in the X direction.

[0368] 20A to 20D differs from the transistor 200A shown in Figures 3A to 3D in that some components of the transistor are provided in a groove 291 instead of an opening 290. The transistor 200E also differs from the transistor 200A shown in Figures 3A to 3D in that the conductive layer 240 is separated into a conductive layer 240a and a conductive layer 240b by the groove 291.

[0369] The oxide semiconductor layer 230 , the insulating layer 250 , and the conductive layer 260 are each disposed so that at least a portion thereof is located within the groove 291 .

[0370] The oxide semiconductor layer 230 is provided in an island shape. The oxide semiconductor layer 230 is provided along part of the bottom and part of the sidewall of the groove 291. The oxide semiconductor layer 230 has a portion in contact with the top surface of the conductive layer 240, a portion in contact with the side surface of the conductive layer 240 on the groove 291 side, and a portion in contact with the bottom surface and side surface of the recess of the conductive layer 220 in the groove 291.

[0371] The insulating layer 250 is provided to cover the oxide semiconductor layer 230. The insulating layer 250 is provided on the insulating layer 280 to cover the top surface and side surfaces of the oxide semiconductor layer 230 and the side surfaces of the conductive layer 240.

[0372] The conductive layer 260 is provided so as to fill at least a part of the groove 291. Therefore, the conductive layer 260 is provided so as to extend in the direction in which the groove 291 extends.

[0373] In the transistor 200E, a channel is also formed along the sidewall of the groove 291.

[0374] Openings reaching the conductive layer 240a are provided in the insulating layers 285, 283, 250, and the oxide semiconductor layer 230, and a conductive layer 243a is provided in the openings. Openings reaching the conductive layer 240b are provided in the insulating layers 285, 283, 250, and the oxide semiconductor layer 230, and a conductive layer 243b is provided in the openings. The conductive layer 243a is in contact with the conductive layer 240a, and the conductive layer 243b is in contact with the conductive layer 240b.

[0375] The conductive layer 246 is provided on the insulating layer 285. The conductive layer 246 is connected to the conductive layer 240a via the conductive layer 243a and to the conductive layer 240b via the conductive layer 243b. The conductive layer 246 functions as the other of the source wiring and the drain wiring. The conductive layer 246 extends in the Y direction. In other words, the direction in which the conductive layer 246 extends intersects with the direction in which the groove portion 291 extends.

[0376] In the transistors 200A to 200D, the width of the conductive layer 240 in the X direction (short side) needs to be larger than the width D of the opening 290 in order to provide the conductive layer 240 in an extended state. On the other hand, in the transistor 200E, the conductive layer 240a and the conductive layer 240b, which function as the other of the source electrode and the drain electrode, are connected to each other through the conductive layer 246. Therefore, the width of the conductive layer 240a and the conductive layer 240b in the X direction can be reduced, and can be made smaller than the width D1 of the groove 291 (see FIG. 20D ), for example. Therefore, miniaturization of the semiconductor device can be achieved.

[0377] In a plan view, a side surface of the conductive layer 260 provided in the groove 291 faces a side surface of the oxide semiconductor layer 230 with the insulating layer 250 interposed therebetween. Therefore, the channel width of the transistor 200E is determined by the width D2 of the oxide semiconductor layer 230 (see FIG. 20D ). The channel width of the transistor 200E can be calculated as "2×D2."

[0378] Note that in the transistors 200A to 200D, the oxide semiconductor layer 230 in the opening 290 does not need to be processed; therefore, the oxide semiconductor layer 230 can be easily processed, which can improve productivity of the semiconductor device.

[0379] In a plan view of the transistor 200E, a portion of the oxide semiconductor layer 230 located in the groove 291 does not have a curved surface. Therefore, distortion is unlikely to occur in a region of the oxide semiconductor layer 230 near the insulating layer 250, and deterioration in the crystallinity of the region can be suppressed. Note that the region includes a channel formation region.

[0380] Note that in a plan view of the transistors 200A to 200D, a portion of the oxide semiconductor layer 230 located at the opening 290 has a curved surface. However, the curvature of the curved surface can be reduced (the radius of curvature of the curved surface can be increased) by increasing the width of the opening 290 or by reducing the thickness of the oxide semiconductor layer 230. Thus, distortion occurring in a region of the oxide semiconductor layer 230 near the insulating layer 250 can be reduced, and deterioration in the crystallinity of the region can be suppressed.

[0381] 20A to 20D , the height of the top surface of the conductive layer 260 is higher than the height of the top surface of the insulating layer 250. Note that the present invention is not limited to this. The height of the top surface of the conductive layer 260 may be the same as or approximately the same as the height of the top surface of the insulating layer 250, or may be lower than the height of the top surface of the insulating layer 250.

[0382] 21A to 21C will be used to describe a modification of the transistor 200E described with reference to FIGS. 20A to 20D. FIG. 21A is a plan view of a semiconductor device including the transistor 200E. FIG. 21B is a cross-sectional view taken along dashed dotted line A1-A2 in FIG. 21A. FIG. 21C is a cross-sectional view taken along dashed dotted line A3-A4 in FIG. 21A. Note that FIG. 20D can be referred to for a cross-sectional view taken along dashed dotted line A5-A6 in FIG. 21B.

[0383] The transistor 200E shown in FIGS. 21A to 21C differs from the transistor 200E shown in FIGS. 20A to 20D in that the height of the top surface of the conductive layer 260 is lower than the height of the top surface of the insulating layer 250.

[0384] By configuring the top surface of the conductive layer 260 to be lower than the top surface of the insulating layer 250, the area where the conductive layer 260 faces the conductive layer 240a or the conductive layer 240b can be reduced, and the parasitic capacitance generated between the conductive layer 260 and the conductive layer 240a or the conductive layer 240b can be reduced. Furthermore, by configuring the above, the physical distance between the conductive layer 260 and the conductive layer 246 can be increased, and the parasitic capacitance generated between the conductive layer 260 and the conductive layer 246 can be reduced. Therefore, the frequency characteristics of a circuit using the transistor can be improved.

[0385] 20A to 20D, the cross-sectional area of ​​the conductive layer 260 functioning as a gate wiring can be increased, leading to reduced wiring resistance. Thus, the power consumption of the semiconductor device can be reduced.

[0386] 20A to 20D illustrate a configuration in which the extension direction of the groove 291 coincides with the extension direction of the conductive layer 260 functioning as the gate wiring, but the present invention is not limited to this. For example, the extension direction of the groove 291 may intersect with the extension direction of the gate wiring.

[0387] [Transistor 200F] Fig. 22A is a plan view of a semiconductor device including transistor 200F. Fig. 22B is a cross-sectional view taken along dashed dotted line A1-A2 in Fig. 22A. Fig. 22C is a cross-sectional view taken along dashed dotted line A3-A4 in Fig. 22A. Fig. 22D is a cross-sectional view taken along dashed dotted line A5-A6 in Fig. 22B.

[0388] 22A to 22D includes an insulating layer 210 over a substrate (not shown), a transistor 200F over the insulating layer 210, and an insulating layer 280 over the insulating layer 210. Similarly to the transistor 200B shown in FIGS. 10A to 10C, the semiconductor device also includes an insulating layer 285 and a conductive layer 265 over the insulating layer 285. The insulating layer 285 is provided over the insulating layer 250.

[0389] The transistor 200F includes a conductive layer 220 , a conductive layer 240 a and a conductive layer 240 b , an oxide semiconductor layer 230 , an insulating layer 250 , and a conductive layer 260 .

[0390] In the transistor 200F, the oxide semiconductor layer 230 functions as a semiconductor layer, the conductive layer 260 functions as a gate electrode, the insulating layer 250 functions as a gate insulating layer, the conductive layer 220 functions as one of a source electrode and a drain electrode, and the conductive layer 240a and the conductive layer 240b function as the other of the source electrode and the drain electrode.

[0391] 22A to 22D differ from the semiconductor device shown in Figures 20A to 20D mainly in that it has a conductive layer 265 and does not have an insulating layer 283, a conductive layer 243a, a conductive layer 243b, or a conductive layer 246. It also differs from the semiconductor device shown in Figures 20A to 20D mainly in that the conductive layer 260 is provided in an island shape and that the conductive layers 240a and 240b are provided in an extended manner.

[0392] The conductive layer 265 is provided to extend in the Y direction, and the conductive layers 240a and 240b are provided to extend in the X direction.

[0393] The conductive layer 260 is provided in an island shape. In a plan view, the outer periphery of the conductive layer 260 is located inside the outer periphery of the oxide semiconductor layer 230. Note that in a plan view, the outer periphery of the conductive layer 260 may overlap with a part of the outer periphery of the oxide semiconductor layer 230 or may be located outside the part of the outer periphery of the oxide semiconductor layer 230.

[0394] The conductive layer 265 contacts the conductive layer 260 .

[0395] In the YZ plane including the oxide semiconductor layer 230, the end of the oxide semiconductor layer 230 outside the groove 291 is located more inward than the end of the conductive layer 240 outside the groove 291 (see FIG. 22B ). Note that in the YZ plane including the oxide semiconductor layer 230, the end of the oxide semiconductor layer 230 outside the groove 291 may coincide or approximately coincide with the end of the conductive layer 240 outside the groove 291, or may be located more outward than the end of the conductive layer 240 outside the groove 291.

[0396] The insulating layer 285 is provided on the insulating layer 250. The insulating layer 285 is also provided so as to fill in the portion of the groove 291 where the conductive layer 260 is not located.

[0397] 22A to 22D , the physical distance between the conductive layer 260 and the conductive layer 240a or 240b can be increased, and the parasitic capacitance generated between the conductive layer 260 and the conductive layer 240a or 240b can be reduced. Furthermore, the physical distance between the conductive layer 265 and the conductive layer 240a or 240b can be increased, and the parasitic capacitance generated between the conductive layer 265 and the conductive layer 240a or 240b can be reduced. Therefore, the frequency characteristics of a circuit using the transistor can be improved.

[0398] 22A to 22D illustrate a configuration in which the conductive layer 260 has a region facing the side surface of the conductive layer 240a with the oxide semiconductor layer 230 interposed therebetween and a region facing the side surface of the conductive layer 240b with the oxide semiconductor layer 230 interposed therebetween, but the present invention is not limited to this. For example, a first conductive layer facing the side surface of the conductive layer 240a with the oxide semiconductor layer 230 interposed therebetween and a second conductive layer facing the side surface of the conductive layer 240b with the oxide semiconductor layer 230 interposed therebetween may be provided.

[0399] [Transistor 200Ga and Transistor 200Gb] Fig. 23A is a plan view of a semiconductor device having two transistors. Fig. 23B is a cross-sectional view taken along dashed dotted line A1-A2 in Fig. 23A. Fig. 23C is a cross-sectional view taken along dashed dotted line A5-A6 in Fig. 23B.

[0400] The semiconductor device shown in FIGS. 23A to 23C includes an insulating layer 210 on a substrate (not shown), a transistor 200Ga and a transistor 200Gb on the insulating layer 210, and an insulating layer 280 on the insulating layer 210.

[0401] The transistor 200Ga includes a conductive layer 220a, a conductive layer 240a on the insulating layer 280, an oxide semiconductor layer 230a, an insulating layer 250a on the oxide semiconductor layer 230a, and a conductive layer 260a on the insulating layer 250a. The transistor 200Gb includes a conductive layer 220b, a conductive layer 240b on the insulating layer 280, an oxide semiconductor layer 230b, an insulating layer 250b on the oxide semiconductor layer 230b, and a conductive layer 260b on the insulating layer 250b.

[0402] In the transistor 200Ga, the oxide semiconductor layer 230a functions as a semiconductor layer, the conductive layer 260a functions as a gate electrode, the insulating layer 250a functions as a gate insulating layer, the conductive layer 220a functions as one of a source electrode and a drain electrode, and the conductive layer 240a functions as the other of the source electrode and drain electrode. In the transistor 200Gb, the oxide semiconductor layer 230b functions as a semiconductor layer, the conductive layer 260b functions as a gate electrode, the insulating layer 250b functions as a gate insulating layer, the conductive layer 220b functions as one of a source electrode and a drain electrode, and the conductive layer 240b functions as the other of the source electrode and drain electrode.

[0403] The semiconductor device shown in Figures 23A to 23C differs from the semiconductor device shown in Figures 22A to 22C in that the conductive layer 220, the oxide semiconductor layer 230, the insulating layer 250, and the conductive layer 260 are each separated in and near the groove 291.

[0404] In the YZ plane including the oxide semiconductor layer 230a and the oxide semiconductor layer 230b, by providing two transistors (transistor 200Ga and transistor 200Gb) in the groove portion 291, miniaturization and high integration of the semiconductor device can be promoted.

[0405] Although FIGS. 23A to 23C illustrate a configuration in which the insulating layer 250 is separated into insulating layers 250a and 250b, the present invention is not limited to this.

[0406] 24A to 24C will be used to describe modifications of the two transistors described using FIGS. 23A to 23C. FIG. 24A is a plan view of a semiconductor device having two transistors 200. FIG. 24B is a cross-sectional view taken along dashed dotted line A1-A2 in FIG. 24A. FIG. 24C is a cross-sectional view taken along dashed dotted line A5-A6 in FIG. 24A.

[0407] 24A to 24C differs from the semiconductor device shown in FIGS. 23A to 23C in that the insulating layer 250 covers the oxide semiconductor layer 230a and the oxide semiconductor layer 230b. Covering the oxide semiconductor layer 230a and the oxide semiconductor layer 230b with the insulating layer 250 can cover the side surface of the oxide semiconductor layer 230a on the groove 291 side and the side surface of the oxide semiconductor layer 230b on the groove 291 side. This can suppress diffusion of hydrogen into the oxide semiconductor layer 230a and the oxide semiconductor layer 230b. This makes it possible to realize a highly reliable transistor.

[0408] Note that a structure similar to that of at least one of the transistors 200A to 200D can also be applied to each of the transistors 200E, 200F, 200Ga, and 200Gb.

[0409] <Structural Example 2 of Semiconductor Device> Another structural example of a semiconductor device of one embodiment of the present invention will be described with reference to FIGS. 25A to 27C . FIG. 25A is a plan view of a semiconductor device including a transistor 200H. FIG. 25B is a cross-sectional view of a portion indicated by a dashed-dotted line A1-A2 in FIG. 25A , which is also a cross-sectional view of the transistor 200H in the channel length direction. FIG. 25C is a cross-sectional view of a portion indicated by a dashed-dotted line A3-A4 in FIG. 25A , which is also a cross-sectional view of the transistor 200H in the channel width direction. FIG. 25D is a cross-sectional view of a portion indicated by a dashed-dotted line A5-A6 in FIG. 25A . Also, FIGS. 26A to 27C show enlarged cross-sectional views of the transistor 200H in the channel length direction.

[0410] The transistor 200H includes a conductive layer 205, an insulating layer 221 on the conductive layer 205, an insulating layer 222 on the insulating layer 221, an insulating layer 224 on the insulating layer 222, an oxide semiconductor layer 230 on the insulating layer 224, conductive layers 242a and 242b on the oxide semiconductor layer 230, an insulating layer 271a on the conductive layer 242a, an insulating layer 271b on the conductive layer 242b, an insulating layer 250 on the oxide semiconductor layer 230, and a conductive layer 260 on the insulating layer 250.

[0411] In the transistor 200H, the oxide semiconductor layer 230 functions as a channel formation region, the conductive layer 260 functions as a first gate electrode (which can also be referred to as an upper gate electrode or a top gate electrode), and the insulating layer 250 functions as a first gate insulating layer. The conductive layer 205 functions as a second gate electrode (which can also be referred to as a lower gate electrode or a bottom gate electrode), and the insulating layers 224, 222, and 221 each function as a second gate insulating layer. The conductive layer 242a functions as one of a source electrode and a drain electrode, and the conductive layer 242b functions as the other of the source electrode and the drain electrode.

[0412] The oxide semiconductor layer 230, the insulating layer 224, the insulating layer 250, and the conductive layer 260 included in the transistor 200H correspond to the oxide semiconductor layer 30, the insulating layer 20, the insulating layer 50, and the conductive layer 60, respectively, described in Embodiment 1. Therefore, the structures, materials, and the like of the oxide semiconductor layer 30, the insulating layer 20, the insulating layer 50, and the conductive layer 60, described in Embodiment 1, can be referred to for the structures, materials, and the like of the oxide semiconductor layer 230, the insulating layer 224, the insulating layer 250, and the conductive layer 260.

[0413] Alternatively, the oxide semiconductor layer 230, the insulating layer 250, the insulating layer 224, and the conductive layer 205 included in the transistor 200H may correspond to the oxide semiconductor layer 30, the insulating layer 20, the insulating layer 50, and the conductive layer 60, respectively, described in Embodiment 1. In this case, the structures, materials, and the like of the oxide semiconductor layer 30, the insulating layer 20, the insulating layer 50, and the conductive layer 60, described in Embodiment 1, can be referred to for the structures, materials, and the like of the oxide semiconductor layer 230, the insulating layer 250, the insulating layer 224, and the conductive layer 205.

[0414] An insulating layer 275 is provided over the insulating layer 271a and the insulating layer 271b, and an insulating layer 280 is provided over the insulating layer 275. An opening 289 reaching the insulating layer 222 and the oxide semiconductor layer 230 is formed in the insulating layer 280 and the insulating layer 275, and the opening 289 overlaps with a region between the conductive layer 242a and the conductive layer 242b. In a plan view, the side surface of the insulating layer 280 in the opening 289 coincides or substantially coincides with the side surfaces of the conductive layer 242a and the conductive layer 242b. The insulating layer 250 and the conductive layer 260 are disposed inside the opening 289. An insulating layer 282 is provided in contact with the top surface of the insulating layer 280, the upper end of the insulating layer 250, and the top surface of the conductive layer 260. An insulating layer 283 is provided over the insulating layer 282. Further, an insulating layer 216 is provided under the insulating layer 221, an insulating layer 214 is provided under the insulating layer 216 and the conductive layer 205, and an insulating layer 212 is provided under the insulating layer 214. The insulating layer 212, the insulating layer 214, the insulating layer 280, the insulating layer 282, the insulating layer 283, and the insulating layer 285 function as interlayer films.

[0415] Openings reaching the conductive layer 242a are formed in the insulating layers 285, 283, 282, 280, 275, and 271a, and conductive layers 243a and 241a are provided in the openings. An insulating layer 241a is provided in contact with the sidewall of the opening, and the conductive layer 243a is provided inside the insulating layer 241a. Furthermore, openings reaching the conductive layer 242b are formed in the insulating layers 285, 283, 282, 280, 275, and 271b, and conductive layers 243b and 241b are provided in the openings. An insulating layer 241b is provided in contact with the sidewall of the opening, and the conductive layer 243b is provided inside the insulating layer 241b. The conductive layers 243a and 243b function as vias that connect a wiring or the like provided over the transistor 200H to the source or drain of the transistor 200H.

[0416] 26B , the oxide semiconductor layer 230 has a channel formation region 231. The oxide semiconductor layer 230 further has a source region and a drain region. The source region and the drain region are n-type regions (low-resistance regions) having a higher carrier concentration than the channel formation region 231. The oxide semiconductor layer 230 may have a single-layer structure or a stacked structure of two or more layers.

[0417] In the oxide semiconductor layer 230, a channel formation region 231 and a source region and a drain region sandwiching the channel formation region 231 are formed in the transistor 200H. At least part of the channel formation region 231 overlaps with the conductive layer 260. The source region overlaps with the conductive layer 242a, and the drain region overlaps with the conductive layer 242b. Note that the source region and the drain region can be interchanged.

[0418] An insulating layer containing excess oxygen is provided near the oxide semiconductor layer, and heat treatment is performed to supply oxygen from the insulating layer to the oxide semiconductor layer, thereby eliminating oxygen vacancies and V Ｏ H can be reduced. However, if an excessive amount of oxygen is supplied to the source region or the drain region, the on-state current or the field-effect mobility of the transistor 200H may decrease. Furthermore, variations in the amount of oxygen supplied to the source region or the drain region within the substrate surface may cause variations in the characteristics of a semiconductor device including the transistor. Furthermore, if the amount of oxygen supplied from the insulating layer to the oxide semiconductor layer becomes excessively large, this may adversely affect the electrical characteristics and reliability of the transistor. Furthermore, oxygen may diffuse into conductive layers such as the gate electrode, source electrode, and drain electrode, oxidizing the conductive layers and impairing their conductivity.

[0419] First, at least one of an insulating layer having a barrier property against hydrogen and an insulating layer having a function of capturing or fixing hydrogen is formed near the oxide semiconductor layer 230, and V in the channel formation region of the oxide semiconductor layer 230 and its vicinity is formed. Ｏ It is preferable to reduce H.

[0420] At least one of the insulating layer 212, the insulating layer 214, the insulating layer 221, the insulating layer 222, the insulating layer 275, the insulating layer 282, and the insulating layer 283 preferably functions as a barrier insulating layer against hydrogen. At least one of the insulating layer 212, the insulating layer 214, the insulating layer 221, the insulating layer 222, the insulating layer 275, the insulating layer 282, and the insulating layer 283 preferably functions as a barrier insulating layer against impurities. At least one of the insulating layer 212, the insulating layer 214, the insulating layer 221, the insulating layer 222, the insulating layer 275, the insulating layer 282, and the insulating layer 283 preferably functions as a barrier insulating layer against oxygen. Note that all of the insulating layer 212, the insulating layer 214, the insulating layer 221, the insulating layer 222, the insulating layer 275, the insulating layer 282, and the insulating layer 283 do not necessarily need to be provided. As long as the insulating layer has sufficient barrier properties against hydrogen, impurities, oxygen, and the like, the insulating layer can be formed by appropriately selecting from the insulating layer 212, the insulating layer 214, the insulating layer 221, the insulating layer 222, the insulating layer 275, the insulating layer 282, and the insulating layer 283. For example, a structure can be used in which the insulating layer 216 and the conductive layer 205 are formed in contact with the upper surface of the insulating layer 212 without providing the insulating layer 214.

[0421] The insulating layer 212, the insulating layer 221, the insulating layer 275, and the insulating layer 283 preferably have a function of suppressing diffusion of hydrogen. For example, the insulating layer 212, the insulating layer 221, the insulating layer 275, and the insulating layer 283 may be formed using silicon nitride, which has a higher hydrogen barrier property.

[0422] The insulating layer 214, the insulating layer 222, and the insulating layer 282 preferably have a function of capturing or fixing hydrogen. For example, aluminum oxide may be used for the insulating layer 214 and the insulating layer 282. For example, hafnium oxide, which is a high-k material, is preferably used for the insulating layer 222, which functions as the second gate insulating layer.

[0423] 26A , by providing the insulating layer 212 having a function of suppressing hydrogen diffusion under the transistor 200H, it is possible to suppress diffusion of hydrogen from a layer below the transistor 200H. Furthermore, by providing the insulating layer 214 having a function of capturing or fixing hydrogen, hydrogen contained in the insulating layer 216 or the like can be captured or fixed in the insulating layer 214. This allows the hydrogen concentration in the oxide semiconductor layer 230 and its vicinity to be reduced.

[0424] Furthermore, by providing the insulating layer 221 having a function of suppressing diffusion of hydrogen under the oxide semiconductor layer 230, it is possible to suppress diffusion of hydrogen from below the oxide semiconductor layer 230. Furthermore, by providing the insulating layer 222 having a function of capturing or fixing hydrogen, hydrogen contained in the insulating layer 224 or the like can be captured or fixed in the insulating layer 222. As a result, the hydrogen concentration in the oxide semiconductor layer 230 and its vicinity can be reduced.

[0425] Furthermore, by providing the insulating layer 275 having the function of suppressing diffusion of hydrogen so as to cover the oxide semiconductor layer 230, the conductive layer 242a, the conductive layer 242b, and the like, diffusion of hydrogen from the insulating layer 280 to the oxide semiconductor layer 230, the conductive layer 242a, the conductive layer 242b, and the like can be suppressed.

[0426] Furthermore, by providing the insulating layer 283 having a function of suppressing hydrogen diffusion over the transistor 200H, diffusion of hydrogen from above the transistor 200H can be suppressed. Furthermore, by providing the insulating layer 282 having a function of capturing or fixing hydrogen, hydrogen contained in the insulating layer 280 or the like can be captured or fixed to the insulating layer 282. As a result, the hydrogen concentration in the oxide semiconductor layer 230 and its vicinity can be reduced.

[0427] In this way, by using a structure in which the transistor 200H is surrounded by barrier insulating layers against hydrogen from above and below, diffusion of hydrogen into the oxide semiconductor is reduced, and the V Ｏ H can be reduced. This can improve the electrical characteristics and reliability of the transistor 200H.

[0428] Furthermore, excess oxygen is preferably contained in the insulating layer 280. When the oxygen is supplied to the oxide semiconductor layer 230 through the insulating layer 250 by heat treatment, oxygen vacancies in the channel formation region can be reduced.

[0429] The insulating layer 282 is preferably formed by a sputtering method in an atmosphere containing oxygen gas, which allows oxygen to be added to the insulating layer 280. The insulating layer 282 may have a single-layer structure or a stacked structure of two or more layers.

[0430] As described above, by performing heat treatment on the insulating layer 280 containing excess oxygen, a suitable amount of oxygen can be supplied to the oxide semiconductor layer 230 through the insulating layer 250. In the heat treatment, the insulating layers 282 and 283 having a barrier property against oxygen are formed over the insulating layer 280, so that the oxygen contained in the insulating layer 280 can be prevented from diffusing excessively from the insulating layer 280. Furthermore, the insulating layer 275 having a barrier property against oxygen is formed between the insulating layer 280 and the oxide semiconductor layer 230 and the conductive layer 242a and 242b, so that the oxygen contained in the insulating layer 280 can be prevented from diffusing excessively from the insulating layer 280. Furthermore, by performing the heat treatment with openings formed in parts of the insulating layer 280, the insulating layer 282, and the insulating layer 283, part of the oxygen contained in the insulating layer 280 can be diffused outward, and the amount of oxygen supplied from the insulating layer 280 to the oxide semiconductor layer 230 can be adjusted.

[0431] 26B , an oxide layer 227 can be provided between the insulating layer 224 and the oxide semiconductor layer 230. The oxide layer 227 corresponds to the oxide layer 27 described in Embodiment 1. Therefore, the structure, material, and the like of the oxide layer 227 can be referred to the structure, material, and the like of the oxide layer 27 described in Embodiment 1.

[0432] The oxide layer 227 is preferably formed by an ALD method. By forming the oxide layer 227 by an ALD method, the coverage of the oxide layer 227 can be improved.

[0433] The oxide layer 227 can also be formed by a sputtering method. When the oxide layer 227 is formed by a sputtering method, a layer in which components contained in the oxide layer 227 and components contained in the conductive layer 220 are mixed is formed due to damage caused by sputtering. The insulating property of this layer is lower than that of the oxide layer 227, and therefore, an increase in contact resistance between the conductive layer 220 and the oxide semiconductor layer 230 can be suppressed. The same applies to the contact resistance between the conductive layer 240 and the oxide semiconductor layer 230.

[0434] 26A shows an example in which the oxide semiconductor layer 230 has a single-layer structure. Note that the oxide semiconductor layer 230 can have a stacked structure of two or more layers. As shown in FIG. 27A , the oxide semiconductor layer 230 can have a two-layer structure including an oxide semiconductor layer 230_1 and an oxide semiconductor layer 230_2 over the oxide semiconductor layer 230_1. The oxide semiconductor layer 230_1 and the oxide semiconductor layer 230_2 correspond to the oxide semiconductor layer 30a and the oxide semiconductor layer 30b described in Embodiment 1, respectively. Therefore, the structures, materials, and the like of the oxide semiconductor layer 30a and the oxide semiconductor layer 30b described in Embodiment 1 can be referred to for the structures, materials, and the like of the oxide semiconductor layer 30a and the oxide semiconductor layer 30b.

[0435] 27A illustrates a structure in which the insulating layer 250 is in contact with the top surface of the oxide semiconductor layer 230_2, but the present invention is not limited to this. For example, as illustrated in FIG. 27B , a structure can be adopted in which the insulating layer 250 is in contact with the side surface of the oxide semiconductor layer 230_2 and the top surface of the oxide semiconductor layer 230_1 by removing the oxide semiconductor layer 230_2 in a region overlapping with the opening 289. With such a structure, the distance between the conductive layer 260 and the oxide semiconductor layer 230_1 can be shortened. Therefore, an electric field from the gate electrode can be suitably applied to the oxide semiconductor layer 230_1.

[0436] The insulating layer 250 preferably has a structure that allows oxygen to diffuse from the insulating layer 280 to the oxide semiconductor layer 230 and prevents the conductive layers 242a, 242b, and 260 from being oxidized.

[0437] The insulating layer 250 is formed within the opening 289 in contact with the top surface of the insulating layer 222, the side surface of the insulating layer 224, the side surface and top surface of the oxide semiconductor layer 230, the side surface of the conductive layer 242a, the side surface of the conductive layer 242b, the side surface of the insulating layer 271a, the side surface of the insulating layer 271b, the side surface of the insulating layer 275, and the side surface of the insulating layer 280.

[0438] Here, as shown in FIG. 26A, the insulating layer 250 preferably has a stacked-layer structure of an insulating layer 250_1 in contact with the oxide semiconductor layer 230, an insulating layer 250_2 over the insulating layer 250_1, and an insulating layer 250_3 over the insulating layer 250_2.

[0439] Furthermore, as shown in FIG. 27C, a structure in which an insulating layer 250_4 is provided on an insulating layer 250_2 may be used.

[0440] The structures, materials, and the like of the insulating layers 250_1 to 250_4 can be referred to those of the insulating layers 250_1 to 250_4 described above in <Structural Example 1 of Semiconductor Device>.

[0441] For example, the insulating layer 250_1, which has a region in contact with the side surface of the conductive layer 242a and the side surface of the conductive layer 242b, has a function of capturing or fixing oxygen, which can prevent the side surfaces of the conductive layer 242a and the conductive layer 242b from being oxidized and oxide films from being formed on the side surfaces. This can prevent a decrease in the on-state current or the field-effect mobility of the transistor 200H. Furthermore, with this structure, the amount of oxygen in the insulating layer 250_2 absorbed by the conductive layer 242a and the conductive layer 242b can be reduced. Therefore, an appropriate amount of oxygen can be supplied from the insulating layer 250_2 to the oxide semiconductor layer 230, and oxygen vacancies in the channel formation region of the oxide semiconductor layer 230 can be reduced.

[0442] Furthermore, by providing the insulating layer 250_1 between the insulating layer 280 and the insulating layer 250_2 and between the insulating layer 250_2 and the oxide semiconductor layer 230, excessive supply of oxygen from the insulating layer 280 to the oxide semiconductor layer 230 can be suppressed, and an appropriate amount of oxygen can be supplied to the oxide semiconductor layer 230. Therefore, the amount of oxygen in the channel formation region of the oxide semiconductor layer 230 and its vicinity can be controlled to an appropriate amount, which can prevent the transistor 200H from becoming excessively normally off and improve reliability. Furthermore, excessive oxidation of the source and drain regions can be suppressed, which can cause a decrease in on-state current or a decrease in field-effect mobility of the transistor 200H.

[0443] By adopting the above-described structure, the channel formation region can be made i-type or substantially i-type, and the source region and drain region can be made n-type, thereby providing a semiconductor device with excellent electrical characteristics. Furthermore, by adopting the above-described structure, the semiconductor device can have excellent electrical characteristics even when miniaturized or highly integrated. Furthermore, miniaturizing the transistor 200H can improve high-frequency characteristics. Specifically, the cutoff frequency can be improved.

[0444] To miniaturize the transistor 200H, the insulating layers 250_1 to 250_4 preferably have thin thicknesses. The insulating layers 250_1 to 250_4 each have a thickness of preferably 0.1 nm to 20 nm, more preferably 0.1 nm to 10 nm, more preferably 0.5 nm to 5.0 nm, more preferably 1.0 nm to less than 5.0 nm, and still more preferably 1.0 nm to 3.0 nm. Note that each of the insulating layers 250_1 to 250_4 may have a region with the above thickness in at least a portion thereof.

[0445] The conductive layer 205 is disposed so as to overlap with the oxide semiconductor layer 230 and the conductive layer 260. The conductive layer 205 can be formed using a conductive material described in the later section [Conductive Layer]. Here, the conductive layer 205 is provided so as to be embedded in an opening formed in the insulating layer 216. Furthermore, the conductive layer 205 is preferably provided so as to extend in the channel width direction as shown in FIGS. 25A and 25C . With such a structure, the conductive layer 205 functions as a wiring when a plurality of transistors are provided.

[0446] 26A , the conductive layer 205 preferably includes a conductive layer 205_1 and a conductive layer 205_2. The conductive layer 205_1 is provided in contact with the bottom surface and sidewall of the opening. The conductive layer 205_2 is provided so as to fill a recess in the conductive layer 205_1 formed along the opening. Here, the height of the top surface of the conductive layer 205 is the same as or approximately the same as the height of the top surface of the insulating layer 216.

[0447] Here, the conductive layer 205_1 contains hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, and nitrogen oxide molecules (N ２ O, NO, NO ２ It is preferable to have a conductive material that has a function of suppressing the diffusion of impurities such as copper atoms, etc. Alternatively, it is preferable to have a conductive material that has a function of suppressing the diffusion of oxygen (for example, at least one of oxygen atoms and oxygen molecules, etc.).

[0448] By using a conductive material that can reduce hydrogen diffusion for the conductive layer 205_1, impurities such as hydrogen contained in the conductive layer 205_2 can be prevented from diffusing into the oxide semiconductor layer 230 through the insulating layer 216 or the like. Furthermore, by using a conductive material that can suppress oxygen diffusion for the conductive layer 205_1, oxidation of the conductive layer 205_2 and a decrease in conductivity can be suppressed. Examples of conductive materials that can suppress oxygen diffusion include titanium, titanium nitride, tantalum, tantalum nitride, ruthenium, and ruthenium oxide. The conductive layer 205_1 can have a single-layer structure or a stacked-layer structure of any of the above conductive materials. For example, the conductive layer 205_1 preferably contains titanium nitride.

[0449] The conductive layer 205_2 is preferably formed using a conductor with high conductivity. For example, the conductive layer 205_2 is preferably formed using a conductive material containing tungsten, copper, or aluminum as a main component. For example, the conductive layer 205_2 preferably contains tungsten.

[0450] The conductive layer 205 can function as a second gate electrode. In this case, the threshold voltage (Vth) of the transistor 200H can be controlled by changing the potential applied to the conductive layer 205 independently of the potential applied to the conductive layer 260. In particular, applying a negative potential to the conductive layer 205 can increase the Vth of the transistor 200H and reduce its off-state current. Therefore, applying a negative potential to the conductive layer 205 can reduce the drain current when the potential applied to the conductive layer 260 is 0 V, compared to when a negative potential is not applied.

[0451] 26A shows a stacked structure of the conductive layer 205_1 and the conductive layer 205_2, the present invention is not limited thereto, and the conductive layer 205 may have a single-layer structure or a stacked structure of three or more layers. For example, the conductive layer 205_1 may have a two-layer structure of a tantalum nitride film and a titanium nitride film on the tantalum nitride film, and the conductive layer 205_2 having a tungsten film may be provided on the conductive layer 205_1. With such a structure, impurities such as hydrogen and metal impurities such as copper contained in the lower layer of the transistor 200H can be prevented from diffusing into the conductive layer 205.

[0452] The insulating layer 224 functions as a second gate insulating layer together with the insulating layers 221 and 222 .

[0453] The insulating layer 224 in contact with the oxide semiconductor layer 230 can be formed using the insulating material applicable to the insulating layer 20 described in Embodiment 1. The insulating layer 224 preferably includes, for example, a silicon oxide film or a silicon oxynitride film. This allows oxygen to be supplied from the insulating layer 224 to the oxide semiconductor layer 230, thereby reducing oxygen vacancies. Note that the insulating layer 224 may have a stacked structure of two or more layers. In this case, the insulating layer 224 is not limited to a stacked structure made of the same material, and may have a stacked structure made of different materials.

[0454] Similarly to the oxide semiconductor layer 230, the insulating layer 224 is preferably processed into an island shape. Thus, when a plurality of transistors 200H are provided, each transistor 200H has an insulating layer 224 of approximately the same size. As a result, the amount of oxygen supplied from the insulating layer 224 to the oxide semiconductor layer 230 in each transistor 200H becomes approximately the same. Therefore, variation in the electrical characteristics of the transistors 200H within the substrate plane can be suppressed.

[0455] Furthermore, by providing the insulating layer 224 in an island shape, at least a part of the lower surface of the conductive layer 260 can be provided below the lower surface of the oxide semiconductor layer 230 (see FIG. 25C ). This allows the conductive layer 260 to be provided facing the upper surface and side surface of the oxide semiconductor layer 230, and therefore the electric field of the conductive layer 260 can be applied to the upper surface and side surface of the oxide semiconductor layer 230.

[0456] However, the insulating layer 224 does not necessarily have to be processed into an island shape. For example, as shown in Figures 28A to 28D, the insulating layer 224 may not be formed into an island shape, but may have a shape in which an opening is formed in part. Figures 28A to 28D correspond to Figures 25A to 25D, respectively, and are similar to Figures 25A to 25D except for the shape of the insulating layer 224.

[0457] 28A to 28D , the insulating layer 224 has a smaller thickness in a region that does not overlap with the oxide semiconductor layer 230 than in a region that overlaps with the oxide semiconductor layer 230. Furthermore, an opening is formed in a region that does not overlap with the oxide semiconductor layer 230 and overlaps with the insulating layer 250. When multiple transistors are provided over the same substrate, forming the insulating layer 224 in this manner allows the oxide semiconductor layer 230 of each transistor to be formed over the same insulating layer 224. This can reduce variations in the amount of oxygen supplied from the insulating layer 224 to the oxide semiconductor layer 230 of each transistor. Therefore, variations in the electrical characteristics of each transistor can be reduced.

[0458] Note that in the insulating layer 224 shown in Figures 28A to 28D, an opening is formed in a region that does not overlap with the oxide semiconductor layer 230 and overlaps with the insulating layer 250; however, a configuration without such an opening may be used.

[0459] The conductive layers 242a, 242b, and 260 can be formed using the conductive materials described in the section "Conductive Layer" below. In particular, it is preferable to use a conductive material that is resistant to oxidation or a conductive material that has a function of suppressing oxygen diffusion for the conductive layers 242a, 242b, and 260. Examples of such conductive materials include a conductive material containing nitrogen and a conductive material containing oxygen. This can suppress a decrease in the conductivity of the conductive layers 242a, 242b, and 260.

[0460] For the conductive layers 242a and 242b, it is preferable to use a metal nitride, such as a nitride containing tantalum, a nitride containing titanium, a nitride containing molybdenum, a nitride containing tungsten, a nitride containing tantalum and aluminum, or a nitride containing titanium and aluminum. For example, tantalum nitride can be used for the conductive layers 242a and 242b. Alternatively, for example, ruthenium, ruthenium oxide, ruthenium nitride, an oxide containing strontium and ruthenium, or an oxide containing lanthanum and nickel may be used. These materials are preferable because they are conductive materials that are resistant to oxidation or that maintain their conductivity even when they absorb oxygen.

[0461] Alternatively, each of the conductive layers 242a and 242b may have a stacked structure. In this case, the conductive material may be used for the lower layers of the conductive layers 242a and 242b, and a conductive material with higher conductivity may be used for the upper layers of the conductive layers 242a and 242b. For example, tantalum nitride may be used for the lower layer, and tungsten may be used for the upper layer.

[0462] The insulating layers 271a and 271b are inorganic insulating layers that function as etching stoppers and protect the conductive layers 242a and 242b when processing the conductive layers 242a and 242b. Furthermore, since the insulating layers 271a and 271b are in contact with the conductive layers 242a and 242b, they are preferably inorganic insulators that are less likely to oxidize the conductive layers 242a and 242b. Therefore, each of the insulating layers 271a and 271b preferably has a two-layer structure. Here, the lower layers of the insulating layers 271a and 271b are preferably made of a nitride insulator that can be used for the insulating layer 250_3, and preferably made of silicon nitride, in order to prevent the conductive layers 242a and 242b from being oxidized. The insulating layer 271a and the insulating layer 271b are each preferably formed using an oxide insulator, which can be used for the insulating layer 250_2, and preferably using silicon oxide, so as to function as an etching stopper.

[0463] The insulating layers that are the basis for the insulating layers 271a and 271b function as masks for the conductive layers that are the basis for the conductive layers 242a and 242b, so that the conductive layers 242a and 242b do not have curved surfaces between their side surfaces and top surfaces, as shown in FIG. 25D . As a result, the conductive layers 242a and 242b have angular ends where their side surfaces and top surfaces intersect. The angular ends where their side surfaces and top surfaces intersect increase the cross-sectional areas of the conductive layers 242a and 242b compared to when the ends have curved surfaces. As a result, the resistance of the conductive layers 242a and 242b is reduced, thereby increasing the on-state current of the transistor.

[0464] The conductive layer 260 is provided in the opening 289 so as to cover the upper surface of the insulating layer 222, the side surface of the insulating layer 224, and the side surface and upper surface of the oxide semiconductor layer 230 via the insulating layer 250. The height of the upper surface of the conductive layer 260 is equal to or approximately equal to the height of the upper end of the insulating layer 250 and the height of the upper surface of the insulating layer 280.

[0465] The sidewall of the opening 289 may be perpendicular or approximately perpendicular to the upper surface of the insulating layer 222, or may be tapered. By tapering the sidewall, the coverage of the insulating layer 250 provided in the opening 289 is improved, and defects such as voids can be reduced.

[0466] 25A and 25C, the conductive layer 260 is preferably provided so as to extend in the channel width direction. With this configuration, when a plurality of transistors are provided, the conductive layer 260 functions as wiring.

[0467] 25C , in a cross-sectional view of the transistor 200H in the channel width direction, a curved surface may be formed between the side surface of the oxide semiconductor layer 230 and the top surface of the oxide semiconductor layer 230. In other words, the end of the side surface and the end of the top surface may be curved.

[0468] 26A , the conductive layer 260 preferably has a two-layer structure. Here, the conductive layer 260 preferably includes a conductive layer 260_1 and a conductive layer 260_2 disposed over the conductive layer 260_1. For example, the conductive layer 260_1 is preferably disposed so as to surround the bottom and side surfaces of the conductive layer 260_2. In this case, it is preferable to use a conductive material that is resistant to oxidation or a conductive material that has a function of suppressing oxygen diffusion as the conductive layer 260_1.

[0469] The conductive layer 260_1 can be formed using a conductive material that can be used for the conductive layer 205_1. For example, the conductive layer 260_1 has a function of suppressing oxygen diffusion, which can suppress a decrease in the conductivity of the conductive layer 260_2 due to oxidation of the conductive layer 260_2 by oxygen contained in the insulating layer 280 or the like.

[0470] The conductive layer 260_2 can be formed using a conductive material that can be used for the conductive layer 205_2. The conductive layer 260_2 may have a stacked-layer structure, for example, a stacked-layer structure of a titanium film or a titanium nitride film and a conductive material that can be used for the conductive layer 205_2.

[0471] The insulating layer 216, the insulating layer 280, and the insulating layer 285 preferably have a lower relative dielectric constant than the insulating layer 222. By using a material with a low relative dielectric constant as an interlayer film, parasitic capacitance generated between wirings can be reduced.

[0472] For example, the insulating layer 216, the insulating layer 280, and the insulating layer 285 can each be made of a material with a low dielectric constant, which will be described later in the section [Insulating Layer]. In particular, silicon oxide and silicon oxynitride are preferable because they are thermally stable. Furthermore, materials such as silicon oxide, silicon oxynitride, and silicon oxide with vacancies are preferable because they can easily form a region containing excess oxygen.

[0473] Furthermore, the upper surfaces of the insulating layer 216 and the insulating layer 280 may each be flattened.

[0474] It is preferable that the concentration of impurities such as water and hydrogen is reduced in the insulating layer 280. For example, it is preferable that the insulating layer 280 has an oxide containing silicon, such as silicon oxide or silicon oxynitride.

[0475] The conductive layers 243a and 243b can be formed using the conductive materials described in the section "Conductive Layer" below. The conductive layers 243a and 243b are preferably formed using a conductive material containing tungsten, copper, or aluminum as a main component, for example. The conductive layers 243a and 243b may have a stacked structure.

[0476] 26A , the conductive layer 243a and the conductive layer 243b may have a two-layer laminated structure. The conductive layer 243a includes a conductive layer 243a1 formed along the opening and a conductive layer 243a2 formed inside the conductive layer 243a1. The conductive layer 243b includes a conductive layer 243b1 formed along the opening and a conductive layer 243b2 formed inside the conductive layer 243b1.

[0477] The conductive layer 243a1 and the conductive layer 243b1 can be formed as a single layer or a stacked layer using a conductive material that can be used for the conductive layer 205_1. Providing the conductive layer 243a1 and the conductive layer 243b1 can prevent impurities such as water and hydrogen from entering the oxide semiconductor layer 230 through the conductive layer 243a2 and the conductive layer 243b2. Note that the conductive layer 243a2 and the conductive layer 243b2 may be formed using a conductive material that can be used for the conductive layer 243a and the conductive layer 243b.

[0478] 25B, the height of the upper surfaces of conductive layers 243a and 243b is the same or approximately the same as the height of the upper surface of insulating layer 285. Also, as shown in Fig. 26A, conductive layer 243a may be formed so that its lower portion is embedded in conductive layer 242a. Similarly, conductive layer 243b may be formed so that its lower portion is embedded in conductive layer 242b.

[0479] The insulating layers 241a and 241b may be barrier insulating layers applicable to the insulating layer 275 or the like. For example, silicon nitride may be used for the insulating layers 241a and 241b. The insulating layers 241a and 241b are provided in contact with the insulating layers 285, 283, 282, 275, 271a, and 271b. This can prevent impurities such as water and hydrogen contained in the insulating layer 280 or the like from being mixed into the oxide semiconductor layer 230 through the conductive layers 243a and 243b. Silicon nitride is particularly suitable because it has a high barrier property against hydrogen. Furthermore, oxygen contained in the insulating layer 280 can be prevented from being absorbed by the conductive layers 243a and 243b.

[0480] The insulating layer 241 a and the insulating layer 241 b may have a stacked structure. In this case, a first insulating layer in contact with a sidewall of an opening such as the insulating layer 280 and a second insulating layer on the inner side thereof preferably use a combination of a barrier insulating layer against oxygen and a barrier insulating layer against hydrogen.

[0481] 25B and other figures, insulating layer 250 is in contact with the side surface of insulating layer 280 in opening 289, but the present invention is not limited to this configuration. For example, an insulating layer may be provided between insulating layer 250 and insulating layer 280 in opening 289.

[0482] 29A to 30C will be used to describe modifications of the semiconductor device described with reference to FIGS. 25A to 25D. FIGS. 29A to 29D are plan views and cross-sectional views of a semiconductor device including a transistor 200H, and correspond to the plan views and cross-sectional views shown in FIGS. 25A to 25D, respectively. Also, FIGS. 30A to 30C are enlarged cross-sectional views of the transistor 200H in the channel length direction, and correspond to the enlarged cross-sectional view shown in FIG. 26B, respectively.

[0483] 29A to 29D differs from the transistor 200H shown in Figures 25A to 25D mainly in that it has an insulating layer 254. Hereinafter, differences from the above description will be mainly described, and overlapping portions will be referred to and may not be described again.

[0484] 29A to 29D, the conductive layers 242a and 242b are each shown as a two-layer structure. The conductive layer 242a has a layered structure of a conductive layer 242a1 and a conductive layer 242a2 on the conductive layer 242a1. The conductive layer 242b has a layered structure of a conductive layer 242b1 and a conductive layer 242b2 on the conductive layer 242b1. The conductive layers 242a1 and 242b1 correspond to the lower layers of the conductive layers 242a and 242b, respectively, and the conductive layers 242a2 and 242b2 correspond to the upper layers of the conductive layers 242a and 242b, respectively.

[0485] 29B and 29C , insulating layer 254 is disposed inside opening 289 and contacts the side surface of insulating layer 280, the side surface of conductive layer 242a2, the side surface of conductive layer 242b2, the top surface of conductive layer 242a1, the top surface of conductive layer 242b1, and the top surface of insulating layer 222 in opening 289. In other words, insulating layer 254 can be said to be formed in the shape of a sidewall in contact with the side wall of opening 289. Here, the side wall of opening 289 corresponds to, for example, the side surface of insulating layer 280, etc. in opening 289.

[0486] The insulating layer 254 preferably has a barrier property against oxygen. The insulating layer 254 having a barrier property against oxygen can prevent the side surfaces of the conductive layers 242a and 242b from being oxidized and oxide films from being formed on the side surfaces. This can prevent a decrease in the on-state current or the field-effect mobility of the transistor 200H. An oxygen barrier insulating layer can be used as the insulating layer 254. For example, silicon nitride can be used as the insulating layer 254.

[0487] The opening 289 overlaps the region between the conductive layer 242a2 and the conductive layer 242b2. In a plan view, the side surfaces of the insulating layer 280 in the opening 289 coincide or substantially coincide with the side surfaces of the conductive layer 242a2 and the conductive layer 242b2. Furthermore, portions of the conductive layers 242a1 and 242b1 are formed to protrude into the opening 289. In other words, the portion of the conductive layer 242a1 on which the insulating layer 254 is formed (hereinafter, sometimes referred to as the protruding portion of the conductive layer 242a1) protrudes toward the conductive layer 260 more than the conductive layer 242a2. Similarly, the portion of the conductive layer 242b1 on which the insulating layer 254 is formed (hereinafter, sometimes referred to as the protruding portion of the conductive layer 242b1) protrudes toward the conductive layer 260 more than the conductive layer 242b2.

[0488] Here, part of the top surface of the conductive layer 242a1 is in contact with the conductive layer 242a2, and part of the top surface of the conductive layer 242b1 is in contact with the conductive layer 242b2. Therefore, the insulating layer 254 is in contact with another part of the top surface of the conductive layer 242a1, another part of the top surface of the conductive layer 242b1, a side surface of the conductive layer 242a2, and a side surface of the conductive layer 242b2 inside the opening 289. Furthermore, the insulating layer 250 is in contact with the top surface of the oxide semiconductor layer 230, the side surface of the conductive layer 242a1, the side surface of the conductive layer 242b1, and the side surface of the insulating layer 254.

[0489] The insulating layer 254 is formed by anisotropic etching to have a sidewall shape in contact with the side wall of the opening 289. The insulating layer 254 is formed in contact with the side surface of the conductive layer 242a2 and the side surface of the conductive layer 242b2 and has a function of protecting the conductive layer 242a2 and the conductive layer 242b2.

[0490] 30A , in a cross-sectional view of the transistor 200H, the side edges of the insulating layer 254 coincide or substantially coincide with the side edges of the conductive layer 242a1 and the conductive layer 242b1.

[0491] Note that after separating the conductive layer 242a1 and the conductive layer 242b1, it is preferable to perform heat treatment in an atmosphere containing oxygen before forming the insulating layer 250. At this time, since the insulating layer 254 is formed in contact with the side surfaces of the conductive layer 242a2 and the conductive layer 242b2, excessive oxidation of the conductive layer 242a2 and the conductive layer 242b2 can be prevented. Furthermore, even when microwave plasma treatment is performed after separating the conductive layer 242a1 and the conductive layer 242b1, formation of an oxide film on the side surfaces of the conductive layer 242a and the conductive layer 242b can be suppressed.

[0492] The insulating layer 254, the insulating layer 250, and the conductive layer 260 are provided to reflect the shape of the opening 289. Therefore, the insulating layer 254 is provided so as to cover the sidewall of the opening 289, the insulating layer 250 is provided so as to cover the bottom of the opening 289 and the insulating layer 254, and the conductive layer 260 is provided so as to fill the recess of the insulating layer 250.

[0493] As described above, the insulating layer 250 may have a stacked structure. For example, as shown in FIG. 30A , the insulating layer 250 may have a three-layer structure of insulating layers 250_1 to 250_3. Alternatively, as shown in FIG. 30B , the insulating layer 250 may have a four-layer structure of insulating layers 250_1 to 250_4.

[0494] The thickness of the insulating layer 254 is preferably 0.5 nm to 20 nm, more preferably 0.5 nm to 10 nm, and still more preferably 0.5 nm to 3 nm. By setting the insulating layer 254 to the above thickness, excessive oxidation of the conductive layer 242a2 and the conductive layer 242b2 can be suppressed. Note that the insulating layer 254 only needs to have a region with the above thickness in at least a portion. Furthermore, since the insulating layer 254 is provided in contact with the sidewall of the opening 289, it is preferable to deposit the insulating layer 254 by an ALD method or the like, which has good coverage. If the insulating layer 254 is too thick, the deposition time of the insulating layer 254 by the ALD method increases, resulting in reduced productivity. Therefore, the thickness of the insulating layer 254 is preferably within the above range. The insulating layer 254 preferably has a thickness large enough not to excessively hinder diffusion of excess oxygen from the insulating layer 280 to the insulating layer 250_2 and from the insulating layer 250_2 to the oxide semiconductor layer 230.

[0495] As shown in FIG. 30A , in a cross-sectional view of the transistor 200H in the channel length direction, the distance L1 between the conductive layers 242a1 and 242b1 is smaller than the distance L2 between the conductive layers 242a2 and 242b2. Here, distance L1 refers to the shortest distance between the conductive layers 242a1 and 242b1, and distance L2 refers to the shortest distance between the conductive layers 242a2 and 242b2. This configuration allows for a shorter source-drain distance and a correspondingly shorter channel length. This improves the frequency characteristics of the transistor 200H. By miniaturizing the semiconductor device in this way, a semiconductor device with improved operating speed can be provided.

[0496] 30A , the difference between distance L2 and distance L1 is equal to twice the film thickness of insulating layer 254. In other words, distance L2 is equal to or approximately equal to distance L1 obtained by adding twice the film thickness of insulating layer 254. Here, the film thickness of insulating layer 254 refers to the width of at least a portion of insulating layer 254 in the A1-A2 direction.

[0497] The insulating layer 254 may also have a stacked structure of two or more layers. In this case, at least one layer can be the inorganic insulating layer that is resistant to oxidation. For example, the inorganic insulating layer that is resistant to oxidation may be used as the first insulating layer of the insulating layer 254, and an insulating material (e.g., silicon oxide) applicable to the insulating layer 250_2 may be used as the second insulating layer on the first insulating layer of the insulating layer 254. The second insulating layer of the insulating layer 254 preferably has a lower dielectric constant than the first insulating layer of the insulating layer 254. By increasing the thickness of the insulating layer 254 by forming the insulating layer 254 into a two-layer structure, the distance between the conductive layer 260 and the conductive layer 242a or 242b can be increased, thereby reducing parasitic capacitance.

[0498] Although the above describes an example in which the insulating layer 254 is formed into a sidewall shape by anisotropic etching, the present invention is not limited to this. As shown in Fig. 30C, the insulating layer 254 may have an opening inside the opening 289. In this case, the opening in the insulating layer 254 can be formed by removing a part of the insulating film that will become the insulating layer 254 by lithography. The opening in the insulating layer 254 preferably overlaps with the region between the conductive layer 242a1 and the conductive layer 242b1.

[0499] 30C, in a cross-sectional view, a protrusion is formed at the lower part of the insulating layer 254. The protrusion of the insulating layer 254 overlaps with the protrusion of the conductive layer 242a1 and the protrusion of the conductive layer 242b1.

[0500] In the first modification, the insulating layer 254 is provided in contact with the sidewall of the opening 289. However, the present invention is not limited to this configuration. For example, the insulating layer 254 may not be provided in the opening 289.

[0501] 31A to 31D are plan views and cross-sectional views of a semiconductor device including a transistor 200H, and correspond to the plan views and cross-sectional views shown in FIGS. 29A to 29D, respectively. FIG. 32 is an enlarged cross-sectional view of the transistor 200H in the channel length direction, and corresponds to the enlarged cross-sectional view shown in FIG. 30C.

[0502] 31A to 31D differs from the transistor 200H shown in Figures 29A to 29D mainly in that it does not have an insulating layer 254. Hereinafter, differences from the above description will be mainly described, and overlapping portions will be referred to and may not be described again.

[0503] 32 , in a configuration in which the insulating layer 254 is not provided, a portion of the insulating layer 250 is disposed so as to overlap the protruding portions of the conductive layer 242a1 and the conductive layer 242b1. Also, a portion of the conductive layer 260 may be disposed so as to overlap the protruding portions of the conductive layer 242a1 and the conductive layer 242b1. Here, the protruding portions of the conductive layer 242a1 and the conductive layer 242b1 contact the insulating layer 250. Furthermore, the side surface of the insulating layer 250 contacts the side surfaces of the insulating layer 280, the insulating layer 275, the insulating layer 271a, the insulating layer 271b, the conductive layer 242a2, and the conductive layer 242b2.

[0504] The insulating layer 250 is formed to reflect the shape of the opening 289. Therefore, the insulating layer 250 is formed to reflect the shapes of the conductive layers 242a1 and 242b1 protruding into the opening 289.

[0505] 32, in a cross-sectional view of the transistor 200H in the channel length direction, the distance L1 between the conductive layer 242a1 and the conductive layer 242b1 is smaller than the distance L2 between the conductive layer 242a2 and the conductive layer 242b2. This configuration allows the distance between the source and the drain to be shortened, thereby shortening the channel length accordingly. This improves the frequency characteristics of the transistor 200H. By miniaturizing the semiconductor device in this way, a semiconductor device with improved operating speed can be provided.

[0506] 32, the width of the upper portion of the conductive layer 260 can be made larger than the distance L1, thereby reducing the wiring resistance of the conductive layer 260. As a result, the power consumption of the semiconductor device can be reduced.

[0507] <Constituent Materials of Semiconductor Device> Materials that can be used in the semiconductor device of this embodiment will be described below. Note that each layer constituting the semiconductor device of this embodiment may have a single-layer structure or a multilayer structure.

[0508] [Oxide Semiconductor Layer] As described above, the oxide semiconductor layer 230 has a channel formation region. The oxide semiconductor layer 230 further has a source region and a drain region. The source region and the drain region are n-type regions (low-resistance regions) having a higher carrier concentration than the channel formation region. The oxide semiconductor layer 230 may have a stacked structure of two or more layers.

[0509] The carrier concentration in the channel formation region is 1×10 １８ cm −３ Below, 1 x 10 １７ cm −３ Less than 1 x 10 １６ cm −３ Less than 1 x 10 １５ cm −３ Less than 1 x 10 １４ cm −３ Less than 1 x 10 １３ cm −３ Less than 1 x 10 １２ cm −３ Less than 1 x 10 １１ cm −３ Less than or 1 x 10 １０ cm −３ The lower limit of the carrier concentration in the channel formation region is not particularly limited, but is preferably less than 1×10 −９ cm −３ It can be said that:

[0510] As described in the above embodiment, in an OS transistor, V ＯThe presence of impurities can cause fluctuations in electrical characteristics and reduce reliability. Therefore, reducing the impurity concentration in the oxide semiconductor is effective for stabilizing the electrical characteristics of an OS transistor. To reduce the impurity concentration in the oxide semiconductor, it is preferable to also reduce the impurity concentration in a nearby film. Examples of impurities include hydrogen, carbon, and nitrogen.

[0511] When an oxide semiconductor contains silicon or carbon, which is one of the Group 14 elements, defect levels are formed in the oxide semiconductor. Therefore, the carbon concentration in the channel formation region of the oxide semiconductor obtained by SIMS is 1×10 ２０ atoms / cm ３ Below 5 × 10, preferably １９ atoms / cm ３ Less than or equal to 3×10, more preferably １９ atoms / cm ３ Less than 1×10, more preferably 1×10 １９ atoms / cm ３ Less than or equal to 3×10, more preferably １８ atoms / cm ３ More preferably, 1×10 １８ atoms / cm ３ The silicon concentration in the channel formation region of the oxide semiconductor obtained by SIMS is 1×10 ２０ atoms / cm ３ Below 5 × 10, preferably １９ atoms / cm ３ Less than or equal to 3×10, more preferably １９ atoms / cm ３ or less, more preferably 1 × 10 １９ atoms / cm ３ Less than or equal to 3×10, more preferably １８ atoms / cm ３ More preferably, 1×10 １８ atoms / cm ３ The following applies.

[0512] Furthermore, when nitrogen is contained in an oxide semiconductor, electrons serving as carriers are generated, the carrier concentration increases, and the semiconductor is likely to become n-type. As a result, a transistor using an oxide semiconductor containing nitrogen as a semiconductor is likely to be normally on. Alternatively, when nitrogen is contained in an oxide semiconductor, trap states may be formed. As a result, the electrical characteristics of the transistor may become unstable. Therefore, the nitrogen concentration in the channel formation region of the oxide semiconductor obtained by SIMS is 1×10 ２０ atoms / cm ３ Below 5 × 10, preferably １９ atoms / cm ３ or less, more preferably 1 × 10 １９ atoms / cm ３ Less than or equal to 5×10, more preferably １８ atoms / cm ３ or less, more preferably 1 × 10 １８ atoms / cm ３ or less, more preferably 5 × 10 １７ atoms / cm ３ The following applies.

[0513] Furthermore, hydrogen contained in an oxide semiconductor reacts with oxygen bonded to a metal atom to form water, which may form an oxygen vacancy. Hydrogen entering the oxygen vacancy may generate electrons as carriers. Furthermore, some of the hydrogen may bond with oxygen bonded to a metal atom to generate electrons as carriers. Therefore, a transistor using an oxide semiconductor containing hydrogen is likely to be normally on. Therefore, it is preferable to reduce hydrogen as much as possible in the channel formation region of the oxide semiconductor. Specifically, the hydrogen concentration in the channel formation region of the oxide semiconductor obtained by SIMS is 1×10 ２０ atoms / cm ３ Less than 5×10 １９ atoms / cm ３ less than 1×10 １９ atoms / cm ３ less than 5×10 １８ atoms / cm ３ less than 1×10１８ atoms / cm ３ less than 1×10 １７ atoms / cm ３ Note that the lower limit of the hydrogen concentration in the channel formation region of the oxide semiconductor is not particularly limited, but is, for example, less than 1×10 １６ atoms / cm ３ It can be more than that.

[0514] Furthermore, when an oxide semiconductor contains an alkali metal or an alkaline earth metal, defect levels may be formed and carriers may be generated. Therefore, a transistor using an oxide semiconductor containing an alkali metal or an alkaline earth metal is likely to be normally on. Therefore, when the concentration of the alkali metal or the alkaline earth metal in the channel formation region of the oxide semiconductor obtained by SIMS is set to 1×10 １８ atoms / cm ３ Below 2 × 10, preferably １６ atoms / cm ３ Do the following:

[0515] When an oxide semiconductor with sufficiently reduced impurities is used for a channel formation region of a transistor, stable electrical characteristics can be obtained.

[0516] For an oxide semiconductor layer that can be used as a semiconductor layer of a transistor according to one embodiment of the present invention, the description in Embodiment 1 can be referred to.

[0517] [Insulating Layer] It is preferable to use an inorganic insulating film for each of the insulating layers (insulating layer 210, insulating layer 212, insulating layer 214, insulating layer 221, insulating layer 222, insulating layer 224, insulating layer 225, insulating layer 241a, insulating layer 241b, insulating layer 250, insulating layer 254, insulating layer 275, insulating layer 280, insulating layer 281, insulating layer 282, insulating layer 283, insulating layer 284, insulating layer 285, etc.) included in the semiconductor device. Examples of the inorganic insulating film include an oxide insulating film, a nitride insulating film, an oxynitride insulating film, and a nitride oxide insulating film. Examples of the oxide insulating film include a silicon oxide film, an aluminum oxide film, a magnesium oxide film, a gallium oxide film, a germanium oxide film, an yttrium oxide film, a zirconium oxide film, a lanthanum oxide film, a neodymium oxide film, a hafnium oxide film, a tantalum oxide film, a cerium oxide film, a gallium zinc oxide film, and a hafnium aluminate film. Examples of nitride insulating films include silicon nitride films and aluminum nitride films. Examples of oxynitride insulating films include silicon oxynitride films, aluminum oxynitride films, gallium oxynitride films, yttrium oxynitride films, and hafnium oxynitride films. Examples of nitride oxide insulating films include silicon nitride oxide films and aluminum nitride oxide films. An organic insulating film may also be used for an insulating layer included in a semiconductor device.

[0518] For example, as transistors become more miniaturized and highly integrated, problems such as leakage current may occur due to thinner gate insulating layers. Using a high-k material for the gate insulating layer allows for lower voltage during transistor operation while maintaining the physical film thickness. It also allows for thinner EOT of the gate insulating layer. Meanwhile, using a material with a low dielectric constant for the insulating layer that functions as an interlayer film can reduce the parasitic capacitance that occurs between wiring. Therefore, it is preferable to select materials according to the function of the insulating layer. Note that materials with a low dielectric constant also have high dielectric strength.

[0519] Examples of high-k materials include aluminum oxide, gallium oxide, hafnium oxide, tantalum oxide, zirconium oxide, hafnium zirconium oxide, oxides having aluminum and hafnium, oxynitrides having aluminum and hafnium, oxides having silicon and hafnium, oxynitrides having silicon and hafnium, and nitrides having silicon and hafnium.

[0520] Examples of materials with a low dielectric constant include inorganic insulating materials such as silicon oxide, silicon oxynitride, and silicon nitride oxide, and resins such as polyester, polyolefin, polyamide (nylon, aramid, etc.), polyimide, polycarbonate, and acrylic resin. Other inorganic insulating materials with a low dielectric constant include silicon oxide containing fluorine, silicon oxide containing carbon, and silicon oxide containing carbon and nitrogen. Another example is silicon oxide having vacancies. These silicon oxides may contain nitrogen.

[0521] Furthermore, a material capable of exhibiting ferroelectricity may be used for the insulating layer of a semiconductor device. Examples of materials capable of exhibiting ferroelectricity include metal oxides such as hafnium oxide, zirconium oxide, and hafnium zirconium oxide. Examples of materials capable of exhibiting ferroelectricity include a material obtained by adding element J1 (here, element J1 is one or more selected from zirconium, silicon, aluminum, gadolinium, yttrium, lanthanum, strontium, etc.) to hafnium oxide. Here, the ratio of the number of hafnium atoms to the number of element J1 atoms can be appropriately set; for example, the ratio of the number of hafnium atoms to the number of element J1 atoms can be set to 1:1 or close to 1:1. Examples of materials capable of exhibiting ferroelectricity include a material obtained by adding element J2 (here, element J2 is one or more selected from hafnium, silicon, aluminum, gadolinium, yttrium, lanthanum, strontium, etc.) to zirconium oxide. The ratio of the number of zirconium atoms to the number of atoms of element J2 can be set appropriately, for example, the ratio of the number of zirconium atoms to the number of atoms of element J2 can be set to 1:1 or close to 1:1. Furthermore, as a material that can have ferroelectricity, lead titanate (PbTiO Ｘ Piezoelectric ceramics having a perovskite structure, such as barium strontium titanate (BST), strontium titanate, lead zirconate titanate (PZT), strontium bismuth tantalate (SBT), bismuth ferrite (BFO), or barium titanate, may also be used.

[0522] Furthermore, examples of materials that may exhibit ferroelectricity include metal nitrides containing elements M1, M2, and nitrogen. Here, element M1 is one or more selected from aluminum, gallium, indium, etc. Furthermore, element M2 is one or more selected from boron, scandium, yttrium, lanthanum, cerium, neodymium, europium, titanium, zirconium, hafnium, vanadium, niobium, tantalum, chromium, etc. The ratio of the number of atoms of element M1 to the number of atoms of element M2 can be set as appropriate. Furthermore, metal oxides containing element M1 and nitrogen may exhibit ferroelectricity even without containing element M2. Furthermore, examples of materials that may exhibit ferroelectricity include materials in which element M3 is added to the above-mentioned metal nitrides. Furthermore, element M3 is one or more selected from magnesium, calcium, strontium, zinc, cadmium, etc. Here, the ratio of the number of atoms of the element M1, the number of atoms of the element M2, and the number of atoms of the element M3 can be set appropriately.

[0523] Furthermore, materials that can have ferroelectricity include SrTaO ２ N and BaTaO ２ Perovskite-type oxynitrides such as N, GaFeO with κ-alumina structure ３ Examples include:

[0524] In the above description, metal oxides and metal nitrides are used as examples, but the present invention is not limited to these. For example, metal oxynitrides in which nitrogen is added to the aforementioned metal oxides, or metal oxynitrides in which oxygen is added to the aforementioned metal nitrides, may also be used.

[0525] Furthermore, as a material capable of exhibiting ferroelectricity, for example, a mixture or compound made of a plurality of materials selected from the materials listed above can be used. Alternatively, the insulating layer 130 described in the third embodiment can have a layered structure made of a plurality of materials selected from the materials listed above. However, since the crystal structure (characteristics) of the materials listed above may change depending not only on the film formation conditions but also on various processes, in this specification and the like, a material that exhibits ferroelectricity is referred to not only as a ferroelectric but also as a material capable of exhibiting ferroelectricity.

[0526] In this specification, a layer of a material that can have ferroelectricity may be referred to as a ferroelectric layer, a metal oxide film, or a metal nitride film. Also, in this specification, a device having such a ferroelectric layer, a metal oxide film, or a metal nitride film may be referred to as a ferroelectric device.

[0527] Ferroelectricity is believed to be manifested by the displacement of oxygen or nitrogen in crystals contained in the ferroelectric layer due to an external electric field. Furthermore, it is believed that the manifestation of ferroelectricity depends on the crystalline structure of the crystals contained in the ferroelectric layer. Therefore, for the insulating layer to exhibit ferroelectricity, the insulating layer 130 must contain crystals. In particular, it is preferable for the insulating layer to contain crystals having an orthorhombic crystalline structure, as this will result in the manifestation of ferroelectricity. The crystalline structure of the crystals contained in the insulating layer may be one or more selected from the group consisting of tetragonal, orthorhombic, monoclinic, and hexagonal. The insulating layer may also have an amorphous structure. In this case, the insulating layer may have a composite structure having an amorphous structure and a crystalline structure.

[0528] A metal oxide containing one or both of hafnium and zirconium is also an insulating material that has the function of capturing or fixing hydrogen. Therefore, by using a metal oxide containing one or both of hafnium and zirconium for at least a part of a gate insulating layer, hydrogen contained in the oxide semiconductor layer can be captured or fixed, thereby reducing the hydrogen concentration in the oxide semiconductor layer. Furthermore, a transistor having the gate insulating layer can function as a ferroelectric field effect transistor (FeFET).

[0529] Furthermore, adding a Group 3 element in the periodic table to an oxide containing one or both of hafnium and zirconium increases the oxygen vacancy concentration in the oxide, making it easier to form crystals with an orthorhombic crystal structure. This is preferable because it increases the proportion of crystals with an orthorhombic crystal structure and increases the remanent polarization. On the other hand, adding too much of the Group 3 element may reduce the crystallinity of the oxide, making it difficult to exhibit ferroelectricity. Therefore, the content of the Group 3 element in the oxide containing one or both of hafnium and zirconium is preferably 0.1 atomic% to 10 atomic%, more preferably 0.1 atomic% to 5 atomic%, and even more preferably 0.1 atomic% to 3 atomic%. Here, the content of the Group 3 element refers to the ratio of the number of atoms of the Group 3 element to the sum of the number of atoms of all metal elements contained in the layer. The Group 3 element is preferably one or more selected from scandium, lanthanum, and yttrium, and more preferably one or both of lanthanum and yttrium.

[0530] Furthermore, a transistor using a metal oxide can have stable electrical characteristics by being surrounded by an insulating layer that has a function of suppressing the permeation of impurities and oxygen. The insulating layer that has a function of suppressing the permeation of impurities and oxygen can be, for example, a single-layer or stacked insulating layer containing one or more elements selected from boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium, and tantalum. Specifically, the insulating layer that has a function of suppressing the permeation of impurities and oxygen can be made of a metal oxide such as aluminum oxide, magnesium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, or tantalum oxide; a nitride such as aluminum nitride or silicon nitride; or a nitride oxide such as silicon nitride oxide.

[0531] Specifically, examples of materials for the insulating layer that have the function of suppressing the permeation of impurities such as water and hydrogen, and oxygen, include metal oxides such as aluminum oxide, magnesium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, tantalum oxide, and oxides containing aluminum and hafnium (hafnium aluminate). Examples of nitrides include aluminum nitride, aluminum titanium nitride, and silicon nitride. Examples of nitride oxides include silicon nitride oxide. Examples of materials for the insulating layer that have the function of suppressing the permeation of oxygen include gallium oxide.

[0532] An insulating layer, such as a gate insulating layer, which is in contact with an oxide semiconductor layer or is provided near the oxide semiconductor layer preferably has a region containing excess oxygen. For example, when an insulating layer having a region containing excess oxygen is in contact with an oxide semiconductor layer or is located near the oxide semiconductor layer, oxygen vacancies in the oxide semiconductor layer can be reduced. For an insulating layer in which a region containing excess oxygen is easily formed, the description in Embodiment 1 can be referred to.

[0533] An insulating layer provided in contact with or near an oxide semiconductor layer is preferably a barrier insulating layer against hydrogen. When the insulating layer has a barrier property against hydrogen, diffusion of hydrogen into the oxide semiconductor layer can be suppressed. The barrier insulating layer against hydrogen can also be said to have a function of suppressing diffusion of hydrogen.

[0534] Examples of insulating materials having the function of capturing or fixing hydrogen include metal oxides such as oxides containing hafnium, oxides containing magnesium, oxides containing aluminum, oxides containing aluminum and hafnium (hafnium aluminate), hafnium silicate, etc. These metal oxides may further contain zirconium, and examples thereof include oxides containing hafnium and zirconium.

[0535] An insulating layer having the function of capturing or fixing hydrogen preferably has an amorphous structure. In a metal oxide having an amorphous structure, some oxygen atoms have dangling bonds, which enhances the ability to capture or fix hydrogen. Therefore, when the insulating layer has an amorphous structure, the function of capturing or fixing hydrogen can be enhanced.

[0536] By making the insulating layer an amorphous structure, it is possible to suppress the formation of crystal grain boundaries. By suppressing the formation of crystal grain boundaries, it is possible to improve the flatness of the insulating layer. This makes it possible to uniformize the film thickness distribution of the insulating layer and reduce areas with extremely thin film thickness, thereby improving the breakdown voltage of the insulating layer. It is also possible to uniformize the film thickness distribution of a film provided on the insulating layer. Furthermore, by suppressing the formation of crystal grain boundaries in the insulating layer, it is possible to reduce leakage current caused by defect levels at the crystal grain boundaries. Therefore, the insulating layer can function as an insulating film with low leakage current.

[0537] The insulating layer may partially include either or both of a crystalline region and a grain boundary.

[0538] The ability to capture or fix a corresponding substance can also be said to have the property of making it difficult for the corresponding substance to diffuse. Therefore, the ability to capture or fix a corresponding substance can be rephrased as barrier properties.

[0539] In this specification and the like, a barrier insulating layer refers to an insulating layer having barrier properties. The barrier properties are also referred to as a property that makes it difficult for a corresponding substance to diffuse (a property that makes it difficult for a corresponding substance to permeate, a property that the permeability of a corresponding substance is low, or a function that suppresses the diffusion of a corresponding substance). Note that hydrogen when described as a corresponding substance includes, for example, a hydrogen atom, a hydrogen molecule, a water molecule, and OH. − Furthermore, unless otherwise specified, impurities when described as corresponding substances refer to impurities in the channel formation region or semiconductor layer, and include, for example, hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, and nitrogen oxide molecules (N ２ O, NO, and NO２ The term "oxygen" when used in reference to a corresponding substance refers to at least one of an oxygen atom, an oxygen molecule, and the like.

[0540] Examples of materials for the barrier insulating layer against hydrogen include aluminum oxide, magnesium oxide, hafnium oxide, zirconium oxide, oxides containing aluminum and hafnium (hafnium aluminate), oxides containing hafnium and zirconium (hafnium zirconium oxide), silicon nitride, and silicon nitride oxide.

[0541] The inorganic insulating layers cited as insulating layers having the function of capturing or fixing hydrogen and insulating layers having the function of suppressing hydrogen diffusion also have barrier properties against oxygen. Examples of materials for oxygen barrier insulating layers include oxides containing one or both of aluminum and hafnium, magnesium oxide, gallium zinc oxide, silicon nitride, and silicon nitride oxide. Examples of oxides containing one or both of aluminum and hafnium include aluminum oxide, hafnium oxide, oxides containing aluminum and hafnium (hafnium aluminate), and hafnium silicate.

[0542] [Conductive Layer] For the conductive layers (conductive layer 205, conductive layer 220, conductive layer 240, conductive layer 242a, conductive layer 242b, conductive layer 243a, conductive layer 243b, conductive layer 246, conductive layer 255, conductive layer 260, conductive layer 265, etc.) included in the semiconductor device, it is preferable to use a metal element selected from aluminum, chromium, copper, silver, gold, platinum, zinc, tantalum, nickel, titanium, iron, cobalt, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, lanthanum, etc., or an alloy containing any of the above metal elements as a component, or an alloy combining any of the above metal elements, etc. As the alloy containing any of the above metal elements as a component, a nitride of the alloy or an oxide of the alloy may be used. For example, it is preferable to use tantalum nitride, titanium nitride, nitride containing titanium and aluminum, nitride containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxide containing strontium and ruthenium, oxide containing lanthanum and nickel, etc. Furthermore, semiconductors with high electrical conductivity, typified by polycrystalline silicon containing impurity elements such as phosphorus, and silicides such as nickel silicide may also be used.

[0543] Nitrogen-containing conductive materials, such as nitrides containing tantalum, nitrides containing titanium, nitrides containing molybdenum, nitrides containing tungsten, nitrides containing ruthenium, nitrides containing tantalum and aluminum, or nitrides containing titanium and aluminum; oxygen-containing conductive materials, such as ruthenium oxide, oxides containing strontium and ruthenium, or oxides containing lanthanum and nickel; and materials containing metal elements, such as titanium, tantalum, or ruthenium, are preferred because they are conductive materials that are resistant to oxidation, have a function of suppressing oxygen diffusion, or maintain conductivity even after absorbing oxygen. Examples of oxygen-containing conductive materials include indium oxide containing tungsten oxide, indium oxide containing titanium oxide, ITO, indium tin oxide containing titanium oxide, ITSO, In—Zn oxide, and indium zinc oxide containing tungsten oxide. In this specification and the like, a conductive film formed using a conductive material containing oxygen may be referred to as an oxide conductive film.

[0544] Conductive materials containing tungsten, copper, or aluminum as a main component are preferred because they have high conductivity.

[0545] Furthermore, a plurality of conductive layers formed from the above materials may be stacked. For example, a stacked structure may be formed by combining the above-described material containing a metal element and a conductive material containing oxygen. A stacked structure may be formed by combining the above-described material containing a metal element and a conductive material containing nitrogen. A stacked structure may be formed by combining the above-described material containing a metal element, a conductive material containing oxygen, and a conductive material containing nitrogen.

[0546] When a metal oxide is used for the channel formation region of a transistor, the conductive layer that functions as a gate electrode preferably has a stacked structure that combines a material containing the metal element and a conductive material containing oxygen. In this case, the conductive material containing oxygen is preferably provided on the channel formation region side. By providing the conductive material containing oxygen on the channel formation region side, oxygen desorbed from the conductive material is easily supplied to the channel formation region.

[0547] [Substrate] Substrates on which transistors are formed can include, for example, insulating substrates, semiconductor substrates, or conductive substrates. Examples of insulating substrates include glass substrates, quartz substrates, sapphire substrates, stabilized zirconia substrates (such as yttria-stabilized zirconia substrates), and resin substrates. Examples of semiconductor substrates include semiconductor substrates made of silicon or germanium, or compound semiconductor substrates made of silicon carbide, silicon germanium, gallium arsenide, indium phosphide, zinc oxide, or gallium oxide. Examples of semiconductor substrates include those having an insulating region within the semiconductor substrate, such as an SOI (Silicon-On-Insulator) substrate. Examples of conductive substrates include graphite substrates, metal substrates, alloy substrates, and conductive resin substrates. Examples of substrates include substrates having a metal nitride or a metal oxide. Examples of substrates include substrates having a conductor or semiconductor provided on an insulating substrate, substrates having a conductor or insulator provided on a semiconductor substrate, and substrates having a semiconductor or insulator provided on a conductive substrate. Alternatively, a substrate provided with elements may be used, such as a capacitor element, a resistor element, a switch element, a light-emitting element, or a memory element.

[0548] The above is the description of the materials that can be used for the semiconductor device of this embodiment mode.

[0549] This embodiment mode can be combined with other embodiment modes or examples as appropriate. In addition, in this specification, when a plurality of configuration examples are shown in one embodiment mode, the configuration examples can be combined as appropriate.

[0550] 33A to 39. The memory device of one embodiment of the present invention includes a memory cell. The memory cell includes a transistor and a capacitor.

[0551] <Configuration Example 1 of Memory Device> The configuration of a memory device including a transistor and a capacitor will be described with reference to Figures 33A to 33C. Figure 33A is a plan view of a memory device including a transistor 200 and a capacitor 100. Figure 33B is a cross-sectional view taken along dashed line A1-A2 in Figure 33A. Figure 33C is a cross-sectional view taken along dashed line A3-A4 in Figure 33A.

[0552] 33A to 33C includes an insulating layer 140 over a substrate (not shown), a conductive layer 110 over the insulating layer 140, a memory cell 150 over the conductive layer 110, an insulating layer 180 over the conductive layer 110, and an insulating layer 280. The insulating layer 140 and the insulating layer 180 function as interlayer films. The conductive layer 110 functions as wiring.

[0553] The memory cell 150 includes a capacitor 100 over a conductive layer 110 and a transistor 200 over the capacitor 100 .

[0554] The capacitor 100 includes a conductive layer 115 over the conductive layer 110, an insulating layer 130 over the conductive layer 115, and a conductive layer 220_1 over the insulating layer 130. The conductive layer 220_1 functions as one of a pair of electrodes (sometimes referred to as an upper electrode), the conductive layer 115 functions as the other of the pair of electrodes (sometimes referred to as a lower electrode), and the insulating layer 130 functions as a dielectric. That is, the capacitor 100 forms a metal-insulator-metal (MIM) capacitor. Note that the conductive layer 220_2 provided over the conductive layer 220_1 can also be considered as part of the upper electrode of the capacitor 100.

[0555] As shown in FIGS. 33B and 33C , an opening 190 reaching the conductive layer 110 is provided in the insulating layer 180. At least a portion of the conductive layer 115 is disposed in the opening 190. Note that the conductive layer 115 has a region in contact with the top surface of the conductive layer 110 in the opening 190, a region in contact with the side surface of the insulating layer 180 in the opening 190, and a region in contact with at least a portion of the top surface of the insulating layer 180. At least a portion of the insulating layer 130 is disposed so as to be located in the opening 190. At least a portion of the conductive layer 220_1 is disposed so as to be located in the opening 190. Note that, as shown in FIGS. 33B and 33C , the conductive layer 220_1 is preferably provided so as to fill the opening 190. Note that the films provided inside the openings 190 are preferably formed using an ALD method. This improves the coverage of the films. For example, the conductive layer 115, the insulating layer 130, and the conductive layer 220_1 are preferably formed by an ALD method.

[0556] The capacitor 100 has a configuration in which the upper electrode and the lower electrode face each other with a dielectric sandwiched between them on the side surfaces as well as the bottom surface within the opening 190, allowing for a larger capacitance per unit area. Therefore, the deeper the opening 190, the larger the capacitance of the capacitor 100 can be. Increasing the capacitance per unit area of ​​the capacitor 100 in this way can stabilize the read operation of the memory device. Furthermore, this can promote miniaturization or high integration of memory devices.

[0557] 33B and 33C show an example in which the sidewall of opening 190 is perpendicular to the top surface of conductive layer 110 and opening 190 is circular in plan view. With such a configuration, miniaturization or high integration of the memory device can be achieved.

[0558] A conductive layer 115 and an insulating layer 130 are stacked along the sidewall of the opening 190 and the top surface of the conductive layer 110. In addition, a conductive layer 220_1 is provided on the insulating layer 130 so as to fill the opening 190. The capacitor 100 having such a configuration may be called a trench capacitor.

[0559] In addition, an insulating layer 280 is disposed over the capacitor 100. The insulating layer 280 has a portion located over the insulating layer 130 and a portion located over the conductive layer 220_2.

[0560] The transistor 200 includes a conductive layer 220 including a conductive layer 220_1 and a conductive layer 220_2, a conductive layer 240, an oxide semiconductor layer 230, an insulating layer 250, and a conductive layer 260.

[0561] The transistor 200 can be described in detail in Embodiment 2 (transistor 200A shown in FIG. 4A ), and therefore detailed description thereof will be omitted. The transistor included in the memory cell 150 is not limited to the transistor 200A, and any of the transistors exemplified in Embodiment 2 can be applied. A transistor having a planar structure, a gate all around (GAA) structure, or a lateral gate all around (LGAA) structure can also be applied.

[0562] As shown in FIGS. 33A to 33C , the transistor 200 is provided so as to overlap with the capacitor 100. Furthermore, an opening 290 in which part of the structure of the transistor 200 is provided overlaps with an opening 190 in which part of the structure of the capacitor 100 is provided. In particular, the conductive layer 220 functions as one of the source electrode and drain electrode of the transistor 200 and as the upper electrode of the capacitor 100. Therefore, the transistor 200 and the capacitor 100 share part of their structures. With this structure, the transistor 200 and the capacitor 100 can be provided without significantly increasing the occupied area in a plan view. This reduces the occupied area of ​​the memory cell 150, thereby enabling the memory cells 150 to be densely arranged and increasing the storage capacity of the memory device. In other words, the memory device can be highly integrated. FIGS. 33B and 33C show an example in which the width of the opening 190 is smaller than the width of the opening 290. The relationship between the width of the opening 190 and the width of the opening 290 is not particularly limited. From the viewpoint of miniaturization, it is preferable that the widt...

Claims

A semiconductor device having an oxide semiconductor layer, the oxide semiconductor layer includes an indium oxide film, the indium oxide film has a channel formation region of a transistor, the indium oxide film has crystal grains, No grain boundaries are observed in the channel formation region, the concentration of the first element in the channel formation region is 0.1 atomic % or less; The semiconductor device, wherein the first element is at least one of boron, aluminum, and gallium. 　 A semiconductor device having an oxide semiconductor layer, the oxide semiconductor layer includes an indium oxide film, the indium oxide film has a channel formation region of a transistor, the indium oxide film in the channel formation region is single crystal; the concentration of the first element in the channel formation region is 0.1 atomic % or less; The semiconductor device, wherein the first element is at least one of boron, aluminum, and gallium. 　 A semiconductor device having an oxide semiconductor layer, the oxide semiconductor layer includes an indium oxide film, the indium oxide film has a channel formation region of a transistor, the indium oxide film has first crystal grains and second crystal grains in the channel formation region, the crystal orientation of the first crystal grains and the crystal orientation of the second crystal grains are identical or substantially identical; the concentration of the first element in the channel formation region is 0.1 atomic % or less; The semiconductor device, wherein the first element is at least one of boron, aluminum, and gallium. 　 In any one of claims 1 to 3, The semiconductor device, wherein the band gap of the indium oxide film is 2.5 eV or more and 3.7 eV or less. 　 In any one of claims 1 to 3, The indium oxide film has a region having a film thickness of 5 nm or more and 10 nm or less. 　 In any one of claims 1 to 3, The semiconductor device, wherein the indium oxide film is a film formed by atomic layer deposition. 　 In any one of claims 1 to 3, The off-state current of the transistor is 1×10 per 1 μm of channel width at 85° C. −１８ A semiconductor device having a resistivity of less than A / μm. 　 In any one of claims 1 to 3, The semiconductor device, wherein the transistor has a cutoff frequency of 100 GHz or higher under room temperature conditions. 　 In any one of claims 1 to 3, The semiconductor device, wherein the indium oxide film is provided on an oxide film having cubic crystal grains. 　 In claim 9, The semiconductor device, wherein a lattice mismatch between the crystal grains of the indium oxide film and the crystal grains of the oxide film is 0% or more and 10% or less. 　 In claim 9, The semiconductor device, wherein the oxide film contains yttrium, zirconium, and oxygen. 　 In claim 11, The semiconductor device, wherein the oxide film is a film formed by a sputtering method. In claim 9, The semiconductor device, wherein the oxide film has a thickness smaller than that of the indium oxide film. 　 In any one of claims 1 to 3, the oxide semiconductor layer has an In—Ga—Zn oxide film on the indium oxide film, The indium oxide film has higher permeability to either or both of oxygen atoms and hydrogen atoms than the In-Ga-Zn oxide film. 　 an oxide semiconductor layer; a conductive layer; an insulating layer having a portion located between the oxide semiconductor layer and the conductive layer; and the conductive layer has a region that functions as a gate electrode of a transistor; the insulating layer has a region that functions as a gate insulating layer of the transistor; the oxide semiconductor layer includes an indium oxide film, the indium oxide film has crystal grains, A semiconductor device, wherein no grain boundaries are observed in a region of the indium oxide film that overlaps the conductive layer and is at a depth of 1 nm or less from the surface on the insulating layer side. 　 an oxide semiconductor layer; a conductive layer; an insulating layer having a portion located between the oxide semiconductor layer and the conductive layer; and the conductive layer has a region that functions as a gate electrode of a transistor; the insulating layer has a region that functions as a gate insulating layer of the transistor; the oxide semiconductor layer includes an indium oxide film, the indium oxide film overlaps the conductive layer and has first crystal grains and second crystal grains in a region at a depth of 1 nm or less from a surface on the insulating layer side; A semiconductor device, wherein the crystal orientation of the first crystal grains and the crystal orientation of the second crystal grains are the same or approximately the same. 　 In claim 15 or claim 16, an oxide film overlapping the insulating layer with the oxide semiconductor layer sandwiched therebetween; The semiconductor device, wherein the oxide film has cubic crystal grains. 　 In claim 17, The semiconductor device, wherein a lattice mismatch between the crystal grains of the indium oxide film and the crystal grains of the oxide film is 0% or more and 10% or less. 　 In claim 17, The semiconductor device, wherein the oxide film contains yttrium, zirconium, and oxygen. 　 In claim 17, The semiconductor device, wherein the oxide film has a thickness smaller than that of the indium oxide film.

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