Method for producing semiconductor device

Abstract

Provided is a highly reliable semiconductor device. According to the present invention, a groove is formed in an interlayer film after the formation of the interlayer film. A semiconductor film is formed so as to have a region that extends along the side wall of the groove. A process that includes a dry etching process for removing a part of the semiconductor film which includes the region that extends along the side wall of the groove and a product removal process for removing a product that is generated by the dry etching process is performed a plurality of times. Consequently, a semiconductor layer which has a region that extends along the side wall of the groove is formed. A plurality of semiconductor layers are formed in the groove.

Description

Method for manufacturing a semiconductor device

[0001] 1. Field of the Invention One embodiment of the present invention relates to a semiconductor device, a memory device, and an electronic device. Another embodiment of the present invention relates to a manufacturing method of a semiconductor device.

[0002] One embodiment of the present invention is not limited to the above technical field, and examples of the technical field of one embodiment of the present invention include semiconductor devices, display devices, light-emitting devices, power storage devices, memory devices, electronic devices, lighting devices, input devices (e.g., touch sensors), input / output devices (e.g., touch panels), driving methods thereof, and manufacturing methods thereof.

[0003] In this specification and the like, a semiconductor device is a device that utilizes semiconductor characteristics, and refers to a circuit including a semiconductor element (transistor, diode, photodiode, etc.), a device having such a circuit, etc. Also, it refers to any device that can function by utilizing semiconductor characteristics. For example, an integrated circuit, a chip including an integrated circuit, and an electronic component in which a chip is housed in a package are examples of semiconductor devices. Furthermore, a memory device, a display device, a light-emitting device, a lighting device, and an electronic device may themselves be semiconductor devices and each may have a semiconductor device.

[0004] In recent years, the development of semiconductor devices has progressed, and semiconductor devices mainly use LSIs (Large Scale Integration), CPUs (Central Processing Units), memories (storage devices), etc. A CPU is an aggregate of semiconductor elements that have integrated circuits (including transistors and memories) formed into chips by processing a semiconductor wafer and on which electrodes serving as connection terminals are formed.

[0005] 2. Description of the Related Art Integrated circuits (ICs) such as LSIs, CPUs, and memories are mounted on circuit boards, such as printed wiring boards, and are used as components of various electronic devices.

[0006] Furthermore, a technology for constructing a transistor using a semiconductor thin film formed on a substrate having an insulating surface has attracted attention. Such transistors are widely used in electronic devices such as integrated circuits (ICs) and display devices. While silicon-based semiconductor materials are widely known as semiconductor materials applicable to transistors, metal oxides have also attracted attention as other materials.

[0007] Furthermore, it is known that transistors using metal oxides have extremely low leakage current in an off state. For example, Patent Document 1 discloses a low-power consumption CPU that utilizes the low leakage current characteristic of transistors using metal oxides. Furthermore, for example, Patent Document 2 discloses a memory device that can retain stored content for a long period of time by utilizing the low leakage current characteristic of transistors using metal oxides.

[0008] In recent years, with the trend toward smaller and lighter electronic devices, there has been an increasing demand for higher density integrated circuits. There is also a demand for improved productivity of semiconductor devices including integrated circuits. For example, Patent Document 3 and Non-Patent Document 1 disclose a technique for increasing the density of integrated circuits by stacking a first transistor using a metal oxide film and a second transistor using a metal oxide film to provide multiple overlapping memory cells. Patent Document 4 also discloses a technique for increasing the density of integrated circuits by vertically arranging the channels of transistors using a metal oxide film.

[0009] JP 2012-257187 A JP 2011-151383 A WO 2021 / 053473 JP 2013-211537 A

[0010] M. Oota et al. , “3D-Stacked CAAC-In-Ga-Zn Oxide FETs with Gate Length of 72nm”, IEDM Tech. Dig. , 2019, pp. 50-53

[0011] An object of one embodiment of the present invention is to provide a semiconductor device that can be miniaturized or highly integrated.An object of one embodiment of the present invention is to provide a highly reliable semiconductor device.An object of one embodiment of the present invention is to provide a semiconductor device that can be manufactured at low cost.An object of one embodiment of the present invention is to provide a semiconductor device with low power consumption.An object of one embodiment of the present invention is to provide a semiconductor device with high operating speed.An object of one embodiment of the present invention is to provide a semiconductor device including a transistor with favorable electrical characteristics.An object of one embodiment of the present invention is to provide a semiconductor device including a transistor with high on-state current.An object of one embodiment of the present invention is to provide a semiconductor device including a transistor with low parasitic capacitance.

[0012] An object of one embodiment of the present invention is to provide a method for manufacturing a semiconductor device that can be miniaturized or highly integrated.An object of one embodiment of the present invention is to provide a method for manufacturing a semiconductor device with high yield.An object of one embodiment of the present invention is to provide a method for manufacturing a semiconductor device at low cost.An object of one embodiment of the present invention is to provide a method for manufacturing a highly reliable semiconductor device.An object of one embodiment of the present invention is to provide a method for manufacturing a semiconductor device with low power consumption.An object of one embodiment of the present invention is to provide a method for manufacturing a semiconductor device with high operating speed.An object of one embodiment of the present invention is to provide a method for manufacturing a semiconductor device including a transistor with favorable electrical characteristics.An object of one embodiment of the present invention is to provide a method for manufacturing a semiconductor device including a transistor with high on-state current.An object of one embodiment of the present invention is to provide a method for manufacturing a semiconductor device including a transistor with low parasitic capacitance.

[0013] Note that the description of these problems does not preclude the existence of other problems. One embodiment of the present invention does not necessarily have to solve all of these problems. Problems other than these can be extracted from the description in the specification, drawings, and claims.

[0014] One embodiment of the present invention is a method for manufacturing a semiconductor device, which includes forming an insulating layer, forming a groove in the insulating layer, forming a semiconductor film to have a region along a sidewall of the groove, and performing a process including a dry etching process to remove part of the semiconductor film including the region along the sidewall of the groove, and a product removal process to remove a product generated by the dry etching process, multiple times to form a semiconductor layer having a region along the sidewall of the groove.

[0015] Another embodiment of the present invention is a method for manufacturing a semiconductor device, including: forming a first conductive layer, a first insulating layer over the first conductive layer, and a conductive film over the first insulating layer; forming a groove in the conductive film and the first insulating layer that reaches the first conductive layer; forming a semiconductor film to have a region along a sidewall of the groove, a region along a top surface of the first conductive layer in the groove, and a region located over the conductive film; forming a semiconductor film having a region along the sidewall of the groove by performing a dry etching treatment that removes part of the semiconductor film including the region along the sidewall of the groove and a product removal treatment for removing a product generated by the dry etching treatment multiple times; and processing the conductive film to form a second conductive layer and a third conductive layer that face each other across the groove in a plan view; forming a second insulating layer over the semiconductor layer to have a region located in the groove; and forming a fourth conductive layer on the second insulating layer to have a region located in the groove.

[0016] Alternatively, in the above aspect, a third insulating layer may be formed on the fourth conductive layer and the second insulating layer, a first opening reaching the second conductive layer and a second opening reaching the third conductive layer are formed in the third insulating layer, the second insulating layer, and the semiconductor layer, a fifth conductive layer is formed in the first opening so as to have a region in contact with the second conductive layer, and a sixth conductive layer is formed in the second opening so as to have a region in contact with the third conductive layer, and a seventh conductive layer is formed so as to have a region in contact with the fifth conductive layer, a region in contact with the sixth conductive layer, and a region located on the third insulating layer.

[0017] Alternatively, in the above aspect, the groove portion may be formed to extend in a first direction in a planar view, and the seventh conductive layer may be formed to extend in a second direction in a planar view, and the second direction may be perpendicular or approximately perpendicular to the first direction.

[0018] Alternatively, in the above aspect, the product removal treatment may include plasma treatment.

[0019] Alternatively, in the above embodiment, the plasma treatment may be carried out in an atmosphere containing one or both of oxygen gas and inert gas.

[0020] Alternatively, in the above embodiment, the product may include carbon.

[0021] Alternatively, in the above embodiment, the dry etching process may be performed using a gas containing carbon.

[0022] Alternatively, in the above embodiment, after forming the semiconductor film, a mask containing carbon may be formed on the semiconductor film, and after forming the mask, dry etching treatment may be performed.

[0023] Alternatively, in the above embodiment, the semiconductor film may contain a metal oxide, and the metal oxide may contain indium.

[0024] According to one embodiment of the present invention, a semiconductor device that can be miniaturized or highly integrated can be provided. According to one embodiment of the present invention, a highly reliable semiconductor device can be provided. According to one embodiment of the present invention, a semiconductor device that can be manufactured at low cost can be provided. According to one embodiment of the present invention, a semiconductor device with low power consumption can be provided. According to one embodiment of the present invention, a semiconductor device with high operating speed can be provided. According to one embodiment of the present invention, a semiconductor device including a transistor with favorable electrical characteristics can be provided. According to one embodiment of the present invention, a semiconductor device including a transistor with high on-state current can be provided. According to one embodiment of the present invention, a semiconductor device including a transistor with low parasitic capacitance can be provided.

[0025] According to one embodiment of the present invention, a method for manufacturing a semiconductor device that can be miniaturized or highly integrated can be provided. According to one embodiment of the present invention, a method for manufacturing a semiconductor device with high yield can be provided. According to one embodiment of the present invention, a method for manufacturing a semiconductor device at low cost can be provided. According to one embodiment of the present invention, a method for manufacturing a highly reliable semiconductor device can be provided. According to one embodiment of the present invention, a method for manufacturing a semiconductor device with low power consumption can be provided. According to one embodiment of the present invention, a method for manufacturing a semiconductor device with high operating speed can be provided. According to one embodiment of the present invention, a method for manufacturing a semiconductor device including a transistor with favorable electrical characteristics can be provided. According to one embodiment of the present invention, a method for manufacturing a semiconductor device including a transistor with high on-state current can be provided. According to one embodiment of the present invention, a method for manufacturing a semiconductor device including a transistor with low parasitic capacitance can be provided.

[0026] Note that the description of these effects does not preclude the existence of other effects. One embodiment of the present invention does not necessarily have all of these effects. Effects other than these can be extracted from the description in the specification, drawings, and claims.

[0027] FIGS. 1A1 and 1A2 are plan views illustrating an example of a semiconductor device. FIGS. 1B to 1E are cross-sectional views illustrating an example of a semiconductor device. FIGS. 2A to 2C are perspective views illustrating an example of a semiconductor device. FIGS. 3A and 3B are cross-sectional views illustrating an example of a semiconductor device. FIG. 4A is a plan view illustrating an example of a method for manufacturing a semiconductor device. FIGS. 4B to 4E are cross-sectional views illustrating an example of a method for manufacturing a semiconductor device. FIG. 5A is a plan view illustrating an example of a method for manufacturing a semiconductor device. FIGS. 5B to 5E are cross-sectional views illustrating an example of a method for manufacturing a semiconductor device. FIG. 6A is a plan view illustrating an example of a method for manufacturing a semiconductor device. FIGS. 6B to 6E are cross-sectional views illustrating an example of a method for manufacturing a semiconductor device. FIG. 7A is a plan view illustrating an example of a method for manufacturing a semiconductor device. FIGS. 7B to 7E are cross-sectional views illustrating an example of a method for manufacturing a semiconductor device. FIGS. 8A to 8D are cross-sectional views illustrating an example of a method for manufacturing a semiconductor device. FIG. 9A is a plan view illustrating an example of a method for manufacturing a semiconductor device. FIGS. 9B to 9E are cross-sectional views illustrating an example of a method for manufacturing a semiconductor device. FIG. 10A is a plan view illustrating an example of a method for manufacturing a semiconductor device. 10B to 10E are cross-sectional views illustrating an example of a manufacturing method of a semiconductor device. FIG. 11A is a plan view illustrating an example of a manufacturing method of a semiconductor device. FIGS. 11B to 11E are cross-sectional views illustrating an example of a manufacturing method of a semiconductor device. FIG. 12A is a plan view illustrating an example of a manufacturing method of a semiconductor device. FIGS. 12B to 12E are cross-sectional views illustrating an example of a manufacturing method of a semiconductor device. FIG. 13A is a plan view illustrating an example of a manufacturing method of a semiconductor device. FIGS. 13B to 13E are cross-sectional views illustrating an example of a manufacturing method of a semiconductor device. FIG. 14A is a plan view illustrating an example of a manufacturing method of a semiconductor device. FIGS. 14B to 14E are cross-sectional views illustrating an example of a manufacturing method of a semiconductor device. FIG. 15 is a cross-sectional view illustrating an example of a semiconductor device. FIGS. 16A to 16F are cross-sectional views illustrating an example of a semiconductor device. FIG. 17 is a cross-sectional view illustrating an example of a semiconductor device. FIGS. 18A and 18B are cross-sectional views illustrating an example of a semiconductor device. FIGS. 19A and 19B are cross-sectional views illustrating an example of a semiconductor device. FIGS. 20A1 and 20A2 are plan views illustrating an example of a semiconductor device. 20B to 20E are cross-sectional views showing an example of a semiconductor device.21A1 and 21A2 are plan views showing an example of a semiconductor device. FIGS. 21B to 21D are cross-sectional views showing an example of a semiconductor device. FIG. 22 is a cross-sectional view showing an example of a semiconductor device. FIG. 23A is a plan view showing an example of a semiconductor device. FIGS. 23B and 23C are cross-sectional views showing an example of a semiconductor device. FIG. 24A is a plan view showing an example of a semiconductor device. FIGS. 24B to 24E are cross-sectional views showing an example of a semiconductor device. FIG. 25A is a plan view showing an example of a semiconductor device. FIGS. 25B to 25D are cross-sectional views showing an example of a semiconductor device. FIG. 26 is a band diagram of an oxide semiconductor layer. FIGS. 27A1 and 27A2 are plan views showing an example of a memory device. FIGS. 27B and 27C are cross-sectional views showing an example of a memory device. FIG. 28A is a plan view showing an example of a memory device. FIG. 28B is a circuit diagram showing a configuration example of a memory cell. FIGS. 29A and 29B are cross-sectional views showing an example of a memory device. FIG. 30 is a cross-sectional view showing an example of a memory device. FIG. 31 is a cross-sectional view showing an example of a memory device. FIG. 32 is a cross-sectional view showing an example of a memory device. FIG. 33 is a graph showing an example of hysteresis characteristics. FIGS. 34A to 34C are equivalent circuit diagrams of a semiconductor device. FIG. 34D is a diagram illustrating the Id-Vg characteristics of a transistor. FIG. 35A is a timing chart illustrating the operation of a semiconductor device. FIG. 35B is a circuit diagram illustrating the operation of a semiconductor device. FIG. 36A is a timing chart illustrating the operation of a semiconductor device. FIG. 36B is a circuit diagram illustrating the operation of a semiconductor device. FIG. 37A is a timing chart illustrating the operation of a semiconductor device. FIG. 37B is a circuit diagram illustrating the operation of a semiconductor device. FIG. 38 is a block diagram illustrating a configuration example of a semiconductor device. FIGS. 39A to 39G are circuit diagrams illustrating a configuration example of a memory cell. FIGS. 40A and 40B are perspective views illustrating a configuration example of a semiconductor device. FIG. 41 is a block diagram illustrating a CPU. FIGS. 42A and 42B are perspective views of a semiconductor device. FIGS. 43A and 43B are perspective views of a semiconductor device. FIG. 44 is a conceptual diagram illustrating layers of a memory device. 45A and 45B are circuit diagrams of the semiconductor device.Fig. 45C is a diagram showing an example of an electronic component using a semiconductor device. Fig. 46 is a diagram showing an example of an electronic component. Figs. 47A to 47C are diagrams showing an example of a mainframe computer. Fig. 47D is a diagram showing an example of space equipment. Fig. 47E is a diagram showing an example of a storage system applicable to a data center. Figs. 48A to 48F are diagrams showing an example of electronic equipment. Figs. 49A to 49G are diagrams showing an example of electronic equipment. Figs. 50A to 50F are diagrams showing an example of electronic equipment.

[0028] The embodiments will be described in detail with reference to the drawings. However, the present invention is not limited to the following description, and it will be readily understood by those skilled in the art that various changes can be made in form and detail without departing from the spirit and scope of the present invention. Therefore, the present invention should not be interpreted as being limited to the description of the embodiments shown below.

[0029] In the configuration of the invention described below, the same parts or parts having similar functions are denoted by the same reference numerals in different drawings, and repeated explanations thereof will be omitted. Furthermore, when referring to similar functions, the same hatching pattern may be used and no particular reference numeral may be assigned.

[0030] Furthermore, for ease of understanding, the position, size, range, etc. of each component shown in the drawings may not represent the actual position, size, range, etc. Therefore, the disclosed invention is not necessarily limited to the position, size, range, etc. disclosed in the drawings.

[0031] In this specification, the ordinal numbers "first" and "second" are used for convenience and do not limit the number of components or the order of the components (for example, the order of processes or stacking order). Furthermore, the ordinal numbers assigned to components in one part of this specification may not match the ordinal numbers assigned to the same components in other parts of this specification or in the claims.

[0032] A transistor is a type of semiconductor element that can perform functions such as amplifying current or voltage and performing a switching operation to control conduction or non-conduction. The term "transistor" used in this specification includes an insulated gate field effect transistor (IGFET) and a thin film transistor (TFT).

[0033] In this specification and the like, a transistor using a metal oxide for a semiconductor layer and a transistor having a metal oxide for a channel formation region may be referred to as an OS (oxide semiconductor) transistor. A transistor having silicon for a channel formation region may be referred to as a Si transistor.

[0034] In this specification and the like, a transistor is an element having at least three terminals including a gate, a drain, and a source. A transistor has a region (also referred to as a channel formation region) where a channel is formed between the drain (drain terminal, drain region, or drain electrode) and the source (source terminal, source region, or source electrode), and current can flow between the source and the drain through the channel formation region. Note that in this specification and the like, the channel formation region refers to a region through which current mainly flows.

[0035] Furthermore, the functions of "source" and "drain" may be interchanged when transistors of different polarities are used, or when the direction of current flow changes during circuit operation, etc. Therefore, in this specification, the terms "source" and "drain" may be used interchangeably.

[0036] Note that impurities in a semiconductor refer to, for example, elements other than the main components that constitute the semiconductor. For example, an element with a concentration of less than 0.1 atomic % can be considered an impurity. The inclusion of impurities can, for example, increase the defect level density of the semiconductor or reduce the crystallinity. When the semiconductor is a metal oxide, impurities that change the characteristics of the semiconductor include, for example, Group 1 elements, Group 2 elements, Group 13 elements, Group 14 elements, Group 15 elements, and transition metals other than the main components of the metal oxide. Specific examples include hydrogen, lithium, sodium, silicon, boron, phosphorus, carbon, and nitrogen. Note that water can also function as an impurity. Furthermore, for example, the inclusion of impurities can cause oxygen deficiency (V) in the metal oxide. Ｏ In some cases, a nucleus (also referred to as a nucleus) may be formed.

[0037] In this specification and the like, an oxynitride refers to a material having a composition in which oxygen is contained in a larger amount than nitrogen, and a nitride oxide refers to a material having a composition in which nitrogen is contained in a larger amount than oxygen.

[0038] To analyze the content of elements such as hydrogen, oxygen, carbon, or nitrogen contained in a film, for example, secondary ion mass spectrometry (SIMS) or X-ray photoelectron spectroscopy (XPS) or electron spectroscopy for chemical analysis (ESCA) can be used. XPS is suitable when the content of the target element is high (e.g., 0.5 atomic% or more, or 1 atomic% or more). On the other hand, SIMS is suitable when the content of the target element is low (e.g., less than 0.5 atomic% or less than 1 atomic%). When comparing the content of elements, it is more preferable to perform a combined analysis using both SIMS and XPS analytical methods.

[0039] In this specification, the term "content" refers to the proportion of a component contained in a film. For example, if a metal oxide layer contains metal elements X, Y, and Z, and the number of atoms of each of metal elements X, Y, and Z contained in the metal oxide layer is A, then the number of atoms of each of metal elements X, Y, and Z is A. Ｘ , AＹ , A Ｚ When the content of the metal element X is Ｘ / (A Ｘ +A Ｙ +A Ｚ In addition, the ratio of the number of atoms of the metal element X, the metal element Y, and the metal element Z in the metal oxide layer (atomic ratio) can be expressed as follows: Ｘ : B Ｙ : B Ｚ When the content of the metal element X is expressed as B Ｘ / (B Ｘ +B Ｙ +B Ｚ ) The content of the metal element X in the metal oxide layer can be expressed as the content not taking into account oxygen, impurities, etc.

[0040] It should be noted that the terms "film" and "layer" can be interchangeable depending on the circumstances. For example, the term "conductive layer" can be changed to the term "conductive film." Or, for example, the term "insulating film" can be changed to the term "insulating layer."

[0041] Furthermore, in this specification, "parallel" refers to a state in which two straight lines are arranged at an angle of -10 degrees or more and 10 degrees or less. Therefore, it also includes cases where the angle is -5 degrees or more and 5 degrees or less. Furthermore, "substantially parallel" refers to a state in which two straight lines are arranged at an angle of -20 degrees or more and 20 degrees or less. Furthermore, "perpendicular" refers to a state in which two straight lines are arranged at an angle of 80 degrees or more and 100 degrees or less. Therefore, it also includes cases where the angle is 85 degrees or more and 95 degrees or less. Furthermore, "substantially perpendicular" refers to a state in which two straight lines are arranged at an angle of 70 degrees or more and 110 degrees or less.

[0042] In this specification, "connection" includes, as an example, "electrical connection." Note that the term "electrical connection" is sometimes used to define the connection relationship between circuit elements as an object. Furthermore, "electrical connection" includes "direct connection" and "indirect connection." "A and B are directly connected" means that A and B are connected without the intervention of a circuit element (e.g., a transistor, a switch, etc.; wiring is not considered a circuit element). On the other hand, "A and B are indirectly connected" means that A and B are connected via one or more circuit elements.

[0043] For example, assuming that a circuit including A and B is operating, if there is a time during the operation of the circuit when an electrical signal is exchanged or an interaction of electrical potential occurs between A and B, then it can be defined that "A and B are indirectly connected" as objects. Note that even if there is a time during the operation of the circuit when no electrical signal is exchanged or an interaction of electrical potential occurs between A and B, it can still be defined that "A and B are indirectly connected" as long as there is a time during the operation of the circuit when an electrical signal is exchanged or an interaction of electrical potential occurs between A and B.

[0044] An example of a case where "A and B are indirectly connected" is when A and B are connected via the source and drain of one or more transistors. On the other hand, an example of a case where it cannot be said that "A and B are indirectly connected" is when an insulator is present in the path from A to B. Specifically, there are cases where a capacitive element is connected between A and B, and cases where a gate insulating film of a transistor is present between A and B. Therefore, it cannot be said that "the gate (A) of a transistor and the source or drain (B) of the transistor are indirectly connected."

[0045] Another example of a case where it cannot be said that "A and B are indirectly connected" is when multiple transistors are connected via their sources and drains to the path from A to B, and a constant potential V is supplied to a node between one transistor and another transistor from a power supply, GND, etc.

[0046] In this specification and the like, unless otherwise specified, the off-state current refers to the leakage current between the source and the drain when the transistor is in an off state (also referred to as a non-conducting state or a cut-off state). Unless otherwise specified, the off-state current refers to the leakage current between the gate and the source when the transistor is in an n-channel transistor. ｇｓ is the threshold voltage V ｔｈ (For p-channel transistors, V ｔｈ This refers to a state of being (higher than)

[0047] In this specification, "normally on" refers to a state in which a channel exists and a current flows through a transistor even when no voltage is applied to the gate, and "normally off" refers to a state in which no current flows through a transistor when no potential is applied to the gate or when a ground potential is applied to the gate.

[0048] In this specification and the like, a tapered shape refers to a shape in which at least a portion of the side surface of a structure is inclined with respect to the substrate surface or the surface to be formed. For example, it is preferable to have a region in which the angle (also called the taper angle) between the inclined side surface and the substrate surface or the surface to be formed is greater than 0 degrees and less than 90 degrees. Note that the side surface of the structure, the substrate surface, and the surface to be formed do not necessarily need to be completely flat, and may be approximately planar with a slight curvature or approximately planar with a slight unevenness.

[0049] In this specification, when it is stated that A is located on B, at least a portion of A is located on B. Therefore, for example, it can be rephrased as "A has a region located on B." Similarly, when it is stated that A contacts B or A overlaps B, at least a portion of A contacts B or overlaps B. Therefore, it can be rephrased as "A has a region contacting B" or "A has a region overlapping B," respectively. Similarly, in this specification, when it is stated that A covers B, at least a portion of A covers B. Therefore, for example, it can be rephrased as "A has a region covering B."

[0050] In this specification and the like, a step disconnection refers to a phenomenon in which a layer, a film, or an electrode is separated due to the shape of the surface on which it is formed (for example, a step or the like).

[0051] In this specification and the like, the term "island-like" refers to a state in which two or more layers made of the same material and formed in the same process are physically separated.

[0052] In the drawings and the like relating to this specification, arrows indicating the X direction, Y direction, and Z direction may be used. In this specification and the like, the "X direction" refers to the direction along the X axis, and there may be no distinction between the forward direction and the reverse direction unless explicitly stated. The same applies to the "Y direction" and the "Z direction." Furthermore, the X direction, Y direction, and Z direction are directions that intersect with each other. For example, the X direction, Y direction, and Z direction are directions that are perpendicular to each other, i.e., vertical directions.

[0053] Embodiment 1 In this embodiment, a semiconductor device of one embodiment of the present invention and a manufacturing method thereof will be described with reference to drawings.

[0054] One embodiment of the present invention relates to a semiconductor device including a transistor in which a source electrode and a drain electrode are located at different heights, and a manufacturing method thereof. In the transistor included in the semiconductor device of one embodiment of the present invention, a source electrode, a semiconductor layer, and a drain electrode can be provided in a stacked manner. Therefore, the occupied area can be significantly reduced compared to a so-called planar transistor in which a semiconductor layer is arranged in a planar shape. Therefore, the semiconductor device can be miniaturized or highly integrated.

[0055] When manufacturing a semiconductor device according to one embodiment of the present invention, a first conductive layer that serves as one of a source electrode and a drain electrode of a transistor is first formed over a substrate, an interlayer film is formed over the first conductive layer, and a conductive film is then formed over the interlayer film. Subsequently, a groove that reaches the first conductive layer is formed in the conductive film and the interlayer film. The groove is formed to extend in a predetermined direction parallel to the substrate surface.

[0056] Next, a semiconductor film is formed, which has a region along the sidewall of the groove, a region along the top surface of the first conductive layer in the groove, and a region located on the conductive film. The semiconductor film is then processed to form a semiconductor layer. The semiconductor film can be processed using photolithography. Specifically, a mask is formed on the semiconductor film, and then the region of the semiconductor film that does not overlap with the mask is removed, thereby forming the semiconductor layer. An etching process can be used to remove the semiconductor film. In particular, dry etching is preferable because it allows for miniaturization or high integration of semiconductor devices compared to, for example, wet etching.

[0057] Here, to form a semiconductor layer having a region located within the groove, it is necessary to remove a portion of the semiconductor film in the region along the sidewall of the groove. However, when removing the region along the sidewall of the semiconductor film by dry etching, the dry etching process must be performed for a longer period of time than, for example, when removing only the region along the top surface of the first conductive layer and the region located on the conductive film. As a result, for example, products resulting from the etching gas may deposit on the surface of the semiconductor film. Furthermore, for example, products resulting from the mask may deposit on the surface of the semiconductor film. For example, when one or both of the etching gas and the mask contain carbon, products containing carbon may deposit on the surface of the semiconductor film. In this case, a transistor with a desired shape may not be fabricated. Furthermore, impurities may diffuse into the semiconductor layer. As a result, the manufacturing yield of the semiconductor device may decrease. Furthermore, the reliability of the semiconductor device may decrease.

[0058] A method for removing the products deposited on the surface of a semiconductor film includes plasma treatment. For example, plasma treatment can be performed in an atmosphere containing one or both of oxygen gas and an inert gas (e.g., argon gas). As described above, when manufacturing a semiconductor device according to one embodiment of the present invention, dry etching of the semiconductor film needs to be performed for a long time, which increases the volume of the products deposited on the surface of the semiconductor film. Therefore, if the plasma treatment is performed only after the semiconductor film processing is completed and the semiconductor layer is formed, the products may not be completely removed. Furthermore, the products deposited on the surface of the semiconductor film may make the semiconductor film difficult to process. This may result in the semiconductor film remaining on the sidewall of the groove.

[0059] Therefore, in a method for manufacturing a semiconductor device according to one embodiment of the present invention, a product removal process is performed multiple times to remove products deposited on the surface of a semiconductor film. Specifically, as a process for processing a semiconductor film, a dry etching process and a product removal process are alternately performed multiple times. This makes it easier to remove the products deposited on the surface of the semiconductor film compared to, for example, performing a dry etching process and a product removal process once each. As described above, in one embodiment of the present invention, semiconductor devices can be miniaturized or highly integrated, while the manufacturing yield of the semiconductor device can be increased. Furthermore, a semiconductor device that can be manufactured at low cost can be provided. Furthermore, a highly reliable semiconductor device can be provided.

[0060] 1A1 is a plan view illustrating an example of a semiconductor device according to one embodiment of the present invention. The semiconductor device illustrated in FIG. 1A1 includes a transistor 200. FIG. 1A2 is a plan view in which some elements are omitted from FIG. 1A1.

[0061] Fig. 1B is a cross-sectional view taken along dashed lines A1-A2 in Fig. 1A1 and 1A2. Fig. 1C is a cross-sectional view taken along dashed lines A3-A4 in Fig. 1A1 and 1A2. Fig. 1D is a cross-sectional view taken along dashed lines B1-B2 in Fig. 1A1 and 1A2. Fig. 1E is a cross-sectional view taken along dashed lines B3-B4 in Fig. 1A1 and 1A2.

[0062] 2A to 2C are perspective views illustrating an example of a semiconductor device according to one embodiment of the present invention. Parts of the configuration illustrated in FIG. 2A are illustrated in FIGS. 2B and 2C. FIG. 2B includes an example cross-sectional configuration taken along dashed lines A1-A2 in FIGS. 1A1 and 1A2. FIG. 2C includes an example cross-sectional configuration taken along dashed lines B1-B2 in FIGS. 1A1 and 1A2.

[0063] Fig. 3A is an enlarged view of Fig. 1B. Fig. 3B is a cross-sectional view taken along dashed line C1-C2 in Fig. 1B, Fig. 1C, and Fig. 3A. Fig. 3B is also referred to as a plan view, and specifically can be said to be a plan view showing an example of the cross-sectional configuration taken along dashed line C1-C2.

[0064] 1A1 to 3B, the X direction, Y direction, and Z direction are indicated by arrows. Note that although the same X, Y, and Z symbols are used in each of FIGS. 1A1 to 3B, the directions do not necessarily have to match between these figures. In the following drawings, the X direction, Y direction, and Z direction do not necessarily have to match between the figures.

[0065] 1A1 to 3B includes an insulating layer 210 on a substrate (not shown), a transistor 200 on the insulating layer 210, an insulating layer 280, an insulating layer 285 on the insulating layer 280, and a conductive layer 245 on the insulating layer 285. Here, FIG. 1A2 is a plan view in which the conductive layer 245 is omitted from FIG. 1A1.

[0066] The insulating layer 210 functions as a base insulating film or an interlayer film. The insulating layers 280 and 285 function as interlayer films. In the example shown in FIGS. 1A1 to 3B, the conductive layer 245 is provided to extend in the X direction.

[0067] The transistor 200 includes a conductive layer 220, conductive layers 240a and 240b over an insulating layer 280, a semiconductor layer 230 over the conductive layer 220, the conductive layer 240a, and the conductive layer 240b, an insulating layer 250 over the semiconductor layer 230, and a conductive layer 260 over the insulating layer 250. The insulating layer 280 is provided over the conductive layer 220.

[0068] 1A1 and 1A2 do not show the insulating layer 210, the insulating layer 250, and the insulating layer 285. Some components may also be omitted in the subsequent plan views.

[0069] The conductive layer 260 functions as a gate electrode of the transistor 200. The insulating layer 250 functions as a gate insulating layer of the transistor 200. The conductive layer 220 functions as one of a source electrode and a drain electrode of the transistor 200. The conductive layer 240a and the conductive layer 240b function as the other of the source electrode and the drain electrode of the transistor 200 and are connected to each other through a conductive layer 245. Hereinafter, the conductive layer 240a and the conductive layer 240b may be collectively referred to as the conductive layer 240. Hereinafter, in the examples shown in FIGS. 1A1 to 3B , the conductive layer 260 and the conductive layer 220 are provided to extend in the Y direction. The conductive layer 240a and the conductive layer 240b are provided in an island shape.

[0070] 1A1 to 3B , the insulating layer 280 has a groove 290, at least a portion of which reaches the conductive layer 220. The groove 290 extends in a direction parallel to the extension direction of the conductive layer 260. That is, the groove 290 extends in the Y direction, similar to the conductive layer 260. As described above, the conductive layer 245 extends in the X direction. As a result, the conductive layer 245 intersects with the groove 290 and the conductive layer 260 in a planar view, for example, perpendicularly or substantially perpendicularly to them.

[0071] In this specification and the like, a groove can be rephrased as a slit or a trench. Also, a groove portion can be rephrased as a slit portion or a trench portion. Note that a groove portion may also be rephrased as a slit or a trench.

[0072] 1A1 to 3B, the conductive layer 220 is provided to extend in the Y direction. The conductive layer 220 may also be provided to extend in the X direction. The conductive layer 220 may also be provided to have a rectangular, approximately rectangular, square, or approximately square shape in a plan view. The groove portion 290 and the conductive layer 260 may also be provided to extend in the X direction. Furthermore, the conductive layer 245 may also be provided to extend in the Y direction.

[0073] At least some of the components of the transistor 200 are disposed in the groove 290. Specifically, the semiconductor layer 230, the insulating layer 250, and the conductive layer 260 are disposed such that at least some of them are located in the groove 290. The conductive layer 240a and the conductive layer 240b are provided so as to face each other across the groove 290 in a plan view. Note that the groove 290 may be provided not only in the insulating layer 280 but also between the conductive layer 240a and the conductive layer 240b.

[0074] 1B shows an example in which the inner side surface (groove 290 side) of the conductive layer 240a coincides or substantially coincides with the sidewall of the groove 290. Also shown is an example in which the inner side surface (groove 290 side) of the conductive layer 240b coincides or substantially coincides with the sidewall of the groove 290. With this configuration, the conductive layer 240a, the conductive layer 240b, and the groove 290 can be formed simultaneously.

[0075] The semiconductor layer 230 has a region that follows the sidewall of the groove 290. Within the groove 290, the semiconductor layer 230 has a region that follows the top surface of the conductive layer 220 and a region that follows the side surface of the insulating layer 280. The semiconductor layer 230 has a region that follows the side surface of the conductive layer 240a, a region that follows the top surface of the conductive layer 240a, a region that follows the side surface of the conductive layer 240b, and a region that follows the top surface of the conductive layer 240b.

[0076] The semiconductor layer 230 has a region in contact with the upper surface of the conductive layer 220, a region in contact with the side surface of the conductive layer 240a, a region in contact with the side surface of the conductive layer 240b, and a region in contact with the side wall of the groove 290. The semiconductor layer 230 also has a region outside the groove 290 in contact with the upper surface of the conductive layer 240a, and a region in contact with the upper surface of the conductive layer 240b.

[0077] The semiconductor layer 230 can be formed by depositing and processing a semiconductor film. The semiconductor film can be processed by etching. In particular, dry etching is preferable because it allows miniaturization or high integration of a semiconductor device compared to, for example, wet etching.

[0078] Here, in order to form the semiconductor layer 230 so as to have a region located within the groove 290, it is necessary to remove a portion of the semiconductor film in the region along the sidewall of the groove 290. However, removing the region of the semiconductor film along the sidewall of the groove by dry etching requires a long period of time. Therefore, for example, products resulting from the etching gas may accumulate on the surface of the semiconductor film. It is preferable to remove the products by product removal processing.

[0079] As described above, when manufacturing a semiconductor device according to one embodiment of the present invention, a dry etching process for a semiconductor film needs to be performed for a long time, and the volume of products deposited on the surface of the semiconductor film increases accordingly. Therefore, if a product removal process is performed only after the semiconductor film processing is completed and the semiconductor layer 230 is formed, the products may not be completely removed. Furthermore, the products deposited on the surface of the semiconductor film may make the semiconductor film difficult to process. As a result, the semiconductor film may remain on the sidewall of the groove 290.

[0080] Therefore, in one embodiment of the present invention, the product removal treatment is performed multiple times. Specifically, as a treatment for processing a semiconductor film, a dry etching treatment and a product removal treatment are alternately performed multiple times. This makes it easier to remove the above-described products deposited on the surface of the semiconductor film compared to, for example, performing a dry etching treatment and a product removal treatment once each. As described above, in one embodiment of the present invention, semiconductor devices can be miniaturized or highly integrated, while the manufacturing yield of the semiconductor devices can be increased. Furthermore, a semiconductor device that can be manufactured at low cost can be provided. Furthermore, a highly reliable semiconductor device can be provided.

[0081] The insulating layer 250 is provided so as to cover the semiconductor layer 230 in the groove 290. The insulating layer 250 has a recess at a position overlapping the groove 290.

[0082] The conductive layer 260 is provided so as to be located within the recessed portion of the insulating layer 250. The conductive layer 260 is provided so as to fill at least a portion of the recessed portion of the insulating layer 250. The conductive layer 260 has a region within the groove 290 that faces the semiconductor layer 230 with the insulating layer 250 sandwiched therebetween.

[0083] As described above, the semiconductor layer 230 is provided in the groove 290. In addition, the transistor 200 has a configuration in which one of the source electrode and the drain electrode (here, the conductive layer 220) is located on the lower side and the other of the source electrode and the drain electrode (here, the conductive layer 240 a and the conductive layer 240 b) is located on the upper side, and thus current flows in the vertical direction. In other words, a channel is formed along the sidewall of the groove 290.

[0084] With the above configuration, a channel formation region and a source region or a drain region can be formed in the groove 290. This allows the transistor 200 to occupy a smaller area than a planar transistor in which the channel formation region, the source region, and the drain region are provided separately on the XY plane. This allows for miniaturization or high integration of semiconductor devices.

[0085] The insulating layer 285 is located on the conductive layer 260 and the insulating layer 250. The insulating layer 285, the insulating layer 250, and the semiconductor layer 230 have an opening 270a that reaches the conductive layer 240a and an opening 270b that reaches the conductive layer 240b. A conductive layer 244a is provided in the opening 270a, and a conductive layer 244b is provided in the opening 270b. For example, the conductive layer 244a is provided to fill the opening 270a, and the conductive layer 244b is provided to fill the opening 270b. The conductive layer 244a may have a region in contact with the conductive layer 240a in the opening 270a. The conductive layer 244b may have a region in contact with the conductive layer 240b in the opening 270b. Hereinafter, the openings 270a and 270b may be collectively referred to as openings 270. The conductive layer 244 a and the conductive layer 244 b may be collectively referred to as the conductive layer 244 .

[0086] The conductive layer 245 is provided over the insulating layer 285, the conductive layer 244a, and the conductive layer 244b. The conductive layer 245 can have a region in contact with the top surface of the conductive layer 244a and a region in contact with the top surface of the conductive layer 244b. As described above, the conductive layer 240a and the conductive layer 240b can be connected via the conductive layer 244a, the conductive layer 245, and the conductive layer 244b.

[0087] The conductive layer 245 overlaps with the conductive layer 260 with the insulating layer 285 interposed therebetween, which functions as an interlayer film. This allows for a smaller parasitic capacitance than, for example, a case in which the conductive layer 240 extends in the Y direction without providing the conductive layer 245. Therefore, the semiconductor device of one embodiment of the present invention can be a semiconductor device capable of high-speed operation. Note that the height of the top surfaces of the conductive layers 244a and 244b is preferably the same as or approximately the same as the height of the top surface of the insulating layer 285.

[0088] As described above, the conductive layer 245 intersects with the conductive layer 260 in a plan view, for example, perpendicularly or substantially perpendicularly. This allows the area where the conductive layer 245 and the conductive layer 260 overlap to be smaller than when the conductive layer 245 and the conductive layer 260 are arranged parallel to each other in a plan view. Therefore, the parasitic capacitance generated between the conductive layer 260 and the conductive layer 245 can be reduced. Therefore, the semiconductor device of one embodiment of the present invention can be a semiconductor device capable of high-speed operation. Note that, for example, when the insulating layer 285 is sufficiently thick and the parasitic capacitance per unit area generated between the conductive layer 260 and the conductive layer 245 is negligibly small, the conductive layer 260 and the conductive layer 245 may be arranged parallel to each other in a plan view.

[0089] 3A is an enlarged view of FIG. 1B as described above, and shows an example of the configuration of transistor 200. As shown in FIG.

[0090] In the semiconductor layer 230, a region facing the conductive layer 260 with the insulating layer 250 sandwiched therebetween in the groove 290 and its vicinity function as a channel formation region of the transistor 200. A region of the semiconductor layer 230 near the conductive layer 220 functions as one of a source region and a drain region. At least one of a region of the semiconductor layer 230 near the conductive layer 240a and a region of the semiconductor layer 230 near the conductive layer 240b functions as the other of the source region and the drain region. In other words, the channel formation region is sandwiched between the source region and the drain region.

[0091] With the above structure, a channel formation region and a source region or a drain region can be formed in the groove 290. As a result, as described above, the transistor 200 can occupy a smaller area than a planar transistor. This allows miniaturization or high integration of the semiconductor device.

[0092] The channel length of the transistor 200 is the distance between the source region and the drain region in the semiconductor layer 230. In Figure 3A, the channel length Lc of the transistor 200 is indicated by a dashed double-headed arrow. In a cross-sectional view, the channel length Lc is the distance between the edge of the region where the semiconductor layer 230 and the conductive layer 240 contact each other and the edge of the region where the semiconductor layer 230 and the conductive layer 220 contact each other.

[0093] The channel length of a planar transistor is limited by the exposure limit of photolithography, making further miniaturization difficult. However, the channel length of the transistor 200 can be set by the thickness of the insulating layer 280, etc. Therefore, the channel length of the transistor 200 can be made into a very fine structure that is equal to or less than the exposure limit of photolithography (for example, 60 nm or less, 50 nm or less, 40 nm or less, 30 nm or less, 20 nm or less, or 10 nm or less, and 0.1 nm or more, 1 nm or more, or 5 nm or more). This increases the on-state current of the transistor 200, thereby improving its frequency characteristics.

[0094] Note that the channel length of the transistor 200 is determined by the film thickness of the insulating layer 280 and the like. Therefore, the channel length does not affect the area occupied by the transistor 200, for example, the area of ​​the transistor 200 in a plan view. By setting the channel length of the transistor 200 to, for example, 1 μm or less, 500 nm or less, or 300 nm or less, productivity and yield can be improved in the formation of the groove 290 and the like.

[0095] From the above, the channel length of the transistor included in the semiconductor device of one embodiment of the present invention is preferably 0.1 nm or more, 1 nm or more, or 5 nm or more, and is preferably 1 μm or less, 500 nm or less, or 300 nm or less.

[0096] 3A shows an example in which the conductive layer 240a has a two-layer structure including a conductive layer 240a1 and a conductive layer 240a2 on the conductive layer 240a1. Also shown is an example in which the conductive layer 240b has a two-layer structure including a conductive layer 240b1 and a conductive layer 240b2 on the conductive layer 240b1. Furthermore, an example in which the conductive layer 220 has a two-layer structure including a conductive layer 220_1 and a conductive layer 220_2 on the conductive layer 220_1 is shown.

[0097] 3A illustrates a configuration in which the upper surface of the conductive layer 220 has a recess. Specifically, the upper surface of the conductive layer 220_2 has a recess. The bottom surface of the recess corresponds to the bottom surface of the recess in the conductive layer 220_2. The side surface of the recess corresponds to the side surface of the recess in the conductive layer 220_2.

[0098] The recess of the conductive layer 220_2 is included in the groove 290. Here, the bottom of the groove 290 includes the bottom surface of the recess of the conductive layer 220_2. Furthermore, the sidewall of the groove 290 includes the side surface of the recess of the conductive layer 220_2 and the side surface of the insulating layer 280. In this case, the semiconductor layer 230 has a region that is aligned with the recess of the conductive layer 220_2.

[0099] By providing the recessed portion in the conductive layer 220_2, the height of the bottom surface of the insulating layer 250 and the height of the bottom surface of the conductive layer 260 in the groove 290 can be made lower than the height of the top surface of the conductive layer 220_2 that is in contact with the insulating layer 280, compared to when the recessed portion is not provided. Here, the height of each surface can be determined based on the surface on which the transistor is formed. Note that the surface used as the reference is not limited to the surface on which the transistor is formed. For example, the top surface of a substrate on which the semiconductor device is provided may be used as the reference.

[0100] By reducing the height of the bottom surface of the conductive layer 260, a gate electric field can be easily applied to the channel formation region of the semiconductor layer 230. This can improve the electrical characteristics of the transistor 200. In addition, a gate electric field can be easily applied to a region of the semiconductor layer 230 in contact with the conductive layer 220_2. This can increase the on-state current of the transistor 200. Furthermore, regardless of whether the conductive layer 220 or the conductive layer 240 is used as the drain electrode, the electrical characteristics of the transistor 200 can be improved.

[0101] 3A shows an example in which the opening 270a is provided not only in the insulating layer 285, the insulating layer 250, and the semiconductor layer 230 but also in the conductive layer 240a2. Similarly, an example in which the opening 270b is provided in the conductive layer 240b2 is also shown. Also shown is an example in which the opening 270a reaches the conductive layer 240a1, and the opening 270b reaches the conductive layer 240b1. In this case, the conductive layer 244a can have a region in contact with the top surface of the conductive layer 240a1 and the side surface of the conductive layer 240a2. Similarly, the conductive layer 244b can have a region in contact with the top surface of the conductive layer 240b1 and the side surface of the conductive layer 240b2.

[0102] By having the conductive layer 244a in contact with the top surface of the conductive layer 240a1, the contact resistance between the conductive layer 240a and the conductive layer 244a can be reduced, even if the contact resistance per unit area between the conductive layer 240a2 and the conductive layer 244a is greater than the contact resistance per unit area between the conductive layer 240a1 and the conductive layer 244a. Furthermore, by having the conductive layer 244a in contact with the side surface of the conductive layer 240a2, the contact area between the conductive layer 240a and the conductive layer 244a can be increased compared to when the conductive layer 244a is in contact only with the top surface of the conductive layer 240a. This reduces the contact resistance between the conductive layer 240a and the conductive layer 244a. Similarly, by having the conductive layer 244b in contact with the top surface of the conductive layer 240b1 and the side surface of the conductive layer 240b2, the contact resistance between the conductive layer 240b and the conductive layer 244b can be reduced.

[0103] Note that the conductive layer 240a2 may not have the opening 270a, and the conductive layer 240b2 may not have the opening 270b. In this case, the opening 270a reaches the upper surface of the conductive layer 240a2, and the opening 270b reaches the upper surface of the conductive layer 240b2. When the conductive layer 240a2 does not have the opening 270a, the opening 270a can be formed more easily than when the conductive layer 240a2 has the opening 270a. Similarly, when the conductive layer 240b2 does not have the opening 270b, the opening 270b can be formed more easily than when the conductive layer 240b2 has the opening 270b.

[0104] 3A , the opening 270a includes an opening in the insulating layer 285, an opening in the insulating layer 250, an opening in the semiconductor layer 230, and an opening in the conductive layer 240a2. Similarly, the opening 270b includes an opening in the insulating layer 285, an opening in the insulating layer 250, an opening in the semiconductor layer 230, and an opening in the conductive layer 240b2. Note that the shape and size of the openings 270a and 270b in a planar view may differ depending on the layer. Furthermore, when the shape of the openings 270a and 270b in a planar view is circular, the openings in each layer may or may not be concentric.

[0105] As described above, FIG. 3B is a cross-sectional view taken along dashed dotted line C1-C2 in FIGS. 1B, 1C, and 3A. As shown in FIG. 3B, an insulating layer 250 is provided in the groove 290 to cover the side surface of the semiconductor layer 230 that does not contact the insulating layer 280. The insulating layer 250 is also provided along the side surface of the insulating layer 280 in the groove 290. A conductive layer 260 is provided in the center of the groove 290. The conductive layer 260 and the semiconductor layer 230 are provided in the groove 290 to face each other with the insulating layer 250 interposed therebetween. That is, in the groove 290, the conductive layer 260 covers the semiconductor layer 230 via the insulating layer 250. In the example shown in FIG. 3B, the channel width of the transistor 200 is determined by the length of the semiconductor layer 230 in the Y direction. In FIG. 3B, the length L230 of the semiconductor layer 230 in the Y direction is shown. The channel width of the transistor 200 can be calculated as "2×L230".

[0106] Increasing the length L230 in the Y direction of the semiconductor layer 230 increases the channel width per unit area of ​​the transistor 200, thereby increasing the on-state current. On the other hand, shortening the length L230 reduces the area occupied by the transistor 200, thereby enabling a semiconductor device to be highly integrated.

[0107] The width of the groove 290 in the X direction is set by the film thickness of each of the semiconductor layer 230, the insulating layer 250, and the conductive layer 260 provided in the groove 290. The width of the groove 290 in the X direction is, for example, 5 nm or more, 10 nm or more, or 20 nm or more, and is preferably 300 nm or less, 200 nm or less, 100 nm or less, 60 nm or less, 50 nm or less, 40 nm or less, or 30 nm or less.

[0108] <Example of Manufacturing Method of Semiconductor Device> An example of a manufacturing method of a semiconductor device of one embodiment of the present invention will be described below with reference to FIGS. 4A to 14E . In the drawings illustrating an example of a manufacturing method of a semiconductor device, (A) in each drawing is a plan view unless otherwise specified. (B) in each drawing is a cross-sectional view taken along dashed-dotted line A1-A2 in (A) of each drawing. (C) in each drawing is a cross-sectional view taken along dashed-dotted line A3-A4 in (A) of each drawing. (D) in each drawing is a cross-sectional view taken along dashed-dotted line B1-B2 in (A) of each drawing. (E) in each drawing is a cross-sectional view taken along dashed-dotted line B3-B4 in (A) of each drawing.

[0109] Thin films (insulating films, semiconductor films, conductive films, etc.) that constitute semiconductor devices can be formed using a sputtering method, a chemical vapor deposition (CVD) method, a vacuum deposition method, a molecular beam epitaxy (MBE) method, a pulsed laser deposition (PLD) method, an atomic layer deposition (ALD) method, or the like.

[0110] Sputtering methods include RF sputtering, which uses a high-frequency power supply as the sputtering power source, DC sputtering, which uses a direct current power supply, and pulsed DC sputtering, which changes the voltage applied to the electrode in a pulsed manner. RF sputtering is mainly used to form insulating films, while DC sputtering is mainly used to form metal conductive films. Pulsed DC sputtering is mainly used to form films of compounds such as oxides, nitrides, and carbides using reactive sputtering.

[0111] CVD methods can be further classified into plasma-enhanced CVD (PECVD) methods that utilize plasma, thermal CVD (TCVD) methods that utilize heat, and photo-CVD (photo-CVD) methods that utilize light. CVD methods can also be further classified into metal CVD (MCVD) methods and metal organic CVD (MOCVD) methods depending on the source gas used.

[0112] The plasma CVD method can produce high-quality films at relatively low temperatures. Furthermore, the thermal CVD method is a film formation method that can minimize plasma damage to the workpiece because it does not use plasma. For example, wiring, electrodes, elements (transistors, capacitors, etc.) included in a semiconductor device may become charged up by receiving electric charge from the plasma. In this case, the accumulated electric charge may destroy the wiring, electrodes, elements, etc. included in the semiconductor device. On the other hand, the thermal CVD method, which does not use plasma, does not cause such plasma damage, and therefore can increase the yield of semiconductor devices. Furthermore, the thermal CVD method does not cause plasma damage during film formation, so films with fewer defects can be obtained.

[0113] As the ALD method, a thermal ALD method in which a precursor and a reactant are reacted using only thermal energy, a plasma ALD (PEALD: Plasma Enhanced ALD) method in which a plasma-excited reactant is used, or the like can be used.

[0114] Note that some precursors used in the ALD method contain elements such as carbon or chlorine. Therefore, films formed by the ALD method may contain more elements such as carbon or chlorine than films formed by other film formation methods. The amounts of these elements can be quantified using XPS or SIMS. Note that the metal oxide film formation method of one embodiment of the present invention uses the ALD method, but employs one or both of the following conditions: a high substrate temperature during film formation and / or an impurity removal treatment. Therefore, the amount of carbon and chlorine contained in the film may be smaller than when the ALD method is used without these conditions.

[0115] Unlike film formation methods in which particles emitted from a target or the like are deposited, the ALD method is a film formation method in which a film is formed by a reaction on the surface of a workpiece. Therefore, it is a film formation method that is less affected by the shape of the workpiece and has good step coverage. In particular, the ALD method has excellent step coverage and excellent thickness uniformity, making it suitable for coating the surface of an opening with a high aspect ratio.

[0116] The CVD and ALD methods differ from sputtering methods in which particles emitted from a target or the like are deposited. Therefore, they are film formation methods that are less affected by the shape of the workpiece and have good step coverage. In particular, the ALD method has excellent step coverage and excellent thickness uniformity, making it suitable for coating the surface of an opening with a high aspect ratio. However, because the ALD method has a relatively slow film formation rate, it may be preferable to use it in combination with other film formation methods, such as the CVD method, which have a faster film formation rate.

[0117] Furthermore, the CVD method allows deposition of a film of any composition by adjusting the flow rate ratio of the source gases. For example, the CVD method allows deposition of a film with a continuously changing composition by changing the flow rate ratio of the source gases during deposition. When deposition is performed while changing the flow rate ratio of the source gases, the time required for deposition can be shortened compared to deposition using multiple deposition chambers because no time is required for transport or pressure adjustment. Therefore, the productivity of semiconductor devices can be improved in some cases.

[0118] In addition, in the ALD method, a film of any composition can be formed by simultaneously introducing multiple different precursors, or by controlling the number of cycles of each precursor when multiple different precursors are introduced.

[0119] Furthermore, thin films (insulating films, semiconductor films, conductive films, etc.) constituting the semiconductor device can be formed by a wet film formation method such as spin coating, dip coating, spray coating, inkjet printing, dispensing, screen printing, offset printing, doctor knife method, slit coating, roll coating, curtain coating, or knife coating.

[0120] Furthermore, when processing a thin film that constitutes a semiconductor device, a photolithography method or the like can be used. Alternatively, the thin film may be processed by a nanoimprint method, a sandblasting method, a lift-off method, or the like. Furthermore, an island-shaped thin film may be directly formed by a film formation method using a shielding mask such as a metal mask.

[0121] There are two typical photolithography methods: one is to form a resist mask on the thin film to be processed, and then remove part of the thin film by etching or the like, and then remove the resist mask; the other is to form a photosensitive thin film, and then expose and develop it to process the thin film into the desired shape.

[0122] In photolithography, the light used for exposure can be, for example, i-line (wavelength 365 nm), g-line (wavelength 436 nm), h-line (wavelength 405 nm), or a mixture of these. Other light sources that can be used include ultraviolet light, KrF laser light, ArF laser light, etc. Exposure can also be performed by immersion exposure technology. Extreme ultraviolet (EUV) light or X-rays can also be used as the light used for exposure. An electron beam can also be used instead of the light used for exposure. Extreme ultraviolet light, X-rays, or an electron beam are preferred because they enable extremely fine processing. When exposure is performed by scanning a beam such as an electron beam, a photomask is not required.

[0123] For etching the thin film, dry etching, wet etching, sandblasting, or the like can be used.

[0124] An example of a method for manufacturing the semiconductor device shown in FIGS. 1A1 to 1E will be described below.

[0125] First, as shown in FIGS. 4A to 4E , an insulating layer 210 is formed on a substrate (not shown), and a conductive layer 220 is formed on the insulating layer 210. For example, a first conductive film that will become the conductive layer 220_1 is formed, a second conductive film that will become the conductive layer 220_2 is formed on the first conductive film, and the first and second conductive films are processed to form the conductive layer 220 having the conductive layer 220_1 and the conductive layer 220_2. The first and second conductive films, i.e., the conductive film that will become the conductive layer 220, can be processed using an etching process. In particular, dry etching is preferable because it is suitable for microfabrication. The conductive layer 220 can be formed to extend in the Y direction.

[0126] 4A to 4E, an insulating layer 280 is formed on the conductive layer 220 and the insulating layer 210, and a conductive film 240f is formed on the insulating layer 280. As the conductive film 240f, for example, a conductive film 240f1 on the insulating layer 280 and a conductive film 240f2 on the conductive film 240f1 are formed.

[0127] 5A to 5E, the conductive film 240f and the insulating layer 280 are processed to form a groove 290 that reaches the conductive layer 220. The groove 290 can be formed to extend in the Y direction.

[0128] The groove 290 is formed so that a part of the upper surface of the conductive layer 220_2 is exposed. At this time, a recess is preferably formed in the conductive layer 220_2. The recess is included in the groove 290. By forming the groove 290, it is preferable that the bottom surface and side surfaces of the recess of the conductive layer 220_2 are exposed.

[0129] When forming the groove 290, etching can be used to process the conductive film 240f and the insulating layer 280. In particular, dry etching is preferable because it is suitable for fine processing.

[0130] Subsequently, heat treatment is preferably performed at a temperature of, for example, 250° C. or higher and 650° C. or lower, preferably 300° C. or higher and 500° C. or lower, and more preferably 320° C. or higher and 450° C. or lower.

[0131] The heat treatment is performed in an inert gas atmosphere or an atmosphere containing an oxidizing gas at 10 ppm or more, 1% or more, or 10% or more. For example, when the heat treatment is performed in a mixed atmosphere of nitrogen gas and oxygen gas, the oxygen gas concentration is preferably about 20%. The heat treatment may be performed under reduced pressure. Alternatively, after the heat treatment in the inert gas atmosphere, the heat treatment may be performed in an atmosphere containing an oxidizing gas at 10 ppm or more, 1% or more, or 10% or more to compensate for the desorbed oxygen. By performing the above-described heat treatment, impurities such as hydrogen or water contained in the insulating layer 280 or the like can be reduced before the formation of the semiconductor layer 230.

[0132] Furthermore, the gas used in the heat treatment is preferably highly purified. For example, the amount of moisture contained in the gas used in the heat treatment is preferably 1 ppb or less, more preferably 0.1 ppb or less, and even more preferably 0.05 ppb or less. By performing the heat treatment using a highly purified gas, it is possible to prevent moisture and the like from being absorbed into the insulating layer 280 and the like as much as possible.

[0133] 6A to 6E , a semiconductor film 230f, which will later become the semiconductor layer 230, is formed to cover the groove 290. The semiconductor film 230f is formed to have a region that follows the sidewall of the groove 290. Within the groove 290, the semiconductor film 230f is formed to have a region that follows the recess of the conductive layer 220_2, a region that follows the side surface of the insulating layer 280, a region that follows the side surface of the conductive film 240f1, and a region that follows the side surface of the conductive film 240f2. The semiconductor film 230f is also formed to have a region that is located on the conductive film 240f2. The semiconductor film 230f is formed in contact with the bottom and side surfaces of the recess of the conductive layer 220_2, the side surfaces of the conductive film 240f1, and the side and top surfaces of the conductive film 240f2.

[0134] The description in Embodiment Mode 2 can be referred to for a manufacturing method of the semiconductor film 230f.

[0135] In this embodiment, a first metal oxide film, a second metal oxide film, and a third metal oxide film are formed in this order as the semiconductor film 230f. For example, an In—Ga—Zn oxide film is formed as the first metal oxide film by thermal ALD, an indium oxide film is formed as the second metal oxide film by thermal ALD, and an In—Ga—Zn oxide film is formed as the third metal oxide film by sputtering.

[0136] It is preferable that the first metal oxide film and the second metal oxide film are successively formed without being exposed to the atmosphere. By successively forming the first metal oxide film and the second metal oxide film without being exposed to the atmosphere, productivity can be improved. Furthermore, impurities (typically, moisture, etc.) introduced into the interface between the first metal oxide film and the second metal oxide film and the vicinity thereof can be reduced.

[0137] After the second metal oxide film is formed, a process of supplying oxygen to the second metal oxide film may be performed. By this process, oxygen can be supplied to the semiconductor layer 230 by heat or the like applied after the process. Note that the above description can be referred to for details of the process of supplying oxygen.

[0138] Next, it is preferable to perform heat treatment. The temperature of the heat treatment is preferably 100° C. or higher and 650° C. or lower, more preferably 250° C. or higher and 600° C. or lower, and even more preferably 350° C. or higher and 550° C. or lower. For details of the heat treatment, refer to the above description.

[0139] In addition, it is preferable that the gas used in the heat treatment be highly purified. By performing the heat treatment using a highly purified gas, moisture and the like can be prevented from being taken into the semiconductor layer 230 as much as possible.

[0140] The heat treatment reduces impurities such as carbon, hydrogen, and water in the semiconductor film 230f. Reducing the impurities in the film in this manner improves the crystallinity of the semiconductor film 230f, resulting in a denser, more compact structure. This increases the crystalline regions in the semiconductor film 230f, reducing in-plane variations in the crystalline regions in the semiconductor film 230f. This reduces in-plane variations in the electrical characteristics of the transistor.

[0141] In addition, it is preferable that oxygen be supplied from the insulating film containing oxygen to the channel formation region of the semiconductor film 230f by the heat treatment. Ｏ H can be reduced.

[0142] In this way, excess oxygen may be supplied to the semiconductor film 230f from an insulating layer in contact with the semiconductor film 230f. The excess oxygen has a function of trapping electrons, which makes it easier for negative charges to be formed. Therefore, the threshold voltage of the transistor is shifted in the positive direction, making it possible to realize a normally-off transistor.

[0143] Note that microwave plasma treatment may be performed after the formation of the second metal oxide film or the third metal oxide film. By performing the microwave plasma treatment, the concentration of impurities such as hydrogen or water contained in the semiconductor film 230f can be reduced. Furthermore, crystalline regions of the semiconductor film 230f may grow. Note that details of the microwave plasma treatment will be described in Embodiment 2.

[0144] 7A to 7E, a mask 231 is formed on the semiconductor film 230f. The mask 231 may include photoresist. The mask 231 may be formed, for example, by applying photoresist to the semiconductor film 230f, followed by exposure and development. In a plan view, the mask 231 is formed in an area where the semiconductor layer 230 will be formed in a later process.

[0145] For example, one or both of a spin on carbon (SOC) film and a spin on glass (SOG) film can be used as a hard mask in combination with a photoresist as the mask 231. The mask 231 can have a laminated structure of, for example, an SOC film, an SOG film on the SOC film, and a photoresist on the SOG film.

[0146] 8A to 8D and 9A to 9E, the semiconductor film 230f is processed to form the semiconductor layer 230. Figures 8A to 8D show the steps from Figure 7C to Figure 9C in order.

[0147] In a method for manufacturing a semiconductor device according to one embodiment of the present invention, a region of the semiconductor film 230f that does not overlap with the mask 231 is removed to form the semiconductor layer 230. Etching treatment can be used to remove the semiconductor film 230f. In particular, dry etching treatment is preferable because it enables miniaturization or high integration of the semiconductor device compared to the case of using wet etching treatment, for example.

[0148] As an etching gas for the dry etching process, a gas containing carbon, such as a hydrocarbon, can be used. For example, methane (CH ４ ), ethane (C ２ H ６ ), propane (C ３ H ８ ), butane (C ４ H １０ ), ethylene (C ２ H ４ ), propylene (C ３ H ６ ), acetylene (C ２ H ２ ), and propyne (C ３ H ４ ) can be used.

[0149] Alternatively, a gas containing a halogen may be used as the etching gas. For example, an etching gas containing at least one of chlorine and bromine may be used as the halogen-containing gas. For example, Cl ２ Gas, BCl３ Gas, SiCl ４ Gas, or BBr ３ The gases may be used alone or in combination of two or more.

[0150] For example, a noble gas can be added to the etching gas. Examples of noble gases include helium, neon, argon, krypton, xenon, and radon. In addition, one or both of nitrogen gas and hydrogen gas may be added to the etching gas. Furthermore, when a gas containing halogen is used as the etching gas, oxygen (O ２ ) gas, carbon dioxide, nitrogen (N ２ At least one of a nitrogen gas, a hydrogen gas, a hydrocarbon gas, etc. may be added as appropriate.

[0151] Furthermore, as the dry etching apparatus, a capacitively coupled plasma (CCP) etching apparatus having parallel plate electrodes can be used. The capacitively coupled plasma etching apparatus having parallel plate electrodes may be configured to apply a high-frequency voltage to one of the parallel plate electrodes. Alternatively, it may be configured to apply a plurality of different high-frequency voltages to one of the parallel plate electrodes. Alternatively, it may be configured to apply a high-frequency voltage of the same frequency to each of the parallel plate electrodes. Alternatively, it may be configured to apply high-frequency voltages of different frequencies to each of the parallel plate electrodes. Alternatively, a dry etching apparatus having a high-density plasma source can be used. As the dry etching apparatus having a high-density plasma source, for example, an inductively coupled plasma (ICP) etching apparatus or the like can be used.

[0152] Here, in order to form the semiconductor layer 230 so as to have a region located within the groove 290 extending in a predetermined direction, for example, the Y direction, it is necessary to remove part of the region of the semiconductor film 230f along the sidewall of the groove 290 (see FIGS. 7C and 9C ). However, when the region of the semiconductor film 230f along the sidewall of the groove 290 is removed by dry etching, the dry etching process needs to be performed for a longer period of time than when, for example, only the region along the top surface of the conductive layer 220 and the region located on the conductive film 240f are removed.

[0153] Therefore, for example, products resulting from the etching gas may be deposited on the surface of the semiconductor film 230f. Also, for example, products resulting from the mask 231 may be deposited on the surface of the semiconductor film 230f. For example, when one or both of the etching gas and the mask 231 contain carbon, products containing carbon may be deposited on the surface of the semiconductor film 230f. For example, when the above-mentioned gas containing hydrocarbon is used as the etching gas, products containing carbon may be deposited on the surface of the semiconductor film 230f. Also, when the mask 231 contains SOC, products containing carbon may be deposited on the surface of the semiconductor film 230f even if the etching gas does not contain carbon.

[0154] If the above-mentioned products are deposited on the surface of the semiconductor film 230f, for example, a transistor with a desired shape may not be manufactured. Furthermore, impurities may diffuse into the semiconductor layer 230. As a result, the manufacturing yield of the semiconductor device may decrease. Furthermore, the reliability of the semiconductor device may decrease. Therefore, it is preferable to remove the products deposited on the surface of the semiconductor film 230f during dry etching of the semiconductor film 230f.

[0155] The by-products deposited on the surface of the semiconductor film 230f can be removed by plasma treatment. The plasma treatment can be performed in an atmosphere containing, for example, oxygen and / or an inert gas. Examples of the inert gas that can be used include noble gases such as argon, helium, and neon, nitrogen, and mixtures thereof.

[0156] In this specification and the like, a process for removing the by-products is referred to as a product removal process. Examples of the product removal process include the above-mentioned plasma treatment. Here, for example, the above-mentioned plasma treatment may be performed two or more times in one product removal process.

[0157] When plasma treatment is performed in an atmosphere containing oxygen, for example, the products deposited on the surface of the semiconductor film 230f can be removed by a chemical reaction between the products and oxygen. For example, the products deposited on the surface of the semiconductor film 230f can be removed by decomposing the products. Here, the process of performing plasma treatment in an atmosphere containing oxygen and decomposing the products is also called an ashing process.

[0158] When performing plasma treatment in an atmosphere containing an inert gas, for example, by-products deposited on the surface of the semiconductor film 230 f can be physically removed by colliding the by-products deposited on the surface of the semiconductor film 230 f with an inert gas accelerated by plasma, thereby scattering and removing the by-products.

[0159] As described above, when manufacturing a semiconductor device according to one embodiment of the present invention, the dry etching process for the semiconductor film 230f needs to be performed for a long time, and the volume of the product deposited on the surface of the semiconductor film 230f also increases accordingly. Therefore, if the product removal process is performed only after the processing of the semiconductor film 230f is completed and the semiconductor layer 230 is formed, the product may not be completely removed. Furthermore, the product deposited on the surface of the semiconductor film 230f may make it difficult to process the semiconductor film 230f. As a result, the semiconductor film 230f may remain on the sidewall of the groove 290.

[0160] Therefore, in a method for manufacturing a semiconductor device according to one embodiment of the present invention, a product removal treatment is performed multiple times. Specifically, as a treatment for processing the semiconductor film 230f, a dry etching treatment and a product removal treatment are alternately performed multiple times. This makes it easier to remove the above-described products deposited on the surface of the semiconductor film 230f compared to, for example, performing a dry etching treatment and a product removal treatment once each. As described above, in one embodiment of the present invention, semiconductor devices can be miniaturized or highly integrated, while the manufacturing yield of the semiconductor devices can be increased. Furthermore, a semiconductor device that can be manufactured at low cost can be provided. Furthermore, a highly reliable semiconductor device can be provided.

[0161] 8A to 8D show an example in which dry etching treatment and product removal treatment are alternately performed twice. FIG. 8A shows a configuration example of a semiconductor device after a first dry etching treatment (also referred to as a first dry etching treatment) is performed. FIG. 8A shows an example in which a region of the semiconductor film along the top surface of the conductive layer 220 and a region located over the conductive film 240f are removed, but a portion of a region along the sidewall of the groove 290 remains. Specifically, in a region of the semiconductor film that does not overlap with the mask 231, a region along the top surface of the conductive layer 220 and a region located over the conductive film 240f are removed, but a portion of a region along the sidewall of the groove 290 remains. In FIG. 8A, the semiconductor film after the first dry etching treatment is designated as a semiconductor film 230fa.

[0162] 8A illustrates an example in which the product 233_1 is formed to cover the semiconductor film 230fa. The product 233_1 can be one or both of a product resulting from the etching gas and a product resulting from the mask 231. For example, the product 233_1 can contain carbon when one or both of the etching gas and the mask 231 contain carbon. Note that although FIG. 8A illustrates an example in which the product 233_1 is formed to cover the exposed top surface of the conductive layer 220, the exposed sidewalls of the groove 290, and the top surface of the conductive film 240f, one embodiment of the present invention is not limited thereto. The product 233_1 does not need to cover at least a portion of the exposed top surface of the conductive layer 220. Furthermore, the product 233_1 does not need to cover at least a portion of the exposed sidewalls of the groove 290. Furthermore, the product 233_1 does not need to cover at least a portion of the top surface of the conductive film 240f.

[0163] 8B illustrates a configuration example of a semiconductor device after a first product removal treatment (also referred to as a first product removal treatment) has been performed, in which the product 233_1 illustrated in FIG. 8A has been removed and the surface of the semiconductor film 230fa is exposed.

[0164] 8C shows an example of the structure of a semiconductor device after a second dry etching process (also referred to as a second dry etching process) has been performed. In FIG. 8C, the semiconductor film is completely removed. Specifically, the region of the semiconductor film that does not overlap with the mask 231 is completely removed. Note that the conditions for the second dry etching process may be the same as or different from the conditions for the first dry etching process.

[0165] 8C shows an example in which a product 233_2 is formed so as to cover the exposed upper surface of the conductive layer 220, the exposed sidewall of the groove 290, and the upper surface of the conductive film 240f. Hereinafter, the products 233_1 and 233_2 may be collectively referred to as the product 233.

[0166] The product 233_2 may contain the same elements as those contained in the product 233_1. The product 233_2 may not cover at least a portion of the exposed upper surface of the conductive layer 220. The product 233_2 may not cover at least a portion of the sidewall of the groove 290. Furthermore, the product 233_2 may not cover at least a portion of the upper surface of the conductive film 240f.

[0167] 8D shows an example of the configuration of a semiconductor device after a second by-product removal process (also referred to as a second by-product removal process) has been performed. Note that the conditions for the second by-product removal process may be the same as or different from the conditions for the first by-product removal process.

[0168] 8D shows an example in which the product 233_2 shown in FIG. 8C has been removed. In this manner, the semiconductor layer 230 shown in FIGS. 9A to 9E can be formed. Note that the dry etching treatment and the product removal treatment may each be performed three or more times. Alternatively, one or both of the dry etching treatment and the product removal treatment may be performed only once.

[0169] Here, it is preferable to perform a cleaning process after the product removal process. This may make it easier to remove the product 233. Examples of cleaning methods include wet cleaning (which may also be called wet etching) using a cleaning solution or the like. Also, cleaning by heat treatment, for example, may be performed. Furthermore, ultrasonic cleaning may be performed. Note that the cleaning process does not necessarily have to be performed.

[0170] Wet cleaning may be performed using an aqueous solution prepared by diluting one or more of ammonia water, oxalic acid, phosphoric acid, and hydrofluoric acid with pure water or carbonated water. Wet cleaning may also be performed using pure water, carbonated water, or the like. Alternatively, ultrasonic cleaning may be performed using these aqueous solutions, pure water, or carbonated water. Alternatively, these cleaning methods may be combined as appropriate.

[0171] In this specification, an aqueous solution of hydrofluoric acid diluted with pure water or carbonated water may be referred to as diluted hydrofluoric acid, and an aqueous solution of ammonia water diluted with pure water may be referred to as diluted ammonia water. The concentration or temperature of the aqueous solution may be adjusted appropriately depending on the impurities to be removed, the configuration of the semiconductor device to be cleaned, and other factors. The ammonia concentration of the diluted ammonia water is preferably 0.01% or more and 5% or less, and more preferably 0.1% or more and 0.5% or less. The hydrogen fluoride concentration of the diluted hydrofluoric acid is preferably 0.01 ppm or more and 100 ppm or less, and more preferably 0.1 ppm or more and 10 ppm or less.

[0172] For ultrasonic cleaning, a frequency of 200 kHz or more is preferably used, and a frequency of 900 kHz or more is more preferably used. By using such a frequency, damage to the semiconductor layer 230 can be reduced, for example.

[0173] The cleaning process may be performed after each of the multiple product removal processes. That is, the cleaning process may be performed the same number of times as the product removal process. In this case, in the example shown in FIGS. 8A to 8D , the first cleaning process is performed after the first product removal process and before the second dry etching process. Also, the second cleaning process is performed after the second product removal process. In the above cases, the cleaning process can be included in the product removal process. For example, the cleaning process can be performed after the above-mentioned plasma process in each of the first product removal process and the second product removal process.

[0174] The number of cleaning processes may be fewer than the number of product removal processes. For example, a cleaning process may be performed only once after the formation of the semiconductor layer 230. In the example shown in FIGS. 8A to 8D , a cleaning process may not be performed after the first product removal process and before the second dry etching process. Furthermore, for example, when the product removal process is performed three times, the cleaning process may be omitted, performed once, twice, or three times. The same applies when the product removal process is performed four or more times. For example, when the product removal process is performed four times, the first cleaning process may be performed after two product removal processes, and then the second cleaning process may be performed after two product removal processes, i.e., after four product removal processes counting from the formation of the semiconductor film 230f. Note that at least one of the above-mentioned wet cleaning, cleaning by heat treatment, ultrasonic cleaning, etc. may be performed two or more times in one cleaning process.

[0175] When performing a cleaning process, the product 233 does not necessarily have to be removed by the product removal process alone, as long as the product 233 can be removed by the cleaning process. For example, if the product 233 can be removed by performing a cleaning process after the above-described plasma process, it is not necessary for all of the product 233 to be removed by the plasma process. In this case, the product removal process can be rephrased as a process for making the product easier to remove, specifically, a process for making the product easier to remove in the cleaning process. Note that, as long as the product 233 can be removed by the cleaning process, the volume of the product 233 may increase by the product removal process.

[0176] The dry etching treatment performed on the semiconductor film is preferably performed under isotropic conditions. For example, when the conductive film that will become the conductive layer 220 is processed by dry etching, the dry etching treatment performed on the semiconductor film is preferably performed under conditions that are more isotropic than the dry etching treatment performed on the conductive film that will become the conductive layer 220. Furthermore, when the groove 290 is formed by dry etching, the dry etching treatment performed on the semiconductor film is preferably performed under conditions that are more isotropic than the dry etching treatment for forming the groove 290. By performing the dry etching treatment on the semiconductor film under isotropic conditions, the region along the sidewall of the groove 290 in the semiconductor film can be easily removed. This can increase the manufacturing yield of semiconductor devices.

[0177] In dry etching, the isotropy can be increased by, for example, reducing the bias power. In addition, the isotropy can be increased by, for example, increasing the pressure of the etching gas. By reducing the bias power, ions generated from the plasma are less likely to be attracted in a direction perpendicular to the substrate, thereby increasing the isotropy. In addition, by increasing the pressure of the etching gas, the mean free path of molecules in the atmosphere becomes shorter. Therefore, collisions between molecules occur more easily, thereby increasing the isotropy.

[0178] 10A to 10E, the conductive film 240f is processed to form the conductive layers 240a and 240b. Specifically, the conductive layers 240a2 and 240b2 are formed from the conductive film 240f2. The conductive layers 240a1 and 240b1 are formed from the conductive film 240f1. The conductive layers 240a and 240b are formed in island shapes facing each other with the groove 290 in between in a plan view.

[0179] The conductive layers 240a and 240b can be formed by removing regions of the conductive film 240f that do not overlap with the mask 231. The conductive film 240f can be processed by etching. In particular, dry etching is preferable because it is suitable for microfabrication. When the conductive film 240f is processed by dry etching, it is preferable to perform the processing under conditions with higher anisotropy than the processing of the semiconductor film 230f.

[0180] 10A to 10E, the mask 231 is removed. The mask 231 can be removed by, for example, wet etching. Alternatively, the mask 231 may be removed by, for example, dry etching.

[0181] The semiconductor film 230f and the conductive film 240f can be processed using the same mask 231. In this case, the number of manufacturing steps of the semiconductor device can be reduced compared to when the semiconductor film 230f and the conductive film 240f are processed using different masks. Note that the semiconductor film 230f and the conductive film 240f may be processed using different masks. In this case, for example, the area of ​​the semiconductor layer 230 in a plan view can be made smaller than the area of ​​the conductive layer 240.

[0182] In the above description, an example is shown in which the conductive film 240f is processed to form the island-shaped conductive layers 240a and 240b after the groove 290 is formed in the conductive film 240f, but one embodiment of the present invention is not limited to this. The conductive film 240f may be processed into an island shape, and then the groove 290 may be formed in the conductive film 240f to form the conductive layers 240a and 240b.

[0183] 11A to 11E, an insulating layer 250 is formed on the semiconductor layer 230. The insulating layer 250 is formed so as to have a region located within a groove 290 having a large aspect ratio. Therefore, the insulating layer 250 is preferably formed using a film formation method with good coverage, and more preferably formed using a CVD method, an ALD method, or the like.

[0184] It is preferable to perform microwave plasma treatment after the formation of the insulating layer 250. By performing the microwave plasma treatment, the concentration of impurities such as hydrogen or water contained in the semiconductor layer 230 can be reduced. Furthermore, a crystalline region of the semiconductor layer 230 may grow. Note that details of the microwave plasma treatment will be described in Embodiment 2.

[0185] In addition, when the insulating layer 250 has a four-layer structure including a fourth insulating layer, a third insulating layer on the fourth insulating layer, a first insulating layer on the third insulating layer, and a second insulating layer on the first insulating layer, microwave plasma treatment may be performed after the formation of the third insulating layer. Furthermore, microwave plasma treatment may be performed again after the formation of the first insulating layer. In this way, microwave plasma treatment in an oxygen-containing atmosphere may be performed multiple times (at least two times or more).

[0186] After the third insulating layer is formed, a process for supplying oxygen to the third insulating layer may be performed. This makes it possible to supply oxygen to the semiconductor layer 230. Note that the above description can be referred to for details of the process for supplying oxygen.

[0187] In this embodiment, the insulating layer 250 is formed by depositing an aluminum oxide film, a silicon oxide film, a hafnium oxide film, and a silicon nitride film in this order using an ALD method.

[0188] 11A to 11E, a conductive film 260f, which will later become the conductive layer 260, is formed on the insulating layer 250. Specifically, the conductive film 260f is formed so as to have a region located inside the groove portion 290.

[0189] 12A to 12E, the conductive film 260f is processed to form a conductive layer 260. The conductive layer 260 is formed on the insulating layer 250 so as to have a region located within the groove 290.

[0190] For example, the conductive layer 260 can be formed in the groove 290 by processing the entire surface of the conductive film 260f by anisotropic etching without forming a mask. Alternatively, the conductive layer 260 can be formed in the groove 290 by performing a planarization process on the conductive film 260f. Chemical mechanical polishing (CMP) is a suitable planarization process. When the conductive layer 260 is formed by performing a planarization process on the conductive film 260f, the upper surface of the conductive layer 260 can be made to coincide or substantially coincide with the upper surface of the insulating layer 250. The conductive layer 260 is formed to extend in a direction parallel to the extension direction of the groove 290. The conductive layer 260 is formed to extend, for example, in the Y direction, similar to the groove 290.

[0191] 13A to 13E, an insulating layer 285 is formed on the conductive layer 260 and the insulating layer 250. Thereafter, the insulating layer 285, the insulating layer 250, the semiconductor layer 230, and the conductive layer 240a2 are processed to form an opening 270a that reaches the conductive layer 240a1. Furthermore, the insulating layer 285, the insulating layer 250, the semiconductor layer 230, and the conductive layer 240b2 are processed to form an opening 270b that reaches the conductive layer 240b1. The opening 270a and the opening 270b can be formed in parallel.

[0192] When forming the openings 270a and 270b, the insulating layer 285, the insulating layer 250, the semiconductor layer 230, the conductive layer 240a2, and the conductive layer 240b2 can be processed by etching. In particular, dry etching is preferable because it is suitable for fine processing. When the insulating layer 285, the insulating layer 250, the semiconductor layer 230, the conductive layer 240a2, and the conductive layer 240b2 are processed by dry etching, it is preferable to perform the processing under conditions with higher anisotropy than the processing of the semiconductor film 230f.

[0193] 14A to 14E , conductive layer 244a is formed to have a region located within opening 270a, and conductive layer 244b is formed to have a region located within opening 270b. For example, conductive layer 244a is formed to fill opening 270a, and conductive layer 244b is formed to fill opening 270b. Conductive layer 244a can be formed to have a region in contact with the top surface of conductive layer 240a1 and a region in contact with the side surface of conductive layer 240a2 within opening 270a. Conductive layer 244b can be formed to have a region in contact with the top surface of conductive layer 240b1 and a region in contact with the side surface of conductive layer 240b2 within opening 270b.

[0194] For example, a conductive film to be the conductive layer 244a and the conductive layer 244b is formed so as to have a region located in the opening 270a and a region located in the opening 270b. Then, planarization treatment is performed on the conductive film to expose the top surface of the insulating layer 285, thereby forming the conductive layer 244a and the conductive layer 244b. CMP treatment is suitable as the planarization treatment. The planarization treatment removes at least a region of the conductive film that overlaps with the top surface of the insulating layer 285. By forming the conductive layer 244a and the conductive layer 244b using CMP treatment, the number of masks can be reduced compared to when the conductive layer 244a and the conductive layer 244b are formed by, for example, etching. In this manner, the transistor 200 is formed.

[0195] 14A to 14E, a conductive layer 245 is formed over the insulating layer 285, the conductive layer 244a, and the conductive layer 244b. For example, a conductive film that will become the conductive layer 245 is formed and then processed to form the conductive layer 245. The conductive film can be processed by etching. In particular, dry etching is preferable because it is suitable for microfabrication. When the conductive film is processed by dry etching, it is preferable to perform the processing under conditions with higher anisotropy than the processing of the semiconductor film 230f.

[0196] The conductive layer 245 can be formed to have a region in contact with the upper surface of the conductive layer 244a and a region in contact with the upper surface of the conductive layer 244b. The conductive layer 245 can also be formed to be in contact with the upper surface of the insulating layer 285. The conductive layer 245 can be formed to extend in the X direction. As described above, the conductive layer 260 can be formed to extend in the Y direction. As a result, the conductive layer 245 intersects with the conductive layer 260 in a plan view.

[0197] The conductive layer 245 can be formed to overlap with the conductive layer 260 with the insulating layer 285 functioning as an interlayer film interposed therebetween. This can reduce parasitic capacitance compared to, for example, a case where the conductive layer 240 is formed to extend in the Y direction without forming the conductive layer 245. Therefore, the semiconductor device of one embodiment of the present invention can be a semiconductor device capable of high-speed operation.

[0198] As described above, the conductive layer 245 intersects with the conductive layer 260 in a plan view, for example, perpendicular or substantially perpendicular to the conductive layer 260. This allows the area where the conductive layer 245 and the conductive layer 260 overlap to be smaller than when the conductive layer 245 and the conductive layer 260 are formed parallel to each other in a plan view. This allows the parasitic capacitance generated between the conductive layer 260 and the conductive layer 245 to be reduced. Therefore, the semiconductor device of one embodiment of the present invention can be a semiconductor device capable of high-speed operation. Note that, for example, when the insulating layer 285 is sufficiently thick and the parasitic capacitance per unit area generated between the conductive layer 260 and the conductive layer 245 is negligibly small, the conductive layer 260 and the conductive layer 245 may be formed parallel to each other in a plan view.

[0199] In this manner, the semiconductor device shown in FIGS. 1A1 to 1E can be manufactured.

[0200] <Constituent Materials of Semiconductor Device> Materials that can be used in the semiconductor device of this embodiment will be described below. Note that each layer that constitutes the semiconductor device of this embodiment may have a single-layer structure or a multilayer structure.

[0201] [Semiconductor Layer] As described above, the semiconductor layer 230 has a channel formation region. The semiconductor layer 230 further has a source region and a drain region. The source region and the drain region are low-resistance regions with higher carrier concentrations than the channel formation region. The semiconductor layer 230 may have a single-layer structure or a stacked structure of two or more layers.

[0202] The crystallinity of the semiconductor material used for the semiconductor layer 230 is not particularly limited, and any of an amorphous semiconductor, a single crystal semiconductor, and a semiconductor having crystallinity other than single crystal (a microcrystalline semiconductor, a polycrystalline semiconductor, or a semiconductor having a crystalline region in part) may be used. Use of a single crystal semiconductor or a crystalline semiconductor is preferable because it can suppress deterioration of transistor characteristics.

[0203] The transistor 200 preferably includes a metal oxide (also referred to as an oxide semiconductor) functioning as a semiconductor in the semiconductor layer 230 including a channel formation region. When a metal oxide functioning as a semiconductor is used for the semiconductor layer 230, the transistor 200 can be referred to as an OS transistor.

[0204] An OS transistor has an oxygen vacancy (V Ｏ ) and impurities, the electrical characteristics are likely to fluctuate and reliability may be reduced. Ｏ H) and generate electrons that serve as carriers. Therefore, if oxygen vacancies are present in the channel formation region of the oxide semiconductor, the OS transistor is likely to be normally on. Therefore, it is preferable that oxygen vacancies and impurities are reduced as much as possible in the channel formation region of the oxide semiconductor. In other words, it is preferable that the carrier concentration of the channel formation region of the oxide semiconductor is reduced and the channel formation region of the oxide semiconductor is made i-type (intrinsic) or substantially i-type.

[0205] On the other hand, the source and drain regions of an OS transistor have more oxygen vacancies than the channel formation region. ＯThe source and drain regions of an OS transistor preferably have a high carrier concentration and low resistance compared to the channel formation region, due to a high concentration of H or an impurity such as hydrogen, nitrogen, or a metal element.

[0206] The band gap of a metal oxide functioning as a semiconductor is preferably 2.0 eV or more, more preferably 2.5 eV or more. By using a metal oxide with a wide band gap for the semiconductor layer 230, the off-state current of the transistor 200 can be reduced. Because the off-state current of an OS transistor is small, the power consumption of the semiconductor device can be sufficiently reduced. Furthermore, because the frequency characteristics of an OS transistor are high, the semiconductor device can operate at high speed.

[0207] For an oxide semiconductor layer that can be used as a semiconductor layer of a transistor according to one embodiment of the present invention, refer to the description in Embodiment 2. Detailed description thereof will be omitted here.

[0208] Note that the semiconductor device of this embodiment may also be applied to a transistor using another semiconductor material in a channel formation region, such as a semiconductor made of a single element or a compound semiconductor.

[0209] Examples of semiconductors made of elemental elements that can be used as semiconductor materials include silicon and germanium. Examples of silicon that can be used as semiconductor materials include single-crystal silicon, polycrystalline silicon, microcrystalline silicon, and amorphous silicon. Examples of polycrystalline silicon include low-temperature polysilicon (LTPS).

[0210] Compound semiconductors that can be used for the semiconductor material include silicon carbide, silicon germanium, gallium arsenide, indium phosphide, boron nitride, and boron arsenide. Boron nitride that can be used for the semiconductor layer preferably has an amorphous structure. Boron arsenide that can be used for the semiconductor layer preferably has a cubic crystal structure. Other examples of compound semiconductors include organic semiconductors and nitride semiconductors. The aforementioned oxide semiconductors are also a type of compound semiconductor. These semiconductor materials may contain impurities as dopants.

[0211] In addition, a transistor in which a layer material functioning as a semiconductor is used for a channel formation region may be applied to the semiconductor device of this embodiment mode. Note that the layer material will be described in detail in Embodiment Mode 6.

[0212] [Insulating Layer] It is preferable to use an inorganic insulating film for each of the insulating layers (insulating layer 210, insulating layer 280, insulating layer 285, insulating layer 250, etc.) included in the semiconductor device. Examples of inorganic insulating films include an oxide insulating film, a nitride insulating film, an oxynitride insulating film, and a nitride oxide insulating film. Examples of oxide insulating films include a silicon oxide film, an aluminum oxide film, a magnesium oxide film, a gallium oxide film, a germanium oxide film, a yttrium oxide film, a zirconium oxide film, a lanthanum oxide film, a neodymium oxide film, a hafnium oxide film, a tantalum oxide film, a cerium oxide film, a gallium zinc oxide film, and a hafnium aluminate film. Examples of nitride insulating films include a silicon nitride film and an aluminum nitride film. Examples of oxynitride insulating films include a silicon oxynitride film, an aluminum oxynitride film, a gallium oxynitride film, an yttrium oxynitride film, and a hafnium oxynitride film. Examples of nitride oxide insulating films include a silicon nitride oxide film and an aluminum nitride oxide film. Furthermore, an organic insulating film may be used for the insulating layer of the semiconductor device.

[0213] For example, as transistors become more miniaturized and highly integrated, problems such as leakage current may occur due to thinner gate insulating layers. Using a high-dielectric-constant (high-k) material for the gate insulating layer allows for lower voltage operation of the transistor while maintaining the physical film thickness. Furthermore, the equivalent oxide thickness (EOT) of the gate insulating layer can be reduced. On the other hand, using a material with a low dielectric constant for the insulating layer that functions as an interlayer film can reduce the parasitic capacitance that occurs between wirings. Therefore, it is preferable to select materials according to the function of the insulating layer. Note that materials with a low dielectric constant also have high dielectric strength.

[0214] Examples of materials with a high relative dielectric constant include aluminum oxide, gallium oxide, hafnium oxide, tantalum oxide, zirconium oxide, hafnium zirconium oxide, oxides containing aluminum and hafnium, oxynitrides containing aluminum and hafnium, oxides containing silicon and hafnium, oxynitrides containing silicon and hafnium, and nitrides containing silicon and hafnium.

[0215] Examples of materials with a low dielectric constant include inorganic insulating materials such as silicon oxide, silicon oxynitride, and silicon nitride oxide, and resins such as polyester, polyolefin, polyamide (nylon, aramid, etc.), polyimide, polycarbonate, and acrylic resin. Other inorganic insulating materials with a low dielectric constant include silicon oxide containing fluorine, silicon oxide containing carbon, and silicon oxide containing carbon and nitrogen. Another example is silicon oxide having vacancies. These silicon oxides may contain nitrogen.

[0216] Furthermore, a material capable of exhibiting ferroelectricity may be used for the insulating layer of a semiconductor device. Examples of materials capable of exhibiting ferroelectricity include metal oxides such as hafnium oxide, zirconium oxide, and hafnium zirconium oxide. Examples of materials capable of exhibiting ferroelectricity include a material obtained by adding element J1 (here, element J1 is one or more selected from zirconium, silicon, aluminum, gadolinium, yttrium, lanthanum, strontium, etc.) to hafnium oxide. Here, the ratio of the number of hafnium atoms to the number of element J1 atoms can be appropriately set; for example, the ratio of the number of hafnium atoms to the number of element J1 atoms can be set to 1:1 or close to that. Examples of materials capable of exhibiting ferroelectricity include a material obtained by adding element J2 (here, element J2 is one or more selected from hafnium, silicon, aluminum, gadolinium, yttrium, lanthanum, strontium, etc.) to zirconium oxide. The ratio of the number of zirconium atoms to the number of atoms of element J2 can be set as appropriate. For example, the ratio of the number of zirconium atoms to the number of atoms of element J2 can be set to 1:1 or close to that. In the above, lanthanum may be replaced with a lanthanoid. Furthermore, lead titanate (PbTiO Ｘ Piezoelectric ceramics having a perovskite structure, such as barium strontium titanate (BST), strontium titanate, lead zirconate titanate (PZT), strontium bismuth tantalate (SBT), bismuth ferrite (BFO), or barium titanate, may also be used.

[0217] Furthermore, examples of materials that may exhibit ferroelectricity include metal nitrides containing element M1, element M2, and nitrogen. Here, element M1 is one or more elements selected from aluminum, gallium, indium, etc. Furthermore, element M2 is one or more elements selected from boron, scandium, yttrium, lanthanum, cerium, neodymium, europium, titanium, zirconium, hafnium, vanadium, niobium, tantalum, chromium, etc. The ratio of the number of atoms of element M1 to the number of atoms of element M2 can be appropriately set. Furthermore, metal oxides containing element M1 and nitrogen may exhibit ferroelectricity even without containing element M2. Furthermore, examples of materials that may exhibit ferroelectricity include materials in which element M3 is added to the above metal nitrides. Furthermore, element M3 is one or more elements selected from magnesium, calcium, strontium, zinc, cadmium, etc. Here, the ratio of the number of atoms of the element M1, the number of atoms of the element M2, and the number of atoms of the element M3 can be set appropriately.

[0218] Furthermore, materials that can have ferroelectricity include SrTaO ２ N and BaTaO ２ Perovskite-type oxynitrides such as N, GaFeO with κ-alumina structure ３ etc.

[0219] In the above description, metal oxides and metal nitrides are used as examples, but the present invention is not limited to these. For example, metal oxynitrides in which nitrogen is added to the aforementioned metal oxides, or metal oxynitrides in which oxygen is added to the aforementioned metal nitrides, may also be used.

[0220] Furthermore, as a material capable of exhibiting ferroelectricity, for example, a mixture or compound made of a plurality of materials selected from the materials listed above can be used. Alternatively, the insulating layer 130 described in embodiment 3 can have a layered structure made of a plurality of materials selected from the materials listed above. Incidentally, the crystal structure (characteristics) of the materials listed above may change depending not only on the film formation conditions but also on various processes, etc., and therefore, in this specification and the like, a material that exhibits ferroelectricity is referred to not only as a ferroelectric but also as a material capable of exhibiting ferroelectricity.

[0221] Metal oxides containing either or both of hafnium and zirconium can have ferroelectricity even in thin films of a few nanometers. Furthermore, metal oxides containing either or both of hafnium and zirconium can have ferroelectricity even in very small areas. Therefore, by using metal oxides containing either or both of hafnium and zirconium, miniaturization of semiconductor devices can be achieved.

[0222] In this specification, a layer of a material that can have ferroelectricity may be referred to as a ferroelectric layer, a metal oxide film, or a metal nitride film. Also, in this specification, a device having such a ferroelectric layer, a metal oxide film, or a metal nitride film may be referred to as a ferroelectric device.

[0223] Ferroelectricity is believed to be manifested by the displacement of oxygen or nitrogen in crystals contained in the ferroelectric layer due to an external electric field. Furthermore, it is believed that the manifestation of ferroelectricity depends on the crystal structure of the crystals contained in the ferroelectric layer. Therefore, for the insulating layer to exhibit ferroelectricity, the insulating layer 130 must contain crystals. In particular, it is preferable for the insulating layer to contain crystals having an orthorhombic crystal structure, as this will result in the manifestation of ferroelectricity. The crystal structure of the crystals contained in the insulating layer may be one or more selected from the group consisting of tetragonal, orthorhombic, monoclinic, and hexagonal. The insulating layer may also have an amorphous structure. In this case, the insulating layer may have a composite structure having an amorphous structure and a crystalline structure.

[0224] Furthermore, adding a Group 3 element in the periodic table to an oxide containing one or both of hafnium and zirconium increases the oxygen vacancy concentration in the oxide, making it easier to form crystals with an orthorhombic crystal structure. This is preferable because it increases the proportion of crystals with an orthorhombic crystal structure and increases the remanent polarization. On the other hand, if the amount of the Group 3 element added is too large, the crystallinity of the oxide may decrease, making it difficult to exhibit ferroelectricity. Therefore, the content of the Group 3 element in the oxide containing one or both of hafnium and zirconium is preferably 0.1 atomic% to 10 atomic%, more preferably 0.1 atomic% to 5 atomic%, and even more preferably 0.1 atomic% to 3 atomic%. Here, the content of the Group 3 element refers to the ratio of the number of atoms of the Group 3 element to the sum of the number of atoms of all metal elements contained in the layer. The Group 3 element is preferably one or more selected from scandium, lanthanum, and yttrium, and more preferably one or both of lanthanum and yttrium.

[0225] Furthermore, a transistor using a metal oxide can have stable electrical characteristics by being surrounded by an insulating layer that has a function of suppressing the permeation of impurities and oxygen. The insulating layer that has a function of suppressing the permeation of impurities and oxygen can be, for example, a single-layer or stacked insulating layer containing one or more elements selected from boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium, and tantalum. Specifically, the insulating layer that has a function of suppressing the permeation of impurities and oxygen can be made of a metal oxide such as aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, or tantalum oxide; a nitride such as aluminum nitride or silicon nitride; or a nitride oxide such as silicon nitride oxide.

[0226] Specifically, examples of materials for the insulating layer that function to suppress the permeation of impurities such as water and hydrogen, and oxygen include metal oxides such as aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, tantalum oxide, and oxides containing aluminum and hafnium (hafnium aluminate). Other examples include nitrides such as aluminum nitride, aluminum titanium nitride, and silicon nitride. Other examples include nitride oxides such as silicon nitride oxide.

[0227] An insulating layer such as a gate insulating layer that is in contact with an oxide semiconductor layer or that is provided near the oxide semiconductor layer is preferably an insulating layer having a region containing oxygen that is released by heating (hereinafter, sometimes referred to as excess oxygen). For example, when an insulating layer having a region containing excess oxygen is in contact with an oxide semiconductor layer or is located near the oxide semiconductor layer, oxygen vacancies in the oxide semiconductor layer can be reduced. Examples of materials for an insulating layer that are likely to form a region containing excess oxygen include silicon oxide, silicon oxynitride, and silicon oxide having vacancies.

[0228] An insulating layer provided in contact with or near an oxide semiconductor layer is preferably a barrier insulating layer against hydrogen, which can suppress diffusion of hydrogen into the oxide semiconductor layer.

[0229] Examples of materials for the insulating layer having the function of capturing or fixing hydrogen include metal oxides such as oxides containing hafnium, oxides containing magnesium, oxides containing aluminum, oxides containing aluminum and hafnium (hafnium aluminate), oxides containing hafnium and zirconium (hafnium zirconium oxide), and oxides containing hafnium and silicon (hafnium silicate). These metal oxides may further contain zirconium, and examples include oxides containing hafnium and zirconium.

[0230] An insulating layer having the function of capturing or fixing hydrogen preferably has an amorphous structure. In a metal oxide having an amorphous structure, some oxygen atoms have dangling bonds, which enhances the ability to capture or fix hydrogen. Therefore, when the insulating layer has an amorphous structure, the function of capturing or fixing hydrogen can be enhanced. For example, an amorphous structure may be realized by adding silicon to the metal oxide. For example, it is preferable to use an oxide containing hafnium and silicon (hafnium silicate).

[0231] By making the insulating layer an amorphous structure, it is possible to suppress the formation of crystal grain boundaries. By suppressing the formation of crystal grain boundaries, it is possible to improve the flatness of the insulating layer. This makes it possible to uniformize the film thickness distribution of the insulating layer and reduce areas with extremely thin film thickness, thereby improving the breakdown voltage of the insulating layer. It is also possible to uniformize the film thickness distribution of a film provided on the insulating layer. Furthermore, by suppressing the formation of crystal grain boundaries in the insulating layer, it is possible to reduce leakage current caused by defect levels at the crystal grain boundaries. Therefore, the insulating layer can function as an insulating film with low leakage current.

[0232] The insulating layer may partially include either or both of a crystalline region and a grain boundary.

[0233] The ability to capture or fix a corresponding substance can also be said to have the property of making it difficult for the corresponding substance to diffuse. Therefore, the ability to capture or fix a corresponding substance can be rephrased as barrier properties.

[0234] In this specification and the like, a barrier insulating layer refers to an insulating layer having barrier properties. The barrier properties refer to a property that makes it difficult for a corresponding substance to diffuse (also referred to as a property that makes it difficult for a corresponding substance to permeate, a property that the permeability of a corresponding substance is low, or a function that suppresses the diffusion of a corresponding substance). Note that hydrogen when described as a corresponding substance includes, for example, a hydrogen atom, a hydrogen molecule, a water molecule, and OH. −Furthermore, unless otherwise specified, impurities when described as corresponding substances refer to impurities in the channel formation region or semiconductor layer, and include, for example, hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, and nitrogen oxide molecules (N ２ O, NO, and NO ２ The term "oxygen" when used in reference to a corresponding substance refers to at least one of an oxygen atom, an oxygen molecule, and the like.

[0235] Examples of materials for the barrier insulating layer against hydrogen include aluminum oxide, magnesium oxide, hafnium oxide, gallium oxide, silicon nitride, and silicon nitride oxide.

[0236] Examples of materials for the barrier insulating layer against oxygen include oxides containing one or both of aluminum and hafnium, magnesium oxide, gallium oxide, gallium zinc oxide, silicon nitride, and silicon nitride oxide. Examples of oxides containing one or both of aluminum and hafnium include aluminum oxide, hafnium oxide, oxides containing aluminum and hafnium (hafnium aluminate), and oxides containing hafnium and silicon (hafnium silicate).

[0237] Since the insulating layer 210 functions as an interlayer film, it is preferable to use the above-mentioned material having a low relative dielectric constant. By using a material having a low relative dielectric constant for the interlayer film, the parasitic capacitance generated between wirings can be reduced.

[0238] A barrier insulating layer against hydrogen is preferably used for the insulating layer 210. When the insulating layer 210 provided below the semiconductor layer 230 has a barrier property against hydrogen, diffusion of hydrogen from below the transistor 200 to the semiconductor layer 230 can be suppressed. For example, a silicon nitride film is preferably used as the insulating layer 210.

[0239] An insulating layer having a function of capturing or fixing hydrogen is preferably used as the insulating layer 210. When the insulating layer 210 has the function of capturing or fixing hydrogen, hydrogen in the semiconductor layer 230 can be diffused into the insulating layer 210 and the hydrogen can be captured or fixed. Therefore, the hydrogen concentration in the semiconductor layer 230 can be reduced.

[0240] The concentration of impurities such as hydrogen or water in the insulating layer 210 is preferably reduced, which can prevent impurities such as hydrogen or water from entering the channel formation region of the semiconductor layer 230.

[0241] 3A shows an example in which the insulating layer 210 has a single-layer structure. Note that the insulating layer 210 can have a stacked structure of two or more layers. For example, the insulating layer 210 can have a two-layer structure of a first insulating layer and a second insulating layer on the first insulating layer. In this case, for example, it is preferable to use a barrier insulating layer against hydrogen as the first insulating layer and an insulating layer having a function of capturing or fixing hydrogen as the second insulating layer. Specifically, it is preferable to use a silicon nitride film as the first insulating layer and a hafnium oxide film, a hafnium silicate film, or an aluminum oxide film as the second insulating layer.

[0242] Since the insulating layer 280 functions as an interlayer film, it is preferable to use the above-mentioned material with a low dielectric constant. By using a material with a low dielectric constant for the interlayer film, the parasitic capacitance generated between wirings can be reduced. For example, silicon oxide or silicon oxynitride can be used as the insulating layer 280.

[0243] The concentration of impurities such as hydrogen or water in the insulating layer 280 is preferably reduced. This can prevent impurities such as hydrogen or water from entering the channel formation region of the semiconductor layer 230.

[0244] For example, an insulating layer having a region containing excess oxygen can be formed by sputtering in an oxygen-containing atmosphere. Furthermore, by using a sputtering method that does not require the use of hydrogen-containing molecules in the deposition gas, the hydrogen concentration in the insulating layer 280 can be reduced. By depositing at least a portion of the layers constituting the insulating layer 280 by sputtering, oxygen can be supplied from the insulating layer 280 to the channel formation region of the semiconductor layer 230, thereby reducing oxygen vacancies and V. Ｏ H can be reduced.

[0245] Note that the thickness of the insulating layer 280 affects the channel length of the transistor 200 , and therefore the thickness of the insulating layer 280 is set appropriately in accordance with the design value of the channel length of the transistor 200 .

[0246] FIG. 3A shows an example in which the insulating layer 280 has a single-layer structure. Note that the insulating layer 280 can have a stacked structure of two or more layers. For example, as shown in FIG. 15, the insulating layer 280 can have a three-layer structure including an insulating layer 280_1, an insulating layer 280_2 on the insulating layer 280_1, and an insulating layer 280_3 on the insulating layer 280_2. In this case, it is preferable to use the above-described material with a low relative dielectric constant for the insulating layer 280_2, and to use barrier insulating layers against oxygen for the insulating layers 280_1 and 280_3. This can suppress oxidation of the conductive layer 220, the conductive layer 240a, and the conductive layer 240b, thereby preventing high resistance.

[0247] For example, it is preferable to use a silicon nitride film or an aluminum oxide film for the insulating layer 280_1 and the insulating layer 280_3, and a silicon oxide film for the insulating layer 280_2. Note that each of the insulating layer 280_1 and the insulating layer 280_3 may have a stacked structure of two or more layers.

[0248] It is preferable to use a barrier insulating layer against hydrogen as the insulating layer 250. When the insulating layer 250 provided on the semiconductor layer 230 has a barrier property against hydrogen, it is possible to suppress diffusion of hydrogen contained in the conductive layer 260 into the semiconductor layer 230. For example, a silicon nitride film is suitable as the insulating layer 250 because it has a high barrier property against hydrogen.

[0249] Furthermore, since the insulating layer 250 is in contact with the semiconductor layer 230, it is preferable to use an insulating layer having a function of capturing or fixing hydrogen. This allows hydrogen contained in the semiconductor layer 230 to be more effectively captured or fixed. Therefore, the hydrogen concentration in the semiconductor layer 230 (particularly, the hydrogen concentration in the channel formation region of the transistor) can be reduced. Therefore, the V Ｏ By reducing H, the channel forming region can be made i-type or substantially i-type.

[0250] In addition, an insulating layer having a region containing excess oxygen is preferably used as the insulating layer 250. This allows oxygen to be supplied from the insulating layer 250 to the semiconductor layer 230, thereby reducing oxygen vacancies in the semiconductor layer 230. A silicon oxide film, a silicon oxynitride film, or the like is suitable as the insulating layer 250 because it has a structure that is stable against heat.

[0251] 3A shows an example in which the insulating layer 250 has a single layer structure. The insulating layer 250 can have a stacked structure of two or more layers. In this case, the insulating layer 250 is preferably formed of two or more types of films. By forming the insulating layer 250 into two or more types of films, multiple functions can be imparted to the insulating layer 250. Examples of the functions of the insulating layer 250 include a function of extracting hydrogen from the semiconductor layer 230 and a function of suppressing diffusion of hydrogen into the semiconductor layer 230.

[0252] For example, the insulating layer 250 can have a two-layer structure including a first insulating layer and a second insulating layer on the first insulating layer. In this case, the first insulating layer is in contact with the semiconductor layer 230. For example, it is preferable to use an insulating layer having a function of capturing or fixing hydrogen as the first insulating layer, and a barrier insulating layer against hydrogen as the second insulating layer. With such a structure, the hydrogen concentration in the semiconductor layer 230 can be reduced and diffusion of hydrogen into the semiconductor layer 230 can be suppressed. Therefore, a highly reliable transistor can be realized. For example, a hafnium oxide film or a hafnium silicate film can be used as the first insulating layer, and a silicon nitride film can be used as the second insulating layer.

[0253] Alternatively, for example, it is preferable to use an insulating layer having a region containing excess oxygen as the first insulating layer and a barrier insulating layer against hydrogen as the second insulating layer. Alternatively, for example, it is preferable to use an insulating layer having a region containing excess oxygen as the first insulating layer and an insulating layer having a function of capturing or fixing hydrogen as the second insulating layer. With such a structure, the amount of oxygen vacancies and the hydrogen concentration in the semiconductor layer 230 can be reduced, and diffusion of hydrogen into the semiconductor layer 230 can be suppressed. Therefore, a highly reliable transistor can be realized.

[0254] Furthermore, for example, the insulating layer 250 can have a third insulating layer between the semiconductor layer 230 and the first insulating layer. In other words, the insulating layer 250 can have a three-layer structure including a third insulating layer, a first insulating layer on the third insulating layer, and a second insulating layer on the first insulating layer.

[0255] For example, it is preferable to use an insulating layer having a region containing excess oxygen or an insulating layer containing a material with a low dielectric constant as the third insulating layer, an insulating layer having a function of capturing or fixing hydrogen as the first insulating layer, and an insulating layer having barrier properties against hydrogen and oxygen as the second insulating layer. The third insulating layer is preferably a silicon oxide film or a silicon oxynitride film. By using an oxide film for the third insulating layer in contact with the semiconductor layer 230, oxygen can be supplied to the semiconductor layer 230. Furthermore, providing the second insulating layer can suppress diffusion of oxygen contained in the third insulating layer into the conductive layer 260, thereby suppressing oxidation of the conductive layer 260. Furthermore, a decrease in the amount of oxygen supplied from the third insulating layer to the semiconductor layer 230 can be suppressed.

[0256] Furthermore, for example, the insulating layer 250 can have a fourth insulating layer between the semiconductor layer 230 and the third insulating layer. In other words, the insulating layer 250 can have a four-layer structure including a fourth insulating layer, a third insulating layer on the fourth insulating layer, a first insulating layer on the third insulating layer, and a second insulating layer on the first insulating layer.

[0257] An insulating layer having a barrier property against oxygen is preferably used as the fourth insulating layer. Note that the first to third insulating layers can have the same structure as the layers used in the three-layer structure described above. The fourth insulating layer is a layer in contact with the semiconductor layer 230 and the conductive layer 240. The fourth insulating layer having a barrier property against oxygen can prevent oxygen from being released from the semiconductor layer 230. Furthermore, the side surfaces of the conductive layer 240 can be prevented from being oxidized and an oxide film can be prevented from being formed on the side surfaces. This can prevent a decrease in on-state current or a decrease in field-effect mobility of the transistor 200.

[0258] For example, an aluminum oxide film may be used as the fourth insulating layer. The aluminum oxide film has a function of capturing or fixing hydrogen, and is therefore suitable as the fourth insulating layer in contact with the semiconductor layer 230. Specifically, the insulating layer 250 preferably has a four-layer structure in which an aluminum oxide film, a silicon oxide film, a hafnium oxide film, and a silicon nitride film are stacked in this order from the semiconductor layer 230 side.

[0259] The insulating layer 250 is preferably a thin film. For example, by setting the thickness of the insulating layer 250 to 1 nm or more and 20 nm or less, preferably 3 nm or more and 10 nm or less, the subthreshold swing value (also referred to as S value), which is one of the transistor characteristics, can be reduced. Note that the S value refers to the amount of change in gate voltage when the drain current is changed by one order of magnitude while the drain voltage is constant in the subthreshold region.

[0260] The thickness of each layer constituting the insulating layer 250 is preferably 0.1 nm to 10 nm, more preferably 0.1 nm to 5 nm, more preferably 0.5 nm to 5 nm, more preferably 1 nm to 5 nm, and even more preferably 1 nm to 3 nm. Each layer constituting the insulating layer 250 preferably has a region with the above-mentioned thickness in at least a portion thereof.

[0261] Typically, the film thicknesses of the fourth insulating layer, the third insulating layer, the first insulating layer, and the second insulating layer are 1 nm, 2 nm, 2 nm, and 1 nm, respectively. For example, as shown in FIG. 16A , when the insulating layer 250 has a four-layer stacked structure including insulating layers 250a, 250b, 250c, and 250d, the insulating layer 250a may be made of aluminum oxide having a film thickness of 1 nm, the insulating layer 250b may be made of silicon oxide having a film thickness of 2 nm, the insulating layer 250d may be made of hafnium oxide, hafnium zirconium oxide, or hafnium zirconium oxide containing yttrium having a film thickness of 2 nm, and the insulating layer 250c may be made of silicon nitride having a film thickness of 1 nm. Here, the insulating layer 250a corresponds to the fourth insulating layer, the insulating layer 250b corresponds to the third insulating layer, the insulating layer 250d corresponds to the first insulating layer, and the insulating layer 250c corresponds to the second insulating layer. In this case, insulating layer 250 has insulating layer 250a on semiconductor layer 230, insulating layer 250b on insulating layer 250a, insulating layer 250d on insulating layer 250b, and insulating layer 250c on insulating layer 250d. However, as shown in Fig. 16A etc., when viewed locally within groove 290, it can also be considered that insulating layer 250a is provided inside semiconductor layer 230, insulating layer 250b is provided inside insulating layer 250a, insulating layer 250d is provided inside insulating layer 250b, and insulating layer 250c is provided inside insulating layer 250d.

[0262] In addition, in forming the insulating layer 250 having a stacked structure of multiple insulating films, it is preferable to use an atomic layer deposition (ALD) process two or more times. For example, it is preferable that two or more of the multiple insulating films included in the insulating layer 250 are formed using the ALD process. By forming at least two or more types of insulating films using the ALD process, it is possible to improve the coverage and film thickness uniformity of the insulating layer 250. Furthermore, it is possible to increase productivity by successively forming two or more types of films, for example, two or more types of insulating films, using the ALD process.

[0263] 16A , an insulator having the function of capturing or fixing hydrogen can be provided in the insulating layer 250d. For example, it is preferable to use an oxide containing hafnium as the insulating layer 250d. Examples of oxides containing hafnium that can be used include hafnium oxide, hafnium aluminate, hafnium silicate, hafnium zirconium oxide, and hafnium zirconium oxide containing yttrium. Furthermore, hafnium zirconium oxide containing a lanthanoid such as lanthanum can also be used as the insulating layer 250d.

[0264] By providing the insulating layer 250d between the insulating layer 250c and the insulating layer 250b, hydrogen contained in the insulating layer 250b and the like can be more effectively captured and fixed. The channel formation region of the semiconductor layer 230 and the insulating layers 250a and 250d, which have the function of capturing and fixing hydrogen, are provided below the insulating layer 250c, which has the function of suppressing hydrogen diffusion. In the region where hydrogen diffusion from above is blocked by the insulating layer 250c, hydrogen contained in the channel formation region of the semiconductor layer 230 and the like can be captured or fixed by the insulating layers 250a and 250d. This reduces the hydrogen concentration in the semiconductor layer 230, thereby suppressing a negative shift in the initial characteristics of the transistor 200 and enabling it to be normally off. Furthermore, negative drift degradation in a +GBT (Gate Bias-Temperature) stress test can be suppressed.

[0265] Note that a configuration in which insulating layers 250a, 250b, and 250d are provided without providing insulating layer 250c may also be used. In this case, it is preferable to provide an insulator (e.g., silicon nitride) having a function of suppressing hydrogen diffusion in insulating layer 285 on insulating layer 250. With such a configuration, semiconductor layer 230 and insulating layers 250a and 250d having a function of capturing or fixing hydrogen are formed in a region covered with silicon nitride, which has a high hydrogen barrier property. Therefore, hydrogen contained in the channel formation region of semiconductor layer 230 can be captured or fixed by insulating layer 250a and insulating layer 250d.

[0266] By adopting the above-described structure, the channel formation region can be made i-type or substantially i-type, and the source region and drain region can be made low-resistance regions, thereby providing a semiconductor device with excellent electrical characteristics. Furthermore, by adopting the above-described structure, the semiconductor device can have excellent electrical characteristics even when miniaturized or highly integrated. Furthermore, miniaturizing the transistor 200 can improve high-frequency characteristics. Specifically, the cutoff frequency can be improved.

[0267] Furthermore, the hafnium-containing metal oxide used for the insulating layer 250d preferably functions as a high-k material. This configuration allows the gate potential applied during transistor operation to be reduced while maintaining the physical thickness of the gate insulator. Furthermore, it also allows the equivalent oxide thickness (EOT) of the insulator functioning as the gate insulator to be reduced.

[0268] Furthermore, it is preferable that the insulating layer 250d has ferroelectricity. For example, the insulating layer 250d can be made of ferroelectric hafnium zirconium oxide, hafnium zirconium oxide containing yttrium, or the like. The insulating layer 250d may also have a structure in which a layer of hafnium zirconium oxide is stacked on a layer of hafnium zirconium oxide containing yttrium. Note that when a ferroelectric material is used for the insulating layer 250d, the insulating layer 250d does not necessarily need to have the function of capturing or fixing hydrogen. For example, the insulating layer 250d can be made of the above-mentioned materials that can have ferroelectricity.

[0269] In this way, by using a ferroelectric material for the insulating layer 250d, the transistor 200 can function as a Ferroelectric Field Effect Transistor (FeFET). The FeFET functions as a memory element by itself. Therefore, the structure of the memory element can be made smaller than that of a Dynamic Random Access Memory (DRAM) type memory element having a transistor and a capacitor. Therefore, miniaturization and high integration of a memory device including the transistor 200 can be achieved. Furthermore, productivity of a memory device including the transistor 200 can be improved.

[0270] Although the above description has been given of a structure in which the insulating layer 250 has a three-layer structure of insulating layers 250a to 250c or a four-layer structure of insulating layers 250a to 250d, the present invention is not limited to this. The insulating layer 250 can also have a single-layer structure, a two-layer structure, or a stacked structure of five or more layers. The insulating layer 250 can also have a structure including at least one of the insulating layers 250a to 250d. For example, the insulating layer 250 can also have a single-layer structure of the insulating layer 250c. In this case, the insulating layer 250 can also be formed of a single layer of hafnium zirconium oxide. By forming the insulating layer 250 using one, two, or three of the insulating layers 250a to 250d, the manufacturing process of the semiconductor device can be simplified and productivity can be improved.

[0271] When the insulating layer 250 has a four-layer structure or a five-layer structure, it can also have a stacked structure such as those shown in Figures 16B to 16F. Figure 16B shows an example of an insulating layer 250 having a stacked structure including an insulating layer 250a on the semiconductor layer 230, an insulating layer 250d on the insulating layer 250a, an insulating layer 250b on the insulating layer 250d, and an insulating layer 250c on the insulating layer 250b. In other words, the insulating layer 250 shown in Figure 16B is the insulating layer 250 shown in Figure 16A, with the positions of the insulating layer 250b and the insulating layer 250d swapped. For example, the insulating layer 250a can be made of aluminum oxide with a thickness of 1 nm, the insulating layer 250d can be made of hafnium zirconium oxide or hafnium zirconium oxide containing yttrium with a thickness of 2 nm, the insulating layer 250b can be made of silicon oxide with a thickness of 2 nm, and the insulating layer 250c can be made of silicon nitride with a thickness of 1 nm. Alternatively, the insulating layer 250d may have a structure in which a layer of hafnium zirconium oxide is stacked on a layer of hafnium zirconium oxide containing yttrium. However, the insulating layers 250a to 250d are not limited to the above structure, and the insulating materials described above can be appropriately selected for the insulating layers 250a to 250d, and the film thicknesses of the insulating layers 250a to 250d can also be appropriately selected. By stacking the insulating layers 250a to 250d as shown in FIG. 16B, the insulating layer 250a and the insulating layer 250d, which have the function of capturing or fixing hydrogen, are provided adjacent to each other, thereby enabling more effective capture and fixation of hydrogen.

[0272] 16C, the positions of insulating layer 250c and insulating layer 250b included in insulating layer 250 of Fig. 16A can be interchanged. In this case, insulating layer 250 has a stacked structure including insulating layer 250a on semiconductor layer 230, insulating layer 250d on insulating layer 250a, insulating layer 250c on insulating layer 250d, and insulating layer 250b on insulating layer 250c.

[0273] 16B, insulating layer 250c may be provided in contact with the upper and lower surfaces of insulating layer 250b. In this case, as shown in FIG. 16D, insulating layer 250 has a stacked structure including insulating layer 250a on semiconductor layer 230, insulating layer 250d on insulating layer 250a, insulating layer 250c1 on insulating layer 250d, insulating layer 250b on insulating layer 250c1, and insulating layer 250c2 on insulating layer 250b. Here, insulating layers 250c1 and 250c2 may be made of any of the insulators that can be used for insulating layer 250c. For example, insulating layers 250c1 and 250c2 may each be made of silicon nitride with a thickness of 1 nm.

[0274] 16E shows an example in which insulating layer 250 has a stacked structure including insulating layer 250a on semiconductor layer 230, insulating layer 250b on insulating layer 250a, insulating layer 250d1 on insulating layer 250b, insulating layer 250c on insulating layer 250d1, and insulating layer 250d2 on insulating layer 250c. That is, insulating layer 250 shown in FIG. 16E has a configuration in which insulators that can be used for insulating layer 250d are provided in contact with the upper and lower surfaces of insulating layer 250c in insulating layer 250 shown in FIG. 16A. Here, insulating layer 250d1 can be made of an insulator (e.g., hafnium oxide) that has the function of capturing or fixing hydrogen, and insulating layer 250d2 can be made of an insulator having ferroelectric properties (e.g., hafnium zirconium oxide or hafnium zirconium oxide containing yttrium). Alternatively, the insulating layer 250d2 may have a structure in which a layer of hafnium zirconium oxide is stacked on a layer of hafnium zirconium oxide containing yttrium. By using a ferroelectric material for the insulating layer 250d2 with such a structure, the transistor 200 can function as an FeFET. Furthermore, since the insulating layer 250d1 can capture or fix hydrogen, the electrical characteristics and reliability of the transistor 200 can be improved.

[0275] Furthermore, when an insulating layer 250d2 is formed and a ferroelectric material such as hafnium zirconium oxide is used for the insulating layer 250d2, a conductive layer 252 can be provided in contact with the lower surface of the insulating layer 250d2, as shown in FIG. 16F. The conductive layer 252 is preferably made of a material that easily generates polarization in the insulating layer 250d2, such as titanium nitride. In this case, the lower portion of the conductive layer 260 that contacts the insulating layer 250d2 is also preferably made of titanium nitride. This configuration allows the insulating layer 250d2 to be ferroelectric, allowing the transistor 200 to function as an FeFET.

[0276] [Conductive Layer] The conductive layers (conductive layer 220, conductive layer 240, conductive layer 260, conductive layer 244, conductive layer 245, etc.) included in the semiconductor device preferably contain a metal element selected from aluminum, chromium, copper, silver, gold, platinum, zinc, tantalum, nickel, titanium, iron, cobalt, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, lanthanum, etc., or an alloy containing the above-mentioned metal element as a component, or an alloy combining the above-mentioned metal elements. As the alloy containing the above-mentioned metal element as a component, a nitride of the alloy or an oxide of the alloy may be used. For example, tantalum nitride, titanium nitride, nitride containing titanium and aluminum, nitride containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxide containing strontium and ruthenium, oxide containing lanthanum and nickel, etc. are preferably used. Furthermore, semiconductors with high electrical conductivity, such as polycrystalline silicon containing impurity elements such as phosphorus, and silicides such as nickel silicide may also be used.

[0277] In addition, conductive materials containing nitrogen, such as nitrides containing tantalum, nitrides containing titanium, nitrides containing molybdenum, nitrides containing tungsten, nitrides containing ruthenium, nitrides containing tantalum and aluminum, or nitrides containing titanium and aluminum, conductive materials containing oxygen, such as ruthenium oxide, oxides containing strontium and ruthenium, or oxides containing lanthanum and nickel, and materials containing metal elements such as titanium, tantalum, or ruthenium, are preferred because they are conductive materials that are resistant to oxidation, have a function of suppressing oxygen diffusion, or maintain low electrical resistance even when absorbing oxygen. Examples of conductive materials containing oxygen include indium oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide (In—Sn oxide, also referred to as ITO), indium tin oxide containing titanium oxide, indium tin oxide containing silicon oxide (also referred to as ITSO), indium zinc oxide (In—Zn oxide, also referred to as IZO (registered trademark)), and indium zinc oxide containing tungsten oxide. In this specification and the like, a conductive film formed using a conductive material containing oxygen may be referred to as an oxide conductive film.

[0278] Conductive materials containing tungsten, copper, or aluminum as a main component are preferred because they have high conductivity.

[0279] Furthermore, a plurality of conductive layers formed from the above materials may be stacked. For example, a stacked structure may be formed by combining the above-described material containing a metal element and a conductive material containing oxygen. A stacked structure may be formed by combining the above-described material containing a metal element and a conductive material containing nitrogen. A stacked structure may be formed by combining the above-described material containing a metal element, a conductive material containing oxygen, and a conductive material containing nitrogen.

[0280] When a metal oxide is used for the channel formation region of a transistor, the conductive layer that functions as a gate electrode preferably has a stacked structure that combines a material containing the metal element and a conductive material containing oxygen. In this case, the conductive material containing oxygen is preferably provided on the channel formation region side. By providing the conductive material containing oxygen on the channel formation region side, oxygen desorbed from the conductive material is easily supplied to the channel formation region.

[0281] The conductive layer 220 and the conductive layer 240 are conductive layers in contact with the semiconductor layer 230, and therefore, it is preferable to use a conductive material that is resistant to oxidation, a conductive material that maintains low electrical resistance even when oxidized, a metal oxide having conductivity (also referred to as an oxide conductor), or a conductive material that has a function of suppressing oxygen diffusion, for each of them. Examples of the conductive material include a conductive material containing nitrogen and a conductive material containing oxygen. This can suppress a decrease in the conductivity of the conductive layer 220 and the conductive layer 240.

[0282] By using a conductive material containing oxygen for the conductive layer 220, the conductive layer 220 can maintain its conductivity even if it absorbs oxygen. Similarly, by using a conductive material containing oxygen for the conductive layer 240, the conductive layer 240 can maintain its conductivity even if it absorbs oxygen. Furthermore, even when an insulating layer containing oxygen such as hafnium oxide is used as the insulating layer 210, the conductive layer 220 is preferably able to maintain its conductivity. For example, ITO, ITSO, In—Zn oxide, or the like is preferably used for each of the conductive layer 220 and the conductive layer 240.

[0283] When the conductive layer 220 and the conductive layer 240 each have a stacked structure, the contact resistance between the conductive layer 220 and the semiconductor layer 230 and between the conductive layer 240 and the semiconductor layer 230 can be reduced by using a conductive material containing oxygen for the layer in the stacked structure that has the largest contact area with the semiconductor layer 230.

[0284] The conductive layer 220 shown in FIG. 3A has a two-layer structure including a conductive layer 220_1 and a conductive layer 220_2 over the conductive layer 220_1. In this case, the conductive layer 220_2 is preferably made of a conductive material that is resistant to oxidation, a conductive material that maintains low electrical resistance even when oxidized, a conductive metal oxide, or a conductive material that has a function of suppressing oxygen diffusion. The conductive layer 220_2 is preferably made of, for example, a conductive material containing oxygen. The conductive layer 220_1 is preferably made of a material having higher conductivity than the conductive layer 220_2. Specifically, the conductive layer 220_2 is preferably made of an oxide conductor (e.g., ITO, ITSO, or In—Zn oxide), and the conductive layer 220_1 is preferably made of tungsten. The conductive layer 220_1 may also be made of ruthenium, titanium nitride, tantalum nitride, or the like. By using an oxide conductor for the conductive layer 220_2 that is mainly in contact with the semiconductor layer 230, the contact resistance with the semiconductor layer 230 can be reduced. Furthermore, when a material having higher conductivity than an oxide conductor is used for the layer forming the conductive layer 220, the conductivity of the conductive layer 220 can be increased.

[0285] Note that a conductive material containing oxygen can be used for the conductive layer 220_1, and a material having higher conductivity than the conductive layer 220_1 can be used for the conductive layer 220_2. In this case, a highly conductive material is used for the layer of the conductive layer 220 that is closest to the channel formation region of the semiconductor layer 230. Therefore, the current path between the source and the drain can be shortened, and the on-state current of the transistor 200 can be increased.

[0286] 3A illustrates an example in which the conductive layer 220_1 and the conductive layer 220_2 each have a single-layer structure. Note that one or both of the conductive layer 220_1 and the conductive layer 220_2 may have a stacked structure of two or more layers. For example, as illustrated in FIG. 17 , the conductive layer 220_1 has a two-layer structure including a conductive layer 220_11 and a conductive layer 220_12 on the conductive layer 220_11. In this case, the conductive layer 220 has a three-layer structure including the conductive layer 220_11, the conductive layer 220_12 on the conductive layer 220_11, and the conductive layer 220_2 on the conductive layer 220_12. For example, it is preferable to use a conductive material that is resistant to oxidation or a conductive material that has a function of suppressing oxygen diffusion as the conductive layer 220_11, a material with high conductivity as the conductive layer 220_12, and a conductive material containing oxygen (more preferably, an oxide conductor) as the conductive layer 220_2. Specifically, it is preferable to use titanium nitride for the conductive layer 220_11, tungsten for the conductive layer 220_12, and an oxide conductor (e.g., ITO, ITSO, or In—Zn oxide) for the conductive layer 220_2. In this case, the titanium nitride film is in contact with the insulating layer 210, and the oxide conductive film is in contact with the semiconductor layer 230. Furthermore, an oxide conductor is used for the layer closest to the channel formation region of the semiconductor layer 230. Compared with tungsten, an oxide conductor has lower contact resistance with the semiconductor layer 230, and therefore the current path between the source and drain can be shortened, and the on-state current of the transistor 200 can be increased. With such a structure, the conductive layer 220 can maintain conductivity even when in contact with the semiconductor layer 230. Furthermore, when an oxide insulating layer is used for the insulating layer 210, excessive oxidation of the conductive layer 220 by the insulating layer 210 can be suppressed. Furthermore, when a metal material (tungsten here) having higher conductivity than an oxide conductor and titanium nitride is used for the conductive layer 220_12, the conductivity of the conductive layer 220 can be increased.

[0287] The conductive layer 240a shown in FIG. 3A has a two-layer structure including a conductive layer 240a1 and a conductive layer 240a2 on the conductive layer 240a1. In this case, for example, it is preferable to use a conductive material containing oxygen for the conductive layer 240a2 and a material having higher conductivity than the conductive layer 240a2 for the conductive layer 240a1. Specifically, it is preferable to use an oxide conductor (e.g., ITO, ITSO, or In—Zn oxide) for the conductive layer 240a2 and tungsten for the conductive layer 240a1. Ruthenium, titanium nitride, tantalum nitride, or the like may also be used for the conductive layer 240a1. Using an oxide conductor for the conductive layer 240a2, which is mainly in contact with the semiconductor layer 230, can reduce contact resistance with the semiconductor layer 230. Furthermore, using a material having higher conductivity than an oxide conductor for the layers constituting the conductive layer 240a can increase the conductivity of the conductive layer 240a.

[0288] Note that a conductive material containing oxygen can be used for the conductive layer 240a1, and a material having higher conductivity than the conductive layer 240a1 can be used for the conductive layer 240a2. In this case, an oxide conductor is used for the layer of the conductive layer 240a that is closest to the channel formation region of the semiconductor layer 230. Therefore, the current path between the source and the drain can be shortened, and the on-state current of the transistor 200 can be increased.

[0289] The conductive layer 260 has a region that functions as a gate electrode. The conductive layer 260 is preferably made of a highly conductive material such as tungsten. Furthermore, the conductive layer 260 is preferably made of a conductive material that is resistant to oxidation, or a conductive material that has a function of suppressing oxygen diffusion. As described above, examples of the conductive material include a conductive material containing nitrogen (e.g., titanium nitride or tantalum nitride) and a conductive material containing oxygen (e.g., ruthenium oxide). This can suppress a decrease in the conductivity of the conductive layer 260.

[0290] Furthermore, the conductive layer 260 preferably uses a conductive material containing oxygen and a metal element contained in the metal oxide in which the channel is formed. Alternatively, the conductive material containing the aforementioned metal element and nitrogen (e.g., titanium nitride, tantalum nitride, etc.) may be used. Alternatively, one or more selected from ITO, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, In—Zn oxide, and ITSO may be used. Alternatively, indium gallium zinc oxide containing nitrogen may be used. Using such a material may allow hydrogen contained in the metal oxide in which the channel is formed to be captured. Alternatively, hydrogen introduced from an outer insulating layer or the like may be captured.

[0291] FIG. 3A shows an example in which the conductive layer 260 has a single-layer structure. The conductive layer 260 can have a stacked structure of two or more layers. The conductive layer 260 can have, for example, a two-layer structure including a first conductive layer and a second conductive layer on the first conductive layer. In this case, it is preferable to use, for example, a titanium nitride film as the first conductive layer and a tungsten film as the second conductive layer. Alternatively, it is preferable to use a tantalum nitride film as the first conductive layer and a copper film as the second conductive layer. Such a structure can increase the conductivity of the conductive layer 260.

[0292] The conductive layer 260 may also have a stacked structure of three or more layers, such as a tantalum nitride film, a titanium nitride film on the tantalum nitride film, and a tungsten film on the titanium nitride film.

[0293] The conductive layer 244 and the conductive layer 245 can be formed using a material that can be used for the conductive layer 240. For example, a high-melting-point material that has both heat resistance and conductivity, such as tungsten or molybdenum, can be used for the conductive layer 244 and the conductive layer 245. Alternatively, a low-resistance conductive material, such as aluminum or copper, can be used. By using a low-resistance conductive material, wiring resistance can be reduced.

[0294] 3A shows an example in which the conductive layer 244 and the conductive layer 245 have a single-layer structure. Note that the conductive layer 244 and the conductive layer 245 can have a stacked structure of two or more layers.

[0295] [Substrate] Substrates on which transistors are formed can include, for example, insulating substrates, semiconductor substrates, or conductive substrates. Examples of insulating substrates include glass substrates, quartz substrates, sapphire substrates, stabilized zirconia substrates (e.g., yttria-stabilized zirconia substrates), and resin substrates. Examples of semiconductor substrates include semiconductor substrates made of silicon or germanium, or compound semiconductor substrates made of silicon carbide, silicon germanium, gallium arsenide, indium phosphide, zinc oxide, or gallium oxide. Examples of semiconductor substrates include those having an insulating region within the semiconductor substrate, such as an SOI (Silicon-On-Insulator) substrate. Examples of conductive substrates include graphite substrates, metal substrates, alloy substrates, and conductive resin substrates. Examples of substrates include substrates having a metal nitride or a metal oxide. Examples of substrates include substrates having a conductor or semiconductor provided on an insulating substrate, substrates having a conductor or insulator provided on a semiconductor substrate, and substrates having a semiconductor or insulator provided on a conductive substrate. Alternatively, a substrate provided with elements may be used, such as a capacitor element, a resistor element, a switch element, a light-emitting element, or a memory element.

[0296] The above is the description of the materials that can be used for the semiconductor device of this embodiment mode.

[0297] The semiconductor device of one embodiment of the present invention may include an insulating layer over the transistor 200. Specifically, an insulating layer may be provided over the conductive layer 245 and the insulating layer 285.

[0298] The insulating layer is preferably a barrier insulating layer against hydrogen, which can suppress diffusion of hydrogen from above the transistor 200 to the semiconductor layer 230.

[0299] 3A shows a configuration in which the inner side surface (groove 290 side) of the conductive layer 240 and the side surface of the insulating layer 280 on the groove 290 side are flush (also referred to as aligned, approximately aligned, coincident, or substantially coincident) in a plan view, but the present invention is not limited to this. For example, in a plan view, the inner side surface (groove 290 side) of the conductive layer 240 and the side surface of the insulating layer 280 on the groove 290 side may be discontinuous. Furthermore, the inclination of the inner side surface (groove 290 side) of the conductive layer 240 and the inclination of the side surface of the insulating layer 280 on the groove 290 side may differ from each other. In this case, part of the side wall of the groove 290 has a tapered shape.

[0300] 18A shows an example in which the inner side surface (groove 290 side) of conductive layer 240 is tapered. Fig. 18B shows an example in which the inner side surface (groove 290 side) of conductive layer 240 and the side surface of insulating layer 280 on the groove 290 side are both tapered.

[0301] By tapering the sidewalls of the groove 290, the coverage of the semiconductor layer 230, the insulating layer 250, etc. can be improved, and defects such as voids can be reduced. When the sidewalls of the groove 290 are tapered, for example, the taper angle (angle θ240) of the side surface of the conductive layer 240 on the inner side (groove 290 side) and the taper angle (angle θ280) of the side surface of the insulating layer 280 on the groove 290 side are preferably 45 degrees or more and less than 90 degrees. Specifically, as described above, a taper angle of 80 degrees or more and less than 90 degrees is preferable, as this allows for miniaturization or high integration of semiconductor devices. Furthermore, an angle of 45 degrees or more or 50 degrees or more and less than 80 degrees, 75 degrees or less, 70 degrees or less, 65 degrees or less, or 60 degrees or less is preferable, as this improves the coverage of the film formed in the groove 290.

[0302] Also, for example, it is preferable that the angle θ240 is smaller than the angle θ280. With this configuration, the coverage of the semiconductor layer 230 and the like on the side surface on the inner side (groove 290 side) of the conductive layer 240 is improved, and defects such as voids can be reduced. Furthermore, when the insulating layer 280 has a laminated structure, the inclination of the side surface of each layer in the groove 290 may be different. Similarly, when the conductive layer 240 has a laminated structure, the inclination of the side surface on the inner side (groove 290 side) of each layer may be different.

[0303] As described above, the semiconductor layer 230 can have a stacked structure of two or more layers.

[0304] 19A shows an example in which the semiconductor layer 230 of the semiconductor device shown in Fig. 3A has a two-layer structure. The semiconductor layer 230 shown in Fig. 19A can have a two-layer structure including a semiconductor layer 230_1 and a semiconductor layer 230_2 over the semiconductor layer 230_1.

[0305] 19B shows an example in which the semiconductor layer 230 of the semiconductor device shown in Fig. 3A has a three-layer structure. The semiconductor layer 230 shown in Fig. 19B can have a three-layer structure including a semiconductor layer 230_1, a semiconductor layer 230_2 over the semiconductor layer 230_1, and a semiconductor layer 230_3 over the semiconductor layer 230_2.

[0306] Note that the boundary (also referred to as an interface) between the semiconductor layer 230_1 and the semiconductor layer 230_2 and the boundary (also referred to as an interface) between the semiconductor layer 230_2 and the semiconductor layer 230_3 may not be clearly visible. Therefore, in Figures 19A and 19B, these boundaries are indicated by dashed lines.

[0307] For an oxide semiconductor layer that can be used for the semiconductor layers 230_1 to 230_3, the description in Embodiment 2 can be referred to.

[0308] <Configuration Example 2 of Semiconductor Device> Below, a configuration example of a semiconductor device that is partially different in configuration from the semiconductor device exemplified in <Configuration Example 1 of Semiconductor Device> will be described. Note that descriptions of overlapping parts will be omitted, and only the differences will be described in detail. Furthermore, even if the position or shape of components differs, if their functions are the same, they may be assigned the same reference numerals and their descriptions may be omitted.

[0309] 20A1, 20A2, 20B, 20C, 20D, and 20E correspond to FIGS. 1A1, 1A2, 1B, 1C, 1D, and 1E, respectively, and show examples in which the conductive layer 260 has an area that does not overlap with the groove portion 290.

[0310] 20A1 to 20D can be formed by, for example, photolithography. That is, the conductive layer 260 can be formed by forming a mask on the conductive film 260f shown in FIGS. 11A to 11E and removing part of the conductive film 260f by etching or the like. This makes it easier to form the conductive layer 260 in a desired shape than when, for example, as shown in FIGS. 12A to 12E, the conductive layer 260 is formed by processing the entire surface of the conductive film 260f by anisotropic etching without forming a mask. On the other hand, when the conductive layer 260 is formed by processing the entire surface of the conductive film 260f by anisotropic etching, the number of manufacturing steps for a semiconductor device can be reduced compared to when the conductive layer 260 is formed by using photolithography.

[0311] FIG. 21A1 is a plan view of a semiconductor device including a transistor 200. FIG. 21A2 is a plan view in which the conductive layer 245 is omitted from FIG. 21A1. FIG. 21B is a cross-sectional view taken along dashed-dotted lines A1-A2 in FIGS. 21A1 and 21A2. FIG. 21C is a cross-sectional view taken along dashed-dotted lines A3-A4 in FIGS. 21A1 and 21A2. FIG. 21D is a cross-sectional view taken along dashed-dotted lines C1-C2 in FIGS. 21B and 21C. FIG. 21D is also referred to as a plan view, and more specifically, can be considered a plan view showing an example of a cross-sectional configuration taken along dashed-dotted lines C1-C2. Note that for an example of a cross-sectional configuration taken along dashed-dotted lines B1-B2 in FIGS. 21A1 and 21A2, refer to FIG. 1D. Also, for an example of a cross-sectional configuration taken along dashed-dotted lines B3-B4 in FIGS. 21A1 and 21A2, refer to FIG. 1E.

[0312] The semiconductor device shown in FIGS. 21A1 to 21C differs from the semiconductor device shown in FIGS. 1A1 to 1E in that it has an insulating layer 225 in the groove 290.

[0313] In the transistor 200 shown in Figures 21A1 to 21C, the stacked structure from the conductive layer 220 to the conductive layer 240 and the stacked structure from the semiconductor layer 230 to the conductive layer 260 are similar to those of the transistor 200 described above, and therefore detailed description thereof will be omitted.

[0314] The insulating layer 225 is provided along at least a portion of the sidewall of the groove 290. In Figures 21B to 21D, the insulating layer 225 is provided so as to cover the side surface of the groove 290. Specifically, the insulating layer 225 has a region in contact with the side surface of the insulating layer 280 within the groove 290. The insulating layer 225 also has a region in contact with the side surface on the inner side (groove 290 side) of the conductive layer 240a, a region in contact with the side surface on the inner side (groove 290 side) of the conductive layer 240b, and a region in contact with the conductive layer 220. The insulating layer 225 can also be referred to as a sidewall, a sidewall insulating layer, a sidewall protective layer, or the like.

[0315] The insulating layer 225 can be made of an insulating material that can be used for the insulating layer 250 .

[0316] As described above, it is preferable that oxygen vacancies and impurities be reduced as much as possible in the channel formation region of the oxide semiconductor layer. In particular, it is preferable that hydrogen be reduced as much as possible in the channel formation region of the oxide semiconductor layer.

[0317] Therefore, it is preferable to use a barrier insulating layer against hydrogen as the insulating layer 225 provided outside the semiconductor layer 230. This can suppress diffusion of hydrogen into the semiconductor layer 230 and improve the reliability of the transistor 200. For example, it is preferable to use a silicon nitride film, a silicon nitride oxide film, or an aluminum oxide film as the insulating layer 225, and it is more preferable to use a silicon nitride film.

[0318] Note that a silicon nitride film also has a barrier property against oxygen. Therefore, by using a silicon nitride film for the insulating layer 225, oxygen can be prevented from being extracted from the semiconductor layer 230, which can prevent oxygen vacancies from being formed in the semiconductor layer 230. Furthermore, by using a silicon nitride film for the insulating layer 225, excessive oxygen can be prevented from being supplied to the semiconductor layer 230. Therefore, the channel formation region of the semiconductor layer 230 can be prevented from becoming oxygen-excessive, thereby improving the reliability of the transistor 200. Furthermore, the insulating layer 225 may be in contact with the side surface of the conductive layer 240a in the groove 290. In this case, by using a silicon nitride film for the insulating layer 225, it is possible to prevent the side surface of the conductive layer 240a in the groove 290 from being oxidized and an oxide film from being formed on the side surface. This can prevent a decrease in the on-state current or the field-effect mobility of the transistor 200.

[0319] The silicon nitride film of the insulating layer 225 is preferably formed using the PEALD method, which can improve the coverage of the insulating layer 225 on the sidewalls of the trench 290 and form an insulating layer 225 with a uniform thickness.

[0320] 21B and 21C show an example in which the insulating layer 225 has a single-layer structure. Note that the insulating layer 225 can have a stacked structure of two or more layers.

[0321] As shown in FIG. 22 , the conductive layer 220_2 preferably has a first recess and a second recess located outside the first recess. The first recess is deeper than the second recess. In other words, the bottom surface of the first recess is located lower (closer to the insulating layer 210) than the bottom surface of the second recess. When forming the groove 290, the second recess is provided in the conductive layer 220_2, and then, when processing the insulating layer 225, the first recess is provided in the conductive layer 220_2. Therefore, in FIG. 22 , the side surface of the second recess is aligned with the side surface of the insulating layer 280 in the groove 290, and the side surface of the first recess is aligned with the surface of the insulating layer 225 facing the semiconductor layer 230. Hereinafter, the first recess and the second recess may be collectively referred to as recesses.

[0322] 22 , the insulating layer 225 contacts the bottom and side surfaces of the recess (specifically, the second recess) of the conductive layer 220, the side surfaces of the conductive layer 240a, and the side surfaces of the conductive layer 240b, and also contacts the side surface of the insulating layer 280 within the groove 290. The semiconductor layer 230 contacts the bottom and side surfaces of the recess (specifically, the first recess) of the conductive layer 220 and the side surface of the insulating layer 225 within the groove 290. The insulating layer 250 is located inside the semiconductor layer 230 within the groove 290, and the conductive layer 260 is located inside the insulating layer 250 within the groove 290.

[0323] The conductive layer 220_2 has the first recess and the second recess, so that the side surface of the conductive layer 220_2 is in contact with the semiconductor layer 230. This increases the contact area between the conductive layer 220_2 and the semiconductor layer 230, thereby reducing the contact resistance between the conductive layer 220_2 and the semiconductor layer 230. Therefore, the on-state current of the transistor 200 can be increased.

[0324] Another structure of a semiconductor device according to one embodiment of the present invention will be described with reference to FIGS. 23A to 23C . FIG. 23A is a plan view of a semiconductor device including a transistor. Note that FIG. 23A illustrates a plan view of a region including two transistors 200 adjacent in the X direction. FIG. 23B is a cross-sectional view taken along dashed-dotted line A1-A2 in FIG. 23A . FIG. 23C is a cross-sectional view taken along dashed-dotted line A3-A4 in FIG. 23A . Note that FIG. 1D can be referred to for an example of a cross-sectional structure taken along dashed-dotted line B1-B2 in FIG. 23A . Furthermore, FIG. 1E can be referred to for an example of a cross-sectional structure taken along dashed-dotted line B3-B4 in FIG. 23A .

[0325] 23A to 23C includes an insulating layer 210 on a substrate (not shown), a transistor 200[1] and a transistor 200[2] on the insulating layer 210, an insulating layer 280 on the insulating layer 210, an insulating layer 285 on the insulating layer 280, and a conductive layer 245 on the insulating layer 285. The transistor 200[1] and the transistor 200[2] are adjacent to each other in the X direction.

[0326] The transistor 200[1] includes a conductive layer 220[1] on the insulating layer 210, a conductive layer 240[1] and a conductive layer 240[2] on the insulating layer 280, a semiconductor layer 230 on the conductive layer 220[1], the conductive layer 240[1], and the conductive layer 240[2], an insulating layer 250 on the semiconductor layer 230, and a conductive layer 260[1] on the insulating layer 250. The transistor 200[2] includes a conductive layer 220[2] on the insulating layer 210, a conductive layer 240[2] and a conductive layer 240[3] on the insulating layer 280, a semiconductor layer 230 on the conductive layer 220[2], the conductive layer 240[2], and the conductive layer 240[3], an insulating layer 250 on the semiconductor layer 230, and a conductive layer 260[2] on the insulating layer 250. Here, the insulating layer 280 and the conductive layer 220[1] have a groove 290[1], and the insulating layer 280 and the conductive layer 220[2] have a groove 290[2]. The semiconductor layer 230 and the insulating layer 250 have a region located in the groove 290[1] and a region located in the groove 290[2]. The conductive layer 260[1] has a region located in the groove 290[1]. The conductive layer 260[2] has a region located in the groove 290[2].

[0327] The insulating layer 285, the insulating layer 250, and the semiconductor layer 230 have an opening 270[1] reaching the conductive layer 240[1], an opening 270[2] reaching the conductive layer 240[2], and an opening 270[3] reaching the conductive layer 240[3]. A conductive layer 244[1] is provided in the opening 270[1], a conductive layer 244[2] is provided in the opening 270[2], and a conductive layer 244[3] is provided in the opening 270[3].

[0328] The conductive layer 245 is provided over the insulating layer 285, the conductive layer 244[1], the conductive layer 244[2], and the conductive layer 244[3]. The conductive layer 245 can have a region in contact with the top surface of the conductive layer 244[1], a region in contact with the top surface of the conductive layer 244[2], and a region in contact with the top surface of the conductive layer 244[3]. As described above, the other of the source electrode and the drain electrode of a plurality of transistors adjacent in the X direction is connected to each other.

[0329] 23A to 23C differ from the semiconductor device shown in FIGS. 1A1 to 1C in that the transistors 200 adjacent in the X direction share the conductive layer 240. Specifically, the transistors 200[1] and 200[2] share the conductive layer 240[2]. By having the transistors 200 adjacent in the X direction share the conductive layer 240, the area occupied by the semiconductor device can be reduced.

[0330] For materials, structures, and the like applicable to the conductive layers 220[1] and 220[2], the description of the conductive layer 220 can be referred to. For materials, structures, and the like applicable to the conductive layers 240[1] to 240[3], the description of the conductive layer 240 can be referred to. For materials, structures, and the like applicable to the conductive layers 260[1] and 260[2], the description of the conductive layer 260 can be referred to. For materials, structures, and the like applicable to the conductive layers 244[1] to 244[3], the description of the conductive layer 244 can be referred to.

[0331] Fig. 24A is a plan view showing an example of a semiconductor device according to one embodiment of the present invention. Fig. 24B is a cross-sectional view taken along dashed dotted line A1-A2 in Fig. 24A . Fig. 24C is a cross-sectional view taken along dashed dotted line A3-A4 in Fig. 24A . Fig. 24D is a cross-sectional view taken along dashed dotted line B1-B2 in Fig. 24A . Fig. 24E is a cross-sectional view taken along dashed dotted line B3-B4 in Fig. 24A .

[0332] 24A to 24E includes an insulating layer 210 over a substrate (not shown), a transistor 200A over the insulating layer 210, an insulating layer 280 over the insulating layer 210, an insulating layer 284 over the insulating layer 280, an insulating layer 285 over the insulating layer 284, and a conductive layer 265 over the transistor 200A, the insulating layer 284, and the insulating layer 285. Note that a description of the same configuration as that of the transistor 200 in the configuration of the transistor 200A may be omitted as appropriate.

[0333] The conductive layer 265 has a region in contact with the top surface of the conductive layer 260. Note that the conductive layer 265 may be considered as a component of the transistor 200A. In the example shown in FIGS. 24A to 24E , the conductive layer 265 is provided to extend in the X direction. The conductive layer 265 functions as a gate wiring. The conductive layer 265 can be formed using the same material as that used for the conductive layer 245.

[0334] 24B, the side surfaces of the conductive layer 260, the insulating layer 250, and the semiconductor layer 230 are aligned or substantially aligned outside the groove 290. Also, as shown in FIGS. 24B and 24C, the side surfaces of the conductive layer 260, the insulating layer 250, and the semiconductor layer 230 that contact the insulating layer 284 are aligned or substantially aligned.

[0335] 24B to 24E , the insulating layer 284 is provided on the insulating layer 280, the conductive layer 240a, and the conductive layer 240b. Outside the groove 290, the insulating layer 284 has regions in contact with the top and side surfaces of the conductive layer 240a and the conductive layer 240b, a region in contact with the side surface of the semiconductor layer 230, a region in contact with the side surface of the insulating layer 250, and a region in contact with the side surface of the conductive layer 260. As shown in FIGS. 24B and 24D , in the region overlapping with the groove 290, the insulating layer 284 has a region in contact with the side surface of the semiconductor layer 230, a region in contact with the side surface of the insulating layer 250, a region in contact with the side surface of the conductive layer 260, and a region in contact with the side surface of the insulating layer 280. The insulating layer 284 has a region in contact with the inner side surface (groove 290 side) of the conductive layer 240a and a region in contact with the inner side surface (groove 290 side) of the conductive layer 240b.

[0336] The insulating layer 284 is preferably an insulating layer having a function of capturing or fixing hydrogen. When the insulating layer 284 has a function of capturing or fixing hydrogen, hydrogen in the semiconductor layer 230 can be diffused into the insulating layer 284 and the hydrogen can be captured or fixed. Furthermore, diffusion of hydrogen from above the insulating layer 284 to the semiconductor layer 230 can be suppressed. Therefore, the hydrogen concentration in the semiconductor layer 230 can be reduced. As the insulating layer 284, an aluminum oxide film, a hafnium oxide film, a hafnium silicate film, or the like can be used.

[0337] Furthermore, a barrier insulating layer against hydrogen can be used as the insulating layer 284. This can suppress diffusion of hydrogen from above the insulating layer 284 into the semiconductor layer 230. A silicon nitride film and a silicon nitride oxide film each have the characteristics of releasing little impurities (for example, water and hydrogen) from themselves and being less permeable to oxygen and hydrogen, and therefore can be suitably used for the insulating layer 284.

[0338] When a silicon nitride film is used as the insulating layer 284, the silicon nitride film is preferably formed by a sputtering method. The sputtering method does not require the use of hydrogen-containing molecules in the film formation gas, and therefore can reduce the hydrogen concentration in the insulating layer 284. Furthermore, by forming the insulating layer 284 by a sputtering method, a silicon nitride film with high density can be formed.

[0339] Alternatively, the insulating layer 284 may have a stacked structure of an insulating layer having a function of capturing or fixing hydrogen and a barrier insulating layer against hydrogen. For example, the insulating layer 284 may be a stacked film of an aluminum oxide film and a silicon nitride film over the aluminum oxide film.

[0340] An opening 271 that reaches the insulating layer 250 is provided in the insulating layer 284 at a position that overlaps the groove 290. The conductive layer 260 is disposed so that at least a portion of the conductive layer 260 is located within the opening 271. The conductive layer 260 contacts the insulating layer 250 within the opening 271.

[0341] The insulating layer 284 also has an opening in the groove 290 in a region that does not overlap with the insulating layer 250. An insulating layer 285 is provided to fill the opening.

[0342] The conductive layer 260 is provided so as to fill the groove 290 and the opening 271. The conductive layer 260 has a portion that faces the semiconductor layer 230 in the groove 290 with the insulating layer 250 interposed therebetween, and a portion that is located within the opening 271.

[0343] The portion of the conductive layer 265 that does not overlap with the groove portion 290 is mainly located on the insulating layer 285. Therefore, the conductive layer 265 mainly overlaps with the conductive layer 240 via the insulating layer 284 and the insulating layer 285. This allows the distance between the conductive layer 265 and the conductive layer 240 to be increased, and the parasitic capacitance generated between the conductive layer 265 and the conductive layer 240 to be reduced. Note that the conductive layer 240 and the conductive layer 265 may have an overlapping portion without the insulating layer 285 being therebetween.

[0344] That is, the transistor 200A has a structure in which parasitic capacitance generated between the other of the source electrode and the drain electrode and the gate wiring is reduced, thereby improving the frequency characteristics of a circuit including the transistor.

[0345] 24B shows an example in which the width of opening 271 is greater than the width of groove 290. Note that, in a plan view, it is preferable that the overlapping area between opening 271 and groove 290 is small. The smaller the overlapping area between opening 271 and groove 290, the greater the distance between conductive layer 240a and conductive layer 260, and the smaller the parasitic capacitance occurring between conductive layer 240a and conductive layer 260. Similarly, the greater the distance between conductive layer 240b and conductive layer 260, and the smaller the parasitic capacitance occurring between conductive layer 240b and conductive layer 260.

[0346] Although the present embodiment has been described with reference to an example in which the opening 271 is rectangular in plan view, the present invention is not limited thereto. In plan view, the opening 271 may be, for example, a substantially circular shape such as an oval or an ellipse, a polygonal shape such as a triangle, a quadrangle (including a rectangle, a diamond, and a square), a pentagon, or a star-shaped polygon, or any of these polygons with rounded corners. The polygon may be either a concave polygon (a polygon with at least one interior angle exceeding 180 degrees) or a convex polygon (a polygon with all interior angles equal to or less than 180 degrees).

[0347] The width of the opening 271 may vary in the depth direction. In particular, the width of the opening 271 used here is the maximum width of the opening 271 provided in the insulating layer 284 in a cross-sectional view.

[0348] It is preferable that the height of the top surface of the conductive layer 260 is the same as or approximately the same as the height of the top surface of the insulating layer 285 or the insulating layer 284. The conductive layer 265 is provided over the insulating layer 285, the insulating layer 284, and the conductive layer 260, and is in contact with the top surface of the conductive layer 260. It can also be said that the conductive layer 260 and the conductive layer 265 are connected to each other.

[0349] Fig. 25A is a plan view of a semiconductor device having two transistors. Fig. 25B is a cross-sectional view taken along dashed dotted line A1-A2 in Fig. 25A. Fig. 25C is a cross-sectional view taken along dashed dotted line A3-A4 in Fig. 25A. Fig. 25D is a cross-sectional view taken along dashed dotted line C1-C2 in Figs. 25B and 25C. Fig. 25D is also called a plan view, and specifically can be said to be a plan view showing an example of a cross-sectional configuration taken along dashed dotted line C1-C2.

[0350] 25A to 25D includes an insulating layer 210 over a substrate (not shown), transistors 200Ba and 200Bb over the insulating layer 210, an insulating layer 280 over the insulating layer 210, an insulating layer 284 over the insulating layer 280, an insulating layer 285 over the insulating layer 284, and conductive layers 265 over the transistors 200Ba, 200Bb, the insulating layer 284, and the insulating layer 285. Note that hereinafter, the transistors 200Ba and 200Bb may be collectively referred to as transistor 200B.

[0351] 25A to 25C differs from the semiconductor device illustrated in Figures 24A to 24E in that two transistors, a transistor 200Ba and a transistor 200Bb, are included in the region where the conductive layer 265 overlaps with the groove 290. The transistor 200Ba includes a conductive layer 220a on the insulating layer 210, a conductive layer 240a on the insulating layer 280, a semiconductor layer 230a on the conductive layer 220a and the conductive layer 240a, an insulating layer 250a on the semiconductor layer 230a, and a conductive layer 260a on the insulating layer 250a. Similarly, transistor 200Bb has a conductive layer 220b on insulating layer 210, a conductive layer 240b on insulating layer 280, a semiconductor layer 230b on conductive layer 220b and conductive layer 240b, an insulating layer 250b on semiconductor layer 230b, and a conductive layer 260b on insulating layer 250b.

[0352] The transistors 200Ba and 200Bb have a linearly symmetrical configuration with respect to the dashed-dotted line D1-D2 shown in Figures 25A and 25D. Therefore, the configuration of the transistor 200Bb can be understood by referring to the description of the configuration of the transistor 200Ba, by replacing the transistor 200Ba, conductive layer 220a, conductive layer 240a, semiconductor layer 230a, insulating layer 250a, and conductive layer 260a with the transistor 200Bb, conductive layer 220b, conductive layer 240b, semiconductor layer 230b, insulating layer 250b, and conductive layer 260b, respectively, and making appropriate necessary modifications. Hereinafter, the transistor 200Ba will be mainly described.

[0353] In the transistor 200Ba, the conductive layer 260a functions as a gate electrode, and the insulating layer 250a functions as a gate insulating layer. The conductive layer 220a functions as one of a source electrode and a drain electrode. The conductive layer 240a functions as the other of the source electrode and the drain electrode. The conductive layer 265 has a region that functions as a gate wiring.

[0354] 25B and 25D , the insulating layer 284 is provided in the groove 290 so as to contact the side surface of the semiconductor layer 230a. By using an insulating layer having the function of capturing or fixing hydrogen as the insulating layer 284, it is possible to suppress the diffusion of hydrogen from above the insulating layer 284 to the semiconductor layer 230a, and further to capture or fix the hydrogen contained in the semiconductor layer 230a. Therefore, the hydrogen concentration in the semiconductor layer 230a can be reduced.

[0355] By providing two transistors in a region where the groove 290 and the conductive layer 265 overlap, the area occupied by the semiconductor device can be reduced, and miniaturization or high integration of the semiconductor device can be achieved.

[0356] This embodiment mode can be combined with other embodiment modes as appropriate. In addition, in this specification, when a plurality of configuration examples are shown in one embodiment mode, the configuration examples can be combined as appropriate.

[0357] Embodiment 2 In this embodiment, an oxide semiconductor layer that can be used as a semiconductor layer of a transistor will be described. As the oxide semiconductor layer of one embodiment of the present invention, a layer containing a metal oxide can be used as a single layer or a stacked layer. Note that in an oxide semiconductor layer with a stacked structure, it may be difficult to identify boundaries between stacked films, as described later.

[0358] [Metal Oxide] The metal oxide according to one embodiment of the present invention preferably contains at least indium (In) or zinc (Zn), and particularly preferably contains indium as the main component. The metal oxide preferably contains two or three elements selected from indium, element M, and zinc, and particularly preferably contains indium and zinc as the main components. Here, the metal oxide may contain indium and zinc as the main components and may further contain element M. The element M is a metal element or a metalloid element having a high bond energy with oxygen, for example, a metal element or a metalloid element having a bond energy with oxygen higher than that of indium. Specific examples of element M include aluminum, gallium, tin, yttrium, titanium, vanadium, chromium, manganese, iron, cobalt, nickel, zirconium, molybdenum, hafnium, tantalum, tungsten, lanthanum, cerium, neodymium, magnesium, calcium, strontium, barium, boron, silicon, germanium, and antimony. The element M contained in the metal oxide is preferably one or more of the above elements, more preferably one or more selected from aluminum, gallium, tin, and yttrium, and even more preferably one or more selected from gallium and tin. When the element M contained in the metal oxide is gallium, the metal oxide according to one embodiment of the present invention preferably contains one or more selected from indium, gallium, and zinc. Note that in this specification and the like, metal elements and metalloid elements may be collectively referred to as "metal elements," and the "metal element" described in this specification and the like may also include metalloid elements.

[0359] Examples of metal oxides according to one embodiment of the present invention include indium zinc oxide (In-Zn oxide, also referred to as IZO (registered trademark)), indium tin oxide (In-Sn oxide, also referred to as ITO), indium titanium oxide (In-Ti oxide), indium gallium oxide (In-Ga oxide), indium gallium aluminum oxide (In-Ga-Al oxide), indium gallium tin oxide (In-Ga-Sn oxide, also referred to as IGTO), and indium aluminum zinc oxide (In-Al-Zn oxide, IAZ). Examples of usable metal oxides include indium tin zinc oxide (In—Sn—Zn oxide), indium titanium zinc oxide (In—Ti—Zn oxide), indium gallium zinc oxide (In—Ga—Zn oxide, IGZO), indium tin oxide containing silicon oxide (ITSO), indium gallium tin zinc oxide (In—Ga—Sn—Zn oxide, IGZTO), and indium gallium aluminum zinc oxide (In—Ga—Al—Zn oxide, IGAZO or IAGZO). Alternatively, examples of usable metal oxides include gallium zinc oxide (Ga—Zn oxide, GZO), aluminum zinc oxide (Al—Zn oxide, AZO), gallium tin oxide (Ga—Sn oxide), and aluminum tin oxide (Al—Sn oxide). Indium oxide can be used as the metal oxide according to one embodiment of the present invention. Gallium oxide, zinc oxide, and the like can be used as the metal oxide according to one embodiment of the present invention.

[0360] By increasing the content of indium in the metal oxide, the transistor can have a large on-state current and high frequency characteristics.

[0361] Note that the metal oxide may contain one or more metal elements having a higher period number in the periodic table instead of indium. Alternatively, the metal oxide may contain one or more metal elements having a higher period number in the periodic table in addition to indium. The greater the overlap of the orbitals of metal elements, the greater the carrier conduction in the metal oxide tends to be. Therefore, by including a metal element having a higher period number in the periodic table, the field-effect mobility of a transistor may be improved. Examples of metal elements having a higher period number in the periodic table include metal elements belonging to the fifth period and the sixth period. Specific examples of such metal elements include yttrium, zirconium, silver, cadmium, tin, antimony, barium, lead, bismuth, lanthanum, cerium, praseodymium, neodymium, promethium, samarium, and europium. Lanthanum, cerium, praseodymium, neodymium, promethium, samarium, and europium are called light rare earth elements.

[0362] The metal oxide may contain one or more nonmetallic elements, which may increase the field-effect mobility of the transistor. Examples of nonmetallic elements include carbon, nitrogen, phosphorus, sulfur, selenium, fluorine, chlorine, bromine, and hydrogen.

[0363] Furthermore, by increasing the zinc content in the metal oxide, the metal oxide can be made highly crystalline, which can suppress the diffusion of impurities in the metal oxide, thereby suppressing fluctuations in the electrical characteristics of the transistor and improving its reliability.

[0364] Furthermore, by increasing the content of element M in the metal oxide, the formation of oxygen vacancies in the metal oxide can be suppressed. Therefore, carrier generation due to oxygen vacancies can be suppressed, and a transistor with a small off-state current can be obtained. Furthermore, fluctuations in the electrical characteristics of the transistor can be suppressed, and reliability can be improved.

[0365] A structural example of an oxide semiconductor layer capable of increasing the field-effect mobility of a transistor will be described. For example, it is preferable to use indium oxide or a stacked structure of indium oxide and IGZO. Specifically, it is preferable that the oxide semiconductor layer has indium oxide and IGZO on the indium oxide. In addition, it is preferable to use IGZO containing nitrogen as the oxide semiconductor layer. For example, it is preferable to use IGZO containing nitrogen during or after the film formation. ２ By performing O plasma treatment, IGZO containing nitrogen can be formed. For the oxide semiconductor layer, at least one of indium oxide, In—Ga oxide, In—Zn oxide, and IGZTO is preferably used.

[0366] In the present embodiment, an In-M-Zn oxide may be used as an example of the metal oxide.

[0367] The oxide semiconductor layer of one embodiment of the present invention preferably includes a crystalline metal oxide. Examples of the structure of a crystalline metal oxide include a c-axis aligned crystal (CAAC) structure, a polycrystalline (poly-crystal) structure, and a nanocrystalline (nc) structure. By using a crystalline metal oxide for the oxide semiconductor layer, the density of defect states in the oxide semiconductor layer can be reduced. Therefore, the reliability of a transistor including the oxide semiconductor layer of one embodiment of the present invention can be improved, and the reliability of a semiconductor device including the transistor can be improved.

[0368] Note that the crystallinity of the metal oxide included in the oxide semiconductor layer is not particularly limited. For example, the oxide semiconductor layer may include one or more of an amorphous semiconductor (a semiconductor having an amorphous structure), a single-crystal semiconductor (a semiconductor having a single-crystal structure), or a semiconductor having crystallinity other than single crystal (a microcrystalline semiconductor, a polycrystalline semiconductor, or a semiconductor having a crystalline region in part). When the oxide semiconductor layer has crystallinity, deterioration of transistor characteristics can be suppressed in some cases.

[0369] The crystallinity of the oxide semiconductor layer can be analyzed by, for example, X-ray diffraction (XRD), transmission electron microscopy (TEM), or electron diffraction (ED). Alternatively, the analysis may be performed by combining a plurality of these techniques.

[0370] The oxide semiconductor layer of one embodiment of the present invention preferably includes a metal oxide having a CAAC structure. The CAAC structure is a crystal structure in which a plurality of microcrystals (typically, a plurality of microcrystals having a hexagonal crystal structure) have c-axis orientation and are connected without being oriented in the a-b plane. Furthermore, when a cross section of an oxide semiconductor layer having a CAAC structure is observed using a high-resolution TEM image (also referred to as a multi-beam interference image), it can be confirmed that metal atoms are arranged in a layered manner in the crystal parts. Therefore, the oxide semiconductor layer having a CAAC structure can also be said to have a structure having layered crystal parts.

[0371] For example, the CAAC structure is formed so that the c-axis is perpendicular or substantially perpendicular to the surface or surface of the oxide semiconductor layer on which the oxide semiconductor layer is to be formed. In the CAAC structure, metal atoms are arranged in layers parallel or substantially parallel to the surface on which the oxide semiconductor layer is to be formed. In the region having the CAAC structure, the c-axis is preferably within 90°±20° (70° to 110°), more preferably within 90°±15° (75° to 105°), more preferably within 90°±10° (80° to 110°), and even more preferably within 90°±5° (85° to 95°) relative to the surface on which the oxide semiconductor layer is to be formed.

[0372] When the oxide semiconductor layer has a CAAC structure, a group of bright spots (specifically, bright spots arranged in layers) reflecting the layered arrangement of metal atoms is observed in a cross section of the oxide semiconductor layer observed using a TEM image. Specifically, the bright spots are observed to be arranged in layers in a direction parallel or approximately parallel to the surface on which the oxide semiconductor layer is formed.

[0373] When electron diffraction is performed on an oxide semiconductor layer having a CAAC structure, spots (bright points) indicating c-axis orientation are observed in the electron diffraction pattern.

[0374] Furthermore, an FFT pattern obtained by subjecting a TEM image to a fast Fourier transform (FFT) process reflects reciprocal lattice space information similar to an electron diffraction pattern.

[0375] A cross-sectional TEM image of an oxide semiconductor layer having a CAAC structure is obtained, and an FFT process is performed on each region in the cross-sectional TEM image to create an FFT pattern. The crystal axis direction of each region can be calculated from the created FFT pattern. Specifically, the direction of a line segment connecting two spots that have high brightness and are approximately equidistant from the center among the spots observed in the created FFT pattern is defined as the crystal axis direction. A region in which the crystal axis direction of each region calculated from the FFT pattern is preferably 70 degrees or more and 110 degrees or less (within 90 degrees ± 20 degrees) relative to the surface to be formed, more preferably 75 degrees or more and 105 degrees or less (within 90 degrees ± 15 degrees), more preferably 80 degrees or more and 100 degrees or less (within 90 degrees ± 10 degrees), or even more preferably 85 degrees or more and 95 degrees or less (within 90 degrees ± 5 degrees) can be considered to have a CAAC structure.

[0376] When an oxide semiconductor layer having a CAAC structure is viewed in a direction perpendicular to a surface where the oxide semiconductor layer is formed, a triangular or hexagonal atomic arrangement is observed in the a-b plane using a TEM image, and the oxide semiconductor layer has crystallinity.

[0377] [Composition of Metal Oxide] The metal oxide according to one embodiment of the present invention preferably contains indium (In), and more preferably has a high In content. By using a metal oxide with a high In content for the oxide semiconductor layer, the on-state current of a transistor can be increased and frequency characteristics can be improved. For example, indium oxide is preferably used for the oxide semiconductor layer.

[0378] Furthermore, the metal oxide according to one embodiment of the present invention may contain zinc. When the metal oxide contains zinc, it becomes a metal oxide with high crystallinity, for example, a metal oxide having a CAAC structure. For example, an In—Zn oxide can be used for the oxide semiconductor layer. Specifically, a metal oxide having a composition of In:Zn=1:1 (atomic ratio) or a composition thereabout, an In:Zn=2:1 (atomic ratio) or a composition thereabout, or an In:Zn=4:1 (atomic ratio) or a composition thereabout can be used. Note that a composition thereabout includes a range of ±30% of the desired atomic ratio.

[0379] Furthermore, the metal oxide according to one embodiment of the present invention can contain an element M. When the metal oxide contains the element M, oxygen vacancies can be suppressed from being formed in the metal oxide. Thus, the reliability of a transistor including an oxide semiconductor layer can be improved.

[0380] For example, the oxide semiconductor layer can be made of an In—Zn oxide containing a trace amount of element M. Specifically, a metal oxide having an atomic ratio of In:Ga:Zn=4:0.1:1 or a composition thereof, an atomic ratio of In:Ga:Zn=2:0.1:1 or a composition thereof, or an atomic ratio of In:Ga:Zn=1:0.1:1 or a composition thereof can be used. Alternatively, a metal oxide having an atomic ratio of In:Sn:Zn=4:0.1:1 or a composition thereof, an atomic ratio of In:Sn:Zn=2:0.1:1 or a composition thereof, or an atomic ratio of In:Sn:Zn=1:0.1:1 or a composition thereof can be used.

[0381] The oxide semiconductor layer can be made of an In—Zn oxide containing an element M. Specifically, a metal oxide having an atomic ratio of In:M:Zn=1:1:1 or a composition thereof, an atomic ratio of In:M:Zn=1:1:1.2 or a composition thereof, an atomic ratio of In:M:Zn=1:1:0.5 or a composition thereof, an atomic ratio of In:M:Zn=1:1:2 or a composition thereof, an atomic ratio of In:M:Zn=4:2:3 or a composition thereof, an atomic ratio of In:M:Zn=1:3:2 or a composition thereof, or an atomic ratio of In:M:Zn=1:3:4 or a composition thereof can be used.

[0382] When a metal oxide is formed by sputtering, the composition of the formed metal oxide may differ from that of the sputtering target. In particular, the zinc content in the formed metal oxide may decrease to about 50% of that in the sputtering target.

[0383] Furthermore, when forming a metal oxide containing multiple metal elements, such as In—Ga—Zn oxide, by atomic layer deposition (ALD), the ratio of the number of cycles of precursors containing each metal element can be set to match the target composition. For example, when forming an In—Ga—Zn oxide with an atomic ratio of In:Ga:Zn = 1:3:2, one cycle of forming an In-containing precursor and treating it with an oxidizing agent can be performed, three cycles of forming a Ga-containing precursor and treating it with an oxidizing agent can be performed, and two cycles of forming a Zn-containing precursor and treating it with an oxidizing agent can be performed. However, the ratio of the number of cycles of precursors containing each metal element and the atomic ratio of each metal element in the formed metal oxide film may not match.

[0384] The composition of the metal oxide used in the oxide semiconductor layer can be analyzed by, for example, EDX, XPS, inductively coupled plasma-mass spectrometry (ICP-MS), or inductively coupled plasma-atomic emission spectrometry (ICP-AES). Alternatively, the analysis may be performed by combining a plurality of these techniques. Note that for elements with low contents, the actual content and the content obtained by analysis may differ due to the influence of analytical accuracy. For example, when the content of element M is low, the content of element M obtained by analysis may be lower than the actual content, may be difficult to quantify, or may be below the detection limit.

[0385] The oxide semiconductor layer of one embodiment of the present invention may have a stacked structure of two or more layers. When the oxide semiconductor layer has a two-layer structure of a first layer and a second layer over the first layer, the second layer preferably has a different composition from the first layer. When the oxide semiconductor layer has a three-layer structure of a first layer, a second layer over the first layer, and a third layer over the second layer, the second layer preferably has a different composition from the first layer and the third layer. Note that the first layer can have the same composition as the third layer. Alternatively, the first layer and the third layer can have different compositions.

[0386] The first to third layers may each be made of the metal oxides described above.

[0387] The second layer can be made of, for example, indium oxide, In—Zn oxide, or In—Zn oxide containing a trace amount of element M. Specifically, a metal oxide having an atomic ratio of In:Zn=1:1 or a composition thereabout, an atomic ratio of In:Zn=2:1 or a composition thereabout, or an atomic ratio of In:Zn=4:1 or a composition thereabout can be used. For example, a metal oxide having an atomic ratio of In:Ga:Zn=4:0.1:1 or a composition thereabout, an atomic ratio of In:Ga:Zn=2:0.1:1 or a composition thereabout, or an atomic ratio of In:Ga:Zn=1:0.1:1 or a composition thereabout can be used. Alternatively, for example, a metal oxide having an atomic ratio of In:Sn:Zn=4:0.1:1 or a composition thereof, an atomic ratio of In:Sn:Zn=2:0.1:1 or a composition thereof, or an atomic ratio of In:Sn:Zn=1:0.1:1 or a composition thereof can be used. Increasing the In content in the second layer can increase the on-current and improve the frequency characteristics.

[0388] The conduction band minimums of the first and third layers are preferably located closer to the vacuum level than the conduction band minimum of the second layer. In other words, the energy of the conduction band minimum of the first and third layers is preferably lower than the energy of the conduction band minimum of the second layer. In this case, the second layer is sandwiched between the first and third layers, whose conduction band minimums are located closer to the vacuum level, and can function mainly as a current path (channel).

[0389] By sandwiching the second layer between the first layer and the third layer, carriers trapped at the interface of the second layer and its vicinity can be reduced. Furthermore, the channel can be distanced from the surface of the gate insulating layer, thereby reducing the influence of surface scattering. This allows a buried-channel transistor in which the channel is distanced from the insulating layer interface to be realized, thereby increasing field-effect mobility. Furthermore, in a transistor having a back gate, the influence of interface states that may be formed on the back gate electrode side (also referred to as the back channel side) of the oxide semiconductor layer is reduced. This allows light degradation (e.g., negative bias light degradation) of the transistor to be suppressed, thereby improving the reliability of the transistor.

[0390] For example, a band diagram of the semiconductor layer 230_1 including the semiconductor layers 230_1 to 230_3 and their vicinity shown in FIG. 19B is as shown in FIG. 26. In FIG. 26, the vertical axis represents energy, and the horizontal axis represents the film thickness direction at the center of the channel formation region. FIG. 26 also shows the valence band maximum (VBM) and conduction band minimum (CBM) of the semiconductor layer 230_1, the semiconductor layer 230_2, the semiconductor layer 230_3, the insulating layer 280, and the insulating layer 250 when no voltage is applied between the gate and the source. Also, in FIG. 26, the vacuum level Vac is indicated by a dashed line.

[0391] Note that the energy of the upper end of the valence band and the energy of the lower end of the conduction band vary depending on the constituent elements and compositions of the semiconductor layer 230_1, the semiconductor layer 230_2, the semiconductor layer 230_3, the insulating layer 280, and the insulating layer 250. Therefore, the relationship in level between the upper ends of the valence bands and the relationship in level between the lower ends of the conduction bands will be mainly described using the band diagram of FIG. 26 .

[0392] Depending on the constituent elements and compositions of the semiconductor layers 230_1 to 230_3, the semiconductor layer 230_2 may be sandwiched between the semiconductor layers 230_1 and 230_3, whose conduction band minimums are closer to the vacuum level than the semiconductor layer 230_2, as shown in FIG. 26 . This structure can realize a buried channel. That is, this structure forms a path through which more current (electrons are illustrated as carriers in FIG. 26 ) flows in the semiconductor layer 230_2. Therefore, an increase in on-state current, improvement in reliability, etc. can be achieved.

[0393] When forming a buried channel using the first to third layers, for example, the first and third layers can be made of a metal oxide having a higher Ga content than the second layer. Specifically, the first and third layers can each be made of a metal oxide having an In:Ga:Zn=1:1:1 atomic ratio or a composition thereabout, a metal oxide having an In:Ga:Zn=1:3:2 atomic ratio or a composition thereabout, or a metal oxide having an In:Ga:Zn=1:3:4 atomic ratio or a composition thereabout. Alternatively, Ga-Zn oxide or gallium oxide can be used. Increasing the Ga content of the first and third layers can sometimes position the conduction band minimum of each of the first and third layers closer to the vacuum level than the conduction band minimum of the second layer.

[0394] Furthermore, increasing the Ga content in the first layer and the third layer can improve the barrier properties of the first layer and the third layer against hydrogen. Therefore, hydrogen diffusion from below the first layer or above the third layer to the second layer can be suppressed. Furthermore, increasing the Ga content in the first layer and the third layer can reduce impurities such as hydrogen or water contained in the oxide semiconductor layer due to heat or the like applied after the formation of the oxide semiconductor layer. Note that the same effect may be achieved by using a metal oxide having a lower In content than the second layer for the first layer and the third layer.

[0395] For example, the third layer preferably uses a metal oxide having an atomic ratio of In:Ga:Zn=1:1:1 or a similar composition, an atomic ratio of In:Ga:Zn=1:3:2 or a similar composition, or an atomic ratio of In:Ga:Zn=1:3:4 or a similar composition, wherein the third layer contains indium and gallium.

[0396] Furthermore, increasing the Ga content in the first layer and the third layer can improve the oxygen barrier properties of the first layer and the third layer. This can suppress oxygen release from the second layer where the channel is formed, and can suppress the formation of oxygen vacancies in the second layer or an increase in the amount of oxygen vacancies in the second layer. This can improve the electrical characteristics of the transistor.

[0397] Furthermore, by increasing the Ga content in the first layer, the resistivity of the first layer can be made higher than that of the second layer in some cases. When the first layer is provided on the back channel side, providing a layer with high resistivity as the first layer can suppress a negative shift in threshold voltage or a decrease in on-current. Therefore, the threshold voltage of the transistor is shifted positively, and the transistor can be made normally off. As described above, the electrical characteristics of the transistor can be improved, and the reliability of the transistor can be improved.

[0398] The band gap of a metal oxide can be evaluated by optical evaluation using a spectrophotometer, spectroscopic ellipsometry, photoluminescence, X-ray photoelectron spectroscopy, or X-ray absorption fine structure (XAFS). Furthermore, a combination of these techniques can be used for analysis. The electron affinity or the bottom of the conduction band can be determined from the ionization potential, which is the energy difference between the vacuum level and the top of the valence band, and the band gap. The ionization potential can be evaluated by, for example, ultraviolet photoelectron spectroscopy (UPS).

[0399] The first layer and the third layer may be made of a metal oxide having a higher In content than the second layer. Alternatively, one of the first layer and the third layer may be made of a metal oxide having a higher In content than the second layer, and the other may be made of a metal oxide having a higher Ga content than the second layer.

[0400] The first layer, the second layer, and the third layer may each have a plurality of layers having the above-described compositions stacked together. For example, the first layer may have a structure in which a metal oxide having a high In content is stacked on a metal oxide having a high Ga content. For example, the third layer may have a structure in which a metal oxide having a high Ga content is stacked on a metal oxide having a high In content.

[0401] [Method for Forming Oxide Semiconductor Layer] The oxide semiconductor layer of one embodiment of the present invention can be formed by a sputtering method, a chemical vapor deposition (CVD) method, a vacuum evaporation method, a molecular beam epitaxy (MBE) method, a pulsed laser deposition (PLD) method, an ALD method, or the like.

[0402] The oxide semiconductor layer of one embodiment of the present invention can be manufactured by forming a metal oxide by two different deposition methods. For example, the oxide semiconductor layer of one embodiment of the present invention can be manufactured by forming a metal oxide by a first deposition method and a second deposition method.

[0403] The oxide semiconductor layer of one embodiment of the present invention can have a two-layer structure including a first layer and a second layer over the first layer. In the case where the oxide semiconductor layer has a two-layer structure, the oxide semiconductor layer can be manufactured by forming the first layer over a surface to be formed by a first film formation method and then forming the second layer thereover by a second film formation method.

[0404] The first deposition method is preferably a deposition method that causes less damage to the surface on which the oxide semiconductor layer is formed than the second deposition method. This can suppress the formation of a mixed layer at the interface between the oxide semiconductor layer and a layer on which the oxide semiconductor layer is formed. Furthermore, impurities such as silicon can be prevented from being mixed into the second layer formed on the first layer, which may lead to higher crystallinity of the oxide semiconductor layer.

[0405] Examples of the first film formation method include ALD, CVD, and MBE. Examples of CVD methods include plasma enhanced CVD (PECVD), thermal CVD, photo-assisted CVD, and MOCVD. The MBE method is a film formation method that grows a thin film having a crystalline structure that reflects the crystalline system of the substrate, and can be considered one of the film formation methods that cause little damage to the surface on which the film is formed. A wet method can also be used as the first film formation method. The wet method is one of the film formation methods that cause little damage to the surface on which the film is formed. Examples of the wet method include spray coating.

[0406] The second film formation method is preferably a method capable of forming a crystalline metal oxide film. It is particularly preferable that the metal oxide film formed in this case has a CAAC structure. Examples of the second film formation method include a sputtering method and a PLD method. Since a metal oxide film formed by a sputtering method is likely to have crystallinity, the sputtering method is suitable as the second film formation method.

[0407] When a metal oxide is formed on a surface to be formed using the second film formation method, damage to the surface to be formed may cause alloying of components contained in the metal oxide with components contained in the layer on the surface to be formed. This alloying may result in the formation of a mixed layer at the interface between the metal oxide and the layer on the surface to be formed. This mixed layer may also be referred to as an alloyed region. The formation of the mixed layer may also be referred to as alloying.

[0408] For example, when a sputtering method is used as the second film formation method, a mixed layer may be formed by particles (also referred to as sputtering particles) emitted from a target or the like, or energy imparted to a substrate by the sputtering particles or the like. Specifically, when a metal oxide film is formed by the second film formation method using a silicon-containing insulating layer, such as a silicon oxide film, as a formation surface, silicon may be mixed into the metal oxide. There is a concern that the inclusion of impurities such as silicon into the metal oxide may inhibit the crystallization of the metal oxide. Furthermore, there is a concern that using an oxide semiconductor layer containing impurities in a transistor may adversely affect the initial characteristics or reliability of the transistor. Furthermore, even when heat treatment, which will be described later, is performed, it is difficult to enhance the crystallinity of the alloyed region.

[0409] Therefore, as described above, by forming a metal oxide by the first film formation method before forming a metal oxide by the second film formation method, impurities can be prevented from being mixed into the oxide semiconductor layer. Furthermore, alloying with a layer on which the metal oxide is to be formed can be suppressed. Therefore, the initial characteristics and reliability of the transistor can be improved. Furthermore, the crystallinity of the oxide semiconductor layer can be further increased.

[0410] A mixed layer may be formed at the interface between the first layer and the second layer. The mixed layer contains the component contained in the first layer and the component contained in the second layer. For example, when gallium oxide is used for the first layer and a metal oxide containing indium is used for the second layer, the mixed layer contains gallium and indium. Furthermore, for example, when the indium content in the second layer is higher than the indium content in the first layer, the indium content in the mixed layer is equal to or greater than the indium content in the first layer and equal to or less than the indium content in the second layer.

[0411] The ALD method is suitable as the first film formation method because it can suppress damage to the surface to be formed compared to the sputtering method. Furthermore, the ALD method is a film formation method with better coverage than the sputtering method, and by using the ALD method as the film formation method for the first layer, the coverage of the oxide semiconductor layer can be improved. Therefore, the oxide semiconductor layer can be well coated on steps, openings, grooves, etc. with high aspect ratios.

[0412] The first layer may be, for example, a metal oxide having a microcrystalline structure or an amorphous structure with lower crystallinity than a CAAC structure. The crystallinity of the first layer may be increased by forming a second layer with high crystallinity on the first layer with low crystallinity or by performing heat treatment after forming the second layer, with the second layer acting as a nucleus. This may increase the crystallinity of the entire oxide semiconductor layer, including the vicinity of the interface with the surface on which the oxide semiconductor layer is formed.

[0413] The layer serving as the surface to be formed is, for example, an insulating film such as a silicon oxide film, a silicon oxynitride film, a silicon nitride film, a silicon nitride oxide film, an aluminum oxide film, or a hafnium oxide film. Note that, depending on the transistor structure, the layer may be a conductive film such as a titanium nitride film, a tungsten film, or an ITSO film. The layer serving as the surface to be formed does not need to have crystallinity. Note that, when the layer has crystallinity, it may have a crystal structure with low lattice matching with the metal oxide contained in the oxide semiconductor layer.

[0414] The first layer is preferably formed by ALD. Here, a method for forming an In-M-Zn oxide as the first layer by ALD will be described.

[0415] First, a source gas containing an indium precursor is introduced into a reaction chamber, and the precursor is adsorbed onto the substrate surface. Next, an oxidizing agent is introduced into the reaction chamber as a reactant and reacted with the adsorbed precursor, thereby removing components other than indium while leaving indium adsorbed onto the substrate, thereby forming a layer in which indium and oxygen are combined.

[0416] Next, a source gas containing a precursor having element M is introduced into the reaction chamber and is adsorbed onto the layer in which indium and oxygen are bonded. Next, an oxidizing agent is introduced into the reaction chamber as a reactant and reacted with the adsorbed precursor, thereby desorbing components other than element M while leaving element M adsorbed on the substrate, thereby forming a layer in which element M and oxygen are bonded.

[0417] Next, a source gas containing a zinc-containing precursor is introduced into the reaction chamber and adsorbed onto the layer in which the element M and oxygen are bonded. Next, an oxidizing agent is introduced into the reaction chamber as a reactant and reacted with the adsorbed precursor, thereby desorbing components other than zinc while leaving zinc adsorbed on the substrate, thereby forming a layer in which zinc and oxygen are bonded.

[0418] By repeating the above-described method, an In-M-Zn oxide can be formed as an oxide semiconductor layer on a layer that is a formation surface by an ALD method.

[0419] When an oxide semiconductor layer is formed by the ALD method, ozone (O ３ ), oxygen (O ２ ), water (H ２ O) and the like can be used. ３ ), oxygen (O ２ By using HCl, HCl, or the like as an oxidizing agent, the amount of hydrogen mixed into the oxide semiconductor layer can be reduced.

[0420] In the above, after the precursor is adsorbed, it is preferable to stop the introduction of the precursor-containing source gas, purge the reaction chamber, and then discharge the excess precursor, reaction products, etc. from the reaction chamber. Also, in the above, it is preferable to stop the introduction of the oxidant, after the adsorbed precursor is reacted with the oxidant, purge the reaction chamber, and then discharge the excess reactant, reaction products, etc. from the reaction chamber.

[0421] Furthermore, unless otherwise specified in this specification and elsewhere, when ozone, oxygen, or water is used as a reactant or oxidant, it is understood that these are not limited to gaseous or molecular states, but also include plasma, radical, and ionic states.

[0422] The second layer is preferably formed by sputtering.

[0423] An In-M-Zn oxide can be used as a target for sputtering. When forming a metal oxide by sputtering, oxygen or a mixed gas of oxygen and a noble gas can be used as a sputtering gas. In addition, by increasing the proportion of oxygen contained in the sputtering gas, the amount of excess oxygen in the oxide film to be formed can be increased.

[0424] Furthermore, the higher the ratio of the flow rate of oxygen gas to the total film-forming gas used during deposition (hereinafter also referred to as oxygen flow rate ratio), the more crystalline the metal oxide that can be formed.

[0425] When a metal oxide is formed by a sputtering method, an oxygen-excess metal oxide may be formed when the percentage of oxygen contained in the sputtering gas is set to more than 30% and less than or equal to 100%, preferably 70% to 100%. A transistor using an oxygen-excess oxide semiconductor layer for a channel formation region can have relatively high reliability. However, one embodiment of the present invention is not limited thereto. An oxygen-deficient metal oxide is formed when the percentage of oxygen contained in the sputtering gas is set to 1% to 30%, preferably 5% to 20%. A transistor using an oxygen-deficient metal oxide for a channel formation region can have relatively high field-effect mobility.

[0426] When forming a metal oxide using a sputtering method, it is preferable to heat the substrate. By increasing the substrate temperature (e.g., stage temperature) during metal oxide formation, a metal oxide with high crystallinity may be formed. When forming a metal oxide using a sputtering method, the substrate heating temperature is preferably, for example, 100°C or higher and 400°C or lower, and more preferably 200°C or higher and 300°C or lower.

[0427] By using the above-described manufacturing method, the thickness of the mixed layer formed at the interface between the layer to be formed and the metal oxide can be reduced, or the thickness of the alloyed region formed at the interface between the layer to be formed and the metal oxide can be reduced to an extent that it cannot be observed. For example, the thickness of the alloyed region can be set to 0 nm or more and 3 nm or less, preferably 0 nm or more and 2 nm or less, more preferably 0 nm or more and 1 nm or less, and even more preferably 0 nm or more and less than 0.3 nm.

[0428] The thickness of the alloyed region may be calculated by performing a line analysis of the composition of the region and its surroundings using SIMS or energy dispersive X-ray spectroscopy (EDX).

[0429] For example, EDX line analysis is performed on the alloyed region and its periphery, with the direction perpendicular to the surface on which the first layer is formed as the depth direction. Next, in the profile of the quantitative values ​​of each element in the depth direction obtained by the analysis, the depth at which the quantitative value of a metal that is the main component of the first layer and is not the main component of the layer that will become the surface on which the layer is formed (In if the first layer contains In) becomes half-value is defined as the depth (position) of the interface between the region and the first layer. Furthermore, the depth at which the quantitative value of an element that is the main component of the layer that will become the surface on which the layer is formed and is not the main component of the first layer (e.g., Si) becomes half-value is defined as the depth (position) of the interface between the region and the layer that will become the surface on which the layer is formed. From the above, the thickness of the alloyed region can be calculated.

[0430] In the oxide semiconductor layer of one embodiment of the present invention, when the thickness of the alloyed region is observed by EDX analysis, the thickness is, for example, 0 nm to 3 nm, preferably 0 nm to 2 nm, more preferably 0 nm to 1 nm, and still more preferably 0 nm to less than 0.3 nm.

[0431] For example, when SIMS analysis is performed on an oxide semiconductor layer formed on a silicon oxide film that is a surface to be formed, the depth at which the silicon concentration is 50% of the maximum concentration of the silicon oxide film is defined as the interface, and the silicon concentration is 1.0×10 ２１ atoms / cm３ , preferably 5.0 × 10 ２０ atoms / cm ３ , more preferably 1.0 × 10 ２０ atoms / cm ３ The distance between the depth at which the thickness decreases and the interface is defined as thickness t. The thickness t is preferably 3 nm or less, and more preferably 2 nm or less.

[0432] By reducing the thickness of the alloyed region, the thickness t can be set to a value within the above range.

[0433] Note that by reducing the alloyed region, it is possible to form a CAAC structure near the formation surface. Here, the vicinity of the formation surface refers to, for example, a region that is more than 0 nm and not more than 3 nm, preferably more than 0 nm and not more than 2 nm, more preferably 1 nm or more and not more than 2 nm, approximately perpendicularly from the formation surface of the oxide semiconductor layer.

[0434] Note that the CAAC structure near the formation surface can be confirmed in some cases by observation using a TEM. For example, in cross-sectional observation of an oxide semiconductor layer using a high-resolution TEM, bright spots arranged in layers in a direction parallel to the formation surface are confirmed near the formation surface.

[0435] Furthermore, the oxide semiconductor layer of one embodiment of the present invention can have a three-layer structure including a first layer, a second layer over the first layer, and a third layer over the second layer.

[0436] When the oxide semiconductor layer has a three-layer structure, the oxide semiconductor layer can be manufactured by forming a first layer on a surface to be formed by a first film formation method, forming a second layer by a second film formation method, and then forming a third layer by the first film formation method.

[0437] Even when the first layer and the third layer are formed using compositions that make it difficult to form a CAAC structure when a single layer is formed, the oxide semiconductor layer can have a structure in which the entire oxide semiconductor layer including the first layer and the third layer has the CAAC structure by crystal growth using the second layer as a nucleus, or a structure in which the CAAC structure is formed in a region including at least a part of each of the first layer and the third layer and the second layer.

[0438] In particular, even when the first layer and the third layer have a high In content, the oxide semiconductor layer can have suitable crystallinity for a semiconductor layer of a transistor. In the oxide semiconductor layer of one embodiment of the present invention, the increase in the In content can improve the on-state characteristics of the transistor, and the improvement in reliability can be achieved by using a CAAC structure with high crystallinity.

[0439] The first and third layers may be made of a metal oxide having the same composition as that of the second layer. Using the same composition may make it easier for the first and third layers to become CAAC after heat treatment.

[0440] Since the second layer has high crystallinity, the third layer can grow using the crystals of the second layer as nuclei or seeds. Therefore, even if a film formation method that easily imparts crystallinity is not used as a film formation method for the third layer, the third layer can be crystallized. Here, for example, by forming the third layer using a film formation method that has higher coverage than the second layer, the oxide semiconductor layer can have both high crystallinity and high coverage throughout the layer.

[0441] Furthermore, the second layer has excellent crystallinity because the influence of the surface on which it is formed is reduced by providing the first layer, and therefore the third layer, which is crystallized using the second layer as a nucleus or seed, is also expected to have excellent crystallinity.

[0442] When the oxide semiconductor layer is used as a semiconductor layer of a transistor, the third layer, which is the uppermost layer of the oxide semiconductor layer, may be in contact with a gate insulating layer. By increasing the crystallinity of the layer in contact with the gate insulating layer, carrier mobility can be increased when the transistor is on.

[0443] The first layer and the third layer each have high crystallinity, using the highly crystalline second layer as a nucleus or seed. Specifically, the crystallinity of the first layer may be increased by heat treatment during or after the deposition of the second layer. The crystallinity of the third layer may be increased by heat treatment during or after the deposition of the third layer. The heat treatment has an assisting effect of increasing the crystallinity.

[0444] As described above, in the method for forming an oxide semiconductor layer according to one embodiment of the present invention, the crystallinity of the upper and lower metal oxides (the first and third layers here) can be increased by using the second layer having a highly crystalline metal oxide (i.e., CAAC) as a nucleus or seed. This increases the crystallinity of the entire oxide semiconductor. In other words, the upper and lower metal oxides can be grown by solid-phase growth using the second layer as a nucleus or seed, thereby forming an oxide semiconductor layer with high crystallinity. An oxide semiconductor layer formed by such a deposition method, i.e., a CAAC film here, can be referred to as an axial growth CAAC (AG CAAC).

[0445] In the oxide semiconductor layer, a region having a CAAC structure is preferably present widely throughout the layer. The region having the CAAC structure in the first layer is crystallinely connected to the region having the CAAC structure in the second layer. The region having the CAAC structure in the third layer is crystallinely connected to the region having the CAAC structure in the second layer. As a result, the boundary between the first layer and the second layer may not be observed. Furthermore, the boundary between the second layer and the third layer may not be observed. The oxide semiconductor layer may be expressed as a single layer whose interface is not clearly observed. The oxide semiconductor layer may be expressed as a single layer.

[0446] In each of the first to third layers, in a region having the CAAC structure, for example, bright spots aligned parallel or substantially parallel to the surface on which the oxide semiconductor layer is formed are observed in cross-sectional observation using a high-resolution TEM. Furthermore, the c-axis of the CAAC structure in each of the first to third layers is preferably parallel or substantially parallel to the normal direction of the surface on which the oxide semiconductor layer is formed.

[0447] Furthermore, a portion of the first layer or the third layer may not be crystallized.

[0448] In addition, when the oxide semiconductor layer has a three-layer structure, the oxide semiconductor layer can also be manufactured in such a manner that a first layer is formed on a surface to be formed by a first film formation method, a second layer is formed by the first film formation method, and a third layer is formed by the second film formation method.

[0449] As described above, using a metal oxide with a high In content in a transistor can increase the field-effect mobility of the transistor. On the other hand, metal oxides with a high In content tend to have a cubic crystal structure. Therefore, using a metal oxide with a high In content in the second layer in contact with the third layer can form a crystal that reflects the crystal orientation of the third layer.

[0450] Furthermore, it is preferable that the lattice mismatch between the crystals of the third layer and the crystals of the second layer is small. This allows the second layer to have crystals that reflect the orientation of the crystals of the third layer. In this case, for example, in cross-sectional observation of the oxide semiconductor layer using a high-resolution TEM, bright spots arranged in layers in a direction parallel to the formation surface are observed in the second layer.

[0451] The crystal structure of the second layer is not particularly limited as long as the lattice mismatch between the crystals of the third layer and the crystals of the second layer is small. The crystal structure of the second layer may be any of cubic, tetragonal, orthorhombic, hexagonal, monoclinic, and trigonal.

[0452] In the above structure, typically, the first layer may be a layer containing gallium oxide or a metal oxide having an atomic ratio of In:Ga:Zn=1:3:2 or a similar composition, the second layer may be a layer containing indium oxide or a metal oxide containing a trace amount of the aforementioned element M, and the third layer may be a layer containing a metal oxide having an atomic ratio of In:Ga:Zn=1:1:1 or a similar composition. In this case, the first layer contains gallium. Furthermore, when the first layer contains a metal oxide having an atomic ratio of In:Ga:Zn=1:3:2 or a similar composition, the indium content in the first layer is lower than the gallium content. Furthermore, the indium content in the second layer is higher than the indium content in the third layer.

[0453] When the first layer and the second layer are formed using the first film formation method, it is preferable to form the first layer and the second layer successively without exposing them to the atmosphere. By forming the first layer and the second layer successively without exposing them to the atmosphere, productivity can be increased. Furthermore, impurities (typically, moisture, etc.) introduced into the interface between the first layer and the second layer and the vicinity thereof can be reduced.

[0454] One or more of the first to third layers may have a plurality of stacked layers having different compositions. For example, the first layer may be formed by forming a layer containing a metal oxide having a high Ga content by the first deposition method, and then forming a layer containing a metal oxide having a higher In content than the first layer by the first deposition method.

[0455] After forming the layer by the first film formation method, it is preferable to perform microwave plasma treatment.

[0456] In this specification, microwaves refer to electromagnetic waves having a frequency of 300 MHz to 300 GHz. Microwave plasma treatment refers to treatment using a device with a power source that generates high-density plasma using microwaves. Microwave plasma treatment can also be called microwave-excited high-density plasma treatment.

[0457] By performing microwave plasma treatment in an atmosphere containing oxygen, the impurity concentration in the semiconductor layer 230 can be reduced. Examples of impurities include hydrogen and carbon. While the above example illustrates a configuration in which microwave plasma treatment is performed on a metal oxide in an atmosphere containing oxygen, the present invention is not limited to this. For example, microwave plasma treatment may be performed on an insulating film, more specifically, a silicon oxide film, provided near the metal oxide in an atmosphere containing oxygen. Furthermore, the heat generated by the microwave plasma treatment may increase the crystallinity of the oxide semiconductor layer.

[0458] The microwave plasma treatment is preferably carried out under reduced pressure, and the pressure is preferably from 10 to 1000 Pa, more preferably from 50 to 700 Pa, and even more preferably from 100 to 400 Pa. The treatment temperature is preferably from room temperature (e.g., 25°C) to 750°C, more preferably from 300 to 500°C, and can be from 400 to 450°C.

[0459] When microwave plasma treatment is performed, the substrate may be heated. The heating temperature of the substrate is preferably room temperature or higher, 100° C. or higher, 200° C. or higher, 300° C. or higher, or 400° C. or higher, and 500° C. or lower, or 450° C. or lower. For example, the heating temperature of the substrate is preferably room temperature or higher and 500° C. or lower, more preferably 100° C. or higher and 450° C. or lower, more preferably 200° C. or higher and 450° C. or lower, more preferably 300° C. or higher and 450° C. or lower, and even more preferably 400° C. or higher and 450° C. or lower.

[0460] The microwave plasma treatment can be performed using, for example, oxygen gas and argon gas. In the microwave plasma treatment using oxygen gas and argon gas, the main oxygen radical is triplet oxygen (O( ３ P ｊ )), singlet oxygen (O( １ D ２ )), and oxygen ions (O ２ ＋) can take three states. Note that oxygen ions act effectively in reducing the hydrogen concentration in the oxide film by microwave plasma processing. The amount of oxygen radicals in each state varies depending on the oxygen flow rate ratio or pressure in microwave plasma processing. For example, under conditions where the oxygen flow rate ratio is low and the pressure is low, the amount of oxygen ions tends to increase. On the other hand, if the oxygen flow rate ratio or pressure is excessively low, there is a concern that the control of the oxygen flow rate becomes unstable, making it difficult to stabilize the discharge, and that the oxide film may be etched. Therefore, for example, when the oxygen flow rate ratio (O ２ / (O ２ +Ar)) is preferably greater than 0% and not greater than 10%, more preferably 0.5% to 5%, more preferably 0.5% to 3%, and typically more preferably 1%.

[0461] The shorter the processing time of the microwave plasma treatment, the more the oxidation of the conductive layer 220 or the conductive layer 240, etc. can be suppressed. Also, the productivity increases. Therefore, for example, the processing time of the microwave plasma treatment is preferably 1 minute or more and 60 minutes or less, more preferably 1 minute or more and 30 minutes or less, and even more preferably 1 minute or more and 10 minutes or less.

[0462] By performing microwave plasma treatment in an atmosphere containing oxygen, oxygen gas is converted into plasma using microwaves or high frequency waves such as RF, and oxygen radicals generated by converting the oxygen gas into plasma can act on the oxide semiconductor layer. Due to the action of plasma, microwaves, oxygen radicals, or the like, defects in which hydrogen has entered oxygen vacancies in the oxide semiconductor layer (hereinafter referred to as V Ｏ By splitting V (sometimes referred to as H) into oxygen vacancies and hydrogen, the hydrogen impurities can be removed from the oxide semiconductor layer. ＯH can be reduced. At this time, carbon bonded to oxygen, hydrogen, or the like can also be removed in some cases. In this way, impurities such as carbon or hydrogen can be reduced by performing microwave plasma treatment. Furthermore, by supplying the oxygen radicals to oxygen vacancies formed in the oxide semiconductor layer, the oxygen vacancies in the oxide semiconductor layer can be further reduced.

[0463] Furthermore, microwave plasma treatment can improve the crystallinity of a layer formed using the first film formation method. Here, the principle of how microwave plasma treatment improves the crystallinity of an oxide semiconductor will be described. First, activated species such as oxygen radicals excited by microwaves arrive at the surface of the oxide semiconductor, and a substitution reaction occurs between the activated species and oxygen in the oxide semiconductor layer. Nuclei or seeds are formed. Lateral growth of the nuclei or seeds is also induced. It is preferable that the activated species excited by microwaves contain oxygen (typically, oxygen ions), which is easily adsorbed to the side surfaces of the nuclei or seeds, because this promotes the lateral growth. Microwave plasma treatment causes the formation of nuclei or seeds and the lateral growth of the nuclei or seeds, thereby improving the crystallinity of the oxide semiconductor.

[0464] On the other hand, a reaction occurs between part of oxygen present in the oxide semiconductor layer before the microwave plasma treatment and hydrogen in the oxide semiconductor layer, in other words, the reaction proceeds as follows: 2H + O → H ２ O↑” reaction occurs, converting the hydrogen to H ２ O (also called dehydration or dehydrogenation). ２ Since O is one of the factors that hinder improvement of crystallinity, it is preferable to remove hydrogen from the oxide semiconductor layer. ２ The hydrogen concentration in the oxide semiconductor layer can be reduced by removing the hydrogen as O, which can also promote improvement in crystallinity. Note that the hydrogen concentration in the oxide semiconductor layer can be further reduced by increasing the temperature during the microwave plasma treatment.

[0465] After the microwave plasma treatment, a heat treatment may be performed without exposing the substrate to the outside air. The temperature of the heat treatment is, for example, preferably 100° C. or higher and 750° C. or lower, more preferably 300° C. or higher and 500° C. or lower, and even more preferably 400° C. or higher and 450° C. or lower.

[0466] It should be noted that the crystallinity can be improved by plasma treatment containing oxygen gas instead of microwave plasma treatment.

[0467] The crystallinity of the layer formed by the first film formation method can be increased, which can further increase the crystallinity of a layer formed over the layer, thereby increasing the crystallinity of the entire oxide semiconductor layer.

[0468] Oxygen supplied to the oxide semiconductor layer can be in various forms such as oxygen atoms, oxygen molecules, oxygen ions (charged oxygen atoms or oxygen molecules), and oxygen radicals (oxygen atoms, oxygen molecules, or oxygen ions having an unpaired electron). Note that the oxygen injected into the oxide semiconductor layer is preferably in one or more of the above forms, and is particularly preferably in the form of oxygen radicals.

[0469] After the oxide semiconductor layer is formed, heat treatment is preferably performed. The heat treatment can improve the crystallinity of the oxide semiconductor layer. The heat treatment here is not limited to heat treatment. For example, heat applied during a manufacturing process may be used.

[0470] The heat treatment temperature can be, for example, 100°C to 800°C, preferably 250°C to 650°C, and more preferably 350°C to 550°C. Typically, it can be 400°C ± 25°C (375°C to 425°C). The treatment time can be 10 hours or less, for example, 1 minute to 5 hours, or 1 minute to 2 hours. When an RTA (Rapid Thermal Anneal) apparatus is used, the treatment time can be, for example, 1 second to 5 minutes. It is expected that the heat treatment will repair atomic-level crystalline gaps in the CAAC structure of the second layer formed using the second film formation method with the third layer formed using the first film formation method.

[0471] The heating device used for the heat treatment is not particularly limited, and may be a device that heats the workpiece by thermal conduction or thermal radiation from a heating element such as a resistance heating element. For example, an electric furnace or an RTA device such as an LRTA (Lamp Rapid Thermal Anneal) device or a GRTA (Gas Rapid Thermal Anneal) device can be used. The LRTA device is a device that heats the workpiece by radiation of light (electromagnetic waves) emitted from a lamp such as a halogen lamp, a metal halide lamp, a xenon arc lamp, a carbon arc lamp, a high-pressure sodium lamp, or a high-pressure mercury lamp. The GRTA device is a device that performs heat treatment using high-temperature gas.

[0472] The heat treatment step may increase the crystallinity of the region having the CAAC structure in the third layer formed by the first film formation method. Furthermore, if the region is formed only below the third layer after film formation by the ALD method, the heat treatment step may cause the region to expand upward. That is, the heat treatment may cause the region having the CAAC structure to be formed throughout the entire third layer.

[0473] Furthermore, it is preferable that the heat treatment step converts at least a portion of the first layer or the second layer formed using the first film formation method into CAAC. It is expected that the conversion into CAAC is facilitated by the mixed layer formed in the first layer or the second layer during the formation of the layer formed using the second film formation method, which acts as a nucleus or seed. It is preferable that the region converted into CAAC in the first layer or the second layer is wide, and it is preferable that the conversion into CAAC extends to the vicinity of the surface to be formed.

[0474] Furthermore, because the CAAC is formed from the top to the bottom of the first layer or the second layer, the CAAC can be formed up to the vicinity of the layer regardless of the material or crystallinity of the layer on which the CAAC is formed. For example, even if the layer has an amorphous structure, the crystallinity of the first layer or the second layer can be increased. Therefore, the method for forming an oxide semiconductor layer according to one embodiment of the present invention is particularly suitable for the case where the layer on which the CAAC is formed has an amorphous structure.

[0475] As described above, by performing microwave plasma treatment and / or heat treatment, the crystallinity of the entire oxide semiconductor layer can be improved. Furthermore, impurities in the oxide semiconductor layer can be reduced. Crystal growth can be performed in a state where the impurity concentration in the oxide semiconductor layer is reduced, thereby further improving the crystallinity.

[0476] By increasing the crystallinity of the oxide semiconductor layer, an increase in the electrical resistance of the semiconductor layer of a transistor using the oxide semiconductor layer can be suppressed or the initial characteristics (particularly, on-state current) of the transistor can be improved, which is expected to make the transistor suitable for high-speed operation. In addition, the reliability of the transistor can be improved and the on-state current can be increased.

[0477] Note that one or both of the microwave plasma treatment and the heat treatment may be performed directly on the oxide semiconductor layer or may be performed after an insulating film or the like is formed over the oxide semiconductor layer.

[0478] Before forming the first layer or after forming the first layer or the second layer by the first film formation method, treatment for supplying oxygen to the first layer or the second layer may be performed, whereby oxygen can be supplied to the oxide semiconductor layer by heat or the like applied after the treatment.

[0479] Examples of the treatment for supplying oxygen include heat treatment in an oxygen-containing atmosphere, plasma treatment (including microwave plasma treatment) in an oxygen-containing atmosphere, and the like. Alternatively, oxygen may be supplied to the first layer or the second layer formed by the first film formation method by forming an oxide film (preferably a metal oxide film) in an oxygen-containing atmosphere by sputtering. The formed oxide film may be removed immediately after deposition, or may be left as it is. When the formed oxide film is left as it is, the oxide film can be used as a layer (second layer or third layer) provided on the first layer or second layer. Note that the oxygen-containing atmosphere may be oxygen gas (O ２ ) as well as ozone (O ３ ) or nitrous oxide (N ２ The atmosphere includes a gas containing a compound containing oxygen such as oxygen (O). The substrate temperature during the plasma treatment is set to be equal to or higher than room temperature (25° C.) and equal to or lower than 450° C.

[0480] The oxide semiconductor layer of one embodiment of the present invention has high crystallinity throughout the entire layer. Therefore, in the oxide semiconductor layer, the boundaries between the stacked films of the first to third layers may not be visible. In particular, it may be difficult to identify the boundaries between the stacked films after heat treatment. The presence or absence of boundaries between the stacked films can be confirmed using, for example, cross-sectional TEM, cross-sectional scanning transmission electron microscope (STEM), or the like.

[0481] Furthermore, an oxide semiconductor layer having a CAAC structure formed using the above-described two types of film formation methods may have higher relative dielectric constant, film density, and film hardness, in some cases, than an oxide semiconductor layer having a CAAC structure formed using one type of film formation method.

[0482] By using an oxide semiconductor layer having a CAAC structure formed by using the above two types of film formation methods for a channel formation region of a transistor, a transistor with excellent characteristics (e.g., a transistor with high on-state current, a transistor with high field-effect mobility, a transistor with a small S value, a transistor with high frequency characteristics (also referred to as f characteristics), a highly reliable transistor, etc.) can be realized.

[0483] The oxide semiconductor layer of one embodiment of the present invention can be formed by using the first film formation method and one or both of microwave plasma treatment and heat treatment. In other words, the oxide semiconductor layer of one embodiment of the present invention can be formed without using the second film formation method. For example, by performing one or both of microwave plasma treatment and heat treatment after forming a first layer by the first film formation method, the crystallinity of the first layer can be increased. Therefore, the crystallinity of a second layer formed on the first layer by the first film formation method can be increased using the first layer as a nucleus or seed. Furthermore, by performing one or both of microwave plasma treatment and heat treatment after forming the second layer, the crystallinity of the oxide semiconductor layer can be increased. Therefore, a CAAC structure can be formed in the oxide semiconductor layer.

[0484] As described above, even in a manufacturing method that does not use the second film formation method, the first layer formed by the first film formation method can be used as a nucleus or seed to cause solid-phase growth of the oxide semiconductor thereover, thereby forming an oxide semiconductor with high crystallinity. An oxide semiconductor formed by such a film formation method can also be referred to as an AG CAAC.

[0485] When the oxide semiconductor layer has a stacked structure of two or more layers, it can also be formed by forming a metal oxide using one film formation method. When the oxide semiconductor layer has a two-layer structure of a first layer and a second layer over the first layer, the oxide semiconductor layer can be formed, for example, by forming the first layer and the second layer in this order by a sputtering method. Sputtering has a higher film formation rate than ALD, and therefore can improve productivity. For example, when the oxide semiconductor layer has a three-layer structure of a first layer, a second layer over the first layer, and a third layer over the second layer, the first layer to the third layer can also be formed by a sputtering method. Furthermore, some of the first layer to the third layer can also be formed by ALD. For example, one or both of the second layer and the third layer may be formed by ALD.

[0486] [Oxide Semiconductor Layer of Transistor] The oxide semiconductor layer of this embodiment can be used as a semiconductor layer of a transistor.

[0487] The oxide semiconductor layer in this embodiment can be used for the semiconductor layer 230 or the like included in each transistor described in Embodiment 1. The layer that is a formation surface corresponds to the insulating layer 280 or the like described in Embodiment 1. For example, the first layer can be used for the semiconductor layer 230_1, the second layer can be used for the semiconductor layer 230_2, and the third layer can be used for the semiconductor layer 230_3.

[0488] The oxide semiconductor layer of this embodiment preferably has a CAAC structure, in which metal atoms are arranged in layers in a direction parallel or substantially parallel to a surface on which the oxide semiconductor layer is formed.

[0489] It is estimated that an oxide semiconductor layer having a CAAC structure exhibits current anisotropy. For example, in an IGZO crystal, current flows more easily in the a-axis direction than in the c-axis direction. That is, it is estimated that in an oxide semiconductor layer having a CAAC structure, current flows more easily in the horizontal direction than in the vertical direction.

[0490] In the semiconductor device described in the previous embodiment, the semiconductor layer 230 has metal atoms arranged in a layered manner in a direction parallel or substantially parallel to the surface on which the semiconductor layer 230 is formed. It can also be expressed as the a-b plane of the CAAC structure being provided in a direction parallel or substantially parallel to the surface on which the semiconductor layer 230 is formed. With this configuration, the a-b plane of the CAAC structure can be provided along the direction of current flow in the channel of the transistor. This can increase the on-state current of the transistor.

[0491] When the oxide semiconductor layer of this embodiment is used as a semiconductor layer of a transistor, the thickness of the oxide semiconductor layer is, for example, preferably 3 nm to 200 nm, more preferably 3 nm to 100 nm, further preferably 5 nm to 100 nm, further preferably 10 nm to 100 nm, further preferably 10 nm to 70 nm, further preferably 15 nm to 70 nm, further preferably 15 nm to 50 nm, and further preferably 20 nm to 50 nm. In a transistor used in a smaller semiconductor device, the thickness of the semiconductor layer 230 is preferably 1 nm to 20 nm, further preferably 3 nm to 15 nm, further preferably 5 nm to 12 nm, and further preferably 5 nm to 10 nm. The average thickness of the oxide semiconductor layer in a channel formation region of the transistor is particularly preferably, for example, 2 nm to 15 nm.

[0492] The first layer preferably has a thickness of 0.5 nm to 50 nm, more preferably 0.5 nm to 30 nm, more preferably 0.5 nm to 20 nm, more preferably 1 nm to 50 nm, more preferably 1 nm to 30 nm, more preferably 1 nm to 20 nm, and even more preferably 2 nm to 20 nm. The first layer is further preferably 0.5 nm to 3 nm.

[0493] The first layer preferably has a region with a thickness of 0.1 nm to 3 nm, more preferably 0.1 nm to 2 nm, or more preferably 0.5 nm to 3 nm, and even more preferably 0.5 nm to 2 nm.

[0494] The second layer preferably has a thickness of, for example, less than 200 nm. When the second layer is lamellar, the thickness is preferably, for example, 1 nm or more and less than 200 nm, more preferably 1 nm or more and 100 nm or less, and more preferably 2 nm or more and 100 nm or less.

[0495] Alternatively, if the second layer can function as a crystal nucleus, the second layer may not exist in a layered structure but may be an aggregate of island-like regions. In such a case, for example, the island-like regions of the second layer exist discretely.

[0496] For the preferred range of the thickness of the third layer, see the description of the thickness of the first layer.

[0497] [Impurities in Oxide Semiconductor Layer] Here, the influence of each impurity in the oxide semiconductor layer will be described.

[0498] As described in the above embodiment, in a transistor including an oxide semiconductor in a semiconductor layer, oxygen vacancies (V Ｏ) and impurities may cause fluctuations in electrical characteristics and reduce reliability. Therefore, reducing the impurity concentration in the oxide semiconductor layer is effective for stabilizing the electrical characteristics of an OS transistor. To reduce the impurity concentration in the oxide semiconductor layer, it is preferable to also reduce the impurity concentration in a nearby film. Examples of impurities include hydrogen, carbon, and nitrogen. Note that the impurity in the oxide semiconductor layer refers to, for example, any element other than the main component constituting the oxide semiconductor. For example, an element with a concentration of less than 0.1 atomic % can be considered an impurity.

[0499] When an oxide semiconductor contains silicon or carbon, which is one of the Group 14 elements, defect levels are formed in the oxide semiconductor. Therefore, the carbon concentration in the channel formation region of the oxide semiconductor obtained by SIMS is 1×10 ２０ atoms / cm ３ Below 5 × 10, preferably １９ atoms / cm ３ Less than or equal to 3×10 １９ atoms / cm ３ or less, more preferably 1 × 10 １９ atoms / cm ３ Less than or equal to 3×10 １８ atoms / cm ３ More preferably, 1×10 １８ atoms / cm ３ The silicon concentration in the channel formation region of the oxide semiconductor obtained by SIMS is 1×10 ２０ atoms / cm ３ Below 5 × 10, preferably １９ atoms / cm ３ Less than or equal to 3×10 １９ atoms / cm ３ or less, more preferably 1 × 10 １９ atoms / cm ３ Less than or equal to 3×10 １８ atoms / cm ３ More preferably, 1×10 １８ atoms / cm ３ The following applies.

[0500] Furthermore, when nitrogen is contained in an oxide semiconductor, electrons serving as carriers are generated, the carrier concentration increases, and the resistance tends to be low. As a result, a transistor using an oxide semiconductor containing nitrogen as a semiconductor tends to be normally on. Alternatively, when nitrogen is contained in an oxide semiconductor, trap states may be formed. As a result, the electrical characteristics of the transistor may become unstable. Therefore, the nitrogen concentration in the channel formation region of the oxide semiconductor obtained by SIMS is 1×10 ２０ atoms / cm ３ Below 5 × 10, preferably １９ atoms / cm ３ Less than 1×10, more preferably 1×10 １９ atoms / cm ３ Less than or equal to 5×10, more preferably １８ atoms / cm ３ Less than 1×10, more preferably 1×10 １８ atoms / cm ３ or less, more preferably 5 × 10 １７ atoms / cm ３ The following applies.

[0501] Furthermore, hydrogen contained in an oxide semiconductor reacts with oxygen bonded to a metal atom to form water, which may form an oxygen vacancy. Hydrogen entering the oxygen vacancy may generate electrons as carriers. Furthermore, some of the hydrogen may bond with oxygen bonded to a metal atom to generate electrons as carriers. Therefore, a transistor using an oxide semiconductor containing hydrogen is likely to be normally on. Therefore, it is preferable to reduce hydrogen as much as possible in the channel formation region of the oxide semiconductor. Specifically, the hydrogen concentration in the channel formation region of the oxide semiconductor obtained by SIMS is 1×10 ２０ atoms / cm ３ Less than 5×10 １９ atoms / cm ３ less than 1×10 １９ atoms / cm ３ less than 5×10 １８ atoms / cm ３less than 1×10 １８ atoms / cm ３ less than 1×10 １７ atoms / cm ３ Less than.

[0502] Furthermore, when an oxide semiconductor contains an alkali metal or an alkaline earth metal, defect levels are formed and carriers are generated in some cases. Therefore, a transistor using an oxide semiconductor containing an alkali metal or an alkaline earth metal is likely to be normally on. Therefore, when the concentration of the alkali metal or the alkaline earth metal in the channel formation region of the oxide semiconductor obtained by SIMS is set to 1×10 １８ atoms / cm ３ Below 2 × 10, preferably １６ atoms / cm ３ Do the following:

[0503] When an oxide semiconductor with sufficiently reduced impurities is used for a channel formation region of a transistor, stable electrical characteristics can be obtained.

[0504] This embodiment mode can be combined with other embodiment modes as appropriate. In addition, in this specification, when a plurality of configuration examples are shown in one embodiment mode, the configuration examples can be combined as appropriate.

[0505] Embodiment 3 In this embodiment, a memory device according to one embodiment of the present invention will be described with reference to drawings. The memory device according to one embodiment of the present invention includes a memory cell. The memory cell includes a transistor and a capacitor.

[0506] <Structure Example 1 of Memory Device> The structure of a memory device including a transistor and a capacitor will be described below. FIG. 27A1 is a plan view illustrating a structure example of a memory cell 150 included in a memory device of one embodiment of the present invention. As illustrated in FIG. 27A1 , the memory cell 150 includes a capacitor 100 and a transistor 200. Here, the structure described in Embodiment 1 can be applied to the transistor 200. The transistor included in the memory cell 150 is not limited to the transistor 200, and each of the transistors described in Embodiment 1 can be applied.

[0507] 27A2 is a plan view of FIG. 27A1 from which conductive layer 245, conductive layer 260, and insulating layer 280 have been omitted, and insulating layer 180 has been added. FIG. 27B is a cross-sectional view taken along dashed-dotted lines A1-A2 in FIGS. 27A1 and 27A2. FIG. 27C is a cross-sectional view taken along dashed-dotted lines B1-B2 in FIGS. 27A1 and 27A2. For an example cross-sectional configuration taken along dashed-dotted lines A3-A4 in FIGS. 27A1 and 27A2, refer to FIG. 1C. For an example cross-sectional configuration taken along dashed-dotted lines B3-B4 in FIGS. 27A1 and 27A2, refer to FIG. 1E.

[0508] 27A1 to 27C includes an insulating layer 140 over a substrate (not shown), a conductive layer 110 over the insulating layer 140, a memory cell 150 over the conductive layer 110, an insulating layer 180 over the conductive layer 110, an insulating layer 280 over the insulating layer 180, an insulating layer 285 over the insulating layer 280, and a conductive layer 245 over the insulating layer 285 and over the memory cell 150. The insulating layer 140, the insulating layer 180, the insulating layer 280, and the insulating layer 285 function as interlayer films. The conductive layer 110 functions as a wiring.

[0509] The memory cell 150 includes a capacitor 100 on a conductive layer 110 and a transistor 200 on the capacitor 100 .

[0510] The capacitor 100 has a conductive layer 115 on the conductive layer 110 , an insulating layer 130 on the conductive layer 115 , and a conductive layer 220 on the insulating layer 130 .

[0511] In the capacitor 100, the conductive layer 220 functions as one of a pair of electrodes (sometimes referred to as an upper electrode), the conductive layer 115 functions as the other of the pair of electrodes (sometimes referred to as a lower electrode), and the insulating layer 130 functions as a dielectric. In other words, the capacitor 100 constitutes a metal-insulator-metal (MIM) capacitor.

[0512] As shown in FIGS. 27B and 27C , an opening 190 is provided in the insulating layer 180, reaching the conductive layer 110. The conductive layer 115 is disposed within the opening 190. The conductive layer 115 has a region in contact with the top surface of the conductive layer 110 within the opening 190 and a region in contact with the side surface of the insulating layer 180 within the opening 190. The insulating layer 130 is disposed so as to be located within the opening 190. The conductive layer 220 is disposed so that at least a portion thereof is located within the opening 190. As shown in FIGS. 27B and 27C , the conductive layer 220 is preferably disposed so as to fill the opening 190. The films disposed within the opening 190 are preferably formed using an ALD method. This improves the film coverage. For example, the conductive layer 115, the insulating layer 130, and the conductive layer 220 are preferably formed using an ALD method.

[0513] The capacitor 100 has a configuration in which the upper electrode and the lower electrode face each other across a dielectric not only on the bottom surface but also on the side surfaces within the opening 190, allowing for a larger capacitance per unit area. Therefore, the deeper the opening 190, the larger the capacitance of the capacitor 100 can be. Increasing the capacitance per unit area of ​​the capacitor 100 in this way can stabilize the read operation of the memory device. Furthermore, it is possible to promote miniaturization or high integration of memory devices.

[0514] As shown in Figures 27A1 and 27A2, it is preferable that opening 190 is circular in plan view. By making it circular, the processing accuracy when forming opening 190 can be improved, and opening 190 of a fine size can be formed. Note that in this specification and the like, "circular" is not limited to a perfect circle. Also, in this embodiment, an example has been shown in which opening 190 is circular in plan view, but the present invention is not limited to this. Shapes that can be applied to opening 190 are the same as the shapes that can be applied to opening 271 described above.

[0515] 27B and 27C show an example in which the sidewall of the opening 190 is perpendicular to the top surface of the conductive layer 110. In this case, the opening 190 has a cylindrical shape. With such a structure, miniaturization or high integration of the memory device can be achieved.

[0516] A conductive layer 115 is provided along the sidewall of the opening 190 and the upper surface of the conductive layer 110. An insulating layer 130 is provided on the conductive layer 115. A conductive layer 220 is provided on the insulating layer 130 so as to fill the opening 190. A capacitor 100 having such a configuration may be referred to as a trench capacitor. However, the configuration of the capacitor 100 is not limited to this, and for example, a pillar capacitor, a parallel plate capacitor, or the like may also be used.

[0517] The insulating layer 140 can be made of an insulating material that can be used for the insulating layer 210 .

[0518] Since the insulating layer 180 functions as an interlayer film, it preferably has a low dielectric constant. By using a material with a low dielectric constant as the interlayer film, the parasitic capacitance generated between wirings can be reduced. As the insulating layer 180, an insulating layer containing a material with a low dielectric constant can be used in a single layer or a stacked layer. Silicon oxide and silicon oxynitride are preferable because they are thermally stable. Note that the insulating layer 180 can use an insulating material that can be used for the insulating layer 280, or the like.

[0519] An insulating layer 280 is disposed on the capacitor 100 .

[0520] As shown in FIG. 27B , the transistor 200 is provided so as to overlap with the capacitor 100. Furthermore, the groove 290 in which part of the structure of the transistor 200 is provided has a region that overlaps with the opening 190 in which part of the structure of the capacitor 100 is provided. With this configuration, the transistor 200 and the capacitor 100 can be provided without significantly increasing the occupied area in a plan view. This reduces the occupied area of ​​the memory cells 150, allowing the memory cells 150 to be arranged at a high density and increasing the storage capacity of the storage device. In other words, the storage device can be highly integrated.

[0521] FIG. 27B illustrates an example in which the width of the opening 190 in the X direction is equal to or approximately equal to the width of the groove 290. The relationship in size between the width of the opening 190 and the width of the groove 290 is not particularly limited. The width of the opening 190 can be smaller than the width of the groove 290. By making the width of the opening 190 in the X direction smaller than the width of the groove 290, the alignment accuracy between the end of the conductive layer 220 and the opening 190 can be reduced, making it relatively easy to process the conductive layer 220. Furthermore, miniaturization or high integration of the memory device can be achieved. Furthermore, the width of the opening 190 can be larger than the width of the groove 290 in the X direction. By making the width of the opening 190 larger than the width of the groove 290 in the X direction, the capacitance of the capacitor 100 can be increased. Note that, for example, as shown in FIG. 27B , the relationship in size between the two widths in the semiconductor device of one embodiment of the present invention can be confirmed by a cross section parallel to the Z direction.

[0522] Furthermore, by providing the transistor 200 above the capacitor 100, the transistor 200 is not affected by heat treatment during manufacturing of the capacitor 100. Therefore, in the transistor 200, deterioration of electrical characteristics such as a change in threshold voltage and an increase in parasitic resistance, as well as an increase in variation in electrical characteristics due to the deterioration of electrical characteristics, can be suppressed.

[0523] Here, Fig. 28A is a plan view showing an example of a memory device in which a plurality of memory cells 150 shown in Fig. 27A1 are arranged. Fig. 28A shows an example in which 2 x 2 memory cells 150 are arranged in the X direction and the Y direction. Note that the X direction shown in Fig. 28A is parallel to the A1-A2 direction shown in Fig. 27A1, and the Y direction shown in Fig. 28A is parallel to the B1-B2 direction shown in Fig. 27A1.

[0524] 28A , a conductive layer 240 can be shared between two adjacent memory cells 150. A conductive layer 245 extending in the X direction can connect multiple conductive layers 240 arranged in the X direction to each other. A conductive layer 260 extending in the Y direction can be shared between multiple memory cells 150 arranged in the Y direction.

[0525] 28A, the semiconductor layer 230 can be shared between memory cells 150 adjacent in the X direction. Furthermore, as shown in FIG. 28A, a plurality of semiconductor layers 230 are provided in one groove 290.

[0526] 28B is a circuit diagram showing a configuration example of 2×2 memory cells 150. As described above, the memory cell 150 includes a transistor 200 and a capacitor 100. One of the source and the drain of the transistor 200 is connected to one of a pair of electrodes of the capacitor 100. The other of the source and the drain of the transistor 200 is connected to a wiring BIL. The gate of the transistor 200 is connected to a wiring WOL. The other of the pair of electrodes of the capacitor 100 is connected to a wiring CAL.

[0527] Here, the wiring BIL corresponds to the conductive layer 245. The wiring WOL corresponds to the conductive layer 260. The wiring CAL corresponds to the conductive layer 110.

[0528] As shown in Figure 28A, it is preferable that the conductive layer 245 is provided extending in the X direction, and the conductive layer 260 is provided extending in the Y direction. With this configuration, the wiring BIL and the wiring WOL are provided so as to intersect with each other. Also, in Figure 28A, the wiring CAL is provided parallel to the wiring BIL. However, the present invention is not limited to this. For example, the wiring CAL may be provided parallel to the wiring WOL.

[0529] The memory cells will be described in detail in a later embodiment.

[0530] The capacitor 100 includes a conductive layer 115, an insulating layer 130, and a conductive layer 220. The conductive layer 110 is provided below the conductive layer 115. The conductive layer 115 has a region in contact with the conductive layer 110.

[0531] The conductive layer 110 functions as wiring CAL and can be provided in, for example, a strip shape. Note that the strip shape refers to a shape having an area extending in a certain direction (for example, the X direction, Y direction, or Z direction).

[0532] The conductive layer 110 has a recess in the area overlapping the opening 190 .

[0533] The conductive layer 110 can be formed as a single layer or a stacked layer using the conductive material described in the section [Conductive Layer] of Embodiment 1. For example, a conductive material with high conductivity such as tungsten can be used as the conductive layer 110. By using such a conductive material with high conductivity, the conductivity of the conductive layer 110 can be improved, and the conductive layer 110 can function sufficiently as a wiring CAL.

[0534] The conductive layer 115 has a region 101 with rounded corners in the recess of the conductive layer 110. This makes it possible to suppress electric field concentration in the insulating layer 130 near the region 101, compared to when the region 101 is a right angle or an acute angle (having a corner), for example. Furthermore, the end 103 of the conductive layer 115 is located at a position lower in height from the reference plane than the top surface of the insulating layer 180. This makes it possible to suppress electric field concentration in the insulating layer 130 near the end 103, compared to when the end 103 is located on the insulating layer 180. As described above, suppressing electric field concentration in the insulating layer 130 suppresses dielectric breakdown of the insulating layer 130, and a highly reliable memory device can be provided.

[0535] The conductive layer 115 can be formed as a single layer or a stacked layer using the conductive material described in the section [Conductive Layer] of Embodiment 1. For the conductive layer 115, a conductive material that is not easily oxidized or a conductive material that has a function of suppressing oxygen diffusion, or the like, may be used as a single layer or a stacked layer. For example, titanium nitride, ITSO, or the like may be used. Alternatively, for example, a structure in which titanium nitride is stacked on tungsten may be used. Alternatively, for example, a structure in which tungsten is stacked on a first titanium nitride and a second titanium nitride is stacked on the tungsten may be used. With such a structure, when an oxide is used for the insulating layer 130, the insulating layer 130 can prevent the conductive layer 115 from being oxidized. Furthermore, when an oxide is used for the insulating layer 180, the insulating layer 180 can prevent the conductive layer 115 from being oxidized.

[0536] The insulating layer 130 is provided on the conductive layer 115. The insulating layer 130 is provided so as to be in contact with the upper surface of the conductive layer 115. In other words, the insulating layer 130 preferably has a structure that covers the end portion of the conductive layer 115. This can prevent the conductive layer 115 and the conductive layer 220 from shorting out.

[0537] It is preferable to use a material with a high relative dielectric constant for the insulating layer 130. By using a material with a high relative dielectric constant for the insulating layer 130, the insulating layer 130 can be made thick enough to suppress leakage current, and the capacitance of the capacitor 100 can be increased.

[0538] Furthermore, the insulating layer 130 is preferably formed by stacking insulating layers made of a material with a high dielectric constant, and preferably by using a layered structure of a material with a high dielectric constant and a material with a higher dielectric strength than the material with a high dielectric constant. For example, the insulating layer 130 can be formed by stacking zirconium oxide, aluminum oxide, and zirconium oxide in this order. Alternatively, the insulating layer 130 can be formed by stacking zirconium oxide, aluminum oxide, zirconium oxide, and aluminum oxide in this order. Alternatively, the insulating layer 130 can be formed by stacking hafnium zirconium oxide, aluminum oxide, hafnium zirconium oxide, and aluminum oxide in this order. By stacking insulating layers with a relatively high dielectric strength, such as aluminum oxide, the dielectric strength is improved, and electrostatic breakdown of the capacitor 100 can be suppressed.

[0539] Furthermore, a material that can have ferroelectricity can be used for the insulating layer 130. For details about the material that can have ferroelectricity, refer to the description in Embodiment Mode 1.

[0540] Metal oxides containing one or both of hafnium and zirconium can have ferroelectricity even when the thickness is as thin as a few nanometers, and are therefore preferred as the insulating layer 130. The film thickness of the insulating layer 130 is preferably 100 nm or less, more preferably 50 nm or less, even more preferably 20 nm or less, and even more preferably 10 nm or less (typically, 2 nm to 9 nm). Furthermore, for example, the film thickness is preferably 8 nm to 12 nm. By using a ferroelectric layer that can be thinned, the capacitor 100 can be combined with semiconductor elements such as miniaturized transistors to form a semiconductor device.

[0541] Furthermore, a metal oxide containing one or both of hafnium and zirconium can have ferroelectricity even in a small area, and is therefore preferable as the insulating layer 130. For example, when the area (occupied area) of the ferroelectric layer in a plan view is 100 μm ２ Below, 10μm ２ Below, 1μm ２ or less than 0.1 μm ２ Even if the thickness is less than 10,000 nm, the film can still have ferroelectricity. ２ or less than 1000 nm ２ Even if the thickness is less than 100 Å, the ferroelectric layer may still have ferroelectricity. By using a ferroelectric layer with a small area, the area occupied by the capacitor 100 can be reduced.

[0542] Yttrium can also be added to metal oxides containing either or both of hafnium and zirconium. For example, adding yttrium to hafnium zirconium oxide can enhance ferroelectricity.

[0543] A ferroelectric material is an insulator that generates polarization internally when an external electric field is applied, and the polarization remains even when the electric field is removed. Therefore, a nonvolatile memory element can be formed using a capacitor (h...

Claims

forming an insulating layer; forming a groove in the insulating layer; forming a semiconductor film so as to have a region along a sidewall of the trench; A method for manufacturing a semiconductor device, comprising: performing a process including a dry etching process for removing a portion of the semiconductor film including a region along the sidewall of the groove; and a product removal process for removing a product produced by the dry etching process, multiple times to form a semiconductor layer having a region along the sidewall of the groove. 　 forming a first conductive layer, a first insulating layer on the first conductive layer, and a conductive film on the first insulating layer; forming a groove portion in the conductive film and the first insulating layer, the groove portion reaching the first conductive layer; forming a semiconductor film so as to have a region along a sidewall of the trench, a region along an upper surface of the first conductive layer in the trench, and a region located on the conductive film; a dry etching process for removing a portion of the semiconductor film including a region along the sidewall of the trench, and a product removal process for removing a product generated by the dry etching process, are performed multiple times to form a semiconductor layer having a region along the sidewall of the trench; forming a second conductive layer and a third conductive layer that face each other across the groove portion in a plan view by processing the conductive film; forming a second insulating layer on the semiconductor layer so as to have a region located within the groove; forming a fourth conductive layer on the second insulating layer so as to have a region located within the trench; 　 In claim 2, forming a third insulating layer on the fourth conductive layer and on the second insulating layer; forming a first opening reaching the second conductive layer and a second opening reaching the third conductive layer in the third insulating layer, the second insulating layer, and the semiconductor layer; forming a fifth conductive layer in the first opening so as to have a region in contact with the second conductive layer, and a sixth conductive layer in the second opening so as to have a region in contact with the third conductive layer; a seventh conductive layer formed to have a region in contact with the fifth conductive layer, a region in contact with the sixth conductive layer, and a region located on the third insulating layer; 　 In claim 3, The groove portion is formed to extend in a first direction in a plan view, the seventh conductive layer is formed to extend in a second direction in a plan view; The method for manufacturing a semiconductor device, wherein the second direction is perpendicular or substantially perpendicular to the first direction. 　 In any one of claims 1 to 4, The method for manufacturing a semiconductor device, wherein the by-product removal treatment includes plasma treatment. 　 In claim 5, The method for manufacturing a semiconductor device, wherein the plasma treatment is performed in an atmosphere containing one or both of an oxygen gas and an inert gas. 　 In any one of claims 1 to 4, The method for manufacturing a semiconductor device, wherein the product comprises carbon. 　 In claim 7, The method for manufacturing a semiconductor device, wherein the dry etching treatment is performed using a gas containing carbon. 　 In claim 7, After forming the semiconductor film, a mask containing carbon is formed on the semiconductor film; The method for manufacturing a semiconductor device further comprises forming the mask and then performing the dry etching process. 　 In any one of claims 1 to 4, the semiconductor film includes a metal oxide; The method for manufacturing a semiconductor device, wherein the metal oxide contains indium.

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