Semiconductor device

Abstract

This semiconductor device includes: a substrate of a first conductivity type having a first concentration; a semiconductor layer of a first conductivity type having a second concentration lower than the first concentration and laminated on the substrate; and a buffer layer of a first conductivity type interposed between the substrate and the semiconductor layer, the buffer layer including a low concentration part having a third concentration lower than the first concentration on the substrate side and a high concentration part having a fourth concentration higher than the third concentration on the semiconductor layer side.

Description

Semiconductor Devices

[0001] This application claims priority to Patent Application No. 2024-032384 filed with the Japan Patent Office on March 4, 2024, the entire contents of which are incorporated herein by reference. TECHNICAL FIELD The present disclosure relates to a semiconductor device.

[0002] Patent Document 1 (US2021 / 0280707A1) discloses a semiconductor device including a silicon carbide substrate, an epitaxial layer, and a buffer layer. The epitaxial layer is stacked on the silicon carbide substrate, and the buffer layer has the same concentration as the silicon carbide substrate and is interposed between the silicon carbide substrate and the epitaxial layer.

[0003] US Patent Application Publication No. 2021 / 0280707

[0004] SUMMARY The present disclosure provides a novel semiconductor device.

[0005] The present disclosure provides a semiconductor device including: a substrate of a first conductivity type having a first concentration; a semiconductor layer of a first conductivity type having a second concentration less than the first concentration and stacked on the substrate; and a buffer layer of a first conductivity type interposed between the substrate and the semiconductor layer, the buffer layer including a low concentration portion on the substrate side having a third concentration less than the first concentration and a high concentration portion on the semiconductor layer side having a fourth concentration higher than the third concentration.

[0006] The present disclosure provides a semiconductor device including: a substrate of a first conductivity type having a first concentration; a semiconductor layer of the first conductivity type having a second concentration less than the first concentration and stacked on the substrate; a buffer layer of the first conductivity type including a low concentration portion on the substrate side having a third concentration less than the first concentration and a high concentration portion on the semiconductor layer side having a fourth concentration higher than the third concentration, the buffer layer being interposed between the substrate and the semiconductor layer; and a device structure formed in the semiconductor layer.

[0007] The present disclosure provides a semiconductor device including: a substrate of a first conductivity type having a first concentration; a semiconductor layer of a first conductivity type having a second concentration less than the first concentration and stacked on the substrate; a buffer layer of a first conductivity type including a low concentration portion on the substrate side having a third concentration less than the first concentration and a high concentration portion on the semiconductor layer side having a fourth concentration higher than the third concentration, the buffer layer being interposed between the substrate and the semiconductor layer; an impurity region of a second conductivity type formed in the semiconductor layer; and a trench electrode type gate structure formed in the semiconductor layer.

[0008] The present disclosure provides a semiconductor device including: a substrate of a first conductivity type having a first concentration; a semiconductor layer of the first conductivity type having a second concentration less than the first concentration and stacked on the substrate; a buffer layer of the first conductivity type including a low concentration portion on the substrate side having a third concentration less than the first concentration and a high concentration portion on the semiconductor layer side having a fourth concentration higher than the third concentration, the buffer layer being interposed between the substrate and the semiconductor layer; an impurity region of a second conductivity type formed in the semiconductor layer; and a planar electrode type gate structure arranged on the semiconductor layer.

[0009] The present disclosure provides a semiconductor device including: a substrate of a first conductivity type having a first concentration; a semiconductor layer of a first conductivity type having a second concentration less than the first concentration and stacked on the substrate; a buffer layer of a first conductivity type including a low concentration portion on the substrate side having a third concentration less than the first concentration and a high concentration portion on the semiconductor layer side having a fourth concentration higher than the third concentration, the buffer layer being interposed between the substrate and the semiconductor layer; a trench electrode type gate structure formed in the semiconductor layer; and a well region of a second conductivity type formed in the semiconductor layer below the gate structure and spaced from the buffer layer in a thickness direction.

[0010] The present disclosure provides a semiconductor device including: a substrate of a first conductivity type having a first concentration; a semiconductor layer of a first conductivity type having a second concentration less than the first concentration and stacked on the substrate; a buffer layer of a first conductivity type including a low concentration portion on the substrate side having a third concentration less than the first concentration and a high concentration portion on the semiconductor layer side having a fourth concentration higher than the third concentration, the buffer layer being interposed between the substrate and the semiconductor layer; and a plurality of well regions of a second conductivity type formed in the semiconductor layer at intervals in the horizontal direction and extending vertically in a thickness direction of the semiconductor layer.

[0011] The present disclosure provides a semiconductor device including: a substrate of a first conductivity type having a first concentration; a semiconductor layer of a first conductivity type having a second concentration less than the first concentration and stacked on the substrate; a buffer layer of a first conductivity type including a low concentration portion on the substrate side having a third concentration less than the first concentration and a high concentration portion on the semiconductor layer side having a fourth concentration higher than the third concentration, the buffer layer being interposed between the substrate and the semiconductor layer; an active region provided in an inner portion of the semiconductor layer; a peripheral region provided on a periphery of the semiconductor layer; and an outer well region of a second conductivity type formed in the semiconductor layer at a distance in a thickness direction from the buffer layer in the peripheral region so as to partition the active region and the peripheral region.

[0012] The present disclosure provides a semiconductor device comprising: a substrate of a first conductivity type having a first concentration; a semiconductor layer of the first conductivity type having a second concentration less than the first concentration and stacked on the substrate; a buffer layer of the first conductivity type including a low concentration portion on the substrate side having a third concentration less than the first concentration and a high concentration portion on the semiconductor layer side having a fourth concentration higher than the third concentration, the buffer layer being interposed between the substrate and the semiconductor layer; an active region provided in an inner portion of the semiconductor layer; a peripheral region provided on a peripheral portion of the semiconductor layer; and at least one field region of a second conductivity type formed in the semiconductor layer in the peripheral region spaced apart from the buffer layer in a thickness direction.

[0013] The present disclosure provides a semiconductor device including: a substrate of a first conductivity type having a first concentration; a semiconductor layer of the first conductivity type having a second concentration less than the first concentration and stacked on the substrate; a buffer layer of the first conductivity type including a low concentration portion on the substrate side having a third concentration less than the first concentration and a high concentration portion on the semiconductor layer side having a fourth concentration higher than the third concentration, the buffer layer being interposed between the substrate and the semiconductor layer; and an electrode forming a Schottky junction with the semiconductor layer.

[0014] The present disclosure provides a semiconductor package including a package body, a support substrate disposed within the package body, at least one terminal extending inside and outside the package body, and the semiconductor device disposed on the support substrate within the package body so as to be electrically connected to the at least one terminal.

[0015] The present disclosure provides a semiconductor module including a first substrate, a semiconductor package disposed on the first substrate, and a second substrate provided above the semiconductor package.

[0016] The above and other objects, features and advantages will become more apparent from the following detailed description taken in conjunction with the accompanying drawings.

[0017] FIG. 1 is a plan view showing a semiconductor device according to a basic embodiment. FIG. 2 is a cross-sectional view taken along line II-II in FIG. 1. FIG. 3A is a graph showing a first example concentration gradient of a buffer layer. FIG. 3B is a graph showing a second example concentration gradient of a buffer layer. FIG. 3C is a graph showing a third example concentration gradient of a buffer layer. FIG. 3D is a graph showing a fourth example concentration gradient of a buffer layer. FIG. 3E is a graph showing a fifth example concentration gradient of a buffer layer. FIG. 3F is a graph showing a sixth example concentration gradient of a buffer layer. FIG. 3G is a graph showing a seventh example concentration gradient of a buffer layer. FIG. 3H is a graph showing an eighth example concentration gradient of a buffer layer. FIG. 3I is a graph showing a ninth example concentration gradient of a buffer layer. FIG. 3J is a graph showing a tenth example concentration gradient of a buffer layer. FIG. 3K is a graph showing an eleventh example concentration gradient of a buffer layer. FIG. 3L is a graph showing a twelfth example concentration gradient of a buffer layer. FIG. 3M is a graph showing a thirteenth example concentration gradient of a buffer layer. FIG. 4 is a cross-sectional view showing a semiconductor device according to a comparative example. FIG. 5 is a graph showing carrier density of the semiconductor device according to the comparative example. FIG. 6 is a cross-sectional view showing the semiconductor device shown in FIG. 1. FIG. 7 is a graph showing carrier density of the semiconductor device shown in FIG. 1. FIG. 8 is a plan view showing a semiconductor device according to the first embodiment. FIG. 9 is a cross-sectional view taken along line IX-IX shown in FIG. 8. FIG. 10 is an enlarged plan view showing a main portion of the first main surface. FIG. 11 is a cross-sectional view taken along line XI-XI shown in FIG. 10. FIG. 12 is a cross-sectional view taken along line XII-XII shown in FIG. 10. FIG. 13 is a cross-sectional view taken along line XIII-XIII shown in FIG. 7. FIG. 14 is an enlarged plan view showing a main portion of the first main surface of a semiconductor device according to a second embodiment. FIG. 15 is a cross-sectional view taken along line XV-XV shown in FIG. 14. FIG. 16 is a cross-sectional view taken along line XVI-XVI shown in FIG. 14. FIG. 17 is an enlarged plan view showing a main portion of the first main surface of a semiconductor device according to a third embodiment. Fig. 18 is a cross-sectional view taken along line XVIII-XVIII shown in Fig. 17. Fig. 19 is a plan view showing a semiconductor device according to a fourth embodiment. Fig. 20 is a cross-sectional view taken along line XX-XX shown in Fig. 19. Fig. 21 is an enlarged plan view showing a main portion of the first main surface. Fig. 22 is a cross-sectional view taken along line XXII-XXII shown in Fig. 21. Fig. 23 is a cross-sectional view taken along line XXIII-XXIII shown in Fig. 19.FIG. 24 is a cross-sectional view showing a semiconductor device according to a fifth embodiment. FIG. 25 is a plan view showing a semiconductor device according to a sixth embodiment. FIG. 26 is a cross-sectional view taken along line XXVI-XXVI shown in FIG. 25. FIG. 27 is a plan view showing a semiconductor device according to a seventh embodiment. FIG. 28 is a perspective view showing a semiconductor package. FIG. 29 is a plan view showing a semiconductor package. FIG. 30 is a front view showing a semiconductor package. FIG. 31 is a bottom view showing a semiconductor package. FIG. 32 is a plan view showing an internal structure of the semiconductor package. FIG. 33 is a plan view showing a further internal structure of the semiconductor package. FIG. 34 is a cross-sectional view taken along line XXXIV-XXXIV shown in FIG. 32. FIG. 35 is a cross-sectional view taken along line XXXV-XXXV shown in FIG. 32. FIG. 36 is a cross-sectional view taken along line XXXVI-XXXVI shown in FIG. 32. FIG. 37 is a cross-sectional view taken along line XXXVII-XXXVII shown in FIG. 32. FIG. 38 is an enlarged cross-sectional view showing a main portion of FIG. 34. FIG. 39 is an enlarged cross-sectional view showing another main portion of FIG. 34. 40 is an enlarged cross-sectional view showing another main part of FIG. 35. FIG. 41 is a circuit diagram showing an example of the electrical configuration of a semiconductor package. FIG. 42 is a perspective view showing a semiconductor module. FIG. 43 is a perspective view showing FIG. 42 with the wiring board omitted. FIG. 44 is a plan view showing the semiconductor module. FIG. 45 is a plan view showing FIG. 42 with the wiring board omitted. FIG. 46 is a front view showing the semiconductor module. FIG. 47 is a bottom view showing the semiconductor module. FIG. 48 is a left side view showing the semiconductor module. FIG. 49 is a right side view showing the semiconductor module. FIG. 50 is a cross-sectional view taken along line LL shown in FIG. 45. FIG. 51 is a cross-sectional view taken along line LI-LI shown in FIG. 45. FIG. 52 is a cross-sectional view taken along line LII-LII shown in FIG. 45. FIG. 53 is a cross-sectional view taken along line LIII-LIII shown in FIG. 45. FIG. 54 is a cross-sectional view taken along line LIV-LIV shown in FIG. 45. FIG. 55 is a partially enlarged cross-sectional view of the semiconductor module. Fig. 56 is a circuit diagram showing an example of the electrical configuration of a semiconductor module, and Fig. 57 is a schematic diagram of a vehicle including the semiconductor module.

[0018] [Detailed Description] Specific embodiments will be described in detail below with reference to the accompanying drawings. The accompanying drawings are all schematic diagrams and are not strictly illustrative, and the relative positional relationships, scales, ratios, angles, etc. are not necessarily consistent. Corresponding structures among the accompanying drawings are given the same reference numerals, and duplicated descriptions are omitted or simplified. For structures whose descriptions are omitted or simplified, the descriptions given before the omission or simplification apply.

[0019] In this specification, open language such as "including" and "having" is described as a concept that encompasses closed language such as "consisting of." When the term "substantially" is used in this specification, this term not only includes a numerical value (form) that is equal to the numerical value (form) of the comparison target, but also includes a numerical error (form error) within a range of ±10% based on the numerical value (form) of the comparison target.

[0020] In this specification, terms such as "first," "second," and "third" are used, but these are symbols added to the names of each structure to clarify the order of explanation, and are not added with the intention of limiting the names of each structure.

[0021] In this specification, the conductivity type of a semiconductor (impurity) is indicated using "p-type" or "n-type," but "p-type" may also be referred to as the "first conductivity type" and "n-type" as the "second conductivity type." "n-type" may also be referred to as the "first conductivity type" and "p-type" as the "second conductivity type."

[0022] "P-type" is a conductivity type resulting from a trivalent element, and "n-type" is a conductivity type resulting from a pentavalent element. Trivalent elements are at least one of boron, aluminum, gallium, and indium. Pentavalent elements are at least one of nitrogen, phosphorus, arsenic, antimony, and bismuth.

[0023] Fig. 1 is a plan view showing a semiconductor device 1X according to the basic form. Fig. 2 is a cross-sectional view taken along line II-II shown in Fig. 1. Fig. 3A is a graph (simulation) showing a first example of the concentration gradient of the buffer layer 8. In Fig. 3A, the vertical axis represents the impurity concentration, and the horizontal axis represents the depth.

[0024] 1 and 2, semiconductor device 1X includes chip 2 formed in a hexahedral shape (specifically, a rectangular parallelepiped shape). In this embodiment, chip 2 includes a single crystal of a wide bandgap semiconductor. In other words, semiconductor device 1X is a "wide bandgap semiconductor device." Chip 2 may also be referred to as a "semiconductor chip," a "wide bandgap semiconductor chip," or the like.

[0025] A wide bandgap semiconductor is a semiconductor having a bandgap that exceeds the bandgap of Si (silicon). Examples of wide bandgap semiconductors include GaN (gallium nitride), SiC (silicon carbide), and C (diamond). In this embodiment, the chip 2 is a "SiC chip" that includes a hexagonal SiC single crystal as an example of a wide bandgap semiconductor. In other words, the semiconductor device 1X is a "SiC semiconductor device."

[0026] Hexagonal SiC single crystal has multiple polytypes, including 2H (Hexagonal)-SiC single crystal, 4H-SiC single crystal, 6H-SiC single crystal, etc. In this embodiment, an example is shown in which the chip 2 includes a 4H-SiC single crystal, but the chip 2 may also include other polytypes. Of course, the chip 2 may also include a cubic crystal or a polycrystal. For example, the chip 2 may include a 3C (Cubic)-SiC single crystal or a 3C-SiC polycrystal.

[0027] The chip 2 has a first main surface 3 on one side, a second main surface 4 on the other side, and first to fourth side surfaces 5A to 5D connected to the first main surface 3 and the second main surface 4. The first main surface 3 and the second main surface 4 are formed in a quadrangular shape in a plan view seen from the vertical direction Z (hereinafter simply referred to as "plan view"). The vertical direction Z is also the thickness direction of the chip 2.

[0028] The first main surface 3 and the second main surface 4 are formed by the c-plane of the SiC single crystal. The first main surface 3 may be formed by the silicon surface ((0001) surface) of the SiC single crystal, and the second main surface 4 may be formed by the carbon surface ((000-1) surface) of the SiC single crystal.

[0029] The first side surface 5A extends in the first direction X. The second side surface 5B is connected to the first side surface 5A and extends in a second direction Y that intersects (specifically, is perpendicular to) the first direction X. The third side surface 5C is connected to the second side surface 5B and extends in the first direction X. The fourth side surface 5D is connected to the first side surface 5A and the third side surface 5C and extends in the second direction Y.

[0030] In this embodiment, the first direction X is the m-axis direction ([1-100] direction) of the SiC single crystal, and the second direction Y is the a-axis direction ([11-20] direction) of the SiC single crystal. The first direction X may be the a-axis direction of the SiC single crystal, and the second direction Y may be the m-axis direction of the SiC single crystal. Hereinafter, the direction extending along the first main surface 3 may be referred to as the "horizontal direction." The horizontal direction is also the XY plane (horizontal plane) formed by the first direction X and the second direction Y, and is perpendicular to the vertical direction Z.

[0031] The chip 2 (first main surface 3 and second main surface 4) has an off angle θ inclined at a predetermined angle in a predetermined off direction with respect to the c-plane of the SiC single crystal. In other words, the c-axis ((0001) axis) of the SiC single crystal is inclined by the off angle from a vertical line along the vertical direction Z toward the off direction. Furthermore, the c-plane of the SiC single crystal is inclined by the off angle θ with respect to the horizontal plane.

[0032] The off-direction is preferably the a-axis direction of the SiC single crystal (the second direction Y in this embodiment). The off-angle θ may be greater than 0° and less than or equal to 10°. The off-angle θ may have a value belonging to at least one of the following ranges: greater than 0° and less than or equal to 1°, 1° to 2.5°, 2.5° to 5°, 5° to 7.5°, and 7.5° to 10°.

[0033] The off angle θ is preferably 5° or less. The off angle θ is particularly preferably 2° or more and 4.5° or less. The off angle θ is typically set in the range of 4°±0.1°. This specification does not exclude a configuration in which the off angle θ is 0° (i.e., a configuration in which the first main surface 3 is a just plane with respect to the c-plane).

[0034] The chip 2 includes an n-type semiconductor substrate 6 (substrate). The semiconductor substrate 6 may also be referred to as a "first semiconductor region," etc. The semiconductor substrate 6 forms a second main surface 4 of the chip 2 and a portion of the first to fourth side surfaces 5A to 5D of the chip 2. The semiconductor substrate 6 includes a single crystal of a wide bandgap semiconductor.

[0035] In this embodiment, the semiconductor substrate 6 is a "SiC substrate" including a hexagonal SiC single crystal. In this embodiment, the semiconductor substrate 6 includes a 4H-SiC single crystal and has the off-orientation and off-angle θ described above. Of course, the semiconductor substrate 6 may include other polytypes. For example, the semiconductor substrate 6 may include a 3C-SiC polycrystal. In this case, the second main surface 4 is formed by a crystal plane of the 3C-SiC polycrystal.

[0036] The semiconductor substrate 6 has basal plane dislocation (BPD) defects (see the dashed line in FIG. 4). The basal plane dislocation defects are dislocations that exist on the c-plane, which is the basal plane of the SiC single crystal. When the semiconductor substrate 6 has an off-orientation and an off-angle θ, the basal plane dislocation defects extend in a state inclined by the off-orientation angle θ toward the off-orientation. The basal plane dislocation defects are located within the semiconductor substrate 6 at a distance of 1 cm －２ More than 10000cm －２ It may have the following densities:

[0037] The semiconductor substrate 6 has a first thickness T1. The first thickness T1 may be greater than 0 μm and less than 500 μm. The first thickness T1 may have a value belonging to at least one of the following ranges: greater than 0 μm and less than 50 μm, 50 μm to 100 μm, 100 μm to 150 μm, 150 μm to 200 μm, 200 μm to 250 μm, 250 μm to 300 μm, 300 μm to 350 μm, 350 μm to 400 μm, 400 μm to 450 μm, and 450 μm to 500 μm.

[0038] 3A, the semiconductor substrate 6 has a first concentration C1 of n-type impurities. The semiconductor substrate 6 may have the first concentration C1 that is uniform in the thickness direction. The first concentration C1 is 1×10 １７cm －３ 1x10 or more ２１ cm －３ It may be the following:

[0039] The first concentration C1 is 1×10 １７ cm －３ 5x10 or more １７ cm －３ Below, 5 x 10 １７ cm －３ 1x10 or more １８ cm －３ Below, 1 x 10 １８ cm －３ 5x10 or more １８ cm －３ Below, 5 x 10 １８ cm －３ 1x10 or more １９ cm －３ Below, 1 x 10 １９ cm －３ 5x10 or more １９ cm －３ Below, 5 x 10 １９ cm －３ 1x10 or more ２０ cm －３ Below, 1 x 10 ２０ cm －３ 5x10 or more ２０ cm －３ Below, and 5 x 10 ２０ cm －３ 1x10 or more ２１ cm －３ It may have a value that falls within at least one of the following ranges:

[0040] The first concentration C1 may be adjusted by a single pentavalent element or multiple pentavalent elements. The first concentration C1 is preferably adjusted by a single pentavalent element. The first concentration C1 may be adjusted by nitrogen as a pentavalent element.

[0041] The chip 2 includes an n-type semiconductor layer 7 stacked on a semiconductor substrate 6. The semiconductor layer 7 may be referred to as a "second semiconductor region" or the like. The semiconductor layer 7 forms part of the first main surface 3 of the chip 2 and the first to fourth side surfaces 5A to 5D of the chip 2. The semiconductor layer 7 includes a single crystal of a wide bandgap semiconductor.

[0042] In this embodiment, the semiconductor layer 7 is a "SiC semiconductor layer" containing hexagonal SiC single crystal. In this embodiment, the semiconductor layer 7 is made of an epitaxial layer (SiC epitaxial layer). In this embodiment, the semiconductor layer 7 contains 4H—SiC single crystal and has the off direction and off angle θ described above. Of course, the semiconductor layer 7 may contain other polytypes.

[0043] The semiconductor layer 7 has a second thickness T2 in the stacking direction that is less than the first thickness T1 of the semiconductor substrate 6. The second thickness T2 may be greater than 0 μm and less than 50 μm. The second thickness T2 may have a value that falls within at least one of the following ranges: greater than 0 μm and less than 5 μm, 5 μm to 10 μm, 10 μm to 15 μm, 15 μm to 20 μm, 20 μm to 25 μm, 25 μm to 30 μm, 30 μm to 35 μm, 35 μm to 40 μm, 40 μm to 45 μm, and 45 μm to 50 μm.

[0044] 3A , the semiconductor layer 7 has a second concentration C2 of n-type impurities that is less than the first concentration C1 of the semiconductor substrate 6. The semiconductor layer 7 may have a uniform second concentration C2 in the thickness direction. The semiconductor layer 7 may have a second concentration C2 that gradually increases from the semiconductor substrate 6 toward the first main surface 3. The second concentration C2 is 1×10 １５ cm －３ 1x10 or more １９ cm －３ It may be the following:

[0045] The semiconductor layer 7 is 1×10 １５ cm －３ 5x10 or more １５ cm －３ Below, 5 x 10 １５ cm －３ 1x10 or more １６ cm －３ Below, 1 x 10 １６ cm －３ 5x10 or more １６ cm －３ Below, 5 x 10 １６ cm －３ 1x10 or more １７ cm －３ Below, 1 x 10１７ cm －３ 5x10 or more １７ cm －３ Below, 5 x 10 １７ cm －３ 1x10 or more １８ cm －３ Below, and 1 x 10 １８ cm －３ 5x10 or more １９ cm －３ It may have a value that falls within at least one of the following ranges:

[0046] The second concentration C2 may be adjusted by a single pentavalent element or multiple pentavalent elements. The second concentration C2 is preferably adjusted by a single pentavalent element. The second concentration C2 may be adjusted by nitrogen as a pentavalent element.

[0047] The chip 2 includes an n-type buffer layer 8 interposed between the semiconductor substrate 6 and the semiconductor layer 7. The buffer layer 8 may be referred to as a "third semiconductor region" or the like. The buffer layer 8 forms part of the first to fourth side surfaces 5A to 5D of the chip 2.

[0048] The buffer layer 8 includes a single crystal of a wide bandgap semiconductor. In this embodiment, the buffer layer 8 is a "SiC buffer layer" including a hexagonal SiC single crystal. In this embodiment, the buffer layer 8 is made of an epitaxial layer (SiC epitaxial layer) stacked on the semiconductor substrate 6. In other words, the semiconductor layer 7 is stacked on the buffer layer 8.

[0049] In this embodiment, the buffer layer 8 includes a 4H—SiC single crystal and has the off-orientation and off-angle θ described above. Of course, the buffer layer 8 may include other polytypes. The buffer layer 8 has a third thickness T3 in the stacking direction that is less than the first thickness T1 of the semiconductor substrate 6. The third thickness T3 is less than the second thickness T2 of the semiconductor layer 7.

[0050] The third thickness T3 may be greater than 0 μm and not greater than 10 μm. The third thickness T3 may have a value belonging to at least one of the ranges of greater than 0 μm and less than or equal to 0.5 μm, 0.5 μm or more and less than or equal to 1 μm, 1 μm or more and less than or equal to 1.5 μm, 1.5 μm or more and less than or equal to 2 μm, 2 μm or more and less than or equal to 2.5 μm, 2.5 μm or more and less than or equal to 3 μm, 3 μm or more and less than or equal to 3.5 μm, 3.5 μm or more and less than or equal to 4 μm, 4 μm or more and less than or equal to 4.5 μm, 4.5 μm or more and less than or equal to 5 μm, 5 μm or more and less than or equal to 5.5 μm, 5.5 μm or more and less than or equal to 6 μm, 6 μm or more and less than or equal to 6.5 μm, 6.5 μm or more and less than or equal to 7 μm, 7 μm or more and less than or equal to 7.5 μm, 7.5 μm or more and less than or equal to 8 μm, 8 μm or more and less than or equal to 8.5 μm, 8.5 μm or more and less than or equal to 9 μm, 9 μm or more and less than or equal to 9.5 μm, and 9.5 μm or more and less than or equal to 10 μm.

[0051] 2, the buffer layer 8 includes a low concentration portion 8a, a high concentration portion 8b, and a transition portion 8c. The low concentration portion 8a is formed in a region on the semiconductor substrate 6 side. The low concentration portion 8a forms the lower end of the buffer layer 8 and extends horizontally along the semiconductor substrate 6. The low concentration portion 8a forms part of the first to fourth side surfaces 5A to 5D.

[0052] The low-concentration portion 8 a may have a thickness of greater than 0 μm and less than or equal to 1 μm. The thickness of the low-concentration portion 8 a may have a value belonging to at least one of the following ranges: greater than 0 μm and less than or equal to 0.2 μm, 0.2 μm to 0.4 μm, 0.4 μm to 0.6 μm, 0.6 μm to 0.8 μm, and 0.8 μm to 1 μm.

[0053] 3A , the low-concentration portion 8a has a relatively low third concentration C3 of n-type impurities and is a portion that forms a minimum value of the impurity concentration of the buffer layer 8. The third concentration C3 is less than the first concentration C1 of the semiconductor substrate 6. In this embodiment, the third concentration C3 is equal to or less than the second concentration C2 of the semiconductor layer 7.

[0054] Specifically, the third concentration C3 is less than the second concentration C2. The fourth concentration C4 may be approximately equal to the second concentration C2. The third concentration C3 may be equal to or greater than the second concentration C2. In this case, the third concentration C3 may be higher than the second concentration C2.

[0055] The low concentration portion 8a forms a concentration gradient that drops sharply from the first concentration C1 of the semiconductor substrate 6. In other words, the high concentration portion 8b has an n-type impurity concentration that is lower than the n-type impurity concentration at the upper end of the semiconductor substrate 6, and forms a concentration gradient that drops sharply from the n-type impurity concentration at the upper end of the semiconductor substrate 6.

[0056] The third concentration C3 is 1×10 １４ cm －３ 1x10 or more １８ cm －３ The third concentration C3 may be 1×10 １４ cm －３ 5x10 or more １４ cm －３ Below, 5 x 10 １４ cm －３ 1x10 or more １５ cm －３ Below, 1 x 10 １５ cm －３ 5x10 or more １５ cm －３ Below, 5 x 10 １５ cm －３ 1x10 or more １６ cm －３ Below, 1 x 10 １６ cm －３ 5x10 or more １６ cm －３ Below, 5 x 10 １６ cm －３ 1x10 or more １７ cm －３ Below, 1 x 10 １７ cm －３ 5x10 or more １７ cm －３ Below, and 5 x 10 １７ cm －３ 1x10 or more １８ cm －３ It may have a value that falls within at least one of the following ranges:

[0057] The third concentration C3 may be adjusted by a single pentavalent element or multiple pentavalent elements. The third concentration C3 is preferably adjusted by a single pentavalent element. The third concentration C3 may be adjusted by nitrogen as a pentavalent element.

[0058] The high concentration portion 8b is formed in a region on the semiconductor layer 7 side. The high concentration portion 8b forms the upper end of the buffer layer 8 and extends horizontally along the semiconductor layer 7 (low concentration portion 8a). The high concentration portion 8b forms part of the first to fourth side surfaces 5A to 5D.

[0059] The high-concentration portion 8b may have a thickness of greater than 0 μm and less than or equal to 1 μm. The thickness of the high-concentration portion 8b may have a value belonging to at least one of the ranges of greater than 0 μm and less than or equal to 0.2 μm, 0.2 μm to 0.4 μm, 0.4 μm to 0.6 μm, 0.6 μm to 0.8 μm, and 0.8 μm to 1 μm.

[0060] 3A , the high-concentration portion 8b has a relatively high fourth concentration C4 of n-type impurities and is a portion where the impurity concentration of the buffer layer 8 has a maximum value. The fourth concentration C4 is higher than the third concentration C3 of the low-concentration portion 8a. The fourth concentration C4 is higher than the second concentration C2 of the semiconductor layer 7.

[0061] In this embodiment, the fourth concentration C4 is equal to or greater than the first concentration C1 of the semiconductor substrate 6. Specifically, the fourth concentration C4 is higher than the first concentration C1. The fourth concentration C4 may be approximately equal to the first concentration C1. The fourth concentration C4 may be equal to or less than the first concentration C1. In this case, the fourth concentration C4 may be less than the first concentration C1.

[0062] The high-concentration portion 8b forms a concentration gradient that drops sharply toward the second concentration C2 of the semiconductor layer 7. That is, the high-concentration portion 8b has an n-type impurity concentration that is higher than the n-type impurity concentration at the lower end of the semiconductor layer 7, and forms a concentration gradient that drops sharply toward the n-type impurity concentration at the lower end of the semiconductor layer 7.

[0063] The fourth concentration C4 is 1×10 １６ cm －３ 1x10 or more １９ cm －３ The fourth concentration C4 may be 1×10 １６ cm －３ 5x10 or more １６ cm －３ Below, 5 x 10 １６ cm －３ 1x10 or more１７ cm －３ Below, 1 x 10 １７ cm －３ 5x10 or more １７ cm －３ Below, 5 x 10 １７ cm －３ 1x10 or more １８ cm －３ Below, 1 x 10 １８ cm －３ 5x10 or more １８ cm －３ Below, and 5 x 10 １８ cm －３ 1x10 or more １９ cm －３ It may have a value that falls within at least one of the following ranges:

[0064] The fourth concentration C4 may be adjusted by a single pentavalent element or multiple pentavalent elements. The fourth concentration C4 is preferably adjusted by a single pentavalent element. The fourth concentration C4 may be adjusted by nitrogen as a pentavalent element.

[0065] The transition portion 8c is formed in a region between the low concentration portion 8a and the high concentration portion 8b, and extends horizontally along both the low concentration portion 8a and the high concentration portion 8b, forming a part of the first to fourth side surfaces 5A to 5D.

[0066] In this embodiment, the transition portion 8c occupies a thickness range of 50% or more and less than 100% of the buffer layer 8. The occupation ratio of the transition portion 8c may have a value belonging to at least one of the ranges of 50% or more and 55% or less, 55% or more and 60% or less, 60% or more and 65% or less, 65% or more and 70% or less, 70% or more and 75% or less, 75% or more and 80% or less, 80% or more and 85% or less, 85% or more and 90% or less, 90% or more and 95% or less, and 95% or more and less than 100%.

[0067] 3A, the transition portion 8c has a concentration gradient in which the concentration gradually increases from the third concentration C3 to the fourth concentration C4. The concentration in the transition portion 8c increases monotonically from the third concentration C3 to the fourth concentration C4. In this configuration, the concentration in the transition portion 8c increases at a substantially constant rate.

[0068] The buffer layer 8 does not necessarily have to have the first concentration gradient example shown in Figure 3A. The buffer layer 8 may have any one of the second to thirteenth concentration gradient examples instead of the first concentration gradient example. Figures 3B to 3M are graphs (simulations) showing the second to thirteenth concentration gradient examples of the buffer layer 8. In Figures 3B to 3M, the vertical axis represents the impurity concentration, and the horizontal axis represents the depth.

[0069] Hereinafter, the first concentration C1 of the semiconductor substrate 6, the second concentration C2 of the semiconductor layer 7, the third concentration C3 of the low concentration portion 8a, and the fourth concentration C4 of the high concentration portion 8b will be simply referred to as "first concentration C1," "second concentration C2," "third concentration C3," and "fourth concentration C4."

[0070] With reference to Figure 3B (second concentration gradient example), the third concentration C3 may be greater than the second concentration C2, and the fourth concentration C4 may be greater than the first concentration C1. With reference to Figure 3C (third concentration gradient example), the third concentration C3 may be less than the second concentration C2, and the fourth concentration C4 may be less than the first concentration C1. With reference to Figure 3D (fourth concentration gradient example), the third concentration C3 may be greater than the second concentration C2, and the fourth concentration C4 may be less than the first concentration C1.

[0071] Referring to Figure 3E (Fifth Concentration Gradient Example), in this example, the third concentration C3 is less than the second concentration C2, and the fourth concentration C4 is greater than the first concentration C1. The third concentration C3 may be greater than the second concentration C2, and the fourth concentration C4 may be greater than the first concentration C1 (see Figure 3B). The third concentration C3 may be less than the second concentration C2, and the fourth concentration C4 may be less than the first concentration C1 (see Figure 3C). The third concentration C3 may be greater than the second concentration C2, and the fourth concentration C4 may be less than the first concentration C1 (see Figure 3D).

[0072] The low-concentration portion 8a may have a third concentration C3 within a certain thickness range. The ratio of the thickness of the low-concentration portion 8a to the third thickness T3 may be greater than 0 and less than or equal to 0.8. The thickness ratio may have a value belonging to at least one of the following ranges: greater than 0 and less than or equal to 0.2, 0.2 to 0.4, 0.4 to 0.6, and 0.6 to 0.8.

[0073] The thickness of the low-concentration portion 8 a may be greater than 0 μm and less than or equal to 5 μm. The thickness of the low-concentration portion 8 a may have a value belonging to at least one of the following ranges: greater than 0 μm and less than or equal to 0.5 μm, 0.5 μm to 1 μm, 1 μm to 1.5 μm, 1.5 μm to 2 μm, 2 μm to 2.5 μm, 2.5 μm to 3 μm, 3 μm to 3.5 μm, 3.5 μm to 4 μm, 4 μm to 4.5 μm, and 4.5 μm to 5 μm.

[0074] The thickness of the transition portion 8c may be greater than 0 μm and less than or equal to 5 μm. The thickness of the transition portion 8c may have a value belonging to at least one of the following ranges: greater than 0 μm and less than or equal to 0.5 μm, 0.5 μm to 1 μm, 1 μm to 1.5 μm, 1.5 μm to 2 μm, 2 μm to 2.5 μm, 2.5 μm to 3 μm, 3 μm to 3.5 μm, 3.5 μm to 4 μm, 4 μm to 4.5 μm, and 4.5 μm to 5 μm.

[0075] Referring to Figure 3F (sixth concentration gradient example), in this example, the third concentration C3 is less than the second concentration C2, and the fourth concentration C4 is greater than the first concentration C1. The third concentration C3 may be greater than the second concentration C2, and the fourth concentration C4 may be greater than the first concentration C1 (see Figure 3B). The third concentration C3 may be less than the second concentration C2, and the fourth concentration C4 may be less than the first concentration C1 (see Figure 3C). The third concentration C3 may be greater than the second concentration C2, and the fourth concentration C4 may be less than the first concentration C1 (see Figure 3D).

[0076] The high-concentration portion 8b may have a fourth concentration C4 within a certain thickness range. The ratio of the thickness of the high-concentration portion 8b to the third thickness T3 may be greater than 0 and less than or equal to 0.8. The thickness ratio may have a value belonging to at least one of the following ranges: greater than 0 and less than or equal to 0.2, 0.2 to 0.4, 0.4 to 0.6, and 0.6 to 0.8.

[0077] The thickness of the high-concentration portion 8b may be greater than 0 μm and less than 5 μm. The thickness of the high-concentration portion 8b may have a value belonging to at least one of the following ranges: greater than 0 μm and less than 0.5 μm, 0.5 μm to 1 μm, 1 μm to 1.5 μm, 1.5 μm to 2 μm, 2 μm to 2.5 μm, 2.5 μm to 3 μm, 3 μm to 3.5 μm, 3.5 μm to 4 μm, 4 μm to 4.5 μm, and 4.5 μm to 5 μm.

[0078] The thickness of the transition portion 8c may be greater than 0 μm and less than or equal to 5 μm. The thickness of the transition portion 8c may have a value belonging to at least one of the following ranges: greater than 0 μm and less than or equal to 0.5 μm, 0.5 μm to 1 μm, 1 μm to 1.5 μm, 1.5 μm to 2 μm, 2 μm to 2.5 μm, 2.5 μm to 3 μm, 3 μm to 3.5 μm, 3.5 μm to 4 μm, 4 μm to 4.5 μm, and 4.5 μm to 5 μm.

[0079] 3G (seventh concentration gradient example), in this example, the third concentration C3 is less than the second concentration C2, and the fourth concentration C4 is greater than the first concentration C1. The third concentration C3 may be greater than the second concentration C2, and the fourth concentration C4 may be greater than the first concentration C1 (see FIG. 3B). The third concentration C3 may be less than the second concentration C2, and the fourth concentration C4 may be less than the first concentration C1 (see FIG. 3C). The third concentration C3 may be greater than the second concentration C2, and the fourth concentration C4 may be less than the first concentration C1 (see FIG. 3D).

[0080] The low-concentration portion 8a may have a third concentration C3 within a certain thickness range. The ratio of the thickness of the low-concentration portion 8a to the third thickness T3 may be greater than 0 and less than or equal to 0.6. The thickness ratio may have a value belonging to at least one of the ranges of greater than 0 and less than or equal to 0.2, 0.2 to 0.4, and 0.4 to 0.6.

[0081] The thickness of the low-concentration portion 8 a may be greater than 0 μm and less than or equal to 5 μm. The thickness of the low-concentration portion 8 a may have a value belonging to at least one of the following ranges: greater than 0 μm and less than or equal to 0.5 μm, 0.5 μm to 1 μm, 1 μm to 1.5 μm, 1.5 μm to 2 μm, 2 μm to 2.5 μm, 2.5 μm to 3 μm, 3 μm to 3.5 μm, 3.5 μm to 4 μm, 4 μm to 4.5 μm, and 4.5 μm to 5 μm.

[0082] The high-concentration portion 8b may have a fourth concentration C4 within a certain thickness range. The thickness of the high-concentration portion 8b may be less than the thickness of the low-concentration portion 8a. The thickness of the high-concentration portion 8b may be approximately equal to the thickness of the low-concentration portion 8a. The thickness of the high-concentration portion 8b may be greater than the thickness of the low-concentration portion 8a.

[0083] The ratio of the thickness of the high-concentration portion 8b to the third thickness T3 may be greater than 0 and less than or equal to 0.6. The thickness ratio may have a value belonging to at least one of the ranges of greater than 0 and less than or equal to 0.2, 0.2 or more and less than or equal to 0.4, and 0.4 or more and less than or equal to 0.6.

[0084] The thickness of the high-concentration portion 8b may be greater than 0 μm and less than 5 μm. The thickness of the high-concentration portion 8b may have a value belonging to at least one of the following ranges: greater than 0 μm and less than 0.5 μm, 0.5 μm to 1 μm, 1 μm to 1.5 μm, 1.5 μm to 2 μm, 2 μm to 2.5 μm, 2.5 μm to 3 μm, 3 μm to 3.5 μm, 3.5 μm to 4 μm, 4 μm to 4.5 μm, and 4.5 μm to 5 μm.

[0085] The thickness of the transition portion 8c may be greater than 0 μm and less than or equal to 5 μm. The thickness of the transition portion 8c may have a value belonging to at least one of the following ranges: greater than 0 μm and less than or equal to 0.5 μm, 0.5 μm to 1 μm, 1 μm to 1.5 μm, 1.5 μm to 2 μm, 2 μm to 2.5 μm, 2.5 μm to 3 μm, 3 μm to 3.5 μm, 3.5 μm to 4 μm, 4 μm to 4.5 μm, and 4.5 μm to 5 μm.

[0086] Referring to Figure 3H (Eighth Concentration Gradient Example), in this example, the third concentration C3 is less than the second concentration C2, and the fourth concentration C4 is greater than the first concentration C1. The third concentration C3 may be greater than the second concentration C2, and the fourth concentration C4 may be greater than the first concentration C1 (see Figure 3B). The third concentration C3 may be less than the second concentration C2, and the fourth concentration C4 may be less than the first concentration C1 (see Figure 3C). The third concentration C3 may be greater than the second concentration C2, and the fourth concentration C4 may be less than the first concentration C1 (see Figure 3D).

[0087] The transition portion 8c may have a concentration gradient in which the rate of increase of the impurity concentration changes in the thickness range between the low-concentration portion 8a and the high-concentration portion 8b. The transition portion 8c may have a gradual portion 8c1 and a steep portion 8c2. The gradual portion 8c1 is a region in which the impurity concentration monotonically increases at a relatively gradual first rate of increase from the low-concentration portion 8a toward the stacking direction. The steep portion 8c2 is a region in which the impurity concentration monotonically increases at a second rate of increase that is higher than the first rate of increase from the gradual portion 8c1 toward the high-concentration portion 8b.

[0088] The ratio of the thickness of the gentle portion 8c1 to the third thickness T3 may be greater than 0 and less than or equal to 0.8. The thickness ratio may have a value belonging to at least one of the ranges of greater than 0 and less than or equal to 0.2, 0.2 to 0.4, 0.4 to 0.6, and 0.6 to 0.8.

[0089] The thickness of the gentle portion 8c1 may be greater than 0 μm and less than 5 μm. The thickness of the gentle portion 8c1 may have a value belonging to at least one of the following ranges: greater than 0 μm and less than 0.5 μm, 0.5 μm to 1 μm, 1 μm to 1.5 μm, 1.5 μm to 2 μm, 2 μm to 2.5 μm, 2.5 μm to 3 μm, 3 μm to 3.5 μm, 3.5 μm to 4 μm, 4 μm to 4.5 μm, and 4.5 μm to 5 μm.

[0090] The ratio of the thickness of the steep portion 8c2 to the third thickness T3 may be greater than 0 and less than or equal to 0.8. The thickness ratio may have a value belonging to at least one of the ranges of greater than 0 and less than or equal to 0.2, 0.2 to 0.4, 0.4 to 0.6, and 0.6 to 0.8.

[0091] The thickness of steep portion 8c2 may be greater than 0 μm and less than 5 μm. The thickness of steep portion 8c2 may have a value belonging to at least one of the following ranges: greater than 0 μm and less than 0.5 μm, 0.5 μm to 1 μm, 1 μm to 1.5 μm, 1.5 μm to 2 μm, 2 μm to 2.5 μm, 2.5 μm to 3 μm, 3 μm to 3.5 μm, 3.5 μm to 4 μm, 4 μm to 4.5 μm, and 4.5 μm to 5 μm.

[0092] Referring to Figure 3I (ninth concentration gradient example), in this example, the third concentration C3 is less than the second concentration C2, and the fourth concentration C4 is greater than the first concentration C1. The third concentration C3 may be greater than the second concentration C2, and the fourth concentration C4 may be greater than the first concentration C1 (see Figure 3B). The third concentration C3 may be less than the second concentration C2, and the fourth concentration C4 may be less than the first concentration C1 (see Figure 3C). The third concentration C3 may be greater than the second concentration C2, and the fourth concentration C4 may be less than the first concentration C1 (see Figure 3D).

[0093] The transition portion 8c may have a concentration gradient in which the rate of increase of the impurity concentration changes in the thickness range between the low-concentration portion 8a and the high-concentration portion 8b. The transition portion 8c may have a steep portion 8c3 and a gradual portion 8c4. The steep portion 8c3 is a region in which the impurity concentration monotonically increases at a relatively steep first concentration increase rate from the low-concentration portion 8a toward the stacking direction. The gradual portion 8c4 is a region in which the impurity concentration monotonically increases at a second concentration increase rate that is lower than the first concentration increase rate from the steep portion 8c3 toward the high-concentration portion 8b.

[0094] The ratio of the thickness of the steep portion 8c3 to the third thickness T3 may be greater than 0 and less than or equal to 0.8. The thickness ratio may have a value belonging to at least one of the ranges of greater than 0 and less than or equal to 0.2, 0.2 to 0.4, 0.4 to 0.6, and 0.6 to 0.8.

[0095] The thickness of steep portion 8c3 may be greater than 0 μm and less than 5 μm. The thickness of steep portion 8c3 may have a value belonging to at least one of the following ranges: greater than 0 μm and less than 0.5 μm, 0.5 μm to 1 μm, 1 μm to 1.5 μm, 1.5 μm to 2 μm, 2 μm to 2.5 μm, 2.5 μm to 3 μm, 3 μm to 3.5 μm, 3.5 μm to 4 μm, 4 μm to 4.5 μm, and 4.5 μm to 5 μm.

[0096] Referring to Figure 3J (a tenth concentration gradient example), in this example, the third concentration C3 is less than the second concentration C2, and the fourth concentration C4 is greater than the first concentration C1. The third concentration C3 may be greater than the second concentration C2, and the fourth concentration C4 may be greater than the first concentration C1 (see Figure 3B). The third concentration C3 may be less than the second concentration C2, and the fourth concentration C4 may be less than the first concentration C1 (see Figure 3C). The third concentration C3 may be greater than the second concentration C2, and the fourth concentration C4 may be less than the first concentration C1 (see Figure 3D).

[0097] The transition portion 8c may have a concentration gradient in which the rate of increase of the impurity concentration changes in the thickness range between the low concentration portion 8a and the high concentration portion 8b. The transition portion 8c may have a first gradual portion 8c5, a steep portion 8c6, and a second gradual portion 8c7.

[0098] The first gradual portion 8c5 is a region where the impurity concentration monotonically increases at a relatively gradual first concentration increase rate from the low-concentration portion 8a toward the stacking direction. The steep portion 8c6 is a region where the impurity concentration monotonically increases at a second concentration increase rate that is higher than the first concentration increase rate from the low-concentration portion 8a toward the stacking direction. The second gradual portion 8c7 is a region where the impurity concentration monotonically increases at a third concentration increase rate that is lower than the second concentration increase rate from the steep portion 8c6 toward the high-concentration portion 8b.

[0099] The ratio of the thickness of the first slow portion 8c5 to the third thickness T3 may be greater than 0 and less than or equal to 0.8. The thickness ratio may have a value belonging to at least one of the ranges of greater than 0 and less than or equal to 0.2, 0.2 to 0.4, 0.4 to 0.6, and 0.6 to 0.8.

[0100] The thickness of first gentle portion 8c5 may be greater than 0 μm and less than 5 μm. The thickness of first gentle portion 8c5 may have a value belonging to at least one of the following ranges: greater than 0 μm and less than 0.5 μm, 0.5 μm to 1 μm, 1 μm to 1.5 μm, 1.5 μm to 2 μm, 2 μm to 2.5 μm, 2.5 μm to 3 μm, 3 μm to 3.5 μm, 3.5 μm to 4 μm, 4 μm to 4.5 μm, and 4.5 μm to 5 μm.

[0101] The ratio of the thickness of the steep portion 8c6 to the third thickness T3 may be greater than 0 and less than or equal to 0.8. The thickness ratio may have a value belonging to at least one of the ranges of greater than 0 and less than or equal to 0.2, 0.2 or more and less than or equal to 0.4, 0.4 or more and less than or equal to 0.6, and 0.6 or more and less than or equal to 0.8.

[0102] The thickness of the steep portion 8c6 may be greater than 0 μm and less than 5 μm. The thickness of the first gentle portion 8c5 may be greater than 0 μm and less than 0.5 μm, greater than 0.5 μm and less than 1 μm, greater than 1 μm and less than 1.5 μm, greater than 1.5 μm and less than 2 μm, greater than 2 μm and less than 2.5 μm, greater than 2.5 μm and less than 3 μm, greater than 3 μm and less than 3.5 μm, greater than 3.5 μm and less than 4 μm, greater than 4 μm and less than 4.5 μm, and greater than 4.5 μm and less than 5 μm.

[0103] The ratio of the thickness of the second slow portion 8c7 to the third thickness T3 may be greater than 0 and less than or equal to 0.6. The thickness ratio may have a value belonging to at least one of the ranges of greater than 0 and less than or equal to 0.2, 0.2 to 0.4, 0.4 to 0.6, and 0.6 to 0.8.

[0104] The thickness of second gentle portion 8c7 may be greater than 0 μm and less than 5 μm. The thickness of second gentle portion 8c7 may have a value belonging to at least one of the following ranges: greater than 0 μm and less than 0.5 μm, 0.5 μm to 1 μm, 1 μm to 1.5 μm, 1.5 μm to 2 μm, 2 μm to 2.5 μm, 2.5 μm to 3 μm, 3 μm to 3.5 μm, 3.5 μm to 4 μm, 4 μm to 4.5 μm, and 4.5 μm to 5 μm.

[0105] Referring to Figure 3K (an eleventh concentration gradient example), in this example, the third concentration C3 is less than the second concentration C2, and the fourth concentration C4 is greater than the first concentration C1. The third concentration C3 may be greater than the second concentration C2, and the fourth concentration C4 may be greater than the first concentration C1 (see Figure 3B). The third concentration C3 may be less than the second concentration C2, and the fourth concentration C4 may be less than the first concentration C1 (see Figure 3C). The third concentration C3 may be greater than the second concentration C2, and the fourth concentration C4 may be less than the first concentration C1 (see Figure 3D).

[0106] The transition portion 8c has a concentration gradient in which the rate of increase in concentration changes continuously in the thickness range between the low-concentration portion 8a and the high-concentration portion 8b. The rate of increase in concentration in the transition portion 8c may monotonically increase from the low-concentration portion 8a to the high-concentration portion 8b.

[0107] Referring to Figure 3L (a twelfth concentration gradient example), in this example, the third concentration C3 is less than the second concentration C2, and the fourth concentration C4 is greater than the first concentration C1. The third concentration C3 may be greater than the second concentration C2, and the fourth concentration C4 may be greater than the first concentration C1 (see Figure 3B). The third concentration C3 may be less than the second concentration C2, and the fourth concentration C4 may be less than the first concentration C1 (see Figure 3C). The third concentration C3 may be greater than the second concentration C2, and the fourth concentration C4 may be less than the first concentration C1 (see Figure 3D).

[0108] The transition portion 8c has a concentration gradient in which the rate of increase in concentration changes continuously in the thickness range between the low concentration portion 8a and the high concentration portion 8b. The rate of increase in concentration in the transition portion 8c may gradually decrease from the low concentration portion 8a to the high concentration portion 8b.

[0109] Referring to Figure 3M (a thirteenth concentration gradient example), in this example, the third concentration C3 is less than the second concentration C2, and the fourth concentration C4 is greater than the first concentration C1. The third concentration C3 may be greater than the second concentration C2, and the fourth concentration C4 may be greater than the first concentration C1 (see Figure 3B). The third concentration C3 may be less than the second concentration C2, and the fourth concentration C4 may be less than the first concentration C1 (see Figure 3C). The third concentration C3 may be greater than the second concentration C2, and the fourth concentration C4 may be less than the first concentration C1 (see Figure 3D).

[0110] The low-concentration portion 8a may have a third concentration C3 within a certain thickness range. The ratio of the thickness of the low-concentration portion 8a to the third thickness T3 may be greater than 0 and less than or equal to 0.8. The thickness ratio may have a value belonging to at least one of the following ranges: greater than 0 and less than or equal to 0.2, 0.2 to 0.4, 0.4 to 0.6, and 0.6 to 0.8.

[0111] The thickness of the low-concentration portion 8 a may be greater than 0 μm and less than or equal to 5 μm. The thickness of the low-concentration portion 8 a may have a value belonging to at least one of the following ranges: greater than 0 μm and less than or equal to 0.5 μm, 0.5 μm to 1 μm, 1 μm to 1.5 μm, 1.5 μm to 2 μm, 2 μm to 2.5 μm, 2.5 μm to 3 μm, 3 μm to 3.5 μm, 3.5 μm to 4 μm, 4 μm to 4.5 μm, and 4.5 μm to 5 μm.

[0112] The high-concentration portion 8b may have a fourth concentration C4 within a certain thickness range. The ratio of the thickness of the high-concentration portion 8b to the third thickness T3 may be greater than 0 and less than or equal to 0.8. The thickness ratio may have a value belonging to at least one of the following ranges: greater than 0 and less than or equal to 0.2, 0.2 to 0.4, 0.4 to 0.6, and 0.6 to 0.8.

[0113] The thickness of the high-concentration portion 8b may be greater than 0 μm and less than 5 μm. The thickness of the high-concentration portion 8b may have a value belonging to at least one of the following ranges: greater than 0 μm and less than 0.5 μm, 0.5 μm to 1 μm, 1 μm to 1.5 μm, 1.5 μm to 2 μm, 2 μm to 2.5 μm, 2.5 μm to 3 μm, 3 μm to 3.5 μm, 3.5 μm to 4 μm, 4 μm to 4.5 μm, and 4.5 μm to 5 μm.

[0114] The buffer layer 8 may have one or more (one in this example) medium concentration portions 8d as transition portions 8c in the thickness range between the low concentration portion 8a and the high concentration portion 8b. The medium concentration portion 8d forms an intermediate portion of the buffer layer 8 and extends horizontally along the low concentration portion 8a and the high concentration portion 8b. The medium concentration portion 8d forms part of the first to fourth side surfaces 5A to 5D.

[0115] The medium-concentration portion 8d has a fifth concentration C5 of n-type impurities that is higher than the third concentration C3 and less than the fourth concentration C4. That is, the buffer layer 8 has a concentration gradient that increases in an upward stepwise manner from the low-concentration portion 8a to the high-concentration portion 8b. The fifth concentration C5 is less than the first concentration C1. The fifth concentration C5 may be approximately equal to the first concentration C1. The fifth concentration C5 may be higher than the first concentration C1. The fifth concentration C5 is higher than the second concentration C2. The fifth concentration C5 may be approximately equal to the second concentration C2. The fifth concentration C5 may be less than the second concentration C2.

[0116] The fifth concentration C5 is 1×10 １４ cm －３ 1x10 or more １９ cm －３ The fifth concentration C5 may be 1×10 １４ cm －３ 5x10 or more １４ cm －３ Below, 5 x 10 １４ cm －３ 1x10 or more １５ cm －３ Below, 1 x 10 １５ cm －３ 5x10 or more １５ cm －３ Below, 5 x 10１５ cm －３ 1x10 or more １６ cm －３ Below, 1 x 10 １６ cm －３ 5x10 or more １６ cm －３ Below, 5 x 10 １６ cm －３ 1x10 or more １７ cm －３ Below, 1 x 10 １７ cm －３ 5x10 or more １７ cm －３ Below, 5 x 10 １７ cm －３ 1x10 or more １８ cm －３ Below, 1 x 10 １８ cm －３ 5x10 or more １８ cm －３ Below, and 5 x 10 １８ cm －３ 1x10 or more １９ cm －３ It may have a value that falls within at least one of the following ranges:

[0117] The fifth concentration C5 may be adjusted by a single pentavalent element or multiple pentavalent elements. The fifth concentration C5 is preferably adjusted by a single pentavalent element. The fifth concentration C5 may be adjusted by nitrogen as a pentavalent element.

[0118] The intermediate-concentration portion 8d may have a fifth concentration C5 within a certain thickness range. The ratio of the thickness of the intermediate-concentration portion 8d to the third thickness T3 may be greater than 0 and less than or equal to 0.8. The thickness ratio may have a value belonging to at least one of the following ranges: greater than 0 and less than or equal to 0.2, 0.2 to 0.4, 0.4 to 0.6, and 0.6 to 0.8.

[0119] The thickness of the medium-concentration portion 8d may be greater than 0 μm and less than or equal to 5 μm. The thickness of the medium-concentration portion 8d may have a value belonging to at least one of the following ranges: greater than 0 μm and less than or equal to 0.5 μm, 0.5 μm to 1 μm, 1 μm to 1.5 μm, 1.5 μm to 2 μm, 2 μm to 2.5 μm, 2.5 μm to 3 μm, 3 μm to 3.5 μm, 3.5 μm to 4 μm, 4 μm to 4.5 μm, and 4.5 μm to 5 μm.

[0120] The buffer layer 8 may have a plurality of intermediate concentration portions 8 d. In this case, the intermediate concentration portions 8 d are formed such that the plurality of fifth concentrations C5 increase in sequence from the low concentration portion 8 a to the high concentration portion 8 b within the range between the third concentration C3 and the fourth concentration C4.

[0121] 2 again, the semiconductor device 1X includes a p-type impurity region 9 formed in the semiconductor layer 7. In this embodiment, the impurity region 9 has a p-type impurity concentration higher than the second concentration C2 of the semiconductor layer 7, and converts the conductivity type of the semiconductor layer 7 from n-type to p-type. The impurity region 9 is formed in the semiconductor layer 7 in a surface layer portion of the first main surface 3.

[0122] The impurity region 9 is formed at a distance from the buffer layer 8 (high concentration portion 8b) toward the first main surface 3, and faces the buffer layer 8 across a part of the semiconductor layer 7. The impurity region 9 is formed at a distance from a depth position of the middle portion of the semiconductor layer 7 toward the first main surface 3. The impurity region 9 forms a pn junction with the semiconductor layer 7. This forms a diode structure Di (pn junction diode structure) having the impurity region 9 as an anode region and the semiconductor layer 7 as a cathode region.

[0123] The semiconductor device 1X includes an insulating interlayer film 10 that selectively covers the first main surface 3. The interlayer film 10 includes at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. The interlayer film 10 has one or more (one in this embodiment) contact openings 11 that selectively expose the impurity region 9.

[0124] The semiconductor device 1X includes a first electrode 12 electrically connected to the semiconductor layer 7. The first electrode 12 is an anode electrode for the diode structure Di. The first electrode 12 is disposed on the first main surface 3. The first electrode 12 has a portion disposed in the contact opening 11 and a portion disposed on the interlayer film 10. The first electrode 12 is electrically connected to the impurity region 9 in the contact opening 11.

[0125] The first electrode 12 may have a single-layer structure or a multilayer structure including at least one of a Ti-based metal film (barrier electrode film) and an Al-based metal film. The Ti-based metal film may include either a Ti film or a Ti alloy film, or both. For example, the Ti-based metal film may have a single-layer structure or a multilayer structure including either a Ti film or a TiN film, or both.

[0126] The Al-based metal film may include at least one of an Al film and an Al alloy film. For example, the Al-based metal film may include at least one of an AlSi alloy film, an AlCu alloy film, and an AlSiCu alloy film.

[0127] The semiconductor device 1X includes an insulating top film 13 that selectively covers the first main surface 3. The top film 13 may also be referred to as a "top insulating film." The top film 13 has a portion that selectively covers the first electrode 12 and a portion that selectively covers the interlayer film 10. The top film 13 has an inner edge portion on the inward side of the first main surface 3 and a peripheral edge portion on the peripheral side of the first main surface 3.

[0128] The inner edge of the top film 13 covers the peripheral edge of the first electrode 12 and defines a pad opening 14 that selectively exposes the inner portion of the first electrode 12. The outer edge of the top film 13 is disposed on the interlayer film 10 at a distance from the peripheral edge of the first main surface 3, exposing the peripheral edge of the interlayer film 10.

[0129] In this embodiment, the top film 13 has a laminated structure including an insulating inorganic film 15 and an insulating organic film 16 laminated in this order. The inorganic film 15 may be referred to as an "inorganic insulating film." The organic film 16 may be referred to as an "organic insulating film," a "resin film," or the like. The top film 13 does not necessarily have to have a laminated structure including the inorganic film 15 and the organic film 16, and may have a single-layer structure consisting of either the inorganic film 15 or the organic film 16.

[0130] The inorganic film 15 may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. The inorganic film 15 preferably includes an insulating material different from the insulating material of the interlayer film 10. The organic film 16 has a thickness smaller than that of the first electrode 12.

[0131] The inorganic film 15 has a portion that selectively covers the first electrode 12 and a portion that selectively covers the interlayer film 10. The inorganic film 15 has an inner edge portion on the inner side of the first main surface 3 and a peripheral edge portion on the peripheral side of the first main surface 3. The inner edge portion of the inorganic film 15 covers the peripheral portion of the first electrode 12 and defines a part of the pad opening 14. The outer edge portion of the inorganic film 15 is disposed on the interlayer film 10 at a distance from the peripheral edge of the first main surface 3, exposing the peripheral portion of the interlayer film 10.

[0132] The inorganic film 15 may have a thickness of greater than 0 μm and less than or equal to 2 μm. The thickness of the inorganic film 15 may have a value belonging to at least one of the following ranges: greater than 0 μm and less than or equal to 0.1 μm, 0.1 μm to 0.5 μm, 0.5 μm to 1 μm, 1 μm to 1.5 μm, and 1.5 μm to 2 μm.

[0133] The organic film 16 may include a transparent resin or a light-transmitting resin. The organic film 16 may include a negative-type or positive-type photosensitive resin. The organic film 16 may include at least one of a polyimide film, a polyamide film, and a polybenzoxazole film.

[0134] The organic film 16 has a thickness greater than that of the inorganic film 15. The organic film 16 has a thickness greater than that of the inorganic film 15. The organic film 16 has a portion that selectively covers the first electrode 12 with the inorganic film 15 sandwiched therebetween, and a portion that selectively covers the interlayer film 10 with the inorganic film 15 sandwiched therebetween. The organic film 16 has an inner edge portion on the inward side of the first main surface 3 and a peripheral edge portion on the peripheral side of the first main surface 3.

[0135] The inner edge of the organic film 16 covers the periphery of the first electrode 12 and defines a part of the pad opening 14. In this embodiment, the inner edge of the organic film 16 exposes the inner edge of the inorganic film 15. The inner edge of the organic film 16 may cover the inner edge of the inorganic film 15.

[0136] The outer edge of the organic film 16 is disposed on the interlayer film 10 at a distance from the periphery of the first main surface 3, exposing the periphery of the interlayer film 10. In this embodiment, the outer edge of the organic film 16 exposes the outer edge of the inorganic film 15. The outer edge of the organic film 16 may cover the outer edge of the inorganic film 15.

[0137] The organic film 16 may have a thickness of 1 μm or more and 25 μm or less. The thickness of the organic film 16 may have a value belonging to at least one of the ranges of 1 μm or more and 5 μm or less, 5 μm or more and 10 μm or less, 10 μm or more and 15 μm or less, 15 μm or more and 20 μm or more and 25 μm or less.

[0138] The semiconductor device 1X includes a second electrode 17 electrically connected to the semiconductor substrate 6. The second electrode 17 is a cathode electrode for the diode structure Di. The second electrode 17 is disposed on the second main surface 4. The second electrode 17 may cover the entire second main surface 4. The second electrode 17 may be formed at a distance from the periphery of the second main surface 4, exposing the periphery of the second main surface 4. The second electrode 17, together with the first electrode 12, forms a current path through the chip 2 (semiconductor substrate 6, semiconductor layer 7, and buffer layer 8).

[0139] The second electrode 17 may have a single-layer structure or a multilayer structure including at least one of an Al-based metal film, a Cu-based metal film, a Ti-based metal film, a Ni-based metal film, a Pd-based metal film, an Au-based metal film, and an Ag-based metal film. The Al-based metal film may include at least one of an Al film and an Al alloy film. For example, the Al-based metal film may include at least one of an AlSi alloy film, an AlCu alloy film, and an AlSiCu alloy film.

[0140] The Ti-based metal film may include either or both of a Ti film and a Ti alloy film. The Ni-based metal film may include either or both of a Ni film and a Ni alloy film. The Pd-based metal film may include either or both of a Pd film and a Pd alloy film. The Au-based metal film may include either or both of an Au film and an Au alloy film. The Ag-based metal film may include either or both of an Ag film and an Ag alloy film.

[0141] When the second electrode 17 has a layered structure, at least two of an Al-based metal film, a Cu-based metal film, a Ti-based metal film, a Ni-based metal film, a Pd-based metal film, an Au-based metal film, and an Ag-based metal film are layered on the second main surface 4 in any order and combination.

[0142] For example, the second electrode 17 may have a layered structure including an Al-based metal film, a Ti-based metal film, a Ni-based metal film, a Pd-based metal film, an Au-based metal film, and an Ag-based metal film, which are layered in this order from the semiconductor substrate 6 side. In this case, at least one of the Al-based metal film, the Ti-based metal film, the Ni-based metal film, the Pd-based metal film, the Au-based metal film, and the Ag-based metal film may be removed.

[0143] The breakdown voltage that can be applied between the first electrode 12 and the second electrode 17 (between the first main surface 3 and the second main surface 4) may be 500 V or more and 3000 V or less. The breakdown voltage may have a value that belongs to at least one of the ranges of 500 V or more and 750 V or less, 750 V or more and 1000 V or less, 1000 V or more and 1250 V or less, 1250 V or more and 1500 V or less, 1500 V or more and 1750 V or less, 1750 V or more and 2000 V or less, 2000 V or more and 2250 V or less, 2250 V or more and 2500 V or less, and 2500 V or more and 3000 V or less.

[0144] Fig. 4 is a cross-sectional view showing a semiconductor device 18 according to a comparative example. Fig. 5 is a graph (simulation) showing the carrier density of the semiconductor device 18 according to the comparative example. In Fig. 5, the vertical axis represents hole density, and the horizontal axis represents depth.

[0145] 4, the semiconductor device 18 according to the comparative example has a buffer layer 19 according to the comparative example instead of the buffer layer 8. The buffer layer 19 has a uniform impurity concentration that is less than the first concentration C1 of the semiconductor substrate 6 and higher than the second concentration C2 of the semiconductor layer 7, and does not have a low concentration portion 8a, a high concentration portion 8b, or a transition portion 8c. The other configuration of the semiconductor device 18 is similar to that of the semiconductor device 1X.

[0146] When a forward voltage Vf is applied to the diode structure Di (impurity region 9), the diode structure Di operates in a bipolar manner. In this case, the impurity region 9 serves as a carrier supply source that supplies holes as minority carriers to the semiconductor layer 7.

[0147] The holes supplied from the impurity region 9 recombine with majority carriers in the chip 2 and release energy. The n-type impurity concentration in the chip 2 increases in the order of the semiconductor layer 7, the buffer layer 19, and the semiconductor substrate 6. Therefore, the lifetime of holes in the chip 2 becomes shorter in the order of the semiconductor layer 7, the buffer layer 19, and the semiconductor substrate 6.

[0148] 5 , the majority of holes recombine with electrons in semiconductor layer 7 and buffer layer 19, but a small number of holes reach semiconductor substrate 6. When holes recombine with electrons at or near basal plane dislocation defects, the energy resulting from the recombination may cause atoms of the basal plane dislocation defects to migrate from semiconductor substrate 6 toward semiconductor layer 7.

[0149] In this case, atom migration due to basal plane dislocations may propagate into the buffer layer 19 as a single Shockley stacking fault (1SSF). The single Shockley stacking fault traps conduction carriers during bipolar operation, causing an increase in on-state voltage and on-state resistance. This type of problem is known as bipolar degradation.

[0150] Fig. 6 is a cross-sectional view showing the semiconductor device 1X shown in Fig. 1. Fig. 7 is a graph (simulation) showing the carrier density of the semiconductor device 1X shown in Fig. 1. In Fig. 7, the vertical axis represents hole density and the horizontal axis represents depth. In Fig. 7, the carrier density of the semiconductor device 18 according to the comparative example is shown by a dashed line, and the carrier density of the semiconductor device 1X is shown by a solid line.

[0151] On the other hand, the semiconductor device 1X includes an n-type (first conductivity type) semiconductor substrate 6 (substrate), an n-type semiconductor layer 7, and an n-type buffer layer 8. The semiconductor substrate 6 has a first concentration C1. The semiconductor layer 7 has a second concentration C2 less than the first concentration C1 and is stacked on the semiconductor substrate 6.

[0152] The buffer layer 8 is interposed between the semiconductor substrate 6 and the semiconductor layer 7. The buffer layer 8 includes a low-concentration portion 8a and a high-concentration portion 8b. The low-concentration portion 8a has a third concentration C3 less than the first concentration C1 and is formed in a region on the semiconductor substrate 6 side. The high-concentration portion 8b has a fourth concentration C4 higher than the third concentration C3 and is formed in a region on the semiconductor layer 7 side.

[0153] This configuration provides a novel semiconductor device 1X. For example, in this semiconductor device 1X, holes (minority carriers) recombine with electrons (majority carriers) in the high-concentration region 8b, reducing the number of holes reaching the low-concentration region 8a. This reduces the number of holes reaching the boundary between the semiconductor substrate 6 and the buffer layer 8, suppressing bipolar degradation due to basal plane dislocation defects. As a result, electrical characteristics are improved.

[0154] Such a configuration is effective in suppressing an increase in the thickness of the buffer layer 8 and an increase in the impurity concentration of the entire buffer layer 8. This appropriately increases the uniformity of the impurity concentration and layer thickness of the buffer layer 8, allowing holes and electrons to appropriately recombine in the high-concentration portion 8 b. In addition, the manufacturing cost of the buffer layer 8 is reduced.

[0155] For example, the fourth concentration C4 of the high-concentration portion 8b is 1×10 １７ cm －３ In the above cases, holes and electrons recombine in multiple modes in the high-concentration portion 8b, effectively shortening the lifetime. For example, the multiple modes include at least two of radiative recombination, direct recombination, Shockley Read Hall (SRH) recombination, and Auger recombination. When the fourth concentration C4 of the high-concentration portion 8b is 1×10 １８ cm －３ In these cases, radiative and Auger recombination are adequately promoted.

[0156] The recombination rate of holes and electrons before reaching the low-concentration portion 8 a may be 80% or more and 100% or less, and may have a value that falls within at least one of the ranges of 80% or more and 85% or less, 85% or more and 90% or less, 90% or more and 95% or less, and 95% or more and 100% or less.

[0157] The semiconductor substrate 6 may contain SiC. The semiconductor layer 7 may contain SiC. The buffer layer 8 may contain SiC. This configuration provides a semiconductor device 1X as a SiC semiconductor device having a novel layout. In this semiconductor device 1X, the electrical characteristics are appropriately improved due to the physical properties of SiC. In particular, in the case of SiC semiconductor devices, since they are used in a relatively high voltage environment, the effect of suppressing bipolar degradation is effective in improving the electrical characteristics.

[0158] The semiconductor substrate 6 may have an off angle θ. The off angle θ may be 10° or less. The off angle θ may be inclined toward the off direction. The off direction may be the a-axis direction.

[0159] The first concentration C1, the second concentration C2, the third concentration C3, and the fourth concentration C4 are adjusted as appropriate depending on the thickness of the buffer layer 8 and the electrical characteristics to be achieved. The third concentration C3 may be equal to or greater than the second concentration C2. The third concentration C3 may be less than the second concentration C2. The fourth concentration C4 may be higher than the second concentration C2. The fourth concentration C4 may be equal to or greater than the first concentration C1. The fourth concentration C4 may be less than the first concentration C1. With the fourth concentration C4 higher than the first concentration C1, holes can be efficiently recombined with electrons in the high-concentration portion 8b.

[0160] The buffer layer 8 may include a transition portion 8c. The transition portion 8c may have a gradient in which the concentration gradually increases from a third concentration C3 to a fourth concentration C4 in a region between the low-concentration portion 8a and the high-concentration portion 8b. With this configuration, holes that have passed through the high-concentration portion 8b can recombine with electrons in the transition portion 8c. Therefore, an increase in the impurity concentration of the entire buffer layer 8 is suppressed, and the number of holes that reach the low-concentration portion 8a can be reduced by the transition portion 8c.

[0161] The semiconductor layer 7 may be thicker than the buffer layer 8. The buffer layer 8 may have a thickness of 10 μm or less. The semiconductor layer 7 may have a thickness of 50 μm or less.

[0162] The semiconductor device 1X may include a p-type (second conductivity type) impurity region 9 formed in the semiconductor layer 7. With this configuration, holes supplied from the impurity region 9 can be recombined with electrons in the high-concentration portion 8b. The semiconductor device 1X may include a first electrode 12 electrically connected to the semiconductor layer 7. The semiconductor device 1X may include a second electrode 17 electrically connected to the semiconductor substrate 6.

[0163] The impurity region 9 may be formed in a surface layer portion of the semiconductor layer 7 at a distance from the high-concentration portion 8b of the buffer layer 8. With this configuration, direct supply of holes from the impurity region 9 to the high-concentration portion 8b is appropriately suppressed, and bipolar deterioration caused by the impurity region 9 is appropriately suppressed. The impurity region 9 appropriately forms a pn junction (diode structure Di) with the semiconductor layer 7. As a result, a depletion layer originating from the pn junction appropriately spreads into the semiconductor layer 7.

[0164] The semiconductor device 1X may include an impurity region 9 partially formed in a surface layer portion of the first main surface 3. In this case, the first electrode 12 may have a portion that forms an ohmic junction with the impurity region 9 and a portion that forms a Schottky junction with the semiconductor layer 7. In this case, the diode structure Di includes both a pn junction diode structure and a Schottky barrier diode structure.

[0165] Hereinafter, the configurations of semiconductor devices 1A to 1G each having the configuration of the semiconductor device 1X (semiconductor substrate 6, semiconductor layer 7, and buffer layer 8) as a basic configuration will be shown.

[0166] Fig. 8 is a plan view showing a semiconductor device 1A according to the first embodiment. Fig. 9 is a cross-sectional view taken along line IX-IX shown in Fig. 8. Fig. 10 is an enlarged plan view showing a main part of the first main surface 3. Fig. 11 is a cross-sectional view taken along line XI-XI shown in Fig. 10. Fig. 12 is a cross-sectional view taken along line XII-XII shown in Fig. 10. Fig. 13 is a cross-sectional view taken along line XIII-XIII shown in Fig. 7.

[0167] The semiconductor device 1A is a semiconductor switching device having an insulated gate transistor structure Tr as an example of a device structure (functional device). The transistor structure Tr has a trench gate vertical structure.

[0168] The semiconductor device 1A includes the aforementioned chip 2. The chip 2 includes a semiconductor substrate 6, a semiconductor layer 7, and a buffer layer 8. The buffer layer 8 includes a low concentration portion 8a, a high concentration portion 8b, and a transition portion 8c. The buffer layer 8 may have any one of the first to thirteenth concentration gradient examples (see FIGS. 3A to 3M).

[0169] The semiconductor device 1A includes an active region 20 provided in the semiconductor layer 7. The active region 20 includes a device structure (transistor structure Tr) and is a region where an output current (drain current) is generated. The active region 20 is set in an inner portion of the semiconductor layer 7 and spaced apart from the periphery of the first main surface 3 (first to fourth side surfaces 5A to 5D).

[0170] In plan view, active region 20 has a polygonal shape (a quadrilateral shape in this embodiment) having four sides parallel to the periphery of first main surface 3. Active region 20 has a quadrilaterally recessed portion along the center of fourth side surface 5D toward second side surface 5B.

[0171] The ratio (area ratio) of the planar area of ​​the active region 20 to the planar area of ​​the first main surface 3 may be 0.5 or more and 0.95 or less. The area ratio may have a value belonging to at least one of the ranges of 0.5 or more and 0.6 or less, 0.6 or more and 0.7 or less, 0.7 or more and 0.8 or less, 0.8 or more and 0.9 or less, and 0.9 or more and 0.95 or less.

[0172] The semiconductor device 1A includes a peripheral region 21 set outside the active region 20 in the semiconductor layer 7. The peripheral region 21 is a region that does not include a device structure (transistor structure Tr). The peripheral region 21 is set in the peripheral portion of the semiconductor layer 7. That is, the peripheral region 21 is provided in a region between the periphery of the first main surface 3 and the active region 20 in a planar view. The peripheral region 21 extends in a band shape along the active region 20 in a planar view, and is set in a polygonal ring shape (a square ring shape in this embodiment) that surrounds the active region 20.

[0173] The semiconductor device 1A includes the aforementioned impurity region 9 formed in the surface layer portion of the first main surface 3 in the active region 20 (inner portion of the first main surface 3). In this embodiment, the impurity region 9 is formed as a p-type body region 22. The body region 22 may also be referred to as a "channel region" or the like. A source potential may be applied to the body region 22. The source potential may be a reference potential that serves as a reference for circuit operation. The reference potential may be a ground potential.

[0174] The body region 22 has a p-type impurity concentration higher than the n-type impurity concentration of the semiconductor layer 7, and replaces the n-type conductivity of the semiconductor layer 7 with p-type. The body region 22 is formed in the active region 20 at a distance from the periphery of the first main surface 3, and is not formed in the peripheral region 21. In this embodiment, the body region 22 is formed throughout the active region 20. The body region 22 is formed in a surface layer portion of the semiconductor layer 7 and extends in a layered form along the first main surface 3.

[0175] The body region 22 is formed at a distance from the buffer layer 8 (high concentration portion 8 b) toward the first main surface 3, and faces the buffer layer 8 across a part of the semiconductor layer 7. The body region 22 is formed at a distance from a depth position of the middle portion of the semiconductor layer 7 toward the first main surface 3. The body region 22 forms a pn junction with the semiconductor layer 7.

[0176] This forms a body diode structure (pn junction diode structure) as a diode structure Di having the body region 22 as an anode region and the semiconductor layer 7 as a cathode region. The body region 22 spreads a depletion layer in the semiconductor layer 7 when a reverse bias voltage is applied. The depletion layer originating from the body region 22 spreads in the horizontal direction and thickness direction within the semiconductor layer 7.

[0177] The semiconductor device 1A includes a plurality of trench-type (trench electrode-type) gate structures 25 formed in an inner portion of the first main surface 3. The gate structures 25 may also be referred to as "trench structures," "trench gate structures," or the like. A gate potential (gate signal) serving as a control potential is applied to the plurality of gate structures 25. The plurality of gate structures 25 control inversion and non-inversion of the channel in the body region 22 in response to the gate potential.

[0178] The multiple gate structures 25 are formed in the active region 20 at intervals from the periphery of the first main surface 3, and are not formed in the peripheral region 21. The multiple gate structures 25 are arranged at intervals in the first direction X (= m-axis direction) in plan view, and each extend in a strip shape in the second direction Y (= a-axis direction). The multiple gate structures 25 are arranged in a strip shape extending in the second direction Y in plan view.

[0179] The extension direction of the multiple gate structures 25 coincides with the off-direction of the SiC single crystal. With respect to the second direction Y, both end portions of the multiple gate structures 25 are located inward from the periphery of the body region 22. Both end portions of the multiple gate structures 25 may be located outward from the periphery of the body region 22. The multiple gate structures 25 may be arranged at intervals in the second direction Y in a plan view, and each extend in a strip shape in the first direction X.

[0180] The plurality of gate structures 25 penetrate the body region 22 to reach the semiconductor layer 7. The plurality of gate structures 25 are formed at intervals from the buffer layer 8 (high concentration portion 8 b) toward the first main surface 3, and face the buffer layer 8 with a part of the semiconductor layer 7 interposed therebetween.

[0181] The plurality of gate structures 25 may be formed at intervals from a depth position of an intermediate portion of the semiconductor layer 7 toward the first main surface 3, or may have a portion located on the buffer layer 8 (high concentration portion 8b) side with respect to the depth position of the intermediate portion of the semiconductor layer 7. The plurality of gate structures 25 are formed substantially perpendicular to the first main surface 3. The plurality of gate structures 25 may be formed in a shape tapering toward the buffer layer 8 (high concentration portion 8b).

[0182] The side walls (long sides) of the plurality of gate structures 25 are formed by the m-plane ((1-100) plane) of the SiC single crystal. The side walls (long sides) of the plurality of gate structures 25 may be formed by the a-plane ((11-20) plane) of the SiC single crystal depending on the extension direction of the gate structures 25. The side walls of the plurality of gate structures 25, together with the first main surface 3, define an opening end curved in an arc shape (circular arc shape).

[0183] The bottom walls of the gate structures 25 are formed by the c-plane (Si-plane) of the SiC single crystal. The bottom walls of the gate structures 25 preferably extend substantially flat in the horizontal direction. The bottom walls of the gate structures 25 may be curved in an arc shape toward the second main surface 4.

[0184] The inclination angle (absolute value) of the sidewall (long side) of the gate structure 25 relative to the vertical line may be 85° or more and 95° or less. The inclination angle may have a value belonging to at least one of the ranges of 85° or more and 87.5° or less, 87.5° or more and 90° or less, 90° or more and 92.5° or less, and 92.5° or more and 95° or less. The inclination angle is preferably 87° or more and 93° or less.

[0185] The gate structure 25 may have a width of 0.1 μm to 2 μm. The width of the gate structure 25 may have a value belonging to at least one of the ranges of 0.1 μm to 0.25 μm, 0.25 μm to 0.5 μm, 0.5 μm to 0.75 μm, 0.75 μm to 1 μm, 1 μm to 1.25 μm, 1.25 μm to 1.5 μm, 1.5 μm to 1.75 μm, and 1.75 μm to 2 μm. The width of the gate structure 25 is preferably 1 μm or less.

[0186] The gate structure 25 may have a depth of 0.1 μm or more and 3 μm or less. The depth of the gate structure 25 is measured from the first main surface 3. The depth of the gate structure 25 may have a value belonging to at least one of the ranges of 0.1 μm or more and 0.5 μm or less, 0.5 μm or more and 1 μm or less, 1 μm or more and 1.5 μm or less, 1.5 μm or more and 2 μm or less, 2 μm or more and 2.5 μm or less, and 2.5 μm or more and 3 μm or less. The depth of the gate structure 25 is preferably 0.5 μm or more and 1.5 μm or less.

[0187] The gate structure 25 may have an aspect ratio of 1 to 3. The aspect ratio of the gate structure 25 is the ratio of the depth of the gate structure 25 to the width of the gate structure 25. The aspect ratio may have a value belonging to at least one of the ranges of 1 to 1.25, 1.25 to 1.5, 1.5 to 1.75, 1.75 to 2, 2 to 2.25, 2.25 to 2.5, 2.5 to 2.75, and 2.75 to 3. The aspect ratio is preferably 1.5 to 2.5.

[0188] The multiple gate structures 25 may be arranged at intervals of 0.1 μm to 2 μm. The interval between the gate structures 25 is the distance between the multiple gate structures 25 in the horizontal direction (first direction X). The interval between the gate structures 25 may have a value belonging to at least one of the ranges of 0.1 μm to 0.25 μm, 0.25 μm to 0.5 μm, 0.5 μm to 0.75 μm, 0.75 μm to 1 μm, 1 μm to 1.25 μm, 1.25 μm to 1.5 μm, 1.5 μm to 1.75 μm, and 1.75 μm to 2 μm. The interval between the gate structures 25 is preferably 1 μm or less.

[0189] Each of the multiple gate structures 25 includes a trench 26, an insulating film 27, and a buried electrode 28. The trench 26 may be referred to as a "gate trench," the insulating film 27 may be referred to as a "gate insulating film," and the buried electrode 28 may be referred to as a "gate electrode." The trench 26 is formed in the first main surface 3 and defines the wall surfaces (sidewalls and bottom wall) of the gate structure 25.

[0190] The insulating film 27 may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. The insulating film 27 may include a silicon oxide film containing an oxide of the semiconductor layer 7. The insulating film 27 may include a silicon oxide film containing an oxide other than the oxide of the semiconductor layer 7.

[0191] The insulating film 27 covers the wall surface of the trench 26. In this embodiment, the insulating film 27 has an upper end located on the bottom wall side of the trench 26 relative to the height position of the first main surface 3, and exposes a part of the chip 2 from the wall surface at the opening end of the trench 26. The upper end of the insulating film 27 is preferably located on the opening side of the trench 26 relative to the depth position of the intermediate part of the trench 26.

[0192] The thickness of the portion of the insulating film 27 that covers the sidewall of the trench 26 may be greater than the thickness of the portion of the insulating film 27 that covers the bottom wall of the trench 26. The thickness of the insulating film 27 may be 10 nm or more and 250 nm or less.

[0193] The thickness of the insulating film 27 may have a value belonging to at least one of the ranges of 10 nm to 25 nm, 25 nm to 50 nm, 50 nm to 75 nm, 75 nm to 100 nm, 100 nm to 125 nm, 125 nm to 150 nm, 150 nm to 175 nm, 175 nm to 200 nm, 200 nm to 225 nm, and 225 nm to 250 nm.

[0194] The buried electrode 28 may include either or both of p-type conductive polysilicon and n-type conductive polysilicon. The buried electrode 28 is preferably made of n-type conductive polysilicon. The buried electrode 28 is buried in the trench 26 with the insulating film 27 interposed therebetween, and faces the semiconductor layer 7 and the body region 22 with the insulating film 27 interposed therebetween.

[0195] The buried electrode 28 has an electrode surface exposed from the trench 26. The electrode surface is located on the bottom wall side of the trench 26 at a distance from the height position of the first main surface 3. The electrode surface is located on the first main surface 3 side with respect to the depth position of the intermediate portion of the trench 26. The electrode surface may be located on the bottom wall side of the trench 26 with respect to the depth position of the intermediate portion of the trench 26. The electrode surface may have a recess recessed toward the bottom wall side of the trench 26.

[0196] The semiconductor device 1A includes a plurality of mesas 29 defined on the first main surface 3 in the active region 20. The mesas 29 are defined in regions between adjacent gate structures 25. The mesas 29 are defined at intervals in the first direction X in accordance with the layout of the gate structures 25, and extend in a strip-like manner in the second direction Y. The mesas 29 extend in a strip-like manner in the second direction Y. The width of each mesa 29 corresponds to the spacing between the gate structures 25.

[0197] The semiconductor device 1A includes a plurality of p-type well regions 30 formed in the semiconductor layer 7. The plurality of well regions 30 are also a form of impurity regions 9. The plurality of well regions 30 have a p-type impurity concentration higher than the n-type impurity concentration of the semiconductor layer 7, and convert the conductivity type of the semiconductor layer 7 from n-type to p-type. A source potential is applied to the plurality of well regions 30.

[0198] The multiple well regions 30 are formed in regions below (specifically, directly below) the multiple gate structures 25, with intervals between them in the horizontal direction (first direction X) within the semiconductor layer 7. The multiple well regions 30 are formed in the thickness range between the buffer layer 8 (high concentration portion 8 b) and the bottom walls of the multiple gate structures 25, and overlap the multiple gate structures 25 in a one-to-one correspondence in the thickness direction.

[0199] The multiple well regions 30 each extend in a strip shape in the second direction Y in plan view, following the extension direction of the corresponding gate structures 25. The multiple well regions 30 are arranged in a stripe shape extending in the second direction Y in plan view. The extension direction of the multiple well regions 30 coincides with the off-direction of the SiC single crystal.

[0200] In the second direction Y, both ends of the multiple well regions 30 may be located on the inner side of the multiple gate structures 25 relative to both ends of the multiple gate structures 25, or may be located on the peripheral side of the active region 20. The multiple well regions 30 may extend in the first direction X according to the extending direction of the multiple gate structures 25. In this case, the multiple well regions 30 intersect (specifically, perpendicular to) the off direction.

[0201] In this embodiment, the multiple well regions 30 extend vertically in the thickness direction of the semiconductor layer 7. The multiple well regions 30 are formed at intervals from the buffer layer 8 (high concentration portion 8b) on the bottom wall side of the multiple gate structures 25, and face the buffer layer 8 with part of the semiconductor layer 7 interposed therebetween. Each of the multiple well regions 30 has an upper end located on the bottom wall side of the corresponding gate structure 25, and a bottom located on the buffer layer 8 (high concentration portion 8b) side.

[0202] The upper ends of the multiple well regions 30 are formed at intervals from the bottom of the body region 22 toward the bottom wall of the corresponding gate structure 25. The upper ends of the multiple well regions 30 are connected to the bottom wall of the corresponding gate structure 25 and face the buried electrode 28 via the insulating film 27.

[0203] The upper ends of the multiple well regions 30 may have portions that extend along the side walls of the corresponding gate structures 25. That is, the multiple well regions 30 may face the buried electrodes 28 on the side walls of the corresponding gate structures 25 via the insulating film 27. The upper ends of the multiple well regions 30 may be formed at intervals from the bottom walls of the corresponding gate structures 25 toward the buffer layer 8 (high concentration portion 8b).

[0204] The bottoms of the multiple well regions 30 may be located on the bottom wall side of the multiple gate structures 25 or on the buffer layer 8 (high concentration portion 8 b) side with respect to the depth position of the intermediate portion of the semiconductor layer 7. The bottoms of the multiple well regions 30 are directly connected to the semiconductor layer 7.

[0205] The multiple well regions 30 may form a superjunction structure together with the semiconductor layer 7 in the region below the gate structure 25. In this case, depletion layers originating from the multiple well regions 30 are connected to each other in the regions between the multiple well regions 30.

[0206] In this embodiment, the depth of the well region 30 relative to the bottom wall of the gate structure 25 is smaller than the depth of the gate structure 25 relative to the first main surface 3. The depth of the well region 30 may be larger than the depth of the gate structure 25 relative to the first main surface 3.

[0207] The depth of the well region 30 may be 0.5 μm or more and 5 μm or less. The depth of the well region 30 may have a value belonging to at least one of the ranges of 0.5 μm or more and 1 μm or less, 1 μm or more and 1.5 μm or less, 1.5 μm or more and 2 μm or less, 2 μm or more and 2.5 μm or less, 2.5 μm or more and 3 μm or less, 3 μm or more and 3.5 μm or less, 3.5 μm or more and 4 μm or less, 4 μm or more and 4.5 μm or less, and 4.5 μm or more and 5 μm or less.

[0208] The plurality of well regions 30 each include a first well region 31 located on the bottom wall side of the gate structure 25 and a second well region 32 located on the buffer layer 8 (high concentration portion 8b) side. The first well region 31 is located on the bottom wall side of the gate structure 25 with respect to the depth position of the middle portion of the well region 30, and forms the upper end portion of the well region 30.

[0209] In the second direction Y, both ends of the first well region 31 may be located inward of both ends of the gate structure 25, or may be located on the peripheral side of the active region 20. The first well region 31 may face the buried electrode 28 via the insulating film 27. The first well region 31 may have a portion along the sidewall of the gate structure 25. In other words, the first well region 31 may face the buried electrode 28 on the sidewall of the gate structure 25 via the insulating film 27.

[0210] The ratio of the depth of the first well region 31 to the depth of the well region 30 (first depth ratio) may be greater than 0 and less than 0.5. The first depth ratio may have a value belonging to at least one of the following ranges: greater than 0 and less than 0.1, 0.1 to 0.2, 0.2 to 0.3, 0.3 to 0.4, and 0.4 to 0.5. The first depth ratio is preferably less than 0.5.

[0211] The depth of the first well region 31 is smaller than the depth of the gate structure 25. The depth of the first well region 31 may be greater than 0 μm and less than or equal to 1 μm. The depth of the first well region 31 may have a value belonging to at least one of the following ranges: greater than 0 μm and less than or equal to 0.1 μm, 0.1 μm to 0.2 μm, 0.2 μm to 0.3 μm, 0.3 μm to 0.4 μm, 0.5 μm to 0.6 μm, 0.6 μm to 0.7 μm, 0.7 μm to 0.8 μm, 0.8 μm to 0.9 μm, and 0.9 μm to 1 μm. The depth of the first well region 31 is preferably less than or equal to 0.5 μm.

[0212] The second well region 32 is located on the buffer layer 8 (high concentration portion 8b) side with respect to the first well region 31, and forms the bottom of the well region 30. The second well region 32 extends in a strip shape in the second direction Y following the extension direction of the gate structure 25. With respect to the second direction Y, both ends of the second well region 32 may be located on the inward side of the gate structure 25 with respect to both ends of the gate structure 25, or may be located on the peripheral side of the active region 20.

[0213] In this embodiment, the second well region 32 has a portion located on the bottom wall side of the gate structure 25 corresponding to the depth position of the middle part of the well region 30, and a portion located on the buffer layer 8 (high concentration portion 8b) side relative to the depth position of the middle part of the well region 30.

[0214] The depth of the second well region 32 is obtained by subtracting the depth of the first well region 31 from the depth of the well region 30. The depth of the second well region 32 is measured from the bottom of the first well region 31. The ratio of the depth of the second well region 32 to the depth of the well region 30 (second depth ratio) is calculated by "1 - first depth ratio."

[0215] The second depth ratio is preferably equal to or greater than 0.5. It is particularly preferable that the second depth ratio is greater than 0.5. In this embodiment, the depth of the second well region 32 is smaller than the depth of the gate structure 25. The depth of the second well region 32 may be greater than the depth of the gate structure 25.

[0216] The depth of the second well region 32 may be 0.5 μm or more and 5 μm or less. The depth of the second well region 32 may have a value belonging to at least one of the ranges of 0.5 μm or more and 1 μm or less, 1 μm or more and 1.5 μm or less, 1.5 μm or more and 2 μm or less, 2 μm or more and 2.5 μm or less, 2.5 μm or more and 3 μm or less, 3 μm or more and 3.5 μm or less, 3.5 μm or more and 4 μm or less, 4 μm or more and 4.5 μm or less, and 4.5 μm or more and 5 μm or less.

[0217] The semiconductor device 1A includes a plurality of n-type source regions 33 formed in the body region 22 in the active region 20. The source regions 33 have a higher n-type impurity concentration than the p-type impurity concentration of the body region 22, thereby converting the conductivity type of the body region 22 from p-type to n-type. The n-type impurity concentration of the source regions 33 is higher than the n-type impurity concentration of the semiconductor layer 7.

[0218] The plurality of source regions 33 are formed in the plurality of mesa portions 29 in the surface layer portion of the body region 22. In this embodiment, the plurality of source regions 33 are formed at intervals in the second direction Y in a one-to-many correspondence with the plurality of mesa portions 29, and are adjacent to two gate structures 25 corresponding to the first direction X. In this embodiment, the plurality of source regions 33 each extend in a strip shape in the second direction Y following the extension direction of the plurality of gate structures 25 in a plan view.

[0219] The plurality of source regions 33 on one side in the first direction X face the plurality of source regions 33 on the other side in the first direction X, with a corresponding gate structure 25 sandwiched between them. That is, the plurality of source regions 33 are arranged in a line in the first direction X in a planar view. In this embodiment, the plurality of source regions 33 are arranged in a matrix with intervals in the first direction X and the second direction Y in a planar view.

[0220] The plurality of source regions 33 on one side in the first direction X may face regions between the plurality of source regions 33 on the other side in the first direction X, with a corresponding gate structure 25 sandwiched therebetween. In other words, the plurality of source regions 33 may be arranged in a staggered pattern at intervals in the first direction X and the second direction Y in a plan view.

[0221] The source regions 33 each have a thickness (depth) less than the thickness (depth) of the body region 22, and are formed at intervals from the bottom of the body region 22 toward the first main surface 3. The source regions 33 face the semiconductor layer 7 with a part (bottom) of the body region 22 sandwiched therebetween.

[0222] The plurality of source regions 33 each have a portion located on the bottom wall side of the plurality of trenches 26 with respect to the electrode surfaces of the plurality of buried electrodes 28, and a portion located on the first main surface 3 side with respect to the electrode surfaces of the plurality of buried electrodes 28. The plurality of source regions 33 each have a portion horizontally facing the corresponding buried electrode 28 with the corresponding insulating film 27 interposed therebetween.

[0223] The source region 33 has a thickness (depth) greater than the thickness between the bottom of the body region 22 and the bottom of the source region 33. The thickness of the source region 33 may be less than the thickness between the bottom of the body region 22 and the bottom of the source region 33. The multiple source regions 33, together with the semiconductor layer 7, define a channel that serves as a current path on the bottom side of the body region 22.

[0224] The channel may have a channel length greater than 0 nm and less than or equal to 500 nm. The channel length is the distance between the bottom of the body region 22 and the bottom of the source region 33. The channel length may have a value belonging to at least one of the following ranges: greater than 0 nm and less than or equal to 50 nm, 50 nm to 100 nm, 100 nm to 150 nm, 150 nm to 200 nm, 200 nm to 250 nm, 250 nm to 300 nm, 300 nm to 350 nm, 350 nm to 400 nm, 400 nm to 450 nm, and 450 nm to 500 nm. The channel length is preferably less than or equal to 300 nm.

[0225] The semiconductor device 1A includes a plurality of contact regions 34 formed in the semiconductor layer 7 in the active region 20. A source potential is applied to the contact regions 34. The contact regions 34 have a p-type impurity concentration higher than the n-type impurity concentration of the semiconductor layer 7. The p-type impurity concentration of the contact regions 34 is higher than the p-type impurity concentration of the body region 22.

[0226] The p-type impurity concentration of the contact region 34 is higher than the p-type impurity concentration of the second well region 32. The p-type impurity concentration of the contact region 34 may be higher or lower than the p-type impurity concentration of the first well region 31. The p-type impurity concentration of the contact region 34 may be higher or lower than the n-type impurity concentration of the source region 33.

[0227] The plurality of contact regions 34 are formed in regions along the plurality of gate structures 25 at intervals from the buffer layer 8 (high concentration portion 8 b) toward the first main surface 3. The plurality of contact regions 34 are formed at intervals in the second direction Y in a one-to-many correspondence with the plurality of gate structures 25. Specifically, the plurality of contact regions 34 are interposed in regions between the plurality of source regions 33.

[0228] The plurality of contact regions 34 may be connected to the plurality of source regions 33 in the second direction Y. The plurality of contact regions 34 may be formed at intervals from the plurality of source regions 33 in the second direction Y. In this case, the plurality of contact regions 34 may face the plurality of source regions 33 with a part of the body region 22 interposed therebetween.

[0229] In plan view, the plurality of contact regions 34 along one gate structure 25 face the plurality of contact regions 34 along the other gate structure 25 in the first direction X. In other words, the plurality of contact regions 34 are generally arranged in a matrix with gaps in the first direction X and the second direction Y in plan view.

[0230] In plan view, one of the plurality of contact regions 34 may face a region between the other of the plurality of contact regions 34 in the first direction X. In other words, the plurality of contact regions 34 may be generally arranged in a staggered pattern with intervals in the first direction X and the second direction Y in plan view.

[0231] The contact regions 34 may extend in a strip-like shape in the second direction Y in a plan view, following the extension direction of the gate structures 25. The lengths of the contact regions 34 in the second direction Y may be equal to each other or may be different from each other. The lengths of the contact regions 34 in the second direction Y are adjusted depending on the area of ​​the channel to be formed.

[0232] The channel area is the total area of ​​the portions of the source regions 33 exposed from the regions between the gate structures 25. That is, the channel area increases or decreases depending on the ratio of the total planar area of ​​the contact regions 34. The total planar area of ​​the contact regions 34 is preferably less than the channel area. That is, in the regions between the gate structures 25, the total planar area of ​​the contact regions 34 is preferably less than the planar area of ​​the source regions 33.

[0233] The length of the contact region 34 may be greater or smaller than the width of the gate structure 25. The length of the contact region 34 may be greater or smaller than the spacing between the multiple gate structures 25 (the width of the mesa portion 29). The spacing between the multiple contact regions 34 may be greater or smaller than the width of the gate structure 25. The spacing between the contact regions 34 may be greater or smaller than the spacing between the multiple gate structures 25.

[0234] The plurality of contact regions 34 each include a first region 34A, a second region 34B, and a third region 34C. The first region 34A extends along the bottom wall of the corresponding gate structure 25. The first region 34A is interposed in a region between the bottom wall of the corresponding gate structure 25 and the bottom of the corresponding well region 30, and is connected to the bottom wall of the corresponding gate structure 25 and the corresponding well region 30. The first region 34A faces the buried electrode 28 via the insulating film 27.

[0235] The first region 34A has a thickness greater than that of the first well region 31, and has a bottom located closer to the bottom of the second well region 32 than the depth position of the lower end (bottom) of the first well region 31. The thickness of the first region 34A is the thickness of the first region 34A in the vertical direction Z, with the bottom wall of the gate structure 25 as the reference.

[0236] The bottom of the first region 34A is formed at a distance from the bottom of the second well region 32 toward the bottom wall of the gate structure 25, and faces the semiconductor layer 7 across a part of the second well region 32. The bottom of the first region 34A may be located on the bottom wall side of the gate structure 25 with respect to the depth position of the intermediate portion of the second well region 32. The bottom of the first region 34A may be located on the bottom side of the second well region 32 with respect to the depth position of the intermediate portion of the second well region 32.

[0237] The first regions 34A have a width greater than that of the gate structures 25, and extend horizontally from the region directly below the corresponding gate structure 25 to both sides of the corresponding gate structure 25. The first regions 34A are connected to the first well region 31 and the second well region 32, and increase the p-type impurity concentration of the first well region 31 and the p-type impurity concentration of the second well region 32.

[0238] The first region 34A may have a thickness less than that of the first well region 31, and may be formed at a distance from the depth position of the lower end of the first well region 31 toward the bottom wall of the gate structure 25. In this case, the first region 34A may face the second well region 32 with a part of the first well region 31 in between.

[0239] The second region 34B is a portion extending along the sidewall of the gate structure 25. The second region 34B faces the buried electrode 28 via the insulating film 27. The second region 34B has a thickness less than that of the first region 34A. The thickness of the second region 34B is the horizontal thickness of the second region 34B based on the sidewall of the gate structure 25. The second region 34B is connected to the first region 34A on the bottom wall side of the gate structure 25, and is connected to the body region 22 on the first main surface 3 side.

[0240] That is, the second region 34B electrically connects the corresponding well region 30 to the body region 22. This prevents the well region 30 from being electrically floating, and improves the electrical response characteristics of the well region 30.

[0241] The third region 34C is a portion that extends in a layer shape along the first main surface 3 in the surface layer portion of the first main surface 3 and is exposed from the first main surface 3. In other words, the third region 34C forms the upper end portion of the contact region 34. In this embodiment, the upper end portion of the third region 34C is exposed from the sidewall of the trench 26 at the opening end of the trench 26.

[0242] The third region 34C is formed integrally with the third region 34C of the adjacent contact region 34. That is, the multiple contact regions 34 are electrically connected to each other via the multiple third regions 34C. The third region 34C has a thickness (depth) less than the thickness (depth) of the body region 22, and faces the semiconductor layer 7 with a part (bottom) of the body region 22 interposed therebetween. The thickness of the third region 34C is the thickness of the third region 34C in the vertical direction Z, with the first main surface 3 as the reference.

[0243] The third region 34C has a bottom located on the bottom side of the body region 22 with respect to the height position of the electrode surfaces of the multiple buried electrodes 28. Specifically, the third region 34C has a portion located on the bottom wall side of the multiple trenches 26 with respect to the electrode surfaces of the multiple buried electrodes 28, and a portion located on the first main surface 3 side with respect to the electrode surfaces of the multiple buried electrodes 28. The third region 34C has a portion facing the corresponding buried electrode 28 with the corresponding insulating film 27 interposed therebetween.

[0244] The thickness of the third region 34C is greater than the thickness of the second region 34B. The thickness of the third region 34C may be approximately equal to the thickness of the first region 34A. The thickness of the third region 34C may be greater or less than the thickness of the first region 34A. The thickness of the third region 34C is less than the thickness (depth) of the source region 33. The third region 34C has a bottom located closer to the first main surface 3 than the bottom of the source region 33.

[0245] The thickness of the third region 34C may be greater than the thickness of the source region 33. The thickness of the third region 34C may be less than the thickness between the bottom of the body region 22 and the bottom of the third region 34C. The thickness of the third region 34C may be less than the thickness between the bottom of the body region 22 and the bottom of the third region 34C.

[0246] The semiconductor device 1A includes a p-type outer well region 35 formed in a surface layer portion of the first main surface 3 in the peripheral region 21 (the peripheral portion of the first main surface 3). The outer well region 35 is also a form of impurity region 9. A source potential is applied to the outer well region 35. The outer well region 35 has a p-type impurity concentration higher than the n-type impurity concentration of the semiconductor layer 7. The p-type impurity concentration of the outer well region 35 may be higher or lower than the p-type impurity concentration of the body region 22.

[0247] The p-type impurity concentration of the outer well region 35 is lower than the p-type impurity concentration of the contact region 34. The p-type impurity concentration of the outer well region 35 is lower than the p-type impurity concentration of the first well region 31. The p-type impurity concentration of the outer well region 35 may be higher or lower than the p-type impurity concentration of the second well region 32.

[0248] The outer well region 35 is formed in a surface layer portion of the semiconductor layer 7 and extends in a layered manner along the first main surface 3. The outer well region 35 is formed at an interval from the periphery of the first main surface 3 toward the plurality of gate structures 25. The outer well region 35 extends in a strip shape along the periphery of the first main surface 3 (the periphery of the active region 20) in a plan view.

[0249] In this embodiment, the outer well region 35 is formed in a polygonal ring shape (a quadrangular ring shape in this embodiment) having four sides parallel to the periphery of the first main surface 3 in a plan view, and surrounds the inner portion (active region 20) of the first main surface 3. In other words, the outer well region 35 collectively surrounds the multiple gate structures 25.

[0250] The outer well region 35 may have an edge portion that connects the band-like portion extending in the first direction X and the band-like portion extending in the second direction Y in an arc shape (preferably a quadrant arc shape). The outer well region 35 has an inner edge portion on the side of the multiple gate structures 25 and an outer edge portion on the peripheral side of the first main surface 3. The inner edge portion of the outer well region 35 defines the boundary between the active region 20 and the outer periphery region 21.

[0251] The inner edge of the outer well region 35 is connected to the ends of the multiple gate structures 25 in a portion extending in the first direction X. The inner edge of the outer well region 35 faces the buried electrode 28 with the insulating film 27 interposed therebetween.

[0252] The inner edge of the outer well region 35 may be located closer to the inner side of the plurality of gate structures 25 than the ends of the plurality of gate structures 25. The inner edge of the outer well region 35 may have a portion located in a region between the plurality of gate structures 25 and connected to the body region 22. The outer edge of the outer well region 35 is formed at a distance from the periphery of the first main surface 3 and extends approximately parallel to the inner edge of the outer well region 35.

[0253] The outer well region 35 may have a width greater than 0 μm and less than 300 μm. The width of the outer well region 35 may have a value belonging to at least one of the ranges of greater than 0 μm and less than 25 μm, 25 μm to 50 μm, 50 μm to 75 μm, 75 μm to 100 μm, 100 μm to 125 μm, 125 μm to 150 μm, 150 μm to 175 μm, 175 μm to 200 μm, 200 μm to 225 μm, 225 μm to 250 μm, 250 μm to 275 μm, and 275 μm to 300 μm.

[0254] The outer well region 35 is formed at a distance from the buffer layer 8 (high concentration portion 8b) toward the first main surface 3, and faces the buffer layer 8 across a part of the semiconductor layer 7. The outer well region 35 may be formed at a distance from the depth position of the intermediate portion of the semiconductor layer 7 toward the first main surface 3, or may have a portion located on the buffer layer 8 (high concentration portion 8b) side relative to the depth position of the intermediate portion of the semiconductor layer 7.

[0255] In this embodiment, the outer well region 35 is formed at an interval toward the first main surface 3 from the depth position of the bottom walls of the plurality of gate structures 25. The depth of the outer well region 35 may be greater or smaller than the depth of the body region 22.

[0256] The outer well region 35 may have a portion located on the buffer layer 8 (high concentration portion 8b) side with respect to the depth position of the bottom walls of the plurality of gate structures 25. In this case, the outer well region 35 may be connected to either one or both of the first well region 31 and the second well region 32.

[0257] The outer well region 35 forms a pn junction with the semiconductor layer 7. The outer well region 35 spreads a depletion layer in the semiconductor layer 7 when a reverse bias voltage is applied. The depletion layer in the outer well region 35 spreads in the horizontal and thickness directions and integrates with the depletion layers spreading from the body region 22 and the well region 30. The outer well region 35 expands the depletion layers spreading from the body region 22 and the well region 30 toward the peripheral edge of the first main surface 3, thereby reducing the electric field intensity (electric field concentration) in the peripheral portion (outer peripheral region 21) of the first main surface 3.

[0258] The semiconductor device 1A includes a p-type outer contact region 36 formed in a surface layer portion of the outer well region 35. The outer contact region 36 has a p-type impurity concentration higher than the p-type impurity concentration of the outer well region 35. The p-type impurity concentration of the outer contact region 36 is higher than the p-type impurity concentration of the body region 22.

[0259] The p-type impurity concentration of the outer contact region 36 may be approximately equal to the p-type impurity concentration of the contact region 34. The p-type impurity concentration of the outer contact region 36 may be higher or lower than the p-type impurity concentration of the contact region 34.

[0260] The outer contact region 36 is formed at a distance from the bottom of the outer well region 35 toward the first main surface 3, and faces the semiconductor layer 7 across a part of the outer well region 35. The outer contact region 36 extends in a strip shape along the outer well region 35 (active region 20) in a plan view.

[0261] In this embodiment, the outer contact region 36 is formed in a polygonal ring shape (a square ring shape in this embodiment) having four sides parallel to the periphery of the first main surface 3 in a plan view, and surrounds the multiple gate structures 25 (active regions 20). The outer contact region 36 may have an edge portion that connects the strip-like extending portion in the first direction X and the strip-like extending portion in the second direction Y in an arc shape (preferably a quadrant arc shape).

[0262] The semiconductor device 1A may include a plurality of outer contact regions 36 arranged at intervals along the extension direction of the outer well region 35 so as to surround the plurality of gate structures 25. In this case, the plurality of outer contact regions 36 may each extend in a strip shape along the extension direction of the outer well region 35.

[0263] The outer contact region 36 has a width less than the width of the outer well region 35, and is formed within the outer well region 35. The outer contact region 36 is formed in the inner part of the outer well region 35 with a gap between both edges of the outer well region 35. The outer contact region 36 is biased toward the outer edge of the outer well region 35 relative to the central part of the outer well region 35. The outer contact region 36 may be formed in the central part of the outer well region 35.

[0264] The semiconductor device 1A includes at least one (in this embodiment, multiple) p-type field region 37 formed in the surface layer portion of the first main surface 3 in the peripheral region 21 (the peripheral portion of the first main surface 3). The multiple field regions 37 are also a form of impurity region 9. The multiple field regions 37 may be formed in an electrically floating state. The multiple field regions 37 may be fixed to the source potential.

[0265] The number of field regions 37 is arbitrary. The number of field regions 37 may be 1 or more and 20 or less. The number of field regions 37 may be a value belonging to at least one of the ranges of 1 or more and 5 or less, 5 or more and 10 or less, 10 or more and 15 or less, and 15 or more and 20 or less. The number of field regions 37 is typically 1 or more and 8 or less. In this embodiment, the semiconductor device 1A includes six field regions 37.

[0266] The field regions 37 are formed at intervals from one another in the surface layer portion of the semiconductor layer 7. The field regions 37 are formed at intervals from the periphery of the first main surface 3 in a region between the periphery of the first main surface 3 and the gate structures 25 (active regions 20). Specifically, the field regions 37 are formed in a region between the periphery of the first main surface 3 and the outer well region 35.

[0267] The field regions 37 extend in a strip shape along the gate structures 25 (active regions 20) in a plan view. Specifically, the field regions 37 extend in a strip shape along the outer well region 35. Each of the field regions 37 has a portion extending in a strip shape in the first direction X and a portion extending in a strip shape in the second direction Y.

[0268] In this embodiment, the plurality of field regions 37 are formed in polygonal ring shapes (square ring shapes in this embodiment) surrounding the plurality of gate structures 25 (active regions 20) in plan view. The plurality of field regions 37 may have edge portions that connect the strip-like extending portion in the first direction X and the strip-like extending portion in the second direction Y in an arc shape (preferably a quadrant arc shape).

[0269] The plurality of field regions 37 are formed at intervals from the buffer layer 8 (high concentration portion 8 b) toward the first main surface 3, and face the buffer layer 8 across a part of the semiconductor layer 7. The plurality of field regions 37 may be formed at intervals from a depth position of the intermediate portion of the semiconductor layer 7 toward the first main surface 3, or may have a portion located on the buffer layer 8 (high concentration portion 8 b) side relative to the depth position of the intermediate portion of the semiconductor layer 7.

[0270] In this embodiment, the field regions 37 are formed at intervals from the depth position of the bottom walls of the gate structures 25 toward the first main surface 3. The depth of the field regions 37 may be greater or smaller than the depth of the body region 22. The field regions 37 may have a portion located on the buffer layer 8 (high concentration portion 8b) side relative to the depth position of the bottom walls of the gate structures 25.

[0271] The plurality of field regions 37 form pn junctions with the semiconductor layer 7. The plurality of field regions 37 spread a depletion layer in the semiconductor layer 7 when a reverse bias voltage is applied. The depletion layers in the plurality of field regions 37 spread in the horizontal direction and the thickness direction, and merge with the depletion layers spreading from the body region 22 and the outer well region 35.

[0272] The multiple field regions 37 expand the depletion layer extending from the body region 22 and the outer well region 35 toward the peripheral side of the first main surface 3, thereby alleviating the electric field strength (electric field concentration) in the peripheral portion (peripheral region 21) of the first main surface 3.

[0273] The width, depth, spacing, p-type impurity concentration, etc. of the multiple field regions 37 are arbitrary and can take various values ​​depending on the electric field to be relaxed. The width of the multiple field regions 37 may be substantially uniform or non-uniform. The width of the multiple field regions 37 may gradually increase toward the periphery of the first main surface 3. The width of the multiple field regions 37 may gradually decrease toward the periphery of the first main surface 3.

[0274] The depth of the multiple field regions 37 may be substantially constant or non-uniform. The depth of the multiple field regions 37 may gradually increase toward the peripheral edge of the first main surface 3. The depth of the multiple field regions 37 may gradually decrease toward the peripheral edge of the first main surface 3. Of course, the multiple field regions 37 may have a relatively shallow portion and a deep portion that is deeper than the shallow portion. The shallow portion may be formed on the inward side, and the deep portion may be formed on the peripheral edge side. The shallow portion may be formed on the peripheral edge side, and the deep portion may be formed on the inward side.

[0275] The spacing between the multiple field regions 37 may be substantially uniform or non-uniform. The spacing between the multiple field regions 37 may gradually increase toward the peripheral edge of the first main surface 3. The spacing between the multiple field regions 37 may gradually decrease toward the peripheral edge of the first main surface 3.

[0276] The p-type impurity concentrations of the multiple field regions 37 may be substantially constant or non-uniform. The p-type impurity concentrations of the multiple field regions 37 may gradually increase toward the periphery of the first main surface 3. The p-type impurity concentrations of the multiple field regions 37 may gradually decrease toward the periphery of the first main surface 3.

[0277] The plurality of field regions 37 may have a p-type impurity concentration that is approximately equal to the p-type impurity concentration of the plurality of body regions 22. The p-type impurity concentration of the plurality of field regions 37 may be higher or lower than the p-type impurity concentration of the plurality of body regions 22.

[0278] The plurality of field regions 37 may have a p-type impurity concentration that is approximately equal to the p-type impurity concentration of the contact region 34. The p-type impurity concentration of the plurality of field regions 37 may be higher or lower than the p-type impurity concentration of the contact region 34.

[0279] The plurality of field regions 37 may have a p-type impurity concentration that is approximately equal to the p-type impurity concentration of the outer well region 35. The p-type impurity concentration of the plurality of field regions 37 may be higher or lower than the p-type impurity concentration of the outer well region 35.

[0280] The semiconductor device 1A includes a main surface insulating film 38 that selectively covers the first main surface 3. The main surface insulating film 38 may also be referred to as a "surface insulating film," an "outer surface insulating film," or the like. The main surface insulating film 38 may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. The main surface insulating film 38 may include a silicon oxide film containing an oxide of the semiconductor layer 7. The main surface insulating film 38 may also include a silicon oxide film containing an oxide other than the oxide of the semiconductor layer 7.

[0281] The main surface insulating film 38 selectively covers the first main surface 3 in the active region 20 and the peripheral region 21. The main surface insulating film 38 covers the first main surface 3 in the active region 20 in a film-like manner. The main surface insulating film 38 is connected to the insulating films 27 of the multiple gate structures 25, and exposes the buried electrodes 28.

[0282] The main surface insulating film 38 covers the outer well region 35, the outer contact region 36, and the plurality of field regions 37 in the peripheral region 21. The main surface insulating film 38 is continuous with the first to fourth side surfaces 5A to 5D. The main surface insulating film 38 may be formed at intervals inward from the first to fourth side surfaces 5A to 5D, exposing the peripheral edge portion of the first main surface 3.

[0283] The main surface insulating film 38 may have a thickness of 10 nm to 250 nm. The thickness of the main surface insulating film 38 may have a value belonging to at least one of the ranges of 10 nm to 25 nm, 25 nm to 50 nm, 50 nm to 75 nm, 75 nm to 100 nm, 100 nm to 125 nm, 125 nm to 150 nm, 150 nm to 175 nm, 175 nm to 200 nm, 200 nm to 225 nm, and 225 nm to 250 nm.

[0284] The semiconductor device 1A includes one or more (one in this embodiment) gate wirings 39 arranged on the first main surface 3 in the peripheral region 21. The gate wiring 39 applies a gate potential to the multiple gate structures 25. The gate wiring 39 may include either or both of p-type conductive polysilicon and n-type conductive polysilicon. The gate wiring 39 preferably has the same conductivity type as the buried electrode 28.

[0285] The gate wiring 39 is disposed on the main surface insulating film 38. The gate wiring 39 is selectively routed on the main surface insulating film 38 at intervals from the periphery of the first main surface 3 toward the plurality of gate structures 25, and faces the outer well region 35 with the main surface insulating film 38 in between.

[0286] The gate wiring 39 extends in a strip shape along the plurality of gate structures 25. The gate wiring 39 has a portion that extends in a strip shape in the first direction X and a portion that extends in a strip shape in the second direction Y. The gate wiring 39 extends in a strip shape so as to intersect (specifically, perpendicular to) the ends (both ends in this embodiment) of the plurality of gate structures 25.

[0287] In this embodiment, the gate wiring 39 is formed in an endless polygonal ring shape (e.g., a square ring shape) having four sides parallel to the periphery of the first main surface 3, and surrounds the multiple gate structures 25 (active regions 20). Of course, the gate wiring 39 may also be formed in a strip shape with ends. The gate wiring 39 may have an edge portion that connects the strip-like portion extending in the first direction X and the strip-like portion extending in the second direction Y in a plan view into an arc shape (preferably a quarter arc shape).

[0288] The gate wiring 39 has an inner edge portion on the inward side of the first main surface 3 and an outer edge portion on the peripheral side of the first main surface 3. The inner edge portion of the gate wiring 39 covers the ends (both ends in this embodiment) of the multiple gate structures 25 and is mechanically and electrically connected to the multiple gate structures 25. Specifically, the inner edge portion of the gate wiring 39 is mechanically and electrically connected to the multiple buried electrodes 28. In this embodiment, the inner edge portion of the gate wiring 39 is formed integrally with the multiple buried electrodes 28 as an extension portion of the multiple buried electrodes 28.

[0289] The inner edge of the gate wiring 39 has a portion located in a region between the plurality of gate structures 25, and faces either one or both of the body region 22 and the outer well region 35 across the main surface insulating film 38 (main surface insulating film 38). The inner edge of the gate wiring 39 is formed at a distance from the outermost source regions 33 and contact regions 34 on the peripheral side of the first main surface 3.

[0290] The outer edge of the gate wiring 39 is disposed on the main surface insulating film 38 at a distance from the plurality of field regions 37 toward the plurality of gate structures 25. With this configuration, the gate wiring 39 is prevented from blocking the dispersion path of the electric field, and the plurality of field regions 37 appropriately distributes the electric field (electric force lines).

[0291] The outer edge of the gate wiring 39 is formed at a distance from the outer edge of the outer well region 35 towards the plurality of gate structures 25. The outer edge of the gate wiring 39 is formed at a distance from the inner edge of the outer contact region 36 towards the plurality of gate structures 25, and faces the outer well region 35 with the main surface insulating film 38 sandwiched therebetween.

[0292] The semiconductor device 1A may include a plurality of gate wirings 39. In this case, the plurality of gate wirings 39 may be arranged at least at both ends of the plurality of gate structures 25. One of the gate wirings 39 may have a portion extending in a strip shape in the first direction X and intersect (specifically, perpendicular to) one end of the plurality of gate structures 25. The other gate wiring 39 may have a portion extending in a strip shape in the first direction X and intersect (specifically, perpendicular to) the other end of the plurality of gate structures 25. Of course, the plurality of gate wirings 39 may have a portion extending in the second direction Y.

[0293] The semiconductor device 1A includes the aforementioned interlayer film 10 covering the first main surface 3. In this embodiment, the interlayer film 10 selectively covers the first main surface 3 in the active region 20 and the peripheral region 21 via a main surface insulating film 38. The interlayer film 10 covers the multiple gate structures 25 in the active region 20 in a film-like manner. The interlayer film 10 covers the buried electrodes 28 and electrically insulates the buried electrodes 28.

[0294] In the peripheral region 21, the interlayer film 10 covers the outer well region 35, the outer contact region 36, and the plurality of field regions 37 via the main surface insulating film 38. The interlayer film 10 directly covers the gate wiring 39 in the peripheral region 21. The interlayer film 10 is continuous with the first to fourth side surfaces 5A to 5D. The interlayer film 10 may be formed at intervals inward from the first to fourth side surfaces 5A to 5D, exposing the peripheral edge portion of the first main surface 3.

[0295] The interlayer film 10 has a thickness greater than that of the main surface insulating film 38. The thickness of the interlayer film 10 may be 0.1 μm or more and 5 μm or less. The thickness of the interlayer film 10 may be 0.1 μm or more and 0.5 μm or less, 0.5 μm or more and 1 μm or less, 1 μm or more and 1.5 μm or less, 1.5 μm or more and 2 μm or less, 2 μm or more and 2.5 μm or less, 2.5 μm or more and 3 μm or less, 3 μm or more and 3.5 μm or less, 3.5 μm or more and 4 μm or less, 4 μm or more and 4.5 μm or less, or 4.5 μm or more and 5 μm or less.

[0296] The semiconductor device 1A includes a plurality of source openings 40 formed in the interlayer film 10 in the active region 20. The plurality of source openings 40 penetrate the main surface insulating film 38 and the interlayer film 10, and expose the plurality of mesa portions 29 (regions between the plurality of gate structures 25). The plurality of source openings 40 are formed in a one-to-one correspondence with the plurality of mesa portions 29. The plurality of source openings 40 each extend in a strip shape in the second direction Y, following the extension direction of the corresponding mesa portion 29.

[0297] The plurality of source openings 40 expose the plurality of source regions 33 and the plurality of contact regions 34 in the corresponding mesa portion 29. The plurality of source openings 40 may each have an opening end that is curved in an arc shape.

[0298] The multiple source openings 40 may be formed in a one-to-many correspondence with the corresponding mesa portions 29. In this case, the multiple source openings 40 may be formed at intervals along the corresponding mesa portions 29. In this case, the multiple source openings 40 may be formed in a quadrangular shape, a rectangular shape (strip shape), a circular shape, or the like in a plan view.

[0299] The semiconductor device 1A includes one or more (multiple in this embodiment) gate openings 41 formed in the interlayer film 10 in the peripheral region 21. The multiple gate openings 41 penetrate the interlayer film 10 and selectively expose the gate wiring 39. In this embodiment, the multiple gate openings 41 extend in a strip shape following the extension direction of the gate wiring 39.

[0300] The plurality of gate openings 41 may be formed at intervals along the extension direction of the gate wiring 39. The plurality of gate openings 41 may be formed in a polygonal or circular shape in a plan view. For example, the plurality of gate structures 25 may be formed in a quadrangular or hexagonal shape in a plan view.

[0301] The plurality of gate openings 41 may have a portion extending in a band shape in the first direction X in a plan view and a portion extending in a band shape in the second direction Y. The plurality of gate openings 41 may have an edge portion that connects the portion extending in a band shape in the first direction X and the portion extending in a band shape in the second direction Y in a plan view in an arc shape (preferably a quarter arc shape).

[0302] The semiconductor device 1A includes at least one outer opening 42 (one in this embodiment) formed in the interlayer film 10 in the peripheral region 21. The outer opening 42 is formed at a distance from the gate wiring 39 toward the peripheral edge of the first main surface 3. The outer opening 42 penetrates the main surface insulating film 38 and the interlayer film 10, exposing the outer contact region 36.

[0303] The outer opening 42 has a width less than the width of the outer contact region 36 and is spaced apart from the inner and outer edges of the outer contact region 36 to expose an inner portion of the outer contact region 36. The outer opening 42 may expose the outer well region 35.

[0304] In this embodiment, the outer opening 42 extends in a band shape following the extension direction of the outer contact region 36. In this embodiment, the outer opening 42 is formed in a polygonal ring shape (a quadrangular ring shape in this embodiment) having four sides parallel to the periphery of the first main surface 3 in a plan view, and surrounds the multiple gate structures 25 (active regions 20). The outer contact region 36 may have an edge portion that connects the band-like extending portion in the first direction X and the band-like extending portion in the second direction Y in an arc shape (preferably a quadrant arc shape).

[0305] The semiconductor device 1A may have a plurality of outer openings 42. In this case, the plurality of outer openings 42 may be formed at intervals following the extension direction of the outer contact region 36. The plurality of outer openings 42 may each extend in a strip shape following the extension direction of the outer contact region 36.

[0306] The semiconductor device 1A includes the aforementioned first electrode 12 disposed on the first main surface 3. In this embodiment, the first electrode 12 includes a source electrode 43, a source finger electrode 44, a gate electrode 45, and a gate finger electrode 46. The source electrode 43 may also be referred to as a "first main surface electrode," a "first terminal (electrode)," a "first pad (electrode)," etc. The gate electrode 45 may also be referred to as a "second main surface electrode," a "second terminal (electrode)," a "second pad (electrode)," etc.

[0307] The source electrode 43 is disposed on the first main surface 3 via the interlayer film 10. In this embodiment, the source electrode 43 includes a main source electrode 43a, a first sub-source electrode 43b, and a second sub-source electrode 43c.

[0308] The main source electrode 43a has a relatively large planar area and forms the main body of the source electrode 43. In this embodiment, the main source electrode 43a is formed in a polygonal shape (a quadrilateral shape in this embodiment) having four sides parallel to the periphery of the first main surface 3 in a plan view, and is located closer to the second side surface 5B than the center of the first main surface 3.

[0309] The first sub-source electrode 43b has a planar area smaller than that of the main source electrode 43a, and is drawn in a strip shape (rectangular) from one end of the main source electrode 43a in the second direction Y (the end on the first side surface 5A side) toward the fourth side surface 5D. The second sub-source electrode 43c has a planar area smaller than that of the main source electrode 43a, and is drawn in a strip shape (rectangular) from the other end of the main source electrode 43a in the second direction Y (the end on the third side surface 5C side) toward the fourth side surface 5D, and faces the first sub-source electrode 43b in the second direction Y.

[0310] The planar area of ​​the second sub-source electrode 43c may be approximately equal to the planar area of ​​the first sub-source electrode 43b. The planar area of ​​the second sub-source electrode 43c may be larger or smaller than the planar area of ​​the first sub-source electrode 43b. Either or both of the first sub-source electrode 43b and the second sub-source electrode 43c may be used as a monitor electrode for monitoring current.

[0311] The main source electrode 43 a, the first sub-source electrode 43 b, and the second sub-source electrode 43 c do not necessarily have to be integrally formed, and at least one or all of the main source electrode 43 a, the first sub-source electrode 43 b, and the second sub-source electrode 43 c may be physically separated.

[0312] The source electrode 43 does not necessarily have to have both the first sub-source electrode 43b and the second sub-source electrode 43c at the same time. The source electrode 43 may have only one of the first sub-source electrode 43b and the second sub-source electrode 43c. The source electrode 43 may be composed of only the main source electrode 43a, and may not have both the first sub-source electrode 43b and the second sub-source electrode 43c.

[0313] The source electrode 43 collectively covers the region of the interlayer film 10 where the plurality of source openings 40 are formed, and extends into the source openings 40 from above the interlayer film 10. The source electrode 43 has a portion that covers the interlayer film 10 and a portion that covers the first main surface 3 within the source openings 40.

[0314] The source electrode 43 is electrically insulated from the plurality of gate structures 25 by the interlayer film 10 and is electrically connected to the first main surface 3 within the plurality of source openings 40. Specifically, the source electrode 43 is mechanically and electrically connected to the plurality of source regions 33 and the plurality of contact regions 34 within the plurality of source openings 40.

[0315] The peripheral portion of the source electrode 43 may be drawn from the active region 20 to the peripheral region 21 and may face a part of the gate wiring 39 across the interlayer film 10. The peripheral portion of the source electrode 43 may have a portion facing the outer well region 35 via the gate wiring 39 and the main surface insulating film 38.

[0316] The peripheral edge of the source electrode 43 is formed at a distance from the plurality of field regions 37 toward the plurality of gate structures 25. Specifically, the peripheral edge of the source electrode 43 is formed at a distance from the outer edge of the outer well region 35 toward the plurality of gate structures 25. The peripheral edge of the source electrode 43 is formed at a distance from the inner edge of the outer contact region 36 toward the plurality of gate structures 25.

[0317] The peripheral portion of the source electrode 43 is formed at a distance from the outer edge of the gate wiring 39 toward the inner edge of the gate wiring 39. The peripheral portion of the source electrode 43 may be formed at a distance from the middle of the gate wiring 39 toward the inner edge of the gate wiring 39. The peripheral portion of the source electrode 43 may be disposed on the inward side of the first main surface 3 from the inner edge of the gate wiring 39.

[0318] The gate electrode 45 is disposed on the first main surface 3 at a distance from the source electrode 43. The gate electrode 45 is disposed in a region on the fourth side surface 5D side of the main source electrode 43a, and faces the center of the fourth side surface 5D and the main source electrode 43a in the first direction X. The gate electrode 45 is interposed in a region between the first sub-source electrode 43b and the second sub-source electrode 43c, and faces both the first sub-source electrode 43b and the second sub-source electrode 43c in the second direction Y.

[0319] The gate electrode 45 is formed in a polygonal shape (a quadrilateral shape in this embodiment) having four sides parallel to the periphery of the first main surface 3 in a plan view. The gate electrode 45 has a planar area smaller than the planar area of ​​the source electrode 43. The gate electrode 45 has a planar area smaller than the planar area of ​​the main source electrode 43a. The gate electrode 45 may also have a planar area smaller than the planar area of ​​the first sub-source electrode 43b (second sub-source electrode 43c).

[0320] The gate electrode 45 faces the outer well region 35 across the interlayer film 10. In this embodiment, the gate electrode 45 is formed spaced apart from the ends (both ends) of the plurality of gate structures 25. In other words, the gate electrode 45 does not face the plurality of gate structures 25 in the stacking direction. The gate structure 25 may have a portion that faces a part (for example, an end) of the gate structure 25 across the interlayer film 10.

[0321] In this embodiment, the gate electrode 45 does not have a connection to the gate wiring 39. Of course, the gate electrode 45 may be mechanically and electrically connected to the gate wiring 39 via one or more gate openings 41.

[0322] The gate finger electrodes 46 are extended from the gate electrode 45 onto the first main surface 3 and transmit the gate potential applied to the gate electrode 45 to other regions. The gate finger electrodes 46 are extended onto a portion of the interlayer film 10 that covers the gate wiring 39 and extend in a strip shape along the periphery of the first main surface 3 and in a region between the source electrodes 43. The gate finger electrodes 46 have a portion that extends in a strip shape in the first direction X and a portion that extends in a strip shape in the second direction Y in plan view.

[0323] In this embodiment, the gate finger electrode 46 is formed in a strip shape with four sides parallel to the periphery of the first main surface 3, and surrounds the source electrode 43. The gate finger electrode 46 is disposed closer to the periphery of the first main surface 3 than both ends of the multiple gate structures 25. The gate finger electrode 46 may have an edge portion that connects the strip-like extending portion in the first direction X and the strip-like extending portion in the second direction Y in an arc shape (preferably a quarter arc shape).

[0324] The gate finger electrodes 46 extend from above the interlayer film 10 into the plurality of gate openings 41, and are mechanically and electrically connected to the gate wiring 39 within the plurality of gate openings 41. As a result, the gate finger electrodes 46 transmit the gate potential applied to the gate electrode 45 to the plurality of gate structures 25.

[0325] The gate finger electrode 46 has an inner edge portion on the inward side of the first main surface 3 and an outer edge portion on the peripheral side of the first main surface 3. The inner edge portion of the gate finger electrode 46 is formed at a distance from the ends of the multiple gate structures 25 toward the peripheral side of the first main surface 3. In other words, the gate finger electrode 46 does not face the multiple gate structures 25 in the stacking direction.

[0326] The inner edge of the gate finger electrode 46 is disposed on the gate wiring 39 and faces the peripheral edge of the source electrode 43 in the horizontal direction. The outer edge of the gate finger electrode 46 is drawn out from above the gate wiring 39 toward the peripheral edge of the first main surface 3 and is disposed on the interlayer film 10 in a region outside the gate wiring 39. In other words, the outer edge of the gate finger electrode 46 does not face the gate wiring 39 in the stacking direction.

[0327] The outer edge of the gate finger electrode 46 is arranged at a distance inward of the first main surface 3 from the innermost field region 37. The outer edge of the gate finger electrode 46 is arranged at a distance inward of the first main surface 3 from the outer edge of the outer well region 35, and faces the outer well region 35 across the main surface insulating film 38 and the interlayer film 10. The outer edge of the gate finger electrode 46 is arranged on the peripheral side of the first main surface 3 with respect to the outer edge of the outer well region 35, and may face the semiconductor layer 7 in the stacking direction.

[0328] The semiconductor device 1A includes source finger electrodes 44 extending from the source electrode 43 onto the first main surface 3. The source finger electrodes 44 transmit the source potential applied to the source electrode 43 to other regions. The source finger electrodes 44 extend from the source electrode 43 onto a portion of the interlayer film 10 that covers the outer contact region 36.

[0329] The source finger electrodes 44 are routed in a strip-like shape around the periphery of the first main surface 3 and in a region between the source electrodes 43, with a gap between them and the gate electrode 45 and the gate finger electrodes 46. The source finger electrodes 44 have a portion extending in a strip-like shape in the first direction X and a portion extending in a strip-like shape in the second direction Y in plan view.

[0330] In this embodiment, the source finger electrode 44 is formed in a polygonal ring shape (quadrature ring) having four sides parallel to the periphery of the first main surface 3, and surrounds the source electrode 43 and the gate finger electrode 46. The outer well region 35 may have an edge portion that connects the strip-like extending portion in the first direction X and the strip-like extending portion in the second direction Y in an arc shape (preferably a quadrant arc shape).

[0331] The source finger electrodes 44 extend into the outer openings 42 from above the interlayer film 10 and are mechanically and electrically connected to the outer contact regions 36 within the outer openings 42. As a result, the source finger electrodes 44 transmit the source potential applied to the source electrode 43 to the outer contact regions 36 (outer well regions 35).

[0332] Source finger electrodes 44 have inner edge portions on the inward side of first main surface 3 and outer edge portions on the peripheral side of first main surface 3. The inner edge portions of source finger electrodes 44 are arranged at a distance from gate finger electrodes 46 on the peripheral side of first main surface 3, and face gate finger electrodes 46 in the horizontal direction.

[0333] The inner edge of the source finger electrode 44 is formed at a distance from the middle of the outer contact region 36 toward the periphery of the first main surface 3. The inner edge of the source finger electrode 44 may be disposed on the outer well region 35 or on the outer contact region 36.

[0334] The outer edge of source finger electrode 44 is drawn out from above outer contact region 36 toward the periphery of first main surface 3, and is disposed on interlayer film 10 in a region outside outer contact region 36. The outer edge of source finger electrode 44 is disposed at a distance from innermost field region 37 toward the inward side of first main surface 3.

[0335] The outer edge of source finger electrode 44 is disposed at a distance from the outer edge of outer well region 35 toward the inside of first main surface 3, and faces outer well region 35 across main surface insulating film 38 and interlayer film 10. The outer edge of source finger electrode 44 may be drawn out from the outer edge of outer well region 35 toward the periphery of first main surface 3, and faces semiconductor layer 7 across main surface insulating film 38 and interlayer film 10.

[0336] The semiconductor device 1A includes the above-described top film 13 that selectively covers the first main surface 3. The top film 13 has a portion that selectively covers the source electrode 43, a portion that selectively covers the gate electrode 45, a portion that selectively covers the gate finger electrode 46, a portion that selectively covers the source finger electrode 44, and a portion that selectively covers the interlayer film 10. The top film 13 covers the entire area of ​​the gate finger electrode 46 and the entire area of ​​the source finger electrode 44.

[0337] The top film 13 has a source inner edge portion on the source electrode 43 side, a gate inner edge portion on the gate electrode 45 side, and an outer edge portion on the peripheral side of the first main surface 3. The source inner edge portion of the top film 13 covers the peripheral edge and inner portion of the source electrode 43 and defines one or more (multiple in this embodiment) source pad openings 47 as pad openings 14 that selectively expose the source electrode 43.

[0338] The multiple source pad openings 47 include a first source pad opening 47 that selectively exposes the main source electrode 43a, a second source pad opening 47 that selectively exposes the first sub-source electrode 43b, and a third source pad opening 47 that selectively exposes the second sub-source electrode 43c.

[0339] The plurality of source pad openings 47 are each defined in a quadrangular shape in a plan view. The second source pad opening 47 and the third source pad opening 47 each have a planar area smaller than the planar area of ​​the first source pad opening 47.

[0340] The inner edge of the gate electrode 45 covers the peripheral edge of the gate electrode 45, and defines a gate pad opening 48 as a pad opening 14 that selectively exposes the inner portion of the gate electrode 45. The outer edge of the top film 13 is disposed on the interlayer film 10 at a distance from the peripheral edge of the first main surface 3, and exposes the peripheral edge of the interlayer film 10.

[0341] The gate pad opening 48 is defined in a rectangular shape in a plan view, and has a plan area smaller than the plan area of ​​the first source pad opening 47. The plan area of ​​the gate pad opening 48 may be smaller or larger than the plan area of ​​the second source pad opening 47 (third source pad opening 47).

[0342] The top film 13 has a laminated structure including, laminated in this order, the inorganic film 15 and the organic film 16. The top film 13 does not necessarily have to have a laminated structure including the inorganic film 15 and the organic film 16, and may have a single layer structure consisting of either the inorganic film 15 or the organic film 16.

[0343] The inorganic film 15 has a portion that selectively covers the source electrode 43, a portion that selectively covers the gate electrode 45, a portion that selectively covers the gate finger electrode 46, a portion that selectively covers the source finger electrode 44, and a portion that selectively covers the interlayer film 10. In this embodiment, the inorganic film 15 covers the entire area of ​​the gate finger electrode 46 and the entire area of ​​the source finger electrode 44.

[0344] The inorganic film 15 has a source inner edge portion on the source electrode 43 side, a gate inner edge portion on the gate electrode 45 side, and an outer edge portion on the peripheral side of the first main surface 3. The source inner edge portion of the inorganic film 15 selectively covers the peripheral edge and inner portion of the source electrode 43 and defines part of a plurality of source pad openings 47. The gate inner edge portion of the inorganic film 15 covers the peripheral edge of the gate electrode 45 and defines part of a gate pad opening 48. The outer edge portion of the inorganic film 15 is disposed on the interlayer film 10 at a distance from the peripheral edge of the first main surface 3, and exposes the peripheral edge portion of the interlayer film 10.

[0345] The inorganic film 15 has a portion that selectively covers the source electrode 43 across the inorganic film 15, a portion that selectively covers the gate electrode 45 across the inorganic film 15, a portion that selectively covers the gate finger electrode 46 across the inorganic film 15, a portion that selectively covers the source finger electrode 44 across the inorganic film 15, and a portion that selectively covers the interlayer film 10 across the inorganic film 15.

[0346] In this embodiment, organic film 16 covers the entire area of ​​gate finger electrode 46 and the entire area of ​​source finger electrode 44, sandwiching inorganic film 15. Organic film 16 has an inner edge portion of the source on the source electrode 43 side, an inner edge portion of the gate on the gate electrode 45 side, and an outer edge portion on the peripheral side of first main surface 3.

[0347] The source inner edge portion of the organic film 16 selectively covers the peripheral and inner portions of the source electrode 43 with the inorganic film 15 in between, and defines some of the source pad openings 47. In this embodiment, the source inner edge portion of the organic film 16 exposes the source inner edge portion of the inorganic film 15. The source inner edge portion of the organic film 16 may also cover the source inner edge portion of the inorganic film 15.

[0348] The gate inner edge portion of the organic film 16 covers the periphery of the gate electrode 45 with the inorganic film 15 sandwiched therebetween, and defines a part of the gate pad opening 48. In this embodiment, the gate inner edge portion of the organic film 16 exposes the gate inner edge portion of the inorganic film 15. The gate inner edge portion of the organic film 16 may also cover the gate inner edge portion of the inorganic film 15.

[0349] The outer edge of the organic film 16 is disposed on the interlayer film 10 at a distance from the periphery of the first main surface 3, exposing the periphery of the interlayer film 10. In this embodiment, the outer edge of the organic film 16 exposes the outer edge of the inorganic film 15. The outer edge of the organic film 16 may cover the outer edge of the inorganic film 15.

[0350] The semiconductor device 1A includes the aforementioned second electrode 17 disposed on the second main surface 4. In this embodiment, the second electrode 17 is formed as a drain electrode 49. The drain electrode 49 may also be referred to as a "third main surface electrode," a "third terminal (electrode)," a "third pad (electrode)," or the like.

[0351] The drain electrode 49 may cover the entire second main surface 4 so as to be continuous with the periphery (first to fourth side surfaces 5A to 5D) of the second main surface 4. The drain electrode 49 may be formed at a distance from the periphery of the second main surface 4, leaving the periphery of the second main surface 4 exposed.

[0352] The drain electrode 49 is mechanically and electrically connected to the semiconductor substrate 6. The drain electrode 49 forms an ohmic contact with the semiconductor substrate 6. The drain electrode 49, together with the source electrode 43, forms a current path through the chip 2 (the semiconductor substrate 6, the semiconductor layer 7, and the buffer layer 8).

[0353] A breakdown voltage that can be applied between the source electrode 43 and the drain electrode 49 (between the first main surface 3 and the second main surface 4) may be 500 V or more and 3000 V or less. The breakdown voltage may have a value belonging to at least one of the ranges of 500 V or more and 750 V or less, 750 V or more and 1000 V or less, 1000 V or more and 1250 V or less, 1250 V or more and 1500 V or less, 1500 V or more and 1750 V or less, 1750 V or more and 2000 V or less, 2000 V or more and 2250 V or less, 2250 V or more and 2500 V or less, and 2500 V or more and 3000 V or less.

[0354] As described above, the semiconductor device 1A includes an n-type (first conductivity type) semiconductor substrate 6 (substrate), an n-type semiconductor layer 7, an n-type buffer layer 8, a p-type (second conductivity type) body region 22 (impurity region 9), and a trench electrode type gate structure 25. The semiconductor substrate 6 has a first concentration C1. The semiconductor layer 7 has a second concentration C2 less than the first concentration C1 and is stacked on the semiconductor substrate 6.

[0355] The buffer layer 8 is interposed between the semiconductor substrate 6 and the semiconductor layer 7. The buffer layer 8 includes a low-concentration portion 8a and a high-concentration portion 8b. The low-concentration portion 8a has a third concentration C3 less than the first concentration C1 and is formed in a region on the semiconductor substrate 6 side. The high-concentration portion 8b has a fourth concentration C4 higher than the third concentration C3 and is formed in a region on the semiconductor layer 7 side. The body region 22 is formed in the semiconductor layer 7. The gate structure 25 is formed in the semiconductor layer 7.

[0356] This configuration provides a novel semiconductor device 1A. For example, in this semiconductor device 1A, holes (minority carriers) supplied from the body region 22 recombine with electrons (majority carriers) in the high-concentration region 8b, reducing the number of holes reaching the low-concentration region 8a. This reduces the number of holes reaching the boundary between the semiconductor substrate 6 and the buffer layer 8, suppressing bipolar degradation due to basal plane dislocation defects.

[0357] Such a configuration is effective in suppressing an increase in the thickness of the buffer layer 8 and an increase in the impurity concentration of the entire buffer layer 8. This appropriately increases the uniformity of the impurity concentration and layer thickness of the buffer layer 8, allowing holes and electrons to appropriately recombine in the high-concentration portion 8 b. In addition, the manufacturing cost of the buffer layer 8 is reduced.

[0358] For example, the fourth concentration C4 of the high-concentration portion 8b is 1×10 １７ cm －３ In the above cases, holes and electrons recombine in multiple modes in the high-concentration portion 8b, effectively shortening the lifetime. For example, the multiple modes include at least two of radiative recombination, direct recombination, Shockley Read Hall (SRH) recombination, and Auger recombination. When the fourth concentration C4 of the high-concentration portion 8b is 1×10 １８ cm －３ In these cases, radiative and Auger recombination are adequately promoted.

[0359] The recombination rate of holes and electrons before reaching the low-concentration portion 8 a may be 80% or more and 100% or less, and may have a value that falls within at least one of the ranges of 80% or more and 85% or less, 85% or more and 90% or less, 90% or more and 95% or less, and 95% or more and 100% or less.

[0360] The semiconductor substrate 6 may contain SiC. The semiconductor layer 7 may contain SiC. The buffer layer 8 may contain SiC. This configuration provides a semiconductor device 1A as a SiC semiconductor device having a novel layout. With this semiconductor device 1A, the electrical characteristics are appropriately improved due to the physical properties of SiC. In particular, in the case of SiC semiconductor devices, since they are used in a relatively high voltage environment, the effect of suppressing bipolar degradation is effective in improving the electrical characteristics.

[0361] The semiconductor substrate 6 may have an off angle θ. The off angle θ may be 10° or less. The off angle θ may be inclined toward the off direction. The off direction may be the a-axis direction.

[0362] The first concentration C1, the second concentration C2, the third concentration C3, and the fourth concentration C4 are adjusted as appropriate depending on the thickness of the buffer layer 8 and the electrical characteristics to be achieved. The third concentration C3 may be equal to or greater than the second concentration C2. The third concentration C3 may be less than the second concentration C2. The fourth concentration C4 may be higher than the second concentration C2. The fourth concentration C4 may be equal to or greater than the first concentration C1. The fourth concentration C4 may be less than the first concentration C1. With the fourth concentration C4 higher than the first concentration C1, holes can be efficiently recombined with electrons in the high-concentration portion 8b.

[0363] The buffer layer 8 may include a transition portion 8c. The transition portion 8c may have a gradient in which the concentration gradually increases from a third concentration C3 to a fourth concentration C4 in a region between the low-concentration portion 8a and the high-concentration portion 8b. With this configuration, holes that have passed through the high-concentration portion 8b can recombine with electrons in the transition portion 8c. Therefore, an increase in the impurity concentration of the entire buffer layer 8 is suppressed, and the number of holes that reach the low-concentration portion 8a can be reduced by the transition portion 8c.

[0364] The semiconductor layer 7 may be thicker than the buffer layer 8. The buffer layer 8 may have a thickness of 10 μm or less. The semiconductor layer 7 may have a thickness of 50 μm or less.

[0365] The body region 22 may be formed in the semiconductor layer 7 at a distance from the high-concentration portion 8b of the buffer layer 8, and may face the high-concentration portion 8b of the buffer layer 8 across a part of the semiconductor layer 7. With this configuration, the direct supply of holes from the body region 22 to the high-concentration portion 8b is appropriately suppressed, and bipolar degradation caused by the body region 22 is appropriately suppressed.

[0366] The gate structure 25 may be formed in the semiconductor layer 7 at a distance from the high concentration portion 8 b of the buffer layer 8, and may face the high concentration portion 8 b of the buffer layer 8 across a part of the semiconductor layer 7. With this configuration, damage to the buffer layer 8 caused by the gate structure 25 is appropriately suppressed.

[0367] The semiconductor device 1A may include an n-type source region 33. The source region 33 may be formed in the body region 22. The semiconductor device 1A may include a p-type well region 30. The well region 30 may be formed in a region of the semiconductor layer 7 along the bottom wall of the gate structure 25. With this configuration, holes (minority carriers) supplied from the well region 30 recombine with electrons (majority carriers) in the high-concentration portion 8b, thereby reducing the number of holes reaching the low-concentration portion 8a. This suppresses bipolar degradation caused by basal plane dislocation defects.

[0368] The well region 30 may be formed in the semiconductor layer 7 at a distance from the high concentration portion 8b of the buffer layer 8 in the thickness direction, and may face the high concentration portion 8b of the buffer layer 8 across a part of the semiconductor layer 7. With this configuration, the direct supply of holes from the well region 30 to the high concentration portion 8b is appropriately suppressed, and bipolar degradation caused by the well region 30 is appropriately suppressed.

[0369] The semiconductor device 1A may include a p-type contact region 34. The contact region 34 may have a higher impurity concentration than the body region 22 and may be formed in a region along the sidewall of the gate structure 25 in the semiconductor layer 7. With this configuration, holes (minority carriers) supplied from the contact region 34 recombine with electrons (majority carriers) in the high-concentration portion 8b, thereby reducing the number of holes reaching the low-concentration portion 8a. This suppresses bipolar degradation caused by basal plane dislocation defects.

[0370] The semiconductor device 1A may include an active region 20 and a peripheral region 21. The active region 20 may be provided in an inner portion of the semiconductor layer 7, and the peripheral region 21 may be provided in an outer portion of the semiconductor layer 7. The body region 22 may be formed in the semiconductor layer 7 in the active region 20. The gate structure 25 may be formed in the semiconductor layer 7 in the active region 20.

[0371] The semiconductor device 1A may include a p-type outer well region 35. The outer well region 35 may be formed in the semiconductor layer 7 in the peripheral region 21 so as to separate the active region 20 from the peripheral region 21. With this configuration, holes (minority carriers) supplied from the outer well region 35 recombine with electrons (majority carriers) in the high-concentration portion 8b, thereby reducing the number of holes reaching the low-concentration portion 8a. This suppresses bipolar degradation caused by basal plane dislocation defects.

[0372] The outer well region 35 may be formed in the semiconductor layer 7 at a distance from the high concentration portion 8b of the buffer layer 8 in the thickness direction, and may face the high concentration portion 8b of the buffer layer 8 across a part of the semiconductor layer 7. With this configuration, the direct supply of holes from the outer well region 35 to the high concentration portion 8b is appropriately suppressed, and bipolar degradation caused by the outer well region 35 is appropriately suppressed.

[0373] The semiconductor device 1A may include a plurality of p-type field regions 37. The plurality of field regions 37 may be formed in the semiconductor layer 7 in the peripheral region 21. With this configuration, holes (minority carriers) supplied from the plurality of field regions 37 recombine with electrons (majority carriers) in the high-concentration portion 8b, thereby reducing the number of holes reaching the low-concentration portion 8a. This suppresses bipolar degradation caused by basal plane dislocation defects.

[0374] The plurality of field regions 37 may be formed in the semiconductor layer 7 at intervals in the thickness direction from the high-concentration portion 8b of the buffer layer 8, and may face the high-concentration portion 8b of the buffer layer 8 across a part of the semiconductor layer 7. With this configuration, the direct supply of holes from the plurality of field regions 37 to the high-concentration portion 8b is appropriately suppressed, and bipolar degradation caused by the plurality of field regions 37 is appropriately suppressed.

[0375] From another perspective, the semiconductor device 1A includes an n-type (first conductivity type) semiconductor substrate 6 (substrate), an n-type semiconductor layer 7, an n-type buffer layer 8, a trench electrode type gate structure 25, and a p-type (second conductivity type) well region 30. The semiconductor substrate 6 has a first concentration C1. The semiconductor layer 7 has a second concentration C2 less than the first concentration C1 and is stacked on the semiconductor substrate 6.

[0376] The buffer layer 8 is interposed between the semiconductor substrate 6 and the semiconductor layer 7. The buffer layer 8 includes a low-concentration portion 8a and a high-concentration portion 8b. The low-concentration portion 8a has a third concentration C3 less than the first concentration C1, and is formed in a region on the semiconductor substrate 6 side. The high-concentration portion 8b has a fourth concentration C4 higher than the third concentration C3, and is formed in a region on the semiconductor layer 7 side. The gate structure 25 is formed in the semiconductor layer 7. The well region 30 is formed below the gate structure 25 within the semiconductor layer 7, spaced apart from the buffer layer 8 in the thickness direction.

[0377] This configuration provides a novel semiconductor device 1A. For example, this semiconductor device 1A appropriately suppresses the direct supply of holes (minority carriers) from the well region 30 to the high-concentration portion 8b. Holes recombine with electrons (majority carriers) in the semiconductor layer 7 and the high-concentration portion 8b, reducing the number of holes reaching the low-concentration portion 8a. This reduces the number of holes reaching the boundary between the semiconductor substrate 6 and the buffer layer 8, suppressing the recombination of holes and electrons at basal plane dislocation defects.

[0378] As a result, bipolar degradation due to basal plane dislocation defects is suppressed. Such a configuration is effective in suppressing an increase in the thickness of the buffer layer 8 and an increase in the impurity concentration of the entire buffer layer 8. As a result, the uniformity of the impurity concentration and layer thickness of the buffer layer 8 is appropriately increased, and holes and electrons can be appropriately recombined in the high-concentration portion 8b. Furthermore, the manufacturing cost of the buffer layer 8 is reduced.

[0379] From another perspective, the semiconductor device 1A includes an n-type (first conductivity type) semiconductor substrate 6 (substrate), an n-type semiconductor layer 7, an n-type buffer layer 8, and a plurality of p-type (second conductivity type) well regions 30. The semiconductor substrate 6 has a first concentration C1. The semiconductor layer 7 has a second concentration C2 less than the first concentration C1 and is stacked on the semiconductor substrate 6.

[0380] The buffer layer 8 is interposed between the semiconductor substrate 6 and the semiconductor layer 7. The buffer layer 8 includes a low-concentration portion 8a and a high-concentration portion 8b. The low-concentration portion 8a has a third concentration C3 less than the first concentration C1, and is formed in a region on the semiconductor substrate 6 side. The high-concentration portion 8b has a fourth concentration C4 higher than the third concentration C3, and is formed in a region on the semiconductor layer 7 side. The multiple well regions 30 are formed in the semiconductor layer 7 at intervals in the horizontal direction, and extend vertically in the thickness direction of the semiconductor layer 7.

[0381] This configuration provides a novel semiconductor device 1A. For example, this semiconductor device 1A appropriately suppresses the direct supply of holes (minority carriers) from the multiple well regions 30 to the high-concentration portion 8b. Because the holes recombine with electrons (majority carriers) in the semiconductor layer 7 and the high-concentration portion 8b, the number of holes reaching the low-concentration portion 8a is reduced. This reduces the number of holes reaching the boundary between the semiconductor substrate 6 and the buffer layer 8, suppressing the recombination of holes and electrons at basal plane dislocation defects.

[0382] As a result, bipolar degradation due to basal plane dislocation defects is suppressed. Such a configuration is effective in suppressing an increase in the thickness of the buffer layer 8 and an increase in the impurity concentration of the entire buffer layer 8. As a result, the uniformity of the impurity concentration and layer thickness of the buffer layer 8 is appropriately increased, and holes and electrons can be appropriately recombined in the high-concentration portion 8b. Furthermore, the manufacturing cost of the buffer layer 8 is reduced.

[0383] From another perspective, the semiconductor device 1A includes an n-type (first conductivity type) semiconductor substrate 6 (substrate), an n-type semiconductor layer 7, an n-type buffer layer 8, an active region 20, a peripheral region 21, and a p-type (second conductivity type) outer well region 35. The semiconductor substrate 6 has a first concentration C1. The semiconductor layer 7 has a second concentration C2 less than the first concentration C1 and is stacked on the semiconductor substrate 6.

[0384] The buffer layer 8 is interposed between the semiconductor substrate 6 and the semiconductor layer 7. The buffer layer 8 includes a low-concentration portion 8a and a high-concentration portion 8b. The low-concentration portion 8a has a third concentration C3 less than the first concentration C1 and is formed in a region on the semiconductor substrate 6 side. The high-concentration portion 8b has a fourth concentration C4 higher than the third concentration C3 and is formed in a region on the semiconductor layer 7 side.

[0385] The gate structure 25 is formed in the semiconductor layer 7. The outer well region 35 is formed in the semiconductor layer 7 in the peripheral region 21 at a distance in the thickness direction from the buffer layer 8 so as to separate the active region 20 and the peripheral region 21.

[0386] This configuration provides a novel semiconductor device 1A. For example, this semiconductor device 1A appropriately suppresses the direct supply of holes (minority carriers) from the outer well region 35 to the high-concentration portion 8b. Holes recombine with electrons (majority carriers) in the semiconductor layer 7 and the high-concentration portion 8b, reducing the number of holes reaching the low-concentration portion 8a. This reduces the number of holes reaching the boundary between the semiconductor substrate 6 and the buffer layer 8, suppressing the recombination of holes and electrons at basal plane dislocation defects.

[0387] As a result, bipolar degradation due to basal plane dislocation defects is suppressed. Such a configuration is effective in suppressing an increase in the thickness of the buffer layer 8 and an increase in the impurity concentration of the entire buffer layer 8. As a result, the uniformity of the impurity concentration and layer thickness of the buffer layer 8 is appropriately increased, and holes and electrons can be appropriately recombined in the high-concentration portion 8b. Furthermore, the manufacturing cost of the buffer layer 8 is reduced.

[0388] From another perspective, semiconductor device 1A includes an n-type (first conductivity type) semiconductor substrate 6 (substrate), an n-type semiconductor layer 7, an n-type buffer layer 8, an active region 20, a peripheral region 21, and at least one p-type (second conductivity type) field region 37. Semiconductor substrate 6 has a first concentration C1. Semiconductor layer 7 has a second concentration C2 less than first concentration C1 and is stacked on semiconductor substrate 6.

[0389] The buffer layer 8 is interposed between the semiconductor substrate 6 and the semiconductor layer 7. The buffer layer 8 includes a low-concentration portion 8a and a high-concentration portion 8b. The low-concentration portion 8a has a third concentration C3 less than the first concentration C1 and is formed in a region on the semiconductor substrate 6 side. The high-concentration portion 8b has a fourth concentration C4 higher than the third concentration C3 and is formed in a region on the semiconductor layer 7 side.

[0390] The gate structure 25 is formed in the semiconductor layer 7. At least one field region 37 is formed in the semiconductor layer 7 in the peripheral region 21 and spaced apart from the buffer layer 8 in the thickness direction.

[0391] This configuration provides a novel semiconductor device 1A. For example, this semiconductor device 1A appropriately suppresses the direct supply of holes (minority carriers) from at least one field region 37 to the high-concentration portion 8b. Because the holes recombine with electrons (majority carriers) in the semiconductor layer 7 and the high-concentration portion 8b, the number of holes reaching the low-concentration portion 8a is reduced. This reduces the number of holes reaching the boundary between the semiconductor substrate 6 and the buffer layer 8, suppressing the recombination of holes and electrons at basal plane dislocation defects.

[0392] As a result, bipolar degradation due to basal plane dislocation defects is suppressed. Such a configuration is effective in suppressing an increase in the thickness of the buffer layer 8 and an increase in the impurity concentration of the entire buffer layer 8. As a result, the uniformity of the impurity concentration and layer thickness of the buffer layer 8 is appropriately increased, and holes and electrons can be appropriately recombined in the high-concentration portion 8b. Furthermore, the manufacturing cost of the buffer layer 8 is reduced.

[0393] Fig. 14 is an enlarged plan view showing a main portion of the first main surface 3 of a semiconductor device 1B according to the second embodiment. Fig. 15 is a cross-sectional view taken along line XV-XV in Fig. 14. Fig. 16 is a cross-sectional view taken along line XVI-XVI in Fig. 14. Referring to Figs. 14 to 16, the semiconductor device 1B has a configuration in which the well region 30 is removed from the semiconductor device 1A.

[0394] In this embodiment, the plurality of contact regions 34 are formed in regions along the plurality of gate structures 25 at intervals from the bottom of the body region 22 toward the first main surface 3. In other words, each of the plurality of contact regions 34 is made up of the third region 34C, and does not have the first region 34A or the second region 34B.

[0395] The plurality of contact regions 34 may be connected to the plurality of source regions 33 in the second direction Y. The plurality of contact regions 34 may be formed at intervals from the plurality of source regions 33 in the second direction Y. In this case, the plurality of contact regions 34 may face the plurality of source regions 33 with a part of the body region 22 interposed therebetween.

[0396] In plan view, the plurality of contact regions 34 along one gate structure 25 face the plurality of contact regions 34 along the other gate structure 25 in the first direction X. In other words, the plurality of contact regions 34 are generally arranged in a matrix with gaps in the first direction X and the second direction Y in plan view.

[0397] In plan view, one of the plurality of contact regions 34 may face a region between the other of the plurality of contact regions 34 in the first direction X. That is, in plan view, the plurality of contact regions 34 may be generally arranged in a staggered pattern with intervals in the first direction X and the second direction Y. The description of the contact region 34 of the semiconductor device 1A applies to other descriptions of the contact region 34 of the semiconductor device 1B.

[0398] As described above, the semiconductor device 1B includes an n-type (first conductivity type) semiconductor substrate 6 (substrate), an n-type semiconductor layer 7, an n-type buffer layer 8, a p-type (second conductivity type) body region 22 (impurity region 9), and a trench electrode type gate structure 25. The semiconductor substrate 6 has a first concentration C1. The semiconductor layer 7 has a second concentration C2 less than the first concentration C1 and is stacked on the semiconductor substrate 6.

[0399] The buffer layer 8 is interposed between the semiconductor substrate 6 and the semiconductor layer 7. The buffer layer 8 includes a low-concentration portion 8a and a high-concentration portion 8b. The low-concentration portion 8a has a third concentration C3 less than the first concentration C1 and is formed in a region on the semiconductor substrate 6 side. The high-concentration portion 8b has a fourth concentration C4 higher than the third concentration C3 and is formed in a region on the semiconductor layer 7 side. The body region 22 is formed in the semiconductor layer 7. The gate structure 25 is formed in the semiconductor layer 7.

[0400] This configuration provides a novel semiconductor device 1B. For example, in this semiconductor device 1B, holes (minority carriers) supplied from the body region 22 recombine with electrons (majority carriers) in the high-concentration region 8b, reducing the number of holes reaching the low-concentration region 8a. This reduces the number of holes reaching the boundary between the semiconductor substrate 6 and the buffer layer 8, suppressing the recombination of holes and electrons at basal plane dislocation defects. As a result, bipolar degradation due to basal plane dislocation defects is suppressed.

[0401] Such a configuration is effective in suppressing an increase in the thickness of the buffer layer 8 and an increase in the impurity concentration of the entire buffer layer 8. This appropriately increases the uniformity of the impurity concentration and layer thickness of the buffer layer 8, allowing holes and electrons to appropriately recombine in the high-concentration portion 8 b. In addition, the manufacturing cost of the buffer layer 8 is reduced.

[0402] Fig. 17 is an enlarged plan view showing a main portion of the first main surface 3 of a semiconductor device 1C according to a third embodiment. Fig. 18 is a cross-sectional view taken along line XVIII-XVIII shown in Fig. 17. Referring to Figs. 17 and 18, the semiconductor device 1C has a configuration obtained by modifying the configuration of the semiconductor device 1A.

[0403] Specifically, the semiconductor device 1C includes a plurality of p-type side well regions 50 as another example of the well region 30. The side well regions 50 are also one example of the impurity region 9. The side well regions 50 may have a p-type impurity concentration higher than the p-type impurity concentration of the body region 22. The p-type impurity concentration of the side well regions 50 may be lower than the p-type impurity concentration of the body region 22.

[0404] The side well regions 50 are formed in a region along one sidewall of each of the gate structures 25. In this embodiment, the side well regions 50 are formed in a one-to-one correspondence with the gate structures 25. The side well regions 50 are formed at intervals on the corresponding gate structure 25 side from the adjacent gate structure 25, and are not formed in a region along the other sidewall of the corresponding gate structure 25.

[0405] The multiple side well regions 50 each extend in the thickness direction along one sidewall of the corresponding gate structure 25 so as to penetrate the body region 22, and each have a bottom located below the bottom wall of the corresponding gate structure 25.

[0406] That is, the multiple side well regions 50 have portions located in the body region 22 and portions located in the semiconductor layer 7. The portions of the multiple side well regions 50 that overlap the body region 22 have a p-type impurity concentration that is higher than the p-type impurity concentration of the side well regions 50 and the p-type impurity concentration of the body region 22.

[0407] The multiple side well regions 50 are formed at intervals from the middle of the mesa portion 29 toward the corresponding gate structure 25. With this configuration, both the side well region 50 and the body region 22 are formed in each mesa portion 29. Of course, the multiple side well regions 50 may be formed at intervals toward the corresponding gate structure 25, and may have a portion that protrudes from the middle of the mesa portion 29 toward the adjacent gate structure 25.

[0408] The side well regions 50 are formed at intervals from the buffer layer 8 (high concentration portion 8 b) toward the first main surface 3, and face the buffer layer 8 with a part of the semiconductor layer 7 sandwiched therebetween. The side well regions 50 have a portion that extends along at least a part of the bottom wall of the corresponding gate structure 25. Specifically, the side well regions 50 extend along a part of the bottom wall of the corresponding gate structure 25, at an interval from the other side wall of the corresponding gate structure 25 toward one side wall.

[0409] The plurality of side well regions 50 may be formed along two-thirds or less of the area of ​​the bottom wall of the corresponding gate structure 25. The plurality of side well regions 50 may be formed along one-half or less of the area of ​​the bottom wall of the corresponding gate structure 25. The plurality of side well regions 50 may be formed along the entire area of ​​the bottom wall of the corresponding gate structure 25.

[0410] In this embodiment, the aforementioned plurality of source regions 33 include a plurality of first source regions 33 a and a plurality of second source regions 33 b. The plurality of first source regions 33 a have an n-type impurity concentration higher than the p-type impurity concentration of the body region 22. The n-type impurity concentration of the first source regions 33 a is higher than the p-type impurity concentration of the side well region 50. The n-type impurity concentration of the first source regions 33 a is higher than the n-type impurity concentration of the semiconductor layer 7.

[0411] The plurality of first source regions 33 a are formed in regions along the other sidewalls of the plurality of gate structures 25 in the surface layer portion of the body region 22. In this embodiment, the plurality of first source regions 33 a are formed in a one-to-one correspondence with the plurality of gate structures 25, and face the corresponding buried electrodes 28 via the corresponding insulating films 27. In this embodiment, the plurality of first source regions 33 a extend in a strip shape in the second direction Y in accordance with the extension direction of the plurality of gate structures 25 in a plan view.

[0412] The plurality of first source regions 33 a may be formed in the body region 22 at intervals from the side well region 50 and may face the side well region 50 across a part of the body region 22. The plurality of first source regions 33 a may have a portion located in the side well region 50 across the boundary between the body region 22 and the side well region 50.

[0413] The plurality of first source regions 33 a are formed at intervals from the bottom of the body region 22 toward the first main surface 3, and face the semiconductor layer 7 across a part (bottom) of the body region 22. The plurality of first source regions 33 a each have a portion located on the bottom wall side of the plurality of trenches 26 with respect to the electrode surfaces of the plurality of buried electrodes 28, and a portion located on the first main surface 3 side with respect to the electrode surfaces of the plurality of buried electrodes 28.

[0414] The plurality of first source regions 33a have a thickness (depth) greater than the thickness between the bottom of the body region 22 and the bottom of the first source region 33a. The thickness of the first source region 33a may be less than the thickness between the bottom of the body region 22 and the bottom of the first source region 33a. The plurality of first source regions 33a, together with the semiconductor layer 7, define a channel that serves as a current path on the bottom side of the body region 22.

[0415] The channel may have a channel length greater than 0 nm and less than or equal to 500 nm. The channel length is the distance between the bottom of the body region 22 and the bottom of the source region 33. The channel length may have a value belonging to at least one of the following ranges: greater than 0 nm and less than or equal to 50 nm, 50 nm to 100 nm, 100 nm to 150 nm, 150 nm to 200 nm, 200 nm to 250 nm, 250 nm to 300 nm, 300 nm to 350 nm, 350 nm to 400 nm, 400 nm to 450 nm, and 450 nm to 500 nm.

[0416] The second source regions 33b have an n-type impurity concentration higher than the p-type impurity concentration of the body region 22. The n-type impurity concentration of the second source regions 33b is higher than the p-type impurity concentration of the side well region 50. The n-type impurity concentration of the second source regions 33b is higher than the n-type impurity concentration of the semiconductor layer 7.

[0417] The second source regions 33b are formed in the surface layer of the side well regions 50 at intervals from the first source regions 33a, respectively, in regions along one sidewall of the gate structures 25. In this embodiment, the second source regions 33b are formed in a one-to-one correspondence with the gate structures 25, and face the corresponding buried electrodes 28 via the corresponding insulating films 27.

[0418] In this embodiment, the second source regions 33b extend in a strip shape in the second direction Y in plan view, following the extension direction of the gate structures 25. The second source regions 33b face the first source regions 33a, respectively, with the corresponding gate structures 25 interposed therebetween.

[0419] The plurality of second source regions 33b may be formed in the side well region 50 at intervals from the body region 22 and face the body region 22 across a portion of the side well region 50. The plurality of second source regions 33b may have a portion located within the body region 22 across the boundary between the body region 22 and the side well region 50. The plurality of second source regions 33b may face the plurality of first source regions 33a in the horizontal direction across either or both of a portion of the body region 22 and a portion of the side well region 50.

[0420] The second source regions 33b are formed at intervals from the bottom of the side well region 50 toward the first main surface 3, and face the semiconductor layer 7 across a part (bottom) of the side well region 50. The second source regions 33b each have a portion located on the bottom wall side of the trenches 26 relative to the electrode surfaces of the buried electrodes 28, and a portion located on the first main surface 3 side of the electrode surfaces of the buried electrodes 28.

[0421] The second source regions 33b each have a thickness (depth) that is less than the thickness (depth) between the bottom of the side well region 50 and the bottom of the second source regions 33b. The second source regions 33b, together with the semiconductor layer 7, define a channel that serves as a current path within the side well region 50. The channel length on the second source region 33b side is longer than the channel length on the first source region 33a side. The channel length on the second source region 33b side may be between two and ten times the channel length on the first source region 33a side.

[0422] In this embodiment, the plurality of source openings 40 expose the plurality of side well regions 50, the plurality of first source regions 33 a, and the plurality of second source regions 33 b, respectively, in the corresponding mesa portion 29. The source electrode 43 extends into the plurality of source openings 40 from above the interlayer film 10, and is mechanically and electrically connected to the plurality of side well regions 50, the plurality of first source regions 33 a, and the plurality of second source regions 33 b within the plurality of source openings 40.

[0423] As described above, the semiconductor device 1C includes an n-type (first conductivity type) semiconductor substrate 6 (substrate), an n-type semiconductor layer 7, an n-type buffer layer 8, a trench electrode type gate structure 25, and a p-type (second conductivity type) side well region 50 (well region 30). The semiconductor substrate 6 has a first concentration C1. The semiconductor layer 7 has a second concentration C2 less than the first concentration C1 and is stacked on the semiconductor substrate 6.

[0424] The buffer layer 8 is interposed between the semiconductor substrate 6 and the semiconductor layer 7. The buffer layer 8 includes a low-concentration portion 8a and a high-concentration portion 8b. The low-concentration portion 8a has a third concentration C3 less than the first concentration C1, and is formed in a region on the semiconductor substrate 6 side. The high-concentration portion 8b has a fourth concentration C4 higher than the third concentration C3, and is formed in a region on the semiconductor layer 7 side. The gate structure 25 is formed in the semiconductor layer 7. The side well region 50 is formed in the semiconductor layer 7 along one sidewall of the gate structure 25.

[0425] This configuration allows for the provision of a novel semiconductor device 1C. This configuration allows for the provision of a novel semiconductor device 1C. For example, in this semiconductor device 1C, holes (minority carriers) supplied from the side well region 50 recombine with electrons (majority carriers) in the high-concentration region 8b, thereby reducing the number of holes reaching the low-concentration region 8a. This reduces the number of holes reaching the boundary between the semiconductor substrate 6 and the buffer layer 8, suppressing the recombination of holes and electrons at basal plane dislocation defects. As a result, bipolar degradation due to basal plane dislocation defects is suppressed.

[0426] Such a configuration is effective in suppressing an increase in the thickness of the buffer layer 8 and an increase in the impurity concentration of the entire buffer layer 8. This appropriately increases the uniformity of the impurity concentration and layer thickness of the buffer layer 8, allowing holes and electrons to appropriately recombine in the high-concentration portion 8 b. In addition, the manufacturing cost of the buffer layer 8 is reduced.

[0427] Fig. 19 is a plan view showing a semiconductor device 1D according to a fourth embodiment. Fig. 20 is a cross-sectional view taken along line XX-XX shown in Fig. 19. Fig. 21 is an enlarged plan view showing a main portion of the first main surface 3. Fig. 22 is a cross-sectional view taken along line XXII-XXII shown in Fig. 21. Fig. 23 is a cross-sectional view taken along line XXIII-XXIII shown in Fig. 19.

[0428] 19 to 23, a semiconductor device 1D is a semiconductor switching device having an insulated gate transistor structure Tr as an example of a device structure (functional device). The transistor structure Tr has a planar gate vertical structure.

[0429] The semiconductor device 1D includes the aforementioned chip 2. The chip 2 includes a semiconductor substrate 6, a semiconductor layer 7, and a buffer layer 8. The buffer layer 8 includes a low concentration portion 8a, a high concentration portion 8b, and a transition portion 8c. The buffer layer 8 may have any one of the first to thirteenth concentration gradient examples (see FIGS. 3A to 3M). The semiconductor device 1D includes the aforementioned active region 20 and peripheral region 21 provided in the semiconductor layer 7.

[0430] The semiconductor device 1D includes the aforementioned impurity region 9 formed in the active region 20 (inner portion of the first main surface 3) in the surface layer portion of the first main surface 3. In this embodiment, the impurity region 9 is formed as a plurality of p-type body regions 22. The plurality of body regions 22 have a p-type impurity concentration higher than the n-type impurity concentration of the semiconductor layer 7, and replace the n-type conductivity of the semiconductor layer 7 with p-type.

[0431] The plurality of body regions 22 are formed in an inner portion of the first main surface 3 at intervals from the periphery of the first main surface 3, and are not formed in the outer peripheral region 21. In this embodiment, the plurality of body regions 22 are formed at intervals in the first direction X, and each extend in a strip shape in the second direction Y. The plurality of body regions 22 are arranged in a stripe shape extending in the second direction Y. The extension direction of the plurality of body regions 22 coincides with the off-direction of the SiC single crystal. The plurality of body regions 22 may be formed at intervals in the second direction Y, and each extend in a strip shape in the first direction X.

[0432] The plurality of body regions 22 are formed at intervals from the buffer layer 8 (high concentration portion 8 b) toward the first main surface 3, and face the buffer layer 8 across a part of the semiconductor layer 7. The plurality of body regions 22 are formed at intervals from a depth position in the middle of the semiconductor layer 7 toward the first main surface 3. The plurality of body regions 22 form pn junctions with the semiconductor layer 7.

[0433] This forms a body diode structure (pn junction diode structure) as a diode structure Di having the plurality of body regions 22 as anode regions and the semiconductor layer 7 as a cathode region. The plurality of body regions 22 spread a depletion layer in the semiconductor layer 7 when a reverse bias voltage is applied. The depletion layer originating from the plurality of body regions 22 spreads in the horizontal direction and thickness direction within the semiconductor layer 7.

[0434] The semiconductor device 1D includes a plurality of n-type source regions 33 formed in the surface layer portions of the plurality of body regions 22. The plurality of source regions 33 are formed at intervals from both edges of the corresponding body region 22 toward the inner portions of the corresponding body region 22 in the first direction X.

[0435] The source regions 33 are formed at intervals in the first direction X in the surface layer portion of the corresponding body region 22, and extend in a strip shape in the second direction Y. The source regions 33 may be formed at intervals in the second direction Y following the extension direction of the corresponding body region 22.

[0436] The plurality of source regions 33 are formed at intervals inward from both end portions of the corresponding body regions 22 in the second direction Y. The plurality of source regions 33 are formed at intervals from the bottoms of the corresponding body regions 22 toward the first main surface 3, and face the semiconductor layer 7 with a part of the corresponding body region 22 interposed therebetween.

[0437] The semiconductor device 1D includes a plurality of p-type contact regions 34 formed in regions different from the plurality of source regions 33 in the surface layer portion of the corresponding body region 22. The plurality of contact regions 34 are interposed in regions between the plurality of source regions 33 in the surface layer portion of the corresponding body region 22, and are electrically connected to the body region 22.

[0438] The plurality of contact regions 34 extend in a strip shape along the extension direction of the corresponding body region 22 (source region 33). The plurality of contact regions 34 are formed at intervals inward from both end portions of the corresponding body region 22 in the second direction Y. The plurality of contact regions 34 are formed at intervals from the bottoms of the corresponding body regions 22 toward the first main surface 3, and face the semiconductor layer 7 with a portion of the corresponding body region 22 sandwiched therebetween.

[0439] In this embodiment, the contact region 34 has a width that is less than the width of the plurality of source regions 33. The width of the contact region 34 may be greater than the width of the plurality of source regions 33. In this embodiment, the plurality of contact regions 34 have a thickness that is greater than the thickness of the plurality of source regions 33, and have bottoms that are located closer to the bottom of the body region 22 than the bottoms of the plurality of source regions 33.

[0440] The semiconductor device 1D includes a plurality of p-type well regions 30 formed in the semiconductor layer 7. The plurality of well regions 30 have a p-type impurity concentration higher than the n-type impurity concentration of the semiconductor layer 7, and convert the conductivity type of the semiconductor layer 7 from n-type to p-type. A source potential is applied to the plurality of well regions 30.

[0441] The multiple well regions 30 are formed in regions below (specifically, directly below) the multiple body regions 22, spaced apart from one another in the horizontal direction (first direction X) within the semiconductor layer 7. The multiple well regions 30 are formed in thickness ranges between the buffer layer 8 (high concentration portion 8 b) and the bottoms of the multiple body regions 22, and overlap the multiple body regions 22 in a one-to-one correspondence in the thickness direction.

[0442] The multiple well regions 30 each extend in a strip shape in the second direction Y in a plan view following the extension direction of the corresponding body region 22. The multiple well regions 30 are arranged in a stripe shape extending in the second direction Y in a plan view. The extension direction of the multiple well regions 30 coincides with the off-direction of the SiC single crystal.

[0443] With respect to the second direction Y, both ends of the multiple well regions 30 may be located on the inner side of the multiple body regions 22 with respect to both ends of the multiple body regions 22, or may be located on the peripheral side of the active region 20. The multiple well regions 30 may extend in the first direction X according to the extending direction of the multiple body regions 22. In this case, the multiple well regions 30 intersect (specifically, perpendicular to) the off direction.

[0444] Each of the multiple well regions 30 has a width less than the width of the corresponding body region 22. Each of the multiple well regions 30 is formed at an interval from both edges of the corresponding body region 22 toward the inner side of the corresponding body. The width of the multiple well regions 30 may be approximately equal to the width of the corresponding body region 22. The width of the multiple well regions 30 may be greater than the width of the corresponding body region 22.

[0445] The multiple well regions 30 are formed at intervals from the buffer layer 8 (high concentration portion 8 b) toward the bottoms of the multiple body regions 22, and face the buffer layer 8 across a part of the semiconductor layer 7. Each of the multiple well regions 30 has an upper end located on the bottom side of the corresponding body region 22, and a bottom located on the buffer layer 8 (high concentration portion 8 b) side.

[0446] The upper ends of the multiple well regions 30 are connected to the corresponding body regions 22. The upper ends of the multiple well regions 30 may be formed at intervals from the corresponding body regions 22 toward the buffer layer 8.

[0447] The bottoms of the multiple well regions 30 may be located on the bottom wall side of the multiple body regions 22 or on the buffer layer 8 (high concentration portion 8 b) side with respect to the depth position of the intermediate portion of the semiconductor layer 7. The multiple well regions 30 may form a super junction structure together with the semiconductor layer 7 in regions below the multiple body regions 22. In this case, depletion layers originating from the multiple well regions 30 are connected to each other in regions between the multiple well regions 30.

[0448] In this embodiment, the depth of the well region 30 based on the bottom of the body region 22 is greater than the depth of the body region 22 based on the first main surface 3. The depth of the well region 30 may be 0.5 μm or more and 5 μm or less. The depth of the well region 30 may have a value belonging to at least one of the ranges of 0.5 μm or more and 1 μm or less, 1 μm or more and 1.5 μm or less, 1.5 μm or more and 2 μm or less, 2 μm or more and 2.5 μm or less, 2.5 μm or more and 3 μm or less, 3 μm or more and 3.5 μm or less, 3.5 μm or more and 4 μm or less, 4 μm or more and 4.5 μm or less, and 4.5 μm or more and 5 μm or less.

[0449] The semiconductor device 1D includes a plurality of n-type surface drift regions 51 formed in a surface portion of the first main surface 3. In this embodiment, the plurality of surface drift regions 51 are each made of a part of the semiconductor layer 7. Of course, the plurality of surface drift regions 51 may have an n-type impurity concentration higher than the n-type impurity concentration of the semiconductor layer 7, or may have an n-type impurity concentration lower than the n-type impurity concentration of the semiconductor layer 7.

[0450] The surface drift regions 51 are each partitioned into regions between adjacent body regions 22 in the surface portion of the semiconductor layer 7. That is, the surface drift regions 51 are arranged at intervals in the first direction X and extend in stripes in the second direction Y. That is, the surface drift regions 51 are formed in stripes extending in the second direction Y.

[0451] The semiconductor device 1D includes a plurality of p-type channel regions 52 formed in a surface layer portion of the first main surface 3. The plurality of channel regions 52 are partitioned into regions between the plurality of source regions 33 and the plurality of surface drift regions 51 (semiconductor layer 7) in the surface layer portions of the plurality of body regions 22. The plurality of channel regions 52 form a current path extending horizontally along the first main surface 3.

[0452] The semiconductor device 1D includes a plurality of planar gate structures 55 (planar electrode 57 type) arranged on the first main surface 3 in the active region 20. The plurality of gate structures 55 are arranged at intervals in the first direction X and extend in a strip shape in the second direction Y. The plurality of gate structures 55 are arranged in a stripe shape extending in the second direction Y. The extension direction of the plurality of gate structures 55 coincides with the off-direction of the SiC single crystal.

[0453] The plurality of gate structures 55 are each disposed on at least one channel region 52 (periphery of the body region 22). The plurality of gate structures 55 cover at least one peripheral portion of the body region 22, at least one source region 33, and one surface drift region 51, respectively.

[0454] In this embodiment, the plurality of gate structures 55 cross one surface drift region 51, straddling the peripheries of two adjacent body regions 22, and covering the plurality of channel regions 52. Specifically, the plurality of gate structures 55 straddle the source region 33 of the body region 22 on one side and the source region 33 of the body region 22 on the other side, and cover the two source regions 33, one surface drift region 51, and two channel regions 52.

[0455] Each of the multiple gate structures 55 has a stacked structure including a planar insulating film 56 and a planar electrode 57. The planar insulating film 56 may be referred to as a "gate insulating film," and the planar electrode 57 may be referred to as a "gate electrode" or a "planar gate electrode."

[0456] The planar insulating film 56 may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. In this embodiment, the planar insulating film 56 has a single-layer structure made of a silicon oxide film. The planar insulating film 56 preferably includes a silicon oxide film containing an oxide of the semiconductor layer 7.

[0457] The planar insulating film 56 covers the first main surface 3 in a film-like manner. The planar insulating film 56 extends in a strip-like shape in the second direction Y. The planar insulating film 56 is disposed on at least one channel region 52 (periphery of the body region 22). The planar insulating film 56 covers the periphery of at least one body region 22, at least one source region 33, and one surface drift region 51.

[0458] In this embodiment, the planar insulating film 56 crosses one surface drift region 51 and extends across the peripheries of two adjacent body regions 22, covering the channel regions 52. Specifically, the planar insulating film 56 extends across the source region 33 of one body region 22 and the source region 33 of the other body region 22, covering the two source regions 33, one surface drift region 51, and two channel regions 52.

[0459] The planar electrode 57 is disposed on the planar insulating film 56. A gate potential as a control potential is applied to the planar electrode 57. The planar electrode 57 may include either or both of p-type conductive polysilicon and n-type conductive polysilicon.

[0460] The planar electrode 57 covers the first main surface 3 in a film form via the planar insulating film 56, and faces at least one channel region 52 (peripheral edge of the body region 22). The planar electrode 57 extends in a strip shape in the second direction Y. In this embodiment, the planar electrode 57 is formed at a distance inward from both ends of the planar insulating film 56 in the second direction Y, exposing both ends of the planar insulating film 56.

[0461] The planar electrode 57 covers the peripheral edge of at least one body region 22 , at least one source region 33 , and one surface drift region 51 via the planar insulating film 56 .

[0462] In this embodiment, the planar electrode 57 crosses one surface drift region 51 and extends across the peripheries of two adjacent body regions 22, and faces the channel regions 52 via the planar insulating film 56. Specifically, the planar electrode 57 extends across the source region 33 of one body region 22 and the source region 33 of the other body region 22, and faces the two source regions 33, one surface drift region 51, and two channel regions 52 via the planar insulating film 56.

[0463] Similar to the semiconductor device 1A, the semiconductor device 1D includes a p-type outer well region 35 formed in the outer peripheral region 21 (the peripheral portion of the first main surface 3) in the surface layer portion of the first main surface 3. The outer well region 35 has a p-type impurity concentration that is lower than the p-type impurity concentration of the contact region 34.

[0464] The p-type impurity concentration of the outer well region 35 may be approximately equal to the p-type impurity concentration of the body region 22. Of course, the p-type impurity concentration of the outer well region 35 may be lower than the p-type impurity concentration of the body region 22, or may be higher than the p-type impurity concentration of the body region 22.

[0465] The outer well region 35 is formed in the surface layer portion of the semiconductor layer 7, as in the case of the semiconductor device 1A. The outer well region 35 extends in a layered manner along the first main surface 3. In this embodiment, the inner edge portion of the outer well region 35 is connected to the plurality of body regions 22 in the portion extending in the first direction X. The inner edge portion of the outer well region 35 may also be connected to the plurality of well regions 30.

[0466] The inner edge of the outer well region 35 may be located closer to the inside of the first main surface 3 than the ends of the plurality of gate structures 55, or may be located closer to the periphery of the first main surface 3 than the ends of the plurality of gate structures 55. The outer edge of the outer well region 35 is formed at a distance from the periphery of the first main surface 3 and extends approximately parallel to the inner edge of the outer well region 35.

[0467] The outer well region 35 has a width greater than that of the plurality of body regions 22. The width of the outer well region 35 is the width in a direction perpendicular to the extension direction. Of course, the width of the outer well region 35 may be approximately equal to the width of the plurality of body regions 22, or may be less than the width of the plurality of body regions 22.

[0468] The ratio of the width of the outer well region 35 to the width of the body region 22 may be 1 or more and 50 or less. The ratio of the width of the gate wiring 39 to the width of the planar electrode 57 may be 1 or more and 50 or less. The width ratio may have a value belonging to at least one of the ranges of 1 or more and 10 or less, 10 or more and 20 or less, 20 or more and 30 or less, 30 or more and 40 or less, and 40 or more and 50 or less. The above description applies to the other descriptions of the outer well region 35.

[0469] Similar to the semiconductor device 1A, the semiconductor device 1D includes a p-type outer contact region 36 and one or more (multiple in this embodiment) p-type field regions 37 formed in the surface layer portion of the outer well region 35. The above description applies to the outer contact region 36 and the multiple field regions 37.

[0470] Similar to the semiconductor device 1A, the semiconductor device 1D includes a main surface insulating film 38 that selectively covers the first main surface 3. The main surface insulating film 38 selectively covers the first main surface 3 in the active region 20 and the peripheral region 21. The main surface insulating film 38 covers the first main surface 3 in the active region 20 in a film form and is connected to a plurality of planar insulating films 56. The main surface insulating film 38 is formed integrally with the plurality of planar insulating films 56 and forms a single insulating film together with the plurality of planar insulating films 56.

[0471] The main surface insulating film 38 covers the outer well region 35, the outer contact region 36, and the plurality of field regions 37 in the peripheral region 21. The main surface insulating film 38 is continuous with the first to fourth side surfaces 5A to 5D. The main surface insulating film 38 may be formed at intervals inward from the first to fourth side surfaces 5A to 5D, exposing the peripheral edge portion of the first main surface 3.

[0472] Similar to the semiconductor device 1A, the semiconductor device 1D includes one or more (one in this embodiment) gate wirings 39 arranged on the first main surface 3 in the peripheral region 21. The gate wiring 39 applies a gate potential to the multiple gate structures 55.

[0473] The gate wiring 39 may include either or both of p-type conductive polysilicon and n-type conductive polysilicon. The gate wiring 39 preferably has the same conductivity type as the planar electrode 57. The gate wiring 39 has a thickness approximately equal to that of the planar electrode 57. The thickness of the gate wiring 39 may be greater than or less than the thickness of the planar electrode 57.

[0474] The gate wiring 39 is disposed on the main surface insulating film 38. The gate wiring 39 is selectively routed on the main surface insulating film 38 at intervals from the periphery of the first main surface 3 toward the plurality of gate structures 55. The gate wiring 39 extends in a strip shape along the plurality of gate structures 55. The gate wiring 39 has a portion extending in a strip shape in the first direction X and a portion extending in a strip shape in the second direction Y.

[0475] In this embodiment, the gate wiring 39 is formed in an endless polygonal ring shape (e.g., a square ring shape) having four sides parallel to the periphery of the first main surface 3, and surrounds the multiple gate structures 55 (active regions 20). Of course, the gate wiring 39 may also be formed in a strip shape with ends. The gate wiring 39 may have an edge portion that connects the strip-like portion extending in the first direction X and the strip-like portion extending in the second direction Y in a plan view into an arc shape (preferably a quarter arc shape).

[0476] The gate wiring 39 has an inner edge portion on the inner side of the first main surface 3 and an outer edge portion on the peripheral side of the first main surface 3. The inner edge portion of the gate wiring 39 is mechanically and electrically connected to a plurality of planar electrodes 57 (gate structures 55) in a portion extending in the first direction X. In this embodiment, the gate wiring 39 is formed integrally with the plurality of planar electrodes 57.

[0477] The inner edge of the gate wiring 39 is formed at a distance from the inner edge of the outer well region 35 (the plurality of body regions 22) toward the outer edge of the outer well region 35. In other words, the inner edge of the gate wiring 39 is formed at a distance from the plurality of source regions 33 and the plurality of contact regions 34, and does not face the plurality of source regions 33 and the plurality of contact regions 34 across the main surface insulating film 38.

[0478] The outer edge of the gate wiring 39 is disposed at a distance from the innermost field region 37 toward the active region 20, and does not face the field region 37 across the main surface insulating film 38. With this configuration, the gate wiring 39 is prevented from blocking the electric field dispersion path, and the electric field (electric force lines) are appropriately dispersed by the multiple field regions 37.

[0479] The outer edge of the gate wiring 39 is formed at a distance from the outer edge of the outer well region 35 toward the plurality of gate structures 55. The outer edge of the gate wiring 39 is formed at a distance from the inner edge of the outer contact region 36 toward the plurality of gate structures 55. The outer edge of the gate wiring 39 may be located above the outer contact region 36.

[0480] The gate wiring 39 has a width less than that of the outer well region 35 and is disposed on the outer well region 35 at a distance from the inner and outer edges of the outer well region 35. The width of the gate wiring 39 is the width in a direction perpendicular to the direction in which it extends. The width of the gate wiring 39 is greater than the width of the planar electrode 57. The width of the gate wiring 39 may be approximately equal to the width of the planar electrode 57 or may be less than the width of the planar electrode 57.

[0481] The ratio of the width of the gate wiring 39 to the width of the planar electrode 57 may be equal to or greater than 1 and equal to or less than 50. The ratio of the width of the gate wiring 39 to the width of the planar electrode 57 may be equal to or greater than 1 and equal to or less than 50. The width ratio may have a value belonging to at least one of the ranges of 1 to 10, 10 to 20, 20 to 30, 30 to 40, and 40 to 50.

[0482] Similar to the semiconductor device 1A, the semiconductor device 1D includes an interlayer film 10 that selectively covers the first main surface 3 in the active region 20 and the peripheral region 21. The interlayer film 10 covers a plurality of gate structures 55 in the active region 20. Specifically, the interlayer film 10 covers a plurality of planar insulating films 56 and a plurality of planar electrodes 57, and electrically insulates the plurality of planar electrodes 57.

[0483] In the peripheral region 21, the interlayer film 10 covers the outer well region 35, the outer contact region 36, and a plurality of field regions 37 via the main surface insulating film 38. The interlayer film 10 directly covers the gate wiring 39 in the peripheral region 21. The above description applies to the rest of the description of the interlayer film 10.

[0484] Similar to the semiconductor device 1A, the semiconductor device 1A includes a plurality of source openings 40, a plurality of gate openings 41, and an outer opening 42 formed in the interlayer film 10. The above description applies to the plurality of gate openings 41 and the outer opening 42.

[0485] The source openings 40 are formed in a one-to-one correspondence in regions between the planar electrodes 57, and extend in strip shapes in the second direction Y following the extension direction of the planar electrodes 57. The source openings 40 penetrate the planar insulating film 56 and the interlayer film 10, and expose the source regions 33 and the contact regions 34, respectively. The source openings 40 may each have an opening end that is curved in an arc shape.

[0486] The source openings 40 may be formed in a one-to-many correspondence in the region between the planar electrodes 57. In this case, the source openings 40 may be formed at intervals along the extension direction of the planar electrodes 57. In this case, the source openings 40 may be formed in a quadrangular, rectangular (strip-like), circular, or other shape in a plan view.

[0487] Similar to the semiconductor device 1A, the semiconductor device 1A includes a source electrode 43 as the first electrode 12 arranged on the first main surface 3, a source finger electrode 44, a gate electrode 45, and a gate finger electrode 46.

[0488] In this embodiment, the source electrode 43 is electrically connected to the body regions 22, the source regions 33, and the contact regions 34 within the source openings 40. The source electrode 43, the source finger electrodes 44, the gate electrode 45, and the gate finger electrodes 46 can be explained by replacing "gate structure 25" with "gate structure 55" in the above explanation.

[0489] Similar to the semiconductor device 1A, the semiconductor device 1A includes the above-described top film 13 that selectively covers the first main surface 3. The above-described description applies to the top film 13. The semiconductor device 1A includes a drain electrode 49 as the above-described second electrode 17 disposed on the second main surface 4. The above-described description applies to the drain electrode 49.

[0490] As described above, the semiconductor device 1D includes an n-type (first conductivity type) semiconductor substrate 6 (substrate), an n-type semiconductor layer 7, an n-type buffer layer 8, a p-type (second conductivity type) body region 22 (impurity region 9), and a planar electrode 57-type gate structure 25. The semiconductor substrate 6 has a first concentration C1. The semiconductor layer 7 has a second concentration C2 less than the first concentration C1 and is stacked on the semiconductor substrate 6.

[0491] The buffer layer 8 is interposed between the semiconductor substrate 6 and the semiconductor layer 7. The buffer layer 8 includes a low-concentration portion 8a and a high-concentration portion 8b. The low-concentration portion 8a has a third concentration C3 less than the first concentration C1 and is formed in a region on the semiconductor substrate 6 side. The high-concentration portion 8b has a fourth concentration C4 higher than the third concentration C3 and is formed in a region on the semiconductor layer 7 side. The body region 22 is formed in the semiconductor layer 7. The gate structure 25 is disposed on the semiconductor layer 7.

[0492] This configuration provides a novel semiconductor device 1D. For example, in this semiconductor device 1D, holes (minority carriers) supplied from the body region 22 recombine with electrons (majority carriers) in the high-concentration region 8b, reducing the number of holes reaching the low-concentration region 8a. This reduces the number of holes reaching the boundary between the semiconductor substrate 6 and the buffer layer 8, suppressing the recombination of holes and electrons at basal-plane dislocation defects. As a result, bipolar degradation due to basal-plane dislocation defects is suppressed.

[0493] Such a configuration is effective in suppressing an increase in the thickness of the buffer layer 8 and an increase in the impurity concentration of the entire buffer layer 8. This appropriately increases the uniformity of the impurity concentration and layer thickness of the buffer layer 8, allowing holes and electrons to appropriately recombine in the high-concentration portion 8 b. In addition, the manufacturing cost of the buffer layer 8 is reduced.

[0494] 24 is a cross-sectional view showing a semiconductor device 1E according to a fifth embodiment. Referring to Fig. 24, the semiconductor device 1E has a configuration in which the well region 30 is removed from the semiconductor device 1D. Even with this configuration, effects similar to those of the semiconductor device 1D can be achieved.

[0495] Fig. 25 is a plan view showing a semiconductor device 1F according to a sixth embodiment. Fig. 26 is a cross-sectional view taken along line XXVI-XXVI shown in Fig. 25. Referring to Fig. 25 and Fig. 26, the semiconductor device 1F is a semiconductor rectifier having a diode structure Di as an example of a device structure (functional device). The diode structure Di has a vertical structure.

[0496] The semiconductor device 1F includes the aforementioned chip 2. The chip 2 includes a semiconductor substrate 6, a semiconductor layer 7, and a buffer layer 8. The buffer layer 8 includes a low concentration portion 8a, a high concentration portion 8b, and a transition portion 8c. The buffer layer 8 may have any one of the first to thirteenth concentration gradient examples (see FIGS. 3A to 3M).

[0497] The semiconductor device 1F includes the aforementioned active region 20 and peripheral region 21 provided in the semiconductor layer 7. In this embodiment, the active region 20 is a region that includes a device structure (diode structure Di) and generates an output current (forward current). In this embodiment, the peripheral region 21 is a region that does not include a device structure (diode structure Di).

[0498] The semiconductor device 1F includes a plurality of p-type well regions 30 formed in the semiconductor layer 7 in the active region 20. The plurality of well regions 30 have a p-type impurity concentration higher than the n-type impurity concentration of the semiconductor layer 7, and convert the conductivity type of the semiconductor layer 7 from n-type to p-type.

[0499] The multiple well regions 30 are formed in the active region 20 at intervals from the periphery of the first main surface 3. The multiple well regions 30 are formed in the semiconductor layer 7 at intervals from one another in the horizontal direction. The multiple well regions 30 are arranged at intervals in the first direction X in a plan view, and each extends in a strip shape in the second direction Y. The extension direction of the multiple well regions 30 coincides with the off-direction of the SiC single crystal.

[0500] The multiple well regions 30 may extend from the active region 20 to the peripheral region 21 and be formed across the entire first main surface 3. In this case, the multiple well regions 30 may have a portion exposed from at least one of the first to fourth side surfaces 5A to 5D. The multiple well regions 30 may be arranged at intervals in the second direction Y in a plan view and each extend in a strip shape in the first direction X. In this case, the multiple well regions 30 intersect (specifically, are perpendicular to) the off-direction.

[0501] In this embodiment, the multiple well regions 30 extend vertically in the thickness direction of the semiconductor layer 7. The multiple well regions 30 are formed at intervals from the buffer layer 8 (high concentration portion 8 b) toward the first major surface 3, and face the buffer layer 8 with a part of the semiconductor layer 7 interposed therebetween. Each of the multiple well regions 30 has an upper end portion on the first major surface 3 side and a bottom portion on the buffer layer 8 side.

[0502] The upper ends of the multiple well regions 30 may be exposed from the first main surface 3, or may be formed at intervals from the first main surface 3 toward the buffer layer 8. The bottoms of the multiple well regions 30 may have a portion located on the buffer layer 8 (high concentration portion 8b) side relative to the depth position of the intermediate portion of the semiconductor layer 7.

[0503] The bottoms of the multiple well regions 30 may be located closer to the first main surface 3 than the depth position of the intermediate portion of the semiconductor layer 7. The multiple well regions 30 may form a superjunction structure together with the semiconductor layer 7. In this case, depletion layers originating from the multiple well regions 30 are connected to each other in the regions between the multiple well regions 30.

[0504] The well region 30 may have a width greater than 0 μm and less than or equal to 10 μm. The width of the well region 30 may have a value belonging to at least one of the following ranges: greater than 0 μm and less than or equal to 1 μm, 1 μm to 2 μm, 2 μm to 3 μm, 3 μm to 4 μm, 4 μm to 5 μm, 5 μm to 6 μm, 6 μm to 7 μm, 7 μm to 8 μm, 8 μm to 9 μm, and 9 μm to 10 μm.

[0505] The well region 30 may have a depth greater than 0 μm and less than or equal to 5 μm. The depth of the well region 30 may have a value belonging to at least one of the following ranges: greater than 0 μm and less than or equal to 0.5 μm, 0.5 μm to 1 μm, 1 μm to 1.5 μm, 1.5 μm to 2 μm, 2 μm to 2.5 μm, 2.5 μm to 3 μm, 3 μm to 3.5 μm, 3.5 μm to 4 μm, 4 μm to 4.5 μm, and 4.5 μm to 5 μm.

[0506] The semiconductor device 1F includes a p-type outer well region 35 formed in the outer peripheral region 21 in a surface layer portion of the first main surface 3. The outer well region 35 has a p-type impurity concentration higher than the n-type impurity concentration of the semiconductor layer 7, and converts the conductivity type of the semiconductor layer 7 from n-type to p-type. The p-type impurity concentration of the outer well region 35 may be higher or lower than the p-type impurity concentration of the well region 30.

[0507] The outer well region 35 extends in a layered manner along the first main surface 3. The outer well region 35 is formed at an interval from the periphery of the first main surface 3 toward the inward side of the first main surface 3. The outer well region 35 extends in a band shape along the periphery of the first main surface 3 (the periphery of the active region 20) in a plan view.

[0508] In this embodiment, the outer well region 35 is formed in a polygonal ring shape (a square ring shape in this embodiment) having four sides parallel to the periphery of the first main surface 3 in a plan view, and surrounds the inner portion (plurality of well regions 30) of the first main surface 3. The outer well region 35 has an inner edge portion on the inner side of the first main surface 3 and an outer edge portion on the periphery side of the first main surface 3. The inner edge portion of the outer well region 35 defines the boundary between the active region 20 and the outer peripheral region 21.

[0509] The outer well region 35 may be connected to multiple well regions 30, or may be formed at intervals from the multiple well regions 30. The outer well region 35 may have an edge portion that connects the portion extending in a strip shape in the first direction X and the portion extending in a strip shape in the second direction Y in an arc shape (preferably a quarter arc shape).

[0510] In this embodiment, the outer well region 35 has a depth smaller than that of the well region 30. The depth of the outer well region 35 may be approximately equal to the depth of the well region 30. The depth of the outer well region 35 may be greater than the depth of the well region 30.

[0511] Similar to the semiconductor device 1A, the semiconductor device 1F includes one or more (in this embodiment, multiple) p-type field regions 37 formed in the surface layer portion of the first main surface 3 in the peripheral region 21 (the peripheral portion of the first main surface 3). The above description applies to the multiple field regions 37.

[0512] The semiconductor device 1F includes the above-mentioned interlayer film 10 that selectively covers the first main surface 3. The interlayer film 10 selectively covers the first main surface 3 in the peripheral region 21. The interlayer film 10 covers the outer well region 35 and the plurality of field regions 37 in the peripheral region 21. In this embodiment, the interlayer film 10 is continuous with the periphery of the first main surface 3. Of course, the interlayer film 10 may be formed at a distance from the periphery of the first main surface 3, so that the semiconductor layer 7 is exposed from the periphery of the first main surface 3.

[0513] The interlayer film 10 has a contact opening 11 that exposes the first main surface 3 in the active region 20. In this form, the contact opening 11 exposes the semiconductor layer 7 and the multiple well regions 30. In this form, the contact opening 11 has an opening wall positioned above the outer well region 35, and exposes the inner edge of the outer well region 35.

[0514] The semiconductor device 1F includes a first electrode 12 disposed on the first main surface 3. In this embodiment, the first electrode 12 is formed as an anode electrode 58. The anode electrode 58 may also be referred to as a "first main surface electrode," a "first terminal (electrode)," a "first pad (electrode)," or the like.

[0515] The anode electrode 58 is disposed at a distance from the periphery of the first main surface 3. The anode electrode 58 is formed in a polygonal shape (a quadrilateral shape in this embodiment) that follows the periphery of the first main surface 3 in a plan view. The anode electrode 58 extends from above the interlayer film 10 into the contact opening 11, and is mechanically and electrically connected to the first main surface 3 within the contact opening 11.

[0516] Specifically, the anode electrode 58 forms a Schottky junction with the semiconductor layer 7, and forms ohmic contact with the multiple well regions 30 and the outer well region 35. This forms a diode structure Di that includes the anode electrode 58 as an anode region and the semiconductor layer 7 as a cathode region. In this embodiment, the diode structure Di is a Schottky barrier diode structure.

[0517] When multiple well regions 30 are formed at intervals from the first main surface 3 toward the buffer layer 8, the anode electrode 58 is mechanically and electrically connected to the semiconductor layer 7 and the outer well region 35 within the contact opening 11.

[0518] The semiconductor device 1F includes the aforementioned second electrode 17 disposed on the second main surface 4. In this embodiment, the second electrode 17 is formed as a cathode electrode 59. The cathode electrode 59 may also be referred to as a "second main surface electrode," a "second terminal (electrode)," a "second pad (electrode)," or the like. The cathode electrode 59 may cover the entire second main surface 4 so as to be continuous with the periphery of the second main surface 4 (first to fourth side surfaces 5A to 5D).

[0519] The cathode electrode 59 may cover an inner portion of the second main surface 4 at a distance from the periphery of the second main surface 4, leaving the periphery of the second main surface 4 exposed. The cathode electrode 59 is mechanically and electrically connected to the semiconductor substrate 6. The cathode electrode 59 forms an ohmic contact with the semiconductor substrate 6. The cathode electrode 59, together with the anode electrode 58, forms a current path through the chip 2 (semiconductor substrate 6, semiconductor layer 7, and buffer layer 8).

[0520] The breakdown voltage that can be applied between the anode electrode 58 and the cathode electrode 59 (between the first main surface 3 and the second main surface 4) may be 500 V or more and 3000 V or less. The breakdown voltage may have a value that belongs to at least one of the ranges of 500 V or more and 750 V or less, 750 V or more and 1000 V or less, 1000 V or more and 1250 V or less, 1250 V or more and 1500 V or less, 1500 V or more and 1750 V or less, 1750 V or more and 2000 V or less, 2000 V or more and 2250 V or less, 2250 V or more and 2500 V or less, and 2500 V or more and 3000 V or less.

[0521] As described above, the semiconductor device 1F includes an n-type (first conductivity type) semiconductor substrate 6 (substrate), an n-type semiconductor layer 7, an n-type buffer layer 8, and a first electrode 12 (anode electrode 58). The semiconductor substrate 6 has a first concentration C1. The semiconductor layer 7 has a second concentration C2 less than the first concentration C1 and is stacked on the semiconductor substrate 6. The buffer layer 8 is interposed between the semiconductor substrate 6 and the semiconductor layer 7.

[0522] The buffer layer 8 includes a low-concentration portion 8a and a high-concentration portion 8b. The low-concentration portion 8a has a third concentration C3 less than the first concentration C1 and is formed in a region on the semiconductor substrate 6 side. The high-concentration portion 8b has a fourth concentration C4 higher than the third concentration C3 and is formed in a region on the semiconductor layer 7 side. The first electrode 12 forms a Schottky junction with the semiconductor layer 7.

[0523] This configuration provides a novel semiconductor device 1F. For example, in this semiconductor device 1F, when holes (minority carriers) are supplied to the semiconductor layer 7, the holes recombine with electrons (majority carriers) in the high-concentration region 8b, reducing the number of holes reaching the low-concentration region 8a. This reduces the number of holes reaching the boundary between the semiconductor substrate 6 and the buffer layer 8, suppressing the recombination of holes and electrons at basal plane dislocation defects. As a result, bipolar degradation due to basal plane dislocation defects is suppressed.

[0524] Such a configuration is effective in suppressing an increase in the thickness of the buffer layer 8 and an increase in the impurity concentration of the entire buffer layer 8. This appropriately increases the uniformity of the impurity concentration and layer thickness of the buffer layer 8, allowing holes and electrons to appropriately recombine in the high-concentration portion 8 b. In addition, the manufacturing cost of the buffer layer 8 is reduced.

[0525] From another perspective, the semiconductor device 1F includes an n-type (first conductivity type) semiconductor substrate 6 (substrate), an n-type semiconductor layer 7, an n-type buffer layer 8, and a p-type well region 30 (impurity region 9). The semiconductor substrate 6 has a first concentration C1. The semiconductor layer 7 has a second concentration C2 less than the first concentration C1 and is stacked on the semiconductor substrate 6. The buffer layer 8 is interposed between the semiconductor substrate 6 and the semiconductor layer 7.

[0526] The buffer layer 8 includes a low-concentration portion 8a and a high-concentration portion 8b. The low-concentration portion 8a has a third concentration C3 less than the first concentration C1, and is formed in a region on the semiconductor substrate 6 side. The high-concentration portion 8b has a fourth concentration C4 higher than the third concentration C3, and is formed in a region on the semiconductor layer 7 side. The well region 30 is formed in the semiconductor layer 7.

[0527] This configuration provides a novel semiconductor device 1F. For example, in this semiconductor device 1F, holes (minority carriers) supplied from well region 30 recombine with electrons (majority carriers) in high-concentration region 8b, reducing the number of holes reaching low-concentration region 8a. This reduces the number of holes reaching the boundary between semiconductor substrate 6 and buffer layer 8, suppressing the recombination of holes and electrons at basal plane dislocation defects. As a result, bipolar degradation due to basal plane dislocation defects is suppressed.

[0528] From another perspective, the semiconductor device 1F includes an n-type (first conductivity type) semiconductor substrate 6 (substrate), an n-type semiconductor layer 7, an n-type buffer layer 8, and a p-type outer well region 35 (impurity region 9). The semiconductor substrate 6 has a first concentration C1. The semiconductor layer 7 has a second concentration C2 less than the first concentration C1 and is stacked on the semiconductor substrate 6. The buffer layer 8 is interposed between the semiconductor substrate 6 and the semiconductor layer 7.

[0529] The buffer layer 8 includes a low-concentration portion 8a and a high-concentration portion 8b. The low-concentration portion 8a has a third concentration C3 less than the first concentration C1, and is formed in a region on the semiconductor substrate 6 side. The high-concentration portion 8b has a fourth concentration C4 higher than the third concentration C3, and is formed in a region on the semiconductor layer 7 side. The outer well region 35 is formed in the semiconductor layer 7 at the periphery of the semiconductor layer 7.

[0530] This configuration provides a novel semiconductor device 1F. For example, in this semiconductor device 1F, holes (minority carriers) supplied from the outer well region 35 recombine with electrons (majority carriers) in the high-concentration region 8b, reducing the number of holes reaching the low-concentration region 8a. This reduces the number of holes reaching the boundary between the semiconductor substrate 6 and the buffer layer 8, suppressing the recombination of holes and electrons at basal plane dislocation defects. As a result, bipolar degradation caused by basal plane dislocation defects is suppressed.

[0531] 27 is a plan view showing a semiconductor device 1G according to the seventh embodiment. Referring to Fig. 27, the semiconductor device 1G has a configuration in which the well region 30 is removed from the semiconductor device 1F. Even with this configuration, the same effects as those of the semiconductor device 1F regarding the outer well region 35 can be achieved.

[0532] Fig. 28 is a perspective view showing the semiconductor package 61. Fig. 29 is a plan view showing the semiconductor package 61. Fig. 30 is a front view showing the semiconductor package 61. Fig. 31 is a bottom view 64 showing the semiconductor package 61. Fig. 32 is a plan view showing the internal structure of the semiconductor package 61. Fig. 33 is a plan view showing further internal structure of the semiconductor package 61.

[0533] Figure 34 is a cross-sectional view taken along line XXXIV-XXXIV shown in Figure 32. Figure 35 is a cross-sectional view taken along line XXXV-XXXV shown in Figure 32. Figure 36 is a cross-sectional view taken along line XXXVI-XXXVI shown in Figure 32. Figure 37 is a cross-sectional view taken along line XXXVII-XXXVII shown in Figure 32. Figure 38 is an enlarged cross-sectional view showing a main part of Figure 34. Figure 39 is an enlarged cross-sectional view showing another main part of Figure 34. Figure 40 is an enlarged cross-sectional view showing another main part of Figure 35.

[0534] 28 to 40, in this form, semiconductor package 61 is a power conversion device that converts DC power into AC power, and is electrically connected to a rotating device such as a polyphase AC motor M. The power conversion device may also be called an "inverter device."

[0535] The semiconductor package 61 includes an insulating package body 62. The package body 62 includes a matrix resin and a plurality of fillers. The matrix resin may include a coloring material such as carbon black. The matrix resin may include a thermosetting resin. The matrix resin may include at least one of an epoxy resin, a phenolic resin, and a polyimide resin.

[0536] The plurality of fillers may be composed of either or both of spherical objects made of an insulating material and amorphous objects made of an insulating material. The amorphous objects may have random shapes other than spheres, such as granular, chipped, or crushed pieces. The plurality of fillers may contain at least one of ceramic, oxide, and nitride. The plurality of fillers may contain silicon oxide particles (silica particles). The particle size of the plurality of fillers may be uniform or non-uniform.

[0537] The package body 62 includes a top surface 63, a bottom surface 64, and first to fourth side walls 65A to 65D. The top surface 63 and the bottom surface 64 are formed in a quadrangular shape (in this embodiment, a rectangular shape extending in the first direction X) in a plan view. The first side wall 65A extends in the first direction X. The second side wall 65B is connected to the first side wall 65A and extends in the second direction Y. The third side wall 65C is connected to the second side wall 65B and extends in the first direction X. The fourth side wall 65D is connected to the first side wall 65A and the third side wall 65C and extends in the second direction Y.

[0538] Hereinafter, the second side wall 65B side may be referred to as one side in the first direction X, and the fourth side wall 65D side may be referred to as the other side in the first direction X. Furthermore, the first side wall 65A side may be referred to as one side in the second direction Y, and the third side wall 65C side may be referred to as the other side in the second direction Y.

[0539] The semiconductor package 61 includes a support substrate 70 disposed within a package body 62. The support substrate 70 may also be referred to as a "die pad." The support substrate 70 includes an insulating substrate 71, a first main electrode 73, and a second main electrode 74. The insulating substrate 71 may include either or both of an inorganic insulator and an organic insulator. The insulating substrate 71 may also include a ceramic such as aluminum nitride or a resin such as an epoxy resin.

[0540] The insulating substrate 71 is disposed in the region between the top surface 63 and the bottom surface 64 within the package body 62. The insulating substrate 71 extends substantially parallel to the top surface 63 and the bottom surface 64. The insulating substrate 71 has an upper surface on the top surface 63 side and a lower surface on the bottom surface 64 side.

[0541] The first main electrode 73 may contain either or both of pure copper and a copper alloy. The first main electrode 73 is disposed in the form of a film, layer, or plate on the upper surface of the insulating substrate 71, and is sealed by the package body 62. The first main electrode 73 forms the upper surface of the support substrate 70. The first main electrode 73 is disposed at a distance from the periphery of the insulating substrate 71, exposing the periphery of the upper surface of the insulating substrate 71.

[0542] The first main electrode 73 includes a first electrode portion 75 and a second electrode portion 76. The first electrode portion 75 is disposed in an area on one side in the first direction X (the second side wall 65B side) on the upper surface of the insulating substrate 71. The first electrode portion 75 is formed in a quadrangular shape in a plan view.

[0543] The second electrode portion 76 is disposed on the upper surface of the insulating substrate 71 in a region on the other side in the first direction X (toward the fourth side wall 65D) at a distance from the first electrode portion 75. The second electrode portion 76 has a rectangular shape in a plan view. The second electrode portion 76 is mechanically and electrically separated from the first electrode portion 75 by the package body 62 sealed in the region between the first electrode portion 75 and the second electrode portion 76.

[0544] The second main electrode 74 may contain either or both of pure copper and copper alloy. The conductive material of the second main electrode 74 may be the same as or different from the conductive material of the first main electrode 73. The second main electrode 74 is disposed in the form of a film, layer, or plate on the lower surface of the insulating substrate 71 inside the package body 62, and forms the lower surface of the support substrate 70.

[0545] The second main electrode 74 is disposed at a distance from the periphery of the insulating substrate 71, and exposes the periphery of the lower surface of the insulating substrate 71. The second main electrode 74 faces the first main electrode 73 across the insulating substrate 71. The second main electrode 74 has a portion facing the first electrode portion 75 across the insulating substrate 71, and a portion facing the second electrode portion 76 across the insulating substrate 71.

[0546] The second main electrode 74 is exposed from the bottom surface 64. Specifically, a part or the entire lower surface of the second main electrode 74 is exposed from the bottom surface 64. The second main electrode 74 may be recessed from the bottom surface 64 toward the top surface 63, or may protrude outward (downward) from the bottom surface 64.

[0547] In this embodiment, the support substrate 70 is configured as a DBC substrate (Direct Bonded Copper substrate) by an insulating substrate 71, a first main electrode 73, and a second main electrode 74. Portions of the insulating substrate 71 that are exposed from the first main electrode 73 and the second main electrode 74 are sealed by the package body 62.

[0548] That is, the inner portion and peripheral portion of the upper surface of the insulating substrate 71 are sealed by the package body 62, and the peripheral portion of the lower surface of the insulating substrate 71 is sealed by the package body 62. As a result, the insulating substrate 71 is sandwiched between the package bodies 62 from above and below.

[0549] The semiconductor package 61 includes one or more (in this embodiment, multiple) devices DV arranged on a support substrate 70 within a package body 62. The multiple devices DV may each be a semiconductor switching device or a semiconductor rectifying device. The semiconductor switching device may be any one of the semiconductor devices 1A to 1E described above. The semiconductor rectifying device may be any one of the semiconductor devices 1X, 1F to 1G described above.

[0550] In this embodiment, the plurality of devices DV are each made up of the same type of semiconductor switching device, and are each configured by one of the semiconductor devices 1A to 1E. Each of the plurality of devices DV includes a main source electrode 43a, a first sub-source electrode 43b, a second sub-source electrode 43c, a gate electrode 45, and a drain electrode 49.

[0551] The multiple devices DV are selectively arranged on the first main electrode 73 (first electrode portion 75 and second electrode portion 76) and are sealed by the package body 62 on the support substrate 70. The multiple devices DV include multiple (four in this embodiment) first devices DV1 arranged on the first electrode portion 75 and multiple (four in this embodiment) second devices DV2 arranged on the second electrode portion 76.

[0552] The number of first devices DV1 may be 1, 2, 3, 4, 5, 6, 7, 8, 9, or 10. Of course, the number of first devices DV1 may be 11 or more and 20 or less. The number of second devices DV2 may be 1, 2, 3, 4, 5, 6, 7, 8, 9, or 10. Of course, the number of second devices DV2 may be 11 or more and 20 or less. The number of second devices DV2 may be the same as or different from the number of first devices DV1.

[0553] The multiple first devices DV1 are arranged in a row on the first electrode portion 75 at intervals in the second direction Y, with the drain electrode 49 facing the first electrode portion 75. The multiple first devices DV1 are arranged with the gate electrode 45, the first sub-source electrode 43 b, and the second sub-source electrode 43 c facing the second sidewall 65B.

[0554] The drain electrodes 49 of the multiple first devices DV1 are mechanically and electrically connected to the first electrode portion 75 via a metal bonding material MP. The metal bonding material MP may contain either or both of solder and metal paste. The solder may be lead-free solder. The metal paste may be copper paste, silver paste, or gold paste. The metal bonding material MP may contain a sintered body of metal particles.

[0555] The second devices DV2 are arranged in a row on the second electrode portion 76 at intervals in the second direction Y, with the drain electrodes 49 facing the second electrode portion 76. The second devices DV2 are arranged with the gate electrodes 45, the first sub-source electrodes 43 b, and the second sub-source electrodes 43 c facing the fourth sidewall 65D. The second devices DV2 face the first devices DV1 in a one-to-one correspondence in the first direction X.

[0556] The drain electrodes 49 of the plurality of second devices DV2 are electrically connected to the second electrode portion 76 via a metal bonding material MP. The metal bonding material MP may contain either or both of solder and metal paste. The solder may be lead-free solder. The metal paste may be copper paste, silver paste, or gold paste. The metal bonding material MP may contain a sintered body of metal particles.

[0557] The semiconductor package 61 includes a plurality of plate-shaped terminals 77-79 extending inside and outside the package body 62. Each of the plurality of terminals 77-79 is made of a metal plate. The plurality of terminals 77-79 may contain at least one of copper, iron, titanium, and nickel. The plurality of terminals 77-79 may also contain an alloy containing at least one of copper, iron, titanium, and nickel. The plurality of terminals 77-79 may also include a plating film covering part or all of the outer surface of the metal plate. The plating film may include at least one of Ni plating film, Pd plating film, and Au plating film.

[0558] The multiple terminals 77 to 79 are selectively electrically connected to the multiple devices DV within the package body 62. The multiple terminals 77 to 79 include one or more (one in this embodiment) positive terminals 77 (first terminals), one or more (two in this embodiment) negative terminals 78 (second terminals), and one or more (two in this embodiment) output terminals 79 (third terminals).

[0559] The positive terminal 77 is a high-potential terminal. For example, a high potential (drain potential) of the DC power supply voltage to be converted into power is applied to the positive terminal 77. The positive terminal 77 is disposed on the second side wall 65B side of the package body 62. In this embodiment, the positive terminal 77 is disposed in the center of the second side wall 65B within the thickness range between the top surface 63 and the support substrate 70.

[0560] The positive electrode terminal 77 is mechanically and electrically connected to the first electrode portion 75 within the package body 62, and is electrically connected to the drain electrodes 49 of the plurality of first devices DV1 via the first electrode portion 75. The positive electrode terminal 77 extends in a strip shape from the first electrode portion 75 toward the second side wall 65B, penetrates the second side wall 65B, and is drawn out to the outside of the package body 62.

[0561] That is, the positive electrode terminal 77 has a base end (connection portion) located inside the package body 62 and a tip end located outside the package body 62. The tip end of the positive electrode terminal 77 has a portion that extends approximately parallel to the top surface 63 and the bottom surface 64.

[0562] The positive electrode terminal 77 may be bonded, welded, or crimped to the first electrode portion 75. For example, the positive electrode terminal 77 may be bonded to the first electrode portion 75 by a metal bonding material MP (such as the above-mentioned solder or metal paste). The positive electrode terminal 77 may be welded to the first electrode portion 75. The positive electrode terminal 77 may be crimped to the first electrode portion 75 by a crimping member.

[0563] The negative electrode terminals 78 are low-potential terminals. For example, a low potential (source potential) of the DC power supply voltage to be converted into power is applied to the negative electrode terminals 78. The negative electrode terminals 78 are arranged on the same side as the positive electrode terminal 77. In other words, the negative electrode terminals 78 are arranged on the second side wall 65B side of the package body 62.

[0564] In this embodiment, the multiple negative electrode terminals 78 are respectively arranged at both end portions of the second side wall 65B in the second direction Y, and sandwich the positive electrode terminal 77 from both sides in the second direction Y. Specifically, one negative electrode terminal 78 is arranged at a distance from the positive electrode terminal 77 toward the first side wall 65A, and the other negative electrode terminal 78 is arranged at a distance from the positive electrode terminal 77 toward the third side wall 65C. The other negative electrode terminal 78 faces the one negative electrode terminal 78 with the positive electrode terminal 77 in between in a plan view.

[0565] The plurality of negative electrode terminals 78 are arranged in the thickness range between the top surface 63 and the support substrate 70. Specifically, the plurality of negative electrode terminals 78 are arranged spaced apart from the top surface 63 of the package body 62 and the upper surface of the first main electrode 73, and do not have an electrical connection portion to the first main electrode 73. The plurality of negative electrode terminals 78 may have a portion facing a portion of the support substrate 70 (for example, one or both of the insulating substrate 71 and the first electrode portion 75) with a portion of the package body 62 interposed therebetween.

[0566] The negative electrode terminals 78 extend in a strip shape from inside the package body 62 toward the second side wall 65B, and penetrate the second side wall 65B to be drawn out to the outside of the package body 62. In other words, the negative electrode terminals 78 have base ends positioned inside the package body 62 and tip ends positioned outside the package body 62. The tip ends of the negative electrode terminals 78 have portions that extend approximately parallel to the top surface 63 and the bottom surface 64 of the package body 62.

[0567] The multiple output terminals 79 are terminals through which AC power converted by the multiple devices DV is output. The multiple output terminals 79 are arranged on the side walls other than the second side wall 65B (at least one of the first side wall 65A, the third side wall 65C, and the fourth side wall 65D). In this embodiment, the multiple output terminals 79 are arranged on the fourth side wall 65D side and face either or both of the positive terminal 77 and the negative terminal 78 across the package body 62.

[0568] In this embodiment, the multiple output terminals 79 are respectively arranged at both ends of the fourth side wall 65D in the second direction Y and face each other in the first direction X. One output terminal 79 is arranged on the first side wall 65A side and faces one negative terminal 78 in the first direction X with the package body 62 in between. The other output terminal 79 is arranged on the third side wall 65C side and faces the other negative terminal 78 in the first direction X with the package body 62 in between.

[0569] The plurality of output terminals 79 are arranged in the thickness range between the top surface 63 and the support substrate 70. The plurality of output terminals 79 are mechanically and electrically connected to the second electrode portion 76 within the package body 62, and are electrically connected to the drain electrodes 49 of the plurality of second devices DV2 via the second electrode portion 76. The plurality of output terminals 79 extend in a strip shape from the second electrode portion 76 toward the fourth side wall 65D, and are drawn out to the outside of the package body 62 by penetrating the fourth side wall 65D.

[0570] That is, the plurality of output terminals 79 have base ends (connection portions) located inside the package body 62 and tip ends located outside the package body 62. The tip ends of the plurality of output terminals 79 have portions that extend substantially parallel to the top surface 63 and the bottom surface 64.

[0571] The plurality of output terminals 79 may be bonded, welded, or crimped to the second electrode portion 76. For example, the plurality of output terminals 79 may be bonded to the second electrode portion 76 by a metal bonding material MP (such as the above-mentioned solder or metal paste). The plurality of output terminals 79 may be welded to the second electrode portion 76. The plurality of output terminals 79 may be crimped to the second electrode portion 76 by a crimping member.

[0572] The semiconductor package 61 includes one or more (two in this embodiment) recesses 80 recessed in the second side wall 65B toward the fourth side wall 65D. The recesses 80 are respectively formed in regions between the positive electrode terminal 77 and the negative electrode terminals 78. The recesses 80 may be recessed in a rectangular or arc shape. The recesses 80 are formed throughout the thickness range of the top surface 63 and the bottom surface 64 in the vertical direction Z.

[0573] The semiconductor package 61 includes a conductive (metallic) first connection member 81 disposed within the package body 62. The first connection member 81 may be referred to as a "first conductive plate" or a "first metal member (plate)." The first connection member 81 may be a metal clip. The first connection member 81 may include pure copper or a copper alloy.

[0574] The first connection member 81 is disposed on the top surface 63 side of the multiple devices DV and is sealed by the package body 62. Specifically, the first connection member 81 is disposed on the second electrode portion 76 and the main source electrodes 43 a of the multiple first devices DV1 and is electrically connected to the second electrode portion 76 and the main source electrodes 43 a of the multiple first devices DV1.

[0575] The first connection member 81 includes a first main body portion 81a, a plurality of first arm portions 81b, and one or a plurality (a plurality in this embodiment) of second arm portions 81c. The first main body portion 81a is disposed so as to straddle the first electrode portion 75 and the second electrode portion 76, and extends in a strip shape in the second direction Y. A portion of the first main body portion 81a may partially overlap the plurality of first devices DV1 in the vertical direction Z. Of course, the first main body portion 81a does not have to overlap the plurality of first devices DV1 in the vertical direction Z.

[0576] The first main body portion 81a has a plurality of through holes that overlap in the vertical direction Z with an area between the first electrode portion 75 and the second electrode portion 76. The first connection member 81 is sandwiched by parts of the package main body 62 from above and below via the plurality of through holes.

[0577] The multiple first arm portions 81b are respectively drawn out from the first main body portion 81a onto the multiple first devices DV1 and face the multiple first devices DV1 in the vertical direction Z. The multiple first arm portions 81b are electrically connected to the main source electrodes 43a of the multiple first devices DV1, respectively. One or multiple (two in this embodiment) first arm portions 81b may be drawn out toward a corresponding one of the main source electrodes 43a.

[0578] The first arm portions 81b each have a base end on the first body portion 81a side and a tip end on the corresponding main source electrode 43a side. The base ends of the first arm portions 81b may be bent from the first body portion 81a toward the main source electrode 43a side. The tip ends of the first arm portions 81b may be positioned closer to the main source electrode 43a than the first body portion 81a (base end).

[0579] The first arm portions 81b may be mechanically and electrically connected to the corresponding main source electrodes 43a via a metal bonding material MP (such as the aforementioned solder or metal paste). It is preferable that the metal bonding material MP on the first arm portion 81b side does not contain a sintered body of metal particles.

[0580] The plurality of second arm portions 81c are drawn out from the first main body portion 81a onto the second electrode portion 76 and are electrically connected to the second electrode portion 76. The plurality of second arm portions 81c have a base end portion on the first main body portion 81a side and a tip end portion on the second electrode portion 76 side. The base ends of the plurality of second arm portions 81c may be bent from the first main body portion 81a toward the second electrode portion 76 side. The tip ends of the plurality of second arm portions 81c may be positioned closer to the second electrode portion 76 than the first main body portion 81a (base end).

[0581] The second arm portions 81c may be mechanically and electrically connected to the second electrode portion 76 via a metal bonding material MP (for example, the above-mentioned solder or metal paste). It is preferable that the metal bonding material MP on the second arm portion 81c side does not contain a sintered body of metal particles.

[0582] The semiconductor package 61 includes a conductive (metallic) second connection member 82 disposed within the package body 62. The second connection member 82 may be referred to as a "second connection plate," a "second metal member (plate)," or the like. The second connection member 82 may be a metal clip. The second connection member 82 may contain pure copper or a copper alloy. The second connection member 82 may be made of the same or a different conductive material as the first connection member 81.

[0583] The second connection member 82 is disposed on the top surface 63 side with respect to the multiple devices DV, and is sealed by the package body 62. Specifically, the second connection member 82 is disposed on the top surface 63 side with respect to the first connection member 81, and has a portion that faces the first connection member 81 via a portion of the package body 62. The second connection member 82 is electrically insulated from the first connection member 81 by a portion of the package body 62.

[0584] The second connection member 82 is arranged on the main source electrodes 43a and the negative terminals 78 of the plurality of second devices DV2 and is electrically connected to the main source electrodes 43a and the negative terminals 78 of the plurality of second devices DV2.

[0585] The second connecting member 82 includes a second main body portion 82a, one or more (five in this embodiment) third arm portions 82b, and multiple (two in this embodiment) fourth arm portions 82c. The second main body portion 82a is disposed in an area on the top surface 63 side of the first connecting member 81 and extends in a strip shape in the second direction Y. The second main body portion 82a faces the first main body portion 81a with a portion of the package body 62 therebetween, and is electrically insulated from the first main body portion 81a by a portion of the package body 62.

[0586] The second main body portion 82a may have a portion that overlaps with either or both of the first main body portion 81a and the first arm portion 81b in the vertical direction Z. A part of the second main body portion 82a may have a portion that partially overlaps with the multiple first devices DV1 in the vertical direction Z. The second main body portion 82a does not have to overlap with the multiple first devices DV1 in the vertical direction Z.

[0587] The plurality of third arm portions 82b are respectively drawn out from the second main body portion 82a onto the plurality of second devices DV2 and face the plurality of second devices DV2 in the vertical direction Z. In this embodiment, the plurality of third arm portions 82b are respectively drawn out from the second main body portion 82a to both sides of the plurality of second devices DV2.

[0588] The third arm portions 82b are arranged offset in the second direction Y from the through holes so as not to overlap with part or all of the through holes of the first connection member 81 in the vertical direction Z. The third arm portions 82b are electrically connected to the main source electrodes 43a of the second devices DV2, respectively.

[0589] Each of the multiple third arm portions 82b has an arm main body portion 82d and one or more arm connection portions 82e. The arm main body portion 82d is pulled out in a strip shape from the second main body portion 82a in the first direction X. The arm main body portion 82d may have one or more recesses recessed toward the second direction Y in a plan view.

[0590] In this embodiment, the two outermost arm main bodies 82d arranged at both ends in the second direction Y have two recesses, and the arm main bodies 82d arranged on the inside do not have any recesses. The recesses may be recessed in a rectangular or arc shape in a plan view.

[0591] One or more arm connection portions 82e are extended from the tip of the arm main body portion 82d toward one side of the second direction Y and / or the other side of the second direction Y toward the main source electrode 43a of the adjacent second device DV2.

[0592] Specifically, the two outermost third arm portions 82b each include a single arm connection portion 82e extended toward the main source electrode 43a of one adjacent second device DV2, and the inner third arm portions 82b each include two arm connection portions 82e extended toward the main source electrodes 43a of the two adjacent second devices DV2.

[0593] The arm connection portions 82e each include a base end portion on the arm main body portion 82d side and a base end portion on the main source electrode 43a side. The base ends of the arm connection portions 82e may be bent from the arm main body portion 82d toward the main source electrode 43a side. The tip ends of the arm connection portions 82e may be positioned closer to the main source electrode 43a than the arm main body portion 82d (base end).

[0594] The third arm portions 82b may be mechanically and electrically connected to the corresponding main source electrodes 43a via a metal bonding material MP (such as the aforementioned solder or metal paste). It is preferable that the metal bonding material MP on the third arm portion 82b side does not contain a sintered body of metal particles.

[0595] The plurality of fourth arm portions 82c are respectively drawn out from the second main body portion 82a onto the plurality of negative electrode terminals 78 in a one-to-one correspondence and electrically connected to the plurality of negative electrode terminals 78. Each of the plurality of fourth arm portions 82c has a narrow portion on the second main body portion 82a side and a wide portion on the negative electrode terminal 78 side. The plurality of fourth arm portions 82c may have a uniform width.

[0596] Each of the plurality of fourth arm portions 82c has one or more (one in this embodiment) through-holes in an area (a wide portion in this embodiment) on the side of the negative terminal 78. The second connection member 82 is sealed so as to be sandwiched by parts of the package body 62 from above and below via the plurality of through-holes.

[0597] The plurality of fourth arm portions 82c may be mechanically and electrically connected to the corresponding negative electrode terminals 78 via a metal bonding material MP (for example, the above-mentioned solder or metal paste). It is preferable that the metal bonding material MP on the fourth arm portion 82c side does not contain a sintered body of metal particles.

[0598] The semiconductor package 61 includes one or more (multiple in this embodiment) wiring structures 83, 84 arranged in a package body 62. The multiple wiring structures 83, 84 include a first wiring structure 83 on the first electrode portion 75 side and a second wiring structure 84 on the second electrode portion 76 side.

[0599] The first wiring structure 83 is disposed on the first electrode portion 75 and is sealed by the package body 62. The first wiring structure 83 is disposed in an area on the second sidewall 65B side of the multiple first devices DV1 and faces at least one (multiple in this embodiment) first device DV1 in the second direction Y. The first wiring structure 83 includes a portion facing the positive electrode terminal 77 in the second direction Y. The second wiring structure 84 includes portions facing the multiple negative electrode terminals 78 in the second direction Y.

[0600] The first wiring structure 83 includes a first insulating plate 85 (first insulating layer), one or more (plural in this embodiment) first wires 86-91, a first metal layer 92, and one or more (plural in this embodiment) first sleeves 93. The first wiring structure 83 is sealed by the package body 62 except for the interiors of the plurality of first sleeves 93.

[0601] The first insulating plate 85 includes either an inorganic insulator or an organic insulator, or both. The insulating substrate 71 may include at least one of an inorganic insulator (e.g., ceramic) and an organic insulator (e.g., epoxy resin or polyimide resin). The first insulating plate 85 may include an insulator that is the same as or different from that of the insulating substrate 71.

[0602] The first insulating plate 85 is disposed on the first electrode portion 75 and extends flatly along the first electrode portion 75. The first insulating plate 85 may extend in a strip shape in the second direction Y. The first insulating plate 85 has an upper surface on the top surface 63 side and a lower surface on the first electrode portion 75 side. The first insulating plate 85 is disposed on the first electrode portion 75 with a gap therebetween from the periphery of the first electrode portion 75.

[0603] The first wirings 86-91 may contain either or both of pure copper and copper alloy. The first wirings 86-91 are arranged on the upper surface of the first insulating plate 85 at intervals from one another and are sealed by the package body 62. The first wirings 86-91 are electrically isolated by a portion of the package body 62.

[0604] The multiple first wirings 86-91 are arranged at intervals from the periphery of the upper surface of the first insulating plate 85, exposing the periphery of the upper surface of the first insulating plate 85. The layout of the multiple first wirings 86-91 is arbitrary. The multiple first wirings 86-91 may have a quadrangular body region. The body region may be formed in a rectangular shape extending in the first direction X or the second direction Y.

[0605] The first wirings 86 to 91 may each have a line region extending in a strip shape from the main body region. The line region may have either or both a portion extending in the first direction X and a portion extending in the second direction Y.

[0606] The multiple first wirings 86 to 91 include a first inner gate wiring 86 (first wiring), a first outer gate wiring 87 (second wiring), a first monitor wiring 88 (third wiring), a first drain wiring 89 (fourth wiring), a first positive wiring 90 (fifth wiring), and a first negative wiring 91 (sixth wiring).

[0607] The first inner gate wiring 86 is disposed near the plurality of first devices DV1 and extends in a strip shape in the second direction Y. The first outer gate wiring 87 is disposed in a region on the second sidewall 65B side at a distance from the first inner gate wiring 86 in the first direction X and extends in a strip shape in the second direction Y.

[0608] The first monitor wiring 88 is interposed in the region between the first inner gate wiring 86 and the first outer gate wiring 87, and extends in a strip shape in the second direction Y. The first monitor wiring 88 has a portion facing the first inner gate wiring 86 in the first direction X, a portion facing the first inner gate wiring 86 in the second direction Y, a portion facing the first outer gate wiring 87 in the first direction X, and a portion facing the first outer gate wiring 87 in the second direction Y.

[0609] The first drain wiring 89 is arranged in an area on the first sidewall 65A side, spaced apart in the second direction Y from the first inner gate wiring 86 etc. The first positive wiring 90 is arranged in an area on the third sidewall 65C side, spaced apart in the second direction Y from the first inner gate wiring 86 etc. The first negative wiring 91 is arranged in an area on the third sidewall 65C side, spaced apart in the second direction Y from the first positive wiring 90. The arrangements of the first negative wiring 91 and the first positive wiring 90 may be interchanged.

[0610] The first outer gate wiring 87, the first monitor wiring 88, the first drain wiring 89, the first positive wiring 90, and the first negative wiring 91 each have a portion positioned on the same straight line in the second direction Y.

[0611] The first metal layer 92 may include either or both of pure copper and copper alloy. The first metal layer 92 is disposed on the lower surface of the first insulating plate 85. Specifically, the first metal layer 92 is interposed in the region between the first electrode portion 75 and the first insulating plate 85.

[0612] The first metal layer 92 is disposed at a distance from the periphery of the lower surface of the first insulating plate 85, and exposes the periphery of the lower surface of the first insulating plate 85. The first metal layer 92 may be mechanically and electrically connected to the corresponding first electrode portion 75 via a metal bonding material MP (for example, the aforementioned solder or metal paste).

[0613] The first sleeves 93 are configured by metallic cylindrical members extending in the vertical direction Z, and are sealed over their entire circumference by the package body 62. The first sleeves 93 may contain either or both of pure copper and copper alloy.

[0614] The multiple first sleeves 93 are erected on at least one of the multiple first wirings 86 to 91. In this embodiment, the multiple first sleeves 93 are respectively arranged on the first outer gate wiring 87, the first monitor wiring 88, the first drain wiring 89, the first positive wiring 90, and the first negative wiring 91, but are not arranged on the first inner gate wiring 86. In this embodiment, the multiple first sleeves 93 are arranged in a line in the second direction Y at intervals.

[0615] The first metal layers 92 of the first sleeves 93 may be mechanically and electrically connected to the corresponding first wirings 86 to 91 via a metal bonding material MP (for example, the above-mentioned solder or metal paste). The first sleeves 93 are exposed from the top surface 63. That is, the first sleeves 93 define conductive through holes that expose the corresponding first wirings 86 to 91 from the top surface 63.

[0616] The second wiring structure 84 is disposed on the second electrode portion 76 and is sealed by the package body 62. The second wiring structure 84 is disposed in a region on the fourth side wall 65D side with respect to the plurality of second devices DV2 and faces at least one (plurality in this embodiment) second device DV2 in the second direction Y. The second wiring structure 84 includes a portion facing a region between the output terminals 79 in the second direction Y. The second wiring structure 84 includes a portion facing at least one (plurality in this embodiment) output terminal 79 in the second direction Y.

[0617] The second wiring structure 84 includes a second insulating plate 94 (second insulating layer), one or more (plural in this embodiment) second wirings 95-100, a second metal layer 101, and one or more (plural in this embodiment) second sleeves 102. The multiple second wirings 95-100 include a second inner gate wiring 95 (seventh wiring), a second outer gate wiring 96 (eighth wiring), a second monitor wiring 97 (ninth wiring), a second drain wiring 98 (tenth wiring), a second positive wiring 99 (eleventh wiring), and a second negative wiring 100 (twelfth wiring).

[0618] The second wiring structure 84 has a layout that is point-symmetrical to the layout of the first wiring structure 83, except that the second wiring structure 84 does not have the second sleeve 102 for the second drain wiring 98. In other words, the number of second sleeves 102 is less than the number of first sleeves 93. Of course, the second wiring structure 84 may have the second sleeve 102 for the second drain wiring 98.

[0619] In addition, the configuration of the second insulating plate 94, the multiple second wirings 95-100, the second metal layer 101, and the multiple second sleeves 102 can be obtained by replacing "first device DV1" with "second device DV2," "first side wall 65A" with "third side wall 65C," and "second side wall 65B" with "fourth side wall 65D" in the description of the first insulating plate 85, the multiple first wirings 86-91, the first metal layer 92, and the multiple first sleeves 93 of the first wiring structure 83.

[0620] The semiconductor package 61 includes one or more (two in this embodiment) thermistors 103, 104 arranged in the package body 62. The multiple thermistors 103, 104 are sensors that detect the temperature inside the package body 62.

[0621] The plurality of thermistors 103, 104 may be NTC (Negative Temperature Coefficient) thermistors having an electrical characteristic that their resistance value decreases with increasing temperature. The plurality of thermistors 103, 104 include a first thermistor 103 on the first wiring structure 83 side and a second thermistor 104 on the second wiring structure 84 side.

[0622] The first thermistor 103 is disposed on the first positive electrode wiring 90 and the first negative electrode wiring 91, and is electrically connected to the first positive electrode wiring 90 and the first negative electrode wiring 91. The first thermistor 103 is mechanically and electrically connected to the first positive electrode wiring 90 and the first negative electrode wiring 91 via a metal bonding material MP (for example, the above-mentioned solder or metal paste).

[0623] The second thermistor 104 is disposed on the second positive electrode wiring 99 and the second negative electrode wiring 100, and is electrically connected to the second positive electrode wiring 99 and the second negative electrode wiring 100. The second thermistor 104 is mechanically and electrically connected to the second positive electrode wiring 99 and the second negative electrode wiring 100 via a metal bonding material MP (for example, the above-mentioned solder or metal paste).

[0624] The semiconductor package 61 includes a plurality of conductive wires 105-111 disposed within a package body 62. The conductive wires 105-111 may be bonding wires (metal wires). The conductive wires 105-111 may include at least one of gold wires, copper wires, silver wires, and aluminum wires. The conductive wires 105-111 may be different types of metal wires or the same type of metal wires.

[0625] The multiple conductors 105-111 include, on the multiple first device DV1 side, one or more (multiple in this embodiment) first gate conductors 105 (first conductors), one or more (multiple in this embodiment) first gate connection conductors 106 (second conductors), one or more (multiple in this embodiment) first monitor conductors 107 (third conductors), and one or more (one in this embodiment) first drain conductors 108 (fourth conductors).

[0626] The plurality of first gate conductors 105 are connected to the gate electrodes 45 of the plurality of first devices DV1 and the first inner gate wiring 86. One or more first gate conductors 105 may be connected to one gate electrode 45 and one first inner gate wiring 86. The plurality of first gate connection conductors 106 are connected to the first inner gate wiring 86 and the first outer gate wiring 87.

[0627] The plurality o...

Claims

1. A semiconductor device comprising: a substrate of a first conductivity type having a first concentration; a semiconductor layer of a first conductivity type having a second concentration less than the first concentration and stacked on the substrate; and a buffer layer of a first conductivity type interposed between the substrate and the semiconductor layer, the buffer layer including a low concentration portion on the substrate side having a third concentration less than the first concentration and a high concentration portion on the semiconductor layer side having a fourth concentration higher than the third concentration.

2. The semiconductor device according to claim 1, wherein the substrate includes SiC, the semiconductor layer includes SiC, and the buffer layer includes SiC.

3. The semiconductor device according to claim 1 or 2, wherein the substrate has an off-axis angle.

4. The semiconductor device according to claim 3, wherein the off angle is 10° or less.

5. The semiconductor device according to any one of claims 1 to 4, wherein the third concentration is equal to or greater than the second concentration.

6. The semiconductor device according to any one of claims 1 to 4, wherein the third concentration is less than the second concentration.

7. The semiconductor device according to claim 1, wherein the fourth concentration is higher than the second concentration.

8. The semiconductor device according to any one of claims 1 to 7, wherein the fourth concentration is equal to or greater than the first concentration.

9. The semiconductor device according to any one of claims 1 to 7, wherein the fourth concentration is less than the first concentration.

10. A semiconductor device according to any one of claims 1 to 9, wherein the buffer layer includes a transition portion in which the concentration gradually increases from the third concentration to the fourth concentration in a region between the low concentration portion and the high concentration portion.

11. The semiconductor device according to any one of claims 1 to 10, wherein the semiconductor layer is thicker than the buffer layer.

12. The semiconductor device according to any one of claims 1 to 11, wherein the buffer layer has a thickness of 10 μm or less.

13. The semiconductor device according to any one of claims 1 to 12, wherein the semiconductor layer has a thickness of 50 μm or less.

14. The semiconductor device according to any one of claims 1 to 13, wherein the first conductivity type is n-type.

15. The semiconductor device according to any one of claims 1 to 14, further comprising an impurity region of a second conductivity type formed in said semiconductor layer.

16. The semiconductor device according to any one of claims 1 to 15, further comprising a trench electrode type gate structure formed in said semiconductor layer and spaced apart from said buffer layer in the thickness direction.

17. The semiconductor device according to claim 16, further comprising a well region of a second conductivity type formed in said semiconductor layer along a bottom wall of said gate structure.

18. The semiconductor device according to any one of claims 1 to 17, further comprising an electrode electrically connected to the semiconductor layer.

19. The semiconductor device according to claim 18, wherein the electrode has a portion that forms a Schottky junction with the semiconductor layer.

20. The semiconductor device according to any one of claims 1 to 19, further comprising a substrate electrode electrically connected to the substrate.

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