Multi-v th linear fet designs

Abstract

MOSFET architectures that provide a channel having multiple VTH regions within the bounds of a single MOSFET device. At least one VTH region provides a low VTH for the device as a whole. A MOSFET device in accordance with the present invention exhibits high linearity, high drain-to-source current IDS capabilities, and short ON-to-OFF switching times. Embodiments modify the architecture of a single MOSFET so as to purposefully exhibit multiple voltage thresholds VTH in different segments of the device. The modifications effectively change the local VTH of different segments within the channel of the MOSFET by altering the implantation or cross-sectional topology of different regions of the active layer of the MOSFET, altering the implantation of different regions of the interface between the active layer and the gate structure, or altering different regions of the gate structure itself.

Description

Multi-V H Linear FET DesignsCROSS-REFERENCE TO RELATED APPLICATIONS

[0001] The present application claims priority to U.S. Provisional Application No. 63 / 561, 107 filed on March 4, 2024, for “Multi-Vm Linear FET Designs”, the contents of which are incorporated herein by reference in their entirety.TECHNICAL FIELD

[0002] This invention relates to electronic integrated circuits, and more particularly to electronic integrated circuits having metal-oxide-semiconductor field-effect transistors (MOSFETs).BACKGROUND

[0003] Virtually all modern electronic products - including laptop computers, mobile telephones, and electric cars - utilize MOSFET-based integrated circuits (ICs). MOSFET- based ICs may be fabricated on bulk silicon or may be fabricated using a semiconductor-on- insulator (SOI) process, such as silicon-on-insulator, germanium-on-insulator, or silicon / germanium-on-insulator (e.g., a SiGe alloy or a layer of Ge on a layer of Si formed on an insulator).

[0004] A number of architectural variations exist for MOSFETs. As one example, an N- type Extended Drain MOS (NEDMOS) FETs fabricated using SOI processes is a common transistor design capable of handling relatively high drain voltages. FIG. 1 A is a stylized cross- sectional view of a typical prior art SOI IC structure for a single NEDMOS FET 100. The SOI structure includes a substrate 102, a buried-oxide (BOX) insulator layer 104, and an active layer 106 (note that the dimensions for the elements of the SOI IC structure are not to scale; some dimensions have been exaggerated for clarity or emphasis). The substrate 102 is typically a semiconductor material such as silicon. The BOX layer 104 is a dielectric and is often SiO? formed as a “top” surface of the silicon substrate 102. In some embodiments, the BOX layer 104 is formed on an optional trap-rich silicon layer (see FIG. 3B) formed on or in the substrate 102. A trap-rich Si layer mitigates parasitic surface conduction and improves device performance at high frequencies.

[0005] The active layer 106 may include some combination of implants and / or layers that include dopants, dielectrics, polysilicon, conductors, passivation, and other materials to form active and / or passive electronic components and / or mechanical structures. For example, the NEDMOS FET 100 of FIG. 1 A includes an N+ source S, a P+ body region B, a gate structure G, an N- drift region, and an N+ drain D, all bounded by a shallow trench isolation (STI) structure 107. A conductive source contact 112, a conductive gate contact 114, and a conductive drain contact 116, which may be self-aligned silicides (also known as “salicides”), are respectively formed in contact with the source S, the gate structure G, and the drain D. Stylized electrical terminals S, G, and D are shown coupled to the corresponding source contact 112, gate contact 114, and contact 116.

[0006] Note that semiconductor materials are often characterized on a spectrum of electron / hole concentration. An undoped material may be N or P type. N or P type materials doped to have a deficit of electrons or holes are indicated as N- and P-, respectively; an even greater deficit of electrons or holes may be indicated as N— and P— , respectively. N or P type materials doped to have an excess of electrons or holes are indicated as N+ and P+, respectively; an even greater excess of electrons or holes may be indicated as N++ and P++, respectively.

[0007] The illustrated gate structure G includes a conductive layer 108, such as N+ doped polysilicon, atop an insulating gate oxide (GOX) layer 110. In the illustrated example, the gate structure G is surrounded by insulating spacers 118. Part of the gate structure G and the N- drift region are coated with a dielectric 120, such as SiCh, SisN , etc., which in turn is overlaid with a salicide block (SAB) layer 122, such as silicon nitride (SiN). In some embodiments, a lightly-doped drain (LDD) region 124 may be formed underneath the spacer 118 adjacent the source S and / or the drain (only the source-side LDD region 124 is shown in FIG. 1 A). In some embodiments, a doped halo region 126 may be formed between at least portions of the source S and body B. Similarly, in some embodiments, a doped halo region may be formed between at least portions of the drain D and body B (not shown in FIG. 1 A). When the FET 100 is in a conducting (ON) state, a conductive channel is formed within the body B below the gate structure G and between the source S and the drain D.

[0008] The BOX layer 104 and the entire active layer 106 (which may include multiple FETs) may be collectively referred to as a “device region” or “substructure” 130 for convenience (noting that other structures or regions may intrude into the substructure 130 inparticular IC designs). A superstructure 132 of various elements, regions, and structures may be fabricated on or above the substructure 130 in order to implement particular functionality. The superstructure 132 may include, for example, conductive interconnections from the illustrated FET 100 to other components (including other FETs) and / or external contacts, passivation layers, and protective coatings.

[0009] FIG. IB is a top plan view of the prior art SOI IC structure of FIG. 1A. The crosssection shown in FIG. 1 A is along line X-X of FIG. IB. The source S, the gate structure G, and the drain D overlay a field of N+ material 140 in this example, comprising part of the active layer 106. The drift region 141 between the gate structure G and the drain D is shown within a dotted outline.

[0010] The illustrated example shows that the source S is associated with multiple source contacts 112 and the drain D is associated with multiple drain contacts 116, while the gate structure G in this particular example is shown as having a single gate contact 114. In other types ofMOSFETs, the drift region 141 is omitted and the drain contacts 116 may be positioned closer to the gate structure G. Also shown in FIG. IB is the top side of a body contact region 142 having an associated conductive body contact 144. In the illustrated example, the body contact region 142 comprises a P+ region formed in electrical contact with the P- body B to provide a fourth terminal to the FET 100.

[0011] In many applications, such as power amplifiers and low-noise amplifiers (LNAs), linearity is an important design goal. The present invention is directed to MOSFET architectures with improved linearity as well as other desirable characteristics compared to conventional MOSFET designs.SUMMARY

[0012] The present invention encompasses a number of MOSFET architectures that provide a channel having multiple VTH regions within the bounds of a single MOSFET device. At least one VTH region provides a low VTH for the device as a whole. A MOSFET device in accordance with the present invention exhibits high linearity, high drain-to-source current IDS capabilities, and short ON-to-OFF switching times.

[0013] Embodiments of the present invention modify the architecture of a single MOSFET so as to purposefully exhibit multiple voltage thresholds VTH in different segments of the device. The modifications effectively change the local VTH of different segments within the channel of the MOSFET by altering the implantation or cross-sectional topology of different regions of the active layer of the MOSFET, altering the implantation of different regions of the interface between the active layer and the gate structure, or altering different regions of the gate structure itself.

[0014] One embodiment encompasses a MOSFET that includes a channel region having multiple VTH regions within the bounds of the MOSFET. Another embodiment encompasses a MOSFET including multiple Vth regions within a channel of the MOSFET. One associated method of fabricating a MOSFET includes providing a substrate, forming an insulator layer on the substrate, forming an active layer on the insulator layer, and modifying at least two segments of a channel region within the active layer to purposefully exhibit different local voltage thresholds VTH. Another associated method of fabricating a MOSFET includes providing a substrate, forming an insulator layer on the substrate, forming an active layer on the insulator layer, forming gate structure overlaying the active layer and defining a channel region, and modifying at least two segments of the channel region to purposefully exhibit different local voltage thresholds VTH.

[0015] The details of one or more embodiments of the invention are set forth in the accompanying drawings and the description below. Other features, objects, and advantages of the invention should be apparent from the description and drawings, and from the claims.DESCRIPTION OF THE DRAWINGS

[0016] FIG. 1 A is a stylized cross-sectional view of a typical prior art SOI IC structure for a single NEDMOS FET.

[0017] FIG. IB is a top plan view of the prior art SOI IC structure of FIG. 1 A.

[0018] FIG. 2A is a double graph of (1) transconductance (left vertical axis) versus VGS and (2) IDS (right vertical axis) versus VGS for one modeled example MOSFET in accordance with the present invention.

[0019] FIG. 2B is a version of the double graph of FIG. 2A showing transconductance versus VGS for a combination of the graph lines 202, 204 of FIG. 2 A.

[0020] FIG. 3A is a top plan view of a first MOSFET that includes multiple VTH regions created by a first type of modification of the MOSFET active area.

[0021] FIG. 3B is a cross-sectional view taken along line Y-Y of FIG. 3A.

[0022] FIG. 3C is a top plan view of a MOSFET that includes multiple VTH regions created by a second type of modification of the MOSFET active area.

[0023] FIG. 3D is a top plan view of a MOSFET that includes multiple VTH regions created by a third type of modification of the MOSFET active area.

[0024] FIG. 4A is a top plan view of a second MOSFET that includes multiple VTH regions created by modification of the shape of the MOSFET active area.

[0025] FIG. 4B is a cross-sectional view taken along line Yl-Yl of FIG. 4A.

[0026] FIG. 4C is a cross-sectional view taken along line Y2-Y2 of FIG. 4A.

[0027] FIG. 4D is a cross-sectional view taken along the X dimension of FIG. 4A.

[0028] FIG. 4E is a stylized perspective view of the MOSFET of FIG. 4A.

[0029] FIG. 5A is a top plan view of a third MOSFET that includes multiple VTH regions created by altering the implantation of different regions of the interface between the active layer and the gate structure.

[0030] FIG. 5B is a cross-sectional view taken along line X-X of FIG. 5A.

[0031] FIG. 6 A is a top plan view of a fourth MOSFET that includes multiple VTH regions.

[0032] FIG. 6B is a cross-sectional view taken along line XI -XI of FIG. 6A.

[0033] FIG. 6C is a cross-sectional view taken along line X2-X2 of FIG. 6A.

[0034] FIG. 7A is a top plan view of a fifth MOSFET that includes multiple VTH regions created by modification of the gate oxide of the gate structure G.

[0035] FIG. 7B is a cross-sectional view taken along line Y-Y of FIG. 7A.

[0036] FIG. 8 is a top plan view of a sixth MOSFET that includes multiple VTH regions created by modification of the work function (WF) of the gate structure G in selected areas.

[0037] FIGS. 9 A and 9B are a process flowchart showing the steps of one subtractive process suitable for some contemporary IC front-end-of-line (FEOL) foundries.

[0038] FIG. 10 is a top plan view of a substrate that may be, for example, a printed circuit board or chip module substrate (e.g., a thin-film tile).

[0039] Like reference numbers and designations in the various drawings indicate like elements unless the context requires otherwise.DETAILED DESCRIPTION

[0040] The present invention encompasses a number of MOSFET architectures that provide a channel having multiple VTH regions within the bounds of a single MOSFET device. At least one VTH region provides a low VTH for the device as a whole. A MOSFET device in accordance with the present invention exhibits high linearity (particularly in low current operational regions), high drain-to-source current IDS capabilities, short ON-to-OFF switching times, and improved output impedance matching.

[0041] In applications in which linearity is an important design goal, such as power amplifiers and LNAs, one conventional approach to enhancing linearity is to use two or more MOSFETs having conduction channels (drain-to-source) coupled in parallel and a common gate coupled to a modulating input signal, where each MOSFET has a different threshold voltage VTH. The result is that one MOSFET with a relatively low VTH will turn ON (conduct) before another MOSFET with a relatively high VTH will turn ON. However, this approach consumes an excessive amount of IC die area and results in higher parasitic capacitances, inductances, and resistances due to the extra MOSFETS and interconnections.

[0042] The present invention overcomes the limitations of multi -MOSFET designs for high linearity circuitry by manipulating the architecture of a single MOSFET so as to purposefully exhibit multiple voltage thresholds VTH in different segments of the device. A multiple VTH MOSFET exhibits multiple transconductance versus gate-to-source voltage (VGS) curves and multiple IDS versus VGS curves. For example, FIG. 2A is a double graph 200 of (1) transconductance (left vertical axis) versus VGS and (2) IDS (right vertical axis) versus VGS for one modeled example MOSFET in accordance with the present invention. Graph line 202 corresponds to one or more segments of the MOSFET having a higher VTH. Graph line 204 corresponds to one or more segments of the MOSFET having a lower VTH. Dashed graph line 206 corresponds to the combined IDS of the MOSFET segments, thereby extending the linear device operation behavior.

[0043] The labels at the top of the graph 200 (“sub-threshold”, “quadratic”, “linear”, “compression”) correspond to conventional operational regions for the aspect of the MOSFET represented by graph line 202. In operational region I, the sub-threshold region, IDS is usually taken to depend exponentially on VGS. In operational region II, as VGS increases, IDS starts to rise quadratically, which implies that the transconductance (gm) should rise linearly. Inoperational region III, for higher values of VGS, short channel effects such as velocity saturation make IDS approach a linear dependence on VGS, with a resulting approximately constant transconductance; MOSFET devices are usually designed to present approximately constant transconductance over a region as wide as possible to achieve better intermodulation distortion (IMD) performance. In operational region IV, for even higher values of VGS, the transconductance will drop and the current compresses, caused by pinch off at the drain and an increase of the drain resistance RD acting as a grounded gate in series with the intrinsic MOSFET transistor.

[0044] The lower VTH graph line 204, while otherwise resembling graph line 202, is essentially shifted to the left, indicating that the low VTH segments of the MOSFET traverse the conventional operational regions at lower VGS values than the high VTH segments of the MOSFET. Thus, for example, the linear range of graph line 204 (lower VTH segments) partly occurs within the quadratic range of graph line 202 (higher VTH segments).

[0045] FIG. 2B is a version of the double graph of FIG. 2A showing transconductance versus VGS for a combination of the graph lines 202, 204 of FIG. 2A. The combination is shown as dotted graph line 222 in FIG. 2B, and indicates a wider range of VGS voltages in which the different VTH segments of the MOSFET are within respective linear ranges, indicated by dotted line 208. Thus, the multiple VTH regions provide extended linearity compared to a MOSFET having a single VTH region. More generally, the combination of the graph lines 202, 204 provides a wider range of VGS voltages in which the different VTH segments operate within a usable transconductance range - 0.03 in this example, indicated by dotted line 210.

[0046] Embodiments of the present invention modify the architecture of a single MOSFET so as to purposefully exhibit multiple voltage thresholds VTH in different segments of the device. The modifications effectively change the local VTH of different segments within the channel of the MOSFET by altering the implantation or cross-sectional topology of different regions of the active layer of the MOSFET, altering the implantation of different regions of the interface between the active layer and the gate structure, or altering different regions of the gate structure itself.

[0047] FIG. 3A is a top plan view of a first MOSFET 300 that includes multiple VTH regions created by a first type of modification of the MOSFET active area. FIG. 3B is a cross-sectional view taken along line Y-Y of FIG. 3A. FIG. 3B shows that the BOX layer 104 is formed on an optional trap-rich silicon layer 302 formed on or in the substrate 102.

[0048] Before fabrication of the gate structure G, the portion 304 of the active layer 106 (see FIG. 1 A) that will become the source S, drain D, and (optional) drift region 141 is coated with a masking material (e.g., a photoresist polymer) which is then masked and etched (z.e., “patterned”) to form implant-resistant stripes 306. The striped structure is then subjected to implantation of a suitable dopant to create a P-well (for an N-type MOSFET) that has varying degrees of doping across the Y dimension of the MOSFET. For example, referring to FIG. 3B, the segments of the active region between the implant-resistant stripes 306 will be more heavily doped (e.g., P type) and the segments of the active region under the implant-resistant stripes 306 will be less heavily doped (e.g., P-- type).

[0049] A doping gradient between the more heavily doped and more lightly doped segments may be achieved by angled implantation of dopant, as shown by arrow 308, with the angle being a design variable. Note that the implant-resistant stripes 306 need not all have the same Y dimension sizing and need not be evenly spaced.

[0050] After doping, the implant-resistant stripes 306 may be removed, the gate structure G (shown in dashed outline in FIG. 3 A) may be formed, and the remaining steps of MOSFET fabrication may be performed. The more heavily doped segments within the channel of the device will exhibit a higher VTH and the more lightly doped segments will exhibit a lower VTH, resulting in a multi-V-m MOSFET.

[0051] In some embodiments, it may be beneficial to arrange the geometry of the implantresistant stripes 306 such that higher VTH regions are formed adjacent to the edges 320 of the source S and drain D regions underlying the gate structure G in order to mitigate current leakage.

[0052] The “varied well-doping” concept shown in FIGS. 3A and 3B may utilize different shapes for the implant-resistant coating instead of stripes. For example, FIG. 3C is a top plan view of a MOSFET 340 that includes multiple VTH regions created by a second type of modification of the MOSFET active area. Before fabrication of the gate structure G, the portion 304 of the active layer 106 that will become the source S, drain D, and (optional) drift region 141 is coated with a masking material 342 which is then patterned to form an angled interface between the source-side active area 344 and the drain-side active area 346, leaving the maskingmaterial 342 on the drain-side active area 346. The source-side active area 344 is then subjected to implantation of a suitable dopant to create a P-well (for an N-type MOSFET) that has varying degrees of doping across the X and Y dimensions of the MOSFET. The masking material 342 on the drain-side active area 346 essentially prevents implantation within the drain-side active area 346. After doping, the implant-resistant masking material 342 may be removed, the gate structure G (shown in dashed outline in FIG. 3C) may be formed, and the remaining steps of MOSFET fabrication may be performed, resulting in a multi-Vm MOSFET.

[0053] As another example, FIG. 3D is a top plan view of a MOSFET 360 that includes multiple VTH regions created by a third type of modification of the MOSFET active area. Before fabrication of the gate structure G, the portion 304 of the active layer 106 that will become the source S, drain D, and (optional) drift region 141 is coated with a masking material 362 which is then patterned to form a multi-angled interface between the source-side active area 364 and the drain-side active area 366, leaving the implant-resistant masking material 362 on the drainside active area 366. The source-side active area 364 is then subjected to implantation of a suitable dopant to create a P-well (for an N-type MOSFET) that has varying degrees of doping across the X and Y dimensions of the MOSFET. The masking material 362 on the drain-side active area 366 essentially prevents implantation within the drain-side active area 366. After doping, the implant-resistant masking material 342 may be removed, the gate structure G (shown in dashed outline in FIG. 3D) may be formed, and the remaining steps of MOSFET fabrication may be performed, resulting in a multi-Vm MOSFET.

[0054] In some embodiments, it may be beneficial to arrange the geometry of the patterned masking material such that higher VTH regions are formed adjacent to the edges 370 of the source S and drain D regions underlying the gate structure G in order to mitigate current leakage.

[0055] As should be appreciated, other geometries for the patterned masking material may be used to implement the “varied well-doping” concept described in this disclosure. For example, while FIG. 3D shows what is essentially a “saw-tooth” interface between the sourceside active area 364 and the drain-side active area 366, other shapes may be used, such as a square-wave like interface.

[0056] FIG. 4A is a top plan view of a second MOSFET 400 that includes multiple VTH regions created by modification of the shape of the MOSFET active area. FIG. 4B is a cross-sectional view taken along line Yl-Yl of FIG. 4A. FIG. 4C is a cross-sectional view taken along line Y2-Y2 of FIG. 4A. FIG. 4D is a cross-sectional view taken along the X dimension of FIG. 4A. FIGS. 4B-4D shows that the BOX layer 104 is formed on an optional trap-rich silicon layer 402 formed on or in the substrate 102. FIG. 4E is a stylized perspective view of the MOSFET 400 of FIG. 4A.

[0057] A crenellated active layer 306 formed on the BOX layer 104 includes thick-region merlons 410 having a width wl and thin-region crenels 412 (the spaces between the merlons 410) having a width w2 (note that w 1 and w2 need not be the same). Each thick-region merlon 410 includes sidewalls that extend in the Z-dimension above the thin-region crenels 412 by a height h. FIG. 4B shows five merlons 410 and four crenels 412 by way of example; fewer or more merlons 410 may be formed. Note that the merlons 410 need not all have the same Y dimension sizing and need not be evenly spaced. The thick-region merlons 410 within the channel of the device will exhibit a higher VTH and the thin-region crenels 412 will exhibit a lower VTH, resulting in a multi-VTH MOSFET.

[0058] FIG. 4C shows a gate structure comprising a GOX layer 110 and a conductive layer 108 formed over the crenellated active layer 406. The deposited GOX layer 110 is conformal to the surface of the merlons 410 and crenels 412 (shown in dashed outline). The conductive layer 108 may be conformal to the surface of the GOX layer 110 with voids within the crenels 412 or may be “filled in” within the crenels 412, as shown in FIG. 4C. In “gate last” embodiments, the gate structure would be a sacrificial gate - for example, the deposited GOX layer 110 may be a pad oxide and the conductive layer 108 may be “dummy” poly silicon.

[0059] FIG. 4D shows that the gate structure G (the GOX layer 110 and the conductive layer 108) has essentially the same structure whether formed over a thin crenel 412 or a thick merlon 410 of the crenellated active layer 406 - the only difference is the Z-dimension thickness of the underlying crenellated active layer 406.

[0060] The crenellated active layer 406 shown in FIGS. 4A-4C may be fabricated in several ways, with a variety of variants, particularly with respect to the gate structure G. For example, the crenels 412 may be formed in a subtractive process by masking and partially etching the active area 406 in a striped pattern to a depth of A, thereby defining the merlons 410 adjacent to each crenel 412. Importantly, the crenels 412 do not extend down to the BOX layer 104 between the merlons 410 - that is, h is always less than the thickest portion of the crenellatedactive layer 406. MOSFET processing may then continue in a conventional manner, including formation of shallow trench isolation (STI) structures, well implantation (e.g., a P-type well for an N-type MOSFET), gate structure G formation (e.g., a gate structure comprising a GOX layer 110 and a conductive layer 108 formed over the crenellated active layer 406), implantation of dopants in various regions (e.g., the source, the drain, LDD regions, and halo regions), and formation of contacts.

[0061] Alternatively, the crenellated active layer 406 may be formed using an additive process. For example, a continuous active layer may be formed on the BOX layer 104. The continuous active layer is then masked in a striped pattern to define regions that are to be crenels 412, such as by laying down an oxide layer and patterning that layer in stripes. Merlons 410 are then formed by an additive process to at least a design height A, such as by epitaxial growth of silicon within stripes from which the oxide layer has been removed. The masking material defining the crenels 412 may then be etched away and a process such as chemicalmechanical polishing (CMP) may be used to planarize the tops of the merlons 410 and achieve the design height h. MOSFET fabrication processing may then continue as described below with respect to the example subtractive fabrication process.

[0062] In some embodiments, it may be beneficial to arrange the geometry of the crenellated active layer 406 such that higher VTH regions are formed adjacent to the edges 420 of the source S and drain D regions underlying the gate structure G in order to mitigate current leakage.

[0063] Further details on the performance, attributes, and fabrication of MOSFETs that include a crenellated active layer are set forth in U.S. Provisional Application No. 63 / 561,095, filed March 4, 2024, entitled "Wide-Chari riel Dual-Thickness Active Area SOI FETs”, Attorney Docket No. PER-503-PROV, assigned to the assignee of the present invention, the contents of which are incorporated by reference.

[0064] FIG. 5A is a top plan view of a third MOSFET 500 that includes multiple VTH regions created by altering the implantation of different regions of the interface between the active layer and the gate structure. FIG. 5B is a cross-sectional view taken along line X-X of FIG. 5 A. Halo and / or LDD regions 501 are generally formed at a particular stage of MOSFET fabrication after formation of the gate structure G by implantation of a suitable dopant at a respective “tilt” angle Q with respect to a vertical line perpendicular to the top surface of theMOSFET device 500, and a “twist” angle of 90° relative to the Y dimension of the gate structure G. The values of 0 typically differ for halo implants versus LDD region implants - for example, the tilt angle 9 may be about 30° for halo implants and about 10° for LDD implants.

[0065] In order to create different local VTH regions, one or more “shadowing” structures 502a, 502b, which may comprise a patterned layer of masking material (e.g., a photoresist polymer), are formed along at least the source-side of the gate structure G (in some embodiments, it may be useful to create one or more “shadowing” structures on the drain-side, especially if there is no drift region). When subjected to angled implantation of a dopant (e.g., an N+ dopant such as phosphorus) to form halo and / or LDD regions, the shadowing structures 502a, 502b will partially block the amount of dopant that reaches and penetrates under the source-side edge of the gate structure G (which straddles a P+ body region in this example). Accordingly, the source-side edge of the gate structure G will exhibit different local VTH values corresponding to the number of shadowing structures 502a, 502b and varying with the respective distance (e.g., tZl, dl in this example) of the shadowing structures 502a, 502b from the source-side edge of the gate structure G. In the illustrated example, the halo and / or LDD regions corresponding to a first shadowed portion 504b of the source-side edge of the gate structure G, at a distance d\ from the shadowing structure 502a, will be the least heavily doped (type P) and thus exhibit the lowest local VTH within the channel of the device. The halo and / or LDD regions corresponding to a non-shadowed portion 504a of the source-side edge of the gate structure G will be more heavily doped (type P-) due to lateral diffusion from higher doping concentration regions to lower doping concentration regions, and thus exhibit an intermediate local VTH within the channel of the device (keeping in mind that in terms of doping concentration, P+ > P- > P). The halo and / or LDD regions of a second shadowed portion 504c of the source-side edge of the gate structure G, at a distance dl from the shadowing structure 502b, will be most heavily doped (type P+) and thus exhibit the highest local VTH within the channel of the device. After halo and / or LDD region formation, the shadowing structures 502a, 502b may be removed and the remaining steps of MOSFET fabrication may be performed, resulting in a multi-Vm MOSFET.

[0066] In some embodiments, it may be beneficial to place the shadowing structures 502a, 502b such that heavily doped (z.e., higher VTH) halo and / or LDD regions are formed adjacentto the edges 506 of the source S and drain D regions underlying the gate structure G in order to mitigate current leakage.

[0067] FIG. 6A is a top plan view of a fourth MOSFET 600 that includes multiple VTH regions. FIG. 6B is a cross-sectional view taken along line Xl-Xl of FIG. 6A. FIG. 6C is a cross-sectional view taken along line X2-X2 of FIG. 6A. In order to create different local VTH regions, one or more “blocking” structures 602a-602d, which may comprise a patterned layer of masking material (e.g., a photoresist polymer), are formed along at least the source-side of the gate structure G. The pattern of masking material may be in the form of regular stripes (as shown in FIG. 6A) or irregular stripes, and may cover the entire source-side of the gate structure G or only a portion of the source-side of the gate structure G (e.g., one-third or one-half of the Y dimension of the gate structure G). Note that the blocking structures 602a-602d need not all have the same Y dimension sizing and need not be evenly spaced.

[0068] When subjected to angled implantation of a dopant to form halo and / or LDD regions, the blocking structures 602a-602d will substantially block dopant from reaching and penetrating under corresponding source-side edges of the gate structure G. Accordingly, the source-side edge of the gate structure G will have regions 602a-602d that lack a halo and / or LDD dopant as well as doped halo and / or LDD regions 604. The different regions 602a-602d, 604 will exhibit different local VTH values, with the undoped blocked regions 602a-602d having lower local VTH values. After halo and / or LDD region formation, the blocking structures 602a-602d may be removed and the remaining steps of MOSFET fabrication may be performed.

[0069] In alternative embodiments, more than one set of blocking structures 602a-602d may be created in order to define and create segments of the gate structure G which: (1) have no halo / LDD regions, (2) are lightly doped halo / LDD regions, (3) are more heavily doped halo / LDD regions (“halo / LDD+ regions), (4) are even more heavily doped halo / LDD regions (“halo / LDD++ regions), etc. For example, blocking structures 602a-602d may be formed as shown and a first halo / LDD implant performed. Blocking structures 602a and 602b may then be removed and a second halo / LDD implant performed, resulting in implantation of dopant under the source-side edge of the gate structure G where blocking structures 602a and 602b used to be, as well as implantation of additional dopant in the original unblocked halo / LDD regions. The result at this stage would be regions with essentially no doping (corresponding to blocking structures 602b and 602d), halo / LDD regions with light doping, and halo / LDDregions with heavier doping, all with different VTH values within the channel of the device. The process may be continued to provide halo / LDD regions with different levels of doping.

[0070] In some embodiments, it may be beneficial to pattern the layer of masking material such that doped halo and / or LDD regions 604 are adjacent to the edges 606 of source S and drain D regions underlying the gate structure G, in order to mitigate current leakage. In some embodiments, it may be beneficial to create halo and / or LDD regions on the drain-side edges of the gate structure G (particularly for MOSFET designs that lack a drift region 141).

[0071] FIG. 6B shows a cross-section of the MOSFET 600 corresponding to doped halo / LDD regions 126, 124. FIG. 6C shows a cross-section of the MOSFET 600 corresponding to blocked (undoped) halo / LDD regions. In these two examples, additional doped halo / LDD regions 126, 124 have been formed on the drain-side of the gates structure G, and the MOSFET 600 lacks a drift region 141.

[0072] FIG. 7A is a top plan view of a fifth MOSFET 700 that includes multiple VTH regions created by modification of the gate oxide of the gate structure G. FIG. 7B is a cross- sectional view taken along line Y-Y of FIG. 7 A. A crenellated GOX layer 710 formed on the active layer 106 includes thick-region merlons 710 and thin-region crenels 712 (the spaces between the merlons 710). FIG. 7B shows five merlons 710 and four crenels 712 by way of example; fewer or more merlons 710 may be formed. Note that the merlons 710 need not all have the same Y dimension sizing and need not be evenly spaced. The thick-region merlons 710 will exhibit a higher VTH and the thin-region crenels 712 will exhibit a lower VTH within the channel of the device, resulting in a multi-Vm MOSFET.

[0073] FIG. 7B shows a conductive layer 708 overlaying the crenellated GOX layer 710. The conductive layer 708 may be conformal to the surface of the GOX layer 710 with voids within the crenels 412 or may be “filled in” within the crenels 412, as shown in FIG. 7B.

[0074] In some embodiments, it may be beneficial to arrange the geometry of the crenellated GOX layer 710 such that higher VTH regions (thick-region merlons 710) are formed adjacent to the edges 720 of the source S and drain D regions underlying the gate structure G in order to mitigate current leakage.

[0075] FIG. 8 is a top plan view of a sixth MOSFET 800 that includes multiple VTH regions created by modification of the work function (WF) of the gate structure G overlaying thechannel of the device. A gate structure G may be formed in a conventional fashion, with a conductive layer 108 (e.g., N-type poly silicon having a relatively low VTH) overlying an insulating GOX layer 110 (see FIG. 1A0. However, the gate structure G may then be coated (e.g., with photoresist) and patterned (e.g., by selective etching) with source-to-drain stripes 802 defined by the presence of the patterning material, with interleaved uncoated stripes 804 of the original conductive layer 108. The uncoated stripes 804 may then be implanted with a suitable dopant (e.g., P-type) to change the work function of the uncoated stripes 804 to have a relatively high VTH. The coating material may then be removed and FEOL processing may resume. As should be appreciated, the Y-dimensions of the coated stripes 802 versus the uncoated stripes 804 may be varied as a design parameter, and the shapes of the stripes 802, 804 may be varied (e.g., slanted or multi-angled or curved source-to-drain stripes).

[0076] In some embodiments, it may be beneficial to arrange the WF of the gate structure G such that higher VTH regions are formed adjacent to the edges 720 of the source S and drain D regions underlying the gate structure G in order to mitigate current leakage.

[0077] MOSFETs in accordance with the present invention may be fabricated using additive processes, subtractive processes, or a combination of additive and subtractive processes. FIGS. 9A and 8B are a process flowchart 900 showing the steps of one subtractive process suitable for some contemporary IC front-end-of-line (FEOL) foundries. Note that some conventional steps, such as planarization, passivation, details of masking and etching, and superstructure formation have been omitted as known to those of ordinary skill in the art. The example process for a NEDMOS FET includes:(1) If needed, thinning the semiconductor active layer (e.g., Si, Ge, SiGe alloy) to a suitable thickness (for example, commercially available SOI wafers may have an active layer thickness of about 750A; it may be useful for some applications, particularly for RF ICs, to thin the active layer, such as to about 500A-550A) [Block 902];(2) Optionally, modifying the semiconductor active layer to define multiple regions that will exhibit different VTH values after formation of the gate structure G, such as by varied well-doping and / or formation of a crenelated active layer [Block 904];(3) Forming shallow trench isolation (STI) regions around the active layer to define boundaries for the FET device [Block 906];(4) Forming a gate oxidation layer, optionally with a crenelated structure [Block 908];(5) Depositing gate material (e.g., poly-Si) and patterning (e.g., masking and etching) the deposited gate material to define gate structures, and optionally forming within the gate material multiple source-side to drain-side stripes having different work functions [Block 910];(6) Forming gate structure spacers [Block 912];(7) Patterning the N-drift region and implanting dopant [Block 914];(8) Optionally, selectively patterning halo / LDD regions and implanting (or blocking) dopant, such as by using shadowing structures and / or blocking structures [Block 916];(9) Implanting a source S region and a drain D region (N+ for NEDMOS devices) within the active layer on opposite sides of the gate structure [Block 918];(10) Implanting a P+ dopant in the body contact region [Block 920];(11) Depositing a salicide block layer and patterning to define contact regions [Block 922];(12) Depositing salicide (e.g., NiSi) in defined contact regions and annealing [Block 924],

[0078] Other fabrication recipes may be used to fabricate multiple VTH MOSFETS. The disclosed techniques for fabricating multiple-Vm MOSFETs may be combined in some embodiments. The structures and methods taught by this disclosure may be readily adapted to apply to P-type MOSFETs, and consequently may also be used with complementary metal - oxi de- semi conductor (CMOS) circuitry.

[0079] Circuits and devices in accordance with the present invention may be used alone or in combination with other components, circuits, and devices. Embodiments of the present invention may be fabricated as integrated circuits (ICs), which may be encased in IC packages and / or in modules for ease of handling, manufacture, and / or improved performance. In particular, IC embodiments of this invention are often used in modules in which one or more of such ICs are combined with other circuit components or blocks (e.g., filters, amplifiers, passive components, and possibly additional ICs) into one package. The ICs and / or modules are then typically combined with other components, often on a printed circuit board, to formpart of an end-product such as a cellular telephone, laptop computer, or electronic tablet, or to form a higher-level module which may be used in a wide variety of products, such as vehicles, test equipment, medical devices, etc. Through various configurations of modules and assemblies, such ICs typically enable a mode of communication, often wireless communication.

[0080] As one example of further integration of embodiments of the present invention with other components, FIG. 10 is a top plan view of a substrate 1000 that may be, for example, a printed circuit board or chip module substrate (e.g., a thin-film tile). In the illustrated example, the substrate 1000 includes multiple ICs 1002a-1002d having terminal pads 1004 which would be interconnected by conductive vias and / or traces on and / or within the substrate 1000 or on the opposite (back) surface of the substrate 1000 (to avoid clutter, the surface conductive traces are not shown and not all terminal pads are labelled). The ICs 1002a-1002d may embody, for example, signal switches, active and / or passive filters, amplifiers (including one or more LNAs), and other circuitry. For example, IC 1002b may incorporate one or more instances of a multi -VTH MOSFET.

[0081] The substrate 1000 may also include one or more passive devices 1006 embedded in, formed on, and / or affixed to the substrate 1000. While shown as generic rectangles, the passive devices 1006 may be, for example, filters, capacitors, inductors, transmission lines, resistors, antennae elements, transducers (including, for example, MEMS-based transducers, such as accelerometers, gyroscopes, microphones, pressure sensors, etc.), batteries, etc., interconnected by conductive traces on or in the substrate 1000 to other passive devices 1006 and / or the individual ICs 1002a-1002d. The front or back surface of the substrate 1000 may be used as a location for the formation of other structures.

[0082] Embodiments of the present invention are useful in a wide variety of larger radio frequency (RF) circuits and systems for performing a range of functions, including (but not limited to) impedance matching circuits, RF power amplifiers, RF low-noise amplifiers (LNAs), phase shifters, attenuators, antenna beam-steering systems, charge pump devices, RF switches, etc. Such functions are useful in a variety of applications, such as radar systems (including phased array and automotive radar systems), radio systems (including cellular radio systems), and test equipment.

[0083] Radio system usage includes wireless RF systems (including base stations, relay stations, and hand-held transceivers) that use various technologies and protocols, including various types of orthogonal frequency-division multiplexing (“OFDM”), quadrature amplitude modulation (“QAM”), Code-Division Multiple Access (“CDMA”), Time-Division Multiple Access (“TDMA”), Wide Band Code Division Multiple Access (“W-CDMA”), Global System for Mobile Communications (“GSM”), Long Term Evolution (“LTE”), 5G, 6G, and WiFi (e.g., 802.11a, b, g, ac, ax, be) protocols, as well as other radio communication standards and protocols.

[0084] The term “MOSFET”, as used in this disclosure, includes any field effect transistor (FET) having an insulated gate whose voltage determines the conductivity of the transistor, and encompasses insulated gates having a metal or metal-like, insulator, and / or semiconductor structure. The terms “metal” or “metal-like” include at least one electrically conductive material (such as aluminum, copper, or other metal, or highly doped polysilicon, graphene, or other electrical conductor), “insulator” includes at least one insulating material (such as silicon oxide or other dielectric material), and “semiconductor” includes at least one semiconductor material.

[0085] As used in this disclosure, the term “radio frequency” (RF) refers to a rate of oscillation in the range of about 3 kHz to about 300 GHz. This term also includes the frequencies used in wireless communication systems. An RF frequency may be the frequency of an electromagnetic wave or of an alternating voltage or current in a circuit.

[0086] With respect to the figures referenced in this disclosure, the dimensions for the various elements are not to scale; some dimensions may be greatly exaggerated vertically and / or horizontally for clarity or emphasis. In addition, references to orientations and directions e.g., “top”, “bottom”, “above”, “below”, “lateral”, “vertical”, “horizontal”, etc.) are relative to the example drawings, and not necessarily absolute orientations or directions.

[0087] Various embodiments of the invention can be implemented to meet a wide variety of specifications. Unless otherwise noted above, selection of suitable component values is a matter of design choice. Various embodiments of the invention may be implemented in any suitable integrated circuit (IC) technology (including but not limited to MOSFET structures), or in hybrid or discrete circuit forms. Integrated circuit embodiments may be fabricated using any suitable substrates and processes, including but not limited to standard bulk silicon, high-resistivity bulk CMOS, silicon-on-insulator (SOI), and silicon-on-sapphire (SOS). Unless otherwise noted above, embodiments of the invention may be implemented in other transistor technologies, such as BiCMOS, LDMOS, BCD, GaN HEMT, GaAs pHEMT, MESFET, FinFET, GAAFET, and SiC-based device technologies, using 2-D, 2.5-D, and 3-D structures. However, embodiments of the invention are particularly useful when fabricated using an SOI or SOS based process, or when fabricated with processes having similar characteristics. Fabrication in CMOS using SOI or SOS processes enables circuits with low power consumption, the ability to withstand high power signals during operation due to FET stacking, good linearity, and high frequency operation (z.e., radio frequencies up to and exceeding 300 GHz). Monolithic IC implementation is particularly useful since parasitic capacitances generally can be kept low (or at a minimum, kept uniform across all units, permitting them to be compensated) by careful design.

[0088] Voltage levels may be adjusted, and / or voltage and / or logic signal polarities reversed, depending on a particular specification and / or implementing technology (e.g., NMOS, PMOS, or CMOS, and enhancement mode or depletion mode transistor devices). Component voltage, current, and power handling capabilities may be adapted as needed, for example, by adjusting device sizes, serially “stacking” components (particularly FETs) to withstand greater voltages, and / or using multiple components in parallel to handle greater currents. Additional circuit components may be added to enhance the capabilities of the disclosed circuits and / or to provide additional functionality without significantly altering the functionality of the disclosed circuits.

[0089] A number of embodiments of the invention have been described. It is to be understood that various modifications may be made without departing from the spirit and scope of the invention. For example, some of the steps described above may be order independent, and thus can be performed in an order different from that described. Further, some of the steps described above may be optional. Various activities described with respect to the methods identified above can be executed in repetitive, serial, and / or parallel fashion.

[0090] It is to be understood that the foregoing description is intended to illustrate and not to limit the scope of the invention, which is defined by the scope of the following claims, and that other embodiments are within the scope of the claims. In particular, the scope of the invention includes any and all feasible combinations of one or more of the processes, machines, manufactures, or compositions of matter set forth in the claims below. (Note that theparenthetical labels for claim elements are for ease of referring to such elements, and do not in themselves indicate a particular required ordering or enumeration of elements; further, such labels may be reused in dependent claims as references to additional elements without being regarded as starting a conflicting labeling sequence).

Claims

CLAIMSWHAT IS CLAIMED IS:

1. A metal-oxide-semiconductor field-effect transistor (MOSFET) including a channel region having multiple VTH regions within the bounds of the MOSFET.

2. The MOSFET of claim 1, wherein the multiple VTH regions provide extended linearity for the MOSFET.

3. The MOSFET of claim 1, wherein the channel region includes one or more first segments having a first VTH and one or more second segments having a second VTH.

4. The MOSFET of claim 1, wherein the channel region includes one or more first segments implanted with a first dopant concentration resulting in a first VTH and one or more second segments implanted with a second dopant concentration resulting in a second VTH.

5. The MOSFET of claim 1, wherein the MOSFET includes a crenellated active layer within the channel region, wherein the crenellated active layer includes at least one thick-region merlon having a first VTH and at least one thin-region crenel having a second VTH.

6. The MOSFET of claim 1, wherein the MOSFET includes an active layer and a gate structure overlaying the channel region, wherein the active layer includes one or more first halo region segments below the gate structure having a first VTH, and one or more second halo region segments below the gate structure having a second VTH.

7. The MOSFET of claim 6, wherein the first VTH of the one or more first halo region segments is set by angled implantation of a dopant in the presence of at least one shadow structure formed on the active layer.

8. The MOSFET of claim 6, wherein the first VTH of the one or more first halo region segments is set by implantation of a dopant in the presence of at least one blocking structure formed on the active layer.

9. The MOSFET of claim 1, wherein the MOSFET includes an active layer and a gate structure overlaying the channel region, wherein the active layer includes one or more first lightly-doped drain region segments below the gate structure having a first VTH, and one ormore second lightly-doped drain region segments below the gate structure having a second VTH.

10. The MOSFET of claim 9, wherein the first VTH of the one or more first lightly-doped drain region segments is set by angled implantation of a dopant in the presence of at least one shadow structure formed on the active layer.

11. The MOSFET of claim 9, wherein the first VTH of the one or more first lightly-doped drain region segments is set by implantation of a dopant in the presence of at least one blocking structure formed on the active layer.

12. The MOSFET of claim 1, wherein the MOSFET includes an active layer and a gate structure overlaying the channel region, wherein the gate structure includes a crenelated gate oxide layer having at least one thick-region merlon having a first VTH and at least one thin-region crenel having a second VTH.

13. The MOSFET of claim 1, wherein the MOSFET includes an active layer and a gate structure overlaying the channel region, wherein the gate structure includes at least one stripe having a first work function resulting in a first VTH and at least one stripe having a work function resulting in a second VTH.

14. A metal-oxide-semiconductor field-effect transistor (MOSFET) including multiple VTH regions within a channel of the MOSFET.

15. The MOSFET of claim 14, wherein the multiple VTH regions provide extended linearity for the MOSFET.

16. The MOSFET of claim 14, wherein the channel region includes one or more first segments having a first VTH and one or more second segments having a second VTH.

17. The MOSFET of claim 14, wherein the channel region includes one or more first segments implanted with a first dopant concentration resulting in a first VTH and one or more second segments implanted with a second dopant concentration resulting in a second VTH.

18. The MOSFET of claim 14, wherein the MOSFET includes a crenellated active layer within the channel region, wherein the crenellated active layer includes at least one thick-region merlon having a first VTH and at least one thin-region crenel having a second VTH.

19. The MOSFET of claim 14, wherein the MOSFET includes an active layer and a gate structure overlaying the channel region, wherein the active layer includes one or more first halo region segments below the gate structure having a first VTH, and one or more second halo region segments below the gate structure having a second VTH.

20. The MOSFET of claim 19, wherein the first VTH of the one or more first halo region segments is set by angled implantation of a dopant in the presence of at least one shadow structure formed on the active layer.

21. The MOSFET of claim 19, wherein the first VTH of the one or more first halo region segments is set by implantation of a dopant in the presence of at least one blocking structure formed on the active layer.

22. The MOSFET of claim 14, wherein the MOSFET includes an active layer and a gate structure overlaying the channel region, wherein the active layer includes one or more first lightly-doped drain region segments below the gate structure having a first VTH, and one or more second lightly-doped drain region segments below the gate structure having a second VTH.

23. The MOSFET of claim 22, wherein the first VTH of the one or more first lightly-doped drain region segments is set by angled implantation of a dopant in the presence of at least one shadow structure formed on the active layer.

24. The MOSFET of claim 22, wherein the first VTH of the one or more first lightly-doped drain region segments is set by implantation of a dopant in the presence of at least one blocking structure formed on the active layer.

25. The MOSFET of claim 14, wherein the MOSFET includes an active layer and a gate structure overlaying the channel region, wherein the gate structure includes a crenelated gate oxide layer having at least one thick-region merlon having a first VTH and at least one thin-region crenel having a second VTH.

26. The MOSFET of claim 14, wherein the MOSFET includes an active layer and a gate structure overlaying the channel region, wherein the gate structure includes at least one stripe having a first work function resulting in a first VTH and at least one stripe having a work function resulting in a second VTH.

27. A metal-oxide-semiconductor field-effect transistor (MOSFET) including an active layer and a gate structure overlaying the active layer and defining a channel region, wherein at least two segments of the channel region have been modified to purposefully exhibit different local voltage thresholds VTH.

28. The MOSFET of claim 27, wherein one or more segments of the at least two segments has been modified to effectively change a corresponding local VTH by implantation of a dopant within the active layer associated with such one or more segments.

29. The MOSFET of claim 27, wherein one or more segments of the at least two segments has been modified to effectively change a corresponding local VTH by altering a cross-sectional topology of the active layer associated with such one or more segments.

30. The MOSFET of claim 27, wherein one or more segments of the at least two segments has been modified to effectively change a corresponding local VTH by implantation of a dopant within an interface between the active layer and the gate structure associated with such one or more segments.

31. The MOSFET of claim 27, wherein one or more segments of the at least two segments has been modified to effectively change a corresponding local VTH by altering a cross-sectional topology of the gate structure associated with such one or more segments.

32. The MOSFET of claim 27, wherein one or more segments of the at least two segments has been modified to effectively change a corresponding local VTH by altering a work function associated with such one or more segments.

33. A method of fabricating a metal-oxide-semiconductor field-effect transistor (MOSFET), including:(a) providing a substrate;(b) forming an insulator layer on the substrate;(c) forming an active layer on the insulator layer; and(d) modifying at least two segments of a channel region within the active layer to purposefully exhibit different local voltage thresholds VTH.

4. A method of fabricating a metal-oxide-semiconductor field-effect transistor (MOSFET), including:(a) providing a substrate;(b) forming an insulator layer on the substrate;(c) forming an active layer on the insulator layer;(d) forming gate structure overlaying the active layer and defining a channel region; and(e) modifying at least two segments of the channel region to purposefully exhibit different local voltage thresholds VTH.

Images