Method and apparatus for interconnecting graphic processing units

Abstract

In accordance with one aspect of the present disclosure, an electrical connector can include an electrical cable. The electrical cable can terminate at a first end and at a second end. A first edge card connector can be coupled to the first end of the electrical cable, and a second edge card connector can be coupled to the second end of the electrical cable. The first edge card connector and the second edge card connector can be in electrical communication with each other via the electrical cable. The second edge card connector can be another of the first edge card connector. The first edge card connector and the second edge card connector can each be configured to couple to mating interfaces of a respective GPU, thereby placing the respective GPUs in direct data communication with one another.

Description

METHOD AND APPARATUS FOR INTERCONNECTING GRAPHIC PROCESSING UNITSCROSS-REFERENCE TO RELATED APPLICATIONS

[0001] This application claims priority to U.S. Application Serial No. 63 / 563,083 filed March 8, 2024, and U.S. Application Serial No. 63 / 563,160 filed March 8, 2024, the contents of which are hereby incorporated by reference for any and all purposes.BACKGROUND

[0002] Electrical connectors include electrical contacts that mount to respective electrical components, and mate with each other to communicate signals between the electrical components. Some electrical components, such as graphics processing units (GPUs), are ty pically coupled to a substrate (e.g., a mother board or integrated chip). Thus, in cases where multiple GPUs are coupled to one another via the substrate, communications between the GPUs may pass to each other via the substrate, which may limit the bandwidth and increase the latency of communication between the GPUs.SUMMARY

[0003] In accordance with one aspect of the present disclosure, a data communication system can include data communication cable that places GPUs in direct data communication with each other. In one example, the data communication cable can be an electrical cable that terminates at a first end and at a second end. A first electrical connector can be coupled to the first end of the electrical cable, and a second electrical connector can be coupled to the second end of the electrical cable. The first and second electrical connectors can be in electrical communication with each other over the cable. The first electrical connector and the second electrical connector can each be configured to couple to mating interfaces of a respective GPU, thereby placing the respective GPUs in direct data communication with one another. The first and second electrical connectors can be configured as first and second edge card connectors in one example. The second edge card connector and the first edge card connector can be substantially identical to each other.BRIEF DESCRIPTION OF THE DRAWINGS

[0004] Fig. 1 is a block diagram of a conventional server;

[0005] Fig. 2 is schematic illustration of a plurality of GPUs interconnected in accordance with one example of the present disclosure;

[0006] Fig. 3 is a block diagram showing an example connection configuration of GPUs implementing electrical connectors according to the present disclosure;

[0007] Fig. 4A is an image of a data communication system;

[0008] Fig. 4B is an image of a data communication system;

[0009] Fig. 4C is a side view of a data communication system implementing an electrical connector according to the present disclosure;

[0010] Fig. 4D is a block diagram showing an example connection configuration of GPUs implementing electrical connectors according to the present disclosure;

[0011] Fig. 4E is a block diagram showing an example connection configuration of GPUs implementing electrical connectors according to the present disclosure;

[0012] FIG. 4F is a data communication system having GPUs implementing electrical connectors according to the present disclosure;

[0013] Fig. 5 is an image of a GPU surface;

[0014] Fig. 6A is a side elevation view of a data communication systems in one example;

[0015] Fig. 6B is a side elevation view of a data communication systems in another example;

[0016] Fig. 7 is a perspective view of an edge card connector of an electrical connector according to the present disclosure;

[0017] Fig. 8 is perspective view of components of an edge card connector according to the present disclosure, with a housing removed;

[0018] Fig. 9 is a perspective view of components of an edge card connector according to the present disclosure;

[0019] Fig. 10 is a perspective view of components of an edge card connector according to the present disclosure;

[0020] Fig. 11 A is a perspective view of a ground interfaces for an electrical connector in accordance with one example;

[0021] Fig. 1 IB is a perspective view of a ground interface for an electrical connector in accordance with another example;

[0022] Fig. 11C is a perspective view of a ground interface for an electrical connector in accordance with still another example;

[0023] Fig. 1 ID is a schematic illustration of a shape of the ground interface of Fig. 11C as the ground interface experiences increasing and / or decreasing loads;

[0024] Fig. 12 is an elevated view of electrical contacts of an edge card connector according to the present disclosure;

[0025] Fig. 13 is an elevated view of electrical contacts of an edge card connector according to the present disclosure;

[0026] Fig. 14 is a side perspective view of electrical contacts of an edge card connector according to the present disclosure;

[0027] Fig. 15 is a side perspective view of a first planar portion of an edge card connector according to the present disclosure;

[0028] Fig. 16 is a top perspective view of a surface of a GPU according to the present disclosure;

[0029] Fig. 17 is a top perspective view of a first planar portion of an edge card connector according to the present disclosure;

[0030] Fig. 18 is a side view of a mating interface of a GPU according to the present disclosure;

[0031] Fig. 19 is a side view of a mating interface of a GPU according to the present disclosure;

[0032] Fig. 20 is a top perspective view of a mating interface of a GPU according to the present disclosure;

[0033] Fig. 21 is a top perspective view of a mating interface of a GPU according to the present disclosure;

[0034] Fig. 22 is a top perspective view of a first electrical shield assembly according to the present disclosure;

[0035] Fig. 23 is a top perspective view of a first electrical shield assembly and a second electrical shield assembly according to the present disclosure;

[0036] Fig. 24 is a side perspective view of electrical contacts according to the present disclosure; and

[0037] Fig. 25 is a top perspective view of mounting interfaces between first electrical cables and first electrical shields.DETAILED DESCRIPTION

[0038] Referring to Fig. 1, a conventional server system 100 can include a plurality of GPUs, such as GPUs 104-a to 104-h. The GPUs can provide processing capabilities for the server system 100, such as artificial intelligence (Al) processing, machine learning (ML) processing, etc. In the system 100 shown in Fig. 1, the GPUs 105 can be in indirect electrical communication with each other, for instance through a switch 110 that route electrical signals between the various GPUs. The GPUs can be arranged in a peripheral component interconnect (PCI) configuration as shown in Fig. 1. Another example of a data communication system including GPUs arranged in a PCI configuration can be found in Fig. 4A. In other examples, GPUs can be arranged in tile configurations (see, e.g., Fig. 4B). In both configurations, electrical signals are routed between conventional GPUs through one or more substrates or switches as shown in Fig. 1. The substrate or switches can receive and transmit or relay communications between respective GPUs, thereby facilitating the aggregation or compartmentalization of the processing powers of multiple GPUs. However, connecting GPUs in this fashion can limit the bandwidth and increase the latency of communications between respective GPUs. This limitation can thus restrict the overall processing power of the server system 100. One example of such a server system 100 can be a DGC Al 00 System commercially available by NVIDIA Corporation having a principal place of business in Santa Clara, CA.

[0039] Referring to now Fig. 2, a data communication system 200 can include a plurality of GPUs 105, such as GPUs 105-a to 105-h. The GPUs can be connected to each other via data communication assemblies 217. The data communication assemblies 217 can include data communication cables 219, which can be configured as electrical cables 230 as described in more detail below. The electrical cables 230 having opposed ends that can be mounted to electrical connectors that, in turn, are mated to the GPUs. The data communication assemblies 217 can thus include the electrical connectors. The electrical cables 230 can be mounted to electrical connectors that, in turn, are mated to the GPUs to place the GPUs in electrical communication with each other. In other examples, the cables 219 of the data communication assemblies 217 can include flex cable circuits. In still other examples, the cables 219 of the data communication assemblies 217 can be configured as optical fibers or cables that are connected between optical interconnect modules that are mated to the GPUs. It will be appreciated that the GPUs 105-a to 105-h are in direct datacommunication with each other via the data communication assemblies 217, meaning that the data signals are transferred between the GPUs without travelling through intermediate switches, as opposed to the indirect communication relied on by the conventional server system 100 shown in Fig. 1. Thus, the data communication system 200 can overcome the bandwidth and latency limitations of the conventional server system 100.

[0040] Referring now to Fig. 2, each of the GPUs can be in direct data communication with one or more up to all other GPUs of the data communication system 200. For example, Fig. 2 shows interconnections between various ones of the GPUs of the data communication system 200 that place the GPUs in direct data communication with each other. For the purposes of illustration, the interconnections are shown broken out into a first region 215, a second region 220, and a third region 225. In practice, the regions 215, 220, and 225 of interconnection are all integrated into the data communication system 200 as shown at Fig. 3. The first region 215 show the GPUs of a first plurality of GPUs 105-ato 105-d in direct data communication with each other. That is, each GPU of the first plurality of GPUs is in direct data communication with all other GPUs of the first plurality of GPUs. The first plurality of GPUs can be arranged in a row, or can alternatively be arranged as desired. The third region 225 shows the GPUs of a second plurality of GPUs 105-e to 105-h in direct data communication with each other. That is, each GPU of the second plurality of GPUs is in direct data communication with all other GPUs of the second plurality of GPUs. The third plurality of GPUs can be arranged in a row, or can alternatively be arranged as desired. The second region 220 shows each GPU of the first plurality of GPUs 105-a to 105- d in direct data communication with each GPU of the second plurality of GPUs 105-e to 105- h. Thus, for example, a first GPU 105-a is in direct data communication with a second GPU 105-b over a first cable 219, with a third to GPU 105-c via a second cable 219; to a fourth GPU 105-d over a third cable 219; to a fifth GPU 105-e over a fourth cable 219; to a sixth GPU 105-f over a fifth cable 219; and to a seventh GPU 105-g over a sixth cable 219; and to an eighth GPU 105-h via a seventh cable 219. Thus, the GPU 105-a is in direct data communication with each of the other GPUs of the system 200 via respective cables 219, such as one cable 219 or a plurality of cables 219. However, one skilled in the art will understand that the data communication system 200 shown in Fig. 2 is not limited to the number of GPUs shown, and can include any number of GPUs as desired. For example, the number of GPUs connected to each other via respective electrical cables can be any numberas desired, such from 2 to 50 and every whole number therebetween, including 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, and 20. Further, one skilled in the art will understand that more than one cable 219 can place a respective pair of GPUs in direct data communication with each other. For example, the first GPU 105 -a can be placed in direct data communication with the second GPU 105 -b over a first electrical cable 219, and also over a second or more electrical cables 219.

[0041] In some cases, a respective electrical cable can provide direct communication from one GPU to multiple other GPUs. Direct communication can refer to continuous, uninterrupted communication between a first GPU and a second GPU (or electrical connectors that are mounted to the first and second GPUs). For example, communications between the first and second GPUs are not routed through an intermediary device or component, such as a switch. Instead, communications from a GPU are sent, via the cable 219 and / or the electrical connectors, directly to the intended GPU destination.

[0042] As an example, the data communication assembly 217 can include a plurality of cables 219. Subsets of one or more of the cables 219 can be connected from the first GPU to the second GPU; another subset of these electrical cables can be coupled from the first GPU to a third GPU, etc. Thus, the arrows shown in Fig. 2 can represent a subset of one or more cables of the plurality of cables 219 of the data communication system 217 placing respective pairs of GPUs in direct data communication with each other.

[0043] As will be further described below, each of the GPUs can define edges, and the cables 219 can be coupled to the GPUs (either directly or via respective electrical connectors) along the edges. The cables 219 can be coupled to one edge of the GPUs, or the cables can be coupled to two edges, which can be opposed edges in another example. Further, the cables 219 can be coupled to one major surface of the GPUs, or can be coupled to each of two opposed major surfaces of the GPUs. For instance, as shown with respect to the fifth GPU 105-e, each of the GPUs is shown with cables 219 coupled along at least one edge 213- b. In particular, the cables 219 can be mounted to an electrical connector 210 that is mated along the edge 213-b. The electrical connector 210 can include an electrically insulative housing that supports a plurality of electrical contacts, and the cables 219 can be mounted to the electrical contacts. Mating portions of the electrical contacts of the electrical connector 210 can be mated to electrical contact pads or alternatively constructed electrical contact locations 2410a-b (see Fig. 5) that can define mating interfaces of the GPU 105-e. Forinstance, the contact locations of the GPU 105-e can be arranged along one of the edges. Thus, as is described in more detail below, the electrical connectors can be configured as electrical edge card connectors. First ends of the electrical cables can be coupled (either directly or through one or more respective electrical connectors) to electrical contact locations of the GPU 105-e. Opposed second ends of the electrical cables can be coupled (either directly or through one or more respective electrical connectors) to mating locations of one or more other GPUs. For example, the first and second ends of a first subset 230-a of the electrical cables 230 can be coupled to the electrical contact locations of the fifth GPU 105-e, respectively. The first and second ends of a second subset 230-b of the electrical cables 230 can be coupled to the electrical contact locations of the electrical contact locations of the fifth GPU 105-e and the seventh GPU105-g of the GPUs, respectively. The first and second ends of a third subset 230-c of the electrical cables 230 can be coupled to the electrical contact locations of the electrical contact locations of the fifth GPU 105-e and the eighth GPU105-h of the GPUs, respectively.

[0044] The data communication system 200 can include any number of electrical connectors 210 mated to each of the GPUs 105 as desired. In one example, the number of electrical connectors 210 mated to each GPU 105 can be in a geometric sequence of a power of two. For example, depending on the number of GPUs in the data communication system 200, the number of electrical connectors 210 mated to each GPU 105 can be 2, 8, 16 (as shown in FIG. 4D), 32, or 64, or the like. The data communication system 200 can include any number of GPUs 105 from 1 through n GPUs, as shown in FIG. 4E, with each GPU 105 of the system 200 in direct data communication with each other GPU 105 of the system. In one example, n can be equal to any number from two to 100 and each integer therebetween, as one example. However, it should be appreciated that n can be any suitable number as desired. Each of the GPUs can be coupled (either directly or through the electrical connectors) to respective subsets of one or more of the electrical cables 230. Thus, a plurality of electrical cables 230 can be mounted to each of the GPUs 105, either directly or to electrical connectors that, in turn, are mated to the GPUs 105. Each subset of one or more, such as a plurality of, electrical cables 230 can extend from one the GPUs 105 to another one of the GPUs, thereby placing the GPUs 105 in electrical communication with each other. Thus, the subsets of electrical cables 230 can place a different respective pairs of GPUs 105 in direct electrical communication with each other. It should thus be appreciated that aplurality of subsets of electrical cables 230 can place all of the GPUs 105 in direct electrical communication with all others of the GPUs 105 of the data communication system 200. Whether the cables 230 are mounted directly to the GPUs 105, or are mounted to electrical connectors 210 that, in turn, are mated to the respective GPUs 105, the electrical cables 230 can be referred to as being in directed communication with the respective GPUs 105.

[0045] Thus, in one example, a first electrical connector of a respective subset of the electrical connectors 210 can be mated to a select GPU. Respective first ends of a plurality of cables of a respective subset of the cables can be mounted to the first electrical connector, thereby placing the cables in electrical data communication with the select GPU. The second end of a first at least one of the plurality of cables can be mounted to an electrical connector that, in turn, is mated to a first other GPU. The second end of a second at least one of the plurality of cables can be mounted to an electrical connector that, in turn, is mated to a second other GPU. The second end of a third at least one of the plurality of cables can be mounted to an electrical connector that, in turn, is mated to a third other GPU. The second end of a fourth at least one of the plurality of cables can be mounted to an electrical connector that, in turn, is mated to a fourth other GPU, and so forth, until the select GPU is in data communication with all others of the GPUs. In this regard, each connector of the first subset of electrical connectors 210 can be mounted to cables 230 that place the select GPU in electrical communication with all others of the GPUs. Each GPU of the data communication system 200 can be considered a select GPU as described above. In one example, the electrical connectors can be configured as edge card connectors that are mated to respective edges of the GPUs. The edges can be defined by opposed ends of the GPUs. Alternatively, the edges can be defined by opposed sides of the GPUs. Alternatively still, the edges can be defined by at least one of the sides and at least one of the ends. Further, while the data communication system has been described in connection with a first electrical connector being mated to the select GPU, it should be appreciated that a plurality of first electrical connectors can be mated to the select GPU, such that multiple cables can place the select GPU in electrical data communication with each other of the GPUs.

[0046] Further, when a plurality' first electrical connectors are mated to a select GPU, the first ends of respective first electrical cables mounted to different ones of the first electrical connectors can have respective second ends that are mounted to different electrical connectors that are mated to a first other GPU. The first ends of respective second electricalcables mounted to different ones of the first electrical connectors can have respective second ends that are mounted to different electrical connectors that are mated to a second other GPU. The first ends of respective third electrical cables mounted to different ones of the first electrical connectors can have respective second ends that are mounted to different electrical connectors that are mated to a third other GPU. The first ends of respective fourth electrical cables mounted to different ones of the first electrical connectors can have respective second ends that are mounted to different electrical connectors that are mated to a fourth other GPU, and so forth, until the select GPU is in direct data communication with all other GPUs over electrical cables that are mounted to at least some up to all of the electrical connectors mated to the select GPU. Each GPU of the data communication system 200 can be considered a select GPU as described above.

[0047] In another configuration, all cables whose first ends are mounted to each connector that is mated to the select GPU can have second ends that are mounted to a single electrical connector that is mated to a first other GPU. Thus, when seven electrical connectors are mated to a select GPU, the seven groups of cables are mounted to the seven electrical connectors at the respective first ends of the cables. Each of the seven groups of cables are mounted to respective electrical connectors that are mated to different ones of the GPUs. Thus, the groups of cables place the select GPU in direct electrical data communication with all others of the GPUs.

[0048] The electrical cables 230 can be configured as twinaxial cables or coaxial cables as desired. The twinaxial cables include pair of electrical conductors that carry differential signal pairs. Coaxial cables include a single electrical conductor. A pair of coaxial cables can combine to transmit differential signal pairs. Adjacent differential signal pairs can be separated by at least one ground member. In other examples, the electrical cables can be configured as flex cable circuits. The GPUs can be placed in direct electrical communication with each other of the GPUs over any number of electrical cables as desired. For instance, each electrical connector that is mated to a respective one of the GPUs can be placed in direct electrical communication with electrical connectors that are mated to all others, respectively, of the GPUs over a respective plurality of electrical cables. Alternatively, the electrical cables can be mounted directly to the GPUs. For instance, the electrical cables can be soldered to contact pads of the GPUs Thus, each of the GPUs can be placed in direct electrical communication with all others of the GPUs over any number ofelectrical cables as desired that can be mounted directly to the GPUs or can be mounted to electrical connectors that, in turn, are mated to the GPUs.

[0049] In one example, a first ends of a plurality of cables of a respective subset of the cables can be mounted directly to a select GPU. The second end of a first at least one of the plurality of cables can be mounted to a first other GPU. The second end of a second at least one of the plurality of cables can be mounted to a second other GPU. The second end of a third at least one of the plurality of cables can be mounted to a third other GPU. The second end of a fourth at least one of the plurality of cables can be mounted to a fourth other GPU, and so forth, until the select GPU is in data communication with all others of the GPUs. In this regard, each GPU of can be mounted to cables 230 that place the GPU in electrical communication with all others of the GPUs. Each GPU of the data communication system 200 can be considered a select GPU as described above. In still other examples, some of the cables can be directly mounted at the first ends to respective GPUs, and at the second ends to electrical connectors that are mated to other GPUs.

[0050] With continuing reference to Fig. 2, and as described above, each GPU can define a plurality of electrical contact locations configured to couple to a respective electrical connector 210 or to an electrical cable. The GPUs can define one or more edges, and the electrical contact locations can be disposed along one or more of the edges. The contact locations can include signal contact locations and ground contact locations. Adjacent ones of the signal contact locations can define differential signal pairs. Adjacent differential signal pairs can be separated by at least one ground contact location. The contact locations of the GPUs can be said to define a mating interface. In some examples, the GPUs can include a substrate that is generally planar in shape. The substrates, and thus the GPUs, can terminate at the respective edges. For example as shown with reference to the fifth GPU 105-e, each of the GPUs can include four edges 213-a to 213-d arranged in opposed pairs. In one example, whereby the GPUs are arranged in a tile configuration as shown in Fig. 4B, the electrical contact locations can be disposed along edges that face edges of adjacent ones of the GPUs. In other examples, the GPUs are arranged in a PCI configuration as shown at Fig. 4A, whereby respective major surfaces of the GPUs can face the major surfaces of adjacent ones of the GPUs.

[0051] As described above, the GPUs can be placed in direct electrical communication with each other over one or more electrical cables. Alternatively, the GPUscan be placed in direct optical communication with each other over one or more optical fibers or cables as described in more detail below. Thus, it can be said that the GPUs can be placed in direct data communication with each other. Further, it can be said that the GPUs are in direct data communication with each other over data communication cables 219. The data communication cables 219 can be configured as electrical cables. For instance, the data communication cables 219 can be configured as one or more flex circuits. Alternatively, the data communication cables 219 can be configured as twinaxial cables. Alternatively, some of the data communication cables 219 can be configured as one or more flex circuits, and one or more others of the data communication cables 219 can be configured as twinaxial cables. Alternatively or additionally, one or more of the data communication cables can be configured as coaxial cables. Alternatively, the data communication cables 219 can be configured as optical cables. It can further be said that first and second opposed terminal ends of each data communication cable are in direct data communication with each other over the data communication cables 219. Further, components mounted to the first and second ends of the data communication cables can be placed in direct data communication with each other. In one example, the components can be electrical connectors that, in turn, or mated to different ones of the GPUs. In another example, the components can be GPUs, for instance when the electrical cables are directly mounted, for instance soldered, to the GPUs. In still another example, the components can be optical interconnect modules, such as optical transceivers, optical transmitters, and optical receivers, that are mounted to the GPUs. Thus, in one example, data communication can be electrical communication. Alternatively, data communication can be an optical communication. When data communication is a direct data communication, the data is transferred without being routed through any intermediate structures such as switches, 1) from first ends of the cables to the second ends of the cables, 2) from respective electrical connectors mounted to respective GPUs to other electrical connectors mounted to different GPUs over respective cable, and / or 3) from respective GPUs to other GPUs over respective cables. In the context of optical connection, data communication is a direct data communication when the data is transferred from respective optical interconnect modules mounted to respective GPUs to other optical interconnect modules mounted to different GPUs over respective optical fibers or cables, without being routed through any intermediate structures such as switches.

[0052] Referring now to Figs. 4A-5, the data communication system can further include a server chassis 410 that supports the GPUs 105. For instance, the GPUs 105 can be disposed inside the server chassis 410. Each of the GPUs 105 can each include a GPU substrate 106 that can be configured as a printed circuit board. Thus, the description of the GPU substrates 106 applies with equal force and effect to the respective GPUs 105. The substrate 106 can define first and second major surfaces 11 la-b that are opposite each other along a transverse direction T. The major surfaces 11 la-b can define a length and width dimension of the substrate, and thus of the GPU. For instance, the substrate 106 can define first and second ends 113a-b that are opposite each other along a longitudinal direction L that is perpendicular to the transverse direction T. The substrate 106 can define first and second sides 115a-b that extend from the first end 113a to the second end 113b, and are opposite each other along a lateral direction A that is perpendicular to each of the longitudinal direction L and the transverse direction T. The longitudinal direction L defines a length dimension of the substrate, the lateral direction A defines a width direction of the substrate that runs perpendicular to the length dimension, and the transverse direction T defines a thickness direction of the substrate that runs perpendicular to each of the length and width directions. The length dimension is greater than the width direction, which is greater than the thickness direction.

[0053] The substrate 106 can define end edges at the first and second ends 1131 and 113b, The ends 113a and 113b can define end edges of the substrate. Similarly, the sides 115a and 115b can define side edges of the substrate. The electrical contact locations of the substrate 106 can be arranged along one or more edges of the substrate at least at one of the major surfaces. For instance, the substrate can include electrical contact locations, which can be configured as contact pads, that extend along either or both of the edges at the first and second ends 113a and 113b. Further, the electrical contact locations can extend along either or both of the edges at one of the first and second maj or surfaces I l la and 111 b, or at both of the first and second major surfaces. The electrical contact locations can be placed in electrical communication with electrical cables in any manner described herein.

[0054] Referring now to Fig. 4A, the GPUs 105 of the data communication system 200 can be disposed in the server chassis 410 in a PCI configuration. In some examples, the PCI configuration can be a PCI express configuration. The chassis 410 also define width, length, and thickness dimensions. The chassis width can be oriented along the transversedirection T, the chassis length can be oriented along the longitudinal direction L, and the chassis thickness can be oriented along the lateral direction A. The chassis length can be greater than the chassis width, which can be greater than the chassis thickness. The chassis 410 can define a cavity within which various electrical components can be disposed, including the GPUs 105 in the PCI configuration. In particular, the GPUs 105 are supported in the chassis 410 at particular locations and orientations of the chassis 410. For example, the GPUs 105 can be oriented such that at least one major surface of each of the GPUs 105 is adjacent to and faces a major surface of a respective adjacent one of the GPUs. Outermost GPUs 105 can define one single major surface that faces a major surface of an adjacent one of the GPUs 105. Both major surfaces of intermediate GPUs 105 can face respective major surfaces of first and second adjacent GPUs 105. Each GPU can be oriented such that the length of the GPU runs along the length of the chassis, the thickness of the GPU runs along the width of the chassis, and the width of the GPU runs along the thickness of the chassis. Further, the GPUs 105 can be configured such that respective sides of the GPUs are coplanar with each other.

[0055] The GPUs 105 can further be arranged in one or more GPU banks 117, such as a first GPU bank 117a and a second GPU bank 117b. Each of the GPU banks 117 can include a group of the GPUs 105 disposed in the chassis 410. The GPU banks 117 can be formed based on a separation of adjacent GPUs 105 along the transverse direction T. For example, adjacent GPUs of each of the banks 117 can be spaced from each other along the transverse direction a first distance. The first distance can be substantially equal to each other. The term “substantially” as used in this context means that the GPUs 105 of each of the banks 117 can be spaced from each other an equal distance, or a distance within 10% of each other. Further, the GPUs 105 of each of the banks 117 can be aligned with each other along the transverse direction T. Similarly, the first and second banks 117a and 117b can be aligned with each other along the transverse direction T. Thus, in one example, all of the GPUs 105 can be arranged in a single row that is oriented along the transverse direction T. The first and second banks 117a and 117b can be spaced from each other a second distance along the transverse direction T that is greater than the first distance.

[0056] In one example, the first bank 117a can include GPUs 105a-105d, and the second bank 117b can include GPUs 105e-105h. While the data communication system 200 can include the first and second banks 117a and 117b, it should be appreciated that the datacommunication system 200 can include any number of banks as desired. The banks can be arranged along a single row or in more than one row as desired. Further, while each of the banks 117 can include four GPUs as shown, it should be appreciated that the banks 117 can include any number of GPUs as desired. The data communication system 200 can include the same number of GPUs in each bank 117, or a different number of GPUs in each bank as desired.

[0057] Referring now to Fig. 4B, the GPUs 105 of the data communication system 200 can alternatively be arranged in a tile configuration. Thus, the GPUs 105 of the data communication system 200 can be referred to as tile GPUs. The GPUs 105 can be disposed in the server chassis 410. The chassis 410 can also define a width, length, and thickness dimensions. The chassis width can be oriented along the lateral direction A, the chassis length can be oriented along the longitudinal direction L, and the chassis thickness can be oriented along the transverse direction T. The chassis length can be greater than the chassis width, which can be greater than the chassis thickness. The chassis 410 can define a cavity within which various electrical components can be placed, including the tile GPUs 105. Further, the chassis 410 can define particular locations and orientations where GPUs are to be positioned. For example, the GPUs can be configured such that the first major surfaces 11 la of the GPUs 105, which can define outer major surfaces in the chassis 410, are coplanar with each other. The second major surfaces 11 lb of the GPUs 105, which can define inner major surfaces in the chassis 410, can be coplanar with each other. Further, the GPUs 105 can be oriented such that at least one side of each of the GPUs 105 is adjacent to and faces a side of a respective adjacent one of the GPUs along a row direction. Outermost GPUs 105 can define one single side that faces a side of an adjacent one of the GPUs 105 along the row direction. Both sides of intermediate GPUs 105 can face respective sides of first and second adjacent GPUs 105 along the row direction. Each GPU can be oriented such that the length of the GPUs runs along the length of the chassis 410, the width of the GPUs run along the width of the chassis 410, and the thickness of the GPUs runs along the thickness of the chassis.

[0058] The GPUs 105 can further be arranged in one or more GPU banks 129, such as a first GPU bank 129a and a second GPU bank 129b. Each of the GPU banks 129 can include a group of the GPUs 105 disposed in the chassis 410. Each of the GPU banks 127a and 127b can include a plurality of adjacent GPUs 105 that are adjacent each other along the lateral direction A, which can define a row direction. Thus, the GPUs 105a-105d of the firstGPU bank 127a can be arranged along a first row, and the GPUs 105e-105h can be arranged along a second row adjacent the first row. The first and second rows can be oriented along the lateral direction A. The rows can be spaced from each other along the longitudinal direction L. Further, the GPUs 105 of each of the banks 117 can be aligned with each other along the lateral direction A.

[0059] In one example, the first bank 129a can include GPUs 105a- 105d, and the second bank 127b can include GPUs 105e-105h. While the data communication system 200 can include the first and second banks 129a and 129b, it should be appreciated that the data communication system 200 can include any number of banks as desired. The banks can be arranged along a single row or in more than one row as desired. Further, while each of the banks 129 can include four GPUs as shown, it should be appreciated that the banks 129 can include any number of GPUs as desired. The data communication system 200 can include the same number of GPUs in each bank 129, or a different number of GPUs in each bank as desired.

[0060] Referring now to Fig. 4C, regardless of whether the GPUs are arranged in a PCI configuration, a tile configuration, or some other configuration, each of the GPUs 105 can be placed in direct data communication with each other of the GPUs in any manner described herein. In some examples, edge card connectors 420 can be mated to respective edges of the GPUs 105. As shown in Fig. 4C with respect to GPUs 105a and 105b, at least one first edge card connector 420a and at least one second edge card connector 420b can be mated to different ones of the GPUs 105. In particular, the edge card connectors 420 can be mated to the substates 106 of the GPUs 105a-105b. The at least one first edge card connector 420a can be configured as a plurality of first edge card connectors 420a. The at least one second edge card connector 420b can be configured as a plurality of second edge card connectors 420b.

[0061] The data communication assembly 217, and thus the data communication system 200, can include first and second cable assemblies 415 and 416 that can each include at least one cable 210 which can be configured in one example as electrical cables 230. The first cable assemblies 415 can include a plurality of first electrical cables 230 that are mounted to respective ones of the first edge card connectors 420a. The data communication assembly 217 can include subsets of the first electrical cables 230 that are mounted to respective ones of the first edge card connectors 420a. Similarly, the second cable assemblies416 can include a plurality of second electrical cables 230 that are mounted to respective ones of the second edge card connectors 420a. The data communication assembly 217 can include subsets of the first electrical cables 230 that are mounted to respective ones of the first edge card connectors 420a. Some of the first subset of electrical cables also define some of the second subset of electrical cables. That is, some of the electrical cables mounted to the second edge card connectors 420b are also mounted to the first edge card connectors 420a, thereby placing the first and second GPUs 105a and 105b in electrical data communication with each other. Others of the first and second subsets of cables can be routed to edge card connectors mounted to other ones of the GPUs, such that all GPUs are in data communication, such as electrical data communication, with each other.

[0062] In some examples, the electrical communication system 200 can include electrical cables that terminate at respective first and second ends. The electrical cables can transfer data as electrical signals between the respective first and second ends. In some cases the electrical cables can include twin axial cables. The twin axial cable can include a pair of electrical conductors that transfer differential signal pairs between the respective ends. In some cases, the electrical cables can include coaxial cables. The coaxial cables can include respective single electrical conductors that each transfer signals. The coaxial cables can be arranged in pairs that transfer differential signal pairs or single-ended signals as desired. In some cases the electrical cables can include flex cables having electrical conductors that run through flat, flexible sheathing.

[0063] It should be appreciated that the GPU substrates 106 of Fig. 4A in the PCI configuration can outer can define first outer edges 103 at the outer side 115 that faces away from the base of the chassis 410. Edge card connectors can be mated to the outer sides 115 of the GPU substrates, and can be placed in electrical communication with each other over one or more first data communication cables. For instance, a first group of one or more first data communication cables 219 can be configured as one or more flex circuits that extend between along the outer edges 103 of the GPUs 105, and have side regions that are mounted to respective outer electrical connectors mated to the GPU substrates 106, such as outer edge card connectors that are mated to the outer edges 103 of the GPU substrates 106. In one example, the flex circuits can have side protrusions that are received by respective ones of the outer electrical connectors, thereby placing the outer electrical connectors mated to the inneredges of the GPU substrates 106 in electrical communication with each other, which thus places each of the GPUs in electrical communication with all other GPUs in the chassis.

[0064] In one example, a single flex circuit having multiple layers of electrical conductors can be mounted to respective different groups of outer inner edge card connectors, wherein each of the outer edge card connectors is mated to the outer edges 103 of respective different ones of the GPU substrates 106. Thus, the single flex circuit places each of the GPU substrates 106, and thus the GPUs 105, in data communication with each other. In other examples, a plurality of flex circuits can be mounted to respective ones of the outer edge card connectors, thereby placing each of the GPU substrates 106, and thus the GPUs 105, in data communication with each other. Alternatively or additionally, the first group of electrical cables can include twinaxial cables or coaxial cables.

[0065] Alternatively or additionally, the GPU substrates 106 can define second outer edges 107 that face a wall, such as an end wall, that defines the interior of the chassis. The second outer edges can face the wall. Thus, the second outer edges 107 of the GPUs can be disposed adjacent the wall and run parallel to the wall. The second outer edges 107 can be defined by one of the first and second ends 113a and 113b. Respective first ends of a second group of second outer data communication cables 129 can be mounted to different ones of outer electrical connectors, such as outer edge card connectors, that are mated to respective different ones of the GPU substrate 106 at the second outer edges 107. At least some up to all of the second outer data communication cables 109 can extend from the outer electrical connectors through the wall and outside the chassis 410, so as to define external data communication cables, as shown in FIG. 4F. While FIG. 4F shows some of the GPUs being connected to other GPUs within the chassis via outer data communication cables, it should be appreciated that one, or more, of all GPUs can be in electrical communication with each of the GPUs within the chassis via outer data communication cables, such that one, or more, or all of the GPUs can be in direct communication with each other. The external data communication cables can be routed inside the server that contains one or more of the chassis. The external data communication cables can reenter the chassis through the wall or any alternative wall, such that the second ends of the external data communication cables are mounted to other outer electrical connectors. For instance, the second ends of some of the external data communication cables 129 can be mounted to electrical connectors that are mated to the second outer surfaces 107 of different respective GPUs. Alternatively oradditionally, the second ends of some of the external data communication cables 129 can be mounted to electrical connectors mated to the first outer surfaces 103 of different respective GPUs.

[0066] As discussed above, some of the second outer data communication cables can define external data communication cables. Others of the second outer data communication cables can be internal data communication cables that are disposed in their respective entireties inside the chassis 410. The second outer data communication cables can be routed internally such that their respective first and second outer ends are mounted to electrical connectors that are mated to different ones of the GPUs 105, for instance at the first outer edge 103 or the second outer edge 107. At least some up to all of the second data communication cables can be configured as twinaxial or coaxial cables. Alternatively or additionally, at least some up to all of the second data communication cables can be configured as one or more flex circuits. It should be appreciated that some up to all of the first data communication cables can define external data communication cables that extend and are routed outside the chassis 410.

[0067] It should be appreciated that the GPU substrates 106, and thus the GPUs 105, of Fig. 4B in the tile configuration can define inner edges 121a that face each other, and outer edges 121b that face away from each other. The inner edges and outer edges can be defined by the ends of the GPU substrates 106. Thus, the inner edges 121a can face each other along the longitudinal direction L. Alternatively, the GPUs can be arranged such that the inner and outer edges are defined by the sides 115 of the GPU substrate. Thus, the inner edges 121a can alternatively face each other along the lateral direction A. The data communication system can include a first group of first data communication cables 219 that place inner edges of the GPUs 105 in data communication with each other. For instance, the first group of the data communication cables 219 can be configured as one or more flex circuits that extend between the inner edges of the GPUs 105, and have side regions that are mated to respective inner edge card connectors that are mated to the inner edges of the GPU substrates 106. In one example, the flex circuits can have side protrusions that are received by respective ones of the inner electrical connectors mated to the inner edges of the GPU substrates 106, thereby placing the inner electrical connectors mated to the inner edges of the GPU substrates 106 in electrical communication with each other, which thus places each of the GPUs in electrical communication with all other GPUs in the chassis.

[0068] In one example, a single flex circuit having multiple layers of electrical conductors can be mounted to respective different groups of the inner edge card connectors, wherein each of the inner edge card connectors is mated to the inner edges of respective different ones of the GPU substrates 106. Thus, the single flex circuit places each of the GPU substrates 106, and thus the GPUs 105, in data communication with each other. In other examples, a plurality of flex circuits can be mounted to respective ones of the inner edge card connectors that are mounted to the inner edges of different ones of the GPU substrates 106, thereby placing each of the GPU substrates 106, and thus the GPUs 105, in data communication with each other.

[0069] Further, the outer edges 121b of the GPUs of the first bank 129a can be disposed adjacent a wall that defines the interior of the chassis, and can face the wall. Thus, the outer edges 121b of the GPUs of the first bank 129a can be disposed adjacent the wall and run parallel to the wall. Respective first ends of a second group of second data communication cables 129 can be mounted to different ones of outer electrical connectors, such as outer edge card connectors, that are mated to respective different ones of the GPU substrate 106 of the first bank 129a at the outer edges 121b. Thus, the outer data communication cables 129 can be mounted at their respective first ends to respective electrical connectors mated to the outer edges 121b of the first bank 129a of GPUs 105. At least some up to all of the outer data communication cables can extend from the outer connectors through the wall and outside the chassis 410, so as to define external data communication cables. The external data communication cables can remain inside the server that contains one or more of the chassis 410. The external data communication cables can reenter the chassis through the wall or any alternative wall, such that the second ends of the external data communication cables are mounted to other electrical connectors of respective different GPUs. For instance, the second ends of some of the external data communication cables can be mounted to outer electrical connectors of the first bank 129a. Others of the external data communication cables can be routed to the second bank 129b, such that the respective second ends can be mounted to different ones of electrical connectors mated to the inner or outer edges of the GPUs 105 at the second bank. For instance, as is described in more detail below, some of the external data communication cables can be routed under respective ones of the GPUs 105 of the first bank 129a and / or the second bank 129b (between the GPUs and the base of the chassis 410). Some of the external cables can be mounted toinner edge card connectors that are mated to the inner edges 121a of the second bank 129b of GPUs 105. Others of the external cables can be mounted to outer edge card connectors that are mated to the outer edges 121b of the second bank 129b of GPUs 105. As described above, one or more of the outer data communication cables 129 can be routed entirely inside the chassis. Further, any of the cables described herein, including the first data communication cables, can be routed outside the respective chassis.

[0070] It should be appreciated that the second ends of the second electrical cables can be mounted to any one of 1) respective different outer edge card connectors mated to different GPUs of the first bank 129a, 2) respective different inner edge card connectors mated to different GPUs of the first bank 1291, 3) respective different inner edge card connectors mated to different GPUs of the second bank 129b, and 4) respective different outer edge card connectors mated to different GPUs 105 of the second bank 129b. One or more of the outer data communication cables can be configured as twinaxial cables in some examples. Alternatively or additionally, one or more of the outer data communication cables can be configured as coaxial cables in some examples. Alternatively or additionally still, one or more of the outer data communication cables can be configured as flex cables in some examples. In still other examples, one or more of the outer data communication cables can be configured as optical cables in some examples.

[0071] It should also be appreciated that respective first and second ends of flex cables can be mounted to edge card connectors of immediately adjacent ones of the GPUs 105, both in the PCI configuration of Fig. 4A and in the tile configuration of Fig. 4B. The term “immediately adjacent” means that no GPUs are disposed between immediately adjacent GPUs.

[0072] A GPU system can include multiple chassis that each contain respective GPUs as described above. For each of the chassis, at least one of the respective GPUs can be placed in data communication with at least one GPU of each other of the chassis, thereby placing each plurality of GPUs in each chassis in electrical communication with each other. For instance, the GPUs of different chassis can be placed in data communication with each other over one or more external cables of the type described herein. The electrical connectors can be placed in direct data communication with each other, or can be in indirect data communication with each other through a switch that routes signals from one chassis toanother as desired. Each chassis can be disposed in a common server, and the cables that extend between different ones of the chassis can reside entirely in the server.

[0073] It should be appreciated that the electrical cables 230 can have any wire gauge size as desired. Further, the electrical conductors of the electrical cables 230 can all have the same wire gauge sizes in some examples. For instance, the wire gauge size can be in a range from 26 to 34 in some examples. For instance, the wire gauge size can be 27. In another example, the wire gauge size can be 33. In other examples, the first electrical cables 230 can have a different wire size that the second electrical cables 230. Thus, the electrical cables 230 of the data communication system 200 can include electrical cables having different wire gauge sizes. In one example, the first electrical cables have a first wire gauge size in a range from 26 to 34, such as 33. The second electrical cables can have a second wire gauge in the range from 26 to 34, such as 27. In some examples, the electrical cables 230 can have a thickness between 0.5 mm and 1.5 mm, such as approximately 0.8 mm. “Approximately” in this context refers to the stated thickness and all thickness plus or minus 10% of the stated thickness, such as plus or minus 9% of the stated thickness, such as plus or minus 8% of the stated thickness, such as plus or minus 7% of the stated thickness, such as plus or minus 6% of the stated thickness, such as plus or minus 5% of the stated thickness, such as plus or minus 4% of the stated thickness, such as plus or minus 3% of the stated thickness, such as plus or minus 2% of the stated thickness, such as plus or minus 1% of the stated thickness. The two electrical conductors of twinaxial cables can be spaced from each other along lateral direction A that defines a width of the electrical cable, the electrical conductors are elongate along a length of the electrical cable, and the thickness of the electrical cable is perpendicular to each of the width and the length. For a coaxial cable, the thickness can be defined by the diameter of the cable. In one example, the thickness of the twinaxial cables can be oriented along the lateral direction A where the cables exit the electrical connectors, and the GPUs are in the PCI configuration or the tile configuration shown in Figs. 4A-4B.

[0074] When the cables are routed between the GPUs of the data communication assembly 200, various ones of the cables can intersect. The minimum thickness occupied by two intersecting cables is two times the cable thickness, or approximately 1.6 mm. When three cables intersect at the same location so as to define two stacked intersections, the two stacked intersections can define a thickness of three times the cable thickness, orapproximately 2.4 mm. When four cables intersect at the same location s as to define three stacked intersections, the three stacked intersections can define a thickness of four times the cable thickness, or approximately 3.2 mm. The cables can be routed in the server chassis in a manner so as to limit the number of cable intersections that are aligned with each other along the thickness direction to no more than three stacked intersections, such as two stacked intersections. Thus, the cables can be routed in the server chassis to place all GPUs in direct data communication with all others of the GPUs.

[0075] In some examples, the edge card connectors can have substantially identical mating interfaces, such as the same size and shape within manufacturing tolerances of the edge card connectors. In some examples, the edge card connectors can be substantially identical to each other, and thus can have the same size and shape within manufacturing tolerances. For instance, the edge card connectors can have identical mating interfaces, and in some examples can be identical to each other. The mating interfaces of the edge card connectors are configured to mate with the GPUs at the edges as described above.

[0076] When the electrical connectors 210 are configured as edge card connectors 420, the edge card connectors can have first and second rows of electrical contacts that mate with the electrical contact locations 2410 of the GPU at the first and second major surfaces described above, and as shown in Fig. 5. For instance a first plurality of electrical contact locations 2410a can be disposed along the first end 113a of the GPU substrate 106, and a second plurality of electrical contact locations 2410b can be disposed along the second end 113b of the GPU substrate 106. As shown the electrical contact locations 2410 can be configured as electrical contact pads. The electrical contact locations 2410 can be arranged in banks that are configured to mate with respective edge card connectors. As shown in Fig. 5, the GPU substrate 106 can include four banks of first electrical contact locations 2410a that are configured to mate with four edge card connectors, respectively. Similarly, the GPU substrate 106 can include four banks of second electrical contact locations 2410b that are configured to mate with four edge card connectors, respectively. It should be appreciated, of course, that the GPU substrate 106 can be configured to mate with any number of electrical connectors are desired.

[0077] Referring now to Fig. 4C, the edge card connectors 420 can each include a housing 425 that receives the edge of the GPU so as to mate with the electrical contact locations arranged along the edge of the GPU. The housings 425 can define a receptacle 430that is dimensioned to receive an edge of a GPU along the longitudinal direction L, which can be referred to as an insertion or mating direction. The mating direction is a direction along which the connector mates with the GPU in the receptacle 430. For example, the GPU can include a substrate 106 that is generally planar in shape. The substrate 106 can terminate at a respective end 113, and the substrate 106 can be received in the receptacle 430 until the end 113 abuts the housing 425, at which point the mating ends are mated with the respective ones of the electrical contact locations of the substrate 106.

[0078] In one example, the housings 425 can define a first planar surface 426 and a second planar surface 428 opposite the first planar surface 426 and spaced from the first planar surface 426 so as to define the receptacle 430 therebetween along the transverse direction T. At least respective portions such as majorities up to entireties of the first and second planar surfaces 426 and 428 can be planar to each other. In some examples, respective leading ends of the surfaces 426 and 428 can be beveled to facilitate insertion of the GPUs into the receptacles 430.

[0079] The edge card connectors 420 can include one or more rows of electrical contacts that are configured to mate with respective ones of the electrical contact locations of the GPU that is received in the receptacle 430. For instance, the electrical contacts can have mating ends that project out with respect to each of the first and second planar surfaces 426 and 428 and are configured to mate with electrical contact locations at the first and second major surfaces of the GPU.

[0080] First and second ends of the electrical cables can be received by respective ones of the edge card connectors 425, and can be mounted to respective mounting ends of the electrical contacts of the edge card connector 425. Thus, the electrical cables can place respective first and second ones of the edge card connectors 435 in electrical data communication with each other. Thus, the electrical cables and first and second edge card connectors can place first and second GPUs in electrical data communication with each other when the first and second edge card connectors are mated to the first and second GPUs.

[0081] The data communication system 200 described herein can provide for direct communications between respective GPUs, which can increase bandwidth and reduce latency of a data communication system compared to the conventional system 100 of Fig. 1. For example, the data communication system 200 can facilitate data transfer along the cables having asynchronous multi-active crosstalk that is no worse than -70 dB up to data transferfrequencies 28 GHZ PAM 4. In some cases, the data communication system 200 can provide data transfer along the cables having asynchronous multi-active crosstalk that is no worse than -70 dB up to data transfer speeds 112 gigabits per second.

[0082] The electrical connectors described herein can provide high speed communications between GPUs without the need for intermediary substrates or electrical components. For example, direct coupling of GPUs via the electrical connectors described herein can provide transmitting signals at data transfer speeds of 224 gigabits / second at frequencies up to 80 GHz, for instance up to 60 GHz, for instance up to 56 GHz, such as up to 50 GHz. Additionally, as the GPUs are coupled to the electrical cables via side edges, surface areas for particular surfaces of the GPUs can be made available for other electrical components, or for electrical cables to be placed through particular regions surrounding the GPU.

[0083] Referring now to Fig. 5 the contact locations 2410 are disposed along respective edges of the GPU substrate 106 in the manner described above. Thus, a region 2405 of one of the major surfaces of the GPU substrate 106 that was reserved for communication interfaces of conventional GPUs can be occupied by other electronics, as the communication interfaces have been relocated to along the edges of the GPU substrate 106. Thus, positioning the contact locations 2410 along respective edges of the substrate 106 provides for additional usable real estate on the substrate 106, for instance at least at one of the major surfaces.

[0084] In one particular example, Fig. 6A shows a system of GPUs coupled to one another via the electrical cable assemblies 415 and 416 and, optionally, the electrical connectors 210 that can be configured as edge card connectors 420 as described above. In one example shown in Fig. 6A, at least some of the cables 219 can be routed along and adjacent to surfaces, such as one or more major surfaces, of respective ones of the GPU substrates 106 at regions that are occupied by other electrical components in conventional GPU. The cables 219 can be routed along and adjacent the GPU substrates at these regions because interface electronics at the major surfaces 211 were replaced with electrical contact locations along one or more edges of the substrate 106. In one example shown in Fig. 6B, at least some of the electrical cables can be routed underneath at least one of the GPUs 105. As described above, the GPUs 105 include substrates 106 that define respective first major surfaces 11 la and second major surfaces 111b opposite the first major surfaces I l la. Thesecond major surfaces 11 lb can face a base of the server chassis when the GPUs are oriented in the tile configuration illustrated in Fig. 4B. Thus, at least some of the cables 219 can be routed between the respective second major surface 111b of at least one of the GPUs 105 and the base of the server chassis with respect to the transverse direction T (see also Fig. 4B).

[0085] While the cables 219 have been described as electrical cables in some examples, in other examples it should be appreciated that the cables 219 can include optical cables that transmit optical signals between the respective first and second ends. In these cases, the respective ends of the optical fibers can be coupled to an optical interconnect module, which can be in electrical communication to the respective GPU. In other words, an optical interconnect module may terminate both ends of an optical cable that includes one or more optical fibers configured to propagate optical signals. The optical interconnect modules on both ends of the optical cable may be identical. The optical interconnect modules may be co-packaged with the GPU, often referred to as on-board optics, or may be situated adjacent to the GPU. The optical interconnect modules may make an electrical connection to an electrical connector on the GPU or to a card edge of the GPU in a similar manner as that previously described for an electrical connector that terminates an electrical cable. The optical interconnect modules perform an electrical-to-optical conversion from electrical signals to optical signals transmitted from the GPU and / or an optical-to-electrical conversion from optical signal to electrical signals transmitted to the GPU. The optical interconnect module may be a transmitter that only performs an electrical-to-optical conversion, a receiver that only performs an optical-to-electrical conversion, or a transceiver that performs both an electrical-to-optical conversion and an optical-to-electrical conversion. Thus, the optical interconnect module can include a transmit optical engine that receives electrical signals, converts the electrical signals to optical signals, and transmits the optical signals to the optical cables. The optical interconnect modules can further include a receive optical engine that receives optical signals from the optical cables, converts the optical signals to electrical signals, and transmits the electrical signals to an electrical component. The optical fibers that transmit the optical signals may be permanently attached to the optical interconnect modules, i.e. pigtailed, or may be attachable / detachable from the optical interconnect modules. The optical fiber cables may be routed in a similar manner as electrical cables, with the optical fiber cables having improved signal integrity, particularly over longer cable spans. Use ofoptical fiber cables may enable GPUs to communicate at a higher data transmission rate with a thinner, more flexible cable than achievable with an electrical cable.

[0086] In some embodiments, the cables 219 may be configured to transport optical signals at multiple wavelengths simultaneously in a wavelength division multiplexing (WDM) arrangement. In this embodiment, the optical interconnect module may transmit a first plurality of optical signals having a different wavelength in a first optical fiber and / or may receive a second plurality of different wavelength optical signals from a second optical fiber. The first and second optical fibers are generally different fibers, but in some cases may be the same fiber with optical signals propagating in both directions. In the transmit case, the optical interconnect module multiplexes the first plurality of optical signals, each based on a unique electrical signal, into the first optical fiber and in the receive case, the optical interconnect module demultiplexes the second plurality of optical signals into a plurality of unique electrical signals. An advantage of the WDM arrangement is that a data transport rate of each optical fiber may be increased relative to an optical fiber transporting only a single wavelength optical signal. As a result, fewer optical fibers are required to interconnect GPUs, which may make routing of the optical fibers easier.

[0087] Examples of the edge card connectors will now be described with reference to Figs. 7-25 generally. It should be appreciated that examples of edge card connectors are described, and that any suitable alternatively constructed edge card connectors or alternatively configured electrical connectors are envisioned. Fig. 7 shows a side perspective view of an example edge card connector of the data communication system 200. It should be appreciated, of course, that the example edge card connector described herein is one example of an electrical connector of the data communication system 200, and that the data communication system can include any suitable alternative connector as desired that can be mated to the GPUs to facilitate data communication in the manner described herein. In one example, the edge card connector can be the first edge card connector 420 of Fig. 4C. As discussed above, the first edge card connector 420 can include the first housing 425, which can further include the first planar portion 426 and the second planar portion 428. The first planar portion 426 can define a first end 502 and a second end 504. The first end 502 and the second end 504 can be separated by a distance in the longitudinal direction L. The first end 502 and the second end 504 can extend in the transverse direction T to define a height of thefirst planar portion 426. In some cases, the height of the first planar portion 426 can be greater at the first end 502 as compared to at the second end 504.

[0088] The first end 502 can define a first cavity assembly 506. The first cavity assembly 506 can include a plurality of cavities, each configured to receive a first end of a first electrical cable of the first electrical assembly 415. Each cavity can extend in the longitudinal direction L, and then can angle towards the receptacle 430. The cavities of the first cavity assembly 506 can terminate at an interior surface of the first planar portion 426, which can expose the first electrical cables to the receptacle 430.

[0089] The cavities of the first cavity assembly 506 can be configured to receive first ends of the first electrical cable of the first electrical cable assembly 415. In some cases, the first cavities can include cables disposed in the cavities, which are then coupled to the first electrical cables of the first electrical cable assembly 415 (e.g., such that the first electrical cables are not inserted into the first cavities. The first electrical cables can be inserted in the respective first cavities, and terminate at the interior surface of the first planar portion 426. Thus, the first ends of the first electrical cables can be exposed to the receptacle 430.

[0090] Likewise, the second planar portion 428 can define a first end 510 and a second end 512. The first end 510 and the second end 512 can be separated by a distance in the longitudinal direction L. The first end 510 and the second end 512 can extend in the transverse direction T to define a height of the second planar portion 428. In some cases, the height of the second planar portion 428 can be greater at the first end 510 as compared to at the second end 512.

[0091] The first end 510 can define a second cavity assembly 516. The second cavity assembly 516 can include a plurality of cavities, each configured to receive a first end of a second electrical cable of the second electrical assembly 416. Each cavity can extend in the longitudinal direction L, and then can angle towards the receptacle 430, which will be described in more detail with reference to Fig. 8. The cavities of the second cavity assembly 516 can terminate at an interior surface of the second planar portion 428, which can expose the second electrical cables to the receptacle 430.

[0092] The cavities of the second cavity assembly 516 can be configured to receive first ends of the second electrical cable of the second electrical cable assembly 416. In some cases, the second cavities can include cables disposed in the cavities, which are then coupledto the second electrical cables of the second electrical cable assembly 416 (e.g., such that the second electrical cables are not inserted into the second cavities). The second electrical cables can be inserted in the respective second cavities, and terminate at the interior surface of the second planar portion 428. Thus, the first ends of the second electrical cables can be exposed to the receptacle 430.

[0093] In some cases, the first planar portions 426 and the second planar portions 428 can include additional components for forming the respective planar portions. For example, the first planar portion 426 can include a first planar outer layer 530, a first planar inner layer 531, and a first edge portion 532. The first planar outer layer 530 can be generally planar in shape, and can extend along the longitudinal direction L. The first planar inner layer 531 can be disposed between the receptacle 430 and the first planar outer layer 530, such that the first planar layer 531 partially defines the inner surface for defining the receptacle 430. The first planar outer layer 530 can extend the length of the first planar portion 426, such that the first planar outer layer 530 terminates as the first end 502 and the second end 504. The first planar inner layer 531 can be shorter in length (in the longitudinal direction L) than the first planar outer layer 530. Thus, the first planar outer layer 531 can terminate at the second end 504, but not at the first end 502. The first edge portion 532 can be positioned to further define the first end 502 and the receptacle 430. For example, the first edge portion 532 can abut the first inner layer portion 531 and the first planar outer layer 530. The first edge portion 532 can also abut the corresponding second edge portion of the second planar portion 428, thereby further defining the receptacle 430.

[0094] Likewise, the second planar portion 428 can further include a second planar outer layer 533, a second planar inner layer 534, and a second edge portion 535. The second planar outer layer 533 can be generally planar in shape, and can extend along the longitudinal direction L. The second planar inner layer 534 can be disposed between the receptacle 430 and the second planar outer layer 533, such that the second planar outer layer 534 partially defines the inner surface for defining the receptacle 430. The second planar outer layer 533 can extend the length of the second planar portion 428, such that the second planar outer layer 533 terminates at the first end 510 and the second end 512. The second planar inner layer 534 can be shorter in length (in the longitudinal direction L) than the second planar outer layer 533. Thus, the second planar outer layer 533 can terminate at the second end 512, but not at the first end 510. The second edge portion 535 can be positioned to further definethe first end 510 and the receptacle 430. For example, the second edge portion 535 can abut the second inner layer portion 534 and the second planar outer layer 533. The second edge portion 535 can also abut the corresponding first edge portion 532 of the first planar portion 426, which further defines the receptacle 430.

[0095] Fig. 8 shows a perspective side view of an edge card connector, with the first and second planar outer layers, and the first and second planar inner layers, removed. The first and second electrical cables can extend through the respective first and second cavities. For example, the first edge portion 533 and the first planar outer portion 531 can define a first cavity portion for the first cavity assembly 506. The first cavity portion can extend in the longitudinal direction L. The first electrical cable assembly 415 can thus extend in the longitudinal direction L for a portion of the length of the first planar portion of the first edge card connector.

[0096] As the first electrical cables extend further into the first cavity assembly 506, the first cavities are further defined by the first planar inner layer 532 and the first planar outer layer 531 (not shown in Fig. 8). The first cavities can extend partially in the longitudinal direction L and partially in the transverse direction T towards the receptacle 430.

[0097] The first electrical cables can terminate within the first cavities. The first electrical cables can terminate at a mounting end 605. The mounting end 605 can be coupled (mounted) to a mounting end 606 of the electrical contact 607. For example, the first electrical cables can include electrically conductive wire covered in an insulating coating. At the mounting end 605, the insulative coating can be stripped or removed, thereby exposing the electrically conductive wire. The electrically conductive wire can be mounted (e.g., soldered) to the mounting end 606 of the electrical contact 607.

[0098] The electrical contact 607 can be angled to extend in the longitudinal direction L and the transverse direction T towards the receptacle 430. The electrical contact 607 can terminate at a mating end 608, which can be configured to mate to a mating interface 610 of the GPU 105-a. In some cases, the mating interface 610 can be an electrically conductive contact pad, and the mating between the mating end 608 and the mating interface 610 can be the mating end 608 contacting the mating interface 610. In some cases, the dimensions and positioning of the electrical contact 607 can be such that, when contacting the mating interface 610, the electrical contact 607 can flex (e.g., in the direction T). Further, the mating end 608 in some cases can be curve, such that a curved portion of the mating end 608contacts the mating interface 610, which can provide a larger contact area between the mating end 608 and the mating interface 610.

[0099] Each first electrical cable can be coupled to one or more electrical contacts 607. For example, the number of electrical contacts 607 can be dependent on a number of electrically conductive wires a given first electrical cable includes. For example, the first electrical cables of Fig. 8 can include two electrically conductive wires for each first electrical cable, which can be representative of a twin axial or biaxial cable. However, the first electrical cables can also be single axial, coaxial, triaxial, and the like. Further, a dielectric shield 611 can be disposed around the exposed electrically conductive wires of the first electrical cable and the mounting end 608 of the electrical contact 607, which can facilitate the mitigation of electrical interference experienced by the respective coupling. In some cases, the dielectric shield 611 can envelope the exposed electrically conductive wires of the first electrical cable and the mounting end 608 of the electrical contact 607. The dielectric shield 611 can also be angled similar as the electrical contact 607, such that the length of the dielectric shield 611 extends towards the receptacle 430.

[0100] Fig. 9 shows a perspective side view of an edge card connector shown in Fig. 8, with the first and second planar outer layers, the first and second planar inner layers, and the electrical contacts and the dielectric shield for the first electrical cables removed. The first edge portion 535 and the first planar outer layer 533 can define a first cavity portion for the second cavity assembly 516. The first cavity portion can extend in the longitudinal direction L. The second electrical cable assembly 416 can thus extend in the longitudinal direction L for a portion of the length of the first planar outer layer of the first edge card connector.

[0101] As the first electrical cables extend further into the second cavity assembly 516, the second cavities are further defined by the first planar inner layer 534 and the first planar outer layer 533 (not shown in Fig. 9). The second cavities can extend partially in the longitudinal direction L and partially in the transverse direction T towards the receptacle 430.

[0102] The second electrical cables can terminate within the second cavities. The second electrical cables can terminate at a mounting end 705. The mounting end 705 can be coupled (mounted) to a mounting end 706 of the electrical contact 707, which can be configured as a signal contact. For example, the second electrical cables can include electrically conductive wire covered in an insulating coating. At the mounting end 705, theinsulative coating can be stripped or removed, thereby exposing the electrically conductive wire. The electrically conductive wire can be mounted (e.g., soldered) to the mounting end706 of the electrical contact 707.

[0103] The electrical contact 707 can be angled to extend in the longitudinal direction L and the transverse direction T towards the receptacle 430. The electrical contact707 can terminate at a mating end 708, which can be configured to mate to a mating interface 710 of the GPU 105. In some cases, the mating interface 710 can be an electrically conductive contact pad, and the mating end 708 can contact mating interface 710 when the electrical connector is mated to the GPU. In one example, the mating interfaces 710 and the mating ends 708 can be signal mating interfaces 710 and signal mating ends 708. The GPU 105 can further include ground interfaces that are placed in electrical communication with the ground shields of the cables 219 of the of the data communication assemblies 217 as described above. In some cases, the dimensions and positioning of the electrical contact 707 can be such that, when contacting the mating interface 710, the electrical contact 707 can flex (e.g., in the direction T). Further, the mating end 708 in some cases can be curved, such that a curved portion of the mating end 708 contacts the mating interface 710, which can provide a larger contact area between the mating end 708 and the mating interface 710.

[0104] Each second electrical cable can be coupled to one or more electrical contacts 707. For example, the number of electrical contacts 707 can be dependent on a number of electrically conductive wires a given second electrical cable includes. For example, the second electrical cables of Fig. 9 can show two electrically conductive wires for each second electrical cable, which can be representative of a twin axial or biaxial cable. However, the second electrical cables can also be single axial, coaxial, triaxial, and the like. Further, a dielectric shield 711 can be disposed around the exposed electrically conductive wires of the second electrical cable and the mounting end 708 of the electrical contact 707, which can facilitate the mitigation of electrical interference experienced by the respective coupling. In some cases, the dielectric shield 711 can envelope the exposed electrically conductive wires of the second electrical cable and the mounting end 708 of the electrical contact 707. The dielectric shield 711 can also be angled similar as the electrical contact 707, such that the length of the dielectric shield 711 extends towards the receptacle 430.

[0105] As shown between Figs. 8 and 9, the GPU 105 can define mating interfaces on opposite sides of the substrate 405. For example, the substrate 405 can define a firstsurface 620 and a second surface 621. The first surface 620 and the second surface 621 can be coplanar to one another, and extend along the direction L, such that a vector normal to the first surface 620 or the second surface 621 is along the direction T. The surfaces 620 and 621 can each define or include mating interfaces configured to mate to the electrical cables. The first surface 620 can include mating interfaces 610 configured to mate to the first electrical cables of the first electrical assembly 415. The second surface 621 can include mating interfaces 710 configured to mate to the second electrical cables of the second cable assembly 416. Thus, both surfaces of the GPU edge can be in electrical communication with the first edge card connector.

[0106] Fig. 10 shows the planar outer layers and the planar inner layers for an edge card connector according to the present disclosure. The planar outer layers and the planar inner layers can further define the cavities for the respective electrical cables. For example, the planar outer layer 533 and the planar inner layer 534 can define the second cavity assembly 516. The planar outer layer 530 and the planar inner layer 531 can define the first cavity assembly 506. Additionally, the planar inner layers 531, 534, can define portions of the cavities that extend in the transverse direction T, which can facilitate the respective electrical contacts angling towards the receptacle 430.

[0107] The edge card connectors can also include ground interfaces 805. The ground interfaces 805 can be positioned between the planar inner layer 531 and the planar inner layer 534. The ground interfaces 805 can be shaped to extend around the cavity openings exposed to the receptacle 430. Further, the ground interfaces 805 can be compressible, such that, when contacted by a GPU substrate, the ground interfaces 805 can compress in the transverse direction T. The ground interfaces 805 can be configured to contact the GPU substrate when the edge card connector is coupled to an edge of a GPU. Further, the ground interfaces 805 can be composed of an electrically conductive material, and can act as a grounding mechanism between the GPU substrate and the edge card connector, and can further facilitate in mitigating electrical interference experienced by the coupling of the electrical contacts of the respective electrical cables, and the mating interfaces of the GPU. The ground interfaces 805 can be configured to provide electrical shielding to the signal contact locations of the GPU, the electrical signal contacts of the electrical connector, and mating interfaces between the signal contact locations and the electrical signal contacts.

[0108] Referring to Figs. 10-1 ID generally, the electrical connector, such as the edge card connector, can include at least one ground interface 805 that is supported by the housing of the electrical connector. As will be described in more detail, the ground interface 805 can be electrically conductive, and can be configured to be brought into contact with contact pads of the GPU when the electrical connector is mated to the GPU. Further, the ground interface 805 can surround respective pairs of signal contact pads of the GPU when the electrical connector is mated to the GPU. Thus, the ground interface 805 can provide electrical shielding to the surrounded pairs of signal contacts pads of the GPU. Further, because the housing of the edge card connector can be electrically conductive, the ground interface 805 can be placed in electrical communication with the housing of the edge card connector as well as the ground shields of the electrical cables that are mounted to the electrical connector. The ground interface 805 can be made of any suitable electrically conductive material. In one example, the ground interface 805 can be an electrically conductive elastomer. In other examples, the ground interface 805 can be any suitable metal. For instance, the ground interface 805 can be a liquid metal or an amorphous metal, such as Metglass. During operation, when the ground interface 805 is contacted by the contact pads of the GPU, the contact pads can apply a compressive force against the metallic glass of the ground interface 805, thereby causing the metallic glass of the ground interface 805 to define undulations. The undulations can define contact surfaces of the ground interface that contact the GPU contact pads. For example, a segment or portion of metallic glass can initially contact another article or structure at only a small number of physical contact points, such as one physical contact point. The number of phy sical contact points can increase as a function of force and a lessening separation distance between the article that carries the portion of metallic glass and the compression article. Stated another way, a portion of metallic glass can be attached to or be carried by any one or more of an electrical ground, an electrical ground conductor, an electrical reference, an electrically grounded trace, and an electrically grounded shield. The portion of metallic glass can initially physically contact another article at any one of only one physical point of contact at a first force, a first separation distance between the article (such as an electrical ground) and a the corresponding compression article, or both. At a second force greater than the first force or at a second separation distance that is less than the first separation distance, the portion of metallic glass can physically contact another article with at least two physical points of contact, at least threephysical points of contact, at least four physical points of contact, at least five physical points of contact, at least six physical points of contact, at least seven physical points of contact, at least eight physical points of contact, and / or more than eight physical points of contact. Without being bound by theory, it is believed that unplated metallic glass or unplated amorphous metal is not as electrically conductive as copper or silver or gold. An example of a metallic glass or amorphous metal is VITRELOY 105, which can contain 52.5 percent zirconium, 5 percent titanium, 5 percent copper, 14.6 percent copper, 10 aluminum. Other compounds with greater electrical conductivity can also be used, such as more copper laden metallic glass or amorphous metal, as VITERLOY 105 has electrical conductivity below copper, silver or gold. However, zirconium metallic glass or amorphous metal can be well- suited for electrical grounding applications due to its high elastic yielding. Instead of taking a permanent set, it creates more and more ground paths as it is deflected and constrained.

[0109] Referring now to Figs. 10-11A, the ground interface 805 can include an electrically conductive interface body 806, and at least one void 808 that extends through the interface body 806 along the transverse direction T. The body 806 can be configured to contact ground contact locations of the GPU, which can define ground mating interfaces of the GPU. In one example, the ground contact locations can be configured as ground contact pads. Signal contact locations of the GPU, such as at least one pair of signal contact locations of the GPU, can be aligned with or disposed in the void 808 and thus can be electrically isolated from the interface body 806.

[0110] The interface body 806, and thus the ground interface 805, can include pair of end walls including a first end wall 810a and a second end wall 810b opposite the first end wall 810a along the longitudinal direction L. The interface body 806, and thus the ground interface 805a, can further include a pair of side walls including a first side wall 812a and a second side wall 812b opposite the first side wall 812a along the lateral direction A. For instance, each of the first and second side walls 812a and 812b can extend from the first end wall 810a to the second end wall 810b. The end walls 810a-b and the side walls 812a-b can combine so as to define the void 808. In this regard, the end walls 810a-b and the side walls 812a-b can combine to define a frame. Thus, the electrically conductive interface body 806 can provide electrical shielding between adjacent differential signal pairs of the signal contact locations of the GPU, the signal contacts of the electrical connector, and the interfacebetween the signal contact locations of the GPU and the signal contacts of the electrical connector.

[0111] The interface body 806, and thus the ground interface 805a, can further include at least one intermediate wall 814 that can include one or a plurality of intermediate walls 814 that are disposed between the first and second side walls 812a and 812b. The intermediate walls 814, if more than one is present, can be spaced from each other along the lateral direction A. Further, the intermediate walls 814 can be elongate along the longitudinal direction L. Adjacent ones of the intermediate walls 814 can divide the void 808 into a plurality of openings 816. When the interface body 806 includes a single intermediate wall 814, the intermediate wall 814 divides the void 808 into a pair of openings 816 that extend from the intermediate wall 814 to respective different ones of the first and second side walls 812a and 812b. The openings 816 can be aligned with or disposed in a respective at least one signal contact location of the GPU, such as a respective pair of signal contact locations of the GPU, when the electrical connector is mated to the GPU. Thus, the pairs of signal contact locations can be electrically isolated from the interface body 806. It should be similarly appreciated that the mating portions of the signal contacts of the electrical connector can be aligned with respective ones of the openings 816 so as to contact the signal contact locations of the GPU when the electrical connector is mated to the GPU. The mating portions of the signal contacts of the electrical connector can thus also be electrically isolated from the interface body 806. The interface body 806, and thus the ground interface 805a, can further include a divider wall 818 that extends from the first side wall 812a to the second side wall 812b, for instance along the lateral direction A. The divider wall 818 can be disposed between the first end wall 810a and the second end wall 810b. In one example, the divider wall 818 can be equidistant from each of the first and second end walls 810a and 810b. The at least one intermediate wall 814 can extend from the first end wall 810a to the divider wall 818. Thus, the openings 816 can be enclosed by the first end wall 810a, the divider wall 818, and a respective pair of adjacent intermediate walls 814 or an intermediate wall 814 and a respective one of the first and second side walls 812a and 812b,. Any one or more of the intermediate walls 814, the divider wall 818, the first end wall 810a, the second end wall 810b, the first side wall 812a, and the second side wall 812b can contact respective ground contact pads of the GPU when the electrical connector is mated to the GPU.

[0112] In some examples, the at least one intermediate wall 814 can be referred to as at least one first intermediate wall 814, and the openings 816 can be referred to as first openings 816. The void 808 can further include a plurality of second openings 817. In particular, the interface body 806, and thus the ground interface 805a, can include at least one second intermediate wall 820, which can be configured as a single intermediate wall 820 or a plurality of second intermediate walls 820 disposed between the first and second side walls 812a and 812b. The at least one second intermediate wall 820 can be offset from each at least one first intermediate wall 814 along the longitudinal direction L. For instance, the at least one second intermediate wall 820 can extend from the divider wall 818 to the second end wall 810b. While the first and second intermediate walls 814 and 820 can thus extend from the same divider wall 818, it should be appreciated that the first and second intermediate walls 814 and 820 can extend from different divider walls 818. Thus, it can be said that the first and second intermediate walls 814 and 820 can extend from a respective at least one divider wall that can be defined by the same divider wall 818 or from different divider walls 818. It should be appreciated that when the respective at least one divider wall are defined by different divider walls, the different divider walls can be referred to as end walls.

[0113] When the at least one second intermediate wall 820 includes a plurality of second intermediate walls 820, the second intermediate walls 820 can be spaced from each other along the lateral direction A. Further, the second intermediate walls 820 can be elongate along the longitudinal direction L. Adjacent ones of the second intermediate walls 820 can divide the void 808 into the plurality of second openings 817. When the interface body 806 includes a single second intermediate wall 820, the intermediate wall 820 divides the void 808 into a pair of second openings 817 that extend from the second intermediate wall 820 to respective different ones of the first and second side walls 812a and 812b. The second openings 817 that can each be aligned with or disposed in a respective at least one signal contact location of the GPU, such as a respective pair of signal contact locations of the GPU, when the electrical connector is mated to the GPU. Thus, the pairs of signal contact locations can be electrically isolated from the interface body 806. It should be similarly appreciated that the mating portions of the signal contacts of the electrical connector can be aligned with respective ones of the second openings 817 so as to contact the signal contact locations of the second row when the electrical connector is mated to the GPU. The mating portions of the signal contacts of the electrical connector can thus also be electrically isolated from theinterface body 806. The second openings 817 can be enclosed by a respective pair of adjacent second intermediate walls 820, the second end wall 810a, and the respective divider wall 818.

[0114] In this regard, it should be appreciated that the GPU can include first and second rows of signal contact locations, whereby the rows are spaced from each other along the longitudinal direction L. At least one such as a pair of adjacent signal contact locations of the first row of signal contact locations can be disposed in different ones of the first openings 816. At least one such as a pair of adjacent signal contact locations of the second row of signal contact locations can be disposed in different ones of the second openings 817. The electrical connector can similarly include first and second rows of signal contacts that are configured to mate with electrical signal contact locations of the GPU of the first and second rows, respectively. The GPU can include ground contact locations between adjacent pairs of signal contact locations along the lateral direction A. It should be appreciated that the ground contact locations and the signal contact locations of the GPU can define any suitable alternative arrangement as desired.

[0115] With continuing reference to Fig. 10, each at least one first intermediate walls 814 can be offset with respect to each at least one second intermediate wall 820 along the lateral direction A. Further, the first side wall 812a defines a first portion that is aligned with the at least one first intermediate wall 814 along the lateral direction A, and a second portion that is aligned with the at least one second intermediate wall 820 along the lateral direction. The first portion can be jogged with respect to the second portion along the lateral direction A. Similarly, the second side wall 812b defines a first portion that is aligned with the at least one first intermediate wall 814 along the lateral direction A, and a second portion that is aligned with the at least one second intermediate wall 820 along the lateral direction. The first portion of the second side wall 812b can be jogged with respect to the second portion of the second side wall 812b along the lateral direction A in the same direction that the first portion of the first side wall 812a is jogged with respect to the second portion of the first side wall 812a. Thus, each first intermediate wall 814 can be at least partially aligned with one of the second openings 817 along the longitudinal direction L. Conversely, each second intermediate walls 820 can be at least partially aligned with one of the first openings 816 along the longitudinal direction L. Alternatively, as shown in Fig. 11A, the first andsecond portions of the first and second side walls 812a and 812b can be inline with each other, for instance along the longitudinal direction L.

[0116] When the electrical connector is mated to the GPU, any location of the interface body 806 can contact respective ones of the ground contact pads. In one example, any one or more of the first and second intermediate walls 814 and 820, the divider wall 818, the first end wall 810a, the second end wall 810b, the first side wall 812a, and the second side wall 812b can contact respective ones of the ground contact pads of the GPU when the electrical connector is mated to the GPU. The interface body 806, including all of the walls of the interface body 806, can define an inner surface 822a that faces the GPU. In some examples, the inner surface 822a can contact respective ground contact locations of the GPU when the electrical connector is mated to the GPU. The interface body 806 can define an outer surface 822b opposite the inner surface 822a along the transverse direction T (see, e.g., Fig. 11C). In one example, the electrical connector can include first and second ground interfaces 805 disposed on opposite sides of the receptacle of the electrical connector, and are thus configured to contact the first and second major surfaces, respectively, of the GPU in the manner described herein. As shown at Figs. 10-11 A, the inner surface 822a can be substantially planar.

[0117] Referring to Fig. 11 A, the interface body 806, and thus the ground interface 806, can be devoid of the intermediate walls 814 and 820. Thus, the divider wall 818 can divide the void 808 into a first void region 808a and a second void region 808b. The first void region 808a can be defined by the divider wall 818, the first end wall 810a, and the first and second side walls 812a and 812b. The second void region 808b can be defined by the divider wall 818, the second end wall 810a, and the first and second side walls 812a and 812b. Any one of or more up to each of the first end wall 810a, the second end wall 810b, the first side wall 812a, the second side wall 812b, and the divider wall 818 can contact respective one or more ground contact pads. The first and second side walls 812a and 812b can extend straight, linearly, and continuously from the first end wall 810a to the second end wall 810b

[0118] Referring now to Fig. 1 IB, in some examples a ground interface 805b can be constructed as described above with respect to the ground interface 805 of Fig. 10 or the ground interface 805a of Fig. 11A. Further, the ground interface 805b can include a plurality of protrusions 905 that extend from the interface body 806 in an inward direction that isdefined as lateral direction A from the outer surface of the interface body 806 toward the inner surface of the interface body 806. The inward direction can thus be oriented along the transverse direction T. The protrusions 905 can be oriented along lateral direction A that includes the inward direction and lateral direction A perpendicular to the inward direction, such as the longitudinal direction L. For instance, the protrusions 905 can be flared in an insertion direction as they extend in the inward direction. The insertion direction is the direction in which the receptacle 430 receives the GPU. Further, all of the protrusions 905 can be identical in size and shape. The protrusions 905 can extend from any portion of the interface body 806 as desired, such as the inner surface. The protrusions 905 can extend into the receptacle 430. Further, the protrusions 905 can be configured to flex or compress in the transverse direction T when a compressive force is applied to the protrusions toward the inner surface 822a. For instance, when the edge card connector is mated to the GPU 105, the GPU can apply the compressive force to the protrusions 905. In this regard, the protrusions 905 can be configured as spring fingers 907 that resiliently flex toward the inner surface 822a in response to the compressive force. Thus, the protrusions 905 can apply a force against the GPU, and in particular against the ground contact locations when the electrical connector is mated to the GPU. In one configuration shown in Fig. 11 A, the protrusions 905 can extend from any one or more up to all of the first end wall 810a, the second end wall 810b, the first side wall 812a, the second side wall 812b, and the divider wall 818. In the configuration shown in Fig. 10, the protrusions 905 can further extend from either or both of the first and second intermediate walls 814 and 820.

[0119] In one example, a respective first plurality of end wall protrusions 905 that extend from the first end wall 810a can be aligned with a first one of the openings 816 along respective planes that include the longitudinal direction L and the transverse direction T. A respective second plurality of the end wall protrusions 905 can extend from the first end wall and can be aligned with a second one of the openings 816 along respective planes that include the longitudinal direction L and the transverse direction T. Similarly, a respective first plurality of end wall protrusions 905 that extend from the second end wall 810b can be aligned with the first one of the openings 816 along respective planes that include the longitudinal direction U and the transverse direction T. A respective second plurality of end wall protrusions 905 can extend from the second end wall 102b and can be aligned with the second one of the openings 816 along respective planes that include the longitudinal directionL and the transverse direction T. The respective first plurality of end wall protrusions 905 that extend from the first end wall 810a can be aligned with the respective first plurality of end wall protrusions 905 that extend from the second end wall 810b along the longitudinal direction L. Similarly, respective second plurality of end wall protrusions 905 that extend from the first end wall 810a can be aligned with the respective second plurality of end wall protrusions 905 that extend from the second end wall 810b along the longitudinal direction L.

[0120] Alternatively or additionally, a respective first plurality of side wall protrusions 905 that extend from the first side wall 812a can be aligned with each opening 816 along respective planes that include the lateral direction A and the transverse direction T. A respective second plurality of sidewall protrusions 905 can extend from the second side wall 812b and can be aligned with each of the openings 816 along respective planes that include the lateral direction A and the transverse direction T. Alternatively or additionally still, a plurality of divider wall protrusions 905 that extend from the divider wall 818 can be aligned with each of the openings 816 along respective planes that include the lateral direction A and the transverse direction T. Further, the divider wall protrusions 905 can extend into the respective openings 816. The end wall protrusions 905 that extend from the first end wall 810a can extend away from the respective openings 816.

[0121] Referring now to Fig. 11 C, a ground interface 805c can be constructed in accordance with any of the ground interface 805 of Fig. 10, the ground interface 805a of Fig. 11 A, or the ground interface 805b of Fig. 1 IB. As shown, the ground interface 805c can be configured as described with respect to the ground interface 805 of Fig. 10, but the protrusions 905 can be configured as tabs 2605 that extend out from the inner surface 822a. In one example, the tabs 2605 can extend from the end walls 810a and 810b, and from the divider wall 818 if present. In some examples, the interface body 806 can be devoid of tabs 2605 at the side walls 812a and 812b, and each intermediate wall 814 and 820 if present. The protrusions 905 can be first to mate with the GPU and the first to unmate from the GPU relative to the signal contacts of the electrical connector.

[0122] Similar to the protrusions 905 of Fig. 11 B, the tabs 2605 can be configured to flex or compress in the transverse direction T when a force is applied. . When a GPU 105 is coupled to the edge card connector, the tabs 2605 can flex in the transverse direction T, and can apply a compressive force on the GPU substrate. Additionally, as the tabs 2605 can be composed of a liquid metal or amorphous metal, the tabs 2605 can deform under differentlevels of compressive force. Fig. 11D shows a schematic of a liquid metal surface under increasing (from top to bottom) or decreasing (from bottom to top) levels of load. As shown, a number of ridges 2705 can define a sinusoidal path along the tabs 2605. As the compressive force on the tabs 2605 increases, the amplitude if the ridges 2705 decreases. Further, the frequency of the ridges 2705 increases. Thus, the number of ridges increases along each of the tabs 2605, which can correspondingly increase the number of contact points between the tabs 2605 and the GPU 105 that applies the compressive force to the tabs 2605. This can provide for a better electrically conductive properties experienced by the interface between the ground interface 805c and the GPU 105. Conversely, when the compressive force on the tabs 2605 decreases, the amplitude of the ridges 2705 can decrease. Further, the frequency of the ridges 2705, and thus the number of ridges 2705 along each of the tabs 2605, can decrease.

[0123] The tabs 2605 can extend from any portion of the interface body 806 as desired, such as the inner surface. The protrusions 905 can extend into the receptacle 430. Further, the tabs 2605 can flare along the insertion direction as they extend in the inward direction. The protrusions 905 can be configured to flex or compress in the transverse direction T when a compressive force is applied to the protrusions toward the inner surface 822a. For instance, when the edge card connector is mated to the GPU 105, the GPU can apply the compressive force to the protrusions 905. The protrusions 905 can be configured as spring fingers that resiliency flex toward the inner surface 822a in response to the compressive force. Thus, the protrusions 905 can apply a force against the GPU, and in particular against the ground contact locations when the electrical connector is mated to the GPU.

[0124] Each of the first end wall 810a and the second end wall 810b can define a respective first portion aligned with a first one of the first openings 816 and a first one of the second openings 817, respectively, and a respective second portion aligned with a second one of the first openings 816 and a second one of the second openings 817, respectively. The divider wall 818 can include a first portion that is aligned with the first one of the first openings 816, and a second portion that is aligned with the second one of the first openings 816.

[0125] The interface body 806 can include a respective first end wall tab 2605 that extends from the first portion of the first end wall 810a, and is aligned with the first one ofthe first openings 816 along a respective plane that includes the longitudinal direction L and the transverse direction T. The respective first end wall tab 2605 can extend along a majority of the width of the first one of the first openings along the lateral direction A. The interface body 806 can include a respective second end wall tab 2605 that extends from the second portion of the first end wall 810a, and is aligned with the second one of the first openings 816 along a respective plane that includes the longitudinal direction L and the transverse direction T. The respective second end wall tab 2605 can extend along a majority of the width of the second one of the first openings along the lateral direction A.

[0126] The interface body 806 can include a respective first end wall tab 2605 that extends from the first portion of the second end wall 810a, and is aligned with the first one of the second openings 817 along a respective plane that includes the longitudinal direction L and the transverse direction T. The respective first end wall tab 2605 can extend along a majority of the width of the first one of the second openings 817 along the lateral direction A. The interface body 806 can include a respective second end wall tab 2605 that extends from the second portion of the second end wall 810b, and is aligned with the second one of the second openings 817 along a respective plane that includes the longitudinal direction L and the transverse direction T. The respective second end wall tab 2605 can extend along a majority of the width of the second one of the second openings 817 along the lateral direction A.

[0127] The interface body 806 can include a first divider wall tab 2605 that extends from the first portion of the divider wall 818, and is aligned with the first one of the first openings 816 along a respective plane that includes the longitudinal direction L and the transverse direction T. The first divider wall tab 2605 can extend along a majority of the width of the first one of the first openings 816 along the lateral direction A. In one example, the first divider wall tab 2605 can be aligned, for instance in its entirety, with the respective first end wall tab 2605 that extends from the first end wall 810a. Further, the first divider wall tab 2605 and the respective first end wall tab 2605 that extends from the first end wall 810a can have the same width along the lateral direction A. The interface body 806 can include a second divider wall tab 2605 that extends from the second portion of the divider wall 810b, and is aligned with the second one of the first openings 816 along a respective plane that includes the longitudinal direction L and the transverse direction T. The second divider wall tab 2605 can extend along a majority of the width of the second one of the firstopenings 816 along the lateral direction A. In one example, the second divider wall tab 2605 can be aligned, for instance in its entirety, with the respective second end wall tab 2605 that extends from the first end wall 810a. Further, the second divider wall tab 2605 and the respective second end wall tab 2605 that extends from the first end wall 810a can have the same width along the lateral direction A. In one example, all of the tabs 2605 can have the same width along the lateral direction A. Further, all of the tabs 2605 can be identical in size and shape. It should be appreciated that respective entireties of the tabs can be aligned with the respective aligned openings.

[0128] Fig. 12 shows an elevated view of a configuration for the first or second electrical cable assemblies according to the present disclosure. While Fig. 12 will be discussed in relation to the first electrical cable assembly, the configuration can also be implemented with respect to the second electrical cable assembly.

[0129] In some cases, the first electrical cables of the first electrical cable assembly can include a staggered configuration, where certain first electrical cables extend in the longitudinal direction L further than other first electrical cables. For example, first electrical cables 1005 and 1010 can extend further in the longitudinal direction L as compared to the first electrical cables 1015 and 1020. Thus, the first electrical cables 1005 and 1010 can couple, via their respective electrical contacts 607 at a different location along the longitudinal direction L as compared to the first electrical cables 1015 and 1020. Likewise, the mating interfaces 610 of the GPU 105 for , the first electrical cables 1005 and 1010 can be positioned or defined at different positions in the longitudinal direction L as compared to the mating interfaces 610 for the first electrical cables 1015 and 1020. This staggered configuration can provide for a maximizing of space in the lateral direction A on the GPU surface 620 (e g., such that interference between adjacent mating interfaces 610 is minimized). Alternatively, Fig. 13 shows a configuration where each of the GPU mating interfaces 610 are at a same distance in the longitudinal direction L with respect to each other. The first electrical cables 1005 to 1120 can likewise be positioned along the same distance in the longitudinal direction L for mating to the respective interface 610.

[0130] Fig. 14 shows an elevated perspective view of an edge card connector coupled to a GPU according to the present disclosure. In Fig. 14, the planar outer layer 530 and the edge portion 532 are removed. Fig. 14 shows some of the first electrical cable assembly 415 coupled to their respective mating interfaces 610. Further, the configuration ofthe first electrical cable assembly 415 can be a staggered configuration, such as that described with reference to Fig. 12.

[0131] In some cases, a dielectric spacer can be positioned between respective electrical contacts 607 of an electrical cable. For example, a dielectric spacer 1205 can be positioned between the electrical contact 607-a and the electrical contact 607-b. The dielectric spacer 1205 can extend from the mounting ends 606 to the mating ends 608 of the electrical contacts. The dielectric spacer 1205 can be composed of a dielectric, and can facilitate minimizing electrical interference between the electrical contacts 607-a and 607-b. Further, the dielectric spacer 1205 can also facilitate synchronous movement between the electrical contacts 607-a and 607-b, and can minimizing lateral movement (e.g., in the lateral direction A) between the electrical contacts 607-a and 607-b.

[0132] Fig. 15 shows a side perspective view of another embodiment of a second planar portion 428 coupled to a GPU 105. In some cases, the planar inner layer 534 and the planar outer layer 533 can extend from both the first end 510 and the second end 512. Thus, the entirety of the cavities of the second cavity assembly can be defined by the planar inner layer 534 and the planar outer layer 533.

[0133] Fig. 16 shows an elevated perspective view of a GPU 105 according to the present disclosure. The mating interfaces 610 can be positioned or defined on a surface 620 of the GPU 105. For example, the mating interfaces 610 can include electrically conductive contact pads. The mating interfaces 610 can be, for example, printed and or etched on the surface 620. In some cases, the mating interfaces 610 can be adjacent to other electrically conductive material 1405 along the surface 620. The mating interfaces 610 can be separated from the other electrically conductive material 1405 by a spaces 1410 where the surface 620 of the substrate is exposed. Thus, the spaces 1410 can facilitate the mitigation of electrical interference between the mating interfaces 610 and the conductive material 1405. Additionally, the ground interface(s) 805 of the edge card connector can be configured to contact the other electrically conductive material 1405, which can further mitigate electrical interference experienced by the coupling between the mating interface 610 and electrical contact 607 of an electrical cable.

[0134] Fig. 17 is a perspective view of a first portion 426 of an edge card connector as described herein. As shown, the first portion 426 can include a ground interface 805. The interface body 806 ,and thus the ground interfaces 805, can include first and secondend walls 810a and 810b, and first and second side walls 812a and 812b that have jogged first and second portions in the manner described above with respect to Figs. 10 and 11C. However, the interface body 806 can define a single first opening 816 and a single second opening 817. Alternatively, the interface body 806 can define a plurality of first openings 816 and second openings 817 as desired. The ground plate can include protrusions 905 in the form of tabs 2605 of Fig. 11C, but it should be appreciated that the protrusions 905 can alternatively or additionally include the spring fingers of Fig. 1 IB. As shown, the tabs 2605 can include first and second end wall tabs that extend from the first end wall 810a and over the first and second ones of the openings 816, respectively. The tabs 2605 can further include first and second divider wall tabs that extend from the at least one divider wall 818 and over the first and second ones of the second openings 817, respectively. As shown, the at least one divider wall 818 can be configured as a pair of divider walls that define respective end walls 810b and 810a for the openings 816 and 818, respectively.

[0135] The interface body 806, and thus the ground interface 805, can further include a plurality of suspended resilient ground contact members 1503. The ground members 1503 can be suspended over the connector housing and the inner surface of the interface body 806 in the inward direction, and thus can be inwardly offset with respect to the end walls 810a-b and side walls 812a-b. In one example, at least a portion of the ground members 1503 can extend into the receptacle of the electrical connector. The ground members 1503 can, for instance, include a first plurality of ground members 1503 that extend from a first end wall 810a to the at least one divider wall 818. For instance, the ground members 1503 of the first plurality of ground members 1503 can include laterally outermost ground members 1503, and an intermediate ground member 1503 that extends over the first intermediate wall 814. Similarly, the ground members 1503 of the second plurality of ground members 1503 can include laterally outermost ground members 1503, and an intermediate ground member 1503 that extends over the second intermediate wall 820. The ground members 1505 can define a plurality of ridges 1505 that define contact locations that contact the GPU when the electrical connector is mated with the GPU. In one example, the ridges 1505 can contact respective ground contact members of the GPU. The ground members 1505 can be configured to compress when urged against the GPU when the GPU applies a compressive force to the ground members 1505, which can occur when the GPU is received in the receptacle of the connector. Fig. 17 shows pairs of the electrical signal contacts of theelectrical connector extending through respective ones of the openings 816 and 817 in the manner described above.

[0136] Fig. 18 shows a magnified side view of an electrical contact 607 mated to a mating interface 610 of a GPU 105 according to the present disclosure. When mated, the mating end 608 of the electrical contact 607 can be in contact with the mating interface 610 of the GPU 105. The GPU 105 can also include mating interfaces 710 on the side 621 opposite the side 620. In one example, the mating interfaces 710 can be configured as contact pads. The edge card connector can thus include the first second electrical cable assemblies 415 and 416, and can be in electrical communication with the GPU via both sides 620 and 621.

[0137] Further, in some cases the GPU 105 can include an electric shield 1605. The electric shield can be disposed on the surface 620 can partially surround the mating interface(s) 610. For example, the electric shield 1605 can form a partial enclosure around the mating interface(s) 610. The electric shield 1605 can in some cases be composed of a dielectric, and can thus mitigate electrical interference experienced by the coupling between the electrical contacts 607 and the mating interfaces 10. Additional views of the electric shield 1605 can be seen in Figs. 19 to 21.

[0138] In some cases, the edge card connector can include electrical shielding as shown in Figs. 20 to 23. The first electrical cable assembly 415 can be arranged along respective rows that are oriented along a lateral direction A. Mounting ends of the first electrical cable assembly 415 can be inserted into contact array housings 2005. The electrically conductive wires of the first electrical cables can be exposed (e.g., from an exterior sheath), and can be mounted to corresponding mounting ends of a first electrical contacts. The first electrical contacts 2010 can likewise be arranged in a row oriented along the direction A, and extend away from the housing 2005 in the direction L. The first electrical contacts 2010 can be composed of an electrically conductive material, such as a metal. Each first electrical cable can be coupled to one or more electrical contacts 2010. For example, each electrically conductive wire of the first electrical cable can be coupled to a respective electrical contact 2010. Thus, a twinaxial cable can be coupled to two electrical contacts.

[0139] Further, the first electrical contacts 2010 can be surrounded, or partially surrounded, by a respective first electrical shield 2015. The first electrical shields 2015 form a cavity, within which the first electrical contacts 2010 are positioned. In some cases, the firstelectrical shields 2015 extend past the mating ends 2020 of first electric contacts 2015 (e.g., the mating ends are within the cavity of the first electrical shield 2015). In some cases, the mating ends extend past the first electrical shield 2015, and thus the mating ends are exposed from the first electrical shield 2015.

[0140] The first electrical contacts 2020 can be configured to mate to corresponding second electrical contacts 2105, which can be in electrical communication with a GPU 105. For example, mounting ends of the second electrical contacts 2105 can be mounted to an interface of the GPU, such as interface 610 of Fig. 8. In some cases, the first electrical contacts 2010 can include a post and a receptacle, which can mate to a corresponding receptacle and post of the second electrical contacts 2105. In some cases, the second electrical contacts 2105 can extend in the longitudinal direction L from an edge of the GPU.

[0141] The second electrical contacts 2105 can be surrounded, or partially by, a respective second electrical shield 2110. The second electrical shield 2110 can include one or more tabs 2115 that can extend into the cavity formed by the second electrical shield 2110. The second electrical shield 2105 can be configured to receive the first electrical shield 2015 when the first electrical contacts 2015 are mated to the second electrical contacts 2105. The exterior surface of the first electrical shield 2015 can contact the tabs 2115 of the respective second electrical shield 2110, which can place the first and second electrical shields in electrical communication with each other. As the first electrical contacts and the second electrical contacts are electrically isolated from both shields when mated, the first and second electrical shield can facilitate the mitigation of electrical interference experienced by the coupling. Fig. 24 shows a post and receptacle configuration, which can be an example of the first electrical contacts 2010 or the second electrical contacts 2105. Fig. 23 shows a top perspective view of mounting ends of the first electrical cables and the first electrical contacts 2010.

[0142] While systems and methods have been described in connection with the various embodiments of the various figures, it will be appreciated by those skilled in the art that changes could be made to the embodiments without departing from the broad inventive concept thereof. It is understood, therefore, that this disclosure is not limited to the particular embodiments disclosed, and it is intended to cover modifications within the spirit and scope of the present disclosure as defined by the claims.

Claims

What is claimed:

1. A data communication system comprising: a data communication cable terminating at a first and a second end and configured to transfer data; a first edge card connector coupled to the first end of the data communication cable; and a second edge card connector coupled to the second end of the data communication cable, such that the first edge card connector and the second edge card connector are in direct data communication with each other over the data communication cable so as to transfer data between the first and second edge card connectors.

2. The data communication system of claim 1, wherein the first and second edge card connectors have substantially identical mating interfaces.

3. The data communication system of claim 2, wherein the first and second edge card connectors are substantially identical to each other.

3. The data communication system of any one of the preceding claims, wherein the mating interfaces are configured to mate with different substrates.4 The data communication system of claim 3, wherein the substrates are configured as graphic processing units.

5. The data communication system of claim 4, wherein the graphic processing units are oriented in a tile configuration.

6. The data communication system of claim 4, wherein the graphic processing units are oriented in a peripheral component interconnect configuration.

7. The data communication system of claim 6, wherein the peripheral component interconnect configuration is a peripheral component interconnect express configuration.

8. The data communication system of any one of the preceding claims, wherein the mating interfaces are configured to mate with contact pads adjacent an edge of the respective substrates.

9. The data communication system of any one of the preceding claims, wherein the data communication cable comprises an electrical cable configured to transfer data as electrical signals between the edge card connectors.

10. The data communication system of claim 9, wherein the electrical cable comprises a twin axial cable having first and second electrical conductors that transfer differential signal pairs between the first and second edge card connectors.

11. The data communication system of claim 10, wherein the electrical cable comprises a pair of coaxial cables having respective electrical conductors that in combination transfer differential signal pairs between the first and second edge card connectors.

12. The data communication system of claim 9, wherein the electrical cable comprises a flex cable.

13. The data communication system of any one of claims 1 to 4, wherein the data communication cable comprises an optical cable configured to transfer data in the form of optical signals.

14. The data communication system of any one of the preceding claims, comprising at least three edge card connectors and a plurality of cables that place each of the edge card connectors in direct data communication with all others of the edge card connectors.

15. The data communication system of claim 14, wherein each cable defines respective first and second ends that are mounted to different ones of the edge card connectors that are, in turn, mated to different graphic processing units.16.. The data communication system of any one of the preceding claims, comprising a number of edge card connectors, the number being in a geometric sequence of a power of 2, and a plurality of cables that each of the edge card connectors in data communication with all others of the edge card connectors.

17. The data communication system of claim 16, wherein the number is at least eight.

18. The data communication system of claim 17, wherein the number is sixteen.

19. The data communication system of claim 18, wherein the number is thirty -two.

20. The data communication system of any one of the preceding claims, configured to communicate signals between all of the edge card connectors having cross talk no worse than -70 dB up to 28 GHZ PAM 4.

21. The data communication system of any one of the preceding claims, configured to communicate signals between all edge card connectors having cross talk no worse than -70 dB up to 112 gigabits per second.

22. The data communication system of any one of the preceding clams, further comprising: a first graphic processing unit coupled to the first edge card connector of the first electrical connector; and a second graphic processing unit coupled to the second edge card connector, thereby directly coupling the first graphic processing unit to the second graphic processing unit via the data communication cable.

23. The data communication system of claim 22, wherein the first graphic processing unit defines a first set of mating interfaces along a first surface, and a second set of mating interfaces along a second surface.

24. The data communication system of claim 23, wherein the first surface and the second surface each define a plane that are parallel to one another.

25. The data communication system of claim 22, wherein an edge of the first graphic processing unit is disposed in a cavity defined by the first edge card connector of the electrical connector, and wherein the first set of mating interfaces of the graphic processing unit are coupled to respective first mating interfaces of the first card connector, and the second set of mating interfaces of the first graphic processing unit are coupled to respective second mating interfaces of the first card connector.

26. The data communication system of claim 25, further comprising a ground shield array enclosing the respective first or second mating interface.

27. The data communication system of claim 25, wherein respective first or second mating interfaces of the first edge card connector are disposed within the ground shield array.

28. The data communication system of claim 25, wherein the ground shield array comprises an electrically conductive elastomer.

29. The data communication system of claim 22, further comprising: a second electrical connector of claim 1; a third graphic processing unit coupled to the first edge card connector of the second electrical connector; and the second edge card connector of the second electrical connector coupled to either the first graphic processing unit of the second graphic processing unit, thereby directly coupling the third graphic processing unit to either the first graphic processing unit or the second graphic processing unit via the second electrical connector.

30. The data communication system of claim 29, further comprising: a third electrical connector of claim 1; the third graphic processing unit coupled to the first edge card connector of the third electrical connector, and the second edge card connector of the third electrical connector coupled to either the second graphic processing unit or the first graphic processing unit, thereby directly coupling the third graphic processing unit to either the second graphic processing unit or the first graphic processing unit via the third electrical connector.

31. The data communication system of any one of the preceding claims, wherein the first edge card connector comprises: a housing defining one or more cavities that run along a central axis of the housing, and wherein each of the one or more cavities contain a respective cable of the electrical cable.

32. The data communication system of any one of the preceding claims, wherein the housing further defines a first face and a second face, wherein the first face extends perpendicular to the central axis, and the second face extends parallel to the central axis.

33. The data communication system of any one of the preceding claims, wherein the first face is configured to contact a side edge of a graphic processing unit when coupled, and the second face is configured to contact a top surface of the graphic processing unit when coupled.

34. The data communication system of any one of the preceding claims, wherein the housing further defines a third face that extends parallel to the central axis.

35. The data communication system of any one of the preceding claims, wherein the third face is configured to contact a bottom surface of a graphic processing unit when coupled.

36. The data communication system of any one of the preceding claims, wherein the first face, the second face, and the third face define a cavity configured to receive an edge of a graphic processing unit (GPU).

37. The data communication system of any one of the preceding claims, wherein the one or more cavities comprise a first cavity group and a second cavity group, and wherein the second face is positioned between the first cavity group and the first face, and wherein the third face is positioned between the first face and the second cavity group.

38. The data communication system of any one of the preceding claims, wherein a first cable assembly are disposed in respective cavities of the first cavity group, and wherein a second cable assembly are disposed in respective cavities of the second cavity group.

39. The data communication system of any one of the preceding claims, wherein respective cables of the first cable assembly are each configured to couple to a respective interface on a top surface of a graphic processing unit.

40. The data communication system of any one of the preceding claims, wherein respective cables of the second cable assembly are each configured to couple to a respective interface on a bottom surface of a graphic processing unit.

41. The data communication system of any one of the preceding claims, wherein the respective interface comprises an electrical contact pad.

42. The data communication system of any one of the preceding claims, wherein each electrical connector comprises an electrical contact.

43. The data communication system of any one of the preceding claims, wherein the electrical contact defines a mating end and a mounting end, wherein the mounting end is coupled to a wire of the respective cable, and the mounting end is configured to contact a mating interface of a graphic processing unit.

44. The data communication system of any one of the preceding claims, wherein the one or more cavities extend parallel to the central axis.

45. The data communication system of any one of the preceding claims, wherein the electrical contact is angled from the coupled wire towards the central axis.

46. The data communication system of any one of the preceding claims, wherein the mating end comprises a hook, wherein a bend of the hook is configured to contact the mating interface of the graphic processing unit.

47. The data communication system of any one of the preceding claims, wherein the mating end is configured to flex away from the central axis when contacting with the mating interface of the graphic processing unit.

48. The data communication system of any one of the preceding claims, further comprising: a dielectric shield enclosing the mounting end of the electrical contact.

49. A data communication system, comprising: a first graphic processing unit; a second graphic processing unit; anda data communication cable coupled to a mating interface of the first graphic processing unit and a mating interface of the second graphic processing unit, wherein the first graphic processing unit is in direct data communication with the second graphic processing unit via the data communication cable.

50. The data communication system of claim 49, configured to communicate signals between the first and second graphic processing units along the data communication cable having cross talk no worse than -70 dB up to 28 GHZ PAM 4 along the data communication cable.

51. The data communication system of any one of claims 49 to 50, configured to communicate signals between the first and second graphic processing units along the data communication cable having cross talk no worse than -70 dB up to 112 gigabits per second along the data communication cable.

52. The data communication system of any one of claims 49 to 51, further comprising: a third graphic processing unit; a second data communication cable in direct data communication with each of the second and third graphic processing units, such that third graphic processing unit is in direct data communication with the second graphic processing unit via the second data communication cable.

53. The data communication system of claim 52, further comprising: a third data communication cable in direct data communication with each of the first and third graphic processing units, such that the third graphic processing unit is in direct data communication with the first graphic processing unit via the third data communication cable.

54. The data communication system of any of claims 49 to 53, wherein each data communication cable comprises a plurality of electrical cables.

55. The data communication system of any of claims 49 to 54, wherein the electrical cables comprise one or more flex cables.

56. The data communication system of any one of claims 49 to 55. wherein at least some of the data communication cables include data communication cables that are directly mounted to at least a respective one of the graphic processing units.

57. The data communication system of claim 56, wherein the data communication cables of at least some of the data communication cables are soldered to the at least a respective one of the graphic processing units.

58. The data communication system of any one of claims 49 to 57, further comprising a server chassis that contains each graphic processing unit and each data communication cable.

59. The data communication system of claim 58, wherein the first and second graphic processing units are spaced in the server chassis such that a third graphic processing unit is disposed between the first and second graphic processing units.

60. The data communication system of any one of claims 49 to 59, wherein each graphic processing unit has first and second ends opposite each other along a longitudinal direction so as to define a length of the graphic processing unit, first and second sides opposite each other along a lateral direction that is perpendicular to the longitudinal direction so as to define a width of the graphic processing unit, and first and second major surfaces opposite each other along a transverse direction that is perpendicular to each of the longitudinal and lateral directions so as to define a thickness of the graphic processing unit, wherein the length is greater than the width, and the width is greater than the thickness.

61. The data communication system of claim 60, wherein each graphic processing unit is configured as a tile graphic processing unit.

62. The data communication system of claim 61 , wherein the first and second major surfaces of at all of the graphic processing units are coplanar with the first and second major surfaces, respectively, of at least some of all others of the graphic processing units.

63. The data communication system of any one of claims 61 to 62. wherein at least some of the graphic processing units are aligned along the lateral direction.

64. The data communication system of claim 63, wherein one of the sides of each graphic processing units faces a respective one of the sides of an adjacent graphic processing unit aligned along the lateral direction.

65. The data communication system of any one of claims 61 to 64, wherein the graphic processing units are arranged in rows that are adjacent each other along the longitudinal direction.

66. The data communication system of claim 60, wherein each graphic processing unit is a configured as a peripheral component interface graphic processing unit.

67. The data communication system of claim 66, wherein at least one of the major surfaces of each graphic processing unit faces a major surface of another graphic processing unit.

68. The data communication system of any one of claims 66 to 67, wherein the first and second sides of at all of the graphic processing units are coplanar with the first and second sides, respectively, of at least some of all others of the graphic processing units.

69. The data communication system of any of claims 66 to 68, wherein the graphic processing units are arranged in banks, wherein the graphic processing units each bank are spaced from each other a first distance along the transverse direction, and adjacent banks are spaced from each other a second distance along the transverse direction that is greater than the first distance.

70. The data communication system of any one of claims 49 to 69, comprising eight graphic processing units, and each of the eight graphic processing units is in direct data communication with all others of the graphic processing units via the data communication cables.

71. The data communication system of any one of claims 49 to 70. comprising sixteen graphic processing units, and each of the sixteen graphic processing units is in direct data communication with all others of the graphic processing units via the data communication cables.

72. The data communication system of any one of claims 49 to 71, comprising thirty -two graphic processing units, and each of the thirty -two graphic processing units is in direct data communication with all others of the graphic processing units via the data communication cables.

73. The data communication system of any one of claims 70 to 72, wherein each of the graphic processing units is in direct data communication wi th each other of the graphic processing units via a plurality of the data communication cables.

74. The data communication system of any of one of claims 49 to 73, wherein the mating interface of the first graphic processing unit and the mating interface of the second graphic processing unit are disposed along an edge of the respective graphic processing unit.

75. The data communication system of any one of claims 49 to 74, wherein the data communication cable comprises a first mating interface and a second mating interface, wherein the first mating interface of the data communication cable is mated to the mating interface of the first graphic processing unit, and wherein the second mating interface of the data communication cable is mated to the mating interface of the second graphic processing unit.

76. The data communication system of claim 75, wherein the mating interface of the first graphic processing unit and the mating interface of the second graphic processing unit comprise edges, wherein one or more electrical contact pads are disposed on at least one major surface of the respective graphic processing unit adjacent the edges.

77. The data communication system of claim 76, wherein the mating interface of the first graphic processing unit and the mating interface of the second graphic processing unit comprise one or more electrical contact pads disposed on first and second opposed major surfaces of the respective graphic processing unit.

78. The data communication system of any one of claims 76 to 77, wherein the one or more electrical contact pads comprise differential signal pairs of electrical contact pads.

79. The data communication system of any one of claims 76 to 78, further comprising edge card connectors that are mated to respective edges of the first and second graphic processing units so as to place the edge card connectors in electrical communication with the contact pads.

80. The data communication system of claim 79, wherein the data communication cable comprises a plurality of electrical cables that are mounted to respective ones of the edge card connectors so as to place the first edge card connector in electrical communication with the second edge card connector.

81. The data communication system of claim 75, further comprising optical interconnect modules, and the data communication cable comprises optical cables that are in optical communication with respective optical engines of the optical interconnect modules.

82. The data communication system of claim 81, wherein the optical interconnect modules are in electrical communication with respective electrical conductor of the graphic processing units.

83. A method of data communication between a plurality of graphic processing units within a server chassis, the method comprising the steps of: transferring data signals along data communication cables directly from a first one of the plurality of first graphic processing units to a second one of the plurality of graphic processing units;transferring data signals along data communication cables directly from the first one of the plurality of first graphic processing units to a third one of the plurality of graphic processing units; and transferring data signals along data communication cables directly from the second one of the plurality of first graphic processing units to a third one of the plurality of graphic processing units.

84. The method of claim 83, wherein none of the data signals are routed through a switch as they are transferred between the graphic processing units.

85. The method of any one of claims 83 to 84, wherein the cables are mounted to respective electrical connectors that are, in turn, mounted to respective ones of the plurality of graphic processing units.

86. The method of any one of claims 83 to 84, wherein the cables are mounted directly to electrical traces of respective ones of the plurality of graphic processing units.

87. The method of any one of claims 83 to 84, wherein the cables are electrical cables.

88. The method of claim 83, wherein the electrical cables comprise flex circuits.

89. The method of any one of claims 83 to 84, wherein the electrical cables comprise coaxial cables.

90. The method of any one of claims 83 to 85, wherein the electrical cables comprise twinaxial cables.

91. The method of any one of claims 83 to 90, wherein the plurality of graphic processing units comprises eight graphic processing units.

92. The method of any one of claims 83 to 91, wherein the plurality of graphic processing units comprises sixteen graphic processing units.

93. The method of any one of claims 83 to 92, wherein the plurality of graphic processing units comprises thirty-two graphic processing units.

94. The method of any one of claims 83 to 93, wherein the data signals have cross talk no worse than -70 dB up to 28 GHZ PAM 4.

95. The method of any one of claims 83 to 94, configured to communicate signals between all edge card connectors having cross talk no worse than -70 dB up to 112 gigabits per second.

96. The method of any one of claims 83 to 95, wherein the data communication cables comprise one or more electrical cables.

97. The method of any one of claims 83 to 96, wherein the data communication cables comprise one or more flex cables.

98. The method of any one of claims 83 to 97, wherein the data communication cables comprise a first mating interface and a second mating interface, wherein the first mating interface of the data communication cables is mated to the mating interface of the first graphic processing unit, and wherein the second mating interface of the data communication cables is mated to the mating interface of the second graphic processing unit.

99. The method of any one of claims 83 to 98, wherein the first graphic processing unit comprise a substrate, and wherein the substrate defines a first pnmary surface and a second primary surface separated by the first primary surface by a substrate thickness.

100. The method of any one of claims 83 to 99, wherein the first and second graphic processing units comprise tile graphic processing units.

101. The method of claim 100, wherein the first and second graphic processing units are oriented in the server chassis such that a length of a respective graphic processing unit runs along a length dimension of the server chassis, and a width of the respective graphic processing unit runs along a width dimension of the server chassis.

102. The method of any of claims 83 to 99, wherein the first and second graphic processing units comprise peripheral component interface graphic processing units.

103. The method of claim 102, wherein the first and second graphic processing units are oriented in the server chassis such that a length of a respective graphic processing unit runs along a length dimension of the server chassis, and a thickness of the respective graphic processing unit runs along a width dimension of the server chassis.

104. The method of any of claims 102 or 103, wherein the first graphic processing unit is disposed in a first graphic processing unit bank of the server chassis, and the second graphic processing unit is disposed in a second graphic processing unit bank of the server chassis.

105. The method of any of claims 83 to 104, wherein the first and second graphic processing units are spaced in the server chassis such that another graphic processing unit is disposed between the first and second graphic processing units.

106. The method of any of claims 83 to 105, wherein the mating interface of the first graphic processing unit and the mating interface of the second graphic processing unit are disposed along an edge of the respective graphic processing unit.

107. A data communication system, comprising: a first graphic processing unit; a second graphic processing unit; and means for communicating data coupled to a means for interfacing of the first graphic processing unit and a means for interfacing of the second graphic processing unit, wherein the first graphic processing unit is in direct data communication with the second graphic processing unit over the means for communicating data.

108. The data communication system of claim 107, configured to communicate signals between the first and second graphic processing units along the means for communicating data having cross talk no worse than -70 dB up to 28 GHZ PAM 4 along the means for communicating data.

109. The data communication system of any one of claims 107 to 108, configured to communicate signals between the first and second graphic processing units along the means for communicating data having cross talk no worse than -70 dB up to 112 gigabits per second along the means for communicating data.

110. The data communication system of any one of claims 107 to 109, further comprising: a third graphic processing unit; a second means for communicating data in direct data communication with each of the second and third graphic processing units, such that third graphic processing unit is in direct data communication with the second graphic processing unit via the second means for communicating data.

111. The data communication system of claim 110, further comprising: a third means for communicating data in direct data communication with each of the first and third graphic processing units, such that the third graphic processing unit is in direct data communication with the first graphic processing unit via the third means for communicating data.

112. The data communication system of any of claims 107 to 111, wherein each means for communicating data comprises an electrical cables.

113. The data communication system of any of claims 107 to 112, wherein each means for communicating data comprise one or more flex cables.

114. The data communication system of any one of claims 107 to 113, wherein at least some of the means for communicating data are directly mounted to at least a respective one of the graphic processing units.

115. A data communication system comprising: means for communicating data terminating at a first and a second end and configured to transfer data;a first means for connecting the first end of the means for communicating to a first graphic processing unit; and a second means for connecting the second end of the means for communicating data to a second graphic processing unit, thereby placing the first and second graphic processing units in direct data communication with each other over the means for communicating data.

116. The data communication system of claim 115, wherein the first and second means for connecting have substantially identical means for interfacing with respective graphic processing units.

117. The data communication system of claim 116, wherein the first and second means for connecting are substantially identical to each other.

118. The data communication system of any one of claims 116 to 117, wherein the graphic processing units are oriented in a tile configuration.

119. The data communication system of any one of claims 116 to 117, wherein the graphic processing units are oriented in a peripheral component interconnect configuration.

120. The data communication system of any one of claims 115 to 119, wherein the means for interfacing are configured to mate with contact pads adjacent an edge of the respective graphic processing units.

121. The data communication system of any one of claims 115 to 120, wherein the means for communicating data comprises an electrical cable configured to transfer data as electrical signals between the edge card connectors.

122. The data communication system of claim 121, wherein the electrical cable comprises a twin axial cable having first and second electrical conductors that transfer differential signal pairs between the first and second means for connecting.

123. The data communication system of claim 121, wherein the electrical cable comprises a pair of coaxial cables having respective electrical conductors that in combination transfer differential signal pairs between the first and second means for connecting.

124. The data communication system of claim 120, wherein the electrical cable comprises a flex cable.

125. The data communication system of any one of claims 115 to 120, wherein the means for communicating data comprises an optical cable configured to transfer data in the form of optical signals.

126. The data communication system of any one of claims 115 to 125, comprising a plurality of means for communicating data, and at least three means for placing respective ones of the means for communicating data to a respective one of the graphic processing units.

127. The data communication system of any one of claims 115 to 126, comprising a number of means for connecting, the number being in a geometric sequence of a power of 2, and a plurality of means for communicating data that each of the means for connecting in data communication with all others of the means for connecting.

128. The data communication system of claim 127, wherein the number is at least eight.

129. The data communication system of claim 127, wherein the number is sixteen.

130. The data communication system of claim 127, wherein the number is thirty-two.

131. The data communication system of any one of claims 115 to 130, configured to communicate signals between all of the edge card connectors having cross talk no worse than -70 dB up to 28 GHZ PAM 4.

132. The data communication system of any one of claims 115 to 131, configured to communicate signals between all edge card connectors having cross talk no worse than -70 dB up to 112 gigabits per second.

133. The method or data communication system of any one of the preceding claims, wherein the GPUs are disposed inside a chassis, and at least some of the data communication cables are routed outside the chassis.

134. A server chassis comprising: a housing;a plurality of graphic processing units disposed in the housing, wherein each of the graphic processing units has a respective plurality of data communication cables in data communication therewith; a plurality of data communication cables disposed in the housing, each having respective first and second ends in data communication with different ones of the graphic processing units, such that each of the graphic processing units is in direct data communication with each other of the graphic processing units over respective ones of the data communication cables.

135. The server chassis of claim 134, wherein the data communication cables comprise electrical cables.

136. The server chassis of claim 135, wherein the electrical cables comprise twinaxial cables.

137. The server chassis of claim 136, wherein the electrical cables comprise coaxial cables.

138. The server chassis of claim 134, wherein the data communication cables comprise flex circuits.

139. The server chassis of claim 134, wherein the data communication cables comprise optical cables.

140. The server chassis of claim 134, wherein the GPUs are arranged in a tile configuration.

141. The server chassis of claim 134, wherein the GPUs are arranged in a PCI configuration.

142. The server chassis of any one of claims 134 to 141, comprising eight GPUs.

143. A GPU system comprising a plurality of server chassis each as recited in any one of claims 134 to 142, wherein at least one GPU of each server chassis is in data communication with at least one other GPU in each other of the server chassis over at least one data communication cable.

Images