Unit cell of a multi-trench semiconductor device and semiconductor device

Abstract

The invention relates to a unit cell (10) of a multi-trench semiconductor device, wherein the unit cell (10) is configured as vertical field effect transistor cell having a carrier transport axis (14) defined between drain and source, wherein in a direction of a gate contact stripe axis (24) being perpendicular to the carrier transport axis (14), the unit cell (10) comprises on two opposite edges each a gate-recess (26) extending vertically through the n+source region (20) and the p-well region (18), wherein along a fin elongation axis (30) the unit cell (10) comprises on two opposite edges each at least one source-recess (32) extending vertically through the n+source region (20), wherein the vertical depth of the source-recess (32) is different to the vertical depth of the gate-recess (26), and wherein a bottom of the sourcerecess (32) is formed by the p-source region (22) of the source structure. Furthermore, the invention relates to a multi-trench semiconductor device, comprising multiple of the above unit cells (10). Furthermore, the invention relates to a method for producing the above multi-trench semiconductor device.

Description

[0001] Description

[0002] Unit cell of a multi-trench semiconductor device and Semiconductor device

[0003] Technical Field

[0004] The invention relates to a unit cell of a multi-trench semiconductor device.

[0005] Furthermore, the invention relates to a multi-trench semiconductor device, comprising multiple of the above unit cells.

[0006] Furthermore, the invention relates to a method for producing the above multi-trench semiconductor device.

[0007] Background Art

[0008] Power semiconductor devices are used as switches controlling the current flow through various electronic systems. Many power semiconductor devices make use of a metal-oxide-sem iconductor (MOS) structure. Devices that comprise a MOS structure are for example a power MOS field-effect transistor (MOSFET) designed to handle significant power levels or an insulated-gate bipolar transistor (IGBT).

[0009] While silicon (Si) is a very common semiconductor material for power semiconductor devices, power semiconductor devices formed with wide-bandgap semiconductor materials as substrate such as a silicon carbide substrate (SiC substrate) composed of silicon (Si) and carbon (C) bonded to each other at a composition ratio of 1 :1 are becoming more and more important, in particular for MOSFETs.

[0010] For example, SiC offers a number of attractive characteristics for high-voltage power semiconductors when compared to commonly used Si. Exemplarily the much higher breakdown field strength and a high thermal conductivity of SiC in principle allow creating devices which outperform by far the corresponding Si devices and enable reaching otherwise unattainable efficiency levels. SiC based power MOSFETs may offer superior dynamic performance over conventional Si based power MOSFETs.

[0011] In other words, the advantageous electro-thermal properties of SiC can provided significant improvements to the design trade-off between the transistor’s specific on- state resistance Ron* and its breakdown voltage (BV). At the same time, the continuous advances in the control of the gate and the unipolar character of these devices have allowed for operation at higher switching frequencies than in Silicon, hence facilitating reductions in the size of the passive components.

[0012] In other words, thanks to their superior electro-thermal properties, wide-bandgap power semiconductor devices have become attractive candidates as switching elements in various power converter applications. In particular, the development of the trench MOSFET architecture, also called U-shaped notch MOS field-effect transistor (U-MOSFET), where the gate electrode is buried in a trench etched in the semiconductor material, which results in a vertical channel, has allowed for significant reductions in the transistor’s specific on-state resistance Ron* (for the same BV), as well as further improvements in gate control and the suppression of the MOSFET’s parasitic bipolar junction transistor (BJT), due to the high built-in voltage.

[0013] Nevertheless, SiC trench MOSFETs are also known to suffer from significant reliability issues regarding the gate insulation due to the high electric field in the bottom portion of the gate insulation during blocking. Thus, there is a need for architectures that reduce the off-state electric fields, in particular at the bottom of the trench as well as in the gate insulation.

[0014] Summary of invention

[0015] It is an object of the invention to provide means to improve the performance and and / or reliability of semiconductor devices having a trench architecture. Furthermore, it is an object of the invention to reduce the off-state electric fields at the bottom of the trench and / or in the gate insulation. It is further an object of the present in invention to increase the freedom of design such that an improved trade-off between channel density of the semiconductor device and the semiconductor device blocking and surge current capabilities can be achieved. The object of the invention is solved by the features of the independent claims. Modified embodiments are detailed in the dependent claims.

[0016] Thus, the object is solved by a unit cell of a multi-trench semiconductor device, wherein the unit cell is configured as vertical field effect transistor cell having a carrier transport axis defined between drain and source, wherein the unit cell comprises:

[0017] - a substrate of a first conductive type acting as drain region,

[0018] - a body layer of a second conductivity type formed along the carrier transport axis on top of the substrate and acting as drift region, and

[0019] - a source structure provided on the body layer, the source structure comprising a p-well region, a n+source region, and a p-source region, the n+source region at least partially covering the p-well region, and the p-source region being below the p-well region, wherein in a direction of a gate contact stripe axis being perpendicular to the carrier transport axis, the unit cell comprises on two opposite edges each a gaterecess extending vertically through the n+source region and the p-well region, such that when multiple unit cells are arranged in a row along the gate contact stripe axis next two each other for forming the multi-trench semiconductor device a gate trench is formed by two gate-recesses of two neighbouring unit cells, wherein in the unit cell in between the two gate-recesses a first fin is formed, the first fin extending along a fin elongation axis being perpendicular to the carrier transport axis and being perpendicular to the gate contact stripe axis, wherein along the fin elongation axis the unit cell comprises on two opposite edges each at least one source-recess extending vertically through the n+source region, wherein the vertical depth of the source-recess is different to the vertical depth of the gate-recess, and wherein a bottom of the source-recess is formed by the p-source region of the source structure.

[0020] Additionally, the object is solved by a multi-trench semiconductor device, comprising multiple unit cells as described above, wherein the unit cells are arranged in a row along the gate contact stripe axis next two each other such that a gate trench is formed by two gate-recesses of two neighbouring unit cells.

[0021] The invention relates further to a method for manufacturing a multi-trench semiconductor device, the multi-trench semiconductor device comprising several unit cells, wherein the unit cell is configured as vertical field effect transistor cell having a carrier transport axis defined between drain and source, comprising the steps of

[0022] - providing a substrate of a first conductive type acting as drain region,

[0023] - forming a body layer of a second conductivity type acting as drift region along the carrier transport axis on top of the substrate,

[0024] - providing a source structure comprising a p-well region and a n+source region (20) on the body layer, the n+source region at least partially covering the p-well region,

[0025] - etching multiple gate trenches extending vertically through the n+source region and the p-well region, such that a gate recess is formed in a direction of a gate contact stripe axis being perpendicular to the carrier transport axis on two opposite edges of the unit cell, wherein in the unit cell in between the two gaterecesses a first fin is formed, the first fin extending along a fin elongation axis being perpendicular to the carrier transport axis and being perpendicular to the gate contact stripe axis,

[0026] - etching multiple source trenches extending vertically through the n+source region, such that at least one source-recess is formed along the fin elongation axis on two opposite edges of the unit cell, wherein the vertical depth of the source-recess is different to the vertical depth of the gate-recess, and

[0027] - forming a p-source region of the source structure at a bottom of the sourcerecess below the p-well region.

[0028] One aspect of the invention is that the unit cell and thus the multi-trench semiconductor device comprises in addition to the gate-recesses on two opposite edges each at least one source-recess extending vertically through the n+source region, such that the vertical depth of the source-recess is different to the vertical depth of the gate-recess and wherein the bottom of the source-recess is formed by the p- source region of the source structure. This has the effect that the unit cell cannot only take advantage of the increased channel mobility due to the first fin, but also that the off-state electric fields at the bottom of the gate-recess are reduced due to the fact that the bottom of the source-recess is formed by the p-source region of the source structure. Furthermore, due to the additional source-recess the freedom of design is increased and an improved compromise between the channel density, the blocking, and the surge capability of the semiconductor device can be implemented.

[0029] The unit cell and the multi-trench semiconductor device comprise several layers on top of each other - e.g. the body layer being provided on the substrate and the source structure being provided on the body layer. The substrate is of the first conductivity type, preferably n+type, while the body layer is of the second conductivity type and is preferably of n-type. In other words, the unit cell preferably has an n- type channel for the MOS capacitor.

[0030] As the unit cell is configured as vertical field effect transistor cell, the charge carriers, preferably electrons, traveling from source to drain travel along the carrier transport axis. In the context of this application the vertical direction along the carrier transport axis of the unit cell is the direction from the substrate / drain towards the source structure. “Up”, “upwards”, or “on top” means a location or direction closer to the source, while “down”, “downwards”, or “below” specifies a location or direction closer to the drain.

[0031] The carrier transport axis, the gate contact stripe axis, and the fin elongation axis together form a three-dimensional Cartesian coordinate system, with axes that are pair-wise perpendicular to each other. A first hyperplane defined by the carrier transport axis and the gate contact stripe axis has a normal vector that is parallel to the fin elongation axis, a second hyperplane defined by fin elongation axis and the gate contact stripe axis has a normal vector that is parallel to the carrier transport axis, and a third hyperplane defined by the carrier transport axis and the fin elongation axis has a normal vector that is parallel to the gate contact stripe axis.

[0032] The unit cell preferably has a primitive form in the shape of a cuboid, with two outer surfaces parallel to the first hyperplane, two outer surfaces parallel to the second hyperplane and two outer surfaces parallel to the third hyperplane. The two opposing edges of the cuboid that are defined by the outer surface parallel to the second hyperplane and the two outer surfaces parallel to the third hyperplane preferably comprise the gate-recess, that extends vertically through the n+source region and the p-well region. The two gate-recesses are preferably arranged opposite to each other, such that when two unit cells are arranged next to each other and the two outer surfaces having the gate-recess meet, the two gate-recesses of the two unit cells form a gate trench, the gate trench preferably having a u-form. The unit cell comprises in between the two gate-recesses the first fin, which preferably forms part of the channel region, where the charge carriers travel. The extent of the first fin in the fin elongation axis - i.e. the length of the first fin preferably corresponds to the width of the gate-recess in the fin elongation axis.

[0033] Further the two opposing edges of the unit cell, not comprising the gate-recess - i.e. the edges formed by the second hypersurface and the two first hypersurfaces - each comprise at least one source-recess. Regarding the source structure and as already mentioned, the n+source region at least partially covers the p-well region. The source structure further comprises the p+source region, forming the bottom of the source-recess and being below the p-well region.

[0034] Preferably, the multi-trench semiconductor device is a power semiconductor device. Further preferably the power semiconductor device is a 0.65 kV to 15 kV volt class power semiconductor device. Further preferably the power semiconductor device is configured for current ratings of 5 A to 600 A in a temperature range of 25 °C to 175 °C. According to another preferred embodiment of the invention the multi-trench semiconductor device is configured as a MOSFET, a MISFET (metal insulator semiconductor field-effect transistor), a JFET (junction field-effect transistor), an IGBT, or a BIGT (bi-mode insulated gate transistor). Particularly preferably, the multitrench semiconductor device is a multi-trench power MOSFET.

[0035] According to a preferred embodiment of the invention, the unit cell and / or the multitrench semiconductor device is of a semiconductor material having a bandgap equal to or greater than the bandgap of silicon. Particularly preferably, the bandgap is greater than that of silicon. Further preferably, the bandgap of the semiconductor material is greater than 1 .5 eV and further preferably greater than 2 eV. Regarding the material of the unit cell and / or the multi-trench semiconductor device and according to another preferred embodiment of the invention, the unit cell and / or the multi-trench semiconductor device is of a semiconductor material selected from the group consisting of silicon (Si), silicon carbide (SiC), gallium nitride (GaN), gal- lium(lll) oxide (Ga2Os), aluminium nitride (AIN), aluminium gallium nitride (AlxGa-i-XN), gallium arsenide (GaAs), and diamond. Preferably, the substrate, the body layer, as well as the source structure are based on the above-mentioned semiconductor materials. Preferably, the semiconductor material is SiC or GaN, and most preferably the semiconductor material is SiC. Particularly preferably, the multitrench semiconductor device is a SiC multi-trench power MOSFET. Further preferably the body layer - which acts as drift region - is preferably a 4H-SiC layer, meaning that the polytype of the SiC is 4H.

[0036] According to another preferred embodiment of the invention, the semiconductor material is SiC and wherein a (0001 ) surface of the body layer is parallel to the carrier transport axis. This allows for a high carrier mobility within the channel region of the first fin of the unit cell and / or multi-trench semiconductor device.

[0037] The source-recess having a different depth than the gate-recess further allows for an easy implementation of a protective p+layer that is biased to the source potential for further reducing the off-state electric fields at the bottom of the gate-recess. In this regard and according to a preferred embodiment of the invention, the gate-re- cess extends vertically through the n+source region and the p-well region into the body layer, wherein the vertical depth of the source-recess is less than the vertical depth of the gate-recess, wherein the unit cell comprises in addition a protective p+layer, the protective p+layer being arranged in the body layer below the gaterecess, and wherein the protective p+layer is connected to the p-well region of the source structure via the p-source region at the bottom of the source-recess. This has the advantage that the protective p+layer is biased to the potential of the source without impeding the flow of the carriers in the channel. Preferably the p-source region is not only formed at the bottom of the source-recess, but also in sidewalls of the source-recess, preferably through a tilted implant. Biasing the protective p+layer to the potential of the source has the advantage that in switching applications the protective p+layer do not get gradually depleted of free carriers by multiple switching and thereby increasing the local electric field, as could be the case for protective p+layer that is left floating (i.e. not biased).

[0038] Furthermore, the buried nature of the protective p+layer will improve the extraction of holes generated in blocking mode or during fault conditions, such as UIS. Thus, the semiconductor device allows for an improved avalanche capability. Additionally, the protective p+layer leads to a reduction of the Miller capacitance thereby allowing for an increased immunity to parasitic turn-on in switching applications. Furthermore, the regular nature of the grounding of the protective p+layer, which is performed in each unit cell, ensures that the potential throughout the entire protective p+layer will be close to that of the source of the multi-trench semiconductor device.

[0039] Regarding the protective p+layer and according to a preferred embodiment of the invention, it is preferred that the protective p+layer is continuous along the fin elongation axis. In other words, the protective p+layer preferably extends below the gaterecess continuously along the fin elongation axis and thus efficiently reduces the off-state electric fields at the bottom of the gate-recess and / or in the gate insulation.

[0040] According to another preferred embodiment of the invention the unit cell and / or the multi-trench semiconductor device comprise a gate insulation layer for electrically insulating a gate layer from the substrate, from the body layer and from the source structure, and wherein a thickness of the gate insulation layer with reference to the fin elongation axis on two opposing sidewalls of the gate-recess is higher than a thickness of the gate insulation layer along the carrier transport axis and / or wherein the thickness of the gate insulation layer with reference to the fin elongation axis on the two opposing sidewalls of the gate-recess is higher than a thickness of the gate insulation layer on a third sidewall of the gate-recess towards the first fin. This has the advantage that the charge carriers travel predominantly through the first fin region at the centre of the unit cell, since a large insulation layer thickness is used on the lateral sidewalls of the gate-recess. Regarding the gate insulation layer it is preferred that the gate insulation layer is a single layer, preferably of AI2O3, or that the gate insulation layer is a stack of several dielectric layers. According to another embodiment of the invention, a region of the unit cell and / or the multi-trench semiconductor device that is arranged with reference to the fin elongation axis in between the source-recess and the gate-recess, and with reference to the gate contact stripe axis adjacent to the first fin, the n+source region is arranged above the p-well region, and the p-well region is arranged above the p- source region. In case the unit cell comprises the protective p+layer, in this region of the unit cell, the p-source region is further arranged above the protective p+layer. In other words, the mechanism used for the reduction of the off-state electric fields at the bottom of gate-recess is preferably only used in those areas of the unit cell, where no current is intended to flow under normal operating conditions in the on- state.

[0041] In principle the unit cell can comprise one source-recess on each of the two opposing edges. According to a preferred embodiment of the invention, the unit cell however comprises on the two opposite edges each two source-recesses, wherein with reference to the gate contact stripe axis in between the two source-recesses of the same edge a second fin is formed, the second fin having the same width or a higher width along the gate contact stripe axis as the first fin. In other words, in this embodiment the source-recess is arranged only in those areas of the unit cell that are with regard to the fin elongation axis next to the gate-recess and exclude the area next to the first fin. Preferably the two source-recesses are arranged in the corner of the unit cell, such that when multiple unit cells are arranged in a two-dimensional pattern with unit cells in a first row along the gate contact stripe axis next two each other and further with unit cells a second row along the fin elongation axis next two each other for forming the multi-trench semiconductor device a source trench is formed by four source-recesses of four neighbouring unit cells.

[0042] Furthermore, due to the location of the source-recess with regard to the fin elongation axis laterally to the first fin, the conductive channel formed by the first fin and the p-source region that shields the corner of the gate-recess are partitioned into separate, distinct planes that are parallel to each other. These planes are defined by the fin elongation axis and the carrier transport axis. Therefore, the freedom of design is increased and an improved compromise between the channel density, the blocking, and the surge capability of the semiconductor device can be implemented.

[0043] In particular for unit cells comprising on the two opposite edges each two sourcerecesses having a vertical depth less than the vertical depth of the gate-recess, and further comprising the additional protective p+layer being arranged in the body layer below the gate-recess, the goal conflict between a) decreasing the electric field and b) increasing the channel density is reduced. Thus, the unit cell allows for an improved performance trade-off: Since the protective p+layer lies in a plane that is parallel to that of the channel, the blocking capability of the semiconductor device will largely be determined by the extent of the fist fin along the gate contact axis. This extent, does not scale with the cell pitch - i.e. the extent of the unit cell along the fin elongation axis - which is why the extent of the unit cell along the fin elongation axis can be increased, without degrading the blocking performance of the semiconductor device. In other words, the unit cell allows to adjust the channel density independently of the blocking performance. As a result, for a comparable breakdown voltage a larger channel width can be achieved.

[0044] In connection to the second fin being formed between the two source-recess of the same edge, and according to a preferred embodiment of the invention, a top of the second fin is formed by the p-well region, and wherein the top of the second fin is with reference to the fin elongation axis adjacent to the n+source region. In other words, in the area of the second fin, the n+source region is not covering the p-well region.

[0045] Regarding the protective p+layer and according to another preferred embodiment of the invention, it is preferred that the protective p+layer is discontinuous along the gate contact stripe axis such that a region of the body layer between the two opposing gate recesses and below the first fin is free of the protective p+type layer. The protective p+layer being discontinuous along the gate contact stripe axis together with the source-recess having a lower depth than the gate-recess allows to bias the protective p+layer to the potential of the source, without impeding the flow of the carriers in the channel, thereby providing an additional degree of freedom to the design of the unit cell. Furthermore, the p-well region, the protective p+layer and the body layer acting as drift region form together a quasi-saddle junction. This pushes the potential field lines deeper into the unit cell, thereby reducing the electric field at the corner of the gate-recess. As a result, the unit cell and / or the multi-trench semiconductor device have a higher breakdown voltage. Moreover, the smaller electric field at the interface to the gate insulation layer can alleviate short channel effects and hence provide more freedom for the design of the p-well region. In particular, the channel length can be decreased, in order to reduce the resistance of the channel.

[0046] According to another preferred embodiment of the invention, the unit cell comprises on the two opposite edges each two source-recesses, wherein with reference to the gate contact stripe axis in between the two source-recesses of the same edge the second fin is formed, the second fin having the same width or a higher width along the gate contact stripe axis as the first fin, and wherein a region within the second fin is free of the protective p+type layer. In other words, not only the region below the first fin is free of the protective p+type layer but also the region below the second fin. This preferably also means that the unit cell has a continuous region of body layer along the fin elongation axis below the first and second fin.

[0047] As already mentioned, the protective p+layer can be continuous along the fin elongation axis. In a preferred alternative embodiment of the invention, the protective p+layer is however discontinuous along the fin elongation axis such that a region of the body layer with reference to the gate contact stripe axis adjacent to the first fin and below the bottom of the gate-recess is free of the protective p+type layer. In other words, the protective p+layer is implemented in regions of the unit cell below the source recess and excluding the regions below the gate-recess. This can further improve the spreading of the current along the gate contact stripe axis. Although the electric field in the gate insulation layer may be larger than in the alternative where the protective p+layer is continuous along the fin elongation axis, the absolute value of the electric field may still be tolerable, provided that the length of the discontinuity along the fin elongation axis is sufficiently small.

[0048] Regarding the source-recess, it was already explained that a preferred embodiment of the unit cell comprises two source-recesses on the same edge. In connection to this and according to an alternative preferred embodiment the unit cell comprises on the two opposite edges each one source-recess, the source-recess being continuous in the direction of the gate contact stripe axis. In other words, the whole edge is used to form the source-recess. When multiple unit cells are arranged in a row along the fin elongation axis next two each other a continuous source trench in a stripe design is formed by two source-recesses of two neighbouring unit cells. The source-recess being continuous along the gate contact stripe axis has further the advantage that manufacturing of the unit cell is simplified and thus costs are reduced. Although the continuous source-recess may impede the spreading of the charge carriers in the direction along the fin elongation axis during the on-state and hence may increase the transistor’s specific on-state resistance Ron*, it will promote the expansion of the depletion layer during the off-state. Therefore, short channel effects can be suppressed more effectively, allowing for the extent of the first fin along the gate contact stripe axis to be increased without compromising the blocking capability. In such a case it is further preferred that the width of the unit cell along the fin elongation axis is sufficiently small for the p-source region forming the bottom of the source-recess to protect the region below the gate-recess of the unit cell.

[0049] As already mentioned, according to a preferred embodiment the vertical depth of the gate-recess is greater than the vertical depth of the source-recess. However, according to a preferred alternative embodiment of the invention, a unit cell is provided wherein the vertical depth of the source-recess is greater than the vertical depth of the gate-recess, and wherein a region of the body layer being arranged below the gate-recess, is free of a protective p+layer. In this embodiment no protective p+layer is needed for reducing the off-state electric fields at the bottom of the gate-recess. Instead, the off-state electric fields at the bottom of the gate-recess and the gate insulation layer are reduced by the source-recess being deeper than the gate-recess. As the bottom of the source-recess is formed by the p-source region, a protection of the gate-recess is achieved. In this regard it is preferred that the p- source region is sufficiently deep and that a distance between the gate insulation layer and the source-recess is sufficiently small, such that a peak of the electric field during the off-state is shifted to the pn junction at the source-recess. Preferably the source-recess is discontinuous along the gate contact strip axis - or in other words, the unit cell preferably comprises two source-recesses on the same edge. In this regard the protective p-source region is preferably formed only in regions of the unit cell where no current is intended to flow.

[0050] In connection to the unit cell where the vertical depth of the source-recess is greater than the vertical depth of the gate-recess, it is further preferred that a region below the gate-recess which extends continuously along the gate contact stripe axis is configured as n-JFET region. In other words, the n-JFET region is also arranged within the first fin. This makes it possible to contain the JFET effect in the on-state.

[0051] Independent of having a continuous or discontinuous source-recess, independent of the relative depth of the source-recess and the gate-recess and independent of the presence of the protective p+layer, it is further preferred that in a region within the first fin the p-well region is arranged below the n+source region. In other words, the n+source region preferably covers the p-well region at least in a part of the first fin. Further preferably the n+source region covers the p-well region along the whole length of the first fin in the fin elongation direction. This preferably also means that the p-well region preferably extends along the whole length of the first fin in the fin elongation direction. Further preferably the p-well region of the unit cell is continuous along the unit cell in the direction of the fin elongation axis.

[0052] Regarding unit cells having discontinuous source-recesses, independent of the relative depth of the source-recess and the gate-recess, independent of the presence of the protective p+layer, and according to another preferred embodiment of the invention, a unit cell is provided wherein the unit cell comprises at least one additional n-JFET region within the second fin, wherein the n-JFET region is arranged below the p-well region and extends vertically down at least to the bottom of the gate-recess. In other words, preferably the unit cell comprises at least one additional n-JFET region to further improve the spreading of the current in the drift region. This has also the advantage that it counterbalances the increased expansion of the depletion region due to the quasi-saddle pn junction into the first fin and helps to achieve a good trade-off between the static losses and the blocking performance of the semiconductor device.

[0053] Regarding the n-JFET region and according to a further preferred embodiment, the n-JFET region preferably extends down to the lower end of the protective p+layer, or the n-JFET region extends down below the lower end of the protective p+layer, and / or wherein the n-JFET region is arranged below the protective p+layer and extends continuously in a plane having the carrier transport axis as normal axis. The n-JFET region can extend down to the bottom of the gate-recess or the protective p+layer, or even deeper. This not only simplifies the fabrication process, it may further reduce the breakdown voltage of the drift region / protective p+layer pn junction, due to the higher doping concentration in the drift region and hence the higher electric field. Alternatively, a dedicated mask can be used to implant donors and thus the n-JFET region only in the second fin, so as to alleviate the effect on the blocking performance. In order for this approach to be effective, the n-JFET region preferably extends at least to the bottom of the gate-recess.

[0054] Regarding the protective p+layer and according to another preferred embodiment of the invention, it is further preferred that the protective p+layer extends vertically deeper into the body layer in a region farther away from the first fin, than in a region closer to the first fin. In other words, the unit cell can have multiple implantations for the protective p+layer. In particular, a deeper implant for the protective p+layer may be used on the external sides of the unit cell, in order to shift the position of the peak electric field away from the corner of the gate-recess and thus guarantee that the breakdown will occur through avalanche at the deep pn junction. This will reduce carrier injection into the gate insulation layer and thereby improve the high field reliability. Moreover, the shallower depth of the protective p+layer close to the first fin will allow for better current spreading, thereby decreasing the JFET resistance. In further embodiments the protective p+layer can be implanted completely away from the gate-recess or the protective p+layer can only be formed beneath certain segments of the gate-recess.

[0055] According to another preferred embodiment of the invention, the unit cell comprises an embedded Schottky diode or an embedded Schottky pn diode arrange in the first fin.

[0056] Preferably an anti-parallel Schottky barrier diode is integrated. In connection to this the p-well region and the n+source region are preferably discontinuous along the fin elongation axis, such that a middle region within the first fin is free of a p-well region and free of a n+source region. In other words, for implementing the anti-parallel Schottky barrier diode the p-well region and the n+source region are preferably implemented only with respect to the fin elongation axis, at the beginning and at the end of the first fin. Preferably for the anti-parallel Schottky barrier diode the middle part of the first fin is not covered with the gate insulation layer. Instead, a metal with a sufficiently high barrier for forming a Schottky junction with the n-channel region within the first fin, is deposited at the center of the first fin. Preferably Ti, Mo, Ni, Pt, and / or Au are used as metal. Preferably, a source contact is then deposited on top of the metal, biasing the Schottky diode to the source potential.

[0057] Even though the integration of the Schottky barrier diode may reduce the channel density of the semiconductor device, the extent of the unit cell along the fin elongation axis (i.e. the cell pitch) can be increased, without aggravating the blocking performance and / or the JFET resistance of the semiconductor device. At the same time, the strong JFET effect due to the quasi-saddle junction formed by the protective p+layer, the p-well region and the body layer being n-type can be used to block conduction through the Schottky barrier diode during the off-state. Thus, the Schottky barrier diode can be included in the unit cell while still maintaining adequate performance of the semiconductor device. The integration of this Schottky barrier diode can reduce the power losses incurred by the MOSFET’s body diode. Moreover, the unipolar character of the Schottky barrier diode may prevent the nucleation and expansion of stacking faults in (or into) the body layer for modest surge current conditions, at which the MOSFET’s body diode is still inactive.

[0058] According to a preferred alternative embodiment an embedded Schottky pn diode is arrange in the fin. Regarding this a p-barrier is preferably positioned between the n-channel region and the source contact within the fin. The p-barrier is preferably designed such that it is fully depleted during both the on- and off-state. This can be achieved by a sufficiently thin barrier having only a low doping concentration. In particular, the turn-on voltage of the diode can be adjusted through the doping concentration and thickness of the p-barrier. This additional capability makes it possible to attain a sufficiently high threshold voltage, without having to use a metal with a specific work function for the Schottky contact. It is instead possible to use the same Ti / AI / Pt stack used for the ohmic source contact of the semiconductor device. Moreover, the source contact used for the ohmic contact with the p-barrier can be deposited directly on top of the Schottky pn diode, thereby reducing the complexity and cost for manufacturing. Thus, this allows for a greater freedom with regards to the design of the fin and, specifically, the spatial window allocated to the Schottky pn diode.

[0059] Further preferably it is possible to use multiple implants in the p-barrier for the Schottky pn diode, such as a combination of a p-region, p region, and p-region as p-barrier. Further preferably the Schottky pn diode can be combined with a Schottky barrier diode to form a quasi-JBS structure (JBS: junction barrier Schottky) to produce a trade-off between a low threshold forward voltage drop and a reduced leakage current. In this case a combination of an n-region, a p region, and an n-region across the first fin along the gate contact stripe axis can be used.

[0060] These and other aspects of the invention will be apparent from and elucidated with reference to the embodiments described hereinafter.

[0061] In the drawings:

[0062] Fig. 1 schematically shows an axonometric view of an upper part of a unit cell according to a preferred embodiment of the invention,

[0063] Fig. 2 schematically shows a cross section across line A-A of figure 1 b),

[0064] Fig. 3 schematically shows a TCAD model of unit cell according to a preferred embodiment,

[0065] Fig. 4 schematically shows on the left the upper part of the TCAD model of figure 3 and on the right a cross section of the TCAD model of figure 3,

[0066] Fig. 5 schematically shows a current density in the TCAD model of figure

[0067] 4, Fig. 6 schematically shows a current path in a cross-section of a centre of a first fin of the TCAD model of figure 4,

[0068] Fig. 7 schematically shows a current path in a further cross-section of a centre of the first fin of the TCAD model of figure 4,

[0069] Fig. 8, 9, 10 schematically show output characteristics, and capacitance characteristics of a TCAD model according to a preferred embodiment compared to a TCAD model according to prior art,

[0070] Fig. 11 schematically shows blocking characteristics of a TCAD model according to a preferred embodiment compared to a TCAD model according to prior art,

[0071] Fig. 12 schematically shows the electric field profile of a TCAD model according to a preferred embodiment compared to a TCAD model according to prior art,

[0072] Fig. 13 schematically shows the electric field profile in a gate insulating layer of the TCAD models of figure 12 at two different cross sections,

[0073] Fig. 14 schematically shows two axonometric view and a cross section of an upper part of a unit cell according to a further preferred embodiment of the invention,

[0074] Fig. 15 schematically shows five axonometric views of an upper part of a unit cells according to five further preferred embodiments of the invention,

[0075] Fig. 16 schematically shows three axonometric views of an upper part of a unit cells according to three further preferred embodiments of the invention, Fig. 17 schematically shows two axonometric views of an upper part of a unit cells according to two further preferred embodiments of the invention,

[0076] Fig. 18 schematically shows two axonometric view and a cross section of an upper part of a unit cell according to a further preferred embodiment of the invention,

[0077] Fig. 19 schematically shows an axonometric view and a cross section of an upper part of a unit cell according to a further preferred embodiment of the invention,

[0078] Fig. 20 schematically shows a axonometric view of an upper part of a unit cell according to a further preferred embodiment of the invention,

[0079] Fig. 21 schematically shows three cross sections of an upper part of a unit cell according to three further preferred embodiment of the invention, and

[0080] Fig. 22 schematically shows on the left the upper part of a TCAD model of a reference unit cell according to prior art and on the right a cross section of the TCAD model.

[0081] Description of embodiments

[0082] Figure 1 schematically shows an axonometric view of an upper part of a unit cell 10 according to a preferred embodiment of the invention. In figure 1 a) the unit cell 10 is shown without a gate insulation layer 12, while figure 1 b) also shows the gate insulation layer 12. Figure 2 schematically shows a cross section across line A-A of figure 1 b).

[0083] In this embodiment the unit cell 10 is configured as vertical field effect transistor cell having a carrier transport axis 14 defined between drain and source. As figure 1 only shows the upper part of the unit cell, the drain region, being formed by a substrate of a first conductivity type is not visible in figure 1 . The unit cell 10 further comprises a body layer 16 of a second conductivity type formed along the carrier transport axis 14 on top of the substrate and acting as drift region. In this embodiment the drift region is of n-type. The unit cell 10 further comprises a source structure provided on the body layer 14, the source structure comprising a p-well region 18 and a n+source region 20, the n+source region 20 at least partially covering the p-well region 18. The source structure further comprises a p-source region 22 being below the p-well region.

[0084] As is shown in figure 1 , in a direction of a gate contact stripe axis 24 being perpendicular to the carrier transport axis 14, the unit cell 10 comprises on two opposite edges each a gate-recess 26 extending vertically through the n+source region 20 and the p-well region 18 into the body layer 16. The two gate-recesses 26 form in between each other a fin 28, the fin 28 extending along a fin elongation axis 30 being perpendicular to the carrier transport axis 14 and being perpendicular to the gate contact stripe axis 24.

[0085] As can be seen in figure 1 , the two opposing edges of the unit cell 10, not comprising the gate-recess 26 comprise instead a source-recess 32. In other words along the fin elongation axis 30 the unit cell 10 comprises on two opposite edges each at least one source-recess 32 - in this embodiment two source recesses 32 - extending vertically through the n+source region 20. The vertical depth of the source-recess 32 is different to the vertical depth of the gate-recess 26. In this embodiment the gate-recess 26 is deeper than the source-recess 32. The bottom of the source-recess 32 is formed by the p-source region 22 of the source structure.

[0086] As can further be seen in figures 1 and 2 is that with reference to the gate contact stripe axis 24 in between the two source-recesses 32 of the same edge of the unit cell 10 a second fin 34 is formed, the second fin 34 having the same width or a higher width along the gate contact stripe axis 24 as the first fin 28 is formed.

[0087] Additionally in this embodiment the gate-recess 26 extends vertically through the n+source region 20 and the p-well region 18 into the body layer 16 deeper than the source-recess 32. The unit cell 10 comprises in addition a protective p+layer 36, the protective p+layer 36 being arranged in the body layer 16 below the gate-recess 26. The protective p+layer 36 is connected to the p-well region 18 of the source structure via the p-source region 22 at the bottom of the source-recess 32. As the gate-recess 26 extends vertically through the p-well region 18 into the body layer 16, the fin 28 comprises a channel region 38 in between the p-well region 18 and the protective p+layer 36.

[0088] In figures 1 and 2 it is also shown that in this embodiment the second fin 34 is free of the protective p+type layer. Additionally, the protective p+layer 36 is discontinuous along in the gate contact stripe axis 24 but continuous along the fin elongation axis 30, such that the bottom of the gate-recess 26 is formed by the protective p+layer 32.

[0089] Not shown in figures 1 and 2 is an electrically conductive gate layer as well as the source and gate contacts.

[0090] Figures 3 and 4 schematically show a TCAD model (technology computer aided design model) of the unit cell 10 according to the first embodiment shown in figures 1 and 2. Figure 3 shows an axonometric view including the drain region, being formed by a substrate 39 of a first conductivity type - in this embodiment n+type - while figure 4 shows an axonometric view of the upper part of the unit cell 10 as well as a cross section through the centre of the fin 28 in a plane defined by the carrier transport axis 14 and the gate contact stripe axis 24.

[0091] In figures 3 and 4 it can be seen, that the TCAD model specifies that an extent 40 of the body layer 16 and the source structure along the carrier transport axis 14 is 10 pm, while the width 42 of the unit cell 10 along the fin elongation axis 30 - i.e. the cell pitch 42 - is 2 pm. The width 44 of unit cell 10 along the gate contact stripe axis 24 is 3 pm. Furthermore, an extent 46 of the source-recess 32 along the fin elongation axis 30 is 0.2 pm, and an extent 48 of the n+source region 22 along the fin elongation axis 30, in a region lateral to the first fin 28 is 0.35 pm. Additionally, an extent 50 of the gate insulating layer 12 along the fin elongation axis 30 covering a sidewall of the gate-recess 26 is 0.2 pm, while an extent 52 of the gate insulating layer 12 along the fin elongation axis 30 being on top of the first fin 28 is 0.5 pm. The extent 54 of the first fin 28 along the gate contact stripe axis 24 which corresponds to the distance 54 between the two gate-recesses 26 is specified by the model to be 1.5 pm. The model uses a n-JFET enhancement layer with a constant total doping of 5x1016cm-3down to the bottom of protective p+layer 36.

[0092] Figure 5 schematically shows the TCAD model view of the profile of the current density for the TCAD model of figures 3 and 4, on the left in an axonometric view including the gate insulation layer 12, on the right in an axonometric view without the gate insulation layer 12.

[0093] Figure 6 schematically shows the current path across the cross-section of the centre of the first fin 28 in a plane defined by the carrier transport axis 14 and the gate contact stripe axis 24. Figure 7 schematically shows the current path across the cross-section of the centre of the first fin 28 in a plane defined by the carrier transport axis 14 and the fin elongation axis 30.

[0094] As comparison Figure 22 schematically shows a reference TCAD model of a unit cell 10’ according to prior art. The reference TCAD model has identical dimensions as the TCAD model according to figures 3 to 7, except that the reference TCAD model does not include the source-recess such that the protective p+layer 36’ underneath the gate-recess is left floating. Furthermore, the protective p+layer 36’ of the reference model is discontinuous along the gate contact stripe axis 24 and discontinuous along the fin elongation axis 30. The protective p+layer 36’ has an extent along the fin elongation axis 30 of 0.9 pm.

[0095] The diagrams in figure 8 schematically show in a) the output characteristics and in b) the capacitance characteristics of the unit cell 10 of figures 3 to 5 with line 55 in comparison to the reference model shown in figure 22 with line 55’. The cell pitch 42 is 2 pm, and the extent 52 of the gate insulation layer 12 along the fin elongation axis 30 on top of the first fin 28 is 0.5 pm. The x-axis in figure 8a) and 8b) specifies the drain voltage in V, the y-axis in figure 8a) specifies the current density in A / cm2, and the y-axis in figure 8b) specifies the capacitance in nF / cm2For the output char- acteristics the gate-to-source voltage was 15 V, while the capacitance was determined with a gate-to-source voltage of 0 V. Figure 8b) shows that the miller capacitance C rss is reduced.

[0096] The diagrams in figure 9 schematically show in a) the output characteristics and in b) the capacitance characteristics of the unit cell 10 of figures 3 to 5 - with a cell pitch 42 of 2.7 pm - with line 55 in comparison to the reference model - also with a cell pitch 42 of 2.7 pm - shown in figure 22 with line 55’. The extent 52 of the gate insulation layer 12 along the fin elongation axis 30 on top of the first fin 28 is the same as for the diagrams in figure 8 (i.e. 0.5 pm), thus the larger cell pitch 42 is achieved only through increasing the lateral width along the fin elongation axis 30 of the source region. The x-axis in figure 9a) and 9b) specifies the drain voltage in V, the y-axis in figure 9a) specifies the current density in A / cm2, and the y-axis in figure 9b) specifies the capacitance in nF / cm2. For the output characteristics the gate-to-source voltage was 15 V, while the capacitance was determined with a gate- to-source voltage of 0 V.

[0097] The diagrams in figure 10 schematically show in a) the output characteristics and in b) the capacitance characteristics of the unit cell 10 of figures 3 to 5 - with a cell pitch 42 of 2.7 pm and an extent 52 of the gate insulation layer 12 along the fin elongation axis 30 on top of the first fin 28 of 1 .2 pm- with line 55 in comparison to the reference model - also with a cell pitch 42 of 2.7 pm and an extent 52 of the gate insulation layer 12 along the fin elongation axis 30 on top of the first fin 28 of 1 .2 pm - shown in figure 22 with line 55’. The x-axis in figure 9a) and 9b) specifies the drain voltage in V, the y-axis in figure 9a) specifies the current density in A / cm2, and the y-axis in figure 9b) specifies the capacitance in nF / cm2. For the output characteristics the gate-to-source voltage was 15 V, while the capacitance was determined with a gate-to-source voltage of 0 V.

[0098] The diagrams in figure 11 schematically show the blocking characteristics of the unit cell 10 compared to the reference for cell pitches 42 of 2 pm and 2.7 pm, where the larger cell pitch 42 is achieved using an extent 52 of the gate insulation layer 12 along the fin elongation axis 30 on top of the first fin 28 of 0.5 pm (a) and 1.2 pm (b). The blocking voltage of the unit cell 10 according to the preferred embodiment is stable to changes of the extent 52. The x-axis in figures 11 a) and 11 b) specifies the drain voltage in V, the y-axis in figures 11 a) and 11 b specifies the current density in A / cm2.

[0099] Figure 12 schematically shows in a) the electric field profile of the reference unit cell, and in 12b) the electric field profile of the unit cell 10 according to the preferred embodiment along the centre of the first fin 28 in a plane defined by the carrier transport axis 14 and the gate contact stripe axis 24 for a cell pitch 42 of 2.7 pm. The gate-to-source voltage was 0 V.

[0100] Figure 13 schematically shows the electrical field profile in the gate insulation layer 12 along the cutlines A (a) and B (b) shown in figure 12a). The improved protection by the protective p+layer 36 in the unit cell 10 according to the preferred embodiment and shown by line 55, reduces the electric field in the gate insulation layer 12 compared to the prior art design indicated by line 55’. The x-axis in figures 13a) and 13b) specifies the depth in pm, the y-axis in figures 13a) and 13b) specifies the electric field in V / cm.

[0101] Figure 14 schematically shows an axonometric view of an upper part of a unit cell 10 according to another preferred embodiment of the invention. On the left of figure 14, the unit cell 10 is shown in an axonometric view including the gate insulation layer 12, on the right in an axonometric view without the gate insulation layer 12, and in the middle in a cross-section along the centre of the first fin 28 in a plane defined by the carrier transport axis 14 and the gate contact stripe axis 24. Compared to the embodiment shown in figures 1 to 3, in the embodiment of figure 14, the source-recess 32 is continuous along the gate contact stripe axis.

[0102] Figure 15 schematically shows five axonometric views of five unit cells 10 according to further preferred embodiments of the invention, where a n-JFET region 56 is used to further improve the spreading of the current in the drift region 16. In the embodiments shown in figure 15a) one n-type JFET region 56 does not reach down into the body layer 16 as deep as the lower end of the protective p+layer 36. In the embodiments shown in figure 15b) one n-type JFET region 56 reaching down into the body layer 16 until the lower end of the protective p+layer 36. In the embodiments shown in figure 15c) one n-type JFET region 56 reaching down into the body layer 16 deeper than the lower end of the protective p+layer 36, and forms a continuous layer below the protective p+layer 36. In the embodiments shown in figure 15d) the n-type JFET region 56 reaching down into the body layer 16 deeper than the lower end of the protective p+layer 36, however, it does not form a continuous layer below the protective p+layer 36, but is confined to regions below the second fin 34. In the embodiments shown in figure 15e) several n-type JFET region 56 - in particular three regions - are used.

[0103] Figure 16 schematically shows three axonometric views of three unit cells 10 according to further preferred embodiments of the invention, where multiple implants for the protective p+layer 36 or multiple positions of the protective p+layer 36 only beneath a certain partial portion of the gate-recess 26 are used. The protective p+layer 36 extends vertically deeper into the body layer 16 in a region farther away from the first fin 28, than in a region closer to the first fin 28.

[0104] Figure 17 schematically shows two axonometric views of two unit cells 10 according to further preferred embodiments of the invention, in which the protective p+layer 36 is discontinuous along the gate contact stripe axis 24 and along the fin elongation axis 30 and extends only up to the edge of the gate insulation layer 12 (left in figure 17) or between the source-recess 32 and the gate-recess 26.

[0105] Figure 18 schematically shows an axonometric view of an upper part of a unit cell 10 according to another preferred embodiment of the invention. On the left of figure 18, the unit cell 10 is shown in an axonometric view including the gate insulation layer 12, on the right in an axonometric view without the gate insulation layer 12, and in the middle in a cross-section along the centre of the first fin 28 in a plane defined by the carrier transport axis 14 and the gate contact stripe axis 24. Compared to the embodiment shown in figures 1 to 3, in the embodiment of figure 18, the source-recess 32 is deeper than the gate-recess 26. Furthermore, the unit cell does not comprise a protective p+layer 36. The source-recess 32 is made discontinuous along the gate contac stripe axis 24 in order to contain the JFET effect in the on-state. Figure 19 schematically shows an upper part of a unit cell 10 according to another preferred embodiment of the invention. On the left of figure 19, the unit cell 10 is shown in an axonometric view without the gate insulation layer 12, on the right in a cross-section along the centre of the first fin 28 in a plane defined by the carrier transport axis 14 and the gate contact stripe axis 24. In this embodiment the unit cell 10 comprises an embedded Schottky barrier diode 58 positioned at the centre of the first fin 28. In this embodiment the built-in Schottky barrier diode 58 is implemented by restricting the implantation of the p-well region 18 and n+source region 20 only to the lateral ends of the first fin 28. A metal with a sufficiently large work function is then deposited on top of the central region of the first fin 28 and biased at the source’s potential, thereby producing the Schottky contact.

[0106] Figure 20 schematically shows an upper part of a unit cell 10 according to another preferred embodiment of the invention, where a Schottky pn diode 60 is positioned at the centre of the first fin 28. Figure 21 shows on the left a cross-section along the centre of the first fin 28 in a plane defined by the carrier transport axis 14 and the gate contact stripe axis 24 of the embodiment of figure 20. As can be see the Schottky pn diode 60 is created by implementing a p region 62 between the source contact (not shown on the figure) and the n-channel region 38.

[0107] Figure 21 further shows in the middle a cross-section along the centre of the first fin 28 in a plane defined by the carrier transport axis 14 and the gate contact stripe axis 24 of a further embodiments of unit cells 10 with an integrated Schottky pn diodes 60, where the pn-junction is generated by multiple implants of p-regions 64 and p regions 62.

[0108] Figure 21 further shows on the right a cross-section along the centre of the first fin 28 in a plane defined by the carrier transport axis 14 and the gate contact stripe axis 24 of a further embodiments of unit cells 10 where the Schottky barrier diode 58 and the Schottky pn diodes 60 are combined to form a quasi-JBS structure by multiple implants of n-regions 66 and p regions 62.

[0109] While the invention has been illustrated and described in detail in the drawings and foregoing description, such illustration and description are to be considered illustrative or exemplary and not restrictive; the invention is not limited to the disclosed embodiments. Other variations to the disclosed embodiments can be understood and effected by those skilled in the art in practicing the claimed invention, from a study of the drawings, the disclosed, and the appended claims. In the claims, the word “comprising” does not exclude other elements or steps, and the indefinite article “a” or “an” does not exclude a plurality. The mere fact that certain measures are recited in mutually different dependent claims does not indicate that a combination of these measures cannot be used to advantage. Any reference signs in the claims should not be construed as limiting scope.

[0110] Reference signs list

[0111] 10 unit cell

[0112] 12 gate insulation layer

[0113] 14 carrier transport axis

[0114] 16 body layer, drift region

[0115] 18 p-wel I region

[0116] 20 n+source region

[0117] 22 p-source region

[0118] 24 gate contact stripe axis

[0119] 26 gate-recess

[0120] 28 first fin

[0121] 30 fin elongation axis

[0122] 32 source-recess

[0123] 34 second fin

[0124] 36 protective p+layer

[0125] 38 channel region

[0126] 39 substrate, drain region

[0127] 40 extent of body layer and the source structure in direction of carrier transport axis

[0128] 42 cell pitch

[0129] 44 width of unit cell in direction of gate contact stripe axis

[0130] 46 extent of source-recess along fin elongation axis

[0131] 48 extent of n+source region lateral of fin along fin elongation axis

[0132] 50 extent of gate insulation layer along fin elongation axis covering sidewall of gate-recess

[0133] 52 extent of gate insulation layer along fin elongation axis on top of first fin

[0134] 54 distance between gate-recesses

[0135] 55 line for unit cell according to preferred embodiment

[0136] 55’ line for prior art unit cell

[0137] 56 n-type JFET region

[0138] 58 Schottky barrier diode

[0139] 60 Schottky pn diode

[0140] 62 p region 64 p-region

[0141] 66 n-region

Claims

Claims1. A unit cell (10) of a multi-trench semiconductor device, wherein the unit cell (10) is configured as vertical field effect transistor cell having a carrier transport axis (14) defined between drain and source, wherein the unit cell (10) comprises:- a substrate (39) of a first conductive type acting as drain region,- a body layer (16) of a second conductivity type formed along the carrier transport axis (14) on top of the substrate (39) and acting as drift region, and- a source structure provided on the body layer (16), the source structure comprising a p-well region (18), a n+source region (20), and a p-source region (22), the n+source region (20) at least partially covering the p-well region (18), and the p-source region (22) being below the p-well region (18), wherein in a direction of a gate contact stripe axis (24) being perpendicular to the carrier transport axis (14), the unit cell (10) comprises on two opposite edges each a gate-recess (26) extending vertically through the n+source region (20) and the p-well region (18), such that when multiple unit cells (10) are arranged in a row along the gate contact stripe axis (24) next two each other for forming the multitrench semiconductor device a gate trench is formed by two gate-recesses (26) of two neighbouring unit cells (10), wherein in the unit cell (10) in between the two gate-recesses (26) a first fin (28) is formed, the first fin (28) extending along a fin elongation axis (30) being perpendicular to the carrier transport axis (14) and being perpendicular to the gate contact stripe axis (24), wherein along the fin elongation axis (30) the unit cell (10) comprises on two opposite edges each at least one source-recess (32) extending vertically through the n+source region (20), wherein the vertical depth of the source-recess (32) is different to the vertical depth of the gate-recess (26), and wherein a bottom of the source-recess (32) is formed by the p-source region (22) of the source structure.

2. Unit cell (10) according to claim 1 , wherein the gate-recess (26) extends vertically through the n+source region (20) and the p-well region (18) into the body layer (16), wherein the vertical depth of the source-recess (32) is less than the vertical depth of the gate-recess (26), wherein the unit cell (10) comprises in addition a protective p+layer (36), the protective p+layer (36) being arranged in the body layer (16) below the gate-recess (26), and wherein the protective p+layer (36) is connected to the p-well region (18) of the source structure via the p-source region (22) at the bottom of the source-recess (32).

3. Unit cell (10) according to claim 1 or 2, comprising a gate insulation layer (12) for electrically insulating a gate layer from the substrate (39), from the body layer (16) and from the source structure, wherein a thickness (50) of the gate insulation layer (12) with reference to the fin elongation axis (30) on two opposing sidewalls of the gate-recess (26) is higher than a thickness of the gate insulation layer (12) in the direction of the carrier transport axis (14) and / or wherein the thickness (50) of the gate insulation layer (12) with reference to the fin elongation axis (30) on the two opposing sidewalls of the gate-recess (26) is higher than a thickness of the gate insulation layer (12) on a third sidewall of the gaterecess (26) towards the first fin (28).

4. Unit cell (10) according to any of the previous claims, wherein in a region of the unit cell (10) that is arranged with reference to the fin elongation axis (30) in between the source-recess (32) and the gate-recess (26), and with reference to the gate contact stripe axis (24) adjacent to the first fin (28), the n+source region (20) is arranged above the p-well region (18), and the p-well region (18) is arranged above the p-source region (22).

5. Unit cell (10) according to any of the previous claims, wherein the unit cell (10) comprises on the two opposite edges each two source-recesses (32), wherein with reference to the gate contact stripe axis (24) in between the two sourcerecesses (32) of the same edge a second fin (34) is formed, the second fin (34) having the same width or a higher width along the gate contact stripe axis (24) as the first fin (28).

6. Unit cell (10) according to claim 5, wherein a top of the second fin (34) is formed by the p-well region (18), and wherein the top of the second fin (34) is with reference to the fin elongation axis (30) adjacent to the n+source region (20).

7. Unit cell (10) according to any of claims 2 to 6, wherein the protective p+layer (36) is discontinuous along of the gate contact stripe axis (24) such that a region of the body layer (16) between the two opposing gate recesses (26) and below the first fin (28) is free of the protective p+type layer (36).

8. Unit cell (10) according to claim 7, wherein the unit cell (10) comprises on two opposite edges each two source-recesses (32), wherein with reference to the gate contact stripe axis (24) in between the two source-recesses (32) of the same edge a second fin (34) is formed, the second fin (34) having the same width or a higher width along the gate contact stripe axis (24) as the first fin (28), and wherein a region within the second fin (34) is free of the protective p+type layer (36).

9. Unit cell (10) according to any of claims 2 to 8, wherein the protective p+layer (36) is discontinuous along of the fin elongation axis (30) such that a region of the body layer (16) with reference to the gate contact stripe axis (24) adjacent to the first fin (28) and below the bottom of the gate-recess (26) is free of the protective p+type layer (36).

10. Unit cell (10) according to any of claims 1 to 4, or 7 to 9, wherein the unit cell (10) comprises on the two opposite edges each one source-recess (32), the source-recess (32) being continuous along the gate contact stripe axis (24).11 . Unit cell (10) according to claim 1 , 3 to 6, or 10, wherein the vertical depth of the source-recess (32) is greater than the vertical depth of the gate-recess (26), and wherein a region of the body layer (16) being arranged below the gate-recess (26), is free of a protective p+layer (36).

12. Unit cell (10) according to any of claims 1 , 3 to 6, 10, or 11 , wherein a region below the gate-recess (26) and extending continuously along the gate contact stripe axis (24) is configured as n-JFET region (56).

13. Unit cell (10) according to any of the previous claims, wherein in a region within the first fin (28) the p-well region (18) is arranged below the n+source region (20).

14. Unit cell (10) according to any of claims 5 to 9, or 11 to 13, wherein the unit cell (10) comprises at least one additional n-JFET region (56) within the second fin (34), wherein the n-JFET region (56) is arranged below the p-well region (18) and extends vertically down at least to the bottom of the gate-recess (26).

15. Unit cell (10) according to claim 14, wherein the n-JFET region (56) extends down to the lower end of the protective p+layer (36), or wherein the n-JFET region (56) extends down below the lower end of the protective p+layer (36), and / or wherein the n-JFET region (56) is arranged below the protective p+layer (36) and extends continuously in a plane having the carrier transport axis (14) as normal axis.

16. Unit cell (10) according to any of claims 2 to 10, or 13 to 15, wherein the protective p+layer (36) extends vertically deeper into the body layer in a region farther away from the first fin (28), than in a region closer to the first fin (28).

17. Unit cell (10) according to any of the claims 1 to 12, or 14 to 16, wherein the unit cell (10) comprises an embedded Schottky barrier diode (58) or an embedded Schottky pn diode (60) arrange in the first fin (28).

18. Unit cell (10) according to any of the preceding claims, wherein the unit cell (10) is of a semiconductor material having a bandgap equal to or greater than the bandgap of silicon.

19. Unit cell (10) according to any of the preceding claims, wherein the unit cell (10) is of a semiconductor material selected from the group consisting of Si, SiC, GaN, Ga20s, AIN, AlxGai-xN, GaAs, and diamond.

20. Multi-trench semiconductor device, comprising multiple unit cells (10) accordingto any of the previous claims, wherein the unit cells (10) are arranged in a row along the gate contact stripe axis (24) next two each other such that a gate trench is formed by two gate-recesses (26) of two neighbouring unit cells (10).21 . Method for manufacturing a multi-trench semiconductor device, the multi-trench semiconductor device comprising several unit cells (10), wherein the unit cell (10) is configured as vertical field effect transistor cell having a carrier transport axis (14) defined between drain and source, comprising the steps of- providing a substrate (39) of a first conductive type acting as drain region,- forming a body layer (16) of a second conductivity type acting as drift region along the carrier transport axis (14) on top of the substrate (39),- providing a source structure comprising a p-well region (18) and a n+source region (20) on the body layer (16), the n+source region (20) at least partially covering the p-well region (18),- etching multiple gate trenches extending vertically through the n+source region (20) and the p-well region (18), such that a gate recess (26) is formed in a direction of a gate contact stripe axis (24) being perpendicular to the carrier transport axis (14) on two opposite edges of the unit cell (10), wherein in the unit cell (10) in between the two gate-recesses (26) a first fin (28) is formed, the first fin (28) extending along a fin elongation axis (30) being perpendicular to the carrier transport axis (14) and being perpendicular to the gate contact stripe axis (24),- etching multiple source trenches extending vertically through the n+source region (20), such that at least one source-recess (32) is formed along the fin elongation axis (30) on two opposite edges of the unit cell (10), wherein the vertical depth of the source-recess (32) is different to the vertical depth of the gaterecess (26), and- forming a p-source region (22) of the source structure at a bottom of the source-recess (32) below the p-well region (18).

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