Semiconductor device, power conversion device, and manufacturing method for semiconductor device

Abstract

This semiconductor device is provided with: a n-type semiconductor layer (1) that includes a n-type oxide semiconductor; a first surface electrode (21) disposed on the first main surface of the n-type semiconductor layer (1); and a p-type semiconductor layer (3) disposed on the first main surface of the n-type semiconductor layer (1) at the perimeter of the first surface electrode (21). The inner circumferential edge of the p-type semiconductor layer (3) extends over the first surface electrode (21).

Description

Semiconductor device, power conversion device, and method of manufacturing the semiconductor device

[0001] The present disclosure relates to a semiconductor device, and more particularly to a semiconductor device made of an oxide semiconductor.

[0002] In semiconductor devices such as vertical MOSFETs (Metal Oxide Semiconductor Field Effect Transistors) and vertical SBDs (Schottky Barrier Diodes), a technique is widely known in which an electric field relaxation layer, which is a p-type semiconductor layer, is disposed around an electrode (hereinafter referred to as a "surface electrode") provided on the surface of an n-type semiconductor layer to prevent electric field concentration near the edge of the surface electrode. This technique is also applied to semiconductor devices made of oxide semiconductors. For example, Patent Document 1 discloses a semiconductor device in which a p-type oxide semiconductor layer is provided around a Schottky electrode on an n-type oxide semiconductor layer, thereby relaxing electric field concentration near the edge of the surface electrode.

[0003] Japanese Patent Application Laid-Open No. 2017-112126

[0004] In the semiconductor device of Patent Document 1, the outer peripheral edge of the front electrode is disposed on the p-type oxide semiconductor layer. In other words, in the manufacturing of the semiconductor device of Patent Document 1, the front electrode is formed after the p-type oxide semiconductor layer is formed. Therefore, heat generated during the contact formation between the front electrode and the n-type oxide semiconductor layer is applied to the p-type oxide semiconductor layer, which may change the conductivity or film composition of the p-type oxide semiconductor layer and impair the electric field relaxation function. Furthermore, depending on the finish of the side surface shape of the p-type oxide semiconductor layer, the front electrode may not cover the p-type oxide semiconductor layer sufficiently, which may result in electric field concentration.

[0005] The present disclosure has been made to solve the above-mentioned problems, and aims to suppress electric field concentration in a p-type oxide semiconductor layer in a semiconductor device in which a p-type oxide semiconductor layer is arranged around a surface electrode.

[0006] The semiconductor device according to the present disclosure comprises a first semiconductor layer made of an oxide semiconductor of a first conductivity type, a first surface electrode provided on a first major surface of the first semiconductor layer, and a second semiconductor layer of a second conductivity type provided on the first major surface around the first surface electrode, wherein an inner peripheral edge of the second semiconductor layer rides on the first surface electrode.

[0007] According to the present disclosure, it is possible to suppress electric field concentration in the p-type oxide semiconductor layer disposed around the surface electrode.

[0008] The objects, features, aspects, and advantages of the present disclosure will become more apparent from the following detailed description and the accompanying drawings.

[0009] FIG. 1 is a diagram showing the configuration of a semiconductor device according to a first embodiment. FIG. 2 is a diagram showing the configuration of a semiconductor device according to a second embodiment. FIG. 3 is a diagram for explaining a method of forming a trench in the second embodiment. FIG. 4 is a diagram showing the configuration of a semiconductor device according to a third embodiment. FIG. 5 is a diagram showing the configuration of a semiconductor device according to a fourth embodiment. FIG. 6 is a diagram showing the configuration of a semiconductor device according to the fourth embodiment. FIG. 7 is a diagram showing the configuration of a semiconductor device according to the fifth embodiment. FIG. 8 is a diagram showing the configuration of a semiconductor device according to the fifth embodiment. FIG. 9 is a diagram showing the configuration of a semiconductor device according to a sixth embodiment. FIG. 10 is a diagram showing the configuration of a power conversion system to which a power conversion device according to a seventh embodiment is applied.

[0010] In the following description, n-type and p-type refer to the conductivity types of semiconductors. In this disclosure, the first conductivity type is referred to as n-type and the second conductivity type as p-type, but the first conductivity type may also be referred to as p-type and the second conductivity type as n-type. The impurity concentration of each region is defined by its peak concentration. That is, a region with a high (or low) impurity concentration refers to a region with a high (or low) peak impurity concentration.

[0011] The drawings are schematic illustrations, and the relative sizes and positions of images shown in different drawings are not necessarily accurately depicted and may be changed as appropriate. In the following description, similar components are denoted by the same reference numerals, and their names and functions are also the same. Therefore, detailed descriptions thereof may be omitted.

[0012] In the following description, terms that indicate specific positions and directions, such as "top," "bottom," "side," "front," and "back," may be used. However, these terms are used for convenience to facilitate understanding of the contents of the embodiments, and do not relate to the directions in which the embodiments are actually implemented.

[0013] Hereinafter, "outside" refers to the direction toward the outer periphery of the semiconductor substrate, and "inside" refers to the opposite direction to "outside." Here, the semiconductor substrate may be a plate-shaped substrate cut from a block, ingot, or the like, or a layer formed by peeling off a semiconductor layer formed on a specific substrate. Furthermore, the semiconductor substrate may include a drift layer formed by epitaxial growth or the like and having a lower impurity concentration than the semiconductor substrate, or other semiconductor layers that constitute semiconductor devices such as diodes and transistors.

[0014] 1 is a diagram showing the configuration of a Schottky barrier diode (SBD) that is a semiconductor device according to embodiment 1. The semiconductor device shown in Fig. 1 is a vertical SBD in which a main current flows in the thickness direction of an n-type semiconductor layer 1 that is a semiconductor substrate.

[0015] As shown in FIG. 1 , the semiconductor device according to the first embodiment includes an n-type semiconductor layer 1 as a first semiconductor layer of a first conductivity type, a first surface electrode 21 provided on an upper surface (front surface) that is a first main surface of the n-type semiconductor layer 1, a p-type semiconductor layer 3 as a second semiconductor layer of a second conductivity type provided outside the first surface electrode 21, and a back surface electrode 4 provided on a lower surface (back surface) that is a second main surface of the n-type semiconductor layer 1.

[0016] The n-type semiconductor layer 1 is a semiconductor substrate made of an oxide semiconductor containing n-type impurities. In this embodiment, the material of the n-type semiconductor layer 1 is gallium oxide (Ga ２ O ３ ) semiconductors are used.

[0017] The first surface electrode 21 is a Schottky electrode that forms a Schottky junction with the upper surface of the n-type semiconductor layer 1. The material of the first surface electrode 21 is a metal that forms a Schottky junction with the n-type semiconductor layer 1, such as Pt or Ni.

[0018] The p-type semiconductor layer 3 is made of a semiconductor layer containing p-type impurities. For example, the p-type semiconductor layer 3 is made of NiO, Cu, ２ The p-type semiconductor layer 3 is a hetero semiconductor layer made of an oxide semiconductor such as O or ZnO that is different from the n-type semiconductor layer 1 (gallium oxide), and can be formed by, for example, a sputtering method. N, Na, Li, or the like can be used as a dopant for the p-type semiconductor layer 3. Generally, it is difficult to form a p-type gallium oxide semiconductor, but if a p-type gallium oxide semiconductor can be formed, a p-type gallium oxide semiconductor layer may be used as the p-type semiconductor layer 3.

[0019] The back electrode 4 is an ohmic electrode that forms an ohmic junction with the lower surface of the n-type semiconductor layer 1. The material of the back electrode 4 is, for example, a metal such as Ti, Ni, Al, Cu, Au, or Ag, or a laminate film made of two or more of these metals.

[0020] In this embodiment, the p-type semiconductor layer 3 is disposed on the n-type semiconductor layer 1 around the first surface electrode 21 and functions as an electric field relaxation layer that relaxes electric field concentration near the end of the first surface electrode 21. Furthermore, the inner peripheral edge of the p-type semiconductor layer 3 extends over the first surface electrode 21. Therefore, in manufacturing a semiconductor device, the process of forming the p-type semiconductor layer 3 may be performed after the process of forming the first surface electrode 21 on the n-type semiconductor layer 1. Therefore, heat treatment for forming a contact between the first surface electrode 21 and the n-type semiconductor layer 1 can be performed before the process of forming the p-type semiconductor layer 3. This prevents the heat from the heat treatment from being applied to the p-type semiconductor layer 3, suppressing deterioration of the p-type semiconductor layer 3 and contributing to improved reliability of the semiconductor device. Furthermore, regardless of the finished state of the side surface shape of the p-type semiconductor layer 3, the end of the first surface electrode 21 is covered, suppressing electric field concentration in the p-type semiconductor layer 3 and contributing to improved reliability of the semiconductor device.

[0021] The area density of the acceptors in the p-type semiconductor layer 3 is 5×10 １２ From 2 x 10 １３ cm －２ is preferable. By setting the area density of the acceptors in the p-type semiconductor layer 3 in this range, the depletion layer in the p-type semiconductor layer 3 spreads appropriately, and electric field concentration can be effectively alleviated. Here, assuming that no n-type impurities exist in the p-type semiconductor layer 3, or that the amount of n-type impurities in the p-type semiconductor layer 3 is negligible compared to the amount of p-type impurities, the area density of the acceptors in the p-type semiconductor layer 3 is determined by the product of the impurity concentration of the p-type impurities and the film thickness. For example, when the thickness of the p-type semiconductor layer 3 is 100 nm, the impurity concentration of the p-type impurities in the p-type semiconductor layer 3 is set to 5×10 １７ From 2 x 10 １８ cm －３ By setting the range of １２ From 2 x 10 １３ cm －２ The range can be:

[0022] <Second Preferred Embodiment> Fig. 2 is a diagram showing the configuration of an SBD, which is a semiconductor device according to a second preferred embodiment. In Fig. 2, elements that are the same as or correspond to elements shown in Fig. 1 are given the same reference numerals.

[0023] As shown in FIG. 2 , in the semiconductor device according to the second embodiment, a trench 5 is formed outside a first surface electrode 21 in an n-type semiconductor layer 1. The inner peripheral edge of a p-type semiconductor layer 3 runs over the first surface electrode 21. That is, the p-type semiconductor layer 3 extends so as to cover the outer peripheral edge of the first surface electrode 21 and the inner side surface of the trench 5. Here, in FIG. 2 , the outer peripheral edge of the p-type semiconductor layer 3 is located inside the trench 5, and the p-type semiconductor layer 3 covers part of the bottom surface of the trench 5. However, the p-type semiconductor layer 3 may also run over from the outer peripheral edge of the trench 5 (not shown) to the outer peripheral side, covering the entire bottom surface of the trench 5. The configuration of the second embodiment can more effectively alleviate electric field concentration near the end of the first surface electrode 21.

[0024] In this embodiment, the position of the outer circumferential edge of the first surface electrode 21 coincides with the position of the inner circumferential edge of the trench 5. The two positions do not need to coincide perfectly, and the above-described effect can be obtained even if they are slightly misaligned (for example, by about 1 μm). However, when the position of the outer circumferential edge of the first surface electrode 21 coincides with the position of the inner circumferential edge of the trench 5, in the manufacture of the semiconductor device, trench 5 can be formed by etching n-type semiconductor layer 1 using first surface electrode 21 as a mask, as shown in FIG. 3 , after forming first surface electrode 21 and before forming p-type semiconductor layer 3, thereby obtaining the effect of suppressing an increase in the number of photolithography steps.

[0025] 4 is a diagram showing the configuration of an SBD, which is a semiconductor device according to a third embodiment. In Fig. 4, elements that are the same as or correspond to elements shown in Fig. 1 are also given the same reference numerals.

[0026] The semiconductor device according to the third embodiment includes a second surface electrode 22 formed on a first surface electrode 21 and made of a metal such as Al or Cu, or an Al alloy such as Al-Si. The second surface electrode 22 may be formed at a temperature lower than the heating temperature in the heat treatment for forming a contact between the first surface electrode 21 and the n-type semiconductor layer 1. In this case, thermal degradation of the p-type semiconductor layer 3 can be suppressed. Covering the first surface electrode 21 with the second surface electrode 22 can mitigate damage to the first surface electrode 21 caused by wire bonding or the like. Forming the second surface electrode 22 thicker than the first surface electrode 21 can further effectively mitigate damage to the first surface electrode 21 caused by wire bonding or the like.

[0027] The outer peripheral edge of the second surface electrode 22 rides up onto the p-type semiconductor layer 3. That is, the second surface electrode 22 covers the portion of the first surface electrode 21 exposed from the p-type semiconductor layer 3 and the inner peripheral edge of the p-type semiconductor layer 3. In this configuration, by adjusting the position of the outer peripheral edge of the second surface electrode 22, the position of the electric field concentration point can be adjusted, and a desired electric field design is possible.

[0028] For example, the outer peripheral edge of the second surface electrode 22 may extend outward beyond the first surface electrode 21. In this case, when the inside of the p-type semiconductor layer 3 is depleted, the portion of the second surface electrode 22 extending outward beyond the first surface electrode 21 functions as a field plate, and an electric field alleviation effect by the field plate can be expected. However, since electric field concentration may occur near the outer peripheral edge of the second surface electrode 22, the position of the outer peripheral edge of the second surface electrode 22 may be determined appropriately to an extent that the insulating properties of the material around the outer peripheral edge of the second surface electrode 22 are not deteriorated.

[0029] On the other hand, if the position of the outer peripheral edge of the second surface electrode 22 is located inside the inner peripheral edge of the first surface electrode 21, the electric field concentration near the outer peripheral edge of the second surface electrode 22 is alleviated, and it is possible to suppress deterioration of the insulating properties of the material around the outer peripheral edge of the second surface electrode 22. However, the position of the outer peripheral edge of the second surface electrode 22 should be determined appropriately so that the electric field alleviation effect as a field plate is not reduced, that is, so that the desired electric field alleviation effect is obtained.

[0030] In this embodiment, the second surface electrode 22 is formed to suppress damage to the first surface electrode 21 due to wire bonding, etc., but a similar effect can be obtained by forming the first surface electrode 21 thick, for example, to a thickness of 1 μm or more, without forming the second surface electrode 22.

[0031] <Fourth Preferred Embodiment> Fig. 5 is a diagram showing the configuration of an SBD, which is a semiconductor device according to a fourth preferred embodiment. In Fig. 5, elements that are the same as or correspond to elements shown in Fig. 1 are also given the same reference numerals.

[0032] The semiconductor device according to the fourth embodiment includes an insulating layer 6 that covers the p-type semiconductor layer 3. The insulating layer 6 extends from above the first surface electrode 21 on the inside of the p-type semiconductor layer 3 to above the n-type semiconductor layer 1 on the outside of the p-type semiconductor layer 3, and covers the entire p-type semiconductor layer 3.

[0033] By covering the p-type semiconductor layer 3 with the insulating layer 6, the p-type semiconductor layer 3 is not exposed to materials other than the insulating layer 6, and changes in the film properties of the p-type semiconductor layer 3 over time, such as deterioration due to external influences, can be suppressed, and a high breakdown voltage can be stably obtained.

[0034] The material of the insulating layer 6 is SiO ２ , Al ２ O ３ , SiN, etc. can be used as the material for the insulating layer 6. ２ , ZnO ２ , TiO ２ and BaTiO ３ Silicon oxide (SiO ２ A high-dielectric (high-k) material having a higher relative dielectric constant than the insulating layer 6 may be used, in which case the electric field concentration can be effectively alleviated by the potential gradient generated within the insulating layer 6.

[0035] 6 shows an example in which the insulating layer 6 of this embodiment is applied to the semiconductor device of the third embodiment (FIG. 4). In FIG. 4, the inner peripheral edge of the insulating layer 6 rides up onto the second surface electrode 22. That is, the outer peripheral edge of the second surface electrode 22 is covered with the insulating layer 6.

[0036] 6 , the outer peripheral edge of the second surface electrode 22 may run onto the insulating layer 6 as shown in FIG. 7 . That is, the inner peripheral edge of the insulating layer 6 may be covered by the second surface electrode 22. In this case, similar to the fourth embodiment, the position of the outer peripheral edge of the second surface electrode 22 can be adjusted to adjust the position of the electric field concentration point, thereby enabling a desired electric field design.

[0037] For example, the outer peripheral edge of the second surface electrode 22 may extend outward beyond the first surface electrode 21. In this case, when the inside of the p-type semiconductor layer 3 is depleted, the portion of the second surface electrode 22 extending outward beyond the first surface electrode 21 functions as a field plate, and an electric field alleviation effect by the field plate can be expected. However, since electric field concentration may occur near the outer peripheral edge of the second surface electrode 22, the position of the outer peripheral edge of the second surface electrode 22 may be determined appropriately to an extent that the insulating properties of the material around the outer peripheral edge of the second surface electrode 22 are not deteriorated.

[0038] On the other hand, if the outer peripheral edge of the second surface electrode 22 is positioned inside the inner peripheral edge of the first surface electrode 21, the electric field concentration near the outer peripheral edge of the second surface electrode 22 is alleviated, and it is possible to suppress deterioration of the insulating properties of the material around the outer peripheral edge of the second surface electrode 22. However, since the electric field alleviation effect as a field plate may be reduced, the position of the outer peripheral edge of the second surface electrode 22 may be determined appropriately to an extent that the desired electric field alleviation effect is obtained.

[0039] Fifth Preferred Embodiment In a fifth preferred embodiment, an example will be shown in which the semiconductor device is a pn junction diode. Fig. 8 is a diagram showing the configuration of a pn junction diode, which is a semiconductor device according to the fifth preferred embodiment. In Fig. 8, elements that are the same as or correspond to elements shown in Fig. 1 are given the same reference numerals.

[0040] The semiconductor device according to the fifth embodiment includes a high-concentration p-type semiconductor layer 7 as a third semiconductor layer between the n-type semiconductor layer 1 and the first surface electrode 21, the high-concentration p-type semiconductor layer 7 having a higher concentration of second conductivity type impurities than the p-type semiconductor layer 3. The high-concentration p-type semiconductor layer 7 and the n-type semiconductor layer 1 form a pn junction diode. The material of the high-concentration p-type semiconductor layer 7 is the same as that of the p-type semiconductor layer 3, for example, NiO, Cu, ２A hetero semiconductor layer such as O or ZnO can be used, and if formable, a p-type gallium oxide semiconductor layer may also be used.

[0041] 9 , the high-concentration p-type semiconductor layer 7 may extend beyond the first surface electrode 21. In this case, the p-type semiconductor layer 3 covers the portion of the high-concentration p-type semiconductor layer 7 that protrudes beyond the first surface electrode 21 (the portion exposed from the first surface electrode 21). The portion of the high-concentration p-type semiconductor layer 7 that is exposed from the first surface electrode 21 may be deteriorated by heat from the heat treatment for forming a contact between the first surface electrode 21 and the high-concentration p-type semiconductor layer 7, but the p-type semiconductor layer 3 is not deteriorated by the heat, and therefore the p-type semiconductor layer 3 is prevented from becoming floating.

[0042] Sixth Preferred Embodiment In a sixth preferred embodiment, an example in which the semiconductor device is a MOSFET is shown. Fig. 10 is a diagram showing the configuration of a MOSFET, which is a semiconductor device according to the sixth preferred embodiment. In Fig. 10, elements that are the same as or correspond to elements shown in Fig. 1 are also given the same reference numerals. The semiconductor device shown in Fig. 10 is a vertical MOSFET in which a main current flows in the thickness direction of an n-type semiconductor layer 1.

[0043] 10, in the semiconductor device according to the sixth embodiment, a plurality of wells 8 are selectively provided in the surface layer portion on the upper surface side of the n-type semiconductor layer 1. The wells 8 are p-type semiconductor layers made of oxide semiconductors or high-resistance layers formed by nitrogen ion implantation or the like. A channel can be formed in the wells 8. In this embodiment, an example is shown in which the wells 8 are high-resistance layers, but a p-type gallium oxide semiconductor layer may also be used. The surface layer portion of each well 8 is provided with an n-type impurity layer containing a higher concentration of n-type impurities than the n-type semiconductor layer 1. ＋ 10 , the well 8 located at the outermost periphery (the well 8 located below the outer periphery of the first surface electrode 21) does not have a source layer 9, but the well 8 may have a source layer 9. The source layer 9 can be formed by, for example, implanting ions into the n-type semiconductor layer 1.

[0044] A gate insulating film 10 is provided on the upper surface of the n-type semiconductor layer 1 so as to straddle the adjacent wells 8. The material of the gate insulating film 10 is SiO ２ , Al ２ O ３ The gate insulating film 10 may be made of HfO. ２ , ZnO ２ , TiO ２ and BaTiO ３ Silicon oxide (SiO ２ A high-dielectric (high-k) material having a higher dielectric constant than the gate insulating film 10 may be used. In this case, the potential gradient generated within the gate insulating film 10 can effectively alleviate electric field concentration. A gate electrode 11 is provided on the gate insulating film 10 so as to straddle the source layers 9 of adjacent wells 8. The gate electrode 11 can be made of a material such as metal or polysilicon. Using polysilicon facilitates processing and improves productivity. Furthermore, a stable electrode layer can be formed, resulting in stable electrical characteristics. An interlayer insulating film 12 is provided to cover the gate insulating film 10 and gate electrode 11. The gate insulating film 10, gate electrode 11, and interlayer insulating film 12 are also provided on the outermost wells 8 where no source layers 9 are provided.

[0045] The first surface electrode 21 is provided on the interlayer insulating film 12. The first surface electrode 21 is connected to the source layer 9 and the well 8 through contact holes formed in the interlayer insulating film 12, and functions as a source electrode of the MOSFET. The back surface electrode 4 functions as a drain electrode of the MOSFET.

[0046] The p-type semiconductor layer 3 serving as an electric field relaxation layer is disposed on the n-type semiconductor layer 1 around the first surface electrode 21, and the inner peripheral edge of the p-type semiconductor layer 3 extends over the first surface electrode 21. Therefore, in manufacturing the semiconductor device, heat treatment for forming contact between the first surface electrode 21 and the n-type semiconductor layer 1 can be performed before forming the p-type semiconductor layer 3. As a result, heat from the heat treatment is not applied to the p-type semiconductor layer 3, and deterioration of the p-type semiconductor layer 3 is suppressed.

[0047] In this embodiment, a planar gate MOSFET is shown, but the MOSFET may be a trench gate MOSFET in which a gate insulating film and a gate electrode are formed in a trench that penetrates the well 8 and reaches the n-type semiconductor layer 1. Furthermore, the region through which the main current of the semiconductor device flows may have a FinFET structure in which the well 8 is not formed, but a plurality of trenches are formed at a narrow pitch in the n-type semiconductor layer 1, and a gate insulating film and a gate electrode are formed in the trenches.

[0048] It is also conceivable that the semiconductor device can be made into an IGBT (Insulated Gate Bipolar Transistor) by providing a p-type hetero semiconductor layer made of the same material as the p-type semiconductor layer 3 or a p-type gallium oxide semiconductor layer on the lower surface side of the n-type semiconductor layer 1.

[0049] In the above embodiment, a vertical semiconductor device in which the main current flows in the thickness direction of the n-type semiconductor layer 1 has been shown, but the technology of the present disclosure can also be applied to a horizontal semiconductor device in which the main current flows in the planar direction of the n-type semiconductor layer 1.

[0050] Seventh Embodiment In this embodiment, the semiconductor device according to any one of the above-described first to sixth embodiments is applied to a power conversion device. Although application of the semiconductor device according to any one of the first to sixth embodiments is not limited to a specific power conversion device, the seventh embodiment will be described below as a case where the semiconductor device according to any one of the first to sixth embodiments is applied to a three-phase inverter.

[0051] FIG. 11 is a block diagram showing the configuration of a power conversion system to which the power conversion device according to this embodiment is applied.

[0052] The power conversion system shown in Fig. 11 is composed of a power supply 100, a power conversion device 200, and a load 300. The power supply 100 is a DC power supply and supplies DC power to the power conversion device 200. The power supply 100 can be composed of various components, such as a DC system, a solar cell, or a storage battery, or it may be composed of a rectifier circuit connected to an AC system or an AC / DC converter. The power supply 100 may also be composed of a DC / DC converter that converts DC power output from a DC system into a predetermined power.

[0053] The power conversion device 200 is a three-phase inverter connected between the power source 100 and the load 300, and converts DC power supplied from the power source 100 into AC power and supplies the AC power to the load 300. As shown in Fig. 11 , the power conversion device 200 includes a main conversion circuit 201 that converts DC power into AC power and outputs it, a drive circuit 202 that outputs drive signals that drive each switching element of the main conversion circuit 201, and a control circuit 203 that outputs control signals to the drive circuit 202.

[0054] The load 300 is a three-phase electric motor driven by AC power supplied from the power conversion device 200. The load 300 is not limited to a specific application, but is an electric motor mounted on various electrical devices, and is used as an electric motor for, for example, a hybrid vehicle, an electric vehicle, a railroad car, an elevator, or an air conditioning device.

[0055] The power conversion device 200 will be described in detail below. The main conversion circuit 201 includes switching elements and freewheel diodes (not shown). The switching elements convert DC power supplied from the power supply 100 into AC power, which is supplied to the load 300. The main conversion circuit 201 can have a variety of specific circuit configurations. The main conversion circuit 201 according to this embodiment is a two-level, three-phase full-bridge circuit, which can be configured with six switching elements and six freewheel diodes connected in anti-parallel to each switching element. At least one of the switching elements and freewheel diodes of the main conversion circuit 201 is configured with a semiconductor device according to any one of the first to sixth embodiments. Two of the six switching elements are connected in series to form upper and lower arms, which constitute a respective phase (U phase, V phase, and W phase) of the full-bridge circuit. The output terminals of each upper and lower arm, i.e., the three output terminals of the main conversion circuit 201, are connected to the load 300.

[0056] The drive circuit 202 generates drive signals for driving the switching elements of the main conversion circuit 201 and supplies them to the control electrodes of the switching elements of the main conversion circuit 201. Specifically, in accordance with control signals from a control circuit 203 (described later), the drive circuit 202 outputs to the control electrodes of each switching element a drive signal that turns the switching element on and a drive signal that turns the switching element off. When maintaining a switching element in the on state, the drive signal is a voltage signal (on signal) that is equal to or higher than the threshold voltage of the switching element, and when maintaining a switching element in the off state, the drive signal is a voltage signal (off signal) that is equal to or lower than the threshold voltage of the switching element.

[0057] The control circuit 203 controls the switching elements of the main conversion circuit 201 so that the desired power is supplied to the load 300. Specifically, it calculates the time (on time) that each switching element of the main conversion circuit 201 should be in the on state based on the power to be supplied to the load 300. For example, the main conversion circuit 201 can be controlled by PWM control, which modulates the on time of the switching elements according to the voltage to be output. The control circuit 203 then outputs a control command (control signal) to the drive circuit 202 so that an on signal is output to the switching element that should be in the on state at each time, and an off signal is output to the switching element that should be in the off state at each time. In accordance with this control signal, the drive circuit 202 outputs an on signal or an off signal as a drive signal to the control electrode of each switching element.

[0058] In the power conversion device according to the present embodiment, the semiconductor device according to any one of the first to sixth embodiments is applied as the switching element of the main conversion circuit 201, and therefore reliability can be improved.

[0059] In the present embodiment, an example has been described in which the semiconductor device according to any one of the first to sixth embodiments is applied to a two-level three-phase inverter, but the application of the semiconductor device according to any one of the first to sixth embodiments is not limited to this, and the semiconductor device can be applied to various power conversion devices. In the present embodiment, a two-level power conversion device is described, but a three-level or multi-level power conversion device may also be used, and when power is supplied to a single-phase load, the semiconductor device according to any one of the first to sixth embodiments may be applied to a single-phase inverter. Furthermore, when power is supplied to a DC load or the like, the semiconductor device according to any one of the first to sixth embodiments can also be applied to a DC / DC converter or an AC / DC converter.

[0060] Furthermore, a power conversion device to which the semiconductor device according to any one of the first to sixth embodiments is applied is not limited to cases in which the load described above is an electric motor, but can also be used, for example, as a power supply device for an electric discharge machine, a laser processing machine, an induction heating cooker, or a contactless power supply system, and can also be used as a power conditioner for a solar power generation system, a power storage system, etc.

[0061] It is possible to freely combine the embodiments, and to modify or omit the embodiments as appropriate.

[0062] The above description is illustrative in all respects, and it is understood that countless variations not illustrated can be envisioned.

[0063] 1 n-type semiconductor layer, 21 first surface electrode, 22 second surface electrode, 3 p-type semiconductor layer, 4 back surface electrode, 5 trench, 6 insulating layer, 7 high-concentration p-type semiconductor layer, 8 well, 9 source layer, 10 gate insulating film, 11 gate electrode, 12 interlayer insulating film, 100 power supply, 200 power conversion device, 201 main conversion circuit, 202 drive circuit, 203 control circuit, 300 load.

Claims

1. A semiconductor device comprising: a first semiconductor layer made of an oxide semiconductor of a first conductivity type; a first surface electrode provided on a first major surface of the first semiconductor layer; and a second semiconductor layer of a second conductivity type provided on the first major surface around the first surface electrode, wherein an inner peripheral edge of the second semiconductor layer rides on the first surface electrode.

2. The semiconductor device according to claim 1, wherein the oxide semiconductor is a gallium oxide semiconductor.

3. The semiconductor device according to claim 1 or claim 2, further comprising a trench provided in the first semiconductor layer around the first surface electrode, the second semiconductor layer covering part or all of the bottom of the trench.

4. The semiconductor device according to claim 3, wherein the position of the outer circumferential edge of said first surface electrode coincides with the position of the inner circumferential edge of said trench.

5. The semiconductor device according to any one of claims 1 to 4, further comprising a second surface electrode provided on the first surface electrode, the outer peripheral edge of the second surface electrode extending over the second semiconductor layer.

6. The semiconductor device according to any one of claims 1 to 5, further comprising an insulating layer covering the second semiconductor layer.

7. The semiconductor device according to any one of claims 1 to 6, further comprising a third semiconductor layer of the second conductivity type provided between the first semiconductor layer and the first surface electrode and having a higher impurity concentration than the second semiconductor layer.

8. The semiconductor device according to claim 7, wherein the third semiconductor layer protrudes outward beyond the first surface electrode, and the portion of the third semiconductor layer protruding outward beyond the first surface electrode is covered by the second semiconductor layer.

9. The semiconductor device according to any one of claims 1 to 6, wherein the first surface electrode is a source electrode of a MOSFET or an IGBT.

10. A power conversion device comprising: a main conversion circuit having a semiconductor device according to any one of claims 1 to 9, which converts input power and outputs it; a drive circuit which outputs a drive signal to drive said semiconductor device; and a control circuit which outputs a control signal to control said drive circuit to said drive circuit.

11. A method for manufacturing a semiconductor device, comprising: a step of forming a first surface electrode on a first main surface of a first semiconductor layer composed of an oxide semiconductor of a first conductivity type; a step of performing heat treatment to form contact between the first surface electrode and the first semiconductor layer; and a step of forming a second semiconductor layer of a second conductivity type on the first main surface around the first surface electrode, the second semiconductor layer climbing up onto the outer peripheral edge of the first surface electrode, after the step of performing the heat treatment.

12. The method for manufacturing a semiconductor device according to claim 11, wherein the oxide semiconductor is a gallium oxide semiconductor.

13. A method for manufacturing a semiconductor device according to claim 11 or 12, further comprising the step of forming a trench in the first semiconductor layer around the first surface electrode by etching using the first surface electrode as a mask, after the step of forming the first surface electrode and before the step of forming the second semiconductor layer.

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