Metal-oxide-semiconductor field-effect transistor (mosfet) and manufacturing method therefor

Abstract

Provided in the present invention are an MOSFET and a manufacturing method therefor. The MOSFET comprises a substrate, wherein an epitaxial layer is provided on the substrate; a trench gate group comprises a first trench gate and a plurality of second trench gates, the first trench gate extends into the epitaxial layer from the surface of the side of the epitaxial layer away from the substrate, the first trench gate extends in a first direction on a plane where the epitaxial layer is located, the plurality of second trench gates are arranged at intervals in the first direction, the orthographic projection of each second trench gate on the substrate is located within the orthographic projection of the first trench gate on the substrate, the top of each second trench gate is in contact with the bottom of the first trench gate, and a gate layer in each second trench gate is connected to a gate layer in the first trench gate; and each shielding region wraps the bottom and all side walls of the corresponding second trench gate and extends to the surface of the side of the epitaxial layer away from the substrate to cover a side wall of the first trench gate, and a plurality of shielding regions are arranged at intervals. Each shielding region has a three-dimensional structure, such that the gate oxide electric field stress in each trench can be reduced, the cell size of the MOSFET can also be reduced, and the current density of the MOSFET is increased.

Description

Metal oxide semiconductor field effect transistor and manufacturing method thereof

[0001] This application claims priority to Chinese patent application CN202410319696.8, entitled “Metal Oxide Semiconductor Field Effect Transistor and Method for Manufacturing Same,” filed on March 20, 2024, the entire contents of which are incorporated herein by reference. Technical Field

[0002] The present invention relates to the technical field of semiconductor devices, and in particular to a metal oxide semiconductor field effect transistor and a manufacturing method thereof. Background Art

[0003] With the development of power semiconductor technology, silicon carbide metal oxide semiconductor field effect transistors (MOSFETs) are becoming increasingly common in the fields of new energy, wind power, photovoltaics, and energy storage due to their material advantages.

[0004] Among them, trench gate MOSFETs can reduce cell size compared to planar gate MOSFETs, significantly improving MOSFET current density. However, due to the wide bandgap characteristics of silicon carbide materials, the gate oxide electric field stress in the trench is extremely high. Therefore, an electric field shielding structure must be designed to protect the gate oxide in the trench to meet long-term reliability requirements. However, the electric field shielding structure introduces parasitic junction field-effect transistor (JFET) region resistance, resulting in a decrease in the MOSFET's current density. Currently, the current density of trench gate silicon carbide MOSFETs with shielding structures needs to be improved, and the cell size needs to be further reduced.

[0005] Summary of the Invention

[0006] The present invention aims to solve one of the technical problems in the related art at least to a certain extent.

[0007] To this end, in one aspect, the present invention provides a metal oxide semiconductor field effect transistor. The metal oxide semiconductor field effect transistor comprises: a substrate; an epitaxial layer disposed on the substrate; a trench gate group, the trench gate group comprising a first trench gate and a plurality of second trench gates, the first trench gate extending from a surface of the epitaxial layer away from the substrate into the epitaxial layer, the first trench gate extending in a first direction in the plane of the epitaxial layer, the plurality of second trench gates spaced apart along the first direction, the orthographic projection of the second trench gate on the substrate being within the orthographic projection of the first trench gate on the substrate, the top of the second trench gate contacting the bottom of the first trench gate, and the gate layer in the second trench gate connected to the gate layer in the first trench gate; and a plurality of shielding regions, each of the shielding regions wrapping around the bottom and all sidewalls of the second trench gate and extending toward the surface of the epitaxial layer away from the substrate to cover the sidewalls of the first trench gate, the plurality of shielding regions spaced apart. The shielding area has a three-dimensional structure, which can not only reduce the trench gate oxide electric field stress, but also reduce the cell size of the MOSFET and increase the current density of the MOSFET.

[0008] Further, in the direction in which the substrate and the epitaxial layer are stacked, the second trench gate extends into the substrate; or, a buffer layer is provided between the substrate and the epitaxial layer, and in the direction in which the substrate and the epitaxial layer are stacked, the second trench gate extends into the buffer layer or extends into the substrate.

[0009] Furthermore, the second trench gate includes a plurality of trench gate portions connected to each other, and the plurality of trench gate portions are sequentially arranged in a direction from the epitaxial layer toward the substrate, and their widths decrease sequentially.

[0010] Furthermore, the thickness of the shielding region covering the sidewall of the first trench gate is consistent with the thickness of the shielding region wrapping the sidewall of the second trench gate, and the thickness is 0.1-1 μm. The thickness of the shielding region wrapping the bottom of the second trench gate is 0.5-2 μm.

[0011] Furthermore, the doping concentration of the shielding region is 1×10 16 cm -3 -1×10 19 cm -3 .

[0012] Furthermore, it includes a plurality of trench gate groups, wherein the first trench gates in the plurality of trench gate groups are arranged in sequence along a second direction in the plane where the epitaxial layer is located, the second direction intersects with the first direction, and in the second direction, two adjacent second trench gates are arranged in the same row or staggered rows.

[0013] Furthermore, the metal oxide semiconductor field effect transistor includes a plurality of trench gate groups, the first trench gates in the plurality of trench gate groups are arranged in sequence along a second direction in the plane where the epitaxial layer is located, the second direction intersects with the first direction, the N+ region and the P+ region in the epitaxial layer extend from the surface of the epitaxial layer away from the substrate side into the epitaxial layer, the top of the P-well region in the epitaxial layer contacts the bottom of the N+ region and the bottom of the P+ region, the first trench gate passes through the N+ region and the P-well region, the P+ region is arranged at intervals along the first direction and is located between two adjacent first trench gates, and the N+ region is located around the P+ region, or the P+ region extends along the first direction and is located between two adjacent first trench gates, and the N+ region is located on both sides of the P+ region.

[0014] Furthermore, the metal oxide semiconductor field effect transistor includes: a plurality of trench gate groups, wherein the first trench gates in the plurality of trench gate groups are arranged in sequence along a second direction in the plane where the epitaxial layer is located, and the second direction intersects with the first direction; and a plurality of third trench gates extending along the second direction and arranged in sequence along the first direction, wherein the third trench gates extend from the surface of the epitaxial layer away from the substrate into the epitaxial layer, and the orthographic projection of the second trench gate on the substrate is located within the orthographic projection range of the intersection area of ​​the first trench gate and the third trench gate on the substrate, and each of the shielding regions further covers the sidewalls of the third trench gate, or the orthographic projection of the second trench gate on the substrate is located between the orthographic projections of two adjacent third trench gates on the substrate, and each of the shielding regions is located between two adjacent third trench gates.

[0015] Furthermore, the N+ region and the P+ region in the epitaxial layer extend from the surface of the epitaxial layer away from the substrate into the epitaxial layer, the top of the P-well region in the epitaxial layer contacts the bottom of the N+ region and the bottom of the P+ region, the first trench gate and the third trench gate both penetrate the N+ region and the P-well region, the P+ region is located in the area surrounded by the first trench gate and the third trench gate, and the N+ region is located around the P+ region.

[0016] Furthermore, the third trench gate and the first trench gate define a plurality of cells, and the shape of the cells includes square, hexagon, octagon or circle.

[0017] In another aspect, the present invention provides a method for fabricating a metal oxide semiconductor field effect transistor, the method comprising: forming an epitaxial layer on a substrate; forming a trench gate group and a plurality of shielding regions in the epitaxial layer, the trench gate group comprising a first trench gate and a plurality of second trench gates, the first trench gate extending from a surface of the epitaxial layer away from the substrate into the epitaxial layer, the first trench gate extending in a first direction in the plane of the epitaxial layer, the plurality of second trench gates spaced apart along the first direction, the orthographic projection of the second trench gate on the substrate being within the orthographic projection of the first trench gate on the substrate, the top of the second trench gate contacting the bottom of the first trench gate, the gate layer in the second trench gate connected to the gate layer in the first trench gate, each shielding region wrapping around the bottom and all sidewalls of the second trench gate and extending toward the surface of the epitaxial layer away from the substrate to cover the sidewalls of the first trench gate, the plurality of shielding regions spaced apart. The shielding regions formed by this method have a three-dimensional structure, which can not only reduce the trench gate oxygen electric field stress, but also reduce the cell size of the MOSFET and increase the current density of the MOSFET.

[0018] Furthermore, forming a trench gate group and multiple shielding regions in the epitaxial layer includes: forming a first trench, the first trench extending from the surface of the epitaxial layer away from the substrate side into the epitaxial layer, and the first trench extending along the first direction; forming multiple second trenches in the first trench, the multiple second trenches being arranged at intervals along the first direction; forming multiple shielding regions, each of the shielding regions wrapping the bottom and all side walls of the second trench, and extending toward the surface of the epitaxial layer away from the substrate side to cover the side walls of the first trench; forming a gate oxide layer on the side walls and bottom of the first trench and the second trench; forming a gate layer in the first trench and the second trench, the gate layer contacting the gate oxide layer to form the first trench gate and the second trench gate to form the trench gate group. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the following is a brief introduction to the drawings required for use in the description of the embodiments. Obviously, the drawings described below are some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative labor.

[0020] FIG1 shows a schematic top view of a MOSFET according to an embodiment of the present invention;

[0021] FIG2 shows a schematic structural diagram of the MOSFET along the section AA' in FIG1 ;

[0022] FIG3 shows a schematic structural diagram of the MOSFET along the BB' section in FIG1 ;

[0023] FIG4 shows a schematic structural diagram of the MOSFET along the C-C' section in FIG1 ;

[0024] FIG5 shows a schematic structural diagram of the MOSFET along the D-D' section in FIG1 ;

[0025] FIG6 shows a schematic structural diagram of a MOSFET according to another embodiment of the present invention;

[0026] FIG7 shows a schematic top view of a MOSFET according to another embodiment of the present invention;

[0027] FIG8 shows a schematic top view of a MOSFET according to another embodiment of the present invention;

[0028] FIG9 shows a schematic top view of a MOSFET according to another embodiment of the present invention;

[0029] FIG10 shows a schematic top view of a MOSFET according to another embodiment of the present invention;

[0030] FIG11 is a schematic flow chart showing a method for manufacturing a MOSFET according to an embodiment of the present invention;

[0031] FIG. 12 is a schematic diagram showing a partial flow chart of a method for manufacturing a MOSFET according to an embodiment of the present invention. DETAILED DESCRIPTION

[0032] The following embodiments of the present invention are described in detail. The embodiments described below are exemplary and are only used to explain the present invention, and are not to be construed as limiting the present invention. Where specific techniques or conditions are not specified in the embodiments, the techniques or conditions described in the literature in the art or in the product specifications shall be followed.

[0033] In one aspect of the present invention, a metal oxide semiconductor field effect transistor is proposed. In some embodiments of the present invention, in combination with Figures 1 to 5, the metal oxide semiconductor field effect transistor includes: a substrate 100, an epitaxial layer 200, a trench gate group 300 and a plurality of shielding regions 400. The epitaxial layer 200 is provided on the substrate 100, the trench gate group 300 includes a first trench gate 310 and a plurality of second trench gates 320, the first trench gate 310 extends from the surface of the epitaxial layer 200 away from the side of the substrate 100 to the epitaxial layer 200 (as shown in Figure 2), and the first trench gate 310 extends along the first direction D1 in the plane where the epitaxial layer 200 is located, and the plurality of second trench gates 320 are arranged at intervals along the first direction D1, and the orthographic projection of the second trench gate 320 on the substrate 100 is located at the first trench gate 310 on the substrate. Within the range of the orthographic projection on the bottom 100, the top of the second trench gate 320 contacts the bottom of the first trench gate 310, and the gate layer 20 in the second trench gate 320 is connected to the gate layer 20 in the first trench gate 310 (as shown in FIG2 ). Each shielding region 400 wraps around the bottom and all sidewalls of the second trench gate 320 (as shown in FIG2 and FIG4 ), and extends toward the surface of the epitaxial layer 200 away from the substrate 100 to cover the sidewalls of the first trench gate 310 (as shown in FIG2 ), and multiple shielding regions 400 are arranged at intervals.

[0034] Since the second trench gates 320 are arranged at intervals along the first direction D1, the shielding region 400 can wrap all the sidewalls of the second trench gates 320. As shown in FIG2 , the shielding region 400 covers the sidewalls of the second trench gates 320 in the second direction D2. As shown in FIG4 , the shielding region 400 also covers the sidewalls of the second trench gates 320 in the first direction D1. The second direction D2 is a direction on the plane where the epitaxial layer 200 is located that intersects with the first direction D1. More specifically, the second direction D2 is perpendicular to the first direction D1.

[0035] Each shielding region 400 wraps around the bottom and all sidewalls of the second trench gate 320 and extends toward the surface of the epitaxial layer 200 away from the substrate 100 to cover the sidewalls of the first trench gate 310 (as shown in Figures 1 and 2). The present invention provides a shielding region with a three-dimensional structure by arranging a second trench gate arranged at intervals below the first trench gate. On the one hand, the shielding region can reduce the gate oxide electric field stress in the trench gate and improve the long-term reliability of the MOSFET. On the other hand, compared with the current two-dimensional shielding structure, the present invention forms a shielding region in the three-dimensional direction (i.e., the first direction D1), which can greatly reduce the size of the MOSFET cell in the two-dimensional direction, thereby improving the current density of the MOSFET. On the other hand, the shielding region around the second trench gate is completely depleted when the MOSFET is in the blocking state, thereby greatly increasing the doping concentration of the epitaxial layer, reducing the resistance of the JFET region, and thus improving the current density of the MOSFET.

[0036] The plurality of shielding regions 400 are arranged at intervals. As shown in FIG. 1 , the plurality of shielding regions are arranged at intervals in the first direction to ensure that the MOSFET is turned on.

[0037] It should be noted that the top of the second trench gate 320 is the end of the second trench gate 320 away from the substrate 100, the bottom of the first trench gate 310 is the end of the first trench gate 310 close to the substrate 100, and the bottom of the second trench gate 320 is the end of the second trench gate 320 close to the substrate 100.

[0038] In some embodiments of the present invention, referring to FIG2 , the first trench gate 310 includes a gate oxide layer 10 disposed on the inner wall and bottom of the first trench and a gate layer 20 filling the middle of the first trench and contacting the gate oxide layer 10. The second trench gate 320 includes a gate oxide layer 10 disposed on the inner wall and bottom of the second trench gate and a gate layer 20 filling the middle of the second trench and contacting the gate oxide layer 10, and the gate layer 20 of the second trench gate 320 is connected to the gate layer 20 of the first trench gate 310. The first trench is a trench for forming the first trench gate, and the second trench is a trench for forming the second trench gate. The gate layer material may include polysilicon, and the thickness of the gate oxide layer 10 may be 1000 nm.

[0039] The plurality of second trench gates 320 are spaced apart along the first direction D1. Preferably, the distance between two adjacent second trench gates 320 is equal, thereby improving the stability of the MOSFET. The specific distance between two adjacent second trench gates is not particularly limited and can be designed by those skilled in the art based on specific circumstances. For example, if the doping concentration of the epitaxial layer is high, the distance between two adjacent second trench gates can be relatively small.

[0040] The second trench gates 320 are spaced apart along the first direction D1, and the orthographic projections of the second trench gates 320 on the substrate 100 are within the orthographic projections of the first trench gates 310 on the substrate 100. Thus, in the second direction D2, the width of the second trench gates is equal to or less than the width of the first trench gates. The width of the first trench gates can be 0.3-2 μm, and the specific width of the second trench gates is not particularly limited and can be designed according to specific circumstances. The length of the second trench gates in the first direction is also not particularly limited. Preferably, the length and width of the second trench gates can be equal, that is, the orthographic projection of the second trench gates on the substrate is a square.

[0041] In some embodiments of the present invention, the depth of the first trench gate 310 may be 0.4-2 μm. There is no particular limitation on the depth of the second trench gate. For example, in the direction in which the substrate 100 and the epitaxial layer 200 overlap, that is, in the third direction D3, the second trench gate may extend into the substrate 100 (this situation is not shown in the figure). When a buffer layer 800 is provided between the substrate 100 and the epitaxial layer 200 (as shown in FIG2 ), in the third direction D3, the second trench gate may extend into the buffer layer 800, or the second trench gate extends through the buffer layer 800 into the substrate 100 (this situation is not shown in the figure). The greater the depth of the second trench gate, the smaller the resistance of the JFET region, which increases the current density of the MOSFET and improves the parasitic diode capability. The thickness of the buffer layer 800 may be 0.5-3 μm, and the doping concentration may be 1×10 18 cm -3 -1×10 19 cm -3 .

[0042] In some embodiments of the present invention, in the third direction D3, the widths of the various portions of the second trench gate may be equal. Alternatively, in other embodiments of the present invention, referring to FIG6 , the second trench gate 320 includes a plurality of trench gate portions (as shown in FIG6 ) connected to each other. The plurality of trench gate portions are arranged sequentially in the direction from the epitaxial layer 200 to the substrate 100, and the widths decrease sequentially. As shown in FIG6 , the width of the trench gate portion 321B located below is smaller than the width of the trench gate portion 321A located above, i.e., the second trench gate is composed of a multi-stage trench gate. The second trench gate composed of the plurality of trench gate portions may extend into the buffer layer or extend through the buffer layer into the substrate. The second trench gate is composed of a gate oxide layer provided on the inner wall and bottom of the second trench gate and a gate layer filling the middle of the second trench and contacting the gate oxide layer. Each trench gate portion is also composed of a gate oxide layer and a gate layer, and the gate layers in each trench gate portion are connected to each other.

[0043] In some embodiments of the present invention, referring to FIG2 , the thickness d1 of the shielding region 400 covering the sidewalls of the first trench gate 310 is consistent with the thickness d2 of the shielding region 400 covering the sidewalls of the second trench gate 320. Both d1 and d2 can be 0.1-1 μm, which reduces gate oxide electric field stress while ensuring a suitable length for the conductive region and preventing breakage in the shielding region. The thickness d3 of the shielding region 400 covering the bottom of the second trench gate 320 can be 0.5-2 μm, effectively reducing gate oxide electric field stress. The length of the shielding region in the first direction can be determined based on the length of the second trench gate and the thickness of the shielding region covering the sidewalls of the second trench gate.

[0044] In some embodiments of the present invention, the doping concentration of the shielding region 400 may be 1×10 16 cm-3 -1×10 19 cm -3 The shielding region can reduce the gate oxide electric field stress in three dimensions. When the MOSFET is in the blocking state, the shielding region and the epitaxial layer are completely depleted, which can increase the doping concentration of the epitaxial layer to 1×10 16 cm -3 -5×10 17 cm -3 , thereby improving the current density of the MOSFET. The substrate can be an N-type silicon carbide substrate, and the shielding region can be a P-type shielding region.

[0045] In some embodiments of the present invention, referring to FIG1 , the metal oxide semiconductor field effect transistor includes a plurality of trench gate groups 300 , wherein the first trench gates 310 in the plurality of trench gate groups 300 are arranged sequentially along a second direction D2 , and in the second direction D2 , two adjacent second trench gates 320 are arranged in the same row (as shown in FIG1 ) or in staggered rows (as shown in FIG7 ).

[0046] In some embodiments of the present invention, referring to FIG3 , the N+ region 220 and the P+ region 230 in the epitaxial layer 200 extend from the surface of the epitaxial layer 200 away from the substrate 100 into the epitaxial layer 200. The top of the P-well region 210 in the epitaxial layer 200 contacts the bottom of the N+ region 220 and the bottom of the P+ region 230. The first trench gate 310 penetrates the N+ region 220 and the P-well region 210. Referring to FIG1 and FIG7 , the P+ regions 230 are arranged at intervals along the first direction D1 and are positioned Between two adjacent first trench gates 310, and the N+ region 220 is located around the P+ region 230, that is, in the second direction D2, the P+ region 230 can be arranged in the same row as the second trench gate 320 (not shown in the figure), or the second trench gate 320 can be located between two adjacent rows of P+ regions 230 (as shown in Figure 1), or part of the second trench gate 320 is arranged in the same row as the P+ region, and part of the second trench gate 320 is located between two adjacent rows of P+ regions (as shown in Figure 7). Alternatively, referring to Figure 8, the P+ region 230 extends along the first direction D1 and is located between two adjacent first trench gates 310, and the N+ region 220 is located on both sides of the P+ region 230. Since the three-dimensional shielding region reduces the size of the MOSFET cell in the two-dimensional direction, the area ratio of the P+ region is increased, thereby improving the current capacity of the parasitic diode. By adjusting the area ratio of the P+ region and the N+ region, the current capacity of the parasitic diode can be controlled. The junction depth of the P-well region can be 0.2-1μm, and the doping concentration is 1×10 17 cm -3 -1×10 18 cm -3 The junction depth of the N+ region can be 0.1-0.4 μm, and the doping concentration is 5×10 18 cm -3 -5×1020 cm -3 The junction depth of the P+ region can be 0.1-1.5 μm, and the doping concentration is 5×10 18 cm -3 -5×10 20 cm -3 .

[0047] In other embodiments of the present invention, referring to Figures 9 and 10, a metal oxide semiconductor field effect transistor includes a plurality of trench gate groups 300 and a plurality of third trench gates 900. The first trench gates 310 in the plurality of trench gate groups 300 are arranged sequentially along the second direction D2. The plurality of third trench gates 900 extend along the second direction D2 and are sequentially arranged along the first direction D1. The third trench gates 900 extend from a surface of the epitaxial layer 200 away from the substrate 100 into the epitaxial layer 200 (a cross-sectional view of the third trench gate is not shown in the figure). The third trench gate 900 intersects with the first trench gate 310. The orthographic projection of the second trench gate 320 on the substrate can be located within the range of the orthographic projection of the intersection region of the first trench gate 310 and the third trench gate 900 on the substrate. Each shielding region further covers the sidewalls of the third trench gate 900 (as shown in Figure 9). Alternatively, the orthographic projection of the second trench gate 320 on the substrate is located between the orthographic projections of two adjacent third trench gates 900 on the substrate, and each shielding region 400 is located between two adjacent third trench gates 900 (as shown in FIG10 ). The third trench gates 900 and the first trench gate 310 define a plurality of cells, and the shape of the cells may include square, hexagonal, octagonal, or circular.

[0048] In this embodiment, the N+ region 220 and the P+ region 230 in the epitaxial layer extend from the surface of the epitaxial layer away from the substrate into the epitaxial layer. The top of the P-well region 210 in the epitaxial layer contacts the bottom of the N+ region 220 and the bottom of the P+ region 230. The first trench gate 310 and the third trench gate 900 both penetrate the N+ region 220 and the P-well region 210 (a cross-sectional view of the third trench gate is not shown in the figure). The P+ region 230 is located in the area enclosed by the first trench gate 310 and the third trench gate 900, and the N+ region 220 is located around the P+ region 230 (as shown in Figures 9 and 10).

[0049] 2 , the metal oxide semiconductor field effect transistor further includes an interlayer dielectric layer 600, a source 500 and a drain 700. The interlayer dielectric layer 600 is located on the side of the first trench gate 310 away from the substrate, and the thickness of the interlayer dielectric layer can be 0.3-0.8 μm. The source 500 covers the interlayer dielectric layer 600 and the P+ region 230 and the N+ region 220. The interlayer dielectric layer 600 has a via (not shown in the figure) connecting the source 500 and the gate layer 20. The source 500 forms an ohmic contact with the P+ region 230 and the N+ region 220. The source 500 may include a nickel layer that forms an ohmic contact with the P+ region 230 and the N+ region 220, and a metal aluminum layer located on the side of the nickel layer away from the substrate. The thickness of the nickel layer can be The thickness of the aluminum layer can be 1-6 μm. The drain electrode 700 is located on the side of the substrate 100 away from the epitaxial layer 200. The drain electrode material can include Ti, Ni and Ag. A plurality of shielding regions are connected in parallel to the source electrode.

[0050] It should be noted that, in order to facilitate the illustration of the positional relationship between the first trench gate, the shielding region, the P+ region, and the N+ region, FIG1 and FIG7 to FIG10 do not show the interlayer dielectric layer and the source located above the epitaxial layer.

[0051] In another aspect of the present invention, a method for fabricating a metal oxide semiconductor field effect transistor is provided. The metal oxide semiconductor field effect transistor fabricated by this method may be the metal oxide semiconductor field effect transistor described above. Thus, the metal oxide semiconductor field effect transistor fabricated by this method may have the same features and benefits as the metal oxide semiconductor field effect transistor described above, and thus will not be further described herein.

[0052] In some embodiments of the present invention, referring to FIG11 , the method includes steps S100 and S200:

[0053] S100: forming an epitaxial layer on a substrate.

[0054] In this step, an epitaxial layer is formed on the substrate. The substrate can be an N-type silicon carbide substrate formed by an in-situ doping process, the doping element can be nitrogen, the thickness is 80-350 μm, and the doping concentration is 1×10 18 cm -3 -5×10 19 cm -3 .

[0055] There is no particular limitation on the formation method of the epitaxial layer. For example, the epitaxial layer can be formed by a homoepitaxial growth process, with nitrogen as the doping element, a thickness of 5-120 μm, and a doping concentration of 2×10 14 cm -3 -3×10 16 cm-3 .

[0056] In this step, a buffer layer can be formed on the substrate before forming the epitaxial layer. The formation method of the buffer layer is not particularly limited. For example, the buffer layer can be formed by an in-situ doping process, with nitrogen as the doping element, a thickness of 0.5-3 μm, and a doping concentration of 1×10 18 cm -3 -1×10 19 cm -3 .

[0057] S200: forming a trench gate group and a plurality of shielding regions in the epitaxial layer.

[0058] In this step, a trench gate group and multiple shielding regions are formed in the epitaxial layer. The trench gate group includes a first trench gate and multiple second trench gates, wherein the first trench gate extends from a surface of the epitaxial layer away from the substrate into the epitaxial layer, and the first trench gate extends along a first direction in the plane of the epitaxial layer. The multiple second trench gates are arranged at intervals along the first direction, the orthographic projections of the second trench gates on the substrate are located within the orthographic projection range of the first trench gate on the substrate, the tops of the second trench gates contact the bottoms of the first trench gates, and the gate layers in the second trench gates are connected to the gate layers in the first trench gates. Each shielding region wraps around the bottom and all sidewalls of the second trench gates and extends toward the surface of the epitaxial layer away from the substrate to cover the sidewalls of the first trench gates, and the multiple shielding regions are arranged at intervals. Thus, the shielding area formed has a three-dimensional structure. On the one hand, the shielding area can reduce the gate oxide electric field stress in the trench gate and improve the long-term reliability of the MOSFET. On the other hand, compared with the current two-dimensional shielding structure, the three-dimensional shielding area of ​​the present invention can greatly reduce the size of the MOSFET cell in the two-dimensional direction, thereby improving the current density of the MOSFET. On the other hand, the shielding area around the second trench gate is completely depleted when the MOSFET is in the blocking state, so the doping concentration of the epitaxial layer can be greatly increased, the resistance of the JFET area is reduced, and the current density of the MOSFET is improved.

[0059] Before forming the trench gate group and the plurality of shielding regions in the epitaxial layer, the step further includes:

[0060] A P-well region is formed in the epitaxial layer. The specific process for forming the P-well region is not particularly limited. For example, the P-well region is formed by a high-temperature ion implantation process at 500°C, with a junction depth of 0.2-1 μm and a doping concentration of 1×10 17 cm -3 -1×10 18 cm -3 , the doping element is aluminum to form a channel region;

[0061] An N+ region is formed in the epitaxial layer. The N+ region is located on the side of the P-well region away from the substrate, and the bottom of the N+ region contacts the top of the P-well region. There is no particular restriction on the specific process for forming the N+ region. For example, the N+ region is formed by a high-temperature ion implantation process at 500°C, with a junction depth of 0.1-0.4μm and a doping concentration of 5×10 18 cm -3 -5×10 20 cm -3 , the doping element is nitrogen;

[0062] A P+ region is formed in the epitaxial layer. The P+ region is located on a side of the P-well region away from the substrate, and the bottom of the P+ region contacts the top of the P-well region. The P+ regions are spaced apart in the N+ region in a first direction, or the P+ regions extend along the first direction, and the N+ regions are located on both sides of the P+ region. There is no particular restriction on the specific process for forming the P+ region. For example, the P+ region is formed by a high-temperature ion implantation process at 500°C, with a junction depth of 0.1-1.5 μm and a doping concentration of 5×10 18 cm -3 -5×10 20 cm -3 In the process of forming the N+ region and the P+ region, a photolithography process can be used to selectively cover a portion of the surface of the epitaxial layer with photoresist so as to form the N+ region and the P+ region by ion implantation.

[0063] In this step, referring to FIG12 , the method for forming a trench gate group and a plurality of shielding regions in the epitaxial layer includes steps S210 to S250:

[0064] S210: forming a first trench.

[0065] In this step, a first trench is formed. The first trench extends from the surface of the epitaxial layer away from the substrate into the epitaxial layer. The first trench penetrates the N+ region and the P-well region, and the first trench extends along a first direction. The specific process for forming the first trench is not particularly limited. For example, the first trench can be formed in the epitaxial layer by plasma etching. The width of the first trench can be 0.3-2 μm, and the depth of the first trench can be 0.4-2 μm.

[0066] This step can form a plurality of first trenches in the epitaxial layer that extend along a first direction and are sequentially arranged along a second direction, so as to subsequently form a plurality of trench gate groups. The second direction is a direction on the plane of the epitaxial layer that intersects the first direction. Specifically, the second direction can be perpendicular to the first direction.

[0067] This step may also include forming a plurality of third trenches extending along the second direction and arranged sequentially along the first direction when forming the first trench, so as to subsequently form a third trench gate, wherein the third trench gate and the first trench gate define a plurality of cells. The width and depth of the third trench may be respectively the same as the width and depth of the first trench. The specific process for forming the third trench is also not particularly limited. For example, the third trench may be formed in the epitaxial layer by plasma etching.

[0068] S220 : forming a plurality of second trenches in the first trench.

[0069] In this step, multiple second trenches are formed in the first trench, with the multiple second trenches spaced apart along the first direction. The width of the second trenches can be equal to or less than the width of the first trench, and the depth of the second trenches is not particularly limited. For example, the second trenches can extend into the substrate, or, when a buffer layer is provided between the substrate and the epitaxial layer, the second trenches can extend into the buffer layer or through the buffer layer into the substrate. This helps further reduce the resistance of the JFET region and improve the current density of the MOSFET.

[0070] The width of each portion of the second trench in the third direction (i.e., the direction in which the substrate and epitaxial layer overlap) can be uniform. Alternatively, the second trench can include multiple interconnected trench portions, with the multiple trench portions sequentially connected in the direction from the epitaxial layer toward the substrate and having successively decreasing widths, thereby forming a multi-level trench. The second trench formed by the multiple trench portions can extend into the buffer layer or penetrate the buffer layer and extend into the substrate.

[0071] The specific process for forming the second trench is not particularly limited. For example, a plurality of second trenches are formed in the first trench by plasma etching.

[0072] In other embodiments of the present invention, a plurality of third trenches are formed in the epitaxial layer. In this case, the second trench may be located below the intersection of the first trench and the third trench, or the second trench may be located between two adjacent third trenches.

[0073] S230: forming a plurality of shielding areas.

[0074] In this step, multiple shielding regions are formed. Each shielding region encompasses the bottom and all sidewalls of the second trench and extends toward the surface of the epitaxial layer away from the substrate to cover the sidewalls of the first trench. Because the second trenches are spaced apart along the first direction, the shielding regions can cover the sidewalls of the second trenches along the second direction as well as the sidewalls along the first direction, forming a three-dimensional shielding region.

[0075] The specific process for forming the shielding region is not particularly limited. For example, the shielding region can be formed by a high-temperature ion implantation process at 500°C with a doping concentration of 1×10 16 cm -3-1×10 19 cm -3 , the doping element is aluminum. It can reduce the electric field stress of the gate oxide layer in three dimensions. When the MOSFET is in the blocking state, the shielding area and the epitaxial layer are completely depleted, and the doping concentration of the epitaxial layer can be increased to 1×10 16 cm -3 -5×10 17 cm -3 , thereby increasing the current density of the MOSFET.

[0076] Since each shielding region wraps around the bottom and all side walls of the second trench and extends toward the surface of the epitaxial layer away from the substrate to cover the side walls of the first trench, the region where ions are implanted into the epitaxial layer covers the second trench and has a width greater than that of the first trench.

[0077] In this step, a high temperature annealing at 1600° C. to 1900° C. may be performed to activate the doping impurities in the P-well region, the P+ region, the N+ region, and the shielding region and to repair the crystal lattice.

[0078] In other embodiments of the present invention, multiple third trenches are formed in the epitaxial layer, and the second trench may be located below the intersection area of ​​the first trench and the third trench. In this case, each shielding region further covers the side wall of the third trench, or the second trench is located between two adjacent third trenches. In this case, each shielding region is located between two adjacent third trenches.

[0079] S240 : forming a gate oxide layer on the sidewalls and bottom of the first trench and the second trench.

[0080] In this step, a gate oxide layer is formed on the sidewalls and bottom of the first trench and the second trench. There is no particular restriction on the specific process for forming the gate oxide layer. For example, a gate oxide layer may be formed in the first trench and the second trench by thermal oxidation. Thick gate oxide layer.

[0081] This step may further include forming a gate oxide layer on the sidewalls and bottom of the third trench to facilitate subsequent formation of a third trench gate.

[0082] S250 : forming a gate layer in the first trench and the second trench.

[0083] In this step, a gate layer is formed in the first trench and the second trench. The gate layer contacts the gate oxide layer to form a first trench gate and a second trench gate, thereby forming a trench gate group. The specific process for forming the gate layer is not particularly limited. For example, polysilicon can be deposited on the gate oxide layer using low-pressure chemical vapor deposition to form a polysilicon gate.

[0084] This step may further include forming a gate layer in the third trench to form a third trench gate.

[0085] The method also includes depositing a 0.3-0.8 μm thick oxide layer on the polysilicon gate by plasma chemical vapor deposition to form an interlayer dielectric layer, and forming a gate-source contact hole in the interlayer dielectric layer by patterning;

[0086] Sputtering on the interlayer dielectric layer and epitaxial layer A thick nickel layer is annealed at 900-1100°C to form an ohmic contact between the nickel layer and the P+ and N+ regions. A 1-6 μm thick aluminum layer is deposited on the nickel layer to form a source electrode.

[0087] Metal Ti, Ni and Ag are sputtered in sequence on the side of the substrate away from the epitaxial layer to form a drain.

[0088] In the description of the present invention, the terms "first" and "second" are used for descriptive purposes only and should not be understood to indicate or imply relative importance or implicitly specify the number of the technical features indicated. Therefore, a feature specified as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the present invention, "plurality" means two or more, unless otherwise specifically defined.

[0089] In the description of this specification, the reference terms "one embodiment", "some embodiments", "example", "specific example", or "some examples" mean that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of this specification. In this specification, the schematic expressions of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described can be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art can combine and combine different embodiments or examples described in this specification and features of different embodiments or examples without contradiction.

[0090] Although the embodiments of the present invention have been shown and described above, it will be understood that the above embodiments are illustrative and are not to be construed as limitations on the present invention. A person skilled in the art may change, modify, replace and modify the above embodiments within the scope of the present invention.

[0091] Reference numerals:

[0092] 100: substrate; 200: epitaxial layer; 210: P-well region; 220: N+ region; 230: P+ region; 300: trench gate group; 310: first trench gate; 320: second trench gate; 321A / 321B: trench gate portion; 10: gate oxide layer; 20: gate layer; 400: shielding region; 500: source; 600: interlayer dielectric layer; 700: drain; 800: buffer layer; 900: third trench gate; D1: first direction; D2: second direction; D3: third direction.

Claims

1. A metal oxide semiconductor field effect transistor, wherein: include: substrate; an epitaxial layer, the epitaxial layer being disposed on the substrate; a trench gate group, the trench gate group comprising a first trench gate and a plurality of second trench gates, the first trench gate extending from a surface of the epitaxial layer away from the substrate into the epitaxial layer, and the first trench gate extending along a first direction in the plane of the epitaxial layer, the plurality of second trench gates being spaced apart along the first direction, the orthographic projection of the second trench gate on the substrate being within the orthographic projection of the first trench gate on the substrate, the top of the second trench gate contacting the bottom of the first trench gate, and the gate layer in the second trench gate being connected to the gate layer in the first trench gate; as well as A plurality of shielding regions, each of which wraps the bottom and all sidewalls of the second trench gate and extends toward the surface of the epitaxial layer away from the substrate to cover the sidewalls of the first trench gate, and the plurality of shielding regions are arranged at intervals.

2. The metal oxide semiconductor field effect transistor according to claim 1, wherein In the stacking direction of the substrate and the epitaxial layer, the second trench gate extends into the substrate; or, A buffer layer is provided between the substrate and the epitaxial layer. In the stacking direction of the substrate and the epitaxial layer, the second trench gate extends into the buffer layer or into the substrate.

3. The metal oxide semiconductor field effect transistor according to claim 1 or 2, wherein: The second trench gate includes a plurality of trench gate portions connected to each other. The plurality of trench gate portions are sequentially arranged in a direction from the epitaxial layer toward the substrate, and their widths decrease sequentially.

4. The metal oxide semiconductor field effect transistor according to claim 1, wherein The thickness of the shielding area covering the sidewall of the first trench gate is consistent with the thickness of the shielding area wrapping the sidewall of the second trench gate, and the thickness is 0.1-1μm. The thickness of the shielding area wrapping the bottom of the second trench gate is 0.5-2μm.

5. The metal oxide semiconductor field effect transistor according to claim 1, wherein The doping concentration of the shielding area is 1×10 16 cm -3 -1×10 19 cm -3 .

6. The metal oxide semiconductor field effect transistor according to claim 1, wherein It comprises a plurality of trench gate groups, wherein the first trench gates in the plurality of trench gate groups are sequentially arranged along a second direction in the plane where the epitaxial layer is located, the second direction intersects with the first direction, and in the second direction, two adjacent second trench gates are arranged in the same row or staggered rows.

7. The metal oxide semiconductor field effect transistor according to claim 1, wherein comprising a plurality of trench gate groups, wherein the first trench gates in the plurality of trench gate groups are sequentially arranged along a second direction on the plane where the epitaxial layer is located, and the second direction intersects with the first direction, The N+ region and the P+ region in the epitaxial layer extend from the surface of the epitaxial layer away from the substrate into the epitaxial layer, and the top of the P-well region in the epitaxial layer contacts the bottom of the N+ region and the bottom of the P+ region. The first trench gate penetrates the N+ region and the P well region, The P+ regions are arranged at intervals along the first direction and located between two adjacent first trench gates, and the N+ region is located around the P+ region. Alternatively, the P+ region extends along the first direction and is located between two adjacent first trench gates, and the N+ region is located on both sides of the P+ region.

8. The metal oxide semiconductor field effect transistor according to claim 1, wherein include: a plurality of trench gate groups, wherein the first trench gates in the plurality of trench gate groups are sequentially arranged along a second direction on a plane where the epitaxial layer is located, and the second direction intersects with the first direction; as well as a plurality of third trench gates extending along the second direction and sequentially arranged along the first direction, wherein the third trench gates extend from a surface of the epitaxial layer away from the substrate into the epitaxial layer; The orthographic projection of the second trench gate on the substrate is located within the orthographic projection range of the intersection region of the first trench gate and the third trench gate on the substrate, and each of the shielding regions further covers the sidewall of the third trench gate. Alternatively, the orthographic projection of the second trench gate on the substrate is located between the orthographic projections of two adjacent third trench gates on the substrate, and each of the shielding regions is located between two adjacent third trench gates.

9. The metal oxide semiconductor field effect transistor according to claim 8, wherein: The N+ region and the P+ region in the epitaxial layer extend from the surface of the epitaxial layer away from the substrate into the epitaxial layer, the top of the P-well region in the epitaxial layer contacts the bottom of the N+ region and the bottom of the P+ region, the first trench gate and the third trench gate both penetrate the N+ region and the P-well region, the P+ region is located in the area surrounded by the first trench gate and the third trench gate, and the N+ region is located around the P+ region.

10. The metal oxide semiconductor field effect transistor according to claim 8, wherein The third trench gate and the first trench gate define a plurality of cells, and the shape of the cells includes square, hexagon, octagon or circle.

11. A method for manufacturing a metal oxide semiconductor field effect transistor, wherein: include: forming an epitaxial layer on a substrate; A trench gate group and multiple shielding regions are formed in the epitaxial layer, the trench gate group includes a first trench gate and multiple second trench gates, the first trench gate extends from the surface of the epitaxial layer away from the substrate into the epitaxial layer, and the first trench gate extends along a first direction in the plane where the epitaxial layer is located, and the multiple second trench gates are arranged at intervals along the first direction, the orthographic projection of the second trench gate on the substrate is located within the orthographic projection range of the first trench gate on the substrate, the top of the second trench gate contacts the bottom of the first trench gate, and the gate layer in the second trench gate is connected to the gate layer in the first trench gate, each of the shielding regions wraps the bottom and all sidewalls of the second trench gate, and extends toward the surface of the epitaxial layer away from the substrate to cover the sidewalls of the first trench gate, and the multiple shielding regions are arranged at intervals.

12. The method according to claim 11, wherein Forming a trench gate group and a plurality of shielding regions in the epitaxial layer includes: A first trench is formed, wherein the first trench extends from a surface of the epitaxial layer away from the substrate to the epitaxial layer. layer, and the first groove extends along the first direction; forming a plurality of second grooves in the first groove, wherein the plurality of second grooves are arranged at intervals along the first direction; forming a plurality of shielding regions, each of which wraps around the bottom and all sidewalls of the second trench and extends toward the surface of the epitaxial layer away from the substrate to cover the sidewalls of the first trench; forming a gate oxide layer on the sidewalls and bottoms of the first trench and the second trench; A gate layer is formed in the first trench and the second trench, wherein the gate layer contacts the gate oxide layer, and the first trench gate and the second trench gate are formed to form the trench gate group.

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