Storage apparatus and data read method therefor, and electronic device

Abstract

The present disclosure relates to a storage apparatus and a data read method therefor, and an electronic device. The storage apparatus comprises a plurality of storage units (U); word lines (WL), which extend in a first direction and are connected to first electrodes (11) of storage units (U) in corresponding rows; bit lines (BL), which extend in a second direction and are connected to second electrodes (12) of storage units (U) in corresponding columns; and a read / write controller (2), which is connected to the word lines (WL) and the bit lines (BL), and is configured to set the voltage of each word line (WL) to a first initial voltage, set the voltage of each bit line (BL) to a second initial voltage, set the voltage of a selected bit line (BL) to a first selected voltage, connect the selected bit line (BL) to an induction amplifier (24), and set the voltage of a selected word line (WL) to a second selected voltage, such that the induction amplifier (24) outputs a data read signal on the basis of whether charge transfer has occurred on the bit line (BL), wherein the data read signal is used for representing data stored in the storage units (U).

Description

Storage device, data reading method thereof, and electronic device

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This disclosure claims priority to a Chinese patent application filed with the Patent Office of China on March 20, 2024, with application number 202410317881.3 and invention name “Storage device, data reading method thereof, and electronic device”. The entire contents of the patent application are incorporated into this disclosure by reference. Technical Field

[0003] The present disclosure relates to the field of storage technology, and in particular to a storage device and a data reading method thereof, and an electronic device. Background Art

[0004] With the development of communication and digital technologies, people continue to pursue products with lower power consumption, lighter weight, and better performance. Storage devices, such as random access memory (RAM), disks, and flash memory, are widely used in electronic devices as memory devices that can store information.

[0005] Summary of the Invention

[0006] According to some embodiments, the present disclosure provides a storage device on one hand, comprising: a memory cell array, a plurality of word lines, a plurality of bit lines, and a read-write controller. The memory cell array comprises: a plurality of memory cells arranged in rows along a first direction and arranged in columns along a second direction. The memory cell comprises a first electrode, a second electrode, and a dielectric layer disposed between the first electrode and the second electrode. The first direction and the second direction intersect. The word lines extend along the first direction and connect the first electrodes of the memory cells in the corresponding rows. The bit lines extend along the second direction and connect the second electrodes of the memory cells in the corresponding columns. The read-write controller is connected to the word lines and the bit lines, and is configured to: set the voltage of each word line to a first initial voltage, and set the voltage of each bit line to a second initial voltage; set the voltage of the selected bit line to a first selected voltage, and connect the selected bit line to a sense amplifier; set the voltage of the selected word line to a second selected voltage, so that the sense amplifier outputs a data read signal based on whether charge transfer occurs on the bit line; the data read signal is used to represent the data stored in the memory cell.

[0007] According to some embodiments, the read / write controller is further configured to: perform a recovery write operation on the memory cell after the charge on the bit line is transferred and the sense amplifier outputs the data read signal, so as to restore the read data in the memory cell.

[0008] According to some embodiments, the memory cell comprises a ferroelectric memory cell; and the dielectric layer comprises a ferroelectric dielectric layer.

[0009] According to some embodiments, a read / write controller includes: a control module, a wordline selection circuit, a bitline selection circuit, and a sense amplifier. The wordline selection circuit is connected to the control module and each wordline, and is configured to: provide a first initial voltage to each wordline in response to a first control instruction from the control module, and to provide a second selected voltage to a selected wordline in response to a third control instruction from the control module. The bitline selection circuit is connected to the control module and each bitline, and is configured to: provide a second initial voltage to each bitline in response to a first control instruction from the control module, and to provide the first selected voltage to a selected bitline in response to a second control instruction from the control module. The sense amplifier is connected to the control module and the bitline selection circuit, and is configured to: connect the selected bitline in response to the second control instruction from the control module, and to output a data read signal after the voltage of the selected wordline is set to the second selected voltage. The first, second, and third control instructions are generated sequentially.

[0010] According to some embodiments, a sense amplifier includes a charge integrator and a secondary amplifier. The charge integrator is configured to, after a selected bit line is turned on, measure the total amount of charge flowing into or out of the selected bit line at a first selected voltage, and convert the total charge into a voltage signal as an initial read signal. The secondary amplifier is connected to an output terminal of the charge integrator and configured to compare the initial read signal with a reference signal and output a data read signal based on the comparison result.

[0011] According to some embodiments, a charge integrator includes: an operational amplifier and a feedback capacitor. The operational amplifier has a first input terminal, a second input terminal, and an output terminal; the first input terminal is connected to a preset voltage terminal; the second input terminal is configured to connect to the selected bit line and precharge to a preset voltage during a data read phase; the output terminal is configured to output the initial read signal during the data read phase. The feedback capacitor has a first electrode and a second electrode; the first electrode of the feedback capacitor is connected to the second input terminal of the operational amplifier, and the second electrode of the feedback capacitor is connected to the output terminal of the operational amplifier.

[0012] According to some embodiments, the preset voltage of the second input terminal after precharging is the same as the preset voltage of the preset voltage terminal to which the first input terminal is connected.

[0013] According to some embodiments, the preset voltage after the second input terminal is pre-charged is the first selected voltage.

[0014] According to some embodiments, the second input terminal is connected to the selected bit line through the bit line selection circuit.

[0015] According to some embodiments, the secondary amplifier comprises a latch amplifier.

[0016] According to some embodiments, the second selected voltage is a reference voltage.

[0017] Accordingly, in some examples, the first initial voltage is the sum of the reference voltage and two-thirds of the rated voltage; the second initial voltage is the sum of the reference voltage and one-third of the rated voltage; and the first selected voltage is the sum of the reference voltage and the rated voltage.

[0018] Accordingly, in other examples, the first initial voltage is the difference between the reference voltage and two-thirds of the rated voltage; the second initial voltage is the difference between the reference voltage and one-third of the rated voltage; and the first selected voltage is the difference between the reference voltage and the rated voltage.

[0019] According to some embodiments, the rated voltage comprises a maximum supply voltage.

[0020] According to some embodiments, the present disclosure further provides a data reading method for a storage device, which is applied to the storage device as described in any of the above embodiments. The data reading method includes the following steps.

[0021] The voltage of each word line is set to a first initial voltage, and the voltage of each bit line is set to a second initial voltage.

[0022] The voltage of the selected bit line is set to a first selected voltage, and the selected bit line is connected to the sense amplifier.

[0023] The voltage of the selected word line is set to a second selected voltage.

[0024] The sense amplifier outputs a data read signal according to whether charge transfer occurs on the bit line. The data read signal is used to represent data stored in the memory cell.

[0025] According to some embodiments, the data reading method of the memory device further includes: performing a recovery write operation on the memory cell to restore the read data in the memory cell after the charge on the bit line is transferred and the sense amplifier outputs the data read signal.

[0026] According to some embodiments, the data reading method of a memory device further includes initializing the sense amplifier while turning on the selected bit line to connect the sense amplifier.

[0027] According to some embodiments, the sense amplifier includes a charge integrator and a secondary amplifier connected to an output terminal of the charge integrator. The sense amplifier outputs a data read signal based on whether charge transfer occurs on the bit line, including: after the charge integrator connects to the selected bit line, measuring the total amount of charge flowing into or out of the bit line at the first selected voltage, and converting the total amount of charge into a voltage signal as an initial read signal; and the secondary amplifier compares the initial read signal with a reference signal to output a data read signal based on the comparison result between the initial read signal and the reference signal.

[0028] According to some embodiments, initializing the sense amplifier includes: pre-charging the charge integrator.

[0029] Correspondingly, when the voltage of the selected word line is set to the second selected voltage, the data reading method further includes: disconnecting the pre-charging circuit of the charge integrator.

[0030] According to some embodiments, the second selected voltage is a reference voltage.

[0031] Accordingly, in some examples, the first initial voltage is the sum of the reference voltage and two-thirds of the rated voltage; the second initial voltage is the sum of the reference voltage and one-third of the rated voltage; and the first selected voltage is the sum of the reference voltage and the rated voltage.

[0032] Accordingly, in other examples, the first initial voltage is the difference between the reference voltage and two-thirds of the rated voltage; the second initial voltage is the difference between the reference voltage and one-third of the rated voltage; and the first selected voltage is the difference between the reference voltage and the rated voltage.

[0033] According to some embodiments, the rated voltage comprises a maximum supply voltage.

[0034] According to some embodiments, the present disclosure further provides an electronic device on another aspect, including: a storage device as described in any of the above embodiments.

[0035] The details of one or more embodiments of the present disclosure are set forth in the accompanying drawings and the description below. Other features, objects, and advantages of the present disclosure will become apparent from the description, drawings, and claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present disclosure. For ordinary technicians in this field, without paying any creative work, they can also obtain drawings of other embodiments based on these drawings.

[0037] FIG1 is a schematic structural diagram of a storage device provided in some embodiments of the present disclosure;

[0038] FIG2 is a schematic structural diagram of a sensing amplifier provided in some embodiments of the present disclosure;

[0039] FIG3 is a schematic structural diagram of a charge integrator provided in some embodiments of the present disclosure;

[0040] FIG4 is a schematic flow chart of a method for reading data from a storage device provided in some embodiments of the present disclosure;

[0041] FIG5 is a schematic flow chart of another method for reading data from a storage device provided in some embodiments of the present disclosure;

[0042] FIG6 is a flow chart of step S400 provided in some embodiments of the present disclosure. DETAILED DESCRIPTION

[0043] To facilitate understanding of the present disclosure, a more comprehensive description of the present disclosure will be provided below with reference to the accompanying drawings. The drawings illustrate embodiments of the present disclosure. However, the present disclosure can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided to provide a more thorough and comprehensive understanding of the present disclosure.

[0044] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art in the art of the present disclosure. The terms used herein in the specification of the present disclosure are only for the purpose of describing specific embodiments and are not intended to limit the present disclosure.

[0045] References to "embodiments" herein mean that a particular feature, structure, or characteristic described in connection with the embodiments may be included in at least one embodiment of the present disclosure. The appearance of this phrase in various places in the specification does not necessarily refer to the same embodiment, nor does it constitute an independent or alternative embodiment that is mutually exclusive of other embodiments. It is understood, both explicitly and implicitly, by those skilled in the art that the embodiments described herein may be combined with other embodiments.

[0046] It is understood that the terms "first," "second," etc., used herein may be used to describe various elements, but these elements are not limited by these terms. These terms are only used to distinguish a first element from another element. For example, a first electrode may be referred to as a second electrode, and similarly, a second electrode may be referred to as a first electrode without departing from the scope of this application. The first electrode and the second electrode are both electrodes, but they are not the same electrode.

[0047] It can be understood that the "coupling" and "connection" in the following embodiments should be understood as "electrical connection", "communication connection", etc. if the coupled or connected circuits, modules, units, etc. have electrical signals or data transmission with each other.

[0048] As used herein, the singular forms "a," "an," and "the" may also include the plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "include," "comprising," "having," and the like specify the presence of stated features, integers, steps, operations, components, parts, or combinations thereof, but do not preclude the presence or addition of one or more other features, integers, steps, operations, components, parts, or combinations thereof. Furthermore, the term "and / or" as used in this specification includes any and all combinations of the relevant listed items.

[0049] Semiconductor memory devices are memory devices implemented based on semiconductor materials such as silicon (Si), germanium (Ge), gallium arsenide (GaAs), or indium phosphide (InP). Semiconductor memory devices can be mainly divided into volatile memory devices and non-volatile memory devices. Among them, volatile memory devices are memory devices in which the data stored therein is lost when the power is disconnected. Examples of volatile memory devices include static random access memory (SRAM), dynamic random access memory (DRAM), and synchronous dynamic random access memory (SDRAM). Non-volatile memory devices are memory devices that can retain the data stored therein even when the power is disconnected. Examples of non-volatile memory devices include read-only memory (ROM), programmable read-only memory (PROM), electrically programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), NAND flash memory, NOR flash memory, phase change random access memory (PRAM), magnetic random access memory (MRAM), resistive random access memory (RRAM), ferroelectric random access memory (FRAM), etc.

[0050] In some embodiments, taking a ferroelectric random access memory (FRAM) as an example, FRAM primarily forms non-volatile memory by applying a voltage to change the polarization direction of the ferroelectric dielectric in its capacitor. Therefore, data reading in FRAM is generally a destructive read, that is, applying a sufficiently high voltage to the capacitor, if the polarization direction of the ferroelectric dielectric is opposite to the voltage direction, will cause the polarization direction of the ferroelectric dielectric to flip, thereby generating a transient current for charge transfer, and thereby reading the stored data in the FRAM. Furthermore, if the polarization direction of the ferroelectric dielectric flips, a reverse voltage must be applied after the data is read to restore the destroyed stored data.

[0051] Based on this, in ferroelectric memory cells with select transistors, such as a single-transistor single-ferroelectric capacitor (1T1C) memory cell, the transistor in the ferroelectric memory cell can be turned on via a word line to implement a read operation after connecting the data read circuit. However, in ferroelectric memory cells without select transistors, such as a single-transistor ferroelectric capacitor (0T1C) memory cell, how to arrange the timing to ensure that the polarization reversal of the ferroelectric dielectric in the ferroelectric memory cell can be effectively detected while not affecting unselected ferroelectric memory cells remains a problem that needs to be solved.

[0052] In summary, the embodiments of the present disclosure provide a storage device and a data reading method thereof, as well as an electronic device, which can ensure and improve the accuracy of reading stored data without a selection transistor, and effectively improve the performance of the storage device and the electronic device.

[0053] Referring to FIG. 1 , a memory device provided in an embodiment of the present disclosure includes: a memory cell array, a plurality of word lines WL, a plurality of bit lines BL, and a read / write controller 2. The memory cell array includes: a plurality of memory cells U arranged in rows along a first direction (e.g., the X direction) and arranged in columns along a second direction (e.g., the Y direction). The first direction (e.g., the X direction) and the second direction (e.g., the Y direction) intersect, for example, are orthogonal. The memory cell U includes a first electrode 11, a second electrode 12, and a dielectric layer 13 disposed between the first electrode 11 and the second electrode 12. That is, the memory cell U mentioned in the embodiment of the present disclosure is a zero-transistor single capacitor (0T1C) memory cell.

[0054] By way of example, the memory cell U is a ferroelectric memory cell, and its dielectric layer 13 is a ferroelectric dielectric layer.

[0055] Illustratively, the materials of the first electrode 11 and the second electrode 12 include metals, such as titanium, titanium nitride, tantalum nitride, platinum, copper, tungsten, titanium tungsten, tungsten nitride and / or ruthenium, as well as other conductive materials and / or combinations thereof.

[0056] By way of example, the material of the ferroelectric dielectric layer includes, but is not limited to, hafnium zirconium oxide (HfZrO, also known as HZO, which includes hafnium, zirconium and oxygen), silicon-doped (Si-doped) hafnium oxide (material containing hafnium, oxygen and silicon), germanium-doped (Ge-doped) hafnium oxide (material containing hafnium, oxygen and germanium), aluminum-doped (Al-doped) hafnium oxide (material containing hafnium, oxygen and aluminum), yttrium-doped (Y-doped) hafnium oxide (material containing hafnium, oxygen and yttrium), lead zirconium titanate (material containing hafnium, including lead, zirconium and titanium), barium zirconium titanate (material containing barium, zirconium and titanium) and combinations thereof.

[0057] For example, the first direction (e.g., X direction) and the second direction (e.g., Y direction) are both parallel to the substrate. The plurality of memory cells U included in the memory cell array can not only be distributed in a two-dimensional single layer along the first direction (e.g., X direction) and the second direction (e.g., Y direction), but can also be stacked along a third direction perpendicular to the substrate (e.g., Z direction, not shown in FIG1 ) to present a three-dimensional multi-layer distribution.

[0058] 1 , the first direction (e.g., X direction) and the second direction (e.g., Y direction) are both parallel to and orthogonal to the substrate. A memory cell U is provided at the intersection of the orthogonal projections of any word line WL and bit line BL in a third direction perpendicular to the substrate.

[0059] In some embodiments of the present disclosure, referring to FIG. 1 , word lines WL extend along a first direction (e.g., the X direction) and connect to first electrodes 11 of memory cells U in corresponding rows. Bit lines BL extend along a second direction (e.g., the Y direction) and connect to second electrodes 12 of memory cells U in corresponding columns. A read / write controller 2 is connected to the word lines WL and the bit lines BL and is configured to: set the voltage of each word line WL to a first initial voltage and the voltage of each bit line BL to a second initial voltage; set the voltage of a selected bit line BL to a first selected voltage and connect the selected bit line BL to a sense amplifier 24; set the voltage of the selected word line WL to a second selected voltage so that the sense amplifier 24 outputs a data read signal based on whether charge transfer occurs on the bit line BL; the data read signal is used to represent the data stored in the memory cell U.

[0060] In the disclosed embodiment, a memory cell array is constructed using transistor-free memory cells U. Word lines WL are used to connect the first electrodes 11 of each memory cell U in a corresponding row, and bit lines BL are used to connect the second electrodes 12 of each memory cell U in a corresponding column. This eliminates the need for a select transistor in each memory cell U, significantly improving storage density. Furthermore, in the disclosed embodiment, a read / write controller 2 connected to the word lines WL and bit lines BL can first set the voltage of each word line WL to a first initial voltage, the voltage of each bit line BL to a second initial voltage, then set the voltage of the selected bit line BL to a first selected voltage, connect the selected bit line BL to a sense amplifier 24, and finally set the voltage of the selected word line WL to a second selected voltage, causing the sense amplifier 24 to output a data read signal based on whether charge transfer occurs on the bit line BL. In other words, the disclosed embodiment effectively implements data reading from the storage device by controlling the timing of the voltages transmitted by each word line WL and each bit line BL through the read / write controller 2, while reducing the risk of misreading or missing data from the memory cells U. In this way, the embodiments of the present disclosure can ensure and improve the reading accuracy of stored data without a selection transistor, thereby effectively improving the performance of the storage device and the electronic device.

[0061] It can be understood that when the memory cell U is a ferroelectric memory cell, when writing data "1" or data "0", the dielectric layer 13 (i.e., the ferroelectric material) in the ferroelectric memory cell will exhibit different polarization states accordingly: for example, when writing data "1", the dielectric layer 13 in the ferroelectric memory cell is in a first polarization state; for example, when writing data "0", the dielectric layer 13 in the ferroelectric memory cell is in a second polarization state. The first polarization state of the dielectric layer 13 can be reversed to the second polarization state under the action of an external electric field, and the second polarization state of the dielectric layer 13 can be reversed to the first polarization state under the action of an external electric field. The second polarization state is, for example, the initial polarization state of the ferroelectric material.

[0062] Accordingly, the voltage difference between the second selected voltage and the first selected voltage can be used to invert one polarization state of the dielectric layer 13 in the ferroelectric memory cell, while the other polarization state remains unchanged.

[0063] For example, the voltage difference between the second selected voltage and the first selected voltage can be used to invert the first polarization state of the dielectric layer 13 while keeping the second polarization state of the dielectric layer 13 unchanged. In this way, after the first selected voltage is provided to the selected bit line BL and the second selected voltage is provided to the selected word line WL, if the data stored in the ferroelectric memory cell is "1", the first polarization state of the dielectric layer 13 in the ferroelectric memory cell can be inverted to the second polarization state; if the data stored in the ferroelectric memory cell is "0", the second polarization state of the dielectric layer 13 in the ferroelectric memory cell remains unchanged.

[0064] On the contrary, for example, the voltage difference between the second selected voltage and the first selected voltage can be used to invert the second polarization state of the dielectric layer 13 while maintaining the first polarization state of the dielectric layer 13 unchanged. In this way, after the first selected voltage is provided to the selected bit line BL and the second selected voltage is provided to the selected word line WL, if the data stored in the ferroelectric memory cell is "0", the second polarization state of the dielectric layer 13 in the ferroelectric memory cell can be inverted to the first polarization state; if the data stored in the ferroelectric memory cell is "1", the first polarization state of the dielectric layer 13 in the ferroelectric memory cell remains unchanged.

[0065] It should be added that, in some embodiments, the read / write controller 2 is further configured to: perform a recovery write operation on the memory cell U after the charge on the bit line BL is transferred and the sense amplifier 24 outputs a data read signal, so as to restore the read data in the memory cell U.

[0066] Here, it can be understood that if the charge on the bit line BL undergoes charge transfer, it means that the data originally written in the memory cell U has been lost during the reading process. The embodiment of the present disclosure performs a recovery write operation on the memory cell U, which facilitates repeated reading of the stored data.

[0067] In some embodiments, referring again to FIG. 1 , the read / write controller 2 includes a control module 21, a word line selection circuit 22, a bit line selection circuit 23, and a sense amplifier 24. The word line selection circuit 22 is connected to the control module 21 and each word line WL and is configured to provide a first initial voltage to each word line WL in response to a first control instruction from the control module 21 and to provide a second selected voltage to a selected word line WL in response to a third control instruction from the control module 21. The bit line selection circuit 23 is connected to the control module 21 and each bit line BL and is configured to provide a second initial voltage to each bit line BL in response to a first control instruction from the control module 21 and to provide the first selected voltage to a selected bit line BL in response to a second control instruction from the control module 21. The sense amplifier 24 is connected to the control module 21 and the bit line selection circuit 23 and is configured to connect the selected bit line BL in response to the second control instruction from the control module 21 and to output a data read signal after the voltage of the selected word line WL is set to the second selected voltage. The first, second, and third control instructions are generated sequentially.

[0068] For example, the control module 21 includes but is not limited to a logic control chip.

[0069] For example, the word line selection circuit 22 and the bit line selection circuit 23 are disposed on the periphery of the memory cell array. For example, the word line selection circuit 22 and the bit line selection circuit 23 can be disposed on two sides of the memory cell array, including two opposite sides or two adjacent sides. The present disclosure does not specifically limit the circuit structure of the word line selection circuit 22 and the bit line selection circuit 23, so long as they can achieve the aforementioned functions. The word line selection circuit 22 and the bit line selection circuit 23 can, for example, be formed by connecting multiplexer transistors.

[0070] Illustratively, the sense amplifier 24 is initialized while the selected bit line is turned on.

[0071] For example, referring to FIG. 2 , the sense amplifier 24 includes a charge integrator 241 and a secondary amplifier 242. The charge integrator 241 is configured to, after the selected bit line BL is turned on, measure the total amount of charge flowing into or out of the selected bit line BL at a first selected voltage, and convert the total amount of charge into a voltage signal as an initial read signal. Here, the first selected voltage is a stable voltage applied to the selected bit line BL; and the total amount of charge on the bit line BL can be effectively sensed after a second selected voltage is applied to the selected word line WL. The secondary amplifier 242 is connected to the output of the charge integrator 241 and is configured to compare the initial read signal with a reference signal to output a data read signal based on the comparison result between the initial read signal and the reference signal.

[0072] In the embodiment of the present disclosure, a charge integrator 241 and a secondary amplifier 242 are provided in the sense amplifier 24. The charge integrator 241 can be used to obtain an initial read signal via the selected bit line BL. Specifically, after connecting the selected bit line BL, the charge integrator 241 can measure the total amount of charge flowing into or out of the selected bit line BL at a first selected voltage, and then convert the total charge into a voltage signal (i.e., a read sense signal) as the initial read signal. Subsequently, the embodiment of the present disclosure can output a data read signal based on the comparison result of the initial read signal and a reference signal via the secondary amplifier 242 to read the data stored in the memory cell U. Due to the above data reading process of the embodiment of the present disclosure, there is no need for the bit line BL to float during the data reading stage, which can prevent the charge change generated by the storage unit U from being shared by the parasitic capacitance of the bit line BL and related circuits such as the peripheral circuit (that is, the parasitic capacitance on the reading path of the storage unit U will not absorb and release charge). Therefore, it will not cause too much voltage change on the selected bit line BL connected to the charge integrator 241 and the reading path of the entire storage unit U, and can effectively avoid significant attenuation or decay of the signal, which is beneficial to improving the accuracy of storing data reading and enhancing the performance of storage devices and electronic devices.

[0073] In some examples, referring to FIG. 3 , the charge integrator 241 includes an operational amplifier 411 and a feedback capacitor 412. The operational amplifier 411 has a first input terminal Input1, a second input terminal Input2, and an output terminal Output. The feedback capacitor 412 has a first electrode and a second electrode; the first electrode of the feedback capacitor 412 is connected to the second input terminal Input2 of the operational amplifier 411, and the second electrode of the feedback capacitor 412 is connected to the output terminal Output of the operational amplifier 411. The first input terminal Input1 is connected to a preset voltage terminal; the second input terminal Input2 is configured to connect to the selected bit line BL and precharge to a preset voltage during the data reading phase; and the output terminal Output is configured to output an initial read signal during the data reading phase.

[0074] For example, the preset voltage of the second input terminal Input2 after pre-charging is the same as the preset voltage of the preset voltage terminal connected to the first input terminal Input1. The operation of the operational amplifier 411 can basically lock the voltage of the second input terminal Input2 to the preset voltage.

[0075] For example, the preset voltage of the second input terminal Input2 after pre-charging is the first selected voltage.

[0076] For example, the second input terminal Input2 is connected to the selected bit line BL through the bit line selection circuit 23 .

[0077] For example, the initialization of the sense amplifier 24 is achieved by initializing the charge integrator 241. The initialization of the charge integrator 241 can be performed as precharging, that is, the initialization of the charge integrator 241 can be achieved by a correspondingly connected precharging circuit. Accordingly, when the voltage of the selected word line WL is set to the second selected voltage, the precharging circuit of the charge integrator 241 also needs to be disconnected. The embodiment of the present disclosure does not specifically limit the circuit design of the aforementioned precharging circuit, so long as it can achieve the aforementioned functions. Optionally, the precharging circuit can be a switching device or other circuit structure connected to a power supply voltage terminal, and the power supply voltage terminal is used to provide a rated high-level voltage.

[0078] In some examples, the secondary amplifier 242 includes but is not limited to a latch amplifier. The circuit design of the secondary amplifier 242 is such that after comparing the initial read signal with the reference signal, it can effectively output a data read signal according to the comparison result between the initial read signal and the reference signal.

[0079] It should be noted that in some embodiments, the initial read signal output by the charge integrator 241 is a voltage signal. Accordingly, the reference signal used in the secondary amplifier 242 for comparison with the initial read signal can use a voltage threshold. In this way, the secondary amplifier 242 can conveniently convert the initial read signal to a high level representing data "1" or a low level representing data "0" based on whether the voltage of the initial read signal crosses the set voltage threshold, thereby simplifying the circuit design of the secondary amplifier 242.

[0080] It is worth mentioning that the aforementioned first initial voltage, second initial voltage, first selected voltage and second selected voltage can all be set to match the requirements. The embodiments of the present disclosure provide some possible implementation schemes by way of example, but are not limited thereto.

[0081] In some embodiments, the second selected voltage provided to the selected word line WL is used as the reference voltage V1. Accordingly, the first initial voltage, the second initial voltage, and the first selected voltage can all be set to match the reference voltage V1.

[0082] In some examples, the first initial voltage V2 is the sum of the reference voltage V1 and two-thirds of the rated voltage Vdd; that is, The second initial voltage V3 is the sum of the reference voltage V1 and one-third of the rated voltage Vdd; that is: The first selected voltage V4 is the sum of the reference voltage V1 and the rated voltage Vdd; that is, V4 = V1 + Vdd.

[0083] In some other examples, the first initial voltage V2 is the difference between the reference voltage V1 and two-thirds of the rated voltage Vdd; that is: The second initial voltage V3 is the difference between the reference voltage V1 and one-third of the rated voltage Vdd; that is: The first selected voltage V4 is the difference between the reference voltage V1 and the rated voltage Vdd; that is, V4 = V1 - Vdd.

[0084] For example, the rated voltage Vdd may be set to match the requirement, such as the maximum power supply voltage.

[0085] In the embodiment of the present disclosure, the first initial voltage, the second initial voltage, the first selected voltage and the second selected voltage adopt the above scheme, which can make the first initial voltage, the second initial voltage and the first selected voltage respectively present different voltage bias states when the second selected voltage is used as the reference voltage V1, which is beneficial to ensure that the selected memory cell U can have a larger read sensing margin and effectively reduce the voltage disturbance of the selected memory cell U to its adjacent memory cell U, thereby further improving the data reading accuracy of the memory cell U without the selection transistor.

[0086] Some embodiments of the present disclosure also provide a method for reading data from a storage device, which can be applied to the storage device described in any of the above embodiments. The data reading method of the storage device also has the technical advantages of the aforementioned storage device, which will not be described in detail here.

[0087] In some embodiments, referring to FIG. 4 , a method for reading data from a storage device includes the following steps S100 - S400 .

[0088] S100 , setting the voltage of each word line to a first initial voltage, and setting the voltage of each bit line to a second initial voltage.

[0089] S200 , setting the voltage of the selected bit line to a first selected voltage, and connecting the selected bit line to a sense amplifier.

[0090] S300 , setting the voltage of the selected word line to a second selected voltage.

[0091] S400 , the sense amplifier outputs a data read signal according to whether charge transfer occurs on the bit line, where the data read signal is used to represent data stored in the memory cell.

[0092] Illustratively, the memory cell is a ferroelectric memory cell.

[0093] In some embodiments, referring to FIG. 5 , the data reading method of the storage device further includes step S500 .

[0094] S500 , after the charge on the bit line is transferred and the sense amplifier outputs a data read signal, a recovery write operation is performed on the memory cell to restore the read data in the memory cell.

[0095] In the embodiment of the present disclosure, if charge transfer occurs on the bit line, it indicates that the data written in the original storage unit has been lost during the reading process. The embodiment of the present disclosure performs a recovery write operation on the storage unit, which facilitates the repeated reading of the stored data.

[0096] In some embodiments, please continue to refer to FIG. 5 , step S200 further includes: initializing the sense amplifier while the selected bit line is connected to the sense amplifier.

[0097] Here, the initialization of the sense amplifier can be performed with reference to the aforementioned related records and will not be described in detail.

[0098] It is worth mentioning that the aforementioned first initial voltage, second initial voltage, first selected voltage and second selected voltage can all be set to match the requirements. The embodiments of the present disclosure provide some possible implementation schemes by way of example, but are not limited thereto.

[0099] In some embodiments, the second selected voltage provided to the selected word line WL is used as the reference voltage V1. Accordingly, the first initial voltage, the second initial voltage, and the first selected voltage can be set to match the reference voltage V1.

[0100] In some examples, the first initial voltage V2 is the sum of the reference voltage V1 and two-thirds of the rated voltage Vdd; that is, The second initial voltage V3 is the sum of the reference voltage V1 and one-third of the rated voltage Vdd; that is: The first selected voltage V4 is the sum of the reference voltage V1 and the rated voltage Vdd; that is, V4 = V1 + Vdd.

[0101] In some other examples, the first initial voltage V2 is the difference between the reference voltage V1 and two-thirds of the rated voltage Vdd; that is: The second initial voltage V3 is the difference between the reference voltage V1 and one-third of the rated voltage Vdd; that is: The first selected voltage V4 is the difference between the reference voltage V1 and the rated voltage Vdd; that is, V4 = V1 - Vdd.

[0102] For example, the rated voltage Vdd may be set to match the requirement, such as the maximum power supply voltage.

[0103] In the embodiment of the present disclosure, the first initial voltage, the second initial voltage, the first selected voltage and the second selected voltage adopt the above scheme, which can make the voltages corresponding to the first initial voltage, the second initial voltage and the first selected voltage respectively present different voltage bias states when the second selected voltage is used as the reference voltage, which is beneficial to ensure that the selected memory cell U can have a larger read sensing margin and effectively reduce the voltage disturbance of the selected memory cell U to its adjacent memory cell U, thereby further improving the data reading accuracy of the memory cell U without the selection transistor.

[0104] It should be supplemented that, in conjunction with Figure 2 and Figure 6 , in some embodiments, the sense amplifier 4 includes: a charge integrator 241 and a secondary amplifier 242. Accordingly, step S400 may include the following steps S410 and S420.

[0105] S410 , after connecting the selected bit line, the charge integrator measures the total amount of charge flowing into or out of the bit line at a first selected voltage, and converts the total amount of charge into a voltage signal as an initial read signal.

[0106] S420 , the secondary amplifier compares the initial read signal with a reference signal to output a data read signal according to a comparison result between the initial read signal and the reference signal.

[0107] Here, the data read signal is used to represent the data stored in the memory unit U.

[0108] In the embodiment of the present disclosure, the charge integrator can measure the total amount of charge flowing into or out of the selected bit line under the first selected voltage, and then convert the total amount of charge into a voltage signal (i.e., a read sensing signal) as an initial read signal; the secondary comparator can output a data read signal based on the comparison result of the initial read signal and the reference signal to read out the data stored in the storage cell. Since the above data reading process of the embodiment of the present disclosure does not require the bit line to float during the data reading phase, it can avoid that the charge change generated by the storage cell will be shared by the parasitic capacitance of the bit line and related circuits such as the peripheral circuit (i.e., the parasitic capacitance on the storage cell reading path will not absorb and release charge), so it will not cause too much voltage change on the selected bit line connected to the charge integrator and the reading path of the entire storage cell, which can effectively avoid significant attenuation or attenuation of the signal, thereby helping to improve the accuracy of reading the stored data and thus enhance the performance of the storage device and electronic device.

[0109] Some embodiments of the present disclosure further provide an electronic device, such as a data storage device, a copier, a network device, a household appliance, an instrument, a mobile phone, a computer, or other device with a data storage function. The electronic device may include the storage device described in some of the aforementioned embodiments. The electronic device may also include other necessary elements or components, which are not limited in the embodiments of the present disclosure.

[0110] The technical features of the above-mentioned embodiments can be combined arbitrarily. To make the description concise, not all possible combinations of the technical features of the above-mentioned embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0111] The above-described embodiments merely represent several implementation methods of the present disclosure. While the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent application. It should be noted that a person of ordinary skill in the art may make various modifications and improvements without departing from the spirit of the present disclosure, all of which fall within the scope of protection of the present disclosure. Therefore, the scope of protection of the patent disclosed herein shall be determined by the appended claims.

Claims

1. A storage device comprising: A memory cell array comprising: a plurality of memory cells arranged in rows along a first direction and in columns along a second direction; the memory cells comprising a first electrode, a second electrode, and a dielectric layer disposed between the first electrode and the second electrode; the first direction and the second direction intersecting; A plurality of word lines; the word lines extend along the first direction and connect the first electrodes of the memory cells in the corresponding row; A plurality of bit lines; the bit lines extend along the second direction and connect the second electrodes of the memory cells in the corresponding columns; A read / write controller is connected to the word line and the bit line and is configured to: Setting the voltage of each word line to a first initial voltage and setting the voltage of each bit line to a second initial voltage; Setting the voltage of the selected bit line to a first selected voltage, and connecting the selected bit line to a sense amplifier; The voltage of the selected word line is set to a second selected voltage so that the sense amplifier outputs a data read signal according to whether charge transfer occurs on the bit line; the data read signal is used to represent the data stored in the memory cell.

2. The storage device according to claim 1, wherein The read / write controller is further configured to perform a recovery write operation on the memory cell after the charge on the bit line is transferred and the sense amplifier outputs the data read signal, so as to restore the read data in the memory cell.

3. The storage device according to claim 1, wherein The memory cell comprises a ferroelectric memory cell; and the dielectric layer comprises a ferroelectric dielectric layer. The storage device according to claim 1 , wherein: The read / write controller includes: Control module; a word line selection circuit connected to the control module and each of the word lines, and configured to: provide the first initial voltage to each of the word lines in response to a first control instruction of the control module, and provide the second selected voltage to the selected word line in response to a third control instruction of the control module; a bit line selection circuit connected to the control module and each of the bit lines, and configured to: provide the second initial voltage to each of the bit lines in response to the first control instruction of the control module, and provide the first selected voltage to the selected bit line in response to the second control instruction of the control module; a sense amplifier connected to the control module and the bit line selection circuit, configured to: turn on the selected bit line in response to the second control instruction of the control module, and output the data read signal after the voltage of the selected word line is set to the second selected voltage; The first control instruction, the second control instruction and the third control instruction are generated in sequence.

5. The storage device according to claim 4, wherein: The sense amplifier comprises: a charge integrator configured to: after the selected bit line is turned on, measure the total amount of charge flowing into or out of the bit line at the first selected voltage, and convert the total amount of charge into a voltage as an initial read signal; The secondary amplifier is connected to the output terminal of the charge integrator and is configured to compare the initial read signal with a reference signal to output the data read signal according to the comparison result between the initial read signal and the reference signal. The storage device according to claim 5 , wherein: The charge integrator comprises: an operational amplifier having a first input terminal, a second input terminal, and an output terminal; the first input terminal is connected to a preset voltage terminal; the second input terminal is configured to connect to the selected bit line and precharge to a preset voltage during a data reading phase; the output terminal is configured to output the initial read signal during the data reading phase; A feedback capacitor has a first electrode and a second electrode; the first electrode of the feedback capacitor is connected to the second input terminal of the operational amplifier, and the second electrode of the feedback capacitor is connected to the output terminal of the operational amplifier.

7. The storage device according to claim 6, wherein: The preset voltage of the second input terminal after precharging is the same as the preset voltage of the preset voltage terminal to which the first input terminal is connected. The storage device according to claim 6 , wherein: The preset voltage after the second input terminal is pre-charged is the first selected voltage.

9. The storage device according to claim 6, wherein: The second input terminal is connected to the selected bit line through the bit line selection circuit.

10. The storage device according to claim 5, wherein The secondary amplifier includes a latch amplifier.

11. The storage device according to any one of claims 1 to 10, wherein: The second selected voltage is a reference voltage; wherein, The first initial voltage is the sum of the reference voltage and two-thirds of the rated voltage; the second initial voltage is the sum of the reference voltage and one-third of the rated voltage; the first selected voltage is the sum of the reference voltage and the rated voltage; Or, the first initial voltage is the difference between the reference voltage and two-thirds of the rated voltage; the second initial voltage is the difference between the reference voltage and one-third of the rated voltage; and the first selected voltage is the difference between the reference voltage and the rated voltage.

12. The storage device according to claim 11, wherein The rated voltage includes the maximum supply voltage.

13. A method for reading data from a storage device, applied to the storage device according to any one of claims 1 to 12; The data reading method comprises: Setting the voltage of each word line to a first initial voltage and setting the voltage of each bit line to a second initial voltage; Setting the voltage of the selected bit line to a first selected voltage, and connecting the selected bit line to a sense amplifier; setting the voltage of the selected word line to a second selected voltage; The sense amplifier outputs a data read signal according to whether charge transfer occurs on the bit line, and the data read signal is used to represent the data stored in the memory cell.

14. The data reading method of the storage device according to claim 13, further comprising: After the charge on the bit line is transferred and the sense amplifier outputs the data read signal, a recovery write operation is performed on the memory cell to restore the read data in the memory cell.

15. The data reading method of the storage device according to claim 13, further comprising: The sense amplifier is initialized while the selected bit line is turned on.

16. The data reading method of the storage device according to claim 13, wherein: The sensing amplifier includes: a charge integrator and a secondary amplifier connected to the output end of the charge integrator; The sense amplifier outputs a data read signal according to whether charge transfer occurs on the bit line, including: After the selected bit line is turned on, the charge integrator measures the total amount of charge flowing into or out of the bit line at the first selected voltage, and converts the total amount of charge into a voltage signal as an initial read signal; The secondary amplifier compares the initial read signal with a reference signal to output a data read signal according to a comparison result between the initial read signal and the reference signal.

17. The data reading method of the storage device according to claim 16, wherein: The initializing the sense amplifier includes: precharging the charge integrator; Wherein, when the voltage of the selected word line is set to the second selected voltage, the data reading method further includes: disconnecting the pre-charging circuit of the charge integrator.

18. The data reading method of a storage device according to any one of claims 13 to 17, wherein: The second selected voltage is a reference voltage; wherein, The first initial voltage is the sum of the reference voltage and two-thirds of the rated voltage; the second initial voltage is the sum of the reference voltage and one-third of the rated voltage; the first selected voltage is the sum of the reference voltage and the rated voltage; Or, the first initial voltage is the difference between the reference voltage and two-thirds of the rated voltage; the second initial voltage is the difference between the reference voltage and one-third of the rated voltage; and the first selected voltage is the difference between the reference voltage and the rated voltage.

19. The data reading method of the storage device according to claim 18, wherein: The rated voltage includes the maximum supply voltage.

20. An electronic device comprising: The storage device according to any one of claims 1 to 10.

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