Sense amplifier and sensing method thereof, storage device and data reading method therefor, and electronic device

Abstract

The present disclosure relates to a sense amplifier and a sensing method thereof, a storage device and a data reading method therefor, and an electronic device. The sense amplifier (1) is configured to be connected to a bit line (BL) to read data stored in a storage unit (U). The sense amplifier (1) comprises a charge integrator (11) and a secondary amplifier (12). The charge integrator (11) is correspondingly connected to the storage unit (U) by means of the bit line (BL), and is configured to: measure the total amount of charge flowing into or out of the bit line (BL) under a stable bit line (BL) voltage, and convert the total amount of charge into a voltage as an initial read signal. The secondary amplifier (12) is connected to an output end of the charge integrator (11) and is configured to: compare the initial read signal with a reference signal so as to output a data read signal on the basis of a comparison result between the initial read signal and the reference signal.

Description

Sense amplifier and sensing method thereof, storage device and data reading method thereof, and electronic device

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This disclosure claims priority to a Chinese patent application filed with the Patent Office of China on March 20, 2024, with application number 202410317884.7 and invention name “Sense amplifier and sensing method thereof, storage device and data reading method thereof, electronic device”. The entire contents of the patent application are incorporated into this disclosure by reference. Technical Field

[0003] The present disclosure relates to the field of semiconductor technology, and in particular to a sense amplifier and a sensing method thereof, a storage device and a data reading method thereof, and an electronic device. Background Art

[0004] With the advancement of communications and digital technologies, people continue to pursue products with lower power consumption, lighter weight, and higher performance. Storage devices, such as random access memory (RAM), disks, and flash memory, are widely used in electronic devices to store information. However, as a key component of storage devices, the performance of sense amplifiers can easily affect the performance of these devices.

[0005] Summary of the Invention

[0006] According to some embodiments, the present disclosure provides, on one hand, a sense amplifier configured to connect to a bit line to read data stored in a memory cell. The sense amplifier includes a charge integrator and a secondary amplifier. The charge integrator is connected to the memory cell via the bit line and is configured to measure the total amount of charge flowing into or out of the bit line at a stable bit line voltage and convert the total charge into a voltage as an initial read signal. The secondary amplifier is connected to the output of the charge integrator and is configured to compare the initial read signal with a reference signal to output a data read signal based on the comparison result between the initial read signal and the reference signal.

[0007] According to some embodiments, the sense amplifier further includes a precharge circuit. The precharge circuit is configured to: connect to the charge integrator to precharge the charge integrator during an initialization phase, and disconnect from the charge integrator during a data reading phase; wherein the bit line is precharged to the first reference voltage or the second reference voltage during the initialization phase.

[0008] According to some embodiments, a charge integrator includes: an operational amplifier and a feedback capacitor. The operational amplifier has a first input terminal, a second input terminal, and an output terminal; the first input terminal is configured to receive a first preset voltage; the second input terminal is connected to a bit line and configured to be precharged to a second preset voltage and receive charge transferred from the bit line during a data read phase; and the output terminal is configured to output an initial read signal during the data read phase. The feedback capacitor has a first electrode and a second electrode; the first electrode of the feedback capacitor is connected to the second input terminal of the operational amplifier, and the second electrode of the feedback capacitor is connected to the output terminal of the operational amplifier.

[0009] According to some embodiments, the reference signal is a voltage threshold; and / or the second preset voltage is equal to the first preset voltage.

[0010] According to some embodiments, the secondary amplifier comprises a latch amplifier.

[0011] According to some embodiments, the present disclosure further provides a sensing method for a sense amplifier, comprising: in a data reading phase: a charge integrator measures the total amount of charge flowing into or out of a bit line at a stable bit line voltage, and converts the total charge into a voltage as an initial read signal; a secondary amplifier compares the initial read signal with a reference signal, and outputs a data read signal based on the comparison result between the initial read signal and the reference signal; wherein the charge integrator is connected to a corresponding storage cell via a bit line, and the data read signal is used to represent data stored in the storage cell.

[0012] According to some embodiments, the sensing method of the sense amplifier further includes: in an initialization phase: precharging the bit line and initializing the charge integrator simultaneously. The initialization phase is before the data reading phase.

[0013] According to some embodiments, during a data reading phase, before a charge integrator measures a total amount of charge flowing into or out of a bit line at a stable bit line voltage and converts the total amount of charge into a voltage as an initial read signal, the sensing method of the sense amplifier further includes: disconnecting a pre-charging circuit of the charge integrator.

[0014] According to some embodiments, the present disclosure further provides a memory device comprising: a memory cell, a bit line, and a sense amplifier as described in any of the above embodiments. The memory cell is configured to store data. The bit line is connected to the memory cell. The sense amplifier is connected to the bit line and configured to read data stored in the memory cell via the bit line.

[0015] According to some embodiments, the memory device further includes a gate transistor connected to the bit line and the charge integrator in the sense amplifier, and configured to control the bit line and the charge integrator in the sense amplifier to be connected in response to a column scan signal during a data reading phase for charge transfer.

[0016] According to some embodiments, a memory cell includes a transistor and a capacitor, wherein a first source / drain of the transistor is connected to a bit line, a second source / drain of the transistor is connected to a first electrode of the capacitor, and a second electrode of the capacitor is grounded. The memory device further includes a word line connected to a gate of the transistor.

[0017] Accordingly, according to some embodiments, the data reading method of the storage device includes:

[0018] Precharging a voltage of a bit line connected to a memory cell to a first reference voltage or a second reference voltage, and simultaneously initializing a charge integrator in a sense amplifier; wherein the first reference voltage is greater than the second reference voltage, and a difference between the first reference voltage and the second reference voltage meets a first preset value;

[0019] providing a third reference voltage to a word line connected to the memory cell;

[0020] The sense amplifier outputs a data read signal according to whether charge transfer occurs on the bit line; the data read signal is used to represent the data stored in the capacitor of the memory cell.

[0021] According to some embodiments, the first reference voltage is a highest voltage in a bit line prechargeable voltage range, and the second reference voltage is a lowest voltage in the bit line prechargeable voltage range.

[0022] According to some embodiments, a memory cell includes a transistor and a first ferroelectric capacitor, wherein a first source / drain of the transistor is connected to a bit line, a second source / drain of the transistor is connected to a first electrode of the first ferroelectric capacitor, and a second electrode of the first ferroelectric capacitor is grounded. The memory device further includes a word line connected to a gate of the transistor.

[0023] Accordingly, according to some embodiments, the data reading method of the storage device includes:

[0024] precharging the voltage of the bit line connected to the memory cell to a first reference voltage and simultaneously initializing the charge integrator in the sense amplifier;

[0025] providing a fourth reference voltage to a word line connected to the memory cell;

[0026] The sense amplifier outputs a data read signal according to whether charge transfer occurs on the bit line; the data read signal is used to represent the data stored in the first ferroelectric capacitor of the memory cell.

[0027] According to some embodiments, the memory cell includes a second ferroelectric capacitor, wherein a first electrode of the second ferroelectric capacitor is connected to a bit line, and the memory device further includes a word line connected to a second electrode of the second ferroelectric capacitor.

[0028] Accordingly, according to some embodiments, the data reading method of the storage device includes:

[0029] precharging the voltage of the bit line connected to the memory cell to a first reference voltage, providing a fifth reference voltage to the word line connected to the memory cell, and simultaneously initializing the charge integrator in the sense amplifier;

[0030] Providing a sixth reference voltage to a word line connected to the memory cell; wherein the fifth reference voltage is greater than the sixth reference voltage, and a difference between the fifth reference voltage and the sixth reference voltage meets a second preset value;

[0031] The sense amplifier outputs a data read signal according to whether charge transfer occurs on the bit line; the data read signal is used to represent the data stored in the second ferroelectric capacitor of the memory cell.

[0032] According to some embodiments, the first reference voltage is the highest voltage of the bit line precharge voltage range, the fifth reference voltage is the highest voltage of the word line settable voltage range, and the sixth reference voltage is the lowest voltage of the word line settable voltage range.

[0033] According to some embodiments, if charge transfer occurs on the bit line, after the sense amplifier outputs the data read signal, the data reading method further includes: performing a recovery write operation on the memory cell to restore the read data in the memory cell.

[0034] According to some embodiments, the present disclosure further provides an electronic device on another aspect, including: the storage device as described in some of the above embodiments.

[0035] The details of one or more embodiments of the present disclosure are set forth in the accompanying drawings and the description below. Other features, objects, and advantages of the present disclosure will become apparent from the description, drawings, and claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present disclosure. For ordinary technicians in this field, without paying any creative work, they can also obtain drawings of other embodiments based on these drawings.

[0037] FIG1 is a schematic structural diagram of a sense amplifier and a storage device provided in some embodiments of the present disclosure;

[0038] FIG2 is a schematic structural diagram of a charge integrator provided in some embodiments of the present disclosure;

[0039] FIG3 is a flow chart of a sensing method of a sense amplifier provided in some embodiments of the present disclosure;

[0040] FIG4 is a flow chart of another sensing method of a sense amplifier provided in some embodiments of the present disclosure;

[0041] FIG5 is a schematic structural diagram of a storage device provided in some embodiments of the present disclosure;

[0042] FIG6 is a schematic flow chart of a method for reading data from the storage device shown in FIG5 ;

[0043] FIG7 is a schematic structural diagram of another storage device provided in some embodiments of the present disclosure;

[0044] FIG8 is a schematic flow chart of a method for reading data from the storage device shown in FIG7 ;

[0045] FIG9 is a schematic structural diagram of another storage device provided in some embodiments of the present disclosure;

[0046] FIG. 10 is a flow chart of a method for reading data from the storage device shown in FIG. 9 . DETAILED DESCRIPTION

[0047] To facilitate understanding of the present disclosure, a more comprehensive description of the present disclosure will be provided below with reference to the accompanying drawings. The drawings illustrate embodiments of the present disclosure. However, the present disclosure can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided to provide a more thorough and comprehensive understanding of the present disclosure.

[0048] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art in the art of the present disclosure. The terms used herein in the specification of the present disclosure are only for the purpose of describing specific embodiments and are not intended to limit the present disclosure.

[0049] References to "embodiments" herein mean that a particular feature, structure, or characteristic described in connection with the embodiments may be included in at least one embodiment of the present disclosure. The appearance of this phrase in various places in the specification does not necessarily refer to the same embodiment, nor does it constitute an independent or alternative embodiment that is mutually exclusive of other embodiments. It is understood, both explicitly and implicitly, by those skilled in the art that the embodiments described herein may be combined with other embodiments.

[0050] It will be understood that the terms "first," "second," "third," "fourth," etc., used herein may be used herein to describe various elements, but these elements are not limited by these terms. These terms are only used to distinguish a first element from another element. For example, a first transistor may be referred to as a second transistor, and similarly, a second transistor may be referred to as a first transistor without departing from the scope of this application. The first transistor and the second transistor are both transistors, but they are not the same transistor.

[0051] It can be understood that the “connection” in the following embodiments should be understood as “electrical connection”, “communication connection”, etc. if there is transmission of electrical signals or data between the connected circuits, modules, units, etc.

[0052] As used herein, the singular forms "a," "an," and "the" may also include the plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "include," "comprising," "having," and the like specify the presence of stated features, integers, steps, operations, components, parts, or combinations thereof, but do not preclude the presence or addition of one or more other features, integers, steps, operations, components, parts, or combinations thereof. Furthermore, the term "and / or" as used in this specification includes any and all combinations of the relevant listed items.

[0053] Semiconductor memory devices are memory devices implemented based on semiconductor materials such as silicon (Si), germanium (Ge), gallium arsenide (GaAs), or indium phosphide (InP). Semiconductor memory devices can be mainly divided into volatile memory devices and non-volatile memory devices. Among them, volatile memory devices are memory devices in which the data stored therein is lost when the power is disconnected. Examples of volatile memory devices include static random access memory (SRAM), dynamic random access memory (DRAM), and synchronous dynamic random access memory (SDRAM). Non-volatile memory devices are memory devices that can retain the data stored therein even when the power is disconnected. Examples of non-volatile memory devices include read-only memory (ROM), programmable read-only memory (PROM), electrically programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), NAND flash memory, NOR flash memory, phase change random access memory (PRAM), magnetic random access memory (MRAM), resistive random access memory (RRAM), ferroelectric random access memory (FRAM), etc.

[0054] However, in related art, sense amplifiers used in various memory devices perform sensing based on voltage detection. For example, a memory cell array connects a bit line and a complementary bit line. During a read or refresh operation, the sense amplifier senses and amplifies the voltage difference between the bit line and the complementary bit line. Because the bit line is floating during this read or refresh operation, the charge change caused by the selected memory cell is shared by parasitic capacitance on the bit line and other peripheral circuits, resulting in significant attenuation of the read signal.

[0055] Based on this, the embodiments of the present disclosure provide a sense amplifier and a sensing method thereof, a storage device and a data reading method thereof, and an electronic device, which can effectively eliminate signal attenuation caused by parasitic capacitance on the bit line to improve the accuracy of reading stored data, thereby enhancing the performance of the sense amplifier, the storage device, and the electronic device.

[0056] Referring to FIG. 1 , in some embodiments of the present disclosure, a sense amplifier 1 is configured to connect to a bit line BL to read data stored in a memory cell U. The sense amplifier 1 includes a charge integrator 11 and a secondary amplifier 12. The charge integrator 11 is connected to the memory cell U via the bit line BL and is configured to measure the total amount of charge flowing into or out of the bit line BL at a stable bit line voltage and convert the total charge into a voltage as an initial read signal. The secondary amplifier 12 is connected to the output of the charge integrator 11 and is configured to compare the initial read signal with a reference signal and output a data read signal based on the comparison result between the initial read signal and the reference signal. The data read signal is used to represent the data stored in the memory cell U.

[0057] It can be understood that the data that can be stored in the memory cell U include, for example, data "0" and data "1". Moreover, by matching the structure of the memory cell U, the storage methods of data "1" and data "0" can be different. For example, in DRAM, data "1" and data "0" can be represented by different data voltages written into the memory cell U, wherein the data voltage corresponding to data "1" and the data voltage corresponding to data "0" can be both positive voltages or both negative voltages or opposite voltages. Or, for example, in FRAM, data "1" and data "0" can be represented by different polarization states of the memory cell U. Thus, in the data reading stage, after the memory cell U is selected, the memory cell U storing data "1" or the memory cell U storing data "0" can produce charge changes that are easily distinguished based on its data voltage or its polarization state.

[0058] For example, a gate transistor is connected between the charge integrator 11 and the bit line BL. The gate transistor can control the bit line BL to be connected to the charge integrator 11 in response to a column scan signal during a data reading phase for charge transfer.

[0059] In the embodiment of the present disclosure, a charge integrator 11 and a secondary amplifier 12 are provided in the sense amplifier 1. During the data read phase, the charge integrator 11 can be used to sense charge changes on the bit line BL. Specifically, the charge integrator can measure the total amount of charge flowing into or out of the bit line at a stable bit line voltage and convert the total charge into a voltage as an initial read signal. After the charge integrator 11 outputs the initial read signal based on the charge change, the secondary amplifier 12 can output a data read signal based on the comparison result of the initial read signal and a reference signal to read the data stored in the memory cell U. Because the above data read process of the embodiment of the present disclosure does not require the bit line BL to be floating during the data read phase, the charge changes generated by the memory cell U can be prevented from being shared by the parasitic capacitance of the bit line BL and related circuits such as the peripheral circuits (i.e., the parasitic capacitance in the read path of the memory cell U does not absorb or release charge). Therefore, excessive voltage changes are not caused on the bit line BL connected to the charge integrator 11 and the entire read path of the memory cell U, effectively preventing significant signal attenuation. This improves the accuracy of stored data reading and enhances the performance of the sense amplifier, storage device, and electronic device.

[0060] In some embodiments, please refer to Figures 1 and 2 to understand that the charge integrator 11 includes: an operational amplifier 111 and a feedback capacitor 112. The operational amplifier 111 has a first input terminal Input1, a second input terminal Input2, and an output terminal Output; the first input terminal Input1 is configured to receive a first preset voltage; the second input terminal Input2 is connected to the bit line BL, is configured to be precharged to a second preset voltage, and receives the charge transmitted by the bit line BL during the data reading phase; the output terminal Output is configured to output an initial read signal during the data reading phase. The feedback capacitor 112 has a first electrode and a second electrode; the first electrode of the feedback capacitor 112 is connected to the second input terminal Input2 of the operational amplifier 111, and the second electrode of the feedback capacitor 112 is connected to the output terminal Output of the operational amplifier 111.

[0061] For example, the second input terminal Input2 is connected to the bit line BL through a gate transistor.

[0062] For example, the second preset voltage is equal to the first preset voltage. That is, the second preset voltage of the second input terminal Input2 after precharging is the same as the first preset voltage received by the first input terminal Input1, and the operation of the operational amplifier 111 can substantially lock the voltage of the second input terminal Input2 to the preset voltage.

[0063] In some embodiments, the sense amplifier 1 further includes a precharge circuit (not shown in FIG1 ). The precharge circuit is configured to connect to the charge integrator 11 during an initialization phase to precharge the charge integrator 11, and disconnect from the charge integrator 11 during a data reading phase. The bit line BL is precharged to the first reference voltage or the second reference voltage during the initialization phase.

[0064] Here, to match the application of the sense amplifier 1 in different memory devices, the precharge voltages of the bit lines BL in the initialization phase may be the same or different, which can be understood in conjunction with the relevant description of the data reading method of the memory device described later.

[0065] For example, referring to FIG2 , the initialization signal of the charge integrator 11 is a pre-charge signal. The first input terminal Input1 and the second input terminal Input2 of the operational amplifier 111 can be connected to a corresponding pre-charge circuit (not shown in FIG2 ), which is configured to pre-charge the operational amplifier 111 during the initialization phase to initialize the operational amplifier 111, and disconnect it from the operational amplifier 111 during the data reading phase. The embodiment of the present disclosure does not specifically limit the circuit design of the pre-charge circuit, and is limited to being able to achieve the aforementioned functions. Optionally, the pre-charge circuit can be a switching device or other circuit structure connected to a power supply voltage terminal, and the power supply voltage terminal is used to provide a rated high-level voltage.

[0066] In some embodiments, the secondary amplifier includes but is not limited to a latch amplifier. The circuit design of the secondary amplifier is such that after comparing the initial read signal with the reference signal, it can effectively output a data read signal according to the comparison result between the initial read signal and the reference signal.

[0067] It should be noted that in some embodiments, the initial read signal is a voltage signal. Accordingly, the reference signal used in the secondary amplifier for comparison with the initial read signal can use a voltage threshold. In this way, the secondary amplifier can conveniently convert the initial read signal to a high level representing data "1" or a low level representing data "0" based on whether the voltage of the initial read signal exceeds the set voltage threshold, thereby simplifying the circuit design of the secondary amplifier.

[0068] Some embodiments of the present disclosure further provide a sensing method for a sense amplifier, which can be applied to the sense amplifiers in some of the above embodiments. The sensing method for the sense amplifier also possesses the technical advantages of the aforementioned sense amplifiers, which will not be described in detail here.

[0069] 3 , the read cycle of the sense amplifier includes a data read phase. The sensing method of the sense amplifier includes steps S10 and S20 performed during the data read phase.

[0070] S10 , a charge integrator measures the total amount of charge flowing into or out of the bit line at a stable bit line voltage, and converts the total amount of charge into a voltage as an initial read signal.

[0071] S20 , the secondary amplifier compares the initial read signal with a reference signal, and outputs a data read signal according to the comparison result between the initial read signal and the reference signal.

[0072] Here, the charge integrator is connected to the corresponding storage unit through the bit line, and the data read signal can be used to represent the data stored in the storage unit.

[0073] In some embodiments, referring to FIG4 , the read cycle of the sense amplifier further includes an initialization phase, which precedes the data read phase. The sensing method of the sense amplifier further includes step S01 performed during the initialization phase.

[0074] S01 , pre-charging the bit line and initializing the charge integrator.

[0075] For example, the bit line may be precharged to a first reference voltage or a second reference voltage.

[0076] For example, the initialization signal of the charge integrator is a pre-charge signal, and the initialization of the charge integrator can be achieved through a correspondingly connected pre-charge circuit.

[0077] Accordingly, in some embodiments, referring to FIG. 4 , the sensing method of the sense amplifier further includes step S02 performed during the data reading phase, and step S02 is performed before step S10 .

[0078] S02, disconnecting the pre-charging circuit of the charge integrator.

[0079] Some embodiments of the present disclosure further provide a storage device, including but not limited to the aforementioned types of semiconductor storage devices.

[0080] For example, referring to Figures 1, 5, 7, and 9, a memory device includes a memory cell U, a bit line BL, and a sense amplifier 1 as described in any of the above embodiments. The memory cell U is configured to store data. The bit line BL is connected to the memory cell U. The sense amplifier 1 is connected to the bit line BL and is configured to read data stored in the memory cell U via the bit line BL.

[0081] For example, a gate transistor is connected between the sense amplifier 1 and the bit line BL. The gate transistor can control the bit line BL to be connected to the charge integrator 11 in response to a column scan signal during a data reading phase for charge transfer.

[0082] It is understood that a storage device typically includes multiple storage units U, and each storage unit U can be distributed in a two-dimensional single layer or a three-dimensional multi-layer distribution. For ease of description and understanding, the storage device described in Figures 5, 7, and 9 is described using a single storage unit U and its connected sense amplifier 1 as an example. Furthermore, when describing the storage device provided by the embodiments of the present disclosure, the embodiments of the present disclosure primarily focus on the storage unit U and the sense amplifier 1 connected to the storage unit U, and do not involve peripheral circuits (e.g., row addressing driver circuits, column addressing driver circuits, etc.) and related circuits in the storage device.

[0083] It is understood that the data that can be stored in the memory unit U include, for example, data "0" and data "1." Furthermore, to match the structure of the memory unit U, the storage methods of data "1" and data "0" can be different.

[0084] In some examples, the storage device is a DRAM. Data "1" and data "0" can be represented by different data voltages written into the memory cell U. The data voltage corresponding to the data "1" and the data voltage corresponding to the data "0" can be both positive voltages, both negative voltages, or opposite voltages.

[0085] In some other examples, the memory device is a FRAM, for example. Data “1” and data “0” can be represented by different polarization states of the memory cell U.

[0086] As described above, in the data reading phase, after the memory cell U is selected, the memory cell U storing data “1” or the memory cell U storing data “0” can generate charge changes that are easily distinguished based on their data voltage or polarization state.

[0087] The following embodiments of the present disclosure exemplify possible implementations of the storage unit U in some different storage devices.

[0088] In some embodiments, referring to FIG. 5 , the memory device is, for example, a DRAM. Memory cell U is a single-transistor, single-capacitor (1T1C) memory cell U1, comprising a transistor T and a capacitor C. A first source / drain S / D1 of transistor T is connected to a bit line BL, for example, via a gate transistor. A second source / drain S / D2 of transistor T is connected to a first electrode 21 of capacitor C. A second electrode 22 of capacitor C is grounded. The memory device further comprises a word line WL connected to a gate G of transistor T.

[0089] Here, to match the current transmission direction, one of the first source / drain S / D1 and the second source / drain S / D2 of the transistor T can be a source and the other can be a drain. The capacitor C is a conventional capacitor, that is, the dielectric layer 23 between the first electrode 21 and the second electrode 22 of the capacitor C is an insulating material.

[0090] Accordingly, in some embodiments, referring to FIG. 6 , the data reading method of the storage device includes the following steps S100 to S300 .

[0091] S100, precharging the voltage of a bit line connected to a single-transistor single-capacitor storage unit to a first reference voltage or a second reference voltage, and simultaneously initializing a charge integrator in a sense amplifier; wherein the first reference voltage is greater than the second reference voltage, and a difference between the first reference voltage and the second reference voltage meets a first preset value.

[0092] S200 , providing a third reference voltage to a word line connected to a single-transistor single-capacitor memory cell.

[0093] S300 , the sense amplifier outputs a data read signal according to whether charge transfer occurs on the bit line; the data read signal is used to represent data stored in the first capacitor of the single-transistor single-capacitor storage unit.

[0094] Here, the process of the sense amplifier acquiring the data read signal can refer to the relevant process of the sensing method of the sense amplifier described above. The technical advantages of the sensing method of the sense amplifier described above are also possessed by the data reading method of the storage device and will not be described in detail here.

[0095] It can be understood that the first reference voltage, the second reference voltage and the third reference voltage can all be set to match the requirements.

[0096] For example, the first reference voltage may be a highest voltage in a bit line prechargeable voltage range, and the second reference voltage may be a lowest voltage in the bit line prechargeable voltage range.

[0097] For example, the third reference voltage can control the conduction of transistor T in the single-transistor, single-capacitor storage unit U1. This causes a change in charge at the first electrode 21 of capacitor C. This change in charge is then transmitted to the charge integrator 11 via the conducting transistor T and the bit line BL, causing the charge integrator 11 to output a corresponding voltage signal as the initial read signal. Subsequently, the secondary amplifier 12 in the sense amplifier 1 compares the initial read signal with a reference signal and outputs a data read signal based on the comparison result.

[0098] For example, the reference signal is a voltage threshold. The secondary amplifier 12 can convert the initial read signal into a high level representing data "1" or a low level representing data "0" based on whether the voltage of the initial read signal crosses the set voltage threshold to achieve data reading.

[0099] It should be added that, in some embodiments, referring to FIG. 6 , if charge transfer occurs on the bit line, then after the sense amplifier outputs the data read signal, the data reading method further includes step S400 .

[0100] S400 , performing a restore write operation on a single-transistor single-capacitor memory cell to restore read data in the single-transistor single-capacitor memory cell.

[0101] It is understood that if charge transfer occurs on the bit line, it indicates that the data originally written to the single-transistor single-capacitor storage cell has been lost during the read process. The embodiments of the present disclosure perform a recovery write operation on the single-transistor single-capacitor storage cell, facilitating repeated reading of stored data.

[0102] In other embodiments, referring to FIG. 7 , the memory device is, for example, a FRAM. The memory cell U is a single-transistor, single-ferroelectric-capacitor (1T1C) memory cell U2, comprising a transistor T and a first ferroelectric capacitor C1. The first source / drain S / D1 of the transistor T is connected to a bit line BL, the second source / drain S / D2 of the transistor T is connected to a first electrode 31 of the first ferroelectric capacitor C1, and the second electrode 32 of the first ferroelectric capacitor C1 is grounded. The memory device further comprises a word line WL connected to the gate G of the transistor T.

[0103] Here, the transmission direction of the current is matched, and one of the first source / drain S / D1 and the second source / drain S / D2 of the transistor T can be a source and the other can be a drain. The dielectric layer 33 between the first electrode 31 and the second electrode 32 in the first ferroelectric capacitor C1 is a ferroelectric material, which includes but is not limited to hafnium zirconium oxide (HfZrO, also known as HZO, which includes hafnium, zirconium and oxygen), silicon-doped (Si-doped) hafnium oxide (a material containing hafnium, oxygen and silicon), germanium-doped (Ge-doped) hafnium oxide (a material containing hafnium, oxygen and germanium), aluminum-doped (Al-doped) hafnium oxide (a material containing hafnium, oxygen and aluminum), yttrium-doped (Y-doped) hafnium oxide (a material containing hafnium, oxygen and yttrium), lead zirconate titanate (a material containing hafnium, including lead, zirconium and titanium), barium zirconate titanate (a material containing barium, zirconium and titanium), and combinations thereof.

[0104] Furthermore, when data "1" or data "0" is written into the single-transistor single-ferroelectric capacitor (1T1C) memory cell U2, the ferroelectric material in the first ferroelectric capacitor C1 will correspondingly assume different polarization states: for example, when data "1" is written, the ferroelectric material in the first ferroelectric capacitor C1 is in a first polarization state; for example, when data "0" is written, the ferroelectric material in the first ferroelectric capacitor C1 is in a second polarization state. The first polarization state of the ferroelectric material can be reversed to the second polarization state under the action of an external electric field, and the second polarization state of the ferroelectric material can be reversed to the first polarization state under the action of an external electric field. The second polarization state is, for example, the initial polarization state of the ferroelectric material.

[0105] As described above, in some embodiments, referring to FIG. 8 , the data reading method of the storage device shown in FIG. 7 may include the following steps S100 ′ to S300 ′.

[0106] S100 ′, precharging the voltage of the bit line connected to the single-transistor single-ferroelectric capacitor memory cell to a first reference voltage, and simultaneously initializing the charge integrator in the sense amplifier.

[0107] S200 ′, providing a fourth reference voltage to a word line connected to a single-transistor single-ferroelectric capacitor memory cell.

[0108] S300', the sense amplifier outputs a data read signal according to whether charge transfer occurs on the bit line; the data read signal is used to represent the data stored in the first ferroelectric capacitor of the single-transistor single-ferroelectric capacitor storage unit.

[0109] For example, the first reference voltage may be a highest voltage in a bit line prechargeable voltage range.

[0110] For example, the fourth reference voltage can control the conduction of transistor T in the single-transistor single-ferroelectric capacitor storage unit U2. At this time, the first electrode 21 of the first ferroelectric capacitor C1, which is in one of the first polarization state or the second polarization state, will produce a charge change. The aforementioned charge change can be transmitted to the charge integrator 11 through the conductive transistor T and the bit line BL. That is, the charge integrator 11 senses whether the charge on the bit line BL has undergone charge transfer and outputs a corresponding voltage signal as the initial read signal. Afterwards, the secondary amplifier 12 in the sense amplifier 1 compares the initial read signal with the reference signal and can output a data read signal based on the comparison result of the initial read signal and the reference signal. The reference signal is, for example, a voltage threshold. The secondary amplifier 12 can convert the initial read signal into a high level that can represent data "1" or a low level that represents data "0" based on whether the voltage of the initial read signal crosses the set voltage threshold, thereby realizing data reading.

[0111] It should be added that, in some embodiments, referring to FIG. 8 , if charge transfer occurs on the bit line, then after the sense amplifier outputs the data read signal, the data reading method further includes step S400 ′.

[0112] S400 ′, performing a recovery write operation on the single-transistor single-ferroelectric capacitor memory cell to restore the read data in the single-transistor single-ferroelectric capacitor memory cell.

[0113] It is understood that if charge transfer occurs on the bit line, it means that the data originally written in the single-transistor single-ferroelectric capacitor storage cell has been lost during the read process. The embodiments of the present disclosure perform a recovery write operation on the single-transistor single-ferroelectric capacitor storage cell, which facilitates the repeated reading of stored data.

[0114] In yet other embodiments, referring to FIG. 9 , the memory device is, for example, a FRAM. The memory cell U is a zero-transistor single ferroelectric capacitor (OT1C) memory cell U3, which includes a second ferroelectric capacitor C2. A first electrode 41 of the second ferroelectric capacitor C2 is connected to a bit line BL, for example, via a gate transistor. The memory device further includes a word line WL connected to a second electrode 42 of the second ferroelectric capacitor C2.

[0115] For example, the dielectric layer 43 of the second ferroelectric capacitor C2 located between the first electrode 41 and the second electrode 42 is a ferroelectric material, which ferroelectric material includes but is not limited to hafnium zirconium oxide (HfZrO, also known as HZO, which includes hafnium, zirconium and oxygen), silicon-doped (Si-doped) hafnium oxide (material containing hafnium, oxygen and silicon), germanium-doped (Ge-doped) hafnium oxide (material containing hafnium, oxygen and germanium), aluminum-doped (Al-doped) hafnium oxide (material containing hafnium, oxygen and aluminum), yttrium-doped (Y-doped) hafnium oxide (material containing hafnium, oxygen and yttrium), lead zirconium titanate (material containing hafnium, including lead, zirconium and titanium), barium zirconium titanate (material containing barium, zirconium and titanium) and combinations thereof.

[0116] Furthermore, when data "1" or data "0" is written into the zero-transistor single ferroelectric capacitor (0T1C) storage unit U3, the ferroelectric material in the second ferroelectric capacitor C2 will correspondingly assume different polarization states: for example, when data "1" is written, the ferroelectric material in the second ferroelectric capacitor C2 is in a first polarization state; for example, when data "0" is written, the ferroelectric material in the second ferroelectric capacitor C2 is in a second polarization state. The first polarization state of the ferroelectric material can be reversed to the second polarization state under the action of an external electric field, and the second polarization state of the ferroelectric material can be reversed to the first polarization state under the action of an external electric field. The second polarization state is, for example, the initial polarization state of the ferroelectric material.

[0117] As described above, in some embodiments, referring to FIG. 10 , the data reading method of the storage device shown in FIG. 9 may include the following steps S100 ″ to S300 ″.

[0118] S100 ”, precharge the voltage of the bit line connected to the zero-transistor single ferroelectric capacitor storage unit to a first reference voltage, provide a fifth reference voltage to the word line connected to the zero-transistor single ferroelectric capacitor storage unit, and initialize the charge integrator in the sense amplifier.

[0119] S200 ”, providing a sixth reference voltage to a word line connected to a zero-transistor single ferroelectric capacitor storage unit; wherein the fifth reference voltage is greater than the sixth reference voltage, and a difference between the fifth reference voltage and the sixth reference voltage meets a second preset value;

[0120] S300 ”, the sense amplifier outputs a data read signal according to whether charge transfer occurs on the bit line; the data read signal is used to represent the data stored in the second ferroelectric capacitor of the zero-transistor single ferroelectric capacitor storage unit.

[0121] It can be understood that the first reference voltage, the fifth reference voltage and the sixth reference voltage can all be set to match the requirements.

[0122] For example, the first reference voltage may be a highest voltage in a bit line prechargeable voltage range.

[0123] For example, the fifth reference voltage may be a highest voltage in a word line settable voltage range, and the sixth reference voltage may be a lowest voltage in the word line settable voltage range.

[0124] In the embodiment of the present disclosure, after the voltage of the word line is lowered from the fifth reference voltage to the sixth reference voltage, the first electrode 41 of the second ferroelectric capacitor C2 in one of the first polarization state or the second polarization state will produce a charge change. The charge integrator 11 connected to the bit line BL can sense whether the charge on the bit line BL has transferred and output a corresponding voltage signal as the initial read signal. Afterwards, the secondary amplifier 12 in the sense amplifier 1 can output a data read signal based on the comparison result of the initial read signal and the reference signal by comparing the initial read signal with the reference signal. The reference signal is, for example, a voltage threshold. The secondary amplifier 12 can convert the initial read signal into a high level that can represent data "1" or a low level that represents data "0" based on whether the voltage of the initial read signal crosses the set voltage threshold, thereby realizing data reading.

[0125] It should be added that, in some embodiments, referring to FIG. 10 , if charge transfer occurs on the bit line, then after the sense amplifier outputs the data read signal, the data reading method further includes step S400 .

[0126] S400 ”, performing a recovery write operation on the zero-transistor single ferroelectric capacitor memory cell to restore the read data in the zero-transistor single ferroelectric capacitor memory cell.

[0127] It is understood that if charge transfer occurs on the bit line, it means that the data written in the original zero-transistor single ferroelectric capacitor storage cell has been lost during the read process. The embodiment of the present disclosure performs a recovery write operation on the zero-transistor single ferroelectric capacitor storage cell, which facilitates the repeated reading of stored data.

[0128] Some embodiments of the present disclosure further provide an electronic device, such as a data storage device, a copier, a network device, a household appliance, an instrument, a mobile phone, a computer, or other device with a data storage function. The electronic device may include the storage device described in some of the aforementioned embodiments. The electronic device may also include other necessary elements or components, which are not limited in the embodiments of the present disclosure.

[0129] The technical features of the above-mentioned embodiments can be combined arbitrarily. To make the description concise, not all possible combinations of the technical features of the above-mentioned embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0130] The above-described embodiments merely represent several implementation methods of the present disclosure. While the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent application. It should be noted that a person of ordinary skill in the art may make various modifications and improvements without departing from the spirit of the present disclosure, all of which fall within the scope of protection of the present disclosure. Therefore, the scope of protection of the patent disclosed herein shall be determined by the appended claims.

Claims

1. A sense amplifier configured to connect a bit line to read data stored in a memory cell; the sense amplifier comprising: a charge integrator connected to the memory cell via the bit line, and configured to: measure the total amount of charge flowing into or out of the bit line at a stable bit line voltage, and convert the total amount of charge into a voltage as an initial read signal; The secondary amplifier is connected to the output terminal of the charge integrator and is configured to compare the initial read signal with a reference signal to output a data read signal according to the comparison result between the initial read signal and the reference signal.

2. The sense amplifier according to claim 1, wherein The sense amplifier further comprises: a precharge circuit configured to: connect to the charge integrator to precharge the charge integrator during an initialization phase, and disconnect from the charge integrator during a data reading phase; The bit line is precharged to a first reference voltage or a second reference voltage during the initialization phase.

3. The sense amplifier according to claim 1 or 2, wherein: The charge integrator comprises: an operational amplifier having a first input terminal, a second input terminal, and an output terminal; the first input terminal is configured to receive a first preset voltage; the second input terminal is connected to the bit line and is configured to be precharged to a second preset voltage and receive charge transferred by the bit line during a data read phase; the output terminal is configured to output the initial read signal during the data read phase; A feedback capacitor has a first electrode and a second electrode; the first electrode of the feedback capacitor is connected to the second input terminal of the operational amplifier, and the second electrode of the feedback capacitor is connected to the output terminal of the operational amplifier.

4. The sense amplifier according to claim 3, wherein: The reference signal is a voltage critical value; And / or, the second preset voltage is equal to the first preset voltage.

5. The sense amplifier according to any one of claims 1 to 4, wherein: The secondary amplifier includes a latch amplifier.

6. A sensing method for a sense amplifier, comprising: During the data reading phase: The charge integrator measures the total amount of charge flowing into or out of the bit line at a stable bit line voltage and converts the total amount of charge into a voltage as an initial read signal; The secondary amplifier compares the initial read signal with a reference signal and outputs a data read signal according to a comparison result between the initial read signal and the reference signal; The charge integrator is connected to the storage unit via the bit line, and the data read signal is used to represent the data stored in the storage unit.

7. The sensing method of the sense amplifier according to claim 6, further comprising: During the initialization phase: precharging the bit line and simultaneously initializing the charge integrator; The initialization phase is before the data reading phase.

8. The sensing method of the sense amplifier according to claim 6, wherein: In the data reading phase, before the charge integrator measures the total amount of charge flowing into or out of the bit line at a stable bit line voltage and converts the total amount of charge into a voltage as an initial reading signal, the sensing method of the sense amplifier further includes: disconnecting the pre-charging circuit of the charge integrator.

9. A storage device comprising: a storage unit configured to store data; A bit line connected to the memory cell; The sense amplifier according to any one of claims 1 to 5, connected to the bit line and configured to read data stored in the memory cell through the bit line.

10. The storage device according to claim 9, further comprising: The gate transistor is connected to the bit line and the charge integrator in the sense amplifier and is configured to: control the bit line and the charge integrator in the sense amplifier to be connected in response to a column scanning signal during a data reading phase for charge transfer.

11. The storage device according to claim 9 or 10, wherein: The storage unit includes: a transistor and a capacitor; wherein the first source / drain of the transistor is connected to the bit line, the second source / drain of the transistor is connected to the first electrode of the capacitor, and the second electrode of the capacitor is grounded; The storage device further includes a word line connected to the gate of the transistor.

12. The storage device according to claim 9 or 10, wherein: The memory cell comprises: a transistor and a first ferroelectric capacitor; wherein the first source / drain of the transistor is connected to the bit line, the second source / drain of the transistor is connected to the first electrode of the first ferroelectric capacitor, and the second electrode of the first ferroelectric capacitor is grounded; The storage device further includes a word line connected to the gate of the transistor.

13. The storage device according to claim 9 or 10, wherein: The memory cell includes a second ferroelectric capacitor; wherein the first electrode of the second ferroelectric capacitor is connected to the bit line; The memory device further includes a word line connected to the second electrode of the second ferroelectric capacitor.

14. A method for reading data from a storage device, wherein the storage device is as claimed in claim 11, the method comprising: Precharging a voltage of a bit line connected to the memory cell to a first reference voltage or a second reference voltage, and simultaneously initializing a charge integrator in a sense amplifier; wherein the first reference voltage is greater than the second reference voltage, and a difference between the first reference voltage and the second reference voltage meets a first preset value; providing a third reference voltage to a word line connected to the memory cell; The sense amplifier outputs a data read signal according to whether charge transfer occurs on the bit line; the data read signal is used to represent the data stored in the capacitor of the memory cell.

15. The data reading method of the storage device according to claim 14, wherein: The first reference voltage is a highest voltage in a voltage range that the bit line can be precharged, and the second reference voltage is a lowest voltage in the voltage range that the bit line can be precharged.

16. A method for reading data from a storage device, the storage device according to claim 12, the method comprising: precharging the voltage of the bit line connected to the memory cell to a first reference voltage and simultaneously initializing the charge integrator in the sense amplifier; providing a fourth reference voltage to a word line connected to the memory cell; The sense amplifier outputs a data read signal according to whether charge transfer occurs on the bit line; the data read signal is used to represent the data stored in the first ferroelectric capacitor of the memory cell.

17. A method for reading data from a storage device, the storage device according to claim 13, the method comprising: precharging a voltage of a bit line connected to the memory cell to a first reference voltage, providing a fifth reference voltage to a word line connected to the memory cell, and simultaneously initializing a charge integrator in a sense amplifier; providing a sixth reference voltage to a word line connected to the memory cell; wherein the fifth reference voltage is greater than the sixth reference voltage, and a difference between the fifth reference voltage and the sixth reference voltage meets a second preset value; The sense amplifier outputs a data read signal according to whether charge transfer occurs on the bit line; the data read signal is used to represent data stored in the second ferroelectric capacitor of the memory cell.

18. The data reading method of the storage device according to claim 17, wherein: The first reference voltage is the highest voltage of the bit line precharge voltage range, the fifth reference voltage is the highest voltage of the word line settable voltage range, and the sixth reference voltage is the lowest voltage of the word line settable voltage range.

19. The data reading method of a storage device according to any one of claims 14 to 18, wherein: If charge transfer occurs on the bit line, then after the sense amplifier outputs the data read signal, the data reading method further includes: A recovery write operation is performed on the storage unit to restore the read data in the storage unit.

20. An electronic device comprising: The storage device according to any one of claims 9 to 13.

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