Data transmission method and apparatus

Abstract

The present application provides a data transmission method and apparatus, applied to an optical transport network (OTN) system, and used for reducing the processing costs during service data mapping and achieving the purpose of improving the system performance. The method comprises: first mapping i paths of first OTN signals to a second OTN signal, wherein the second OTN signal comprises n paths of third OTN signals; then generating a fourth OTN signal from the second OTN signal on the basis of the X-byte interleave granularity, and sending the fourth OTN signal. The mapping granularity used for mapping a j-th path of first OTN signals among the i paths of first OTN signals to the second OTN signal is nj*X bytes, the rate of the j-th path of first OTN signals is nj times the reference rate, i is an integer greater than or equal to 1, j=1, 2, 3, …, i, nj is an integer greater than or equal to 1, and n and X are integers greater than 1.

Description

Method and device for transmitting data

[0001] This application claims priority to the Chinese patent application filed with the State Intellectual Property Office of China on March 22, 2024, with application number 202410341230.8 and application name “Method and Apparatus for Transmitting Data”, the entire contents of which are incorporated by reference into this application. Technical Field

[0002] The present application relates to the field of optical transport networks, and more particularly, to a method and apparatus for transmitting data. Background Art

[0003] With the development of optical transport network (OTN) technology, OTN technology with a transmission speed exceeding 1T has gradually become a research hotspot.

[0004] The problem that needs to be solved is how to simplify the process of mapping client service data to super-1T OTN signals, thereby reducing the bit rate of the super-1T physical interface. Summary of the Invention

[0005] The present application provides a method and apparatus for transmitting data, which can reduce the processing cost during business data mapping and improve system performance.

[0006] In a first aspect, an embodiment of the present application provides a method for transmitting data, which can be performed by an OTN device or by a component of the OTN device (such as a chip, an optical module, or a chip system, etc.), and is not limited in this application. Specifically, the method is performed by a sending device, and the method includes: mapping i first optical transport network OTN signals to second OTN signals, wherein the second OTN signals include n third OTN signals, and the mapping granularity used by mapping the jth first OTN signal in the i first OTN signals to the second OTN signal is n. j *X bytes, the rate of the j-th first OTN signal is n j times the base rate, i is an integer greater than or equal to 1, j = 1, 2, 3…i, n j is an integer greater than or equal to 1, and n and X are integers greater than 1; generating a fourth OTN signal based on an X-byte interleaving granularity by using the second OTN signal; and sending the fourth OTN signal.

[0007] Based on the above solution, the mapping granularity of each first OTN signal mapped to the second OTN signal is an integer multiple of the interleaving granularity of the second OTN signal interleaved to the fourth OTN signal, which can reduce the processing cost and thus achieve the purpose of improving system performance.

[0008] In combination with the first aspect, in some implementations of the first aspect, X is 32.

[0009] In some embodiments, the mapping granularity or interleaving granularity can also be represented by bits. For example, the mapping granularity used for mapping the j-th first OTN signal to the second OTN signal is n. j *Y bits, the second OTN signal generates a fourth OTN signal based on the Y-bit interleaving granularity. When bits are used to represent the mapping granularity or interleaving granularity, Y bits do not necessarily correspond to an integer number of bytes. For example, the mapping granularity used for mapping the j-th first OTN signal to the second OTN signal is n j *255 bits, which is less than 32 bytes. For example, the mapping granularity used for mapping the j-th first OTN signal to the second OTN signal is n j *256 bits, which equals 32 bytes.

[0010] In combination with the first aspect, in some implementations of the first aspect, the fourth OTN signal includes n time slots, and the second OTN signal mapped to the j-th first OTN signal is n timeslots in the n timeslots. j time slots.

[0011] In combination with the first aspect, in certain implementations of the first aspect, each of the n time slots is 100G.

[0012] Based on the above solution, the rate of the first OTN signal on the jth path is n j times the base rate, and the second OTN signal mapped by the first OTN signal on the jth path is n j time slots, that is, the solution of the present application aligns the reference rate with the rate corresponding to each time slot in the fourth OTN signal, thereby simplifying the mapping process and helping to improve mapping efficiency.

[0013] In combination with the first aspect, in some implementations of the first aspect, the n-way third OTN signal is an n-way flexible optical network FlexO instance, and the second OTN signal mapped to the j-th first OTN signal is n-way flexible optical network FlexO instance. j The fourth OTN signal includes the n FlexO instances, and the rate of each of the n FlexO instances is 100 Gbit / s.

[0014] In combination with the first aspect, in some implementations of the first aspect, the n third OTN signals are n FlexO instances, and the second OTN signal mapped to the j-th first OTN signal is n jThe fourth OTN signal includes the n FlexO instances, and the rate of each FlexO instance in the n FlexO instances is 100 Gbit / s.

[0015] In conjunction with the first aspect, in certain implementations of the first aspect, n=n1+n2+...+n j +n i .

[0016] Based on the above solution, a fourth OTN signal with large bandwidth and high rate is constructed through n FlexO instances, which can achieve compatibility with existing FlexO instances.

[0017] In combination with the first aspect, in some implementations of the first aspect, the rate of the j-th first OTN signal is 100 Gbit / s*n j .

[0018] With reference to the first aspect, in certain implementations of the first aspect, the fourth OTN signal rate is 1.6 Tbit / s.

[0019] In combination with the first aspect, in some implementations of the first aspect, the fourth OTN signal includes an overhead area, the overhead area includes a payload type PT, and the PT indicates that the timeslot granularity is 100 Gbit / s.

[0020] In conjunction with the first aspect, in certain implementations of the first aspect, the first OTN signal is an optical data unit (ODU). The first OTN signal may also be a FlexO channel layer signal.

[0021] In a second aspect, an embodiment of the present application provides a method for transmitting data, which can be performed by an OTN device or by a component of the OTN device (such as a chip, an optical module, or a chip system, etc.), and is not limited in this application. Specifically, the method is performed by a receiving device, and the method includes: receiving a fourth OTN signal; deinterleaving the fourth OTN signal with X bytes to obtain a second OTN signal, wherein the second OTN signal includes n third OTN signals; demapping the second OTN signal to obtain i first OTN signals, wherein the mapping granularity of the jth first OTN signal in the i first OTN signals to the second OTN signal is n. j *X bytes, the rate of the j-th first OTN signal is n j times the base rate, i is an integer greater than or equal to 1, j = 1, 2, 3…i, n j is an integer greater than or equal to 1, and n and X are integers greater than 1.

[0022] In combination with the second aspect, in some implementations of the second aspect, X is 32.

[0023] In combination with the second aspect, in some implementations of the second aspect, the fourth OTN signal includes n time slots, and the second OTN signal mapped to the j-th first OTN signal is n timeslots in the n timeslots. j time slots.

[0024] In combination with the second aspect, in certain implementations of the second aspect, each of the n time slots is 100G.

[0025] In combination with the second aspect, in some implementations of the second aspect, the n-way third OTN signal is an n-way flexible optical network FlexO instance, and the second OTN signal mapped to the j-th first OTN signal is n-way flexible optical network FlexO instance. j The fourth OTN signal includes the n FlexO instances, and the rate of each of the n FlexO instances is 100 Gbit / s.

[0026] In combination with the second aspect, in some implementations of the second aspect, the n third OTN signals are n FlexO instances, and the second OTN signal mapped to the j-th first OTN signal is n j The fourth OTN signal includes the n FlexO instances, and the rate of each FlexO instance in the n FlexO instances is 100 Gbit / s.

[0027] In conjunction with the second aspect, in certain implementations of the second aspect, n=n1+n2+...+n j +n i .

[0028] In conjunction with the second aspect, in some implementations of the second aspect, the rate of the j-th first OTN signal is 100 Gbit / s*n j .

[0029] In combination with the second aspect, in some implementations of the second aspect, the fourth OTN signal rate is 1.6 Tbit / s.

[0030] In combination with the second aspect, in some implementations of the second aspect, the fourth OTN signal includes an overhead area, the overhead area includes a payload type PT, and the PT indicates that the timeslot granularity is 100 Gbit / s.

[0031] In conjunction with the second aspect, in certain implementations of the second aspect, the first OTN signal is an optical data unit (ODU). The first OTN signal may also be a FlexO channel layer signal.

[0032] In a third aspect, an embodiment of the present application provides a device for transmitting data. The device is used to execute the method provided in the first aspect above, or to execute the method provided in the second aspect above. Specifically, the device may include units and / or modules for executing the method provided in the first aspect or any one of the above-mentioned implementations of the first aspect, or the device may include units and / or modules, such as a processing module and a transceiver module, for executing the method provided in the second aspect or any one of the above-mentioned implementations of the second aspect.

[0033] In one implementation, the apparatus for transmitting data may include units and / or modules for executing the method provided in the first aspect or any of the aforementioned implementations of the first aspect, and may be a transmitting device. The transceiver module may be a transceiver or an input / output interface. The processing module may be at least one processor. Alternatively, the transceiver may be a transceiver circuit. Alternatively, the input / output interface may be an input / output circuit.

[0034] Alternatively, the data transmission device may be a chip, chip system, or circuit in a transmitting device. The transceiver module may be an input / output interface, interface circuit, output circuit, input circuit, pin, or related circuit on the chip, chip system, or circuit. The processing module may be at least one processor, processing circuit, or logic circuit.

[0035] In another implementation, the data transmission apparatus may include units and / or modules for executing the method provided in the second aspect or any of the aforementioned implementations of the second aspect, and may be a receiving device. The transceiver module may be a transceiver or an input / output interface. The processing module may be at least one processor. Alternatively, the transceiver may be a transceiver circuit. Alternatively, the input / output interface may be an input / output circuit.

[0036] Alternatively, the data transmission device may be a chip, chip system, or circuit in a receiving device. The transceiver module may be an input / output interface, interface circuit, output circuit, input circuit, pin, or related circuit on the chip, chip system, or circuit. The processing module may be at least one processor, processing circuit, or logic circuit.

[0037] In a fourth aspect, an embodiment of the present application provides a processor for executing the methods provided in the above aspects.

[0038] For the operations such as sending and acquiring / receiving involved in the processor, unless otherwise specified, or if they do not conflict with their actual functions or internal logic in the relevant descriptions, they can be understood as processor output, reception, input and other operations, and can also be understood as sending and receiving operations performed by the radio frequency circuit and antenna. This application does not limit this.

[0039] In a fifth aspect, embodiments of the present application provide a computer-readable storage medium storing program code for execution by a device, the program code including a method for executing any one of the implementations of the first or second aspects.

[0040] In a sixth aspect, an embodiment of the present application provides a computer program product comprising instructions. When the computer program product is run on a computer or a processor, the computer or processor is caused to execute the method provided in any one of the implementations of the first or second aspect.

[0041] In a seventh aspect, an embodiment of the present application provides a chip. The chip includes a processor and a communication interface, wherein the processor reads instructions stored in a memory through the communication interface and executes the method provided in any one of the implementations of the first or second aspect.

[0042] Optionally, as an implementation method, the chip also includes a memory, in which a computer program or instruction is stored, and the processor is used to execute the computer program or instruction stored in the memory. When the computer program or instruction is executed, the processor is used to execute the method provided in any one of the implementation methods of the first or second aspect above.

[0043] In an eighth aspect, an embodiment of the present application provides a network device, comprising: a processor and an input / output interface, for executing the method provided in any one of the implementations of the first or second aspects above, wherein the input / output interface is for transmitting and receiving OTN signals, and the processor is for processing the OTN signals.

[0044] In a ninth aspect, an embodiment of the present application provides an optical module, comprising a signal processor and an optical transmission component, wherein the signal processor is used to execute the method provided in any one of the implementations of the first aspect above; and the optical transmission component is used to convert the fourth OTN signal into an optical signal and send the optical signal.

[0045] In a tenth aspect, an embodiment of the present application provides an optical module, wherein the optical module includes a signal processor and an optical receiving component, wherein:

[0046] The optical receiving component is configured to receive an optical signal and convert the optical signal into the fourth OTN signal;

[0047] The signal processor is used to execute the method provided by any one of the implementations of the second aspect above.

[0048] The beneficial effects brought about by the second to tenth aspects mentioned above can be specifically referred to the description of the beneficial effects in the first aspect, and will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0049] FIG1 is a schematic diagram of an OTN optical network system applicable to an embodiment of the present application.

[0050] FIG2 is a schematic diagram of the hardware structure of an OTN device applicable to an embodiment of the present application.

[0051] FIG3 is a schematic diagram of the hardware structure of an optical module applicable to an embodiment of the present application.

[0052] FIG4 is a schematic flowchart of a method 400 for transmitting data provided in an embodiment of the present application.

[0053] FIG5 is a schematic diagram of a first method provided by an embodiment of the present application for mapping i ODUflex signals to n FlexO instances using an integer multiple of 32 bytes (or 256 bits), and interleaving n FlexO instances using 32 bytes to generate a FlexO-n signal.

[0054] FIG6 is a schematic diagram of a second method provided by an embodiment of the present application for mapping i ODUflex signals to n FlexO instances using integer multiples of 32 bytes (or 256 bits), and interleaving n FlexO instances using 32 bytes to generate a FlexO-n signal.

[0055] FIG7 is a schematic block diagram of a data transmission device 700 provided in an embodiment of the present application.

[0056] FIG8 is a schematic structural diagram of a possible data transmission device provided in an embodiment of the present application.

[0057] FIG9 is a schematic diagram of a chip system 1200 provided in accordance with an embodiment of the present application. DETAILED DESCRIPTION

[0058] In order to facilitate understanding of the embodiments of the present application, the following explanations are provided.

[0059] First, the terms "first," "second," and various numbers in the following descriptions or drawings of the embodiments of the present application are used for ease of description and are not intended to limit the scope of the embodiments of the present application. For example, they are used to distinguish between different OTN signals.

[0060] Second, the terms "including" and "having" and any variations thereof in the embodiments of the present application shown below are intended to cover non-exclusive inclusions. For example, a system, product or device that includes a series of units is not necessarily limited to those units explicitly listed, but may include other units that are not explicitly listed or are inherent to these products or devices.

[0061] Third, in the embodiments of this application, words such as "exemplarily" or "for example" are used to indicate examples, illustrations, or descriptions. An embodiment or design described as "exemplary" or "for example" should not be construed as being preferred or advantageous over other embodiments or designs. The use of words such as "exemplary" or "for example" is intended to present related concepts in a concrete manner to facilitate understanding.

[0062] Fourth, unless otherwise defined, all terms (including technical and scientific terms) used in this application have the same meaning as commonly understood by ordinary technicians in the field to which this application belongs.

[0063] Fifth, the embodiment of the present application is described using flexible optical data unit (ODUflex) mapping as an example, but the solution of the present application is not limited thereto. The data transmission method provided in the present application can also be applied to other ODU signals.

[0064] Sixth, in this application, "sending" and "receiving" indicate the direction of signal transmission. For example, "receiving information from YY" can be understood as the source of the information being YY, which can include receiving directly from YY through a communication interface, or indirectly from YY from other units or modules through a communication interface. "Sending" can also be understood as the "output" of a chip interface, and "receiving" can also be understood as the "input" of a chip interface. In other words, sending and receiving can be performed between devices, for example, between a sending device and a receiving device, or can be performed within a device, for example, sending or receiving between components, modules, chips, software modules, or hardware modules within a device through a bus, trace, or interface.

[0065] Seventh, in the solution provided in this application document, the sending device can be referred to as a sending end device, a sending end node, or a sending node, etc. Similarly, the receiving device can be referred to as a receiving device, a receiving end node, or a receiving node, etc.

[0066] Eighth, in this application, a "signal" may also be referred to as a "frame" or "data frame." For example, OTN may be referred to as an OTN signal, an OTN frame, or an OTN data frame. It should be noted that when used to describe the data structure that carries service data, it is generally understood as a "frame." When used to describe the carrier that carries service data or to describe the transmission of service data, it is generally understood as a "signal." In the following description, this application does not specifically distinguish between "frame" and "signal."

[0067] Ninth, in the present application, OTN signals are referred to as OTN frames, or OTN data frames, etc. OTN signals may include optical payload unit (OPU) signals, ODU signals (such as ODUk, ODUflex, etc.), optical transport unit (OTU) signals (such as OTUk, OTUCn, where k represents a different rate level and Cn represents a variable rate), FlexO signals, etc. FlexO signals include FlexO instances, FlexO interface signals (such as FlexO-n, FlexO-ne, FlexO-x-FEC, FlexO-x-FEC-m), and other FlexO interface signals with rates exceeding 100 Gbit / s defined by other OTN signals developed in future technologies.

[0068] 10. In the embodiments of this application, service data refers to services carried by an optical transport network or a metropolitan area transport network. For example, it may be Ethernet services, packet services, wireless backhaul services, etc. Service data may also be referred to as service signals, customer data, or customer service data. It should be understood that the types of service data are not limited in the embodiments of this application.

[0069] The technical solution of this application is described in detail below with reference to the accompanying drawings.

[0070] The embodiments of the present application are applicable to optical networks, such as OTN. An OTN is usually composed of multiple devices connected by optical fibers and can be formed into different topologies such as linear, ring, and mesh according to specific needs.

[0071] Figure 1 is a schematic diagram of an OTN optical network system applicable to embodiments of the present application. As shown in Figure 1 , OTN 100 includes eight interconnected OTN devices 101, namely, devices A and H. Reference numeral 102 indicates an optical fiber used to connect two devices; 103 indicates a customer service interface used to receive or transmit customer service data. As shown in Figure 1 , OTN 100 is used to transmit service data for customer devices 1-3. Customer devices 1-3 can be Ethernet devices, and the service data can be Ethernet service data. Customer devices connect to OTN devices via customer service interfaces. For example, in Figure 1 , customer devices 1-3 are connected to OTN devices A, H, and F, respectively.

[0072] Depending on actual needs, an OTN device may have different functions. Generally speaking, OTN devices are divided into optical layer devices, electrical layer devices, and optoelectronic hybrid devices. Optical layer devices refer to devices that can process optical layer signals, such as optical amplifiers and optical add-drop multiplexers. Optical amplifiers are used to amplify optical signals to support transmission over longer distances while ensuring the specific performance of optical signals. Optical add-drop multiplexers are used to spatially transform optical signals so that they can be output from different output ports (sometimes also called directions). Electrical layer devices refer to devices that can process electrical layer signals, such as devices that can process OTN signals. Optoelectronic hybrid devices refer to devices that have the ability to process optical layer signals and electrical layer signals. It should be noted that, depending on specific integration needs, an OTN device can integrate multiple different functions. The technical solution provided in this application is applicable to OTN devices of different forms and integration levels that include electrical layer functions.

[0073] Figure 2 is a schematic diagram of the hardware structure of an OTN device applicable to an embodiment of the present application. Specifically, the OTN device may include one or more of a tributary board, a line board, and a cross-connect board. It may also include a system control board, as well as one or more of a power supply, a fan, and an auxiliary board. A line board may also be an optical layer processing board. Depending on specific needs, the type and number of boards included in each device may vary. For example, an OTN device serving as a core node may have no tributary boards. An OTN device serving as an edge node may have multiple tributary boards. Power supply boards are used to power the OTN device and may include primary and backup power supplies. Fan boards are used to dissipate heat. Auxiliary boards provide auxiliary functions such as external alarms or access to external clocks. Tributary boards, cross-connect boards, and line boards primarily process OTN electrical layer signals (also known as OTN frames). Tributary boards are used to receive and transmit various client signals (also known as client services). Client signals may include constant bit rate (CBR) signals (e.g., synchronous digital hierarchy (SDH) signals) and packet signals (e.g., Ethernet signals). Furthermore, the tributary board may include a client-side optical module and a signal processor. The client-side optical module is used to receive and / or transmit client signals. The signal processor is used to map and demap client signals into OTN frames. The signal processor may be located inside or outside the client-side optical module. If the signal processor is a combination of multiple chips, one (or some) of the chips may be inside the client-side optical module, while the other chips may be located outside. The cross-connect board is used to switch OTN frames, for example, switching one or more types of OTN frames. The line board primarily processes line-side OTN frames. Specifically, the line board may include a line-side optical module and a signal processor. The line-side optical module is used to receive and / or transmit optical signals carrying OTN frames. The signal processor is used to multiplex and demultiplex, or map and demap, OTN frames on the line side. The signal processor can be located inside or outside the line-side optical module. If the signal processor is a combination of multiple chips, one (or some) chips are inside the line-side optical module, and the other chips are outside the line-side optical module. Client-side optical modules or line-side optical modules can also be collectively referred to as optical modules or optical transceivers. The signal processor in either the client-side optical module or the line-side optical module can be an optical digital signal processor (oDSP) or a framer, or a combination of a framer and an oDSP.System control boards are used for system control. Specifically, they can collect information from different boards or send control instructions to corresponding boards. Unless otherwise specified, the specific components (e.g., tributary boards) can be one or more, and this application does not impose any restrictions.

[0074] FIG3 is a schematic diagram of the hardware structure of an optical module applicable to an embodiment of the present application. As shown in FIG3 , the optical module may include a signal processor, an optical transmitter component, and an optical receiver component. As described above, the signal processor may include a Framer or an oDSP, or may include a combination of a Framer and an oDSP. The optical module may be a unidirectional optical module, i.e., including either an optical transmitter component or an optical receiver component. The optical module may also be a bidirectional optical module, i.e., including both an optical transmitter component and an optical receiver component.

[0075] A framer, also known as a service chip or physical layer (PHY) chip, is primarily responsible for OTN electrical layer encapsulation / decapsulation (or mapping / demapping). It encapsulates client signals into OTN frames or decapsulates OTN frames to obtain client signals. For example, a framer can encapsulate client signals into ODUs, encapsulate low-rate ODUs into high-rate ODUs, encapsulate ODUs into Flexible OTN (FlexO) frames, or directly encapsulate client signals into FlexO frames. Decapsulation is the reverse of encapsulation.

[0076] The oDSP performs digital signal processing on OTN frames generated by the Framer or on electrical signals received by the optical receiver. The oDSP performs one or more of the following processes: forward error correction (FEC), clock recovery, equalization, sequence detection, and signal decision making.

[0077] FEC is an error control method that encodes the signal according to a certain algorithm before it is sent into the transmission channel, adds redundant data with the signal's own characteristics, and decodes the received signal at the receiving end according to the corresponding algorithm to identify and correct the error codes generated during the transmission process.

[0078] Optical transmitter assembly (OTA), also known as a transmitter optical subassembly (TOSA), is used to convert electrical signals into optical signals. The OTA may include a light source, a driver chip, a modulator, and other components. The light source can be a semiconductor laser (also known as a laser diode (LD) or a light-emitting diode (LED). The driver chip processes the electrical signal generated by the oDSP and drives the light source to emit a modulated optical signal. The modulated optical signal is then transmitted to the optical fiber line via the optical fiber interface.

[0079] Optical receiver assembly: Also known as the receiver optical subassembly (ROSA), it converts optical signals into electrical signals. The optical receiver assembly may include a photodetector and amplifier. The photodetector may be an avalanche photodiode (APD) or a PIN photodiode. The amplifier may include a preamplifier and a postamplifier. After the optical signal enters the optical fiber interface, the photodetector converts it into an electrical signal, which is then output by the amplifier.

[0080] When mapping current OTN signals (such as ODUk and fgODUflex) to FlexO interface signals, they must undergo multiple layers of mapping, such as the ODUCn / OTUCn layer. Furthermore, the mapping granularity of the OTN signal to the FlexO instance differs from the interleaving granularity of the FlexO instance to the FlexO interface signal, resulting in excessive processing overhead and low efficiency. In view of this, the present application proposes a method and apparatus for transmitting data that eliminates the ODUCn / OTUCn layer mapping process, simplifies the process of mapping OTN signals to FlexO interface signals, and improves mapping efficiency.

[0081] Figure 4 is a schematic flowchart of a data transmission method 400 provided in an embodiment of the present application. As shown in Figure 4 , the transmitting device can be an OTN device, or the method can be executed by a component of an OTN device (such as a chip or chip system). The receiving device can be an OTN device, or the method can be executed by a component of an OTN device (such as a chip or chip system). Specifically, the method includes the following steps.

[0082] S410: The sending device maps i first OTN signals to second OTN signals, wherein the second OTN signals include n third OTN signals. The mapping granularity used for mapping the jth first OTN signal in the i first OTN signals to the second OTN signal is n. j *X bytes, the rate of the first OTN signal on the jth channel is n jtimes the base rate, i is an integer greater than or equal to 1, j = 1, 2, 3…i, n j is an integer greater than or equal to 1, and n and X are integers greater than 1.

[0083] S420: The sending device interleaves the second OTN signal based on X bytes to generate a fourth OTN signal.

[0084] S430: The sending device sends a fourth OTN signal, and correspondingly, the receiving device receives the fourth OTN signal.

[0085] S440: The receiving device deinterleaves the fourth OTN signal using X bytes to obtain a second OTN signal, where the second OTN signal includes n third OTN signals.

[0086] S450: The receiving device demaps the second OTN signal to obtain i first OTN signals.

[0087] It should be noted that this application does not limit the generation of i-channel first OTN signals. In some embodiments, i-channel first OTN signals are generated by an OTN device receiving service data and mapping the service data into a first OTN frame. Alternatively, in other embodiments, i-channel first OTN signals are generated by an OTN device receiving an OTN signal from another device, demapping the service data from the OTN signal, and then mapping the service data into the first OTN frame. It is understood that when a receiving device demaps the i-channel first OTN signal from a second OTN signal, the receiving device obtains the service data from the i-channel first OTN signal through demapping.

[0088] Specifically, the i-way first OTN signal is an OTN signal that carries service data, and the i-way first OTN signal can be an ODU signal, for example, it can be an i-way ODUflex. Exemplarily, when the i-way first OTN signal is an ODUflex, the i-way first OTN signals are respectively the first ODUflex#1, the second ODUflex#2, the third ODUflex#3, and the i-th ODUflex#i. For each first OTN signal, its rate can be expressed as an integer multiple of the reference rate. For example, for the j-th first OTN signal, its rate can be expressed as n j *Base rate, where n j is an integer greater than or equal to 1, j = 1, 2, 3 ... i. For example, when the i-th first OTN signal is i-th ODUflex, for the first ODUflex#1, its rate can be expressed as n1*reference rate, for the second ODUflex#2, its rate can be expressed as n2*reference rate, similarly, for the i-th ODUflex#i, its rate can be expressed as n i*The reference rate is not described here. It is understood that the rate of the first OTN signal can also be the same as the reference rate. For example, for the first first OTN signal, if the first first OTN signal has the same rate as the reference rate, then n1 is equal to 1. It is also understood that this application does not limit the rates of the i first OTN signals; they can be completely identical, partially identical, or completely different. It should be noted that in this application, the reference rate can be around 100 Gbit / s, i.e., approximately 100 Gbit / s, for example, 100.844 Gbit / s; or the reference rate can be 100 Gbit / s.

[0089] The second OTN signal is an OTN signal generated by mapping i first OTN signals and includes n third OTN signals. Optionally, the second OTN signal is a FlexO instance. For example, when the second OTN signal is a FlexO instance, the n third OTN signals included in the second OTN signal are FlexO#1, FlexO#2, ..., and FlexO#n, respectively. The rate of each FlexO instance can be the same as the base rate, approximately 100 Gbit / s. For example, the rate of each FlexO instance can be 100.844 Gbit / s, 105643510.782 kbit / s, 100622438.327 kbit / s, and so on.

[0090] The fourth OTN signal is generated by interleaving the second OTN signal. Optionally, the fifth OTN signal is a FlexO interface signal, such as a FlexO-n signal (or other interface signals, refer to the relevant instructions above, which will not be repeated here). The rate of the fifth OTN signal can be 1.2Tbit / s, 1.6Tbit / s, 2.4Tbit / s, 3.2Tbit / s, etc., which is not limited in this application. In the present application scheme, the fourth OTN signal includes at least n time slots (time slot or tributary slot, TS), where n is an integer greater than 1. Each time slot corresponds to a third OTN signal, that is, the size of each time slot can be set to a size corresponding to the rate of each third OTN signal. It can be understood that since the rate of the j-th first OTN signal is n j Therefore, when the rate of the third OTN signal is set to the reference rate, the jth first OTN signal will correspond to the nth in the second OTN signal. j The third OTN signal, that is, the nth OTN signal corresponding to j time slots (the n jFor example, if the first OTN signal i is i ODUflex, the second OTN signal is n FlexO instances, and the fourth OTN signal is FlexO-n, the first OTN signal j, ODUflex#j, will be mapped to n j In the FlexO instance, the n j The FlexO instances will be interwoven into the n in FlexO-n j In a time slot.

[0091] It should be noted that this application involves "mapping" and "interleaving." The difference between "mapping" and "interleaving" can be understood as follows: the mapped signal will generate corresponding mapping overhead during the mapping process, while the interleaved signal will not generate new overhead during the interleaving process. Specifically, in the solution of this application, i-channel first OTN signals are mapped signals. When i-channel first OTN signals are mapped to the second OTN signal, the i-channel first OTN signals are carried in the payload area of ​​the second OTN signal. At the same time, the overhead generated by the mapping process is carried in the overhead area of ​​the second OTN signal. The n-channel third OTN signals in the second OTN signal are interleaved signals. When the n-channel third OTN signals are interleaved to the fourth OTN signal, the n-channel third OTN signals are rearranged and multiplexed into the fourth OTN signal. This process does not generate new overhead, and the content of the n-channel third OTN signals does not change.

[0092] In the present application, the mapping granularity of each first OTN signal mapped to the second OTN signal is a multiple of the interleaving granularity of the second OTN signal (i.e., n third OTN signals) interleaved to the fourth OTN signal. For example, for the jth first OTN signal, the mapping granularity of its mapping to the second OTN signal is n. j *X bytes, the interleaving granularity when the second OTN signal is interleaved to generate the fourth OTN signal is X bytes, that is, for the j-th first OTN signal, the mapping granularity is n times the interleaving granularity. j It should be noted that for the first OTN signal on the jth path, n j It is also the multiple of the rate of the first OTN signal of the jth channel and the reference rate, that is, when n jWhen n is equal to 1, the mapping granularity of the j-th first OTN signal mapped to the second OTN signal is the same as the interleaving granularity when the second OTN signal is interleaved to generate the fourth OTN signal, both of which are X bytes. In other words, for the first OTN signal with a rate of the reference rate, the mapping granularity of the first OTN signal mapped to the second OTN signal is X bytes. For example, when the reference rate is 100Gbit / s and X is 32, if the rate of the j-th first OTN signal is 400Gbit / s, then the rate of the j-th first OTN signal is 4*100Gbit / s. At this time, n j Equal to 4. The mapping granularity of the first OTN signal with a rate of 400 Gbit / s to the second OTN signal is 4*32 bytes. At the same time, the second OTN signal is interleaved based on 32 bytes to generate a fourth OTN signal.

[0093] It should be noted that, in the present application, the value of X is not limited, for example, it can be equal to 32, 16, 64, etc. In addition, in the exemplary description of the present application, the mapping granularity or interleaving granularity is described in bytes. In some embodiments, the mapping granularity or interleaving granularity can also be described in bits. For example, the mapping granularity used for mapping the j-th first OTN signal to the second OTN signal is n. j *Y bits. It should be noted that when bits are used as the unit to describe the mapping granularity or interleaving granularity, this application does not limit whether Y bits correspond to an integer number of bytes, that is, Y bits can be an integer number of bytes, or not. It is understandable that when Y bits correspond to an integer number of bytes, the mapping granularity or interleaving granularity can be expressed in bytes or bits. For example, the mapping granularity used for mapping the j-th first OTN signal to the second OTN signal is n j *X bytes, which can also be expressed as the mapping granularity of the j-th first OTN signal to the second OTN signal is n j *8*X bits, where Y = 8*X. Similarly, the interleaving granularity when the second OTN signal is interleaved to generate the fourth OTN signal is X bytes, which can also be expressed as the interleaving granularity when the second OTN signal is interleaved to generate the fourth OTN signal is 8*X bits. When Y bits correspond to a non-integer number of bytes, the mapping granularity or interleaving granularity is generally expressed in bits, and in this case, Y is not equal to 8*X.

[0094] In the present application, mapping i first OTN signals to second OTN signals (i.e., n third OTN signals) includes two implementation methods. Specifically, in one implementation method, each first OTN signal is directly mapped to n third OTN signals of the second OTN signal, and the n third OTN signals are not grouped. Alternatively, in another implementation method, the n third OTN signals of the second OTN signal are grouped, so that each first OTN signal is mapped to multiple third OTN signals in the corresponding group. It should be noted that in the second method, the multiple third OTN signals in the group corresponding to each first OTN signal can be understood as constituting a new OTN signal. When interleaving to generate a fourth OTN signal, it can be understood that the new OTN signals mapped from each first OTN signal are interleaved to generate the fourth OTN signal. The following describes these two methods separately.

[0095] Method 1: Each first OTN signal is directly mapped to n third OTN signals of the second OTN signal, and the n third OTN signals are not grouped.

[0096] Specifically, when each first OTN signal is directly mapped to the second OTN signal, each first OTN signal is mapped to one or more of the n third signals of the second OTN signal. For example, the jth first OTN signal adopts n third signals. j *X bytes map to n j Among the third OTN signals, the n j The third OTN signal is a part of the n third signals. After the mapping of the i first OTN signals is completed, the n third signals are interleaved with X bytes to generate a fourth OTN signal.

[0097] For example, the first data transmission method provided by the present application is described in conjunction with Figure 5. Figure 5 is a schematic diagram of the first method provided by the present application, which maps i ODUflex signals to n FlexO instances using integer multiples of 32 bytes (or 256 bits), and interweaves n FlexO instances using 32 bytes to generate a FlexO-n signal. As shown in Figure 5, the i ODUflex signals are the first ODUflex signal ODUflex#1, the second ODUflex signal ODUflex#2, etc., and the i-th ODUflex signal ODUflex#i. The i ODUflex signals have the same frame structure and can have the same or different rates. The i ODUflex signals can also be signals that carry different service data, without limitation. The FlexO-n signal is divided into at least n 100G time slots, each 100G time slot corresponds to a 100G FlexO instance. In other words, the FlexO-n signal includes at least n 100G FlexO instances, each 100G FlexO instance corresponding to one 100G time slot. Specifically, ODUflex#1 can be mapped to any n1-way FlexO instance based on a mapping granularity of n1*256 bits using a generic mapping procedure (GMP). Similarly, ODUflex#2 can be mapped to an n2-way FlexO instance based on a mapping granularity of n2*256 bits using a GMP mapping method. ODUflex#i can be mapped to an n2-way FlexO instance based on a mapping granularity of n2*256 bits using a GMP mapping method. i *256-bit mapping granularity is mapped to n i FlexO instances, and finally get n FlexO instances, n = n1 + n2 + ... + n i It should be noted that the n1-way FlexO instance of ODUflex#1 is any n1-way FlexO instance. During the mapping process, the first 256 bits of the n1*256 bits of the ODUflex#1 signal are mapped to the x1-th way in the n-way FlexO instance, the second 256 bits are mapped to the x2-th way in the n-way FlexO instance, and so on. The n1-th 256 bits are mapped to the x2-th way in the n-way FlexO instance. n1 In the middle of the road, x1 <x2<x n1 Similarly, the n2-way FlexO instance of ODUflex#2 is any n2-way FlexO instance. During the mapping process, the first 256 bits of the n2*256 bits of the ODUflex#2 signal are mapped to the y1-th way in the n-way FlexO instance, the second 256 bits are mapped to the y2-th way in the n-way FlexO instance, and so on. The n1-th 256 bits are mapped to the y2-th way in the n-way FlexO instance.n2 In the middle of the road, y1 <y2<y n2 ODUflex#i i A FlexO instance is any n of the n FlexO instances. i During the mapping process, the n i * The first 256 bits of the 256 bits are mapped to the z1th path in the n-path FlexO instance, the second 256 bits are mapped to the z2th path in the n-path FlexO instance, and so on. The n1th 256 bits are mapped to the zth path in the n-path FlexO instance. ni Road, where z1 <z2<z ni .

[0098] When n FlexO instances are interwoven to generate a FlexO-n signal, it is composed of n1 FlexO instance frames, n2 FlexO instances, and so on. i FlexO instance frames are interleaved with a 256-bit interleaving granularity to generate FlexO-n signals. Specifically, for n1 FlexO instances mapped to ODUflex#1, the n1 FlexO instances are interleaved to any n1 time slots in FlexO-n, such as time slot x1, time slot x2, ..., time slot x n1 , x1 <x2<x n1 , where time slot x1, time slot x2, ..., time slot x n1 They correspond to the 1st, 2nd, ... n1th channels of the n1-channel FlexO instance, that is, the x1th, x2th, ..., xth channels in the n-channel FlexO instance. n1 That is, the first 256 bits of the n1*256 bits of the ODUflex#1 signal are carried in time slot x1, the second 256 bits are carried in time slot x2, ..., the n1th 256 bits are carried in time slot x n1 It should be noted that the n1 time slots corresponding to the n1-way FlexO instance are any n1 of at least n time slots in FlexO-n. Therefore, the above-mentioned time slot x1 and time slot x2 can be two adjacent time slots, or two non-adjacent time slots. That is, the n1 time slots are not necessarily continuous. Similarly, for the n2-way FlexO instance mapped by ODUflex#2, the n2-way FlexO instance is interwoven into any n2 time slots in FlexO-n, such as time slot y1, time slot y2, ..., time slot y n2 , y1 <y2<y n2 , where time slot y1, time slot y2, ..., time slot y n2They correspond to the 1st, 2nd, ... n2th channels of the n2-channel FlexO instance, that is, the y1th, y2th, ..., yth channels in the n-channel FlexO instance. n2 That is, the first 256 bits of the n2*256 bits of the ODUflex#2 signal are carried in time slot y1, the second 256 bits are carried in time slot y2, ..., the n2th 256 bits are carried in time slot y n2 For ODUflex#i mapping n i For example, the n i FlexO instances are interwoven into any n FlexO-n instances. i time slots, for example, time slot z1, time slot z2, ..., time slot z n1 , z1 <z2<z ni , where time slot z1, time slot z2, ..., time slot z ni Corresponding to n i The first, second, ..., nth FlexO instance i The z1th, z2th, ..., zth, etc. ni Channel, that is, n of ODUflex#i signal i * The first 256 bits of the 256 bits are carried in time slot z1, the second 256 bits are carried in time slot z2, ..., the nth 256 bits are carried in time slot z1, the nth 256 bits are carried in time slot z2, ..., the nth i 256 bits are carried in time slot z ni It can be understood that, for each ODUflex signal, the mapping granularity thereof to the second OTN signal can be expressed as the number of time slots corresponding to each ODUflex signal*256 bits.

[0099] It is understandable that since the number of time slots included in the FlexO-n signal is greater than or equal to n, when the number of time slots included in the FlexO-n signal is equal to n, the n FlexO instances mapped to the i-channel ODUflex signal occupy n time slots in the FlexO-n signal, that is, all time slots in the FlexO-n signal are used to carry valid signals. When the number of time slots included in the FlexO-n signal is greater than n, some 100G time slots in the FlexO-n signal are idle (that is, there are 100G FlexO instances that are not mapped with ODUflex signals) and are not used to carry ODUflex signals. These unoccupied 100G time slots (that is, the payload areas of the 100G FlexO instances that are not mapped with ODUflex signals) can be fixedly filled.

[0100] Method 2: Each first OTN signal is mapped to multiple third OTN signals in corresponding groups.

[0101] Specifically, n third OTN signals are divided into i groups according to i first OTN signals, wherein the number of third OTN signals included in the jth group is n. j , the n j The third OTN signal constitutes a new OTN signal, which can be called an intermediate OTN signal, and is used to carry the jth first OTN signal. For example, if the third OTN signal is a FlexO instance, then the nth OTN signal in the jth packet j The OTN signal composed of the third OTN signal can be FlexO-n j Signal, at this time, the first OTN signal of the jth channel adopts n j *X bytes mapped to FlexO-n j It is understandable that after the corresponding mapping of i first OTN signals is completed, the new OTN signal mapped to each first OTN signal (such as FlexO-n1 signal, FlexO-n2 signal, ..., FlexO-n i signal) uses X bytes to interleave to generate a fourth OTN signal.

[0102] For example, the second method of transmitting data provided by the present application is described in conjunction with FIG6. Taking the ODUflex signal as an example, the ODUflex signal is mapped to FlexO-n with a 32-byte (ie, 256-bit) granularity.

[0103] Figure 6 is a schematic diagram of a second embodiment of the present application, which maps i ODUflex signals to n FlexO instances using integer multiples of 32 bytes (or 256 bits), and interweaves n FlexO instances using 32 bytes to generate a FlexO-n signal. As shown in Figure 6, the i ODUflex signals are the first ODUflex signal ODUflex#1, the second ODUflex signal ODUflex#2, etc., and the i-th ODUflex signal ODUflex#i, wherein the i ODUflex signals have the same frame structure, can be the same or different rates, and can also carry different service data. The FlexO-n signal is divided into at least n 100G time slots, each 100G time slot corresponds to a 100G FlexO instance. In other words, the FlexO-n signal contains at least n 100G FlexO instances, each 100G FlexO instance corresponds to one 100G time slot. Specifically, ODUflex#1 adopts GMP mapping and is mapped to FlexO-n1 signal based on the mapping granularity of n1*256 bits. The FlexO-n1 signal corresponds to n1 FlexO instances. Meanwhile, ODUflex#2 adopts GMP mapping and is mapped to FlexO-n2 signal based on the mapping granularity of n2*256 bits. The FlexO-n2 signal corresponds to n2 FlexO instances. And ODUflex#i adopts GMP mapping and is mapped to n i *256-bit mapping granularity mapped to FlexO-n i signal, the FlexO-n i Signal corresponding to n i After the mapping of i-channel ODUflex signals is completed, the FlexO-n1 frame, FlexO-n2 frame, or FlexO-n2 frame generated after the mapping of each ODUflex signal is generated. i The frame is interleaved again with a 256-bit interleaving granularity to generate a FlexO-n signal, where n = n1 + n2 + ... + n i .

[0104] It can be understood that for the n1-way FlexO instance corresponding to the FlexO-n1 signal, the 1st, 2nd, ..., n1th of the n1-way FlexO instance correspond to the x1th, x2th, ..., xth of the n-way FlexO instance. n1 The time slots x1, x2, ..., x3, etc. in the FlexO-n signal are n1 For the n2-way FlexO instance corresponding to the FlexO-n2 signal, the 1st, 2nd, ..., n2th channels of the n2-way FlexO instance correspond to the y1th, y2th, ..., yth channels of the n-way FlexO instance.n2 , that is, time slot y1, time slot y2, ..., time slot y in the FlexO-n signal n2 For FlexO-n i The signal corresponding to n i FlexO instance, the n i The first, second, ..., nth FlexO instance i The z1th, z2th, ..., zth, etc. ni The time slot z1, time slot z2, ..., time slot z in the FlexO-n signal ni .

[0105] It should be noted that the present application solution does not limit the mapping method of i-channel first OTN signal to the second OTN signal. For example, it can be GMP shown in FIG. 5 or FIG. 6 above.

[0106] It should also be noted that, in this application, the fourth OTN signal overhead is not limited. Optionally, the fourth OTN signal overhead area may include at least one of the following: Trail Trace Identifier (TTI), X-Bit Interleaved Parity (BIP-X), Backward Error Indication (BEI), Backward Defect Indication (BDI), Status (STAT), Payload Type (PT), Multiplex Structure Identifier (MSI), Tributary Port Identifier (TPID), and Occupation (OCCU). The PT indicates the 100G timeslot granularity. It should be understood that the value of this timeslot granularity is only approximate. For details, please refer to the above description.

[0107] The above, in combination with Figures 4 to 6, illustrates the method for transmitting data provided in the embodiments of the present application. In the various embodiments of the present application, unless otherwise specified or there is a logical conflict, the terms and / or descriptions between the various embodiments are consistent and can be referenced by each other. The technical features in different embodiments can be combined to form new embodiments according to their internal logical relationships.

[0108] The following describes in detail the apparatus, device, and chip system for transmitting data provided by the embodiments of the present application in conjunction with Figures 7 and 9. It should be understood that the description of the apparatus embodiment corresponds to the description of the method embodiment. Therefore, for matters not described in detail, please refer to the method embodiment above. For the sake of brevity, some contents will not be repeated.

[0109] FIG7 is a schematic block diagram of a data transmission apparatus 700 provided in an embodiment of the present application. The data transmission apparatus 700 includes a receiving module 701, which can be used to implement corresponding receiving functions. The receiving module 701 can also be referred to as a receiving unit.

[0110] The data transmission device 700 further includes a processing module 702 , which can be used to implement corresponding processing functions.

[0111] The data transmission device 700 further includes a sending module 703 . The sending module 703 may be configured to implement a corresponding sending function. The sending module 703 may also be referred to as a sending unit.

[0112] Optionally, the device 700 for transmitting data also includes a storage unit, which can be used to store instructions and / or data. The processing unit 702 can read the instructions and / or data in the storage unit so that the device implements the actions of the relevant nodes in the aforementioned various method embodiments.

[0113] The device 700 for transmitting data can be used to execute the actions performed by the sending device or the receiving device in the above method embodiments. In this case, the device 700 for transmitting data can be a component of the sending device or the receiving device, the receiving module 701 is used to execute the reception-related operations of the sending device or the receiving device in the above method embodiments, the processing module 702 is used to execute the processing-related operations of the sending device or the receiving device in the above method embodiments, and the sending module 703 is used to execute the sending-related operations of the sending device or the receiving device in the above method embodiments.

[0114] As a design, the data transmission device 700 is used to perform the actions performed by any device in the above various method embodiments. In one embodiment, the data transmission device 700 can be used to perform the operations of the sending device in Figure 4 above. For example:

[0115] The processing module 702 is configured to map i first OTN signals to second OTN signals, and to generate a fourth OTN signal based on an X-byte interleaving granularity from the second OTN signals. The second OTN signal includes n third OTN signals, and the mapping granularity used for mapping the j-th first OTN signal in the i first OTN signals to the second OTN signal is n. j *X bytes, the rate of the first OTN signal on the jth channel is nj times the base rate. i is an integer greater than or equal to 1, j = 1, 2, 3…i, n j is an integer greater than or equal to 1, and n and X are integers greater than 1.

[0116] The sending module 703 is configured to send a fourth OTN signal.

[0117] It should be understood that the specific process of each module executing the above corresponding steps has been described in detail in the above method embodiment, and for the sake of brevity, it will not be repeated here.

[0118] In addition, the receiving module 701, the processing module 702 and the sending module 703 in the apparatus 700 for transmitting data may also implement other operations or functions of the receiving device in the above method, which will not be described in detail here.

[0119] In another embodiment, the apparatus may be used to perform the operations of the receiving device in FIG4 . For example:

[0120] The receiving module 701 is configured to receive a fourth OTN signal.

[0121] The processing module 702 is configured to deinterleave the fourth OTN signal with X bytes to obtain a second OTN signal, and demap i first OTN signals from the second OTN signal. The second OTN signal includes n third OTN signals. The mapping granularity used for mapping the jth first OTN signal in the i first OTN signals to the second OTN signal is n. j *X bytes, the rate of the first OTN signal on the jth channel is n j times the base rate, i is an integer greater than or equal to 1, j = 1, 2, 3…i, n j is an integer greater than or equal to 1, and n and X are integers greater than 1.

[0122] It should be understood that the specific process of each module executing the above corresponding steps has been described in detail in the above method embodiment, and for the sake of brevity, it will not be repeated here.

[0123] Next, the apparatus for processing service signal transmission data provided by an embodiment of the present application will be described in detail with reference to FIG8 . It should be understood that the description of the apparatus embodiment corresponds to the description of the method embodiment. Therefore, for matters not described in detail, reference can be made to the method embodiment above. For the sake of brevity, some of the contents will not be repeated here.

[0124] Figure 8 is a schematic diagram of the structure of a possible data transmission device provided in an embodiment of the present application. The communication device is a transmitting device or a receiving device. As shown in Figure 8, the communication device 800 includes a processor 801, an optical transceiver 802, and a memory 803. Among them, the memory 803 is optional. The communication device 800 can be applied to both a transmitting-side device (e.g., a transmitting device) and a receiving-side device (e.g., the receiving device described above).

[0125] When used in a transmitting device, processor 801 and optical transceiver 802 are used to implement the method performed by the transmitting device shown in Figure 4. During implementation, each step of the processing flow can be completed by hardware integrated logic circuits in processor 801 or software instructions to complete the method performed by the transmitting device shown in the above figure. Optical transceiver 802 is used to receive, process, and transmit data frames to a peer node (also referred to as a receiving device).

[0126] When applied to a receiving device, processor 801 and optical transceiver 802 are used to implement the method performed by the receiving device shown in Figure 4. During implementation, each step of the processing flow can be completed by hardware integrated logic circuits in processor 801 or software instructions to complete the method performed by the receiving device described in the above figures. Optical transceiver 802 is used to receive data frames sent by a peer device (also called a transmitting device) and transmit them to processor 801 for subsequent processing.

[0127] The memory 803 may be used to store instructions so that the processor 801 can be used to perform the steps mentioned in the above figure. Alternatively, the memory 803 may also be used to store other instructions to configure the parameters of the processor 801 to implement corresponding functions.

[0128] It should be noted that, in the network device hardware structure diagram shown in FIG2 , the processor 801 and memory 803 may be located in a tributary board, or may be located in a single board that combines the tributary and line boards. Alternatively, both the processor 801 and memory 803 may include multiple components, located in the tributary board and the line board, respectively, with the two boards cooperating to complete the aforementioned method steps.

[0129] It should be noted that the apparatus described in FIG. 8 can also be used to execute the method steps involved in the embodiment variations shown in the aforementioned figures, which will not be described in detail here.

[0130] 9 is a schematic diagram of a chip system 900 according to an embodiment of the present application. The chip system 900 (or also referred to as a processing system) includes a logic circuit 910 and an input / output interface 920 .

[0131] The logic circuit 910 may be a processing circuit in the chip system 900. The logic circuit 910 may be coupled to a storage unit and call instructions in the storage unit so that the chip system 900 can implement the methods and functions of the various embodiments of the present application. The input / output interface 920 may be an input / output circuit in the chip system 900, outputting information processed by the chip system 900 or inputting data or signaling information to be processed into the chip system 900 for processing.

[0132] Alternatively, the logic circuit 910 may be implemented by one or more processors, including the one or more processors or a processing portion in the one or more processors.

[0133] Optionally, the input / output interface 920 may include a transceiver circuit, a transceiver, an input / output circuit, or a communication interface.

[0134] As a solution, the chip system 900 is used to implement the operations performed by the sending device or the receiving device in the above various method embodiments.

[0135] Specifically, the logic circuit 910 is used to implement the processing-related operations performed by the sending device or the receiving device in the above method embodiment; the input / output interface 920 is used to implement the sending and / or receiving-related operations performed by the sending device or the receiving device in the above method embodiment.

[0136] An embodiment of the present application further provides a computer-readable storage medium storing computer instructions for implementing the methods executed by the first device or the ONU device in the above-mentioned method embodiments.

[0137] For example, when the computer program is executed by a computer, the computer can implement the method performed by the first device or the ONU device in each embodiment of the above method.

[0138] Based on the above embodiments, embodiments of the present application further provide a computer-readable storage medium. This storage medium stores a software program that, when read and executed by one or more processors, can implement the methods provided in any one or more of the above embodiments. The computer-readable storage medium may include any medium capable of storing program code, such as a USB flash drive, a mobile hard drive, a read-only memory, a random access memory, a magnetic disk, or an optical disk.

[0139] Obviously, those skilled in the art can make various changes and modifications to the embodiments of the present application without departing from the scope of the embodiments of the present application. Thus, if these modifications and variations of the embodiments of the present application fall within the scope of the claims of the present application and their equivalents, the present application also intends to include these modifications and variations.

[0140] It should be understood that the processor mentioned in the embodiments of the present application may be a central processing unit (CPU), or may be other general-purpose processors, digital signal processors (DSP), application-specific integrated circuits (ASIC), field programmable gate arrays (FPGA) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. The general-purpose processor may be a microprocessor or any conventional processor, etc.

[0141] It should also be understood that the memory mentioned in the embodiments of the present application may be a volatile memory and / or a non-volatile memory. Among them, the non-volatile memory may be a read-only memory (ROM), a programmable read-only memory (PROM), an erasable programmable read-only memory (EPROM), an electrically erasable programmable read-only memory (EEPROM), or a flash memory. The volatile memory may be a random access memory (RAM). For example, RAM can be used as an external cache. By way of example and not limitation, RAM may include the following forms: static random access memory (SRAM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), double data rate synchronous dynamic random access memory (DDR SDRAM), enhanced synchronous dynamic random access memory (ESDRAM), synchronous link dynamic random access memory (SLDRAM), and direct rambus RAM (DR RAM).

[0142] It should be noted that when the processor is a general-purpose processor, DSP, ASIC, FPGA or other programmable logic device, discrete gate or transistor logic device, or discrete hardware component, the memory (storage module) can be integrated into the processor.

[0143] Those skilled in the art will appreciate that the units and steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented using electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Professionals and technicians may use different methods to implement the described functions for each specific application; such implementations should not be considered to exceed the scope of protection of this application.

[0144] In the several embodiments provided in this application, it should be understood that the disclosed devices and methods can be implemented in other ways. For example, the device embodiments described above are only schematic. For example, the division of the units is only a logical function division. In actual implementation, there may be other division methods, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. In addition, the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of devices or units, which can be electrical, mechanical or other forms.

[0145] In the above embodiments, it can be implemented in whole or in part by software, hardware, firmware or any combination thereof. When implemented using software, it can be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, the process or function described in the embodiment of the present application is generated in whole or in part. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. For example, the computer can be a personal computer, a server, or a network device, etc. The computer instructions can be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another computer-readable storage medium. For example, the computer instructions can be transmitted from one website, computer, server or data center to another website, computer, server or data center by wired (e.g., coaxial cable, optical fiber, digital subscriber line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.) mode. The computer-readable storage medium can be any available medium that a computer can access or a data storage device such as a server or data center that includes one or more available media integrations. The available medium may be a magnetic medium (e.g., a floppy disk, a hard disk, a magnetic tape), an optical medium (e.g., a DVD), or a semiconductor medium (e.g., a solid state disk (SSD)). For example, the aforementioned available medium may include, but is not limited to, various media that can store program code, such as a USB flash drive, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk, or an optical disk.

[0146] The above description is merely a specific embodiment of the present application, but the scope of protection of the present application is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in this application should be included in the scope of protection of this application. Therefore, the scope of protection of this application should be based on the scope of protection of the claims.

Claims

1. A method for transmitting data, characterized in that: include: Mapping i first optical transport network OTN signals to second OTN signals, wherein the second OTN signals include n third OTN signals, and the mapping granularity used for mapping the jth first OTN signal in the i first OTN signals to the second OTN signal is n j *X bytes, the rate of the j-th first OTN signal is n j times the base rate, i is an integer greater than or equal to 1, j = 1, 2, 3…i, n j is an integer greater than or equal to 1, and n and X are integers greater than 1; Generate a fourth OTN signal based on an X-byte interleaving granularity from the second OTN signal; The fourth OTN signal is sent.

2. The method according to claim 1, characterized in that The X is 32.

3. The method according to claim 1 or 2, characterized in that The fourth OTN signal includes n time slots, and the second OTN signal mapped to the j-th first OTN signal is n timeslots in the n time slots. j time slots.

4. The method according to claim 3, characterized in that Each of the n time slots is 100G.

5. The method according to any one of claims 1 to 4, characterized in that The n-way third OTN signal is an n-way flexible optical network FlexO instance, and the second OTN signal mapped by the j-th first OTN signal is n j The fourth OTN signal includes the n FlexO instances, and the rate of each of the n FlexO instances is 100 Gbit / s.

6. The method according to any one of claims 1 to 4, characterized in that The n-way third OTN signal is an n-way FlexO instance, and the second OTN signal mapped to the j-th first OTN signal is n-way FlexO instance. j The fourth OTN signal includes the n FlexO instances, and the rate of each FlexO instance in the n FlexO instances is 100 Gbit / s.

7. The method according to any one of claims 1 to 6, characterized in that n=n1+n2+……+n j +n i 。 8. The method according to any one of claims 1 to 7, characterized in that The rate of the j-th first OTN signal is 100Gbit / s*n j .

9. The method according to any one of claims 1 to 8, characterized in that The fourth OTN signal rate is 1.6 Tbit / s.

10. The method according to any one of claims 1 to 9, characterized in that The fourth OTN signal includes an overhead area, the overhead area includes a payload type PT, and the PT indicates that the time slot granularity is 100 Gbit / s.

11. The method according to any one of claims 1 to 10, characterized in that The first OTN signal is an optical data unit (ODU) or a FlexO channel layer signal.

12. A method for transmitting data, characterized in that: include: receiving a fourth OTN signal; Deinterleaving the fourth OTN signal using X bytes to obtain a second OTN signal, where the second OTN signal includes n third OTN signals; Demap i first OTN signals from the second OTN signal, and map the j-th first OTN signal in the i first OTN signals to the second OTN signal using a mapping granularity of n j *X bytes, the rate of the j-th first OTN signal is n j times the base rate, i is an integer greater than or equal to 1, j = 1, 2, 3…i, n j is an integer greater than or equal to 1, and n and X are integers greater than 1.

13. The method according to claim 12, characterized in that The X is 32.

14. The method according to claim 12 or 13, characterized in that The fourth OTN signal includes n time slots, and the second OTN signal mapped to the j-th first OTN signal is n timeslots in the n time slots. j time slots.

15. The method according to claim 14, characterized in that Each of the n time slots is 100G.

16. The method according to any one of claims 12 to 15, characterized in that The n-way third OTN signal is an n-way flexible optical network FlexO instance, and the second OTN signal mapped by the j-th first OTN signal is n j The fourth OTN signal includes the n FlexO instances, and the rate of each of the n FlexO instances is 100 Gbit / s.

17. The method according to any one of claims 12 to 15, characterized in that The n-way third OTN signal is an n-way FlexO instance, and the second OTN signal mapped to the j-th first OTN signal is n-way FlexO instance. j The fourth OTN signal includes the n FlexO instances, and the rate of each FlexO instance in the n FlexO instances is 100 Gbit / s.

18. The method according to any one of claims 12 to 17, characterized in that n=n1+n2+……+n j +n i 。 19. The method according to any one of claims 12 to 18, characterized in that The rate of the j-th first OTN signal is 100Gbit / s*n j .

20. The method according to any one of claims 12 to 19, characterized in that The fourth OTN signal rate is 1.6 Tbit / s.

21. The method according to any one of claims 12 to 20, characterized in that The fourth OTN signal includes an overhead area, the overhead area includes a payload type PT, and the PT indicates that the time slot granularity is 100 Gbit / s.

22. The method according to any one of claims 12 to 21, characterized in that The first OTN signal is an optical data unit (ODU) or a FlexO channel layer signal.

23. A network device, characterized in that: include: A processor and an input / output interface for executing the method according to any one of claims 1 to 11, or executing the method according to any one of claims 12 to 22, wherein: The input and output interfaces are used to send and receive OTN signals; The processor is configured to process the OTN signal.

24. An optical module, characterized in that: The optical module includes a signal processor and an optical transmission component, wherein: The signal processor is configured to perform the method according to any one of claims 1 to 11; The optical transmission component is used to convert the fourth OTN signal into an optical signal and send the optical signal.

25. An optical module, characterized in that: The optical module includes a signal processor and a light receiving component, wherein: The optical receiving component is configured to receive an optical signal and convert the optical signal into the fourth OTN signal; The signal processor is configured to execute the method according to any one of claims 12 to 22.

26. An optical chip, characterized in that: The chip includes a processor and a communication interface, wherein: The processor is configured to execute the method according to any one of claims 1 to 11; The communication interface is configured to convert the fourth OTN signal into an optical signal and send the optical signal.

27. An optical chip, characterized in that: The chip includes a processor and a communication interface, wherein: The communication interface is configured to receive an optical signal and convert the optical signal into the fourth OTN signal; The processor is configured to execute the method according to any one of claims 12 to 22.

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