Electrical circuit arrangement having a transistor-based switch, and method for switching the transistor-based switch

Abstract

Proposed is an electrical circuit arrangement having an input contact (in) which is switchably connected via two series-connected transistors (T1, T2) to an output contact (out), wherein source contacts respectively assigned to the two transistors are interconnected, and gate contacts respectively assigned to the two transistors are interconnected, and the source and gate contacts of the two transistors are connected, with the ability to be switched on and off, to at least one current source (I) that is suitably designed to generate at the two transistors a source / gate voltage (Vgs_1, 2) that is higher than the respectively associated threshold voltages of the transistors. Furthermore, the source and gate contacts of the two transistors can be connected to a circuit unit (T4, T5, D5) which is suitably designed to equalize the gate voltage and the source voltage of each of the two transistors as soon as the current source is disconnected from the source and gate contacts of the two transistors. Also proposed is a method for switching the transistor-based switch. The electrical circuit arrangement is distinguished by the fact that the current source is connected to a high-voltage supply voltage (HV) and can be connected via an ON / OFF switching functional unit (SE) to a functional unit (T_D1), which is connected in series and causes a voltage drop, and to a source-drain path of a third transistor (T3), which is connected to a low-voltage supply voltage (LV), and by the fact that the gate contacts of the two transistors are connected via the ON / OFF switching functional unit (SE) to the current source (I), and the source contacts of the two transistors are connected to the gate contact of the third transistor (T3).

Description

[0001] Electrical circuit arrangement with transistor-based switch and method for switching the transistor-based switch

[0002] Technical area

[0003] The invention relates to an electrical circuit arrangement having an input contact that is switchably connected to an output contact via two series-connected transistors. A source contact associated with each of the two transistors is connected to one another, and a gate contact associated with each of the two transistors is connected to one another. The source and gate contacts of the two transistors are connected to at least one current source that can be switched on and off, and is designed to generate a source / gate voltage across the two transistors that is greater than their respective associated threshold voltage. Furthermore, a method for switching the transistor-based switch is described.

[0004] State of the art

[0005] Switches that assume two switching states, for example, switchable between "closed" and "open," or "on" and "off," are among the most important components in electrical circuits. Integrated electrical circuits use semiconductor components, usually in the form of transistors, as switches. These components, in various circuit configurations, for example, in the form of transmission gates, enable bidirectional switching for electrical currents. The quality of such components depends not least on their ability to conduct no current when switched "off."

[0006] "Off" switching states are characterized by semiconductor regions in semiconductor components that are polarized in the reverse direction, but in which a small current flows in the reverse direction, known as leakage current, still occurs. Leakage currents occur particularly in power semiconductors, such as high-voltage CMOS components, for a variety of reasons, the severity of which increases with increasing temperatures.

[0007] The relevance of leakage currents must be assessed depending on the application of such switches. A particularly preferred area of ​​application in this case concerns implantable electronic devices used to treat various types of neurological dysfunctions by stimulating nerves with electrical charge. The electrical circuitry underlying these implants represents multifunctional, highly integrated circuits designed with the highest operational reliability, maximum energy efficiency, and the greatest possible miniaturization. Particularly in the case of intracorporeal electrical stimulation of certain body regions, e.g., nerve fibers, leakage currents via electrodes that contact biological tissue areas are unsustainable. Leakage currents can thus permanently lead to charge integration on electrodes, which must be prevented.

[0008] An example of a bidirectional analog high-voltage switch is disclosed in US Pat. No. 4,595,847 A, which is implemented with a pair of depletion-mode MOS transistors whose source contacts are connected to each other and whose gate contacts are connected to each other. The drain contacts form the high-voltage input terminal and the high-voltage output terminal. However, leakage currents can flow via a diode connected in reverse bias to the source contacts.

[0009] The publication US 10 517 570 B2 discloses a circuit for operating an ultrasonic transducer in which the switching transistors are short-circuited in the off-state by short-circuiting the gate contacts and the source contacts of both switching transistors via a source-drain path of another transistor. However, any leakage currents occurring between the switching transistors in the off-state cannot be ruled out in the known circuit due to an electrical connection path between the source contacts of the switching transistors and the supply voltage Vdd.

[0010] Description of the invention

[0011] The invention is based on the object of an electrical circuit arrangement with an input contact which is switchably connected to an output contact via two series-connected transistors, wherein a source contact assigned to each of the two transistors is connected to one another and a gate contact assigned to each of the two transistors is connected to one another, and the source and gate contacts of the two transistors are connected to at least one current source which can be switched on and off and which is designed to generate a source / gate voltage at the two transistors which is greater than their respectively assigned threshold voltage, wherein the source and gate contacts of the two transistors are connectable to a circuit unit which is designed to equalize the gate voltage and the source voltage of the two transistors to one another as soon as the current source is disconnected from the source and gate contacts of the two transistors,to be further developed in such a way that no or only negligible leakage currents can develop within the switch arrangement, which is in the "off" state, ie the transistors involved in the switching process are blocked. The resistance R attributable to the transistors involved in this case, O ff should be as large as possible. In this context, operational reliability, energy efficiency, and miniaturization must be significantly improved compared to previously implemented circuit arrangements of this type.

[0012] The solution to the problem underlying the invention is defined in claim 1. The subject matter of claim 19 is a method according to the invention for switching a transistor-based switch. Features that advantageously further develop the inventive concept are the subject matter of the dependent claims and the further description, in particular with reference to the figures.

[0013] The electrical circuit arrangement according to the solution with the features of the preamble of claim 1 is characterized in that the power source is connected to a high-voltage supply voltage and can be connected via an ON / OFF switching function unit to a series-connected voltage-drop-causing function unit and to a source-drain path of a third transistor, which is connected to a low-voltage supply voltage. Furthermore, the gate contacts of the two transistors are connected to the power source via the ON / OFF switching function unit, and the source contacts of the two transistors are connected to the gate contact of the third transistor.

[0014] By contacting the two transistors with the rest of the circuit arrangement exclusively via high-impedance paths, such as gate contacts, i.e. on the one hand, the two transistors are connected to the ON / OFF switching function unit via their own gate contacts and on the other hand the source contacts of the two transistors are connected to the gate contact of the third transistor, the two transistors are decoupled from both the high-voltage and the low-voltage supply voltage in the OFF switching state or are connected to them via very high-impedance current paths, so that any current flowing between the two transistors originates exclusively, or almost exclusively, from a potential prevailing between the input and output contacts. The circuit arrangement therefore has no influence on the two transistors in the OFF switching state, nor, for that matter, in the ON switching state.

[0015] The novel switching concept, in particular for the realization of high-voltage robust CMOS switches with negligible leakage currents using SOI technology, is based on an active control of both the switching on and off process of the two transistors connected in series between the input and output contacts, which are essentially responsible for the switching function, and combines a number of advantages over previously known generic switches: Possible leakage currents in the off state, ie "ofT state, are a few pico-amperes and less,

[0016] Since switching on and off is active, the switching processes are defined reversible and very fast, e.g. within 10 ps and less,

[0017] By preferably designing at least the two transistors responsible for the switching function as NMOS transistors, a very small resistance is formed in the switched-on state, ie in the “on” state,

[0018] To implement the electrical circuit arrangement, only a small number of components with a small space requirement are required, which also have low power consumption and a small loss of internal power.

[0019] The electrical circuit arrangement is applicable over a wide voltage range, which is essentially determined by the selection of the two transistors connected to the circuit unit. Thus, with a suitable selection of HV transistors, switching voltages of 200 V and more can be achieved.

[0020] Starting with two transistors connected in series and connected to one another via their source contacts, preferably each in the form of NMOS transistors, whose drain contacts represent an input contact on the one hand and an output contact on the other, which can be connected as required by both transistors, i.e. "on" state, or separated, i.e. "off" state, the control of both transistors is current-controlled independently of the voltage domain applied to the input and output contacts, or as working potentials HV and LV on the circuit unit. For this purpose, the source and gate contacts of the two transistors are connected to at least one current source such that it can be switched on and off, which is designed to generate a source / gate voltage across the two transistors that is greater than their respectively assigned threshold voltage.This current can generate a voltage swing between the gate and source contacts of both transistors, forming a low-resistance connection between the input and output contacts, e.g., Ron = 100 ohms, and thus switching the switch to the "on" state. For the controlled switch-on process, the current source is connected to a high-voltage supply voltage and, via an ON / OFF switching function unit, to a series-connected voltage-drop-inducing function unit, preferably in the form of a diode or similar, and to a source-drain path of a third transistor, which is connected to a low-voltage supply voltage. The gate contacts of the two transistors are connected to the current source via the ON / OFF switching function unit, and the source contacts of the two transistors are connected exclusively to the gate contact of the third transistor. This current path can be referred to as the switch-on current path.

[0021] This ensures that the source contacts of the two transistors are each connected to a high-impedance current path, so that the currents occurring within the circuit unit have no disruptive influence on the signal current present between the input and output contacts.

[0022] Unless further circuitry precautions are taken, switching off the power source results in the two transistors only discharging passively due to the parasitic capacitances contained in the inrush current path and transitioning uncontrollably into a high-impedance state, corresponding to the "off" state. Leakage currents are completely avoided with this circuit, especially since the two transistors responsible for the switching function are connected to the control only via gate contacts—i.e., the gate contacts of the two transistors themselves, and the gate contact of the third transistor, which is connected to the source contacts of both transistors—and thus do not form a leakage current path.

[0023] To accelerate the turn-off process and ensure it is controlled or actively controlled, a separate circuit unit is provided. This circuit unit can be connected to the source and gate contacts of the two transistors and is designed to equalize the gate and source voltages of the two transistors as soon as the current source is disconnected from the source and gate contacts of the two transistors. To achieve this, the circuit unit must be selected so that, on the one hand, leakage currents are avoided and, on the other hand, the logic levels for controlling the digital circuit components contained in the circuit unit are in a low-voltage range.

[0024] In a first embodiment of the circuit unit, a fourth transistor is provided, the source-drain path of which is connected in parallel to the gate-source contacts of the two transistors, and the gate contact of which is connected to the current source in a switchable and switchable manner. The fourth transistor forms a type of switch-off current path and is connected to the current source via the ON / OFF switching function unit, via which the switch-on current path explained above is connected to the current source. When switched off, the switch-on current path is disconnected from the current source, and the switch-off current path is connected to it. In this way, only one current source is required to activate both current paths, which both operate uniformly with control signals from the low-voltage range, typically 1.8 V.

[0025] As soon as the turn-off current path is connected to the power source, a gate / source voltage necessary to open the fourth transistor is applied to it, whereby the fourth transistor becomes low-ohmic and ensures voltage equalization between the gate and source contacts of the two transistors responsible for the switching function, whereby they assume a high-ohmic state, i.e. the "off" state, in which an ohmic resistance Roff of greater than 1 GQ can form between the input and output contact.

[0026] Various further design options are conceivable for controlling the fourth transistor as well as for the design of the circuit unit representing the switch-off current path, which are explained with reference to the following figures.

[0027] The electrical circuit arrangement according to the solution is based on a novel switching method characterized by the fact that the source and gate contacts of the two transistors are each connected to the circuit unit via a currentless connection, thus enabling a leakage-current-free transition of the two transistors to the off state. This is achieved via high-resistance current paths between the source and gate contacts of the two transistors and the circuit unit, each of which contacts the gate contacts.

[0028] In addition, the circuit unit connected to the source and gate contacts of the two transistors is capable of forming a floating potential difference dV = V1 - V2, which is applied by the circuit unit between the source and gate contacts of the two transistors, with the potential V2 prevailing at the source contacts and the potential V1 prevailing at the gate contacts.

[0029] The floating potential difference that develops between the source and gate contacts of the two transistors preferably forms a low-voltage potential difference, i.e., less than 3V, and this is independent of the high-voltage and low-voltage supply voltage applied to the circuit unit, which, depending on the circuit technology used, can range from ±60 V to ±200 V or more. This opens up the possibility of using low-voltage transistors to implement the circuit unit, which can thus be optimally miniaturized.

[0030] Brief description of the invention

[0031] The invention is described below, without limiting the general inventive concept, using an exemplary embodiment with reference to the drawing. It shows:

[0032] Fig. 1 Circuit topology with actively switchable on and off current path,

[0033] Fig. 2 Circuit topology as above, but with

[0034] Turn-off current path in the form of an NMOS and PMOS source follower circuit, Fig. 3 Circuit topology as Fig. 1 , but with turn-off current path with a source follower,

[0035] Fig. 4 Circuit topology as Fig. 1 , but with switch-off control with latch,

[0036] Fig. 5 Circuit topology as Fig. 1 , but with switch-off control with a current mirror, and

[0037] Fig. 6 General circuit topology to explain the solution-based process principle

[0038] Ways of implementing the invention, industrial applicability

[0039] Figure 1 shows an electrical circuit arrangement with an input contact "in" and an output contact "out," which must be connected in a controlled manner (i.e., "on" state) and interrupted (i.e., "off" state). For example, assume that the output contact is connected to an implanted electrode in direct contact with an intracorporeal organic structure, e.g., a nerve fiber bundle, for its electrical stimulation.

[0040] To implement the switching process between the "on" and "off" states and vice versa, two series-connected transistors T1, T2 are arranged between the input "in" and output "out" contacts, with the source contacts of the two transistors T1, T2 being connected to one another, and the gate contacts of the two transistors T1, T2 being connected to one another. Furthermore, both transistors T1, T2 have a bulk terminal, which is connected to the source contacts of both transistors T1, T2. Both transistors T1, T2 are preferably designed as high-voltage NMOS transistors.In order to switch the transistors T1, T2 into the “on” state, the electrical circuit arrangement provides an inrush current path Ion which has a current source I connected to a high-voltage supply voltage HV, which is connected via an ON / OFF switching function unit SE to a series-connected diode in the form of a transistor diode T_D1 which causes a voltage drop, as well as to the source-drain path of a third transistor T3, which in turn is connected to a low-voltage supply voltage LV. A control signal Vctrl controls the ON / OFF switching function unit between two specific switching states, namely “on” and “off”. Furthermore, the gate contacts of the two transistors T1, T2 are connected via the ON / OFF switching function unit SE to the current source I and the source contacts of the two transistors T1, T2 are connected to the gate contact of the third transistor T3.The gate contact of the transistor diode T_D1 is connected to the ON / OFF switching function unit SE and thus, in the "on" state, directly to the current source I. By exclusively connecting the gates of the two transistors T1 and T2 to all other components of the electrical circuit arrangement, leakage currents can be avoided, especially in the "off" state.

[0041] As soon as the ON / OFF switching function unit SE is connected to the inrush current path Ion, as shown in Figure 1, a current Ion, e.g. of 20 nA, flows through the transistor diode T_D1 and the third transistor T3, which is designed as a PMOS transistor, whereby their assignable gate-source voltages increase above their respective threshold voltages. Due to the voltage drop occurring across the transistor diode T_D1 and the third transistor T3, a floating potential difference dV = V1 - V2 forms between the gate contacts and source contacts of the two transistors T1 and T2, whereby both transistors T1, T2 become conductive, i.e. realize the "on" state of the switch with a low contact resistance Ron, e.g. of approximately 100 Ω.

[0042] In order to switch the transistors T1, T2 into the "off" state in an actively controlled manner, the electrical circuit arrangement provides a switch-off current path loff along which a fourth transistor T4 is provided, the source-drain path of which is connected in parallel to the gate and source contacts of the two transistors T1 and T2. The fourth transistor is controlled in such a way that in the "on" state of the electrical circuit arrangement, as described above, the fourth transistor is not conductive and forms a high resistance. Only in the "off" state of the electrical circuit arrangement does the fourth transistor T4 become conductive and short-circuits the gate and source contacts of the two transistors T1 and T2 with each other, i.e. V1 = V2, as a result of which both transistors T1, T2 together assume a high-ohmic contact resistance Roff between the input and output contact of more than 1 GQ.

[0043] To control the fourth transistor T4, a fifth transistor T5 is also connected in the turn-off current path loff. Its source-drain path is connected to the current source I via the ON / OFF switching function unit SE and to the low-voltage supply voltage LV. Furthermore, the gate contact of the fifth transistor T5 is connected to the source contacts of the two transistors T1, T2, as well as to the source contact of the fourth transistor T4. The gate contact of the fourth transistor T4 is connected to the current source I via the ON / OFF switching function unit SE.

[0044] Due to the voltage difference Vgs_5 which forms at the fifth transistor T5 in the “off” state of the electrical circuit arrangement and which is also present at the gate of the fourth transistor T4, the fourth transistor T4 is opened and thus develops the previously described short-circuit effect on the two transistors T1, T2, ie the voltage potential V1 applied to the gate contacts of both transistors T1, T2 is actively pulled to the voltage potential V2, ie dV = 0 V.

[0045] The diodes D2, D3, D4, and D5, which are additionally arranged in the electrical circuit, primarily serve to protect and ensure the operational reliability of the individual transistors T3, T4, and T5, for example, to ensure that the locally generated potentials do not invert. Diode D5 also supports the switching process from "off" to "on". 1to "on" that the fifth transistor T5 is de-energized by the diode D5 connecting the gate contact to the source contact of the fifth transistor.

[0046] Figure 2 shows an electrical circuit arrangement with an alternative configuration for the breaking current path loff. With the exception of the breaking current path loff, the electrical circuit arrangement illustrated in Figure 2 otherwise corresponds to that in Figure 1, so that, to avoid repetition, a further explanation of the components not related to the breaking current path loff is omitted.

[0047] A circuit unit is arranged along the switch-off current path loff with two transistors T6, T7 which are connected to the current source I via the ON / OFF switching function unit SE and are connected in the form of an NMOS and PMOS source sequence circuit and are designed such that when connected to the current source I, the circuit unit generates a voltage potential V1 applied to the gate contacts of the two transistors T1, T2, which voltage potential corresponds to a voltage potential V2 applied to the source contacts of the two transistors T1, T2.

[0048] The source-drain path of one of the PMOS transistors T6 is connected to the current source I via the ON / OFF switching unit SE, and its gate contact is connected to the source contacts of the two transistors T1 and T2. The source-drain path of the NMOS transistor T7 is connected to the high-voltage supply voltage HV on the one hand and to the gate contacts of the two transistors T1, T2 on the other. Furthermore, the gate contact of the transistor T7 is connected to the current source I via the ON / OFF switching unit SE. The source-drain paths of the two transistors T6, T7 are also connected to the low-voltage supply voltage LV via two further transistors T8, T9 connected as current mirrors. This current mirror T8 / T9 represents a current sink.

[0049] When current is applied to the PMOS transistor T6, it builds up a gate-source voltage Vgs_6. At the same time, the NMOS transistor T7 opens. Its source-drain path is connected between the high-voltage potential HV and a lower voltage potential prevailing at the current mirror T8 / T9, and its gate contact is connected to the current source I (20 nA) via the ON / OFF switching function unit SE. The gate voltage of the NMOS transistor T7 is raised to a value V2+Vgs_6 and defines the voltage V1, since this corresponds to the source voltage of T7. Ideally, the transistors T6 and T7 are matched to one another so that their gate-source voltages Vgs_6 and Vgs_7 are equal, i.e. V1 = V2 +Vgs_6 -Vgs_7 and thus V1 = V2. Figure 3 shows an electrical circuit arrangement with a further alternative design for the switching-off current path, which has two current path branches loff1 and Ioff2.With the exception of the switching-off current path branches loffl and Ioff2, the electrical circuit arrangement illustrated in Figure 3 otherwise corresponds to that in Figure 1, so that in order to avoid repetition, a further explanation of the components not contained in the switching-off current paths loffl and Ioff2 is omitted.

[0050] The circuit unit provides a fourth transistor T4 along the turn-off current path branches Ioff1 and Ioff2, which is connected both to the third transistor T3 and to the gate contacts of the two transistors T1, T2 in such a way that a voltage potential V2 applied to the source contacts of the two transistors T1, T2 and the voltage potential V1 applied to the gate contacts of the two transistors T1, T2 are influenced at least by the fourth transistor T4 in such a way that both voltage potentials V1, V2 correspond.

[0051] For this purpose, the fourth transistor T4 has a doping type opposite to that of the third transistor T3. In Figure 3, the third transistor T3 is embodied as a PMOS transistor and the fourth transistor T4 as an NMOS transistor. The source-drain path associated with the fourth transistor T4 is connected, on the one hand, to the high-voltage supply voltage HV and, on the other hand, switchably connected to the low-voltage supply voltage LV, which represents a current sink Is and thereby forms the turn-off current path branch Ioff2. The gate contact of the fourth transistor T4 is also connected via the ON / OFF switching function unit SE to the current source I and to the source-drain path of the third transistor T3.

[0052] In contrast to the preceding embodiments, in the case of the circuit arrangement shown in Figure 3, current flows through the third transistor T3 both in the "on" state and in the "off" state, which current causes the third transistor T3 to build up a gate-source voltage Vgs_3 in the "off" state. The fourth transistor T4 is dimensioned so as to be coordinated with the third transistor T3, so that the fourth transistor T4 builds up a gate-source voltage Vgs_4 that corresponds to the gate-source voltage Vgs_3 and thus generates a control voltage V1 applied to its gate contact, for which the following applies: V1 = V2 + Vgs_3 - Vgs_4. In this way, in the ideal case, the same voltage, V1 = V2, is applied to the gate contacts of the two transistors T1, T2 as well as to their source contacts, so that dV = 0.

[0053] Figure 4 shows a circuit arrangement in which the source-drain path of the third transistor T3 is always connected to the current source 11 on the one hand and to the low-voltage supply voltage LV on the other, regardless of the switching state of the ON / OFF switching functional unit SE. The functional unit connected in series with the third transistor T3 and causing the voltage drop is designed as two diode arrangements D1, DT connected in parallel.

[0054] The diode arrangements D1, DT each have two transistors T_D1, T10 and T_D1', T10' connected in series, of which T_D1 and T_D1' are each connected as diodes. They primarily serve to provide voltage drop. The transistors T_D1 and T_D1' each have a uniform doping type, in this case NMOS, and are each connected via their source-drain path to the source-drain path of the third transistor T3. The transistors T10, T10' also have a uniform doping type, in this case PMOS, which differs from the doping type of the transistors T_D1 and T_D1'. The source contact of the transistor T10 is permanently connected to the gate contacts of the first and second transistors T1, T2. Both the source contact of the other transistor T10' and the gate contact of the transistor T_D1' are switchably connected to the current source 11 via the ON / OFF switching function unit SE.The gate contact of the transistor T_D1, however, is permanently connected to the gate contacts of the first and second transistors T1, T2.

[0055] The circuit unit that implements the turn-off current path has two fourth transistors T4, T4' connected as latches, the gate contacts of which are each connected to the drain contact of the other fourth transistor T4, T4' via a contact K, K'. The source contacts of the two fourth transistors T4, T4' are each connected to the source contacts of the first and second transistors T1, T2. Furthermore, the gate contact of transistor T_D1 is connected to the drain contact of the fourth transistor T4, and the gate contact of transistor T_D1' is connected to the drain contact of the other fourth transistor T4'.

[0056] In the case of the “on” state of the electrical circuit arrangement, as can be seen from Figure 4, current flows via the diode arrangement D1 and the third transistor T3, which leads to a voltage Vgs_1,2 being formed at the gate-source contacts of the two transistors T1, T2 and switching the transistors on, ie to “on”.

[0057] Since in the "on" state of the electrical circuit arrangement the voltage potential V1 at the gate contacts of the two transistors T1, T2 is greater than V2 and the voltage potential Voff is less than V1, the transistor T10' closes and so prevents a possible current flow from V1 via the further fourth transistor T4' and T_D1' to V2. In addition, the further fourth transistor T4' is in an open state, i.e. low-resistance, due to the control voltage V1 applied to it, whereby the voltage Voff is pulled towards V2, whereby the transistor T10 is wide open, i.e. low-resistance, while the transistors T10', T_D1 and T4 are closed, i.e. high-resistance.

[0058] In the case of the "off" state of the electrical circuit arrangement, current 11 flows via the diode arrangement D1' and the third transistor T3, which leads to the gate-source contacts of the two transistors T1, T2 being short-circuited with V2, ie V1 = V2, whereby the transistors T1, T2 are high-resistance, ie are switched to "off".

[0059] The current I1 flowing through the diode arrangement D1' leads to a voltage Voff that is higher than the threshold voltage Vth of the transistors T10' and T_D1', and also higher than Von, causing the diode arrangement DT and the third transistor T3 to become conductive. The voltage Voff is also present at contact point K', causing the fourth transistor T4 to become conductive and ensuring that V1 = V2, with the fourth transistor T4' being off.

[0060] The advantage of the electrical circuit arrangement illustrated in Figure 4 is, among other things, that the transistors T4, T4', T_D1, T_DT, T10, T10 are designed as low-voltage transistors, which is associated with a smaller area requirement of these

[0061] transistors.

[0062] Figure 5 shows an electrical circuit arrangement with a turn-on current path corresponding to that in the circuit arrangements of Figures 1 to 3. That is, the third transistor T3, connected in series with the diode T_D1, is connected to the gate-source contacts of the two transistors T1 and T2 to open them in the "on" state. In the "on" switching state, the current source 11 supplies current along the turn-on current path; the inverter Inv de-energizes the current sources I2 and I3.

[0063] To implement the turn-off current path, a fourth transistor T4 is provided, the source-drain path of which is connected in parallel to the gate-source contacts of the two transistors T1, T2 and is connected to a further fourth transistor T4' as a current mirror, the gate contacts of the fourth and the further fourth transistor T4, T4' being connected to one another and the source-drain path of the further fourth transistor T4' being connected on the one hand to a further current source I2 and a current sink. In the exemplary embodiment shown, the current sink is formed from the transistors T11 and T1T in the form of a current mirror. In addition, the further fourth transistor T4' is connected as a diode, i.e. its gate contact is connected to its source-drain path and serves to ensure that no current can flow through T4' in the "on" state.

[0064] The transistors T4 and T4', which are connected as current mirrors, form a floating current mirror, since their source and drain voltages follow the potentials of V1 and V2 and are not otherwise fixed.

[0065] To control the two fourth transistors T4, T4', a fifth transistor T5 is provided, whose source-drain path is connected to the gate contacts of the first and second transistors T1, T2, as well as to the gate contacts of the two fourth transistors T4, T4' connected as a current mirror. Furthermore, the gate contact of the fifth transistor T5 is connected to the source contacts of the two transistors T1, T2. In the "off" state, the current source 11 is switched off and the current sources I2, I3 are connected. The transistor T4', which is connected as a diode and whose source contact is connected to V1 together with the source contact of the fourth transistor T4, i.e. is connected to the gate contacts of the two transistors T1, T2, and is further connected to the current sink T11, T1T, opens the transistor T4 via the common gate connection between T4 and T4', whereby a potential equalization between V1 and V2 occurs, i.e. dV= 0.In this case, the fifth transistor T5 becomes high-resistance.

[0066] Figure 6 illustrates a circuit topology used to explain the switching process concept underlying all of the circuit topologies explained above. The source and gate contacts of the two transistors T1, T2 are each connected via currentless connection paths OA to a circuit unit S, which is otherwise connected between a high-voltage supply voltage HV and a low-voltage supply voltage LV. The high-voltage supply voltage HV is connected to the circuit unit S via an ON-OFF switching function unit SE in a switchable manner. Neither in the ON switching state nor in the OFF switching state of the switching function unit SE does any current flow via the connection paths OA between the circuit unit S and the two transistors T1, T2.

[0067] The circuit unit S is able to form a floating potential difference dV = V1 - V2 between the connection path OA connected to the gate contacts of the two transistors T1, T2 and the connection path OA connected to the source contacts of the two transistors T1, T2, whereby the potential V2 predominates at the source contacts of the two transistors T1, T2 and the potential V1 predominates at the gate contacts of the two transistors T1, T2. The floating potential dV adapts to the potential V2 at the source contacts of the two transistors T1, T2. In the ON switching state of the switching function unit SE, V1 is always greater than V2; in the OFF switching state of the switching function unit SE, the following applies: V1 = V2.

[0068] The floating potential difference dV that forms between the source and gate contacts of the two transistors T1, T2 preferably forms as a low-voltage potential difference, i.e., preferably less than 3 V, and this is independent of the high-voltage supply voltage HV and low-voltage supply voltage LV that are applied to the circuit unit S. This opens up the possibility of using low-voltage transistors to implement the circuit unit S, which can thus be miniaturized in an optimized manner, i.e., with a small area requirement.

[0069] List of reference symbols

[0070] T1 to T11 transistors

[0071] T_D1 , T_DT transistor diode

[0072] D1 , DT diode arrangement

[0073] HV high-voltage potential

[0074] LV low-voltage potential

[0075] SE ON-OFF switching function unit

[0076] I, 11 , I2, I3 current source

[0077] V1 , V2 voltage potentials dV voltage difference in input contact out output contact

[0078] Vctrl control signal

[0079] Is current sink

[0080] S circuit unit

Claims

Patent claims 1. An electrical circuit arrangement comprising an input contact (in) which is switchably connected to an output contact (out) via two series-connected transistors (T1, T2), wherein a source contact associated with each of the two transistors (T1, T2) is connected to one another, and a gate contact associated with each of the two transistors (T1, T2) is connected to one another, and the source and gate contacts of the two transistors (T1, T2) are connected to and disconnected from at least one current source (I) which is designed to generate a source / gate voltage at the two transistors (T1, T2) which is greater than their respective associated threshold voltage (Vth), wherein the source and gate contacts of the two transistors (T1, T2) are connectable to a circuit unit which is designed to equalize the gate voltage and the source voltage of the two transistors (T1, T2).as soon as the current source (I) is separated from the source and gate contacts of the two transistors (T1, T2), characterized in that the current source (I) is connected to a high-voltage supply voltage (HV) and can be connected via an ON / OFF switching function unit to a series-connected voltage drop-causing function unit and to a source-drain path of a third transistor (T3) which is connected to a low-voltage supply voltage (LV), and in that the gate contacts of the two transistors (T1, T2) are connected via the ON / OFF switching function unit to the current source (I) and the source contacts of the two transistors (T1, T2) are connected to the gate contact of the third transistor (T3). 2 Electrical circuit arrangement according to claim 1, characterized in that the functional unit has at least one of the following components: resistor, diode, transistor with substrate connection, latch. 3 Electrical circuit arrangement according to claim 1 or 2, characterized in that the circuit unit has a fourth transistor (T4) whose source-drain path is connected in parallel to the gate-source contacts of the two transistors (T1, T2) and whose gate contact is connected to the current source (I) via the ON / OFF switching function unit.

4. Electrical circuit arrangement according to claim 3, characterized in that the circuit unit has a fifth transistor (T5), the source-drain path of which is connected on the one hand via the ON / OFF switching function unit to the current source (I) and on the other hand to the low-voltage supply voltage (LV) and the gate contact of which is connected to the source contacts of the two transistors (T1, T2) and to the source contact of the fourth transistor (T4).

5. Electrical circuit arrangement according to claim 4, characterized in that a diode is connected between the gate contacts of the fourth and fifth transistors (T4, T5).

6. Electrical circuit arrangement according to claim 1 or 2, characterized in that the circuit unit can be connected to the current source (I) via the ON / OFF switching function unit and has two further transistors (T6, T7) which are connected to one another in the form of an NMOS and PMOS source follower circuit and are designed such that, when connected to the current source (I), the circuit unit generates a voltage potential (V2) applied to the source contacts of the two transistors (T1, T2), which corresponds to a voltage potential (V1) applied to the gate contacts of the two transistors (T1, T2).

7. Electrical circuit arrangement according to claim 6, characterized in that the source-drain path of the one transistor (T6) designed as a PMOS of the two further transistors (T6, T7) of the NMOS and PMOS source follower circuit can be connected to the current source (I) via the ON / OFF switching function unit and its gate contact is connected to the source contacts of the two transistors (T1 and T2), and that the source-drain path of a transistor (T7) designed as an NMOS of the two further transistors (T6, T7) of the NMOS and PMOS source follower circuit is connected on the one hand to the high-voltage supply voltage (HV) and on the other hand to the gate contacts of the two transistors (T1, T2) and its gate contact is connectable to the current source (I) via the ON / OFF switching function unit.

8. Electrical circuit arrangement according to claim 6 to 7, characterized in that the source-drain paths of the two further transistors (T6, T7) of the NMOS and PMOS source follower circuit are connected to the low-voltage supply voltage (LV) via two further transistors (T8, T9) connected as current mirrors.

9. Electrical circuit arrangement according to claim 1 or 2, characterized in that the source-drain path of the third transistor (T3) is always connected to the current source (I) regardless of the switching state of the ON / OFF switching function unit, that the circuit unit has a fourth transistor (T4) which is connected both to the third transistor (T3) and to the gate contacts of the two transistors (T1, T2) in such a way that a voltage potential (V2) applied to the source contacts of the two transistors (T1, T2) is passed at least through the third transistor (T3) and a voltage potential (V1) applied to the gate contacts of the two transistors (T1, T2) is passed at least through the fourth transistor (T4) are influenced in such a way that both voltage potentials (V1, V2) correspond.

10. Electrical circuit arrangement according to claim 9, characterized in that the fourth transistor (T4) is doped oppositely to the third transistor (T3), that the source-drain path assigned to the fourth transistor (T4) is connected on the one hand to the high-voltage supply voltage (HV) and on the other hand is switchably connectable to the low-voltage supply voltage (LV), and that the gate contact of the fourth transistor (T4) is connectable to the current source (I) via the ON / OFF switching function unit and is connected to the source-drain path of the third transistor (T3).

11. Electrical circuit arrangement according to one of claims 1 to 10, characterized in that the functional unit causing the voltage drop is designed as a transistor diode (T_D1), the source-drain path of which is connected in series to the source-drain path of the third transistor (T3) and is connected to the gate contacts of the first and second transistors (T1, T2), and in that the transistor diode (T_D1) has a substrate connection connected to the source contacts of the first and second transistors (T1, T2).

12. Electrical circuit arrangement according to claim 1 or 2, characterized in that the source-drain path of the third transistor (T3) is, independently of the switching state of the ON / OFF switching function unit, always connected to the current source (I) on the one hand and to the low-voltage supply voltage (LV) on the other hand, that the circuit unit has two fourth transistors (T4, T4') connected as latches, the gate contacts of which are connected via a contact to the source-drain path of the respective other fourth transistor (T4, T4'), that the source-drain path of the two fourth transistors (T4, T4') are connected to the source contacts of the first and second transistors, and that the functional unit causing the voltage drop provides two diode arrangements (D1, DT) connected in parallel, of which one diode arrangement (D1) is connected to one transistor (T4) of the two fourth transistors (T4, T4') and another of the two diode arrangements (DT) is connected to the other transistor (T4') of the two transistors (T4, T4').

13. Electrical circuit arrangement according to claim 12, characterized in that the diode arrangements (D1, DT) each comprise two series-connected transistors (T10, T_D1;T10', T_D1')) each having a first and second doping, of which the source-drain path of those transistors (T_D1, T_D1') having the first doping is each connected to the source-drain path of the third transistor (T3), that the source contact of the transistor (T10) having the second doping and the gate contact of the transistor (T_D1) having the first doping of one of the two diode arrangements (T_D1, T_D1') are permanently connected to the gate contacts of the first and second transistors (T1, T2), and that the gate contact of the transistor (T_D1') having the first doping and the source contact of the transistor (T10') having the second doping of the other of the two diode arrangements (T_D1, T_D1') are each connected to the current source (11) via the ON / OFF switching function unit SE ) are connectable.; 14. Electrical circuit arrangement according to claim 13, characterized in that the transistors with the first doping are NMOS transistors and the transistors with the second doping are PMOS transistors.

15. Electrical circuit arrangement according to one of claims 13 to 14, characterized in that the gate contact of one of the transistors with the first doping is connected to the source-drain path of one transistor (T4) of the two fourth transistors (T4, T4') and the gate contact of the other of the transistors with the first doping is connected to the source-drain path of the other transistor (T4) of the two fourth transistors (T4, T4').

16. Electrical circuit arrangement according to one of claims 1 to 2, characterized in that the circuit unit has a fourth transistor (T4), the source-drain path of which is connected in parallel to the gate-source contacts of the two transistors (T1, T2) and is connected to a further fourth transistor (T4') as a current mirror, and in that a source-drain path of a fifth transistor (T5) is connected to the gate contacts of the first and second transistors (T1, T2) and to the gate contacts of the two fourth transistors (T4, T4') connected as a current mirror.

17. Electrical circuit arrangement according to claim 16, characterized in that a gate contact associated with the fifth transistor (T5) is connected to the source contacts of the first and second transistors (T1, T2).

18. Electrical circuit arrangement according to claim 16 or 17, characterized in that the further fourth transistor (T4') is connected as a diode and its gate contact is connected to its source-drain path.

19. Method for switching two series-connected transistors (T1, T2) in an electrical circuit arrangement according to one of claims 1 to 18, characterized in that the transistors connected to the source and gate contacts of the two The circuit unit (S) connected to the transistors (T1, T2) is connected to the two transistors (T1, T2) without current.

20. The method according to claim 19, characterized in that the circuit unit (S) connected to the source and gate contacts of the two transistors (T1, T2) forms a floating potential difference (dV = V1 - V2) which is applied by the circuit unit (S) between the source and gate contacts of the two transistors (T1, T2), the potential (V2) being present at the source contacts and the potential (V1) being present at the gate contacts.

21. Method according to claim 20, characterized in that the floating potential difference (dV = V1 - V2) adapts to the potential (V2) applied to the source contacts of the two transistors (T1, T2).

22. Method according to claim 20 or 21, characterized in that the floating potential difference (dV = V1 - V2) is formed as a low-voltage potential difference, independently of the high-voltage supply voltage (HV) and low-voltage supply voltage (LV) applied to the circuit unit (S).

23. Method according to one of claims 20 to 22, characterized in that the high-voltage supply voltage (HV) is connected to the circuit unit (S) in a switchable and switchable manner, and in that when switched on the potential (V1) is greater than the potential (V2) and when switched off the following applies: V1 = V2.

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