Reconfigurable electronic circuit and associated methods

Abstract

The present invention relates to a reconfigurable electronic circuit (10), the electronic circuit (10) comprising a stack (12) of layers, the stack (12) of layers including: - a substrate (14); - a first layer (16), the first layer (16) being made of a first material, the first material being a ferroelectric material; and - a second layer (20), the second layer (20) being made of a second material, the second material being an oxide material that can be reduced by applying an electric field, the first layer (16) being positioned between the substrate (14) and the second layer (20).

Description

[0001] Reconfigurable electronic circuit and associated methods

[0002] The present invention relates to a reconfigurable electronic circuit. The present invention also relates to a configuration method as well as to a manufacturing method of such an electronic circuit.

[0003] The development of electronics has led to the emergence of electronic circuits with increasingly advanced functionalities.

[0004] Typically, these circuits are manufactured using lithography techniques combined with etching and deposition techniques to physically add or remove material from silicon wafers. The term "wafer" is an Anglicism meaning a very thin slice or plate of material. This makes it possible to produce semiconductor boards.

[0005] The physical components used to obtain the functionalities of the devices are interconnected on semiconductor boards thus produced.

[0006] However, to upgrade the components of such circuits, a new circuit is made from scratch.

[0007] This leads to the generation of a lot of so-called electronic waste containing many useful materials, such as copper, gold, silver, lead, tin, which are most of the time not recycled.

[0008] It is known to avoid such waste to reuse the old circuit for a reconditioning of the old circuit but this always leads to the existence of two circuits while the initial need of the use is simply to update the old circuit to have the new functionalities.

[0009] There is therefore a need for a reconfigurable electronic circuit allowing such updates.

[0010] For this purpose, a reconfigurable electronic circuit is described, the electronic circuit comprising a stack of layers, the stack of layers comprising:

[0011] - a substrate,

[0012] - a first layer, the first layer being made of a first material, the first material being a ferroelectric material, and

[0013] - a second layer, the second layer being made of a second material, the second material being an oxide material reducible by application of an electric field, the first layer being interposed between the substrate and the second layer. According to other advantageous aspects of the invention, the electronic circuit comprises one or more of the following characteristics, taken in isolation or in all technically possible combinations:

[0014] - the thickness of at least one layer among the first layer and the second layer is between 1 nanometer and 200 nanometers, advantageously between 10 nanometers and 30 nanometers.

[0015] - the first material is chosen from the list consisting of BaTiOs, PZT, PbTiCh, BiFeOa, Nao.sBio.sTiCh, SBT, Bi4Ti30i2, BiFeOs-PbTiCh, PMN-PT, LiNbOs, LiTaOs, HfCh, ZrC>2, h-LuMnCh, h-LuMnCh, h-YMnCh, NaSrR(BC>3)2 and LuFeCh.

[0016] - the second material is chosen from the list consisting of ferrite, rhombohedral hematite, spinel, mixed valence manganite and multivalent oxide.

[0017] - the substrate is a conductive substrate.

[0018] - the substrate is chosen from the list consisting of Nb-doped SrTiCh, L-doped SrTiCh, Y-doped SrTiOs, Nb-doped LaAIO3, SrRuCh, RuO2, lrO2, LSCO, ITO or a combination of these elements.

[0019] The description also describes a method of configuring an electronic circuit, the configuration method comprising the steps of:

[0020] - provision of a reconfigurable electronic circuit, the electronic circuit comprising a stack of layers, the stack of layers comprising:

[0021] - a substrate,

[0022] - a first layer, the first layer being made of a first material, the first material being a ferroelectric material, and

[0023] - a second layer, the second layer being made of a second material, the second material being an oxide material reducible by application of an electric field, the first layer being interposed between the substrate and the second layer, and

[0024] - writing a configuration on the electronic circuit on the second layer, the tip following a path depending on the configuration to be written, the writing being, for example, carried out by applying a tip, the tip being electrically polarized.

[0025] According to other advantageous aspects of the invention, the configuration method comprises one or more of the following characteristics, taken individually or in all technically possible combinations:

[0026] - the method further comprises the steps of: - erasing the written configuration by heating the electronic circuit, and

[0027] - writing a new configuration on the electronic circuit on the second layer, the tip following a path depending on the new configuration to be written, the writing being, for example, carried out by applying a tip, the tip being electrically polarized.

[0028] - heating is carried out by annealing in an oxidizing environment.

[0029] The description also describes a method of manufacturing a reconfigurable electronic circuit, the manufacturing method comprising the steps of:

[0030] - a step of providing a substrate,

[0031] - a step of depositing a first layer on the substrate, the first layer being made of a first material, the first material being a ferroelectric material, and

[0032] - a step of depositing a second layer on the first layer, the second layer being made of a second material, the second material being an oxide material reducible by application of an electric field, the first layer being intercalated between the substrate and the second layer.

[0033] In this description, the expression "suitable for" means indifferently "adapted for", "adapted to" or "configured for".

[0034] Characteristics and advantages of the invention will appear on reading the description which follows, given solely by way of non-limiting example, and made with reference to the appended drawings, in which:

[0035] - Figure 1 is a schematic representation of a reconfigurable electronic circuit in perspective,

[0036] - figure 2 is a flowchart of an example of implementation of a method for configuring the electronic circuit of figure 1,

[0037] - figures 3 and 4 are schematic representations of the implementation of a step of the configuration method of figure 2,

[0038] - Figure 5 is a graph illustrating the variation of the current as a function of the applied voltage, and

[0039] - Figure 6 is a set of images representing the experimental results obtained by the applicant by implementing the configuration method of Figure 2 and a set of corresponding diagrams making it possible to determine the functionality of the different configured zones.

[0040] Figure 1 schematically illustrates a reconfigurable electronic circuit 10. An electronic circuit is a physical device comprising a set of components interconnected with each other and positioned on a support. The set of components is arranged to perform one or more predefined functions.

[0041] The electronic circuit 10 is reconfigurable here in the sense that it is possible to modify the configuration of the electronic circuit 10.

[0042] A configuration is defined here as an arrangement of components, so that the reconfigurability of the electronic circuit 10 here designates the possibility for a user of the electronic circuit 10 to modify the components of the electronic circuit 10 as well as their position.

[0043] By way of illustration, it is possible to switch the electronic circuit 10 from a first configuration in which the electronic circuit 10 is an RC circuit to a second configuration in which the electronic circuit 10 is an RL circuit.

[0044] It may be emphasized here that the configuration of the electronic circuit 10 may be any combination of any number of components R, L and C.

[0045] Before explaining how it is possible to configure the electronic circuit 10 and to reconfigure it, it is appropriate to describe the elements making up the electronic circuit 10.

[0046] As shown schematically in Figure 1, the electronic circuit 10 comprises a stack 12 of layers.

[0047] According to the example of FIG. 1, the stack 12 comprises a substrate 14, a first layer 16, a second layer 20 and two electrodes 22.

[0048] The first layer 16 is interposed between the substrate 14 and the second layer 20, so that the substrate 14 could be described as the lower layer, the first layer 16 as the intermediate layer and the second layer 20 as the upper layer.

[0049] The substrate 14 is made of a conductive material, so that the substrate 14 is conductive.

[0050] In a particular case, the substrate 14 is made of a doped material, such as SrTiOa doped with Nb, L or Y.

[0051] Other materials are also possible for substrate 14, such as LaAIO3 doped with Nb, SrRuCh, RuO2, I rO2, LSCO or ITO.

[0052] Multi-layers could also be used.

[0053] In particular, the substrate 14 could be a set of layers of the Pt / Ti / SiO2 / Si or RuO2 / TiO2 / Si type.

[0054] The substrate 14 is, furthermore, compatible with the deposition of thin layers.

[0055] In fact, both layers 16 and 20 are thin layers.

[0056] The thickness of each 16 or 20 layer is between 1 nanometer (nm) and 200 nm. Each 16 or 20 layer has a thickness (measured along the stacking direction) less than or equal to 30 nm. Typically, the thickness of each 16 or 20 layer is greater than or equal to 5 nm, preferably greater than or equal to 10 nm.

[0057] The first layer 16 is made of a first material, which here is a ferroelectric material.

[0058] A ferroelectric material is a material exhibiting spontaneous electric polarization that can be reversed in the presence of an external electric field.

[0059] According to the example described, the first material is stable to allow annealing in air at a moderate temperature. Typically, the first material remains stable for annealing carried out at a temperature of 300°C.

[0060] Here, "moderate temperature" means a temperature between the Curie temperature of the first material and 500°C.

[0061] The first material is, in particular, BaTiCh.

[0062] In such a case, the Curie temperature is of the order of 120°C.

[0063] The first material can thus present a perovskite structure, as is the case for BaTiCh, PZT (i.e. PbZr x Tii. x O3 with x strictly between 0 and 1), PbTiOa or BiFeOa.

[0064] In one example, the first material has a tungsten bronze structure. In particular, the first material is Nao.sBio.sTiOa.

[0065] In another example, the first material is an Aurivillius phase, including SBT, Bi4TiaOi2 or BiFeO3-PbTiO3.

[0066] A first material could also be chosen from PMN-PT, LiNbOa, LiTaOa, HfOa, ZrOa, hexagonal HoMnOa (also noted h-HoMnOa), h-LuMnOa, h-YMnOa, NaSrR(BOa)2 and LuFeOa.

[0067] The second layer 20 is made of a second material.

[0068] The second material is an oxide material reducible by application of an electric field.

[0069] The electric field is such that the highest minimum has the value of the coercive field of the first layer and the maximum is lower than the value of the electric field causing the breakdown of the first layer 16 or the second layer 20.

[0070] The electric field is obtained by applying an electric voltage.

[0071] This corresponds to a typical electrical voltage of 4 V to 10 V (for the example material system shown here).

[0072] The material is thus a material capable of exhibiting chemical reduction, accompanied by a drop in resistance, during low amplitude electrical polarization and reoxidation by air annealing at moderate temperature. The second material is, in particular, a ferrite NiFe2O4 or a rhombohedral hematite Fe2O3.

[0073] The second material can also be a spinel, a mixed-valence manganite, or a multivalent oxide.

[0074] Examples of spinel include: NiFe2O4, MnFe2C>4, CoFe2C>4, MgFe2C>4, FesCL, CuC^CL, MgC^CL and FeC^CL.

[0075] The Lai-xSr x MnO3 (with x between 0 and 1) or Pri-xCa x MnO3 (with x between 0 and 1) are examples of mixed-valence manganite.

[0076] As an example of a multivalent oxide, we can cite: TiO x , VO X , CrO x , MnO x , CoO x , NiOx , CuO x , HfO x , ZrO x , WO X , NbO x and TaOx.

[0077] It is in this second layer 20 that the components of the electronic circuit 10 will be made.

[0078] More precisely, as will appear in the remainder of the description, the components will appear on the surface 24 of the second layer 20.

[0079] The second layer 20 is surmounted by two electrodes 22.

[0080] Each electrode 22 is, in this example, a conductive line positioned at the ends of the second layer 20.

[0081] For illustration, each electrode 22 is made of gold.

[0082] The two electrodes 22 are used here to conduct and read the current of the components produced in the second layer 20.

[0083] Depending on the needs, as many contacts as desired or necessary can be inserted to configure the desired circuits, knowing that a circuit can have several contacts (typically an RLC circuit involves four contacts, two for the input and two for the output).

[0084] The reconfigurable nature of the electronic circuit 10 can be illustrated with reference to FIG. 2. FIG. 2 corresponds to an example of implementation of a method for configuring the electronic circuit 10.

[0085] A case will be illustrated here where two configurations are written, it being understood that the erase-write process which will be described can be repeated as many times as necessary.

[0086] The configuration method comprises several steps: a step of writing a first configuration E30, an erasing step E32 and a step of writing a second configuration E34.

[0087] The writing step of the first configuration, simply first writing step E30, is implemented by using an electrically polarized tip. According to the example of Figure 3, the polarized tip is a piezoelectric force microscope tip 40 as shown schematically in Figure 3.

[0088] Such a microscope is more often referred to by the abbreviation PFM, which refers to the corresponding English term for “Piezoresponse force microscope”.

[0089] Tip 40 is a conductive tip, most often made of metal, which can be brought into contact with a sample. The application of a static potential at tip 40 makes it possible to locally excite the deformation of the sample by inverse piezoelectric effect. This makes it possible to manipulate the ferroelectric domains of the first material.

[0090] Alternatively, the polarized tip is an atomic force microscope tip.

[0091] As a note, the tip is conductive and is typically made of Ni, Ag, Al, Pt Pt-lr, carbon nanotubes, doped Si, W, diamond-doped boron, or SiC-doped boron.

[0092] The first writing step E30 thus makes it possible to locally and reversibly modify the properties of the first and second layers 16 and 20.

[0093] The area whose properties are modified is hatched in Figure 3 and designated by the reference sign 42.

[0094] An example of a property is resistance.

[0095] Another example of a property is the magnetization of the second layer 20.

[0096] The resistor value before the first E30 write step corresponds to the initial resistance value.

[0097] This value is sometimes referred to as the pristine resistance value, this denomination designating the state of a layer in the absence of excitation and therefore of writing.

[0098] As explained previously, the application of a local electric field on the tip makes it possible to polarize the first layer 16 and to induce a reduction in the surface resistance of the second layer 20 which thus becomes locally conductive.

[0099] In fact, the local reduction in resistance is obtained by chemical reduction of the surface of the first layer 16. This surface reduction is induced by the condensation of charges at the interface between the first layer 16 and the second layer 20.

[0100] More precisely, as visible in Figure 4, the polarization is manifested by the accumulation of negative charges on the side of the first material forming the interface between the two layers. In parallel, the negative charges accumulate at the other interface between the first material with the substrate 14. The accumulation of negative charges induces positive charges on the other side of the interface, i.e. on the side of the second material. To maintain charge neutrality, the upper part of the second layer 20 accumulates negative charges at the other interface. The doping of the negative charges is manifested by an accumulation of oxygen vacancies. The more oxygen vacancies there are, the less the second material is oxidized (more reduced). A greater number of oxygen vacancies (chemical reduction of the second material) leads to a decrease in resistance.

[0101] It is therefore possible to reduce the resistance locally by passing the tip 40 with a significant factor. Figure 5 experimentally illustrates this modification in the form of a current-voltage curve in the case of writing a wire (curve C1 pristine state and curve C2 written wire).

[0102] This makes it possible to produce different patterns with reduced resistance in the second layer 20 using the tip 40. These different patterns allow the creation of different electronic components.

[0103] The correspondence between the patterns and the function of electronic components is known.

[0104] For example, a straight line with a greater length and / or width corresponds to a resistance of a different value.

[0105] To make an inductance, a wire can be made in a zigzag pattern, while a hair comb shape can be used to create a capacitor (interdigitated electrode).

[0106] It is therefore sufficient to convert the components of the electronic circuit 10 to be produced into the path of the tip 40 to write the desired electronic circuit 10.

[0107] A configuration of the electronic circuit 10 is thus obtained.

[0108] During the erasing step E32, the electronic circuit 10 is heated to restore the oxidation state of the second layer 20.

[0109] For this, for example, an annealing step is carried out by sending a hot gas containing oxygen.

[0110] Gas is, for example, air.

[0111] More generally, annealing takes place in an oxidizing environment, such as an environment containing a plasma with oxygen, or an oxidizing gas such as Oa, NO, NO2, NO3 or H2O2.

[0112] The annealing temperature is chosen to be low enough not to damage the second layer 20 but high enough to achieve erasure.

[0113] The annealing temperature is therefore higher than the Curie temperature of the first material. As a specific example, an annealing temperature of 300°C with a duration of 3 hours allows erasure to be carried out without damaging the second material.

[0114] Under the effect of heating, the first material adopts a paraelectric phase in which the polarization disappears. This causes the charge accumulation at the interface between the first material and the second material to disappear, resulting in the second layer 20 returning to its resistance in the virgin state.

[0115] At the same time, the presence of oxygen allows the surface of the second material to be reoxidized, leaving it in its virgin state.

[0116] The erasure step E32 thus makes it possible both to erase the components written during a previous writing step and to restore the physical properties of the two thin layers to the virgin state.

[0117] Thus, the configuration of the electronic circuit 10 is erased and it is possible to write a new configuration.

[0118] According to the example described, this new configuration is the second configuration written during the second write step E34.

[0119] As in the case of the first writing step E30, the tip 40 of the piezoelectric force microscope is controlled to achieve a path allowing the components of the second desired configuration to be physically produced.

[0120] An example of experimental implementation of such a configuration method is illustrated by figure 6 which shows the electronic circuit 10 obtained at several different stages.

[0121] More precisely, the experiment consisted here of showing the transition from a first configuration corresponding to a wire to a second configuration corresponding to an inductance.

[0122] Figure 6 includes four images of the electronic circuit 10 seen from above which were obtained by a polarized tip on a sample in which the first material is BaTiOs, the second material is NiFe2O4 and the substrate 14 is made of Nb:SrTiO3.

[0123] Each image is matched with a diagram to understand the functionality of each area visible on the image.

[0124] The first image 11 corresponds to the electronic circuit 10 provided before the implementation of the first written step. In this first image 11, we see the two gold electrodes 22 at the top and bottom which are used to supply the current.

[0125] After implementing the first writing step, as seen in the second image I2, a wire was produced with a width of 3 micrometers. As a note, this width is not limiting, the wire can be less wide, widths as small as 10 nanometers can be obtained.

[0126] The third image I3 corresponds to the electronic circuit 10 obtained after erasure (annealed at 300°C for 3 hours). The wire has disappeared.

[0127] Finally, the fourth image I4 shows the top view after writing the second configuration.

[0128] A zigzag line clearly appears, corresponding to the presence of an inductance.

[0129] This experiment clearly shows that it is possible to reconfigure the electronic circuit 10 as desired and at will.

[0130] For this, the electronic circuit 10 simply comprises a set of thin oxide / ferroelectric layers as well as a substrate 14 having two distinct properties.

[0131] On the one hand, the substrate 14 is compatible with the deposition of thin layers.

[0132] On the other hand, the substrate 14 is made of a material allowing the circuit to be written to, for example with a polarized tip as described previously.

[0133] In fact, with a substrate that would be insulating, the applied voltage would go mainly towards the substrate. This would imply a low effective voltage between the first layer 16 and the second layer 20, not allowing the configuration of the electronic circuit 10 to be achieved.

[0134] The substrate 14 is therefore specific in that it allows both the deposition of thin layers and the writing of the electronic circuit 10 to allow its reconfiguration.

[0135] This possibility of reconfiguration makes it possible to greatly reduce the quantity of electronic waste generated since it becomes possible to keep the same electronic circuit 10 and simply change its configuration.

[0136] This change is, moreover, relatively simple insofar as it is sufficient to have a heating system allowing annealing in an oxidizing environment and a piezoelectric force microscope tip 40 whose path is controlled.

[0137] The process for manufacturing the electronic circuit 10 in the virgin state is, moreover, also easy to implement.

[0138] For this, the layers can be deposited with a molecular beam epitaxy system assisted by an oxygen plasma source.

[0139] This ensures good crystallinity and good control of the oxidation of the layers, in particular to obtain good ferroelectric properties for the first layer 16. However, other techniques allowing the deposition of thin layers can be used here such as an ALD technique or a PLD technique.

[0140] The abbreviation ALD refers to the English term "Atomic Layer Deposition" which designates a technique allowing the desired set of layers to be produced atomic layer by atomic layer.

[0141] The abbreviation PLD refers to the English term "Pulsed Laser Deposition" (literally pulsed laser deposition), which designates a technique for creating a layer using a laser.

[0142] Other embodiments benefiting from the aforementioned advantages are also conceivable.

[0143] For example, it is also possible that the electrodes 22 of the electronic circuit 10 are produced in the second layer 20.

[0144] This avoids adding new contact points by depositing conductive material such as gold.

[0145] According to another example, the second layer 20 comprises sub-areas made of different materials.

[0146] For example, it could be envisaged that the second layer 20 comprises a first sub-zone having a high relative resistance and a second sub-zone having a low relative resistance.

[0147] As a particular example, the second layer 20 comprises a first sub-zone in NiFe2C>4, a second sub-zone in CoFe2C>4 and a third sub-zone which is an iron oxide.

[0148] This corresponds to a second material whose composition would vary depending on the sub-zone considered.

[0149] However, whatever the sub-zone considered, the second material would always be a reducible oxide material under the application of an electric field.

[0150] This would make it easier to obtain complex electronic circuits.

Claims

CLAIMS 1. Reconfigurable electronic circuit (10), the electronic circuit (10) comprising a stack (12) of layers, the stack (12) of layers comprising: - a substrate (14), - a first layer (16), the first layer (16) being made of a first material, the first material being a ferroelectric material, and - a second layer (20), the second layer (20) being made of a second material, the second material being an oxide material reducible by application of an electric field, the first layer (16) being interposed between the substrate (14) and the second layer (20).

2. Reconfigurable electronic circuit according to claim 1, in which the thickness of at least one layer among the first layer (16) and the second layer (20) is between 1 nanometer and 200 nanometers, advantageously between 10 nanometers and 30 nanometers.

3. Reconfigurable electronic circuit according to claim 1 or 2, wherein the first material is selected from the list consisting of BaTiCh, PZT, PbTiCh, BiFeOa, Nao.sBio.sTiCh, SBT, Bi4Ti30i2, BiFeOs-PbTiCh, PMN-PT, LiNbCh, LiTaOs, HfCh, ZrC>2, h-LuMnCh, h-LuMnCh, h-YMnCh, NaSrR(BC>3)2 and LuFeOs.

4. Reconfigurable electronic circuit according to any one of claims 1 to 3, wherein the second material is chosen from the list consisting of a ferrite, a rhombohedral hematite, a spinel, a mixed valence manganite and a multivalent oxide.

5. Reconfigurable electronic circuit according to any one of claims 1 to 4, in which the substrate is a conductive substrate.

6. Reconfigurable electronic circuit according to any one of claims 1 to 5, wherein the substrate is selected from the list consisting of Nb-doped SrTiCh, L-doped SrTiOs, Y-doped SrTiCh, Nb-doped LaAIO3, SrRuCh, RuO2, lrO2, LSCO, ITO or a combination of these elements.

7. Method for configuring an electronic circuit (10), the configuration method comprising the steps of: - provision of a reconfigurable electronic circuit (10), the electronic circuit (10) comprising a stack (12) of layers, the stack (12) of layers comprising: - a substrate (14), - a first layer (16), the first layer (16) being made of a first material, the first material being a ferroelectric material, and - a second layer (20), the second layer (20) being made of a second material, the second material being an oxide material reducible by application of an electric field, the first layer (16) being interposed between the substrate (14) and the second layer (20), and - writing a configuration on the electronic circuit (10) on the second layer (20), the tip (40) following a path depending on the configuration to be written, the writing being, for example, carried out by applying a tip (40), the tip (40) being electrically polarized.

8. The configuration method of claim 7, wherein the method further comprises the steps of: - erasing the written configuration by heating the electronic circuit (10), and - writing a new configuration on the electronic circuit (10) on the second layer (20), the tip (40) following a path depending on the new configuration to be written, the writing being, for example, carried out by applying a tip (40), the tip (40) being electrically polarized.

9. A configuration method according to claim 8, wherein the heating is carried out by annealing in an oxidizing environment.

10. Method for manufacturing a reconfigurable electronic circuit (10), the manufacturing method comprising the steps of: - a step of providing a substrate (14), - a step of depositing a first layer (16) on the substrate (14), the first layer (16) being made of a first material, the first material being a ferroelectric material, and - a step of depositing a second layer (20) on the first layer (16), the second layer (20) being made of a second material, the second material being an oxide material reducible by application of an electric field the first layer (16) being intercalated between the substrate (14) and the second layer

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