Data processing device, processing core allocation method therefor, processing core allocation program, and data processing server system

Abstract

The present invention facilitates the reduction of power consumption in a CPU when media data, which is repeatedly inputted by each user at fixed intervals, is inputted into a general-purpose server or the like and processed. In this invention, a type of processing to be performed on data of each user is specified such that each processing is subjected to classification by the processing type, and preferentially allocated to a different logical core or the like. Power saving control of each logical core is performed by reflecting processing characteristics for each processing type. In the case of transcoding, the classification of decoding, data conversion, and encoding, and differences in codecs is reflected in the allocation of logical cores or the like. The allocation of logical cores or the like is determined by reflecting a difference in distance corresponding to a hierarchical structure of a cache memory so as to improve a cache hit rate at a time when each logical core accesses the data. Data processing of the processing type having a large processing load is divided into a plurality of parts and allocated to the plurality of logical cores in a distributed manner. Data processing of the processing type that has a large processing load and cannot be performed only by a single logical core is allocated first.

Description

Data Processing Apparatus, Processing Core Allocation Method Thereof, Processing Core Allocation Program, and Data Processing Server System

[0001] The present invention relates to a data processing apparatus, a processing core allocation method thereof, a processing core allocation program, and a data processing server system, and more particularly to a technology applicable to, for example, a virtualized radio access network (vRAN) or transcoding.

[0002] For example, media data that occupies most of the traffic on the network, such as voice data and video data, generally arrives at a server or the like at regular intervals, for example, every 20 [ms].

[0003] For such media data that arrives regularly, transcoding processing may be required on the server, or predetermined processing may be executed according to a predetermined rule. Also, since media data arrives regularly, the server must complete the above-mentioned processing within a certain time respectively.

[0004] On the other hand, a technique for controlling the idle state of a CPU (Central Processing Unit) in a virtualized radio access network to suppress power consumption is disclosed in Non-Patent Document 1.

[0005] Kei Fujimoto, et.al,"PWU: Pre-Wakeup for CPU Idle to Reduce Latency and Power Consumption", Internet <URL:https: / / ieeexplore.ieee.org / document / <9911402>

[0006] FIG. 1 shows an example of a general core allocation and the execution order of each process assumed when transcoding processing is performed on media data that arrives regularly using a CPU on a general-purpose server. The example shown in FIG. 1 represents a case where transcoding processing is executed on input data 201 to 205 for each sequentially arriving user in a situation where a plurality of independent processing cores 301 to 308 existing on the CPU of a general-purpose server are available.

[0007] ​Generally, to achieve the transcoding function, decoding, data conversion, and encoding processes are required. In addition, since there are multiple types of encoding methods (codecs), decoding and encoding processes corresponding to each codec are required.

[0008] The general-purpose server assigns a process 210 required to execute a transcoding function on the initially input data 201 to the first (#1) processing core 301. As shown in Figure 2, this process 210 includes a decoding process 211, a decoding process 212, a decoding process 213, a data conversion process 214, a coding process 215, an encoding process 216, and an encoding process 217. The decoding processes 211, 212, and 213 each use a different encoding method. Furthermore, the encoding processes 215, 216, and 217 each use a different encoding method.

[0009] The first processing core 301 sequentially executes the decoding process 211, the decoding process 212, the decoding process 213, the data conversion process 214, the encoding process 215, the encoding process 216, and the encoding process 217 shown in FIG. 2 between the start time t01 and the end time t02.

[0010] The general-purpose server assigns a process 220 required to execute a transcoding function on the second input data 202 to the second (#2) processing core 302. The processing core 302 sequentially executes each of the processes included in the required process 220, shown in FIG. 2 : a decoding process 211 for decoding data of encoding method A, a decoding process 212 for decoding data of encoding method B, a decoding process 213 for decoding data of encoding method C, a data conversion process 214, an encoding process 215 for encoding data to encoding method A, an encoding process 216 for encoding data to encoding method B, and an encoding process 217 for encoding data to encoding method C.

[0011] Similarly, the general-purpose server assigns the process 230 required to execute the transcoding function on the input data 203 to the third (#3) processing core 303. The processing core 303 sequentially executes the decoding process 211, the decoding process 212, the decoding process 213, the data conversion process 214, the encoding process 215, the encoding process 216, and the encoding process 217 included in the required process 220 shown in FIG.

[0012] Furthermore, the general-purpose server assigns a process 240 required to execute a transcoding function on the input data 204 to the fourth (#4) processing core 304. The processing core 304 sequentially executes the decoding process 211, the decoding process 212, the decoding process 213, the data conversion process 214, the encoding process 215, the encoding process 216, and the encoding process 217 included in the required process 220 shown in FIG.

[0013] Furthermore, the general-purpose server assigns to the fifth (#5) processing core 305 a process 250 required to execute a transcoding function on the input data 205. The processing core 305 sequentially executes each of the processes included in the required process 220 shown in FIG. 2 , namely, a decoding process 211, a decoding process 212, a decoding process 213, a data conversion process 214, a code process 215, an encoding process 216, and an encoding process 217.

[0014] Therefore, like the processing core 301, each of the processing cores 303 to 308 sequentially executes the decoding process 211, the decoding process 212, the decoding process 213, the data conversion process 214, the code process 215, the encoding process 216, and the encoding process 217 shown in FIG. 2.

[0015] When handling media data, each user's input data 201-205 is repeatedly input at regular intervals. Therefore, the length from start time t01 to end time t02 must be limited to a certain time. When the next input data 201 arrives after end time t02, the processing core 301 can again be used to execute the processes 210 required for that data, including decoding process 211, decoding process 212, decoding process 213, data conversion process 214, encoding process 215, encoding process 216, and encoding process 217.

[0016] When assigning data processing to multiple processing cores 301-308 as shown in Figures 1 and 2, it is necessary to consider the worst-case scenario and ensure that all processing is completed within a certain time. Therefore, in practice, it is necessary to equally assign operating frequency settings related to power-saving control and idle control parameters to all of the multiple processing cores 301-308 being used. As a result, each processing core 301-308 may operate at an operating frequency higher than the frequency required to execute the actual processing, or idle control may not be performed during time periods when processing is not being performed. This makes it impossible to prevent an increase in the power consumption of the general-purpose server. Furthermore, it makes it impossible to prevent a deterioration in the cache hit rate in the cache storage unit that temporarily stores the data to be processed. As a result, the time required for data access for each processing operation increases, resulting in increased processing time.

[0017] The present invention has been made in consideration of the above-mentioned circumstances, and aims to provide a data processing device and its processing core allocation method, processing core allocation program, and data processing server system that are useful for efficiently reducing power consumption in a central processing unit that executes processing and improving processing performance.

[0018] The processing core allocation method of the present invention for a data processing device utilizes multiple processing cores each capable of independent operation, allocates each of user data that is input repeatedly on a regular basis to one of the multiple processing cores, and outputs the results of the user data processed by each processing core, and is characterized in that, when controlling the data processing device, the method includes the steps of: a core allocation determination unit identifying the processing type of each of the input user data; a core allocation determination unit preferentially allocating processing of multiple user data of the same type to the same processing core; an allocation step of distributing processing of multiple user data of different types to multiple different processing cores; and a core setting unit determining the conditions for power saving control for each processing core in accordance with the characteristics of the processing of the user data allocated to each processing core.

[0019] The data processing device, the processing core allocation method, the processing core allocation program, and the data processing server system of the present invention enable efficient reduction of power consumption and improvement of processing performance in a central processing unit that executes processing. That is, it is possible to appropriately allocate the processing of each user data to the multiple processing cores based on the processing type, and it is possible to appropriately determine the power saving control conditions for each processing core.

[0020] 9 is a schematic diagram showing an example of general core allocation in a general-purpose server and the execution order of each process. FIG. 10 is a diagram showing details of each process. FIG. 11 is a block diagram showing main components of a data processing server system according to an embodiment of the present invention. FIG. 12 is a schematic diagram showing Example 1 of core allocation and the execution order of each process according to an embodiment of the present invention. FIG. 13 is a flowchart showing the control processing procedure for realizing the operation shown in FIG. 4. FIG. 14 is a flowchart showing details of a portion of FIG. 15. FIG. 16 is a schematic diagram showing Example 2 of core allocation and the execution order of each process according to an embodiment of the present invention. FIG. 17 is a flowchart showing the control processing procedure for realizing the operation shown in FIG. 16. FIG. 18 is a schematic diagram showing an example of the relationship between core allocation and a hierarchical structure of a cache. FIG. 19 is a flowchart showing an example of the processing procedure for realizing the operation of FIG. 17. FIG. 19 is a time chart showing an example of the relationship between multiple processes assigned to each core and time. FIG. 19 is a flowchart showing the processing procedure when core allocation is performed according to the number of cores required for each processing type. FIG. 19 is a schematic diagram showing an example of the relationship between each process and core allocation. FIG. 19 is a schematic diagram showing an example of the relationship between each process and core allocation. FIG. 19 is a flowchart showing a characteristic processing procedure when there is a constraint on the number of cores capable of processing. FIG. 19 is a time chart showing an example of CPU idle control. FIG. 19 is a time chart showing Example 1 of the timing at which each core executes each assigned process. FIG. 19 is a time chart showing Example 2 of the timing at which each core executes each assigned process.

[0021] An embodiment of the present invention will be described below with reference to the accompanying drawings. <System Configuration Example> Figure 3 shows the main components of a data processing device 100 and a data processing server system according to an embodiment of the present invention. The data processing device 100 shown in Figure 3 is installed, for example, as a general-purpose server in a master station of a virtualized wireless access network or in a central data center, and is connected to slave station wireless base stations or other general-purpose servers via a communication interface (IF) 12 and a predetermined communication network 150. In other words, the data processing device 100 in Figure 3 is used as a data processing server system. Furthermore, the CPU unit 11 of the data processing device 100 can embody various processing units and perform various processes by executing programs (not shown), allowing functions to be flexibly changed without relying on a specific hardware (HW) configuration.

[0022] As a representative example, a transcoding function can be installed in the data processing device 100. For example, the data processing device 100 can periodically input general media data such as audio data or video data, convert the input data in accordance with predetermined instructions or predetermined rules, and output the converted data to provide it to another server.

[0023] 3 is composed of hardware 10, an OS (operating system) unit 20, and an application unit 30. The hardware 10 includes a CPU unit 11, which is a physical electronic circuit similar to that of a typical server device. The CPU unit 11 includes CPU devices 110 and 111, multiple physical cores 110a to 110d that can operate independently of one another, and multiple logical cores 11a to 11g that execute multiple independent processing threads.

[0024] The CPU unit 11 is equipped with CPU devices 110 and 111. The CPU device 110 includes multiple physical cores 110a, 110b, 110c, and 110d that can operate independently of one another. The CPU device 111 includes multiple physical cores (not shown) that can operate independently of one another. The physical core 110a includes multiple logical cores 11a and 11b that can execute multiple independent processing threads. The physical core 110b includes multiple logical cores 11c and 11d that can execute multiple independent processing threads. The physical core 110c includes multiple logical cores 11e and 11f that can execute multiple independent processing threads. The physical core 110d includes multiple logical cores 11g and 11h that can execute multiple independent processing threads. The operating frequency and idle control parameters can also be individually controlled for each of the logical cores 11a to 11h.

[0025] The processing cores in this embodiment are assumed to be logical cores 11a to 11h, but are not limited to this and may be physical cores 110a to 110d, etc.

[0026] The OS unit 20 is realized by the CPU unit 11 executing basic software. The basic software is necessary for the application unit 30 to use the hardware 10. The OS unit 20 includes a core allocation unit 21, a performance counter 22, a CPU idle driver 23, and a CPU frequency driver 24.

[0027] The application unit 30 is realized by the CPU unit 11 executing a processing core allocation program (not shown). The core allocation unit 21 has a function of allocating data processing threads to the logical cores 11a to 11g of the CPU unit 11 in accordance with instructions from a core allocation determination unit 31d of the application unit 30. The performance counter 22 acquires the numerical value of the cache hit rate for each of the logical cores 11a to 11g from the CPU unit 11, and provides this numerical value to a cache hit rate acquisition unit 31c of the application unit 30.

[0028] The CPU idle driver 23 follows instructions from the core setting unit 31g to individually control the idle state of each of the logical cores 11a to 11g in the CPU unit 11. The CPU frequency driver 24 follows instructions from the core setting unit 31g to individually control the operating frequency of the CPU unit 11, i.e., the frequency of the clock pulse, for each of the logical cores.

[0029] The application unit 30 is realized by the CPU unit 11 executing application software (not shown). The application unit 30 includes a management unit 31 and a processing unit 32. The management unit 31 includes a session information acquisition unit 31a, a thread setting / wake-up unit 31b, a cache hit rate acquisition unit 31c, a core allocation determination unit 31d, a required core number calculation unit 31e, a core usage rate acquisition unit 31f, and a core setting unit 31g.

[0030] The session information acquisition unit 31a reads the communication session for each user, extracts information about the time slot in which the user is present and data is being transmitted, and determines the scheduled timing for the thread that processes the communication in that time slot to actually start processing, and instructs the thread setting and waking-up unit 31b to wake up the thread a little before the scheduled timing.

[0031] The session information acquisition unit 31a also extracts information necessary for calculating the required number of cores and determining core allocation from the session information for each user, such as the number of users included in the session, the type of processing performed in the session (decoding, data conversion, encoding, etc.), and session quality information (higher quality means longer processing time).

[0032] The thread setting and wake-up unit 31b, in accordance with instructions from the session information acquisition unit 31a, allocates independent data processing threads for each processing type and encoding method of the required data processing for each user's communication session on the processing unit 32. Then, in accordance with instructions from the session information acquisition unit 31a, the thread setting and wake-up unit 31b controls each thread on the processing unit 32 to be woken up in advance slightly before the timing at which data processing actually starts. The cache hit rate acquisition unit 31c acquires the numerical value of the cache hit rate for each logical core 11a to 11g in the CPU unit 11 from the performance counter 22 on the OS unit 20.

[0033] The core allocation determination unit 31d determines the allocation of cores to execute each data processing thread. In this embodiment, it is assumed that the CPU unit 11 has multiple physical cores, each of which is separated into multiple logical cores 11a to 11g. Therefore, the core allocation determination unit 31d determines which logical core to allocate each data processing thread to. The core allocation determination unit 31d identifies the type of each user data item that is periodically and repeatedly input from the communication network, and prioritizes allocation of processing of multiple user data items of the same processing type to the same processing core, and allocates processing of multiple user data items of different processing types to multiple different processing cores. Details of the characteristic operations of the core allocation determination unit 31d will be described later. Note that, in this embodiment, the relationship between each physical core and each logical core is determined in advance by hardware.

[0034] The required core number calculation unit 31 e calculates the number of logical cores required to complete a type of data processing that is not expected to be completed within a predetermined time using only a single logical core. The core allocation determination unit 31 d determines the allocation of threads for each data processing to each logical core using the required number of cores calculated by the required core number calculation unit 31 e.

[0035] The core usage rate acquisition unit 31f, for example, periodically acquires information on the CPU usage rate for each of the logical cores 11a to 11g from the CPU unit 11. The core allocation determination unit 31d acquires information on the CPU usage rate for each of the logical cores 11a to 11g from the core usage rate acquisition unit 31f and determines the allocation of each logical core and processing thread so that the CPU usage rate is maintained at an appropriate level.

[0036] The core setting unit 31g performs appropriate power saving control for each of the logical cores 11a to 11g in accordance with the allocation of each logical core and processing thread determined by the core allocation determination unit 31d. For example, if a logical core has a margin in its processing capacity relative to the load of the assigned processing thread, the operating frequency is lowered to reduce the power consumption of that logical core. Furthermore, if there is sufficient time between the predicted processing completion time for each thread and the predicted start time of the next processing, during which no processing is performed, the logical core is switched to a predetermined idle state to reduce power consumption during that time. The core setting unit 31g determines the conditions for power saving control for that processing core in accordance with the characteristics of the processing of user data assigned to each processing core by the core allocation determination unit 31d.

[0037] The processing unit 32 individually holds and manages information on each data processing thread (D1, D2, D3, M1, M2, M3, E1, E2, E3) assigned by the thread setting and wake-up unit 31b to each of the logical cores 11a to 11g. Each data processing thread is periodically and repeatedly executed by the assigned logical core for each piece of input user data. If there is sufficient time, each data processing thread transitions to a predetermined idle state after data processing is completed, and is woken up in advance by instructions from the thread setting and wake-up unit 31b before the scheduled time to start processing the next piece of user data.

[0038] <Core Allocation Example 1> -<Data Processing Flow> Example 1 of core allocation and the execution order of each process according to an embodiment of the present invention is shown in Fig. 4. The operation shown in Fig. 4 will be described below.

[0039] Input data 201, 202, 203, ... are sequentially input to data processing device 100 in Figure 3 from communication network 150. Each piece of input data 201 to 205 is input independently for each communication session, i.e., for each user. Most of the input data 201 to 205 is media data that appears sequentially in time series, such as audio data or video data, and is repeatedly input as packets for each user at a fixed interval, for example, every 20 ms.

[0040] 3 is required to execute necessary processes 210, 220, 230, 240, and 250 for each piece of input data 201 to 205 input from communication network 150, and output the results. That is, as necessary processes 210, 220, 230, 240, and 250, data processing such as data conversion according to predefined rules and encoding method conversion according to instructions from a user or the like is executed for each piece of input data 201 to 205.

[0041] In the operation example shown in FIG. 4, the core allocation determination unit 31d classifies the necessary processes 210, 220, 230, 240, and 250 by process type, and allocates each process so that one or more specific logical cores that differ for each process type are preferentially selected as the allocation destination from among the multiple available logical cores 11a to 11g.

[0042] In the example of operation shown in FIG. 4, the core allocation determination unit 31d allocates different types of processes 401 to 407 to different logical cores 11a to 11g, respectively.

[0043] In this case, the logical core 11a sequentially executes processing on data of multiple users requiring the same type of processing within the same thread as process 401. Similarly, the logical core 11b sequentially executes processing on data of multiple users requiring the same type of processing within the same thread as process 402. The logical core 11c sequentially executes processing on data of multiple users requiring the same type of processing within the same thread as process 403. The logical core 11d sequentially executes processing on data of multiple users requiring the same type of processing within the same thread as process 404. The logical core 11e sequentially executes processing on data of multiple users requiring the same type of processing within the same thread as process 405. The logical core 11f sequentially executes processing on data of multiple users requiring the same type of processing within the same thread as process 406. The logical core 11g sequentially executes processing on data of multiple users requiring the same type of processing within the same thread as process 407.

[0044] When the same type of processing is performed, the time required for processing per user is approximately constant. Therefore, for example, in Figure 4, the length of time from when processing 401 starts at time t11 to when it ends at time t15 can be predicted in advance. Furthermore, since the cycle in which data is input for each user is constant, the time t21 from when processing 401 for input data 201 at a certain point in time starts at time t11 to when processing 401 for input data 201 of the next cycle starts can also be predicted in advance.

[0045] 4, the length of time from time t15 when process 401 ends to time t21 when the next cycle starts is sufficiently long, so this interval is treated as an idle interval (idle) and the core allocation determination unit 31d performs power saving control on the logical core 11a. However, since it takes some time for a data processing thread that has transitioned to the idle state to wake up and return to a state where it can actually resume data processing, the thread setting and wake-up unit 31b pre-wakes up the thread at a timing prior to time t21 when process 401 for input data 201 of the next cycle starts.

[0046] As described above, the logical core 11b executes process 402 in the time period from t11 to t15. The core allocation determination unit 31d also executes power saving control for the logical core 11b in the time period from t15 to t21. The logical core 11c executes process 403 in the time period from t11 to t14. The core allocation determination unit 31d also executes power saving control for the logical core 11c in the time period from t14 to t21. The logical core 11d also executes process 404 in the time period from t12 to t16. The core allocation determination unit 31d also executes power saving control for the logical core 11d in the time period from t16 to t21.

[0047] Furthermore, the logical core 11e executes process 405 in the period from time t13 to t17. The logical core 11f executes process 406 in the period from time t13 to t17. The logical core 11g executes process 407 in the period from time t13 to t17. Furthermore, since the period from time t17 to t21 is short, the idle period power saving control is not applied to this period.

[0048] On the other hand, in the example shown in Figure 4, the processing loads of the processes 401, 402, 403, and 404 assigned to each of the logical cores 11a to 11d are relatively small, and the logical cores 11a to 11d have ample processing capacity, allowing the processes to be completed in a relatively short time. Therefore, the core allocation determination unit 31d determines the operating frequency of each of the logical cores 11a to 11d to be a relatively low 2 [GHz]. Note that the idle state is called the C-state, and each idle state is referred to as Cn. Here, the upper limit of the idle state in the CPU idle control of each of the logical cores 11a to 11d is determined to be "C6." This enables more power-saving operation during the idle interval.

[0049] 4, the processing loads of the processes 405, 406, and 407 assigned to the logical cores 11e, 11f, and 11g are relatively large, requiring high processing power to complete each process within a specified time. Therefore, the core allocation determination unit 31d determines the operating frequency of each of the logical cores 11e, 11f, and 11g to be a relatively high 3 GHz. Furthermore, the core allocation determination unit 31d determines the upper limit of the idle state in the CPU idle control of each of the logical cores 11e, 11f, and 11g to be "C1." This minimizes power-saving operations during the idle interval and shortens the delay time from waking up from the idle state to returning to the normal operating state.

[0050] -<Control Processing Procedure> The control processing procedure for realizing the operation shown in Fig. 4 is shown in Fig. 5. Details of step S18 in Fig. 5 are shown in Fig. 6. The contents of the processing procedure shown in Fig. 5 will be described below.

[0051] The management unit 31 of the data processing device 100 sequentially acquires user data for each user's communication session, i.e., input data 201 to 205 in FIG. 4, in step S11. The core allocation determination unit 31d identifies the type of each acquired user data in step S12. The core allocation determination unit 31d also identifies the type of processing required for data processing corresponding to the type of user data in step S13, and then allocates each data processing to an appropriate logical core in steps S14 to S17.

[0052] In step S14, the core allocation determination unit 31d identifies whether there is a logical core (processing core) to which the same processing type as the processing type to be allocated has already been assigned, and if there is, proceeds to step S15; if there is not, proceeds to step S16.

[0053] In step S15, the core allocation determination unit 31d preferentially allocates the process to a specific logical core to which the same process type as the process to be allocated is assigned. For example, when newly allocating the process 401 shown in FIG. 4, if the process 401 of the same type has already been allocated to the logical core 11a, the core allocation determination unit 31d allocates the new process 401 to the logical core 11a of the same process type.

[0054] In step S16, the core allocation determination unit 31d preferentially allocates the process to an empty logical core that has not yet been assigned a process. For example, when newly allocating process 402 shown in FIG. 4, if another process 401 has already been assigned to logical core 11a and logical core 11b is still empty, the new process 402 is allocated to logical core 11b. Therefore, by performing the procedure of steps S13 to S17, it is possible to sequentially allocate processes 401 to 407, each having a different process type, to multiple different logical cores 11a to 11g, as shown in FIG. 3, for example.

[0055] When the allocation of each type of process 401 to 407 to the multiple logical cores 11a to 11g is completed, the process proceeds to steps S17 to S18, and the core setting unit 31g performs processing for power saving control of the CPU as shown in FIG. 6.

[0056] In step S21, the core allocation determination unit 31d or the core setting unit 31g grasps the characteristics of the assigned processing for each logical core and identifies whether high-speed processing is required. For example, when a complex processing that takes time is to be executed or when there are many users of the same type of data and the processing load is heavy, it is recognized that high-speed processing is required.

[0057] If high-speed processing is not required, in step S22 the core setting unit 31g instructs the CPU frequency driver 24 to lower the operating frequency of the logical core to a relatively low frequency, for example, 2 GHz. At the same time, the core setting unit 31g sets the upper limit of the CPU idle state for the logical core to "C6" or the like to enable more effective power saving control.

[0058] If high-speed processing is required, the core setting unit 31g instructs the CPU frequency driver 24 to maintain the operating frequency of the logical core at a normal, relatively high frequency, for example, 3 GHz, in step S23. Also, the upper limit of the CPU idle state for the logical core is set to "C1" or the like so that the logical core can quickly return to the normal operating state from the idle state.

[0059] In step S24, the core allocation determination unit 31d identifies, for each logical core, whether or not an idle period of a certain duration or more exists between the end of the current processing and the start of processing of the next data to be processed. If an idle period of a certain duration or more exists, the core allocation determination unit 31d controls the logical core to enter a sleep state during the idle period in step S25.

[0060] 4, there is a sufficiently long idle period between time t15 when process 401 ends and time t21 when the next process starts, so the CPU idle state of the logical core 11a is switched to "C6" after time t15. As a result, the logical core 11a transitions to a sleep state after time t15, resulting in low power consumption.

[0061] In step S26, the thread setting and wake-up unit 31b determines whether each of the logical cores 11a to 11g is in a sleep state due to idle control. The thread setting and wake-up unit 31b then executes advance wake-up control for each logical core in a sleep state. For example, during the idle period from time t15 to time t21 for the logical core 11a shown in FIG. 4, the logical core 11a is woken up from the sleep state at a timing earlier than time t21, when the next processing starts. This allows the logical core 11a to immediately resume normal operation at time t21.

[0062] In any case, by having the management unit 31 of the data processing device 100 perform the operation shown in Figure 5, it becomes possible to perform appropriate power saving control regarding the CPU operating frequency and idle state, reflecting differences in the type of processing for each logical core, as shown in Figure 4, for example.

[0063] <Core Allocation Example 2> -<Data Processing Flow> Example 2 of core allocation and the execution order of each process according to an embodiment of the present invention is shown in Fig. 7. The operation example shown in Fig. 7 represents an example in which operation is optimized in a situation where the data processing device 100 in Fig. 3 has a transcoding data processing function.

[0064] 3, input data 201, 202, 203, ... are sequentially input to data processing device 100 from communication network 150. Each piece of input data 201 to 205 is input independently for each communication session, i.e., for each user. Most of the input data 201 to 205 is media data that appears sequentially in time series, such as audio data or video data, and is repeatedly input for each user at a fixed interval, for example, every 20 ms.

[0065] The data processing device 100 in FIG. 3 must execute the necessary processes 501, 502, 503, 504, and 505 on each piece of input data 201 to 205 input from the communication network 150, as shown in FIG. 6, and output the results.

[0066] Here, it is assumed that the data processing device 100 has a transcoding data processing function, and therefore at least three types of data processing, namely, decoding, data conversion, and encoding, are included in each of the required processes 501, 502, 503, 504, and 505. Furthermore, it is generally assumed that a situation will arise in which multiple types of encoding methods (codecs) are handled, and therefore it is necessary to separately prepare multiple types of decoding processes and multiple types of encoding processes corresponding to the different encoding methods.

[0067] 7, the core allocation determination unit 31d distinguishes between the decoding, data conversion, and encoding included in each of the required processes 501 to 505, and the codecs involved, and reflects these differences in the allocation of the logical cores 11a to 11g. That is, each process is allocated so that, from among the multiple available logical cores 11a to 11g, one or more specific logical cores that differ for each process type and codec are preferentially selected as the allocation destination.

[0068] In the operation example shown in Figure 7, the core allocation determination unit 31d assigns each of the data processes, decoding process 511, decoding process 512, decoding process 513, data conversion process 514, encoding process 515, encoding process 516, and encoding process 517, to different logical cores 11a to 11g.

[0069] Here, decoding processes 511, 512, and 513 are processes for decoding data using different codec types, respectively. Also, encoding processes 515, 516, and 517 are processes for encoding data into encoded data using different codec types, respectively.

[0070] In this case, the logic core 11a sequentially executes, within the same thread, processing of data of multiple users that requires data processing of the same type of processing and codec, namely, the decoding process 511. Similarly, the logic core 11b sequentially executes, within the same thread, processing of data of multiple users that requires data processing of the same type of processing and codec, namely, the decoding process 512.

[0071] The logic core 11c sequentially executes, within the same thread, processing on data of multiple users that requires the same decoding process 513 of the same processing type and codec type. The logic core 11d sequentially executes, within the same thread, processing on data of multiple users that requires the same data conversion process 514 of the same processing type. The logic core 11e sequentially executes, within the same thread, processing on data of multiple users that requires the same encoding process 515 of the same processing type and codec type. The logic core 11f sequentially executes, within the same thread, processing on data of multiple users that requires the same encoding process 516 of the same processing type and codec type. The logic core 11g sequentially executes, within the same thread, processing on data of multiple users that requires the same encoding process 517 of the same processing type and codec type.

[0072] In the operational example shown in Figure 7, similar to the operational example shown in Figure 4, data processing of the same type is assigned to the same logical core. When each logical core executes the same type of processing, the processing time required for each user is approximately constant. Therefore, for example, in Figure 7, the length of time from when the logical core 11a starts the decryption process 511 at time t11 until the decryption process 511 for all user data is completed can be predicted in advance.

[0073] 7, similar to the example in FIG. 4, the management unit 31 appropriately controls the power consumption of each of the logical cores 11a-11g according to the type and characteristics of the assigned processing. That is, the management unit 31 determines the operating frequency of each of the logical cores 11a-11g according to the type and characteristics of the processing, and appropriately determines the upper limit of the idle state in the CPU idle control. Furthermore, the CPU is transitioned to a sleep state during an idle period after each of the logical cores 11a-11g has completed its processing. Furthermore, the thread of the logical core that has transitioned to the sleep state is pre-woke by the thread setting and wake-up unit 31b before time t21, when the data processing of the next cycle is to begin.

[0074] -<Control Processing Procedure> Fig. 8 shows the control processing procedure for realizing the operation shown in Fig. 7. The details of the processing procedure shown in Fig. 8 will be described below.

[0075] In step S31, the management unit 31 of the data processing device 100 sequentially acquires user data for each user's communication session, i.e., input data 201 to 205 in FIG. 7. In step S32, the core allocation determination unit 31d identifies the type of each acquired user data. In step S33, the core allocation determination unit 31d identifies the processing type and codec type for each of multiple processes required for processing the user data, and then in steps S34 to S38, allocates each data process to an appropriate logical core.

[0076] For example, in the example operation shown in FIG. 7, there are three types of processing: decoding, data conversion, and encoding. Furthermore, processing corresponding to three types of codecs is performed, and these data processing operations are assigned to one of the multiple logical cores 11a to 11g.

[0077] Specifically, when the core allocation determination unit 31d identifies the process type in step S34 and assigns data processing of the process type "decoding" to a logical core, the core allocation determination unit 31d assigns the decoding process to a specific logical core to which the decoding process of the same codec has already been assigned in step S35. Also, if a logical core to which the decoding process of the same codec has already been assigned does not exist, the core allocation determination unit 31d assigns the decoding process to an empty logical core to which no process has yet been assigned in step S35.

[0078] Furthermore, when the core allocation determination unit 31d assigns data processing of the processing type "data conversion" to a logical core, the core allocation determination unit 31d assigns the data conversion processing to a specific logical core to which a data conversion processing of the same conversion method has already been assigned in step S36. Furthermore, if a logical core to which a data conversion processing of the same conversion method has already been assigned does not exist, the core allocation determination unit 31d assigns the data conversion processing to an empty logical core to which no processing has yet been assigned in step S36.

[0079] Furthermore, when the core allocation determination unit 31d assigns data processing of the processing type "encoding" to a logical core, the encoding processing is assigned to a specific logical core to which an encoding processing of the same codec has already been assigned in step S37. Furthermore, if a logical core to which an encoding processing of the same codec has been assigned does not yet exist, the encoding processing is assigned to an empty logical core to which no processing has yet been assigned in step S37.

[0080] By repeating the processing of steps S34 to S38, the core allocation determination unit 31d can assign each of the data processes, namely, decoding process 511, decoding process 512, decoding process 513, data conversion process 514, encoding process 515, encoding process 516, and encoding process 517, to each of the logical cores 11a to 11g, as shown in FIG. 7, for example.

[0081] In step S39, the core setting unit 31g performs appropriate power saving control for each logical core, as shown in FIG. 6. That is, the operating frequency of each logical core 11a-11g is determined according to the type and characteristics of processing, and the upper limit of the idle state in CPU idle control is appropriately determined. Furthermore, the CPU is transitioned to a sleep state during an idle interval after each logical core 11a-11g has completed processing. Furthermore, the thread of the logical core that has transitioned to the sleep state is pre-woke by the thread setting and wake-up unit 31b before time t21, at which data processing for the next cycle begins.

[0082] <Core Allocation Example 3> In computer systems capable of high-speed operation, such as various server devices, cache memory generally exists between the CPU and main memory. It is also common for cache memory to be implemented with multiple tiers of partitioned memory. Because the CPU can access data from cache memory faster than from main memory, accessing data stored in cache memory can be expected to improve processing speed. However, because cache memory has a small storage capacity, it is not possible to store all of the data accessed by the CPU in the same cache memory. If the data accessed by the CPU is not present in the cache memory, the CPU must access the data in the main memory, which takes time to access the data and reduces processing speed. In other words, a decrease in the CPU's cache hit rate reduces the CPU's processing speed.

[0083] Therefore, in this embodiment, when the management unit 31 of the data processing device 100 allocates each data process to each logical core, the allocation is performed as follows (1) and (2) in consideration of improving the CPU cache hit rate: (1) Functions / threads that use the same data are allocated to the same CPU core or a CPU core that is close in the cache hierarchy; (2) Functions / threads that use different data are allocated to different CPU cores or a CPU core that is far in the cache hierarchy.

[0084] Furthermore, when the management unit 31 of the data processing device 100 allocates each data process to each logical core, the allocation is performed as follows (3) and (4) to prevent cache out from occurring, taking into consideration the cache size: (3) Functions and threads with large cache sizes are allocated to independent physical CPU cores as much as possible; (4) Functions and threads with small cache sizes are allowed to be allocated to the same physical CPU core.

[0085] - <Specific example of allocation> An example of the relationship between core allocation and the hierarchical structure of the cache is shown in Figure 9. The example shown in Figure 9 assumes a situation in which there are two sockets on the circuit board of the hardware 10, and two independent CPU devices 110 and 111 are mounted in each socket. The CPU device 110 also has four physical cores 110a, 110b, 110c, and 110d. The logical cores 11a and 11b are on the physical core 110a, and the logical cores 11c and 11d are on the physical core 110b. The logical cores 11e and 11f are on the physical core 110c, and the logical cores 11g and 11h are on the physical core 110d.

[0086] The CPU device 111 has four physical cores 111a, 111b, 111c, and 111d. Logical cores 11i and 11j are on the physical core 111a, logical cores 11k and 11l are on the physical core 111b, logical cores 11m and 11n are on the physical core 111c, and logical cores 11o and 11p are on the physical core 111d.

[0087] Here, four physical cores 110a, 110b, 110c, and 110d on the same CPU device 110 share a last level cache (LLC) of cache memory. Furthermore, multiple logical cores 11a and 11b on the physical core 110a share level 1 / level 2 (L1 / L2C) of the cache memory. Furthermore, multiple logical cores 11c and 11d on the physical core 110b share L1 / L2C of the cache memory. Furthermore, multiple logical cores 11e and 11f on the physical core 110c share L1 / L2C of the cache memory. Furthermore, multiple logical cores 11g and 11h on the physical core 110d share L1 / L2C of the cache memory.

[0088] Here, by arranging two data processes 701 and 702 that reference the same data on the same physical core 110a, the cache hit rate can be increased and processing time can be shortened. Therefore, the two data processes 701 and 702 are assigned to two logical cores 11a and 11b on the same physical core 110a, respectively.

[0089] Similarly to the above, by arranging two data processes 704 and 706 that reference common data on the same physical core 110b, it is possible to increase the cache hit rate and shorten the processing time when executing the data processes 704 and 706. Therefore, the two data processes 704 and 706 are assigned to two logical cores 11c and 11d on the same physical core 110b, respectively.

[0090] Furthermore, the common data referenced by the two data processes 703 and 705 exists in the cache of the same CPU device 110. Therefore, the core allocation determination unit 31d in Fig. 3 allocates the two data processes 703 and 705 to the logical cores 11b and 11c, respectively, on the same CPU device 110. This increases the cache hit rate when the data processes 703 and 705 are executed, and shortens the processing time.

[0091] Furthermore, because the data handled by the data processing 707 is large in size, this data occupies a large area of ​​the cache memory. Therefore, the data processing 707 is assigned to the logical core 11f on an independent physical core 110c separately from other processes. This increases the cache hit rate when the logical core 11f executes the data processing 707, thereby shortening the processing time.

[0092] 3 assigns the two data processes 708 and 709 to the logical core 11g on the single physical core 110d. This allows the logical core 11g to reference data in the L1 / L2 cache on the same physical core 110d without caching out data, eliminating the need to read data from the LLC and enabling a reduction in processing time.

[0093] -<Control Processing Procedure> An example of the processing procedure for realizing the operation of Fig. 9 is shown in Fig. 10. It is assumed that the processing procedure shown in Fig. 10 is executed, for example, in each of steps S15 and S16 shown in Fig. 5. The processing procedure of Fig. 10 will be described below.

[0094] In step S41, the core allocation determination unit 31d identifies whether there are multiple candidates for a logical core to which the data processing to be allocated can be assigned, and if there are multiple candidates, proceeds to step S42. In step S42, the core allocation determination unit 31d determines the status of the data used by each process. Specifically, it determines whether the common data has already been assigned, and if it has already been assigned, it determines the location of the data in the cache in step S42.

[0095] Furthermore, the core allocation determination unit 31d determines in step S43 whether the data referenced by the multiple data processes to be allocated is common. If it is common, the process proceeds to step S44, and if it is not common, the process proceeds to step S45.

[0096] In step S44, when allocating multiple data processes that reference common data to each logical core, the core allocation determination unit 31d preferentially allocates the data processes to logical cores that share a common physical core. For example, when allocating data processes 701 and 702 in Figure 9, since these processes reference the same data, the core allocation determination unit 31d preferentially allocates the data processes 701 and 702 to logical cores 11a and 11b on the same physical core 110a.

[0097] In step S45, the core allocation determination unit 31d preferentially allocates multiple data processes that do not reference common data to multiple logical cores that are relatively far apart in the cache hierarchical structure. For example, when allocating multiple data processes 701 and 704 in FIG. 9, the data processes 701 and 704 are allocated to multiple logical cores 11a and 11c on different physical cores 110a and 110b, respectively. Similarly, when allocating multiple data processes 703 and 705 that reference far-away data on the LLC in the CPU device 110, the data processes 703 and 705 are allocated to multiple logical cores 11b and 11c on different physical cores 110a and 110b, respectively.

[0098] In step S46, the core allocation determination unit 31d compares the size of the data referenced by the data processing to be allocated with the size of the cache, and proceeds to the next step S47 or S48.

[0099] When allocating a data process that references large-sized data, the core allocation determination unit 31d preferentially allocates the data process to another logical core that is independent from other data processes in step S47. For example, since the data process 707 shown in Fig. 9 references large-sized data, the data process 707 is allocated to the independent logical core 11f on the physical core 110c so that the data can exclusively use the cache area on the independent physical core 110c.

[0100] When allocating multiple data processes that reference small-sized data, the core allocation determination unit 31d executes step S48. That is, in step S48, the core allocation determination unit 31d preferentially allocates the multiple data processes to logical cores that share a common physical core. For example, the multiple data processes 708 and 709 shown in FIG. 9 each reference small data sizes. Therefore, the multiple data processes 708 and 709 are each allocated to the logical core 11g on the common physical core 110d.

[0101] <Core Allocation Example 4> -<Relationship Between Multiple Processes and Time> An example of the relationship between multiple processes allocated to each core and time is shown in Fig. 11. The example shown in Fig. 11 assumes a situation in which four processes 601, 602, 603, and 604 of the same type, each with a relatively large processing load, are executed consecutively by a single logical core.

[0102] 11, it is assumed that the processing time T1x per user and per core is constant at 4 ms, the processing deadline Lx per data processing cycle is 10 ms, and the number of users Ux is 4. Therefore, when a single logical core sequentially executes four processes 601, 602, 603, and 604 corresponding to four users as shown in FIG. 10, the total processing time Tx is calculated by the following formula (1): Tx = T1x · Ux = 4 × 4 = 16 (1)

[0103] 11, the total processing time Tx is longer than the processing deadline Lx of 10 ms, so a single logical core cannot execute all four processes 601, 602, 603, and 604. Therefore, in this situation, the core allocation determination unit 31d divides the same type of processes 601, 602, 603, and 604 into multiple processes and assigns each of the divided processes to multiple logical cores. This allows each of the multiple logical cores to complete the assigned process within the processing deadline Lx.

[0104] -<Control Processing Procedure> The processing procedure for allocating cores according to the number of cores required for each processing type is shown in Fig. 12. The processing procedure shown in Fig. 12 is executed, for example, in step S16 in Fig. 5. The processing procedure shown in Fig. 12 will be described below.

[0105] The core allocation determination unit 31d acquires the processing time T1x per user per core for each processing type of data processing to be allocated in step S51. The core allocation determination unit 31d also acquires the number of users Ux for each data processing to be allocated to each logical core in step S52. The core allocation determination unit 31d also acquires the processing deadline Lx for each data processing type in step S53.

[0106] In step S54, the core allocation determination unit 31d calculates the total processing time Tx for each process type based on the above formula (1) and the parameters acquired in steps S51 and S52. In step S55, the core allocation determination unit 31d compares the calculated processing time Tx with the processing deadline Lx, and if the processing time Tx is greater than the processing deadline Lx, the process proceeds to step S57, and if not, the process proceeds to step S56.

[0107] In step S56, the core allocation determination unit 31d allocates data processing of the corresponding processing type to a single logical core. In step S57, the core allocation determination unit 31d calculates the required number of cores Cx using the following formula (2): Cx=CEILING(Tx / Lx) (2) CEILING(): a function that returns the smallest integer equal to or greater than itself

[0108] In step S58, the core allocation determination unit 31d allocates the data processing of the corresponding processing type in a distributed manner across multiple logical cores, the number of which is equal to the required number of cores Cx. This ensures that even when data processing with a long processing time T1x is allocated to each logical core, each logical core can process the data of all users within the processing deadline Lx.

[0109] <Core Allocation Example 5> -<Allocation When the Number of Available Cores is Limited> Examples of the relationship between each process and core allocation are shown in Figures 13 and 14, respectively. There are cases where the number of cores available in the CPU unit 11 on the data processing device 100 is limited. In such a situation, the core allocation determination unit 31d cannot allocate independent logical cores to all process types due to the upper limit on the number of available cores. In such cases, the core allocation determination unit 31d can make appropriate allocations by applying the logic of (1) and (2) shown below.

[0110] (1) The core allocation determination unit 31d in FIG. 3 calculates the required number of cores Cx for each process type that cannot be processed by one core, and prioritizes allocating the corresponding process type to the logical cores in the number corresponding to the required number of cores Cx. For example, the core allocation determination unit 31d assumes that the required number of cores Cx for processes 611 and 612 shown in FIG. 13 is "2." Therefore, the core allocation determination unit 31d prioritizes allocating process 611 to the two logical cores 11a and 11b. Furthermore, the core allocation determination unit 31d prioritizes allocating process 612 to the two logical cores 11c and 11d.

[0111] (2) The core allocation determination unit 31d allocates the processing types that can be processed by one core to the remaining logical cores, excluding the logical cores allocated in (1) above, from the number of available cores. For example, in the example shown in FIG. 13 , the core allocation determination unit 31d allocates each of the processing types 621, 622, 623, 624, and 625 that can be processed by one core to one of the remaining logical cores 11e, 11f, 11g, and 11h. Here, the core allocation determination unit 31d allocates as much CPU time as possible to the processing type with the longest processing time. Specifically, the processing is performed as described below in (2-1) to (2-3). (2-1) For each processing type that can be processed by one core, the core allocation determination unit 31d multiplies the processing time per user and per core by the current number of users to calculate the processing time per core, and then sorts the processing types in descending order of processing time. For example, the processes 621, 622, 623, 624, and 625 shown in FIG. 13 are rearranged in order of processing time, and are arranged as shown in FIG. 14, such as processes 625, 624, 623, 622, and 621. (2-2) The core allocation determination unit 31d sequentially assigns each process type to the remaining logical cores in the order arranged in (2-1) above. In the example shown in FIG. 14, the processes 625, 624, 623, and 622 are assigned sequentially to the logical cores 11e, 11f, 11g, and 11h. (2-3) After the above allocation of processes to the remaining logical cores in (2-2) is completed, the process returns to the beginning of the remaining process types for which allocation has not yet been completed, and sequentially assigns them to the remaining logical cores that can be allocated. This operation is repeated until allocation of all process types is completed. For example, in the example shown in FIG. 14, after the processes 625, 624, 623, and 622 are assigned to the logical cores 11e, 11f, 11g, and 11h, the remaining process 621 is assigned to the remaining assignable logical core 11h.

[0112] -<Control Processing Procedure> A characteristic processing procedure when there is a constraint on the number of cores capable of processing is shown in Fig. 15. The processing procedure in Fig. 15 is described below. In step S61, the core allocation determination unit 31d determines whether or not there is an upper limit on the number of usable cores, and if there is an upper limit, executes the processing from step S62 onwards.

[0113] In step S62, the core allocation determination unit 31d allocates logical cores to each process type of the data processing to be allocated that requires two or more cores Cx and cannot be processed by only one core. As a result, in the example shown in Fig. 13, process 611 is allocated to the two logical cores 11a and 11b, and process 612 is allocated to the two logical cores 11c and 11d.

[0114] In step S63, the core allocation determination unit 31d calculates the processing time T1x per user per core for each data process of the process type that can be processed by one core. In step S64, the core allocation determination unit 31d sorts the data processes of the process type that can be processed by one core in descending order of processing time T1x. As a result, in the example shown in FIG. 14, the processes 625, 624, 623, 622, and 621 are sorted in descending order from top to bottom.

[0115] In step S65, the core allocation determination unit 31d sequentially allocates the data processes of each processing type that have not yet been allocated to the remaining allocatable logical cores in the order arranged in step S64. In the example shown in Fig. 14, the first execution of step S65 allocates processes 625, 624, 623, and 622 to the logical cores 11e, 11f, 11g, and 11h, respectively.

[0116] If, after step S65 is executed, there remains data processing of the processing type for which allocation has not been completed, the core allocation determination unit 31d returns from step S66 to step S65 and repeats the same process. In the example shown in FIG. 14, the second execution of step S65 assigns process 621 to the logical core 11h.

[0117] <Example of CPU Idle Control Operation> An example of CPU idle control operation of the data processing device 100 is shown in FIG. 16. For example, if processes 660-1 and 660-2 (e.g., "decoding" and "data conversion") with a short processing time per user are assigned to one logical core 11a as shown in FIG. 16, the processing load on the logical core 11a is small, and processing can be completed with ease within a time shorter than the arrival period of the media data. Therefore, in this case, the core allocation determination unit 31d reduces the operating frequency of the logical core 11a to 2 [GHz] in step S22 of FIG. 6 to reduce the power consumption of the logical core 11a. At the same time, because there is processing capacity, the core allocation determination unit 31d sets the upper limit of the CPU idle state of the logical core 11a to "C6."

[0118] During the interval in which the logical core 11a executes each of the processes 660-1 and 660-2, the logical core 11a is released from its idle state, and its CPU idle state becomes "C0." Furthermore, immediately after time t12, when one cycle of process 660-1 is completed in the logical core 11a, the core allocation determination unit 31d lowers the CPU idle state of the logical core 11a to the upper limit of "C6" in step S25. In practice, the core allocation determination unit 31d predicts time t21, when the next media data arrives and process 660-1 will begin, and switches the CPU idle state to an appropriate depth depending on the length of time the idle state should last. Furthermore, the thread setting and wake-up unit 31b pre-wakes up the processing thread at an appropriate time t13 so that process 660-2 can begin immediately at time t21. This prevents processing delays associated with wake-up.

[0119] Therefore, at time t21 when the logical core 11a starts executing process 660-2, the CPU idle state of the logical core 11a becomes "C0." Immediately after time t22 when one cycle of process 660-2 ends, the core allocation determination unit 31d reduces the CPU idle state of the logical core 11a to the upper limit "C6" in step S25, and places the logical core 11a back into a sleep state with low power consumption. The length of the idle section in each cycle can be, for example, about 1 ms.

[0120] <Example of Timing for Executing Data Processing> Examples of timing for executing each assigned process by each core are shown in Fig. 17 and Fig. 18. The example shown in Fig. 17 assumes a situation in which the data processing device 100 processes user data in which a certain number or more of encoding method C, which has a long processing time, exists.

[0121] 17, a decoding process 671A that decodes data using encoding method A, a decoding process 671B that decodes data using encoding method B, a decoding process 671C that decodes data using encoding method C, and a data conversion process 672 are assigned to the logical cores 11a to 11d, respectively. Also, an encoding process 673A that encodes data using encoding method A is assigned to the logical core 11e, and an encoding process 673B that encodes data using encoding method B is assigned to the logical core 11f. Also, an encoding process 673C that encodes data using encoding method C is divided into two and assigned to the two logical cores 11g and 11h.

[0122] For example, by having the core allocation determination unit 31d execute the operation shown in FIG. 12, the encoding process 673C having the same encoding method and processing type can be distributed and allocated to the plurality of logical cores 11g and 11h.

[0123] The example shown in Figure 18 assumes a situation in which the data processing device 100 processes user data whose frequency is biased toward encoding method A. In the example shown in Figure 18, the core allocation determination unit 31d divides the decoding process 681A that decodes data using encoding method A into two groups and assigns them to two logical cores 11a and 11b. The core allocation determination unit 31d also combines a decoding process 681B that decodes data using encoding method B and a decoding process 681C that decodes data using encoding method C into one group and assigns them to one logical core 11c. The data conversion process 682 is assigned to the logical core 11d. The encoding process 683A that encodes data using encoding method A is divided into three groups and assigned to three logical cores 11e, 11f, and 11g. The encoding process 683B that encodes data using encoding method B is assigned to the logical core 11g, and the encoding process 683C that encodes data using encoding method C is assigned to the logical core 11h.

[0124] 18, since data of encoding method A frequently appears in the processing of each input user data, multiple logical cores are preferentially allocated to processing related to encoding method A. Specifically, the number of logical cores that process encoding method A, which appears frequently, is increased, and allocation is made so that a single logical core 11c, 11g can be assigned to process multiple types of encoding methods A, B. This makes it possible to process data compatible with various types of encoding methods even when the total number of available logical cores is small.

[0125] <Features of the Present Invention> Characteristic features of the data processing device, its processing core allocation method, processing core allocation program, and data processing server system of the present invention are listed in [1] to [8] below. [1] A processing core allocation method for a data processing device (100) that utilizes a plurality of processing cores (logical cores 11a to 11g) each capable of independent operation, allocates each of user data (input data 201 to 205) that is periodically and repeatedly input to one of the plurality of processing cores, and outputs a result of the user data processed by each processing core, the method comprising: a core allocation determination unit (31d) identifying a processing type of each of the input user data (S12, S13); a core allocation determination unit (31d) preferentially allocating processing of a plurality of user data of the same type to the same processing core (S14, S15); a core allocation determination unit (31d) allocating processing of a plurality of user data of different types to a plurality of different processing cores so as to distribute the processing of the plurality of user data

[0126] According to the processing core allocation method for a data processing device according to the procedure [1] above, since each of the multiple processing cores can be assigned to execute only a specific type of data processing, it is easy to predict the magnitude of the processing load for each processing core. Therefore, it is possible to appropriately control the CPU's power saving for each processing core, thereby reducing power consumption. Furthermore, since each of the multiple processing cores repeatedly executes the same type of processing, it is possible to improve the cache hit rate, and improved processing performance can be expected.

[0127] [2] The processing core allocation method of a data processing device described in [1] above, wherein, in a situation where the data processing device (100) inputs the user data as a processing target, the user data requiring each of the processes of decoding, data conversion, and encoding, the core allocation determination unit (31d) allocates the plurality of types of processing for the single user data in a distributed manner to the plurality of different processing cores, reflecting differences in the processing categories of decoding, data conversion, and encoding for the single user data and differences in codec types; and the core setting unit (31g) determines conditions for power saving control for the processing cores according to differences in the processing categories of the processes allocated to each of the processing cores and differences in codec types (S39).

[0128] According to the processing core allocation method of the data processing device of procedure [2] above, since each of the data processes of decoding, data conversion, and encoding can be executed by a different processing core, it becomes easy to predict the magnitude of the processing load for each processing core, and efficient power saving control for each processing core becomes possible. Also, transcoding compatible with multiple types of codecs becomes possible.

[0129] [3] The processing core allocation method for a data processing device described in [1] above, further comprising the steps (S41 to S45) of: determining an allocation of the processing cores that execute each process of a plurality of user data sets so as to reflect the difference in similarity between the plurality of user data sets processed by the data processing device (100) and the proximity in the hierarchical structure of the cache memory units associated with the respective processing cores that execute the process of the user data sets.

[0130] According to the processing core allocation method of the data processing device according to the procedure [3] above, each processing core can refer to data located nearby in the cache memory unit, thereby improving the cache hit rate and increasing the data processing capacity of the entire device.

[0131] [4] A processing core allocation method for a data processing device described in [1] above, in which the core allocation determination unit (31d) executes a step in which, when allocating processes of the same type among processes on user data to the processing cores, processes with excessive processing loads are divided into multiple parts and allocated in a distributed state to multiple processing cores based on the expected processing load and processing deadline for the processes.

[0132] According to the processing core allocation method of the data processing device according to the procedure [4] above, even when the processing core executes a type of data processing that has a large processing load, the processing can be completed within a predetermined processing time limit.

[0133] [5] A processing core allocation method for a data processing device as described in [4] above, which executes the following steps in a situation where the number of available cores of the plurality of processing cores is limited: the core allocation determination unit (31d) prioritizes allocation of the processing cores to processes of a type with a heavy processing load (S62); and the core allocation determination unit (31d) first allocates each processing core to a higher-level process that requires allocation to at least a plurality of processing cores, and then allocates the remaining lower-level processes that can be processed by a single processing core to the remaining free processing cores available for process allocation.

[0134] According to the processing core allocation method of the data processing device according to the procedure [5] above, even if the number of available cores is limited due to constraints such as the hardware used, it is easy to allocate each process with priority so that each processing core can process the higher-level process within a predetermined processing deadline. Also, it is easy to allocate the lower-level process to the limited number of remaining processing cores.

[0135] [6] A data processing device (100) comprising: a plurality of processing cores (logical cores 11a to 11g) each capable of independent operation; a core allocation determination unit (31d) that identifies the type of each user data that is periodically and repeatedly input, and allocates processing of a plurality of user data of the same processing type preferentially to the same processing core (logical cores 11a to 11g), and allocates processing of a plurality of user data of different processing types so as to be distributed among the plurality of different processing cores (logical cores 11a to 11g); and a core setting unit (31g) that determines conditions for power saving control for each processing core (logical cores 11a to 11g) in accordance with characteristics of the processing of the user data allocated to that processing core by the core allocation determination unit (31d).

[0136] According to the data processing device having the configuration described in [6] above, since each of the multiple processing cores can be assigned to execute only a specific type of data processing, it is easy to predict the magnitude of the processing load for each processing core. Therefore, it is possible to appropriately control the CPU's power saving for each processing core, thereby reducing power consumption. Furthermore, since each of the multiple processing cores repeatedly executes the same type of processing, it is possible to improve the cache hit rate, and improved processing performance can be expected.

[0137] [7] A processing core allocation program executable by a computer that controls the operation of a data processing device that utilizes multiple processing cores each capable of independent operation, assigns each of user data that is repeatedly input on a regular basis to one of the multiple processing cores, and outputs the results of the user data processed by each processing core, wherein the processing core allocation program causes the computer to execute the following steps: a procedure for identifying the type of each of the input user data (steps S12, S13); a procedure for preferentially assigning processing of multiple user data of the same processing type to the same processing core (step S15); a procedure for allocating processing of multiple user data of different processing types so as to be distributed among multiple different processing cores (step S16); and a procedure for determining conditions for power saving control for each processing core depending on the characteristics of the processing of the user data assigned to each processing core (step S18).

[0138] According to the processing core allocation program of [7] above, since each of the multiple processing cores can be assigned to execute only a specific type of data processing, it is easy to predict the magnitude of the processing load for each of the processing cores. Therefore, it is possible to appropriately control the power saving of the CPU for each of the processing cores, thereby reducing power consumption. Furthermore, since each of the multiple processing cores repeatedly executes the same type of processing, it is possible to improve the cache hit rate, and it is expected that processing performance will improve.

[0139] [8] A data processing server system comprising: a plurality of processing cores (logical cores 11a to 11g) each capable of independent operation; a core allocation determination unit (31d) that identifies the type of each piece of user data that is periodically and repeatedly input from a predetermined communication network (150), and allocates processing of a plurality of user data of the same processing type preferentially to the same processing core (logical cores 11a to 11g), and allocates processing of a plurality of user data of different processing types so as to be distributed among the plurality of different processing cores (logical cores 11a to 11g); and a core setting unit (31g) that determines conditions for power saving control for each processing core (logical cores 11a to 11g) in accordance with the characteristics of the processing of the user data allocated to each processing core (logical cores 11a to 11g) by the core allocation determination unit (31d).

[0140] According to the data processing server system of [8] above, since each of the multiple processing cores can be assigned to execute only a specific type of data processing, it is easy to predict the magnitude of the processing load for each processing core. Therefore, it is possible to appropriately control the CPU's power saving for each processing core, thereby reducing power consumption. Furthermore, since each of the multiple processing cores repeatedly executes the same type of processing, it is possible to improve the cache hit rate, and improved processing performance can be expected.

[0141] 10 Hardware 11 CPU unit 11a, 11b, 11c, 11d, 11e, 11f, 11g Logical core 12 Communication interface 20 OS unit 21, 21A Core allocation unit 22 Performance counter 23 CPU idle driver 24 CPU frequency driver 30 Application unit 31 Management unit 31a Session information acquisition unit 31b Thread setting / wake-up unit 31c Cache hit rate acquisition unit 31d Core allocation determination unit 31e Required core number calculation unit 31f Core usage rate acquisition unit 31g Core setting unit 32 Processing unit 110, 111 CPU device 110a, 110b, 110c, 110d Physical core 100 Data processing device (data processing server system) 150 Communication network 201, 202, 203, 204, 205 Input data 210, 220, 230, 240, 250 Necessary processing 211 Decoding processing 212 Decoding processing 213 Decoding processing 214 Data conversion processing 215 Encoding processing 216 Encoding processing 217 Encoding processing 301, 302, 303, 304, 305 Processing core 401, 402, 403, 404, 405, 406, 407 Processing 501, 502, 503, 504, 505 Necessary processing 511 Decoding processing 512 Decoding processing 513 Decoding processing 514 Data conversion processing 515 Encoding processing 516 Encoding processing 517 Encoding processing 601, 602, 603, 604 Processing 611, 612 Processing 621, 622, 623, 624, 625 Processing 631, 632, 633, 634, 635 Processing 650 CPU idle state 660 Processing 671A, 671B, 671C, 681A, 681B, 681C Decoding processing 672, 682 Data conversion processing 673A, 673B, 673C, 683A, 683B, 683C Encoding processing 701, 702, 703, 704, 705, 706, 707 Data processing Cx Required number of cores Lx Processing deadline Tx, T1x Processing time Ux Number of users

Claims

1. A processing core allocation method for a data processing device that utilizes multiple processing cores, each capable of independent operation, allocates each of user data that is input periodically and repeatedly to one of the multiple processing cores, and outputs the results of the user data processed by each processing core, the method comprising the steps of: identifying the processing type of each of the input user data; a core allocation determination unit preferentially allocating processing of multiple user data of the same type to the same processing core; a core allocation determination unit allocating processing of multiple user data of different types so as to be distributed among multiple different processing cores; and a core setting unit determining the conditions for power saving control for each processing core in accordance with the characteristics of the processing of the user data allocated to each processing core.

2. A processing core allocation method for a data processing device as described in claim 1, wherein, in a situation where the data processing device inputs user data as the processing target, which requires decoding, data conversion, and encoding processes, the core allocation determination unit allocates multiple types of processing for a single user data in a distributed manner to multiple different processing cores, reflecting differences in processing categories for decoding, data conversion, and encoding for the single user data, and differences in codec types; and the core setting unit determines conditions for power saving control for each processing core, depending on differences in processing categories for the processing allocated to each processing core and differences in codec types.

3. The processing core allocation method of a data processing device according to claim 1, further comprising the step of: determining the allocation of the processing cores that execute each process of the plurality of user data so as to reflect the difference in similarity between the plurality of user data processed by the data processing device and the proximity in the hierarchical structure of the cache memory units associated with each of the processing cores that executes the process of the user data.

4. A processing core allocation method for a data processing device as described in claim 1, wherein when the core allocation determination unit allocates processes of the same type among processes on user data to the processing cores, the core allocation determination unit divides processes with excessive processing loads into multiple parts and allocates the parts in a distributed manner to multiple processing cores based on the expected processing load and processing deadline for the processes.

5. A processing core allocation method for a data processing device as described in claim 4, wherein, under circumstances where the number of available cores of the plurality of processing cores is limited, the core allocation determination unit executes the steps of: preferentially allocating the processing cores to processes of a type with a heavy processing load; and the core allocation determination unit first allocates each processing core to a higher-level process that requires allocation to multiple processing cores, and then allocates the remaining lower-level processes that can be processed by a single processing core to the remaining free processing cores available for process allocation.

6. A data processing device comprising: a plurality of processing cores each capable of independent operation; a core allocation determination unit that identifies the type of each user data that is input repeatedly at regular intervals, and allocates processing of a plurality of user data of the same processing type preferentially to the same processing core, and allocates processing of a plurality of user data of different processing types so as to be distributed among a plurality of different processing cores; and a core setting unit that determines the conditions for power saving control for each processing core in accordance with the characteristics of the processing of the user data allocated to each processing core by the core allocation determination unit.

7. A processing core allocation program executable by a computer that controls the operation of a data processing device that utilizes multiple processing cores, each capable of independent operation, assigns each of user data that is input periodically and repeatedly to one of the multiple processing cores, and outputs the results of the user data processed by each processing core, wherein the processing core allocation program causes the computer to execute the following steps: a procedure for identifying the type of each of the input user data; a procedure for preferentially assigning the processing of multiple user data of the same processing type to the same processing core; a procedure for distributing the processing of multiple user data of different processing types to multiple different processing cores; and a procedure for determining the conditions for power saving control for each processing core depending on the characteristics of the processing of the user data assigned to each processing core.

8. A data processing server system comprising: a plurality of processing cores each capable of independent operation; a core allocation determination unit that identifies the type of each user data input periodically and repeatedly from a communications network, and allocates processing of a plurality of user data of the same processing type preferentially to the same processing core, and allocates processing of a plurality of user data of different processing types so as to be distributed among a plurality of different processing cores; and a core setting unit that determines the conditions for power saving control for each processing core in accordance with the characteristics of the processing of the user data allocated to each processing core by the core allocation determination unit.

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