Imaging device and camera system

Abstract

An imaging device according to the present invention is provided with: a pixel; a signal line connected to the pixel; and an AD conversion circuit connected to the signal line. The pixel includes: a photoelectric conversion part that converts light into a signal charge; a charge accumulation region where the signal charge is accumulated; a first transistor connected to the charge accumulation region; and a second transistor that outputs a signal corresponding to the potential of the charge accumulation region. The pixel outputs a first signal Sig1 to the signal line, the first signal Sig1 corresponding to the potential of the charge accumulation region when the first transistor is in an ON state, outputs a second signal Sig2 to the signal line, the second signal Sig2 corresponding to the potential of the charge accumulation region when the first transistor is in an OFF state, outputs a third signal Sig3 to the signal line, the third signal Sig3 corresponding to the potential of the charge accumulation region in a state where the signal charge has been accumulated, and outputs a fourth signal Sig4 to the signal line, the fourth signal Sig4 corresponding to the potential of the charge accumulation region when the first transistor is in an ON state.

Description

Imaging device and camera system

[0001] The present disclosure relates to an imaging device and a camera system.

[0002] 2. Description of the Related Art Image capture devices using a charge coupled device (CCD) image sensor and a complementary metal oxide semiconductor (CMOS) image sensor are widely used in digital cameras and the like.

[0003] In the field of imaging devices, there is a demand for noise reduction. In particular, there is a demand for reducing kTC noise, which occurs when a charge accumulation region that accumulates signal charge generated by photoelectric conversion is reset. This kTC noise is also called "reset noise." To reduce reset noise, a known technique is to temporarily store a digital signal containing reset noise in a memory and subtract it from a digital signal representing an image of a subject. The digital signal representing the image of the subject corresponds to the amount of signal charge accumulated in the charge accumulation region. For example, Patent Document 1 discloses an imaging device that temporarily stores a first digital signal corresponding to a reset signal representing a reset level in a frame memory and outputs the difference between a second digital signal corresponding to a pixel signal representing the image of the subject and the first digital signal stored in the frame memory.

[0004] Furthermore, a technique for reducing an offset component of a signal output from a pixel in an imaging device is known. For example, Patent Document 2 discloses an imaging device including a photoelectric conversion element, a first amplification element that amplifies a signal from the photoelectric conversion element, a second amplification element that amplifies an output from the first amplification element, an offset element provided between the first amplification element and the second amplification element, a first reset element that resets the first amplification element, and a second reset element that resets the second amplification element.

[0005] U.S. Patent No. 11,825,223, Japanese Patent No. 6,968,797, International Publication No. 2018 / 025544

[0006] In the technology described in Patent Document 2, the number of circuit elements included in the pixel increases in order to reduce the offset component, and a feedback loop must also be formed in the pixel, which complicates the circuit configuration and increases the size of the imaging device. Therefore, a new technology for reducing the offset component is needed.

[0007] Therefore, the present disclosure provides an imaging device and the like that can reduce the offset component of a signal output from a pixel.

[0008] An imaging device according to an aspect of the present disclosure includes a pixel, a signal line connected to the pixel, and an AD (Analog to Digital) conversion circuit connected to the signal line, wherein the pixel includes a photoelectric conversion unit that converts light into a signal charge, a charge accumulation region that accumulates the signal charge, a first transistor having one of a source and a drain connected to the charge accumulation region, and a second transistor having a gate electrically connected to the charge accumulation region and outputting a signal corresponding to a potential of the charge accumulation region, and the pixel outputs a first signal to the signal line corresponding to a potential of the charge accumulation region when the first transistor is in an on state, and after outputting the first signal, outputs a second signal to the signal line corresponding to a potential of the charge accumulation region when the first transistor is in an off state. and outputs a second signal corresponding to the potential of the charge accumulation region when the signal charge is accumulated to the signal line, and after outputting the second signal, outputs a third signal corresponding to the potential of the charge accumulation region when the first transistor is in an on state to the signal line, and after outputting the third signal, outputs a fourth signal corresponding to the potential of the charge accumulation region when the first transistor is in an on state to the signal line, and the AD conversion circuit generates a fifth signal, which is a digital signal, by performing a counting operation on the difference between the first signal and the second signal, and generates a sixth signal, which is a digital signal, by performing a counting operation on the difference between the third signal and the fourth signal.

[0009] A camera system according to one aspect of the present disclosure includes the imaging device described above.

[0010] According to the present disclosure, it is possible to provide an imaging device or the like that can reduce offset components in signals output from pixels.

[0011] FIG. 1 is a diagram illustrating an exemplary schematic configuration of an imaging device according to a first embodiment. FIG. 2 is a diagram illustrating an example of a substrate configuration in the imaging device according to the first embodiment. FIG. 3 is a diagram illustrating an exemplary circuit configuration of the imaging device according to the first embodiment. FIG. 4 is a diagram illustrating an exemplary circuit configuration of a differential amplifier circuit included in a column signal processing circuit according to the first embodiment. FIG. 5 is a cross-sectional view illustrating a device structure of a pixel according to the first embodiment. FIG. 6 is a flowchart illustrating an example of a method for driving the imaging device according to the first embodiment. FIG. 7 is a timing chart illustrating an example of a method for driving the imaging device according to the first embodiment. FIG. 8 is a diagram illustrating an example of details of driving the imaging device according to the first embodiment during a reset signal readout period and a pixel signal readout period. FIG. 9A is a diagram illustrating a case where the distribution of the output after AD conversion of a signal from a pixel is wide. FIG. 9B is a diagram illustrating a case where the distribution of the output after AD conversion of a signal from a pixel is narrow. FIG. 10 is a diagram illustrating an exemplary circuit configuration of an imaging device according to a first modification of the first embodiment. FIG. 11 is a diagram illustrating an example of an arrangement of a plurality of switches. FIG. 12 is a diagram illustrating another example of an arrangement of a plurality of switches. Fig. 13 is a diagram for explaining an example of details of driving of an imaging device according to Modification 1 of Embodiment 1 in a reset signal readout period and a pixel signal readout period. Fig. 14 is a diagram showing an example of a configuration of a pixel array according to Modification 2 of Embodiment 1. Fig. 15 is a diagram showing an example of an arrangement of an effective pixel region and a reference pixel region according to Modification 2 of Embodiment 1. Fig. 16 is a diagram showing another example of an arrangement of an effective pixel region and a reference pixel region according to Modification 2 of Embodiment 1. Fig. 17 is a block diagram showing an example of a configuration of a camera system according to Embodiment 2.

[0012] (Summary of the Present Disclosure) As an overview of the present disclosure, examples of an imaging device and a camera system according to the present disclosure are described below.

[0013] For example, an imaging device according to a first aspect of the present disclosure includes a pixel, a signal line connected to the pixel, and an AD (Analog to Digital) conversion circuit connected to the signal line, wherein the pixel includes a photoelectric conversion unit that converts light into a signal charge, a charge accumulation region that accumulates the signal charge, a first transistor having one of a source and a drain connected to the charge accumulation region, and a second transistor having a gate electrically connected to the charge accumulation region and outputting a signal corresponding to a potential of the charge accumulation region, and the pixel outputs a first signal to the signal line, the first signal corresponding to a potential of the charge accumulation region when the first transistor is in an on state, and after outputting the first signal, outputs a second signal to the signal line, the second transistor outputting a second signal corresponding to a potential of the charge accumulation region when the first transistor is in an off state. and outputs a second signal corresponding to the potential of the charge accumulation region when the signal charge is accumulated to the signal line, and after outputting the second signal, outputs a third signal corresponding to the potential of the charge accumulation region when the first transistor is in an on state to the signal line, and after outputting the third signal, outputs a fourth signal corresponding to the potential of the charge accumulation region when the first transistor is in an on state to the signal line, and the AD conversion circuit generates a fifth signal, which is a digital signal, by performing a counting operation on the difference between the first signal and the second signal, and generates a sixth signal, which is a digital signal, by performing a counting operation on the difference between the third signal and the fourth signal.

[0014] Each of the first signal, the second signal, the third signal, and the fourth signal includes an offset component resulting from variations in the threshold voltage of the second transistor, which outputs a signal corresponding to the potential of the charge accumulation region. Therefore, the offset component is removed by calculating the difference between the first signal and the fourth signal and the second signal corresponding to the reset level of the pixel and the third signal corresponding to a signal level according to the amount of signal charge accumulated in the charge accumulation region. Therefore, the imaging device according to this aspect can reduce the offset component of the signal output from the pixel. Furthermore, because the counting operation is performed on the difference from which the offset component has been removed, the offset component does not unnecessarily occupy the signal range of the AD conversion, making it possible, for example, to ensure the signal range of the AD conversion, shorten the AD conversion time, and reduce the number of gradations of the AD conversion.

[0015] Also, for example, an imaging device according to a second aspect of the present disclosure is the imaging device according to the first aspect, further comprising a signal processing circuit, wherein the signal processing circuit generates a seventh signal corresponding to the difference between the fifth signal and the sixth signal.

[0016] The fifth signal and the sixth signal each contain a kTC noise component that accompanies turning off the second transistor. When the kTC noise components contained in the fifth signal and the sixth signal each have the same sign, the signal processing circuit calculates the difference between the fifth signal and the sixth signal, thereby obtaining, as the seventh signal, a signal that corresponds to the amount of signal charge accumulated in the charge accumulation region and from which the kTC noise has been removed.

[0017] Also, for example, an imaging device according to a third aspect of the present disclosure is the imaging device according to the first aspect, further comprising a signal processing circuit, wherein the signal processing circuit generates a seventh signal corresponding to the sum of the fifth signal and the sixth signal.

[0018] The fifth signal and the sixth signal each contain a kTC noise component that accompanies turning off the second transistor. When the kTC noise components contained in the fifth signal and the sixth signal each have opposite signs, the signal processing circuit sums the fifth signal and the sixth signal to obtain, as the seventh signal, a signal that corresponds to the amount of signal charge accumulated in the charge accumulation region and from which the kTC noise has been removed.

[0019] Also, for example, an imaging device according to a fourth aspect of the present disclosure is the imaging device according to any one of the first to third aspects, further including a memory that holds the fifth signal.

[0020] This makes it possible to perform signal processing using the fifth signal and the sixth signal even if the fifth signal and the sixth signal are generated at different times.

[0021] Also, for example, an imaging device according to a fifth aspect of the present disclosure is the imaging device according to the fourth aspect, wherein the bit width of the fifth signal held in the memory is 7 bits or less.

[0022] This reduces the memory capacity and memory area.

[0023] Furthermore, for example, an imaging device according to a sixth aspect of the present disclosure is an imaging device according to any one of the first to fifth aspects, wherein the AD conversion circuit performs a counting operation during each of a period in which the pixel outputs the first signal and a period in which the pixel outputs the second signal to generate the fifth signal, and performs a counting operation during each of a period in which the pixel outputs the third signal and a period in which the pixel outputs the fourth signal to generate the sixth signal.

[0024] As a result, when generating each of the fifth and sixth signals, one of the two counting operations can be used as a counting operation relative to the reference voltage to remove the offset level in the AD conversion, thereby reducing variation in the AD conversion.

[0025] Also, for example, an imaging device according to a seventh aspect of the present disclosure is the imaging device according to any one of the first to sixth aspects, wherein the number of transistors included in the pixel is four or less.

[0026] This allows the pixels to be miniaturized.

[0027] Also, for example, an imaging device according to an eighth aspect of the present disclosure is an imaging device according to any one of the first to seventh aspects, wherein the period during which the first transistor is in an on state when the fourth signal is output to the signal line is longer than the period during which the first transistor is in an on state when the first signal is output to the signal line.

[0028] This makes it possible to ensure time for AD conversion when the fourth signal is output to the signal line, even if the period during which the first transistor is in the on state when the first signal is output to the signal line is shortened.

[0029] Also, for example, an imaging device according to a ninth aspect of the present disclosure is an imaging device according to any one of the first to eighth aspects, further comprising a voltage line to which a voltage is applied from a voltage supply circuit, and a switch that switches between connection and disconnection between the voltage supply circuit and the voltage line, and the other of the source and drain of the first transistor is connected to the voltage line.

[0030] This makes it possible to prevent fluctuations in the output voltage of the voltage supply circuit from affecting the potential of the charge storage region via the first transistor by disconnecting the voltage supply circuit from the voltage line at the required timing.

[0031] Also, for example, an imaging device according to a tenth aspect of the present disclosure is the imaging device according to the ninth aspect, wherein the switch disconnects the voltage supply circuit from the voltage line during a period in which the first transistor is in an on state, and connects the voltage supply circuit from the voltage line during a period in which the first transistor is in an off state.

[0032] This makes it possible to prevent fluctuations in the output voltage of the voltage supply circuit from affecting the potential of the charge storage region via the first transistor when the pixel is outputting the first signal and the fourth signal.

[0033] Also, for example, an imaging device according to an eleventh aspect of the present disclosure is an imaging device according to any one of the first to tenth aspects, further comprising one or more reference pixels whose output signals do not change in response to the incidence of light, and a memory, wherein the AD conversion circuit generates one or more reference signals corresponding to the fifth signal based on signals output by the one or more reference pixels as signals corresponding to the first signal and the second signal, and the memory holds an eighth signal having a digital value corresponding to the difference between the digital value of the fifth signal and a digital value determined from the one or more reference signals.

[0034] This allows the offset component contained in the fifth signal to be cancelled by the reference signal, and makes it possible to suppress an increase in the capacity of the memory for storing the digital signal.

[0035] Also, for example, an imaging device according to a twelfth aspect of the present disclosure is an imaging device according to the eleventh aspect, which is provided with a plurality of reference pixels as the one or more reference pixels, and the AD conversion circuit generates one reference signal as the one or more reference signals based on signals output by two or more reference pixels among the plurality of reference pixels.

[0036] This makes it possible to generate a reference signal by leveling out variations and noise in the offset components of the signal output by the reference pixel.

[0037] Also, for example, an imaging device according to a thirteenth aspect of the present disclosure is an imaging device according to the eleventh aspect, which comprises a plurality of reference pixels as the one or more reference pixels, and the AD conversion circuit generates two or more reference signals corresponding to the two or more reference pixels as the one or more reference signals based on signals output by two or more reference pixels among the plurality of reference pixels.

[0038] This makes it possible to use two or more reference signals to average out variations and noise in the offset components of the signal output by the reference pixel, and then use the offset component contained in the fifth signal for cancellation.

[0039] Also, for example, a camera system according to a fourteenth aspect of the present disclosure includes the imaging device according to any one of the first to thirteenth aspects.

[0040] As a result, the camera system according to this aspect includes the imaging device described above, and therefore can reduce the offset component of the signal output from the pixel.

[0041] Hereinafter, embodiments of the present disclosure will be described in detail with reference to the drawings. Note that the embodiments described below are all comprehensive or specific examples. The numerical values, shapes, materials, components, component arrangements and connection forms, steps, and step orders shown in the following embodiments are merely examples and are not intended to limit the present disclosure. The various aspects described in this specification can be combined with each other as long as no contradiction occurs. Furthermore, among the components in the following embodiments, components not recited in independent claims will be described as optional components. In the following description, components having substantially the same functions will be designated by common reference symbols, and their description may be omitted. Furthermore, to avoid overly complicated drawings, illustration of some elements may be omitted.

[0042] Furthermore, each drawing is a schematic diagram and is not necessarily an exact representation, and therefore, for example, the scales of the drawings do not necessarily match.

[0043] Furthermore, in this specification, the terms "upper" and "lower" do not refer to the upper direction (vertically upper) and lower direction (vertically lower) in absolute spatial recognition, but are used as terms defined by a relative positional relationship based on the stacking order in the stacked structure. Specifically, the light-receiving side of the imaging device is referred to as "upper," and the side opposite the light-receiving side is referred to as "lower." Note that terms such as "upper" and "lower" are used solely to specify the relative arrangement of components and are not intended to limit the orientation of the imaging device during use. Furthermore, the terms "upper" and "lower" are used not only when two components are arranged with a gap between them and another component is present between them, but also when two components are arranged closely together and the two components are in contact with each other.

[0044] In addition, in this specification, "connected" and "disconnected" mean electrical connection and electrical disconnection unless otherwise specified.

[0045] First Embodiment An imaging device according to a first embodiment will be described below.

[0046] [Overall Configuration] First, the overall configuration of the imaging device according to this embodiment will be described.

[0047] FIG. 1 is a diagram illustrating an exemplary schematic configuration of an image pickup device 100 according to the present embodiment. As shown in FIG. 1, the image pickup device 100 includes a pixel array PA configured with a plurality of pixels Px, each of which includes a photoelectric conversion unit supported on a semiconductor substrate. A configuration in which the photoelectric conversion unit is disposed above the semiconductor substrate is sometimes called a "stacked type." In other words, hereinafter, an image pickup device having a so-called stacked type configuration will be exemplified as the image pickup device 100.

[0048] A plurality of pixels Px are two-dimensionally arranged on a semiconductor substrate to form an imaging area. In this embodiment, the plurality of pixels Px are arranged in a plurality of rows and columns. In FIG. 1, the plurality of pixels Px are arranged in m rows and n columns. Here, m and n independently represent integers of 2 or greater.

[0049] The imaging device 100 includes a plurality of row signal lines R ｉand a plurality of output signal lines S ｊ The imaging device 100 also includes peripheral circuits for driving the plurality of pixels Px and processing signals output from the plurality of pixels Px, such as a row scanning circuit 130, an AD (Analog to Digital) conversion circuit 140, a reference signal generation circuit 141, a digital memory 150, a signal processing circuit 160 having a frame memory 161, a digital output interface (I / F) 170, and a control circuit 220. Although each circuit of the peripheral circuits is schematically shown as one functional block in FIG. 1 , these circuits may be arranged together in one location or may be arranged separately in several circuit blocks.

[0050] A plurality of row signal lines R ｉ are m row signal lines R arranged corresponding to a plurality of rows of pixels Px. ０ , R １ , R ２ , ..., R ｍ－２ , R ｍ－１ The signal i corresponds to the row of the pixel Px and is an integer between 0 and m-1. ｉ Each of these row signal lines R is electrically connected to one or more pixels Px belonging to the same row. ｉ are connected to the row scanning circuit 130. It is possible that two or more signal lines are provided for each row of a plurality of pixels Px.

[0051] A plurality of output signal lines S ｊ are n output signal lines S arranged corresponding to a plurality of columns of pixels Px. ０ , S １ , S ２ , ..., S ｎ－２ , S ｎ－１ j corresponds to the column of the pixel Px and is an integer between 0 and n-1. ｊ Each of the output signal lines S is electrically connected to a readout circuit of one or more pixels Px belonging to the same column. ｊ The AD conversion circuit 140 is connected to the output signal line S ｊ is an example of a signal line. Two or more output signal lines Sｊ may also be established.

[0052] The AD conversion circuit 140 outputs a signal from the pixel Px to the output signal line S ｊ The AD conversion circuit 140 converts the analog signal output from the pixel Px to the output signal line S. ｊ The AD conversion circuit 140 forms a single-slope AD conversion circuit together with a reference signal generation circuit 141, for example.

[0053] The reference signal generating circuit 141 generates a reference signal such as a ramp signal and supplies the generated reference signal to the AD conversion circuit 140 .

[0054] The digital memory 150 temporarily stores, for example, one row's worth of digital signals generated by the AD conversion circuit 140. By interposing the digital memory 150 between the AD conversion circuit 140 and a circuit downstream of the AD conversion circuit 140, it becomes possible, for example, to store one row's worth of digital signals of pixels Px in the digital memory 150 while the AD conversion circuit 140 performs AD conversion on signals read from the pixels Px of the next row. In other words, AD conversion on a row-by-row basis can be processed at higher speeds. Note that the imaging device 100 does not necessarily have to include the digital memory 150.

[0055] The signal processing circuit 160 processes the digital signal generated by the AD conversion circuit 140. The signal processing circuit 160 has a frame memory 161 that temporarily stores the digital signal generated by the AD conversion circuit 140. The frame memory 161 can temporarily store, for example, digital data corresponding to one frame of an image, in other words, digital signals corresponding to the number of pixels Px. The frame memory 161 is an example of a memory.

[0056] As will be described in detail later, the signal processing circuit 160 outputs a seventh signal corresponding to the difference between the reset signal and the pixel signal based on a fifth signal temporarily stored in the frame memory 161, the fifth signal being a digital signal based on the reset signal, and a sixth signal being a digital signal based on the pixel signal output from the AD conversion circuit 140. The reset signal is a signal representing a reset level, and the pixel signal is a signal representing an image of a subject. The difference between the reset signal and the pixel signal can substantially cancel the influence of reset noise caused by a reset operation performed immediately before an exposure period. In the example shown in FIG. 1 , the signal output by the signal processing circuit 160 is output to the outside via the digital output interface 170. This eliminates the need for the digital output interface 170 to output digital signals corresponding to the reset signal and the pixel signal to the outside, thereby reducing the amount of data output to the outside and lowering the output rate.

[0057] The signal processing circuit 160 may be realized, for example, by a microcontroller including one or more processors. The functions of the signal processing circuit 160 may be realized by a combination of a general-purpose processing circuit and software, or by hardware specialized for such processing. The signal processing circuit 160 may share a processor with other circuits. The frame memory 161 may be, for example, a static random access memory (SRAM). The frame memory 161 may also be a dynamic random access memory (DRAM), a magnetoresistive random access memory (MRAM), or a flash memory.

[0058] The control circuit 220 receives command data, clocks, and the like provided, for example, from outside the imaging device 100, and controls the entire imaging device 100. In the example shown in FIG. 1 , the control circuit 220 is connected to the row scanning circuit 130, the AD conversion circuit 140, the reference signal generation circuit 141, the signal processing circuit 160, and the digital output interface 170. The control circuit 220 receives control signals, for example, a vertical synchronization signal and a horizontal synchronization signal, from outside. The control circuit 220 has, for example, a timing generator and supplies drive signals to the row scanning circuit 130, the AD conversion circuit 140, and the like. In FIG. 1 , arrows extending from the control circuit 220 schematically represent output signals from the control circuit 220. Note that the signal flow shown in FIG. 1 is an example and is not limited to the example shown in FIG. 1 .

[0059] The control circuit 220 may be realized, for example, by a microcontroller including one or more processors. The functions of the control circuit 220 may be realized by a combination of a general-purpose processing circuit and software, or by hardware specialized for such processing. The control circuit 220 may share a processor with other circuits.

[0060] The pixel array PA and the peripheral circuits are formed on a substrate including a semiconductor substrate. The pixel array PA and the peripheral circuits may be formed on a single substrate, or may be formed separately on multiple substrates. Figure 2 is a diagram for explaining an example of the substrate configuration of the image pickup device 100 according to this embodiment.

[0061] In the example shown in Fig. 2, the imaging device 100 includes a pixel substrate 101 and a circuit substrate 102. Each of the pixel substrate 101 and the circuit substrate 102 includes a semiconductor substrate. For example, transistors in circuits included in the pixel array PA and transistors in circuits included in the peripheral circuits are formed on the semiconductor substrate. In the example shown in Fig. 2, the pixel array PA is formed on the pixel substrate 101, and the peripheral circuits are formed on the circuit substrate 102. In Fig. 2, a row scanning circuit 130 and a plurality of row signal lines R ｉare omitted from the illustration. The row scanning circuit 130 is formed on, for example, the circuit board 102. The imaging device 100 is, for example, a single element, and the pixel substrate 101 and the circuit board 102 are stacked on top of each other and joined to each other. Note that part of the peripheral circuit formed on the circuit board 102 may be formed on the pixel substrate 101, or may be formed on another substrate stacked on the pixel substrate 101 and the circuit board 102.

[0062] The signal processing circuit 160 may be disposed in a subsequent stage of the digital output interface 170. That is, the digital signal generated by the AD conversion circuit 140 may be output to the signal processing circuit 160. In this case, the signal processing circuit 160 is formed in an element separate from the element in which the pixel array PA is formed.

[0063] [Circuit Configuration] Next, the circuit configuration of the imaging device 100 according to this embodiment will be described. Fig. 3 is a diagram showing an exemplary circuit configuration of the imaging device 100 according to this embodiment. For simplicity, Fig. 3 schematically shows four of the multiple pixels Px included in the pixel array PA shown in Fig. 1. The basic circuit configuration of the pixels Px is common to the multiple pixels Px.

[0064] 3, the imaging device 100 includes, as peripheral circuits, a current source circuit 180, a voltage supply circuit 190, and a reset voltage supply circuit 198 in addition to the configuration shown in FIG. 1. The imaging device 100 also includes a voltage line 192, a power supply line 194, a reset voltage line 196, and a plurality of reset signal lines Q ｉ Equipped with.

[0065] The current source circuit 180 has a plurality of output signal lines S ｊ Each of the current sources 181 is connected to one of the output signal lines S ｊ , and are connected to a corresponding one of the

[0066] The voltage supply circuit 190 is configured to be able to apply a predetermined voltage to the photoelectric conversion unit 10 of each pixel Px when the imaging device 100 is in operation. The voltage supply circuit 190 is not limited to a specific power supply circuit. The voltage supply circuit 190 may be a circuit that generates a predetermined voltage, or a circuit that converts a voltage supplied from another power source into a predetermined voltage. The voltage supply circuit 190 may be part of the row scanning circuit 130.

[0067] The reset voltage supply circuit 198 is an example of a voltage supply circuit, and is configured to be able to apply a predetermined reset voltage VR to each pixel Px during operation of the imaging device 100. The reset voltage supply circuit 198 is not limited to a specific power supply circuit, similar to the voltage supply circuit 190. The reset voltage supply circuit 198 may be a circuit independent of the voltage supply circuit 190, or one of the reset voltage supply circuit 198 and the voltage supply circuit 190 may be a part of the other.

[0068] Each pixel Px includes a photoelectric conversion unit 10 and a readout circuit 20 electrically connected to the photoelectric conversion unit 10. The photoelectric conversion unit 10 generates charge pairs, such as hole-electron pairs, upon receiving incident light. The charge generated by the photoelectric conversion unit 10 is used as a signal charge. In other words, the photoelectric conversion unit 10 converts light into a signal charge. As will be described in detail below, the photoelectric conversion unit 10 includes a pixel electrode 11, a counter electrode 13, and a photoelectric conversion layer 12 sandwiched between these electrodes. The photoelectric conversion unit 10 of each pixel Px is electrically connected to a voltage line 192 connected to a voltage supply circuit 190, and is configured to apply a predetermined voltage between the pixel electrode 11 and the counter electrode 13 during operation of the imaging device 100. Note that the photoelectric conversion unit 10 is not limited to the above configuration and may be a photodiode formed on a semiconductor substrate. In this case, the imaging device 100 would not include the voltage supply circuit 190 and the voltage line 192.

[0069] In the example shown in FIG. 3 , the readout circuit 20 includes a signal detection transistor 22, an address transistor 24, and a reset transistor 26. The signal detection transistor 22 is also called an amplification transistor and is an example of a second transistor. The reset transistor 26 is an example of a first transistor. In the example shown in FIG. 3 , the number of transistors included in the pixel Px is three: the signal detection transistor 22, the address transistor 24, and the reset transistor 26. Note that the number of transistors included in the pixel Px may be four. By including four or fewer transistors in the pixel Px, the pixel Px can be miniaturized.

[0070] The signal detection transistor 22, the address transistor 24, and the reset transistor 26 are, for example, field effect transistors (FETs) formed on the semiconductor substrate 110. In the following, an example in which N-channel MOSFETs (Metal Oxide Semiconductor Field Effect Transistors) are used as the signal detection transistor 22, the address transistor 24, and the reset transistor 26 will be described.

[0071] The gate of the signal detection transistor 22 is connected to a node FD that is connected to the pixel electrode 11 of the photoelectric conversion unit 10. The node FD is at least a part of a charge accumulation region that accumulates signal charges generated by the photoelectric conversion unit 10, and the potential of the node FD is substantially the same as the potential of the charge accumulation region. The potential of the node FD of the pixel Px after the exposure period corresponds to the amount of signal charges accumulated in the charge accumulation region of the pixel Px during the exposure period.

[0072] The drain of the signal detection transistor 22 is connected to a power supply line 194. When the imaging device 100 is in operation, the power supply line 194 functions as a source follower power supply by applying a power supply voltage VDD of about 3.3 V. The source of the signal detection transistor 22 is connected to the corresponding output signal line S via the address transistor 24. ｊ The drain of the signal detection transistor 22 is connected to the corresponding output signal line S via the address transistor 24. ｊThe output signal is sent to the output signal line S ｊ The analog signal output to is input to the AD conversion circuit 140. The signal detection transistor 22 forms a source follower circuit together with the current source 181 when the address transistor 24 is in the on state.

[0073] The gate of the address transistor 24 is connected to the row signal line R ｉ The row scanning circuit 130 is connected to the row signal line R ｉ By controlling the voltage level applied to the address transistor 24, the row scanning circuit 130 switches on and off the address transistor 24. As a result, the row scanning circuit 130 outputs a signal from the pixel Px belonging to the selected row to the corresponding output signal line S ｊ The signal can be read out.

[0074] One of the drain and source of the reset transistor 26 is connected to the node FD. The other of the drain and source of the reset transistor 26 is connected to a reset voltage line 196. The reset voltage line 196 is connected to a reset voltage supply circuit 198. The reset voltage line 196 is an example of a voltage line to which a voltage is applied from the reset voltage supply circuit 198, and when the imaging device 100 is in operation, a predetermined reset voltage VR is applied to the reset voltage line 196 from the reset voltage supply circuit 198.

[0075] A plurality of reset signal lines Q are provided corresponding to a plurality of pixels Px. ｉ In the example shown in FIG. 3, one reset signal line Q is commonly connected to the gates of the reset transistors 26 of the pixels Px that belong to the same row. ｉ is connected to the reset signal line Q ｉ has a connection to the row scanning circuit 130. Therefore, the row scanning circuit 130 connects the reset signal line Q ｉ By controlling the voltage level applied to the reset transistor 26, it is possible to turn on the reset transistor 26 for a plurality of pixels Px on a row-by-row basis, and reset the potential of the node FD of the pixel Px whose reset transistor 26 is turned on to the reset voltage VR. Furthermore, since the node FD is connected to the pixel electrode 11, resetting the potential of the node FD to the reset voltage VR also resets the potential of the pixel electrode 11 to the reset voltage VR.

[0076] As shown in FIG. 3, the AD conversion circuit 140 has a plurality of output signal lines S ｊ Each of the column signal processing circuits 145 may have a plurality of output signal lines S ｊ Each column signal processing circuit 145 is provided corresponding to one of the columns of pixels Px. Each column signal processing circuit 145 performs signal processing such as AD conversion on the analog signals output from the pixels Px. Each column signal processing circuit 145 includes, for example, a comparator circuit.

[0077] Here, a detailed description will be given of the column signal processing circuit 145. Fig. 4 is a diagram showing an exemplary circuit configuration of the differential amplifier circuit 146 included in the column signal processing circuit 145.

[0078] The differential amplifier circuit 146 receives the signal from the pixel Px through the output signal line S ｊ The differential amplifier circuit 146 receives as inputs an output voltage Vout output from the differential amplifier 145 and a reference signal Vramp output from the reference signal generation circuit 141. The differential amplifier circuit 146 includes capacitors C1 and C2. The output voltage Vout is input to one end of the capacitor C1, and the reference signal Vramp is input to one end of the capacitor C2. The differential amplifier circuit 146 compares the potential of a node Sin connected to the other end of the capacitor C1 with the potential of a node REFin connected to the other end of the capacitor C2, and outputs the comparison result to an output line cmpout. The output line cmpout is connected to a counter 147 included in the column signal processing circuit 145. The counter 147 is, for example, an up-down counter that can count in both positive and negative directions.

[0079] The differential amplifier circuit 146 includes transistors M1 and M2. The transistor M1 is connected to a node Sin, and the transistor M2 is connected to a node REFin. The on / off states of the transistors M1 and M2 are controlled by a control signal Vacds. The differential amplifier circuit 146 stores the input immediately before the transistors M1 and M2 are turned off, and the difference between that input and the subsequent input appears at the nodes Sin and REFin.

[0080] [Device Configuration of Pixel] Next, the device configuration of the pixel Px of the imaging device 100 according to this embodiment will be described. Fig. 5 is a cross-sectional view showing the device structure of the pixel Px according to this embodiment. Note that in Fig. 5, for ease of viewing, hatching indicating the cross section of the insulating layer 50 and the semiconductor substrate 110 has been omitted.

[0081] 5 , an insulating layer 50 covering the readout circuit 20 is disposed between the semiconductor substrate 110 and the photoelectric conversion unit 10. The pixel Px generally includes a semiconductor substrate 110 on which a readout circuit 20 (specifically, the signal detection transistor 22, the address transistor 24, and the reset transistor 26 in FIG. 5 ) is formed, and a photoelectric conversion unit 10 supported by the semiconductor substrate 110. The semiconductor substrate 110 is, for example, a semiconductor substrate included in the pixel substrate 101 described above. In the example shown in FIG. 5 , an insulating layer 50 covering the readout circuit 20 is disposed between the semiconductor substrate 110 and the photoelectric conversion unit 10.

[0082] The photoelectric conversion section 10 includes a pixel electrode 11 supported by an insulating layer 50 , a light-transmitting counter electrode 13 facing the pixel electrode 11 , and a photoelectric conversion layer 12 located between the pixel electrode 11 and the counter electrode 13 .

[0083] The pixel electrode 11 is located closer to the semiconductor substrate 110 than the photoelectric conversion layer 12. The pixel electrode 11 collects signal charges generated in the photoelectric conversion layer 12. The pixel electrode 11 may be formed from a metal such as aluminum or copper, a metal nitride, or polysilicon doped with impurities to provide conductivity. As shown in FIG. 5 , the pixel electrode 11 is spatially separated from the pixel electrodes 11 of other adjacent pixels Px by an insulating layer 50, and is thereby electrically isolated from these.

[0084] The counter electrode 13 is located on the side of the photoelectric conversion layer 12 where light from a subject arrives. The counter electrode 13 faces the pixel electrode 11 across the photoelectric conversion layer 12. The counter electrode 13 is a light-transmitting electrode made of a conductive material such as ITO. In this specification, the term "light-transmitting" means that the photoelectric conversion layer 12 transmits at least a portion of light of a wavelength that can be absorbed, and it is not essential that the counter electrode 13 transmits light over the entire wavelength range of visible light. An optical filter such as a color filter, a microlens, or the like may be arranged on the main surface of the counter electrode 13 opposite the photoelectric conversion layer 12.

[0085] The counter electrode 13 is provided, for example, in the form of a single continuous electrode layer spanning multiple pixels Px. The aforementioned voltage line 192 is connected to the counter electrode 13 of the photoelectric conversion unit 10. While FIG. 3 illustrates a voltage line 192 connected to each of the photoelectric conversion units 10 of multiple pixels Px, the counter electrode 13 of each pixel Px may be part of a single, light-transmitting electrode that is continuous between the multiple pixels Px. Therefore, the counter electrode 13 of each pixel Px is basically at an equipotential, and it is not essential that the voltage line 192 be a wiring that branches into multiple lines.

[0086] The photoelectric conversion layer 12 generates charge pairs through photoelectric conversion when light that has passed through the counter electrode 13 is incident on it. The photoelectric conversion layer 12 is located between the pixel electrode 11 and the counter electrode 13. The photoelectric conversion layer 12 is formed, for example, from an organic material such as an organic semiconductor or an inorganic material such as amorphous silicon. Like the counter electrode 13, the photoelectric conversion layer 12 is provided, for example, in the form of a single photoelectric conversion structure that is continuous across multiple pixels Px. In other words, the photoelectric conversion layer 12 in each pixel Px can be part of a photoelectric conversion structure that is continuously formed across multiple pixels Px.

[0087] By selecting one or more appropriate materials as the photoelectric conversion material to form the photoelectric conversion layer 12, it is possible to obtain a photoelectric conversion layer 12 that exhibits sensitivity in both the visible and infrared regions, for example. Examples of such materials are described in detail in, for example, Patent Document 3. The photoelectric conversion layer 12 may be composed of quantum dots and / or nanotubes. Alternatively, the photoelectric conversion layer 12 may contain quantum dots and / or nanotubes as the photoelectric conversion material. The photoelectric conversion layer 12 may include a layer composed of an organic material and a layer composed of an inorganic material.

[0088] The insulating layer 50 located between the semiconductor substrate 110 and the photoelectric conversion unit 10 includes, for example, multiple insulating layers each formed of silicon dioxide. As shown in Figure 5, a multilayer wiring including at least a conductive structure 52 having one end connected to the pixel electrode 11 of the photoelectric conversion unit 10 is provided inside the insulating layer 50. The conductive structure 52 may include vias and wiring formed of a metal such as copper, a plug formed of polysilicon, or the like. In the example shown in Figure 5, another end of the conductive structure 52 is electrically connected to an impurity region 111 formed in the semiconductor substrate 110.

[0089] The semiconductor substrate 110 has impurity regions 112, 113, 114, and 115 in addition to the impurity region 111. The semiconductor substrate 110 also has an element isolation region 116 that electrically isolates the readout circuit 20 provided for each pixel Px between the pixels Px. In the following, a P-type silicon substrate is exemplified as the semiconductor substrate 110. The semiconductor substrate 110 is not limited to a substrate whose entire surface is made of semiconductor. For example, the semiconductor substrate 110 may be an insulating substrate with a semiconductor layer provided on its surface.

[0090] Each of the impurity regions 111, 112, 113, 114, and 115 is, for example, an N-type diffusion region. Of these impurity regions, the impurity region 111, to which the conductive structure 52 is connected, functions as one of the source region and drain region of the reset transistor 26. The reset transistor 26 further includes an impurity region 112 that functions as the other of the source region and drain region, a gate insulating layer 26g on the semiconductor substrate 110, and a gate electrode 26e on the gate insulating layer 26g. Although not shown in FIG. 5 , the impurity region 112 is connected to the above-mentioned reset voltage line 196.

[0091] The signal detection transistor 22 includes an impurity region 113 and an impurity region 114, a gate insulating layer 22g on the semiconductor substrate 110, and a gate electrode 22e on the gate insulating layer 22g. The impurity region 113 functions as a drain region of the signal detection transistor 22, and the impurity region 114 functions as a source region of the signal detection transistor 22. Although not shown in FIG. 5 , the impurity region 113 is connected to the above-mentioned power supply line 194.

[0092] As shown in FIG. 5, the element isolation region 116 is also provided between the signal detection transistor 22 and the reset transistor 26 .

[0093] The address transistor 24 includes an impurity region 114 and an impurity region 115, a gate insulating layer 24g on the semiconductor substrate 110, and a gate electrode 24e on the gate insulating layer 24g. The impurity region 114 functions as the drain region of the address transistor 24, and the impurity region 115 functions as the source region of the address transistor 24. In the example shown in FIG. 5, the address transistor 24 shares the impurity region 114 with the signal detection transistor 22. Although not shown in FIG. 5, the impurity region 115 has a plurality of impurity regions 114 and 115, which are connected to the above-mentioned plurality of output signal lines S ｊ The corresponding one of them is connected.

[0094] The insulating layer 50 covers the signal detection transistor 22, the address transistor 24, and the reset transistor 26. As shown in FIG. 5 , the conductive structure 52 in the insulating layer 50 is also connected to the gate electrode 22 e of the signal detection transistor 22. That is, the conductive structure 52 in each pixel Px has the function of electrically connecting the pixel electrode 11 of the photoelectric conversion unit 10 to the readout circuit 20 including the signal detection transistor 22 and the like formed on the semiconductor substrate 110. Specifically, the conductive structure 52 electrically connects the pixel electrode 11, the gate electrode 22 e of the signal detection transistor 22, and the impurity region 111 that functions as one of the source region and drain region of the reset transistor 26.

[0095] Furthermore, the conductive structure 52 also functions as part of a charge accumulation region that temporarily accumulates charges collected by the pixel electrode 11, i.e., signal charges. As described with reference to FIG. 3 , the voltage supply circuit 190 applies a predetermined voltage to the photoelectric conversion unit 10 of each pixel Px via a voltage line 192. For example, the voltage supply circuit 190 applies a voltage to the counter electrode 13 of the photoelectric conversion unit 10, thereby creating a predetermined potential difference between the counter electrode 13 and the pixel electrode 11 during an exposure period. For example, the voltage supply circuit 190 applies a voltage to the counter electrode 13 so that the potential of the counter electrode 13 is higher than that of the pixel electrode 11. This allows the pixel electrode 11 to collect, as signal charges, positive charges, such as holes, among positive and negative charges generated in the photoelectric conversion layer 12 by incident light. For example, when the imaging device 100 performs rolling shutter driving, as described below, the voltage supply circuit 190 constantly applies a voltage to the counter electrode 13 to collect signal charges in the pixel electrode 11.

[0096] The signal charge is temporarily stored in a charge storage region that includes the conductive structure 52 as a part thereof. Similar to the conductive structure 52, the impurity region 111 formed in the semiconductor substrate 110, the pixel electrode 11 of the photoelectric conversion unit 10, and the gate electrode 22 e of the signal detection transistor 22 also function as part of the charge storage region that temporarily stores the signal charge.

[0097] [Method of Driving the Imaging Device] Next, a method of driving the imaging device 100 according to this embodiment will be described.

[0098] FIG. 6 is a flowchart illustrating an example of a method for driving the imaging device 100 according to the present embodiment. FIG. 7 is a timing chart illustrating an example of a method for driving the imaging device 100 according to the present embodiment. FIG. 8 is a diagram illustrating an example of details of driving the imaging device 100 according to the present embodiment during a reset signal readout period and a pixel signal readout period. In FIG. 7, time passes from time t0 to time t24. FIG. 8 also illustrates details of driving the imaging device 100 during a reset signal readout period for the pixel Px in the 0th row R0 from time t1 to time t2 and during a pixel signal readout period for the pixel Px in the 0th row R0 from time t7 to time t8. In FIG. 8, time passes from time T0 to time T18. Times t1, t2, t7, and t8 in FIG. 7 correspond to times T0, T9, T10, and T18 in FIG. 8, respectively.

[0099] 7 indicates the timing of the rising edge of the pulse of the vertical synchronization signal VD supplied to the control circuit 220. The rising edge of the pulse of the vertical synchronization signal VD indicates the start of a period for reading out pixel signals.

[0100] 7 and 8, "HD" indicates the timing of the rising edge of a pulse of the horizontal synchronization signal HD supplied to the control circuit 220. In the horizontal synchronization signal HD, the period from the rising edge of one pulse to the rising edge of the next pulse corresponds to one horizontal scanning period, 1H.

[0101] In FIG. 7 , "R0," "R1," "R2," and "R3" respectively represent multiple blocks indicating the operation of multiple pixels Px included in the imaging area. For simplicity, the number of rows of the multiple pixels Px is assumed to be four, from the 0th row R0 to the 3rd row R3, and the operation of the pixels Px is schematically represented by multiple rectangular blocks. "R0" to "R3" correspond to the 0th row R0 to the 3rd row R3, respectively. In FIG. 7 , white rectangular blocks schematically represent exposure periods within a frame period. In addition, in FIG. 7 , rectangular blocks hatched with vertical lines represent readout periods of reset signals that represent reset levels corresponding to signal levels in the dark. In addition, in FIG. 7 , rectangular blocks hatched with diagonal lines represent readout periods of pixel signals that represent an image of a subject. In addition, in FIG. 7 , rectangular blocks hatched with dots schematically represent blanking periods other than the exposure period, the readout period of reset signals, and the readout period of pixel signals.

[0102] 8, "ΦS" indicates the voltage level of the row selection signal ΦS supplied to the gate of the address transistor 24 of the pixel Px in the 0th row R0 from the row scanning circuit 130. When the row selection signal ΦS is at a high level, the address transistor 24 is turned on, and when the row selection signal ΦS is at a low level, the address transistor 24 is turned off.

[0103] 8, "ΦR" indicates the voltage level of the reset control signal ΦR supplied to the gate of the reset transistor 26 of the pixel Px in the 0th row R0 from the row scanning circuit 130. When the reset control signal ΦR is at a high level, the reset transistor 26 is turned on, and when the reset control signal ΦR is at a low level, the reset transistor 26 is turned off.

[0104] 8 indicates the voltage level of the control signal Vacds input to the differential amplifier circuit 146. The control signal Vacds is output from, for example, the control circuit 220. When the control signal Vacds is at a low level, the transistors M1 and M2 are turned on, and when the control signal Vacds is at a high level, the transistors M1 and M2 are turned off.

[0105] In FIG. 8, "Vramp" indicates the voltage waveform of the reference signal Vramp input from the reference signal generating circuit 141 to the differential amplifier circuit 146.

[0106] "ADcount" in FIG. 8 indicates the voltage level of a counter operation pulse ADcount, which indicates the period during which the AD conversion circuit 140 performs a counting operation when performing AD conversion. The counter operation pulse ADcount is output, for example, from the control circuit 220. While the counter operation pulse ADcount is at a high level, the counter 147 operates in accordance with the output of the differential amplifier circuit 146. In the counting operation, the counter 147 starts counting in synchronization with the start of the ramp-down of the reference signal Vramp, and counts the time until the comparison result of the differential amplifier circuit 146 is inverted and the comparison result output to the output line cmpout changes. Note that, although the reference signal Vramp is ramping down in the example shown in FIG. 8, it may also ramp up.

[0107] "Vout" in FIG. 8 indicates the voltage from the pixel Px to the output signal line S ｊ , the output voltage Vout (i.e., the signal level of the analog signal output from the pixel Px) is shown.

[0108] In the example shown in FIG. 6, the driving method of the imaging device 100 roughly includes a step of resetting the potential of the charge accumulation region of the pixel Px (step S11), and a step of transmitting a first signal corresponding to the potential of the charge accumulation region when the reset transistor 26 is in an on state to the output signal line S ｊ a step of outputting a second signal corresponding to the potential of the charge storage region when the reset transistor 26 is in the OFF state to the output signal line S ｊ(step S13), a step of generating a fifth signal which is a digital signal corresponding to the difference between the first signal and the second signal (step S14), a step of storing the fifth signal in a frame memory (step S15), a step of accumulating the signal charge generated by the photoelectric conversion unit 10 in the charge accumulation region after resetting the pixel Px (step S16), and a step of outputting a third signal corresponding to the potential of the charge accumulation region in a state in which the signal charge has been accumulated in the step of accumulating the signal charge in the charge accumulation region to the output signal line S. ｊ a step of outputting a fourth signal corresponding to the potential of the charge storage region when the reset transistor 26 is in the OFF state to the output signal line S ｊ (step S18), a step of generating a sixth signal that is a digital signal corresponding to the difference between the third signal and the fourth signal (step S19), and a step of generating a seventh signal based on the fifth signal and the sixth signal (step S20). An exemplary method of driving the image capture device 100 will be described in detail below with reference to Figures 7 and 8. The image capture device 100 shown in Figures 7 and 8, which will be described below, is driven based on the control of the control circuit 220, for example.

[0109] 7 shows an example of an operation based on a so-called rolling shutter, in which exposure and signal readout are performed for each row of a plurality of pixels Px. Here, we first focus on row 0 R0 among rows 0 R0 to 3 R3. Image acquisition begins with resetting the potential of the charge storage region of each pixel Px and reading out the reset signal. In the example shown in FIG. 7 , where k is an integer greater than or equal to 0, the reset signal readout period for pixels Px belonging to row 0 R0 begins at time t1 during the kth frame period.

[0110] 8, the address transistor 24 is turned on at time T1, and the reset transistor 26 is turned on at time T2. This causes the potential of the charge storage region, which at least partially includes the node FD, to be aligned with the potential of the reset voltage line 196. That is, the potential of the charge storage region is set to the reset voltage VR. Furthermore, since the address transistor 24 is in the on state, an analog signal corresponding to the potential of the node FD is output to the output signal line S ｊ At this time, the signal is output to the output signal line S ｊ The analog signal output to the capacitor C1 is the first signal Sig1 corresponding to the potential of the charge storage region when the reset transistor 26 is in the on state. At time T2, the transistor M1 is in the on state, so that a charge corresponding to the first signal Sig1 is stored in the capacitor C1.

[0111] When the potential of the charge storage region of the pixel Px is the reset voltage VR, the output signal line S ｊ is Vrst, and the gate-source voltage of the signal detection transistor 22 is Vgs(SF), the first signal Sig1 is Vrst-Vgs(SF).

[0112] Next, at time T3, transistors M1 and M2 are turned off, and nodes Sin and REFin are brought into a floating state. Next, at time T4, the reference signal Vramp ramps down and the counter 147 starts counting. Thus, while pixel Px is outputting the first signal Sig1, the AD conversion circuit 140 performs an AD conversion counting operation using the first signal Sig1 as a reference voltage. In this counting operation, the AD conversion circuit 140 can also be said to be counting the offset level in the AD conversion. At this time, the counter 147 counts in the negative direction. Furthermore, the counter 147 retains the count value without resetting it.

[0113] Next, the counting operation is completed, and at time T5, the reset transistor 26 is turned off. At this time, the address transistor 24 is in the on state, and the output signal line S ｊThe analog signal output to is a second signal Sig2 corresponding to the potential of the charge accumulation region when the reset transistor 26 is in an off state, after the first signal Sig1 is output and before signal charge is accumulated by exposure. The second signal Sig2 can also be considered a reset signal representing a reset level. The second signal Sig2 includes reset noise that occurs when the reset transistor 26 is turned off. Specifically, the second signal Sig2 is a signal in which reset noise is superimposed on the first signal Sig1, and if the reset noise is kTC, then the second signal Sig2 is Vrst - Vgs(SF) + kTC.

[0114] Also, since the transistor M1 is in the off state, the output signal line S ｊ When the second signal Sig2 is output to the node Sin, the potential of the node Sin becomes the difference voltage between the first signal Sig1 and the second signal Sig2, which is obtained by subtracting the second signal Sig2 from the first signal Sig1. In other words, the differential amplifier circuit 146 acquires the difference voltage between the first signal Sig1 and the second signal Sig2.

[0115] Next, at time T6, the reference signal Vramp ramps down again, and the counter 147 starts counting again. In this manner, the AD conversion circuit 140 performs counting of the difference between the first signal Sig1 and the second signal Sig2 during the period in which the pixel Px outputs the second signal Sig2. At this time, the counter 147 counts in the positive direction from the count value held in the counting operation started at time T4. As a result, the AD conversion circuit 140 generates, as the AD conversion result, a fifth signal, which is a digital signal corresponding to the difference between the first signal Sig1 and the second signal Sig2. Furthermore, since the counter 147 counted in the negative direction during the counting operation started at time T4, by counting in the positive direction in the opposite direction, the offset level in the AD conversion is removed, and a fifth signal from which count variations have been removed is obtained.

[0116] Since the fifth signal = the first signal Sig1 - the second signal Sig2, the fifth signal is a digital signal corresponding to (Vrst - Vgs(SF)) - (Vrst - Vgs(SF) + kTC) = -kTC. That is, in the fifth signal, Vrst and Vgs(SF) are removed, and only -kTC corresponding to the reset noise remains.

[0117] The counter 147 may count in the positive direction from time T3 onwards and count in the negative direction from time T6 onwards. In this case, the fifth signal is a digital signal corresponding to kTC.

[0118] The fifth signal generated by the AD conversion circuit 140 is input to, for example, the signal processing circuit 160 and stored in the frame memory 161 by the signal processing circuit 160. The fifth signal is temporarily held in the frame memory 161.

[0119] Then, after the counting operation is completed at time T7, at time T8, the address transistor 24 is turned off and the transistors M1 and M2 are turned on. By turning off the address transistor 24 of the pixel Px belonging to the 0th row R0, a signal is output from the pixel Px belonging to the 0th row R0 to the output signal line S ｊ The output of the analog signal to the

[0120] As shown in FIG. 7 , the reset signal readout operation is performed sequentially row by row of pixels Px in synchronization with the horizontal synchronization signal HD. The interval between pulses of the horizontal synchronization signal HD, i.e., the 1H period, represents the period from when a row is selected to when the next row is selected. For example, from time t1 to time t2, the pixel Px belonging to the 0th row R0 is reset and the first signal Sig1 and the second signal Sig2 are output from the pixel Px. From time t2 to time t3, the pixel Px belonging to the 1st row R1 is reset and the first signal Sig1 and the second signal Sig2 are output from the pixel Px. As can be seen from the above, the reset signal readout period includes a period during which the potential of the charge storage region of the pixel Px is reset. Furthermore, during the reset signal readout period, the reset transistor 26 is not turned on after the second signal Sig2 is output, and the potential of the charge storage region of the pixel Px is not reset.

[0121] The AD conversion circuit 140 generates a fifth signal corresponding to the difference between the first signal Sig1 and the second signal Sig2 sequentially output for each row of the pixels Px. The signal processing circuit 160 stores the fifth signal generated by the AD conversion circuit 140 in the frame memory 161. That is, the fifth signals corresponding to each of the pixels Px from the 0th row R0 to the 3rd row R3 generated between time t1 and time t5 in FIG. 7 are temporarily held in the frame memory 161.

[0122] After the reset signal readout period ends, the exposure period begins. In the example shown in FIG. 7 , focusing on the 0th row R0, the period from time t2 to time t7 is the exposure period for the kth frame period. The exposure period is a period for accumulating signal charges generated by the photoelectric conversion unit 10 in accordance with the amount of exposure for the pixels Px in the charge accumulation region. The length of the exposure period for each row of the multiple pixels Px is, for example, in the range of 1 / 16000 seconds or more and 1 / 60 seconds or less.

[0123] The counter electrode 13 of the photoelectric conversion unit 10 of each pixel Px is supplied with a predetermined voltage V1 from the voltage supply circuit 190 via a voltage line 192, and is thereby set to, for example, a high potential state relative to the pixel electrode 11. The potential of the pixel electrode 11 immediately after reset is determined by the above-mentioned reset voltage VR, and immediately after reset, a bias voltage of (V1-VR) is applied between the pixel electrode 11 and the counter electrode 13.

[0124] By increasing the potential of the counter electrode 13 relative to the pixel electrode 11, positive charges among the charge pairs generated by photoelectric conversion are collected by the pixel electrode 11. The PN junction formed in the semiconductor substrate 110 by forming the impurity region 111 functions as a junction capacitance that temporarily stores the positive charges collected by the pixel electrode 11. When holes are used as signal charges, the potential of the impurity region 111 serving as a charge storage portion increases as the signal charges accumulate in the impurity region 111. Note that, although (V1-VR)>0 holds when holes are used as signal charges, it is also possible to use electrons as signal charges by, for example, applying a voltage to the counter electrode 13 that makes the potential of the counter electrode 13 lower than that of the pixel electrode 11. When electrons are used as signal charges, the potential of the impurity region 111 serving as a charge storage portion decreases as the signal charges accumulate in the impurity region 111.

[0125] After a predetermined time has elapsed since the end of the readout period of the reset signal, a pixel signal corresponding to the potential of the charge accumulation region after the exposure period is read out. In the example shown in Figure 7, the readout period of the pixel signal from pixel Px belonging to row 0 R0 starts at time t7 based on the vertical synchronization signal VD.

[0126] Specifically, as shown in FIG. 8, at time T11, the address transistor 24 is turned on, and an analog signal corresponding to the potential of the charge storage region is output to the corresponding output signal line S ｊ At this time, the signal is output to the output signal line S ｊThe analog signal output to the capacitor C1 is the third signal Sig3, which corresponds to the potential of the charge accumulation region in a state in which signal charge has been accumulated during the exposure period after the second signal Sig2 has been output. At time T11, the transistor M1 is in the on state, so that charge corresponding to the third signal Sig3 is accumulated in the capacitor C1.

[0127] The third signal Sig3 can also be said to be a pixel signal that represents an image of a subject based on ambient light such as sunlight. The third signal Sig3 includes reset noise generated by a reset operation performed before the exposure period. The third signal Sig3 is also an analog signal that corresponds to the potential of the charge storage section that has increased in accordance with the amount of signal charge accumulated, relative to the potential of the charge storage section before the exposure period. A signal is output from the output signal line S in accordance with the amount of signal charge accumulated in the charge storage region during the exposure period. ｊ When the output voltage of the pixel Px appearing in the third signal Sig3 is Vrst-Vgs(SF)+kTC+Vsig, the third signal Sig3 is Vrst-Vgs(SF)+kTC+Vsig.

[0128] Next, at time T12, transistors M1 and M2 are turned off, and nodes Sin and REFin are brought into a floating state. Next, at time T13, the reference signal Vramp ramps down and the counter 147 starts counting. Thus, during the period when pixel Px is outputting the third signal Sig3, the AD conversion circuit 140 performs an AD conversion count operation using the third signal Sig3 as a reference voltage. At this time, the counter 147 counts in the negative direction. Therefore, the counter 147 performs counting operations such that the positive and negative directions are the same during the period when pixel Px is outputting the first signal Sig1 and during the period when pixel Px is outputting the third signal Sig3. Furthermore, the counter 147 retains the count value without resetting it.

[0129] Next, the counting operation is completed, and at time T14, the reset transistor 26 is turned on. As a result, the potential of the charge storage region of the pixel Px is set to the reset voltage VR. At this time, the address transistor 24 is in the on state, and the output signal line S ｊThe analog signal output to the reset transistor 26 is a fourth signal Sig4 that corresponds to the potential of the charge storage region when the reset transistor 26 is in the on state after the third signal Sig3 is output. The fourth signal Sig4 is Vrst-Vgs(SF), similar to the first signal Sig1.

[0130] Also, since the transistor M1 is in the off state, the output signal line S ｊ When the fourth signal Sig4 is output to the node Sin, the potential of the node Sin becomes a voltage difference between the third signal Sig3 and the fourth signal Sig4, which is obtained by subtracting the fourth signal Sig4 from the third signal Sig3. In other words, the differential amplifier circuit 146 acquires the voltage difference between the third signal Sig3 and the fourth signal Sig4.

[0131] Next, at time T15, the reference signal Vramp ramps down again, and the counter 147 starts counting again. In this manner, the AD conversion circuit 140 performs counting of the AD conversion of the difference between the third signal Sig3 and the fourth signal Sig4 during the period in which the pixel Px outputs the fourth signal Sig4. At this time, the counter 147 counts in the positive direction. As a result, the AD conversion circuit 140 generates, as the AD conversion result, a sixth signal, which is a digital signal corresponding to the difference between the third signal Sig3 and the fourth signal Sig4. Furthermore, since the counter 147 counted in the negative direction during the counting operation that started at time T13, by counting in the opposite positive direction at this time, the offset level in the AD conversion is removed, and a sixth signal from which count variations have been removed is obtained. Furthermore, the counter 147 performs counting operations such that the positive and negative directions are the same during the period when the pixel Px outputs the second signal Sig2 and during the period when the pixel Px outputs the fourth signal Sig4.

[0132] Since the sixth signal = the third signal Sig3 - the fourth signal Sig4, the sixth signal is a digital signal corresponding to (Vrst - Vgs(SF) + kTC + Vsig) - (Vrst - Vgs(SF)) = kTC + Vsig. In other words, in the sixth signal, Vrst and Vgs(SF) are removed, and kTC and Vsig corresponding to the reset noise and the amount of signal charge accumulated in the charge accumulation region during the exposure period remain.

[0133] The sixth signal generated by the AD conversion circuit 140 is input to, for example, the signal processing circuit 160. The signal processing circuit 160 generates a seventh signal based on the sixth signal and the fifth signal temporarily stored in the frame memory 161. Specifically, the signal processing circuit 160 generates the seventh signal by taking the sum of the digital value of the fifth signal and the digital value of the sixth signal. In other words, since the seventh signal = the fifth signal + the sixth signal, the seventh signal is a digital signal corresponding to (-kTC) + (kTC + Vsig) = Vsig. This removes the reset noise kTC, resulting in a digital signal with reduced noise. The seventh signal can also be considered a digital signal indicating the difference between the reset signal and the pixel signal during the kth frame period.

[0134] The signal processing circuit 160 can also generate the seventh signal by subtracting the digital value of the fifth signal from the digital value of the sixth signal and calculating the difference between the fifth and sixth signals. In this case, the counter 147 counts in the positive direction during the counting operation starting from time T3, counts in the negative direction during the counting operation starting from time T6, counts in the negative direction during the counting operation starting from time T13, and counts in the positive direction during the counting operation starting from time T15. That is, the counter 147 performs counting operations such that the positive and negative directions are different between the counting operation during the period when the pixel Px outputs the first signal Sig1 and the counting operation during the period when the pixel Px outputs the third signal Sig3. The counter 147 also performs counting operations such that the positive and negative directions are different between the counting operation during the period when the pixel Px outputs the second signal Sig2 and the counting operation during the period when the pixel Px outputs the fourth signal Sig4. Since the seventh signal = the sixth signal - the fifth signal, even in this case, the seventh signal is a digital signal corresponding to (kTC + Vsig) - kTC = Vsig. In this way, the signal processing circuit 160 generates the seventh signal by performing a process to remove reset noise from the sixth signal using the fifth signal. When the count directions of the count with respect to the reference voltage and the count with respect to the differential voltage are the same during the reset signal readout period and the pixel signal readout period, the signal processing circuit 160 generates a seventh signal corresponding to the sum of the fifth signal and the sixth signal. Furthermore, when the count directions of the count with respect to the reference voltage and the count with respect to the differential voltage are opposite during the reset signal readout period and the pixel signal readout period, the signal processing circuit 160 generates a seventh signal corresponding to the difference between the fifth signal and the sixth signal.

[0135] The signal processing circuit 160 outputs the seventh signal as pixel value data. The seventh signal output from the signal processing circuit 160 is output to the outside, for example, via the digital output interface 170. As described above, the reset noise remaining in the sixth signal has been removed from the seventh signal, and the imaging device 100 can output data from which the effects of the reset noise have been removed.

[0136] At time T16, the counting operation is completed and the reset transistor 26 is turned off. ｊ During the period (from time T14 to time T16) when the reset transistor 26 is in the on state, the first signal Sig1 is output to the output signal line S ｊ The period is longer than the period (from time T2 to time T5) during which the reset transistor 26 is in the on state when the pixel Px belonging to the 0th row R0 is output to the output signal line S. Then, at time T17, the address transistor 24 is turned off and the transistors M1 and M2 are turned on. By turning off the address transistor 24 of the pixel Px belonging to the 0th row R0, the pixel Px belonging to the 0th row R0 is supplied with the signal S ｊ The output of the analog signal to the

[0137] As shown in Figure 7, the pixel signal readout operation described above is performed sequentially row by row of pixels Px in synchronization with the horizontal synchronization signal HD. As can be seen from the above, the pixel signal readout period includes a period for resetting the potential of the charge accumulation region of the pixel Px. At time t11, the pixel signal readout period for the pixels Px from the 0th row R0 to the 3rd row R3 is completed, thereby ending the kth frame period. After the kth frame period ends, the k+1th frame period following the kth frame period begins, and during the k+1th frame period, the same operation as during the kth frame period is performed.

[0138] In the example shown in FIG. 7 , the readout period for sequential reset signals on a row-by-row basis and the readout period for sequential pixel signals on a row-by-row basis do not overlap, but they may overlap as in Patent Document 1. Also, in the example shown in FIG. 7 , the kth frame period and the k+1th frame period do not overlap, but they may overlap as in Patent Document 1. Also, in the example shown in FIG. 7 , the kth frame period and the k+1th frame period have the same frame period length (exposure period length), but they may differ as in Patent Document 1. Furthermore, the operations in the driving method of the imaging device 100 described above may be performed earlier or later, or the order of the operations may be reversed, as long as no change occurs in the output result.

[0139] Furthermore, while the driving method of the imaging device 100 described above illustrates an example of operation based on a rolling shutter, the imaging device 100 may also operate based on a global shutter. In operation based on a global shutter, a predetermined voltage V1 is supplied to the counter electrode 13 by the voltage supply circuit 190 during an exposure period common to all pixels Px. As a result, signal charges are collected by the pixel electrodes 11 in all pixels Px. Before and after the exposure period, the voltage supply circuit 190 supplies the counter electrode 13 with a voltage that substantially prevents signal charge movement in the photoelectric conversion unit 10, for example, a voltage V2 that causes the potential difference between the pixel electrodes 11 and the counter electrode 13 to be close to zero. As a result, signal charges generated by photoelectric conversion in all pixels Px are substantially not accumulated in the charge accumulation region. In operation based on a global shutter, the period during which the voltage V1 is supplied to the counter electrode 13 is the exposure period common to all pixels Px. During periods other than the exposure period, the voltage V2 is supplied to the counter electrode 13, and operations are performed during the reset signal readout period and the pixel signal readout period.

[0140] [Effects, etc.] As described above, in the driving method of the imaging device 100, the AD conversion circuit 140 generates a fifth signal corresponding to the difference between the first signal Sig1 and the second signal Sig2, and generates a sixth signal corresponding to the difference between the third signal Sig3 and the fourth signal Sig4.

[0141] As described above, the first signal Sig1, the second signal Sig2, the third signal Sig3, and the fourth signal Sig4 each contain a component of Vgs(SF), which is the gate-source voltage of the signal detection transistor 22. Therefore, Vgs(SF) is removed from the fifth and sixth signals due to the difference between the first signal Sig1 and the second signal Sig2 and the difference between the third signal Sig3 and the fourth signal Sig4. The Vgs(SF) component can be an offset component in the signal output from pixel Px, so removing Vgs(SF) can reduce the offset component in the signal output from pixel Px. This point will be described in detail below.

[0142] Even if the potential of the charge accumulation region is the same, the output voltage of the pixel Px fluctuates due to variations in the characteristics of the signal detection transistor 22. Specifically, the Vgs(SF) component of the output voltage of the pixel Px varies depending on the threshold voltage Vth of the signal detection transistor 22. Therefore, if the threshold voltage Vth of the signal detection transistor 22 varies among multiple pixels Px and among production lots of the imaging device 100, Vgs(SF) will also vary. As a result, the signal level corresponding to the magnitude of the variation in Vgs(SF) becomes an offset component. In subsequent processing, a design that can handle signals superimposed with an offset component corresponding to the maximum signal level of the variation is required. In other words, the magnitude of the variation in Vgs(SF) corresponds to the magnitude of the offset component.

[0143] The Vgs(SF) component is included in both the second signal Sig2, which is a reset signal representing the reset level, and the third signal Sig3, which is a pixel signal representing the image of the subject. Therefore, for example, it is possible to remove the Vgs(SF) component by temporarily storing a digital signal corresponding to the second signal Sig2 in the frame memory 161 and then calculating the difference between this and the digital signal corresponding to the third signal Sig3. However, using this method can result in adverse effects, such as an increase in the bit width of the signal stored in the frame memory 161. Furthermore, using this method results in the offset component occupying the signal range of the AD conversion, making it difficult to shorten the AD conversion time and reduce the number of gradations of the AD conversion. This point will be explained with reference to Figures 9A and 9B.

[0144] FIG. 9A is a diagram showing a case where the distribution of the AD-converted output of the signal from pixel Px is wide. FIG. 9B is a diagram showing a case where the distribution of the AD-converted output of the signal from pixel Px is narrow. In the graphs of FIGS. 9A and 9B, the horizontal axis indicates the signal level of the AD-converted output of the signal from pixel Px, and the vertical axis indicates the number of pixels corresponding to the output indicated on the horizontal axis. Also, in FIGS. 9A and 9B, the bit width of the AD-converted output is schematically shown below the graph. The graph of FIG. 9A is a diagram showing an example of the distribution of the AD-converted output when the AD conversion circuit 140 AD-converts the second signal Sig2 directly. FIG. 9B is a diagram showing an example of the distribution of the AD-converted output when the AD conversion circuit 140 outputs a fifth signal corresponding to the difference between the first signal Sig1 and the second signal Sig2, as in the above-described driving method.

[0145] As shown in FIG. 9A , when AD-converting the second signal Sig2 containing a Vgs(SF) component, the output after AD conversion varies significantly for each pixel Px due to variations in the Vgs(SF) component. To ensure a certain level of resolution in AD conversion, AD conversion must be performed with at least 7-bit gradation, as indicated by the hatched area. To ensure saturation is avoided, AD conversion with 8-bit gradation is desirable. Therefore, the frame memory 161 also requires an 8-bit capacity per pixel. Furthermore, if AD-converting the third signal Sig3 requires 10-bit gradation, AD conversion with at least 17-bit gradation is required.

[0146] In contrast, as shown in FIG. 9B , the output after AD conversion when outputting the fifth signal is unaffected by the Vgs(SF) component, and the variation between pixels Px is smaller than in the case shown in FIG. 9A . In the example shown in FIG. 9B , even when AD conversion is performed at the same resolution as in FIG. 9A , AD conversion can be performed with the 3-bit gradation indicated by the hatched area. Considering the need to ensure saturation, AD conversion can also be performed with 4-bit gradation. This allows the capacity of the frame memory 161 to be reduced compared to the case shown in FIG. 9A . Furthermore, as with the fifth signal, AD conversion for generating the sixth signal is unaffected by the Vgs(SF) component, and if the gradation corresponding to Vsig is 10 bits, AD conversion can be performed with 13-bit gradation.

[0147] In this way, the influence of variations in Vgs(SF) is eliminated in the fifth signal, and the offset component of the signal is reduced. This allows the capacity of the frame memory 161 to be reduced. For example, the bit width of the fifth signal held in the frame memory 161 is 7 bits or less. Reducing the capacity of the frame memory 161 also enables the imaging device 100 to be downsized. Furthermore, the bit width of the fifth signal held in the frame memory 161 is, for example, 4 bits or more. The bit width of the fifth signal held in the frame memory 161 may be 5 bits or more.

[0148] Furthermore, in the example of the driving method described above, the AD conversion circuit 140 generates the fifth signal by performing a count operation on the difference between the first signal Sig1 and the second signal Sig2, and generates the sixth signal by performing a count operation on the difference between the third signal Sig3 and the fourth signal Sig4. This prevents offset components caused by variations in Vgs(SF) from unnecessarily occupying the signal range of AD conversion, making it possible to ensure the signal range of AD conversion, shorten the conversion time of AD conversion, and reduce the number of gradations of AD conversion.

[0149] [Modification 1] Next, a description will be given of Modification 1 of Embodiment 1. The following description will focus on the differences from Embodiment 1, and the description of the commonalities will be omitted or simplified.

[0150] Fig. 10 is a diagram showing an exemplary circuit configuration of an image pickup device 100A according to this modification. For simplicity, Fig. 10 shows only four of the multiple pixels Px included in the pixel array PA, similar to Fig. 3 .

[0151] As shown in FIG. 10, an imaging device 100A according to this modification is different from the imaging device 100 according to the first embodiment in that a switch 197 is further provided.

[0152] The switch 197 is disposed between a reset voltage supply circuit 198, which is an example of a voltage supply circuit, and a reset voltage line 196, which is an example of a voltage line, and switches between electrical connection and disconnection between the reset voltage supply circuit 198 and the reset voltage line 196. The switch 197 is, for example, an N-channel MOSFET, but the configuration of the switch 197 is not particularly limited. For example, the switch 197 may be a P-channel MOSFET. An example in which an N-channel MOSFET is used for the switch 197 will be described below.

[0153] The switch 197 operates, for example, under the control of the control circuit 220. For example, the switch 197 disconnects the reset voltage supply circuit 198 from the reset voltage line 196 while the reset transistor 26 is in the on state. Because the reset voltage line 196 has parasitic capacitance with other wiring, etc., it can hold the reset voltage VR and reset the potential of the charge accumulation region of the pixel Px even when it is disconnected from the reset voltage supply circuit 198. Note that the imaging device 100A may also include a capacitor for holding the reset voltage VR. In this case, the capacitor may be located anywhere as long as it is connected to the reset voltage line 196 that connects the switch 197 and the reset transistor 26. Furthermore, multiple capacitors may be connected to the reset voltage line 196.

[0154] Furthermore, in the example shown in FIG. 10 , the imaging device 100A includes one switch 197, but this is not limiting. The imaging device 100A may include multiple switches 197. In this case, the arrangement of the multiple switches 197 is selected according to the layout of the reset voltage lines 196 and is not particularly limited. For example, the multiple switches 197 may be arranged in the layout shown in FIG. 11 or 12 . FIG. 11 is a diagram showing an example of the arrangement of the multiple switches 197. FIG. 12 is a diagram showing another example of the arrangement of the multiple switches 197. In the example shown in FIG. 11 , multiple reset voltage lines 196 and multiple switches 197 are provided corresponding to each column of pixels Px. In the example shown in FIG. 12 , multiple reset voltage lines 196 and multiple switches 197 are provided corresponding to each row of pixels Px. In the examples shown in FIGS. 11 and 12 , each of the multiple switches 197 is connected to a corresponding one of the multiple reset voltage lines 196.

[0155] Next, a driving method of the imaging device 100A according to this modified example will be described. FIG. 13 is a diagram illustrating an example of details of driving the imaging device 100A according to this modified example during the reset signal readout period and the pixel signal readout period. FIG. 13 illustrates details of driving the imaging device 100A during the reset signal readout period and the pixel signal readout period of the pixel Px in the 0th row R0. Note that the same driving as shown in FIG. 13 is performed during the reset signal readout period and the pixel signal readout period of the pixel Px in rows other than the 0th row R0. The terms "HD," "ΦS," "ΦR," "Vacds," "Vramp," "ADcount," and "Vout" in FIG. 13 are the same as those in FIG. 8. Furthermore, in the driving method of the imaging device 100A shown in FIG. 13, the timing of the exposure period, reset signal readout period, and pixel signal readout period of the pixels Px in each row is the same as the example described in FIG. 7.

[0156] 13 indicates the voltage level of the control signal Φrst supplied to the switch 197. When the control signal Φrst is at a high level, the switch 197 is turned on, and the reset voltage supply circuit 198 and the reset voltage line 196 are electrically connected. When the control signal Φrst is at a low level, the switch 197 is turned off, and the reset voltage supply circuit 198 and the reset voltage line 196 are electrically disconnected.

[0157] In the example shown in FIG. 13, the imaging device 100A is driven in the same manner as the imaging device 100 shown and described with reference to FIG. 8, except that the switch 197 is driven in addition.

[0158] 13 , switch 197 is turned off at time T2 and turned on at time T5. Switch 197 is also turned off at time T14 and turned on at time T16. That is, switch 197 disconnects reset voltage supply circuit 198 from reset voltage line 196 during the periods from time T2 to time T5 and from time T14 to time T16, when reset transistor 26 is in the on state.

[0159] In the reset voltage supply circuit 198, noise from circuits and electronic components inside and outside the imaging device 100A can cause periods in which the output voltage of the reset voltage supply circuit 198 is unstable. Furthermore, in the imaging device 100A, the AD conversion circuit 140 performs counting operations during periods in which the pixel Px outputs the first signal Sig1 and the fourth signal Sig4, which are periods in which the pixel Px outputs a signal when the reset transistor 26 is in the on state. Therefore, in the imaging device 100A, the reset transistor 26 tends to be in the on state for a long time, which can make it difficult to reset the potential of the charge storage region of the pixel Px while avoiding periods in which the output voltage of the reset voltage supply circuit 198 is unstable. However, in the example shown in FIG. 13 , the reset voltage supply circuit 198 and the reset voltage line 196 are disconnected during periods in which the reset transistor 26 is in the on state, so fluctuations in the output voltage of the reset voltage supply circuit 198 do not affect the potential of the charge storage region of the pixel Px when it is reset. Therefore, in the AD conversion by the AD conversion circuit 140, the result of the counting operation during the period when the pixel Px outputs the first signal Sig1 and the result of the counting operation during the period when the pixel Px outputs the fourth signal Sig4 are stabilized, and noise in the fifth and sixth signals is reduced.

[0160] 13, the switch 197 is turned on while the reset transistor 26 is in the off state, and connects the reset voltage supply circuit 198 and the reset voltage line 196. As a result, the voltage of the reset voltage line 196 is held at the reset voltage VR.

[0161] The switch 197 may disconnect the reset voltage supply circuit 198 from the reset voltage line 196 during at least a portion of the period during which the reset transistor 26 is in the on state. This suppresses the effect of fluctuations in the output voltage of the reset voltage supply circuit 198 on the reset voltage of the charge accumulation region of the pixel Px. For example, the period during which the switch 197 disconnects the reset voltage supply circuit 198 from the reset voltage line 196 may be a period during which the AD conversion circuit 140 is performing a counting operation, such as from time T4 to time T5 and from time T15 to time T16. Furthermore, for example, the period during which the switch 197 disconnects the reset voltage supply circuit 198 from the reset voltage line 196 may be a period including a portion of the period during which the reset transistor 26 is in the off state, such as from time T2 to time T8 and from time T12 to time T16.

[0162] [Modification 2] Next, a description will be given of Modification 2 of Embodiment 1. The following description will focus on the differences between Embodiment 1 and Modification 1 of Embodiment 1, and description of commonalities will be omitted or simplified.

[0163] 14 is a diagram showing an example of the configuration of a pixel array PA1 according to this modification. The imaging device according to this modification has a configuration in which the pixel array PA of the imaging device 100 or the imaging device 100A described above is replaced with a pixel array PA1.

[0164] The pixel array PA1 differs from the pixel array PA in that it further includes a plurality of reference pixels SPx in addition to a plurality of pixels Px. In the pixel array PA1, the plurality of pixels Px and a plurality of reference pixels SPx are arranged two-dimensionally. The reference pixels SPx are pixels whose output signals do not change when light is incident on the reference pixels SPx. In other words, the reference pixels SPx are non-photoresponsive pixels. On the other hand, the pixels Px can also be considered effective pixels whose output signals change when light is incident on the pixels Px (i.e., are photoresponsive). The pixel array PA1 includes an effective pixel area A1 in which a plurality of pixels Px are arranged, and a reference pixel area A2 in which a plurality of reference pixels SPx are arranged. In the example shown in FIG. 14 , the reference pixel areas A2 are arranged at both ends of the pixel array PA1 in the row direction, sandwiching the effective pixel area A1. Note that the reference pixel areas A2 may be arranged only at one end of the pixel array PA1 in the row direction. Also, in the example shown in Figure 14, the pixel array PA1 includes two columns of reference pixels SPx, but the number of columns of reference pixels SPx in the pixel array PA1 is not particularly limited and may be one column or three or more columns.

[0165] The reference pixel SPx has the same configuration as the pixel Px described above, except that, for example, signal charge is not accumulated in the node FD when light is incident on the reference pixel SPx. Furthermore, the connection between the reference pixel SPx and the peripheral circuit is also the same as, for example, the connection between the pixel Px and the peripheral circuit. Note that the voltage line 192 does not necessarily need to be connected to the reference pixel SPx.

[0166] The reference pixel SPx includes at least the same readout circuit 20 and node FD as those of the pixel Px, and outputs a signal corresponding to the potential of the node FD, which functions as at least a part of the charge storage region. In the reference pixel SPx, no signal charge is stored in the charge storage region, so the charge storage region can also be considered a dummy charge storage region.

[0167] The reference pixel SPx is, for example, an OB (Optical Black) pixel that has the same circuit configuration as the pixel Px shown in Fig. 3 but is provided with a light-shielding layer so that light does not enter the photoelectric conversion unit 10. The reference pixel SPx may also have a configuration in which the photoelectric conversion unit 10 is removed from the circuit configuration of the pixel Px shown in Fig. 3. The reference pixel SPx may also be a pixel that has the same configuration as the pixel Px shown in Fig. 3 but in which a connection between the photoelectric conversion unit 10 and the node FD is not formed.

[0168] When the imaging device according to this modification is driven, the reference pixel SPx outputs the first signal Sig1 and the second signal Sig2 to the output signal line S, similarly to the pixel Px. ｊ The reference pixel SPx outputs the first signal Sig1 and the second signal Sig2 to the output signal line S ｊ 8 or 13. The first signal Sig1 and the second signal Sig2 output by the reference pixel SPx correspond to the first signal Sig1 and the second signal Sig2 output by the pixel Px. For the sake of distinction, the first signal Sig1 output by the reference pixel SPx will be referred to as the first reference signal, and the second signal Sig2 output by the reference pixel SPx will be referred to as the second reference signal below.

[0169] The AD conversion circuit 140 generates a third reference signal, which is a digital signal corresponding to the fifth signal, based on the first and second reference signals. Similarly to generating the fifth signal, the AD conversion circuit 140 generates the third reference signal by, for example, counting the difference between the first and second reference signals. The third reference signal is an example of a reference signal.

[0170] The signal processing circuit 160 generates an eighth signal corresponding to the difference between the fifth signal and the third reference signal by subtracting the digital value of the third reference signal from the digital value of the fifth signal, and stores the generated eighth signal in the frame memory 161. The eighth signal has a digital value corresponding to the difference between the digital value of the fifth signal and the digital value of the third reference signal. The eighth signal is temporarily held in the frame memory 161. The eighth signal is used in place of the fifth signal in driving the imaging devices according to the first embodiment and the first modification of the first embodiment described above.

[0171] As described above, in this modification, the eighth signal is stored in the frame memory 161 instead of the fifth signal. In the above description, only the component corresponding to the reset noise remains in the fifth signal. However, the fifth signal may contain a component resulting from an offset voltage, such as feedthrough caused by the on / off transition of the reset transistor 26. Therefore, if the component resulting from this offset voltage in the fifth signal becomes large, the capacity of the frame memory 161 required to store the fifth signal may increase. In this modification, by storing the eighth signal, which is the difference between the fifth signal and the third reference signal, in the frame memory 161, the third reference signal cancels out the above component, thereby suppressing an increase in the capacity of the frame memory 161.

[0172] In this modification, the AD conversion circuit 140 may generate one third reference signal based on the first and second reference signals output by two or more of the plurality of reference pixels SPx. This makes it possible to average out the variations and noise in the offset components of the signals output by the reference pixels SPx, and more effectively cancel the above components from the fifth signal. For example, ｊ When two or more reference pixels SPx are output, the two or more reference pixels SPx are connected by the signal line S1, and the AD conversion circuit 140 generates one third reference signal by performing a counting operation on the difference between the first reference signal output by the two or more reference pixels SPx that have been electrically averaged and the second reference signal output by the two or more reference pixels SPx that have been electrically averaged. ｊ Wiring or a switch or the like may be provided to connect them together.

[0173] In this modification, the AD conversion circuit 140 may generate two or more third reference signals corresponding to two or more reference pixels SPx based on the first and second reference signals output by two or more reference pixels SPx among the multiple reference pixels SPx. In this case, the signal processing circuit 160 subtracts a digital value determined from the two or more third reference signals from the digital value of the fifth signal to generate an eighth signal corresponding to the difference between the fifth signal and the two or more third reference signals, and stores the generated eighth signal in the frame memory 161. This also makes it possible to level out variations and noise in the offset components of the signals output by the reference pixels SPx and more effectively cancel the above components from the fifth signal. The digital value determined from the two or more third reference signals is the arithmetic average of the digital values ​​of the two or more third reference signals. The arithmetic average of the digital values ​​of the two or more third reference signals is performed, for example, by the signal processing circuit 160, but may also be performed by another circuit.

[0174] The two or more reference pixels SPx that output the signal used to generate the third reference signal may be all of the reference pixels SPx among the plurality of reference pixels SPx, or may be some of the reference pixels SPx. When some of the plurality of reference pixels SPx are used to generate the third reference signal, the some of the reference pixels SPx may be, for example, reference pixels SPx in the same row as pixels Px that output the signal used to generate the fifth signal, the difference between which is obtained from the third reference signal.

[0175] The arrangement of the effective pixel area A1 and the reference pixel area A2 in the pixel array PA1 is not limited to the example shown in Fig. 14 and may be designed according to the purpose. Fig. 15 is a diagram showing an example of the arrangement of the effective pixel area A1 and the reference pixel area A2 according to this modification.

[0176] 15 , the reference pixel regions A2 are arranged at both ends of the pixel array PA1 in the column direction so as to sandwich the effective pixel region A1. Note that the reference pixel regions A2 may be arranged at only one end of the pixel array PA1 in the column direction. In the example shown in Fig. 15 , when some of the reference pixels SPx among the multiple reference pixels SPx are used to generate the third reference signal, the some of the reference pixels SPx are, for example, reference pixels SPx in the same column as pixels Px that output a signal used to generate a fifth signal that is a difference between the third reference signal and the reference pixel region A2.

[0177] 16 is a diagram showing another example of the arrangement of the effective pixel area A1 and the reference pixel area A2 according to this modification. In the example shown in Fig. 16, the reference pixel area A2 is arranged in a corner of the pixel array PA1.

[0178] (Embodiment 2) Next, a description will be given of embodiment 2. In embodiment 2, a camera system including an imaging device according to the present disclosure will be described.

[0179] FIG. 17 is a block diagram showing an example of the configuration of a camera system 400 according to this embodiment.

[0180] 17 , camera system 400 according to this embodiment includes lens optical system 601, imaging device 602, system controller 603, camera signal processing circuit 604, and display device 605. Camera system 400 may be, for example, a smartphone, a digital camera, a video camera, or an in-vehicle camera.

[0181] The lens optical system 601 focuses light onto an imaging surface of the imaging device 602. The lens optical system 601 may include, for example, a lens group including an autofocus lens and a zoom lens, and an aperture. The imaging device 602 may be, for example, the imaging device 100 according to the first embodiment. The imaging device 602 may also be an imaging device according to the first or second modification of the first embodiment.

[0182] The system controller 603 controls the entire camera system 400. The system controller 603 is, for example, a semiconductor integrated circuit, and a specific example is a CPU (Central Processing Unit).

[0183] The camera signal processing circuit 604 has a function of processing an output signal from the image capture device 602. The camera signal processing circuit 604 receives output data from the image capture device 602 and performs processes such as gamma correction, color interpolation, spatial interpolation, and auto white balance. The camera signal processing circuit 604 is, for example, a DSP (Digital Signal Processor). The image capture device 602 and the camera signal processing circuit 604 may be implemented as a single semiconductor device. The semiconductor device may be, for example, a so-called SoC (System on a Chip). This configuration allows for further miniaturization of electronic devices that include the image capture device 602 as a part thereof.

[0184] The display device 605 presents an image based on the output data from the imaging device 602 to the user of the camera system 400. The display device 605 is, for example, a liquid crystal display or an organic EL (Electro Luminescence) display.

[0185] While the imaging device and camera system according to the present disclosure have been described above based on the embodiments, the present disclosure is not limited to these embodiments. As long as they do not deviate from the gist of the present disclosure, various modifications conceivable by those skilled in the art to the embodiments, as well as other forms constructed by combining some of the components of the embodiments, are also included within the scope of the present disclosure.

[0186] In the above embodiment, the imaging device 100 includes the signal processing circuit 160, but this is not limiting. For example, the imaging device 100 may not include the signal processing circuit 160, and may instead output the fifth and sixth signals via the digital output interface 170. In this case, the function of the signal processing circuit 160 may be realized by the camera signal processing circuit 604.

[0187] In the above embodiment, the AD conversion circuit 140 performs a counting operation to generate the fifth signal during each of the periods when the pixel Px outputs the first signal Sig1 and the second signal Sig2, and performs a counting operation to generate the sixth signal during each of the periods when the pixel Px outputs the third signal Sig3 and the fourth signal Sig4, but this is not limiting. The AD conversion circuit 140 does not have to perform a counting operation during each of the periods when the pixel Px outputs the first signal Sig1 and the third signal Sig3.

[0188] In the above-described embodiment, the processing performed by a specific processing unit (for example, a circuit in a peripheral circuit such as the signal processing circuit 160 or the control circuit 220) may be performed by another processing unit. The order of multiple processes may be changed, or multiple processes may be performed in parallel.

[0189] In the above-described embodiments, each component may be realized by executing a software program suitable for that component, or by a program execution unit such as a CPU or processor reading and executing a software program recorded on a recording medium such as a hard disk or semiconductor memory.

[0190] Furthermore, each component may be realized by hardware. Each component may be a circuit (or integrated circuit). These circuits may form a single circuit as a whole, or each may be a separate circuit. Furthermore, each of these circuits may be a general-purpose circuit or a dedicated circuit.

[0191] Furthermore, the general or specific aspects of the present disclosure may be realized as a system, an apparatus, a method, an integrated circuit, a computer program, or a computer-readable recording medium such as a CD-ROM, or as any combination of a system, an apparatus, a method, an integrated circuit, a computer program, and a recording medium.

[0192] For example, the present disclosure may be realized as an imaging device according to the above-described embodiment, as a control device that controls an imaging device, as a program for causing a computer to execute a driving method for an imaging device performed by a processing unit such as a control circuit or a processing circuit, or as a computer-readable non-transitory recording medium on which such a program is recorded.

[0193] Furthermore, the above-described embodiments can be modified, substituted, added, omitted, and the like in various ways within the scope of the claims or their equivalents.

[0194] The imaging device etc. according to the present disclosure is useful, for example, in an image sensor, a digital camera, etc. The imaging device etc. according to the present disclosure can be used in a medical camera, a robot camera, a security camera, a camera mounted on a vehicle, etc.

[0195] 10 Photoelectric conversion unit 11 Pixel electrode 12 Photoelectric conversion layer 13 Counter electrode 20 Readout circuit 22 Signal detection transistor 22e, 24e, 26e Gate electrode 22g, 24g, 26g Gate insulating layer 24 Address transistor 26 Reset transistor 50 Insulating layer 52 Conductive structure 100, 100A, 602 Imaging device 101 Pixel substrate 102 Circuit substrate 110 Semiconductor substrate 111, 112, 113, 114, 115 Impurity region 116 Element isolation region 130 Row scanning circuit 140 AD conversion circuit 141 Reference signal generation circuit 145 Column signal processing circuit 146 Differential amplifier circuit 147 Counter 150 Digital memory 160 Signal processing circuit 161 Frame memory 170 Digital output interface 180 Current source circuit 181 Current source 190 Voltage supply circuit 192 Voltage line 194 Power supply line 196 Reset voltage line 197 Switch 198 Reset voltage supply circuit 220 Control circuit 400 Camera system 601 Lens optical system 603 System controller 604 Camera signal processing circuit 605 Display device A1 Effective pixel area A2 Reference pixel area C1, C2 Capacitance cmpout Output line FD, REFin, Sin Node M1, M2 Transistor PA, PA1 Pixel array Px Pixel Q ｉ Reset signal line R ｉ Row signal line Sig1 1st signal Sig2 2nd signal Sig3 3rd signal Sig4 4th signal S ｊ Output signal line SPx Reference pixel

Claims

1. A pixel comprising: a signal line connected to the pixel; and an AD (Analog to Digital) conversion circuit connected to the signal line, wherein the pixel includes: a photoelectric conversion unit that converts light into signal charge; a charge accumulation region that accumulates the signal charge; a first transistor having a source or a drain connected to the charge accumulation region; and a second transistor having a gate electrically connected to the charge accumulation region and outputting a signal corresponding to the potential of the charge accumulation region, wherein the pixel: outputs a first signal to the signal line corresponding to the potential of the charge accumulation region when the first transistor is in an on state; after outputting the first signal, outputs a second signal to the signal line corresponding to the potential of the charge accumulation region when the first transistor is in an off state; after outputting the second signal, outputs a third signal to the signal line corresponding to the potential of the charge accumulation region in a state where the signal charge has been accumulated; and after outputting the third signal, outputs a fourth signal to the signal line corresponding to the potential of the charge accumulation region when the first transistor is in an on state, and the AD conversion circuit an imaging device that generates a fifth signal, which is a digital signal, by performing a counting operation on a difference between the first signal and the second signal; and that generates a sixth signal, which is a digital signal, by performing a counting operation on a difference between the third signal and the fourth signal.

2. The imaging device according to claim 1, further comprising a signal processing circuit, wherein the signal processing circuit generates a seventh signal corresponding to the difference between the fifth signal and the sixth signal.

3. The imaging device according to claim 1, further comprising a signal processing circuit, wherein the signal processing circuit generates a seventh signal corresponding to the sum of the fifth signal and the sixth signal.

4. The imaging device according to claim 1, further comprising a memory for storing the fifth signal.

5. The imaging device according to claim 4, wherein the fifth signal stored in the memory has a bit width of 7 bits or less.

6. The imaging device according to claim 1, wherein the AD conversion circuit performs a counting operation during each of a period in which the pixel outputs the first signal and a period in which the pixel outputs the second signal to generate the fifth signal, and performs a counting operation during each of a period in which the pixel outputs the third signal and a period in which the pixel outputs the fourth signal to generate the sixth signal.

7. The imaging device according to claim 1, wherein the number of transistors included in the pixel is four or less.

8. The imaging device according to claim 1, wherein the period during which the first transistor is in an on state when the fourth signal is output to the signal line is longer than the period during which the first transistor is in an on state when the first signal is output to the signal line.

9. The imaging device according to claim 1, further comprising: a voltage line to which a voltage is applied from a voltage supply circuit; and a switch that switches between connection and disconnection between the voltage supply circuit and the voltage line, wherein the other of the source and drain of the first transistor is connected to the voltage line.

10. The imaging device according to claim 9, wherein the switch disconnects the voltage supply circuit from the voltage line while the first transistor is in an on state, and connects the voltage supply circuit from the voltage line while the first transistor is in an off state.

11. An imaging device as described in claim 1, further comprising one or more reference pixels whose output signals do not change when light is incident on them; and a memory, wherein the AD conversion circuit generates one or more reference signals corresponding to the fifth signal based on signals output by the one or more reference pixels as signals corresponding to the first signal and the second signal, and the memory holds an eighth signal having a digital value corresponding to the difference between the digital value of the fifth signal and a digital value determined from the one or more reference signals.

12. The imaging device according to claim 11, further comprising a plurality of reference pixels as the one or more reference pixels, and wherein the AD conversion circuit generates one reference signal as the one or more reference signals based on signals output by two or more reference pixels among the plurality of reference pixels.

13. The imaging device according to claim 11, further comprising a plurality of reference pixels as the one or more reference pixels, and wherein the AD conversion circuit generates two or more reference signals corresponding to the two or more reference pixels as the one or more reference signals based on signals output by two or more reference pixels among the plurality of reference pixels.

14. A camera system comprising an imaging device according to any one of claims 1 to 13.

Images