Plasma processing device, bias power supply system, and plasma processing method

Abstract

This plasma processing device comprises a chamber, a substrate support part, a plasma generation unit, and a bias power supply system. The substrate support part has a bias electrode. The bias power supply system is configured to intermittently apply a voltage pulse to the bias electrode to draw ions from the plasma to the substrate. The bias power supply system includes at least one DC power supply, a switching circuit, and a pulse control unit. The switching circuit is electrically connected between the bias electrode and the at least one DC power supply. The pulse control unit is configured to control the switching circuit so as to cause the voltage level of the voltage pulse to reach, in a stepwise manner, an attainment voltage level thereof having a maximum potential difference in the negative direction with respect to a reference potential.

Description

Plasma processing apparatus, bias power supply system, and plasma processing method

[0001] SUMMARY Exemplary embodiments of the present disclosure relate to a plasma processing apparatus, a bias power supply system, and a plasma processing method.

[0002] A plasma processing apparatus that processes a substrate using plasma is known. The plasma processing apparatus described in Patent Document 1 includes a substrate-holding electrode and a counter electrode disposed in a chamber, a radio-frequency generator, a DC negative pulse generator, and a controller. The radio-frequency generator applies a radio-frequency wave of 50 MHz or higher to the substrate-holding electrode. The DC negative pulse generator applies a DC negative pulse voltage to the substrate-holding electrode so as to be superimposed on the radio-frequency wave. The controller controls the radio-frequency generator to apply the radio-frequency wave intermittently, and also controls the DC negative pulse generator to apply a DC negative pulse intermittently in accordance with the on / off timing of the radio-frequency wave.

[0003] JP 2009-187975 A

[0004] The present disclosure provides a technique for suppressing a decrease in the energy of ions supplied from a plasma to a substrate during application of a voltage pulse.

[0005] In one exemplary embodiment, a plasma processing apparatus is provided. The plasma processing apparatus includes a chamber, a substrate support, a plasma generation unit, and a bias power system. The substrate support has a bias electrode. The substrate support is disposed within the chamber. The plasma generation unit is configured to generate plasma within the chamber. The bias power system is electrically coupled to the bias electrode. The bias power system is configured to apply intermittent voltage pulses to the bias electrode to attract ions from the plasma to a substrate on the substrate support. The bias power system includes at least one DC power supply, a switching circuit, and a pulse controller. The switching circuit is electrically connected between the bias electrode and the at least one DC power supply. The pulse controller is configured to control the switching circuit. The pulse controller is configured to control the switching circuit to gradually increase the voltage level of the voltage pulse to a target voltage level having a maximum potential difference in the negative direction relative to a reference potential.

[0006] According to one exemplary embodiment, a technique is provided for suppressing the decrease in energy of ions delivered from a plasma to a substrate during application of a voltage pulse.

[0007] 9A is a diagram for explaining an example of the configuration of a plasma processing system; FIG. 9B is a diagram for explaining an example of the configuration of a capacitively coupled plasma processing apparatus; FIG. 9C is a diagram for explaining an example of the configuration of a plasma processing apparatus according to an exemplary embodiment; FIG. 9D is a diagram for explaining an example of the configuration of a capacitively coupled plasma processing apparatus; FIG. 9E is a diagram for explaining an example of the configuration of a plasma processing apparatus according to an exemplary embodiment; FIG. 9F is a diagram for explaining an example of the configuration of a bias power supply system according to an exemplary embodiment; FIG. 9G is a diagram for explaining an example of the configuration of a bias power supply system according to an exemplary embodiment; FIG. 9H is a diagram for explaining an example of the configuration of a bias power supply system according to an exemplary embodiment; FIG. 9H is a diagram for explaining an example of the configuration of a bias power supply system according to an exemplary embodiment; FIG. 9H is a diagram for explaining an example of the configuration of a bias power supply system according to an exemplary embodiment; FIG. 9H is a diagram for explaining an example of the configuration of a bias power supply system according to an exemplary embodiment; 16(a) is an example timing chart related to a bias power supply system according to yet another exemplary embodiment, and FIG. 16(b) is an enlarged view of a portion S of the timing chart of FIG. 16(a). FIG. 16(b) is a schematic diagram of a bias power supply system according to yet another exemplary embodiment. FIG. 16(c) is a flow chart of a plasma processing method according to one exemplary embodiment. FIG. 16(d) is a block diagram of a processing circuit for performing the operations described herein on a computer.

[0008] Various exemplary embodiments will be described in detail below with reference to the drawings, in which the same or equivalent parts are designated by the same reference numerals.

[0009] FIG. 1 is a diagram illustrating an exemplary configuration of a plasma processing system. In one embodiment, the plasma processing system includes a plasma processing apparatus 1 and a control unit 2. The plasma processing system is an example of a substrate processing system, and the plasma processing apparatus 1 is an example of a substrate processing apparatus. The plasma processing apparatus 1 includes a chamber 10, a substrate support unit 11, and a plasma generation unit 12. The chamber 10 has an internal space (plasma processing space). The chamber 10 also has at least one gas supply port for supplying at least one processing gas to the internal space and at least one gas exhaust port for exhausting gas from the internal space. The gas supply port is connected to a gas supply unit 20 (described later), and the gas exhaust port is connected to an exhaust system 40 (described later). The substrate support unit 11 is disposed within the internal space and has a substrate support surface for supporting a substrate.

[0010] The plasma generating unit 12 is configured to generate plasma from at least one processing gas supplied into the internal space. The plasma formed in the internal space may be capacitively coupled plasma (CCP), inductively coupled plasma (ICP), electron-cyclotron-resonance plasma (ECR plasma), helicon wave plasma (HWP), or surface wave plasma (SWP). Various types of plasma generating units may be used, including alternating current (AC) plasma generating units and direct current (DC) plasma generating units. In one embodiment, the AC signal (AC power) used in the AC plasma generator has a frequency in the range of 100 kHz to 10 GHz. Therefore, AC signals include RF (Radio Frequency) signals and microwave signals. In one embodiment, the RF signal has a frequency in the range of 100 kHz to 150 MHz.

[0011] The control unit 2 processes computer-executable instructions that cause the plasma processing apparatus 1 to perform various processes described in this disclosure. The control unit 2 may be configured to control each element of the plasma processing apparatus 1 to perform various processes described herein. In one embodiment, part or all of the control unit 2 may be included in the plasma processing apparatus 1. The control unit 2 may include a processing unit 2a1, a storage unit 2a2, and a communication interface 2a3. The control unit 2 may be implemented by, for example, a computer 2a. The processing unit 2a1 may be configured to read a program from the storage unit 2a2 and execute the read program to perform various control operations. This program may be stored in the storage unit 2a2 in advance or may be acquired via a medium when needed. The acquired program is stored in the storage unit 2a2 and read from the storage unit 2a2 by the processing unit 2a1 for execution. The medium may be various storage media readable by the computer 2a or a communication line connected to the communication interface 2a3. The processing unit 2a1 may be a CPU (Central Processing Unit). The storage unit 2a2 may include a random access memory (RAM), a read-only memory (ROM), a hard disk drive (HDD), a solid state drive (SSD), or a combination thereof. The communication interface 2a3 may communicate with the plasma processing apparatus 1 via a communication line such as a local area network (LAN).

[0012] The following describes a configuration example of a capacitively coupled plasma processing apparatus as an example of the plasma processing apparatus 1. Fig. 2 is a diagram for explaining a configuration example of a capacitively coupled plasma processing apparatus.

[0013] The capacitively coupled plasma processing apparatus 1 includes a chamber 10, a gas supply unit 20, a power supply 30, and an exhaust system 40. The plasma processing apparatus 1 also includes a substrate support 11 and a gas inlet. The gas inlet is configured to introduce at least one process gas into the chamber 10. The gas inlet includes a showerhead 13. The substrate support 11 is disposed within the chamber 10. The showerhead 13 is disposed above the substrate support 11. In one embodiment, the showerhead 13 forms at least a portion of the ceiling of the chamber 10. The chamber 10 has an internal space 10s defined by the showerhead 13, a sidewall 10a of the chamber 10, and the substrate support 11. The chamber 10 is grounded. The showerhead 13 and the substrate support 11 are electrically insulated from the housing of the chamber 10.

[0014] The substrate support 11 includes a main body 111 and a ring assembly 112. The main body 111 has a substrate support surface 111a (central region) for supporting a substrate W, and a ring support surface 111b (annular region) for supporting the ring assembly 112. The ring support surface 111b of the main body 111 surrounds the substrate support surface 111a of the main body 111 in a plan view. The substrate W is placed on the substrate support surface 111a of the main body 111, and the ring assembly 112 is placed on the ring support surface 111b of the main body 111 so as to surround the substrate W on the substrate support surface 111a of the main body 111.

[0015] In one embodiment, the main body 111 includes a base 1110 and an electrostatic chuck 1111. The base 1110 includes a conductive member. The conductive member of the base 1110 can function as a bias electrode. The electrostatic chuck 1111 is disposed on the base 1110. The electrostatic chuck 1111 includes a ceramic member 1111a and an electrostatic electrode 1111b disposed within the ceramic member 1111a. The ceramic member 1111a has a substrate support surface 111a. In one embodiment, the ceramic member 1111a also has a ring support surface 111b. Note that another member surrounding the electrostatic chuck 1111, such as an annular electrostatic chuck or an annular insulating member, may have the ring support surface 111b. In this case, the ring assembly 112 may be disposed on the annular electrostatic chuck or the annular insulating member, or may be disposed on both the electrostatic chuck 1111 and the annular insulating member. Furthermore, at least one RF / DC electrode coupled to an RF power supply 31 and / or a DC power supply 32, which will be described later, may be disposed within the ceramic member 1111a. In this case, the at least one RF / DC electrode functions as a bias electrode. When a bias RF signal and / or a DC signal, which will be described later, is supplied to the at least one RF / DC electrode, the RF / DC electrode is also called a bias electrode. Note that the conductive member of the base 1110 and the at least one RF / DC electrode may function as multiple bias electrodes. Furthermore, the electrostatic electrode 1111b may function as a bias electrode. Therefore, the substrate support 11 includes at least one bias electrode.

[0016] The ring assembly 112 includes one or more annular members. In one embodiment, the one or more annular members include one or more edge rings and at least one cover ring. The edge rings are formed of a conductive or insulating material, and the cover rings are formed of an insulating material.

[0017] The substrate support 11 may also include a temperature adjustment module configured to adjust at least one of the electrostatic chuck 1111, the ring assembly 112, and the substrate to a target temperature. The temperature adjustment module may include a heater, a heat transfer medium, a flow passage 1110a, or a combination thereof. A heat transfer fluid such as brine or a gas flows through the flow passage 1110a. In one embodiment, the flow passage 1110a is formed in the base 1110, and one or more heaters are disposed in the ceramic member 1111a of the electrostatic chuck 1111. The substrate support 11 may also include a heat transfer gas supply unit configured to supply a heat transfer gas to a gap between the backside of the substrate W and the substrate support surface 111a.

[0018] The showerhead 13 is configured to introduce at least one process gas from the gas supply unit 20 into the internal space 10s. The showerhead 13 has at least one gas supply port 13a, at least one gas diffusion chamber 13b, and multiple gas inlets 13c. The process gas supplied to the gas supply port 13a passes through the gas diffusion chamber 13b and is introduced into the internal space 10s from the multiple gas inlets 13c. The showerhead 13 also includes at least one upper electrode. In addition to the showerhead 13, the gas inlet may include one or more side gas injectors (SGIs) attached to one or more openings formed in the sidewall 10a.

[0019] The gas supply unit 20 may include at least one gas source 21 and at least one flow controller 22. In one embodiment, the gas supply unit 20 is configured to supply at least one process gas from a corresponding gas source 21 to the showerhead 13 via a corresponding flow controller 22. Each flow controller 22 may include, for example, a mass flow controller or a pressure-controlled flow controller. Additionally, the gas supply unit 20 may include at least one flow modulation device that modulates or pulses the flow rate of the at least one process gas.

[0020] The power supply 30 includes an RF power supply 31 coupled to the chamber 10 via at least one impedance matching circuit. The RF power supply 31 is configured to supply at least one RF signal (RF power) to at least one bias electrode and / or at least one upper electrode. This causes plasma to be formed from at least one process gas supplied to the internal space 10s. Therefore, the RF power supply 31 can function as at least a part of the plasma generating unit 12. Furthermore, by supplying a bias RF signal to the at least one bias electrode, a bias potential is generated on the substrate W, and ion components in the formed plasma can be attracted to the substrate W.

[0021] In one embodiment, the RF power supply 31 includes a first RF generating unit 31a and a second RF generating unit 31b. The first RF generating unit 31a is coupled to at least one bias electrode and / or at least one upper electrode via at least one impedance matching circuit and is configured to generate a source RF signal (source RF power) for plasma generation. In one embodiment, the source RF signal has a frequency in the range of 10 MHz to 150 MHz. In one embodiment, the first RF generating unit 31a may be configured to generate multiple source RF signals having different frequencies. The generated one or more source RF signals are supplied to at least one bias electrode and / or at least one upper electrode.

[0022] The second RF generator 31b is coupled to at least one bias electrode via at least one impedance matching circuit and is configured to generate a bias RF signal (bias RF power). The frequency of the bias RF signal may be the same as or different from the frequency of the source RF signal. In one embodiment, the bias RF signal has a frequency lower than the frequency of the source RF signal. In one embodiment, the bias RF signal has a frequency in the range of 100 kHz to 60 MHz. In one embodiment, the second RF generator 31b may be configured to generate multiple bias RF signals having different frequencies. The generated one or more bias RF signals are supplied to at least one bias electrode. In various embodiments, at least one of the source RF signal and the bias RF signal may be pulsed.

[0023] The power supply 30 may also include a DC power supply 32 coupled to the chamber 10. The DC power supply 32 includes a first DC generator 32a and a second DC generator 32b. In one embodiment, the first DC generator 32a is connected to at least one bias electrode and configured to generate a first DC signal. The generated first DC signal is applied to the at least one bias electrode. In one embodiment, the second DC generator 32b is connected to at least one upper electrode and configured to generate a second DC signal. The generated second DC signal is applied to the at least one upper electrode.

[0024] In various embodiments, the first and second DC signals may be pulsed. In this case, a sequence of voltage pulses is applied to at least one bias electrode and / or at least one upper electrode. The voltage pulses may have a rectangular, trapezoidal, triangular, or combination thereof pulse waveform. In one embodiment, a waveform generator for generating the sequence of voltage pulses from the DC signal is connected between the first DC generator 32a and at least one bias electrode. Thus, the first DC generator 32a and the waveform generator constitute a voltage pulse generator. When the second DC generator 32b and the waveform generator constitute a voltage pulse generator, the voltage pulse generator is connected to at least one upper electrode. The voltage pulses may have either positive or negative polarity. Furthermore, the sequence of voltage pulses may include one or more positive voltage pulses and one or more negative voltage pulses within one period. The first DC generating unit 32a and the second DC generating unit 32b may be provided in addition to the RF power supply 31, or the first DC generating unit 32a may be provided instead of the second RF generating unit 31b.

[0025] The exhaust system 40 may be connected to, for example, a gas exhaust port 10e provided at the bottom of the chamber 10. The exhaust system 40 may include a pressure regulating valve and a vacuum pump. The pressure in the internal space 10s is regulated by the pressure regulating valve. The vacuum pump may include a turbomolecular pump, a dry pump, or a combination thereof.

[0026] Reference will now be made to Fig. 3, which is a schematic diagram of a plasma processing apparatus according to an exemplary embodiment. The substrate support 11, the power supply, and the configuration related to the power supply shown in Fig. 3 can be employed in the plasma processing apparatus 1.

[0027] The plasma processing apparatus 1 includes a substrate support 11. The substrate support 11 is disposed in a chamber 10. The substrate support 11 may include a base 1110 and an electrostatic chuck 1111. The base 1110 may function as a bias electrode BE.

[0028] The substrate support 11 may include a first region R1 and a second region R2. In FIG. 3 , the boundary between the first region R1 and the second region R2 is indicated by a dashed line. The first region R1 is a region that intersects with the axis AX and has a substantially disk shape. The axis AX is the central axis of the substrate support 11 and may coincide with the central axis of the chamber 10. The first region R1 includes the above-mentioned substrate support surface 111a as its upper surface. The second region R2 extends to surround the first region R1.

[0029] The substrate W is placed on the substrate support surface 111a and is supported on the first region R1. The second region R2 is an annular region around the axis AX. The second region R2 may include the above-mentioned ring support surface 111b as its upper surface. The edge ring ER included in the ring assembly 112 is placed on the ring support surface 111b and is supported on the second region R2. The substrate W is disposed within the region surrounded by the edge ring ER.

[0030] 3, the electrostatic chuck 1111 may include a dielectric portion 1111d. The dielectric portion 1111d may be the ceramic member 1111a described above. A central portion of the dielectric portion 1111d may form a first region R1 and may have the substrate support surface 111a as its upper surface. A peripheral portion of the dielectric portion 1111d may form a second region R2 and may have the ring support surface 111b as its upper surface.

[0031] The electrostatic chuck 1111 may include a chuck electrode CE1 as part of the electrostatic electrode 1111b. The chuck electrode CE1 is disposed within the dielectric portion 1111d and within the first region R1. The chuck electrode CE1 may be a film formed from a conductive material. The chuck electrode CE1 may have a substantially circular planar shape. The chuck electrode CE1 may be disposed such that its center is located on the axis AX. The chuck electrode CE1 may extend between the substrate support surface 111a and the first bias electrode BE1.

[0032] The electrostatic chuck 1111 may also include chuck electrodes CE2 and CE3 as separate parts of the electrostatic electrode 1111b. Each of the chuck electrodes CE2 and CE3 is disposed within the dielectric portion 1111d and the second region R2. Each of the chuck electrodes CE2 and CE3 may be a film formed of a conductive material. Each of the chuck electrodes CE2 and CE3 may extend circumferentially around the axis AX or have a substantially annular planar shape. The chuck electrode CE2 is disposed inward relative to the chuck electrode CE3. That is, the radial distance between the chuck electrode CE2 and the axis AX is smaller than the radial distance between the chuck electrode CE3 and the axis AX.

[0033] As described above, the plasma processing apparatus 1 further includes the first RF generating unit 31 a. The first RF generating unit 31 a may be electrically connected to the bias electrode BE via a matching unit 31 am and an electrical path 30 p.

[0034] The plasma processing apparatus 1 may further include a DC power supply 41p. The DC power supply 41p is electrically connected to the chuck electrode CE1 via a switch 41s. A filter 41f may further be connected between the DC power supply 41p and the chuck electrode CE1. The filter 41f is a low-pass filter configured to block or attenuate RF signals such as source RF signals. When a voltage from the DC power supply 41p is applied to the chuck electrode CE1, an electrostatic attraction force is generated between the electrostatic chuck 1111 and the substrate W. The generated electrostatic attraction force attracts the substrate W to the first region R1 and holds the substrate W in the first region R1.

[0035] The plasma processing apparatus 1 may further include DC power supplies 42p and 43p. The DC power supply 42p is electrically connected to the chuck electrode CE2 via a switch 42s. A filter 42f may further be connected between the DC power supply 42p and the chuck electrode CE2. The filter 42f is a low-pass filter configured to block or attenuate RF signals such as source RF signals.

[0036] The DC power supply 43p is electrically connected to the chuck electrode CE3 via a switch 43s. A filter 43f may be further connected between the DC power supply 43p and the chuck electrode CE3. The filter 43f is a low-pass filter configured to block or attenuate RF signals such as source RF signals.

[0037] When voltages from the DC power supplies 42p and 43p are applied to the chuck electrodes CE2 and CE3, an electrostatic attractive force is generated between the electrostatic chuck 1111 and the edge ring ER. The generated electrostatic attractive force attracts the edge ring ER to the second region R2 and holds it there. Note that a voltage may be applied to the chuck electrodes CE2 and CE3 so as to generate a potential difference therebetween. In other words, the second region R2 may constitute a bipolar electrostatic chuck.

[0038] The plasma processing apparatus 1 includes a bias power supply system 50. The bias power supply system 50 is electrically coupled to the bias electrode BE via a filter 301f and an electrical path 30p. The filter 301f is a low-pass filter configured to block or attenuate RF signals such as source RF signals. In FIG. 3, the base 1110 constitutes the bias electrode BE, but the location of the bias electrode BE on the substrate support 11 is not limited. The bias electrode BE may be at least one conductive member of the base 1110. The bias electrode BE may be, for example, at least one electrode in the electrostatic chuck 1111.

[0039] 4 is a schematic diagram of a bias power supply system 50 according to one exemplary embodiment. The bias power supply system 50 is configured to intermittently apply a voltage pulse VP (see FIG. 5) to the bias electrode BE to attract ions from the plasma to the substrate W on the substrate support 11. The voltage pulse VP may be applied to the bias electrode BE periodically. That is, the voltage pulse VP may be applied periodically at a time interval equal to the time length of its waveform period. The bias frequency, which is the reciprocal of the time length of the waveform period of the voltage pulse VP, is lower than the frequency of the source RF signal and may be a frequency in the range of 100 kHz to 50 MHz. The bias frequency is, for example, 400 kHz.

[0040] 4, the bias power supply system 50 includes at least one DC power supply 51, a switching circuit 53, and a pulse control unit 54. The switching circuit 53 is electrically connected between the bias electrode BE and the at least one DC power supply 51. The pulse control unit 54 is configured to control the switching circuit 53. The pulse control unit 54 controls the switching circuit 53 so that the voltage level of the voltage pulse VP gradually reaches its target voltage level having a maximum potential difference in the negative direction with respect to a reference potential. The reference potential is, for example, a ground potential.

[0041] In one embodiment, the bias power supply system 50 may include, as shown in FIG. 4 , at least one DC power supply 51, a first DC power supply 511 and a second DC power supply 512. The first DC power supply 511 is capable of outputting an output voltage having a potential difference with respect to a reference potential that is smaller than the above-mentioned final voltage level. The second DC power supply 512 is capable of outputting an output voltage having a final voltage level. Each of the first DC power supply 511 and the second DC power supply 512 may be a variable DC power supply. The positive terminal of the first DC power supply 511 is connected to ground. The positive terminal of the second DC power supply 512 is connected to ground.

[0042] In one embodiment, the switching circuit 53 may include a first switching element SW1, a second switching element SW2, and a switching element SWG.

[0043] The first switching element SW1 is electrically connected between the negative pole of the first DC power supply 511 and the bias electrode BE. The first switching element SW1 is electrically connected to the bias electrode BE via an electrical path 53p. When the first switching element SW1 is closed, the first DC power supply 511 and the bias electrode BE are in a conductive state, and when the first switching element SW1 is open, the first DC power supply 511 and the bias electrode BE are in a non-conductive state.

[0044] The second switching element SW2 is electrically connected between the negative pole of the second DC power supply 512 and the bias electrode BE. The second switching element SW2 is electrically connected to the bias electrode BE via an electrical path 53p. When the second switching element SW2 is closed, the second DC power supply 512 and the bias electrode BE are in a conductive state, and when the second switching element SW2 is open, the second DC power supply 512 and the bias electrode BE are in a non-conductive state.

[0045] The switching element SWG is electrically connected between the ground and the bias electrode BE. The switching element SWG is electrically connected to the bias electrode BE via an electrical path 53p. When the switching element SWG is closed, the ground and the bias electrode BE are in a conductive state, and when the switching element SWG is open, the ground and the bias electrode BE are in a non-conductive state.

[0046] The pulse control unit 54 is electrically connected to the first switching element SW1, the second switching element SW2, and the switching element SWG of the switching circuit 53. The pulse control unit 54 can switch the first switching element SW1, the second switching element SW2, and the switching element SWG between open and closed states by providing pulse control signals to these elements. The pulse control unit 54 may be configured from a processing circuit, which will be described later.

[0047] The pulse control unit 54 is configured to control the switching circuit 53 so that, when a voltage pulse VP is applied to the bias electrode BE, the first switching element SW1 is set to a closed state and the second switching element SW2 is set to an open state, and then the second switching element SW2 is set to a closed state and the first switching element SW1 is set to an open state.

[0048] An example of the operation of the pulse control unit 54 will now be described. Fig. 5 is a timing chart of an example related to a bias power supply system according to an exemplary embodiment. In Fig. 5, the horizontal axis represents time. In Fig. 5, the vertical axis represents the states of the first switching element SW1, the second switching element SW2, and the switching element SWG, as well as the voltage level of the voltage pulse VP. In Fig. 5, the reference potential of the voltage level of the voltage pulse VP is the ground potential.

[0049] The first switching element SW1, the second switching element SW2, and the switching element SWG are each in a closed state during a period corresponding to "On" shown in Fig. 5. The first switching element SW1, the second switching element SW2, and the switching element SWG are each in an open state during a period corresponding to "Off" shown in Fig. 5.

[0050] 5, the pulse control unit 54 may be configured to periodically apply a voltage pulse VP to the bias electrode BE. The waveform cycle of the voltage pulse VP includes a first period T1 and a second period T2. During the first period T1, the pulse control unit 54 controls the switching circuit 53 to gradually change the voltage level of the voltage pulse VP to a target voltage level having a maximum potential difference in the negative direction relative to a reference potential. During the second period T2, the level of the output voltage of the bias power supply system 50 is set to a reference potential level (e.g., ground potential).

[0051] In one embodiment, the first period T1 includes a period T11 and a period T12. The period T12 follows the period T11. During the period T11, the pulse control unit 54 sets the first switching element SW1 to a closed state and the second switching element SW2 to an open state. Also, during the period T11, the pulse control unit 54 sets the switching element SWG to an open state. During the period T11, the bias electrode BE is connected to the negative electrode of the first DC power supply 511, and the output voltage of the first DC power supply 511 is applied to the bias electrode BE. As a result, during the period T11, the voltage level of the voltage pulse VP reaches a first voltage level V1, which is the voltage level of the output voltage of the first DC power supply 511.

[0052] Next, during period T12, the pulse control unit 54 sets the second switching element SW2 to a closed state and sets the first switching element SW1 to an open state. During period T12, the pulse control unit 54 sets the switching element SWG to an open state. During period T12, the bias electrode BE is connected to the negative electrode of the second DC power supply 512, and the output voltage of the second DC power supply 512 is applied to the bias electrode BE. As a result, during period T12, the voltage level of the voltage pulse VP reaches the second voltage level V2, which is the voltage level of the output voltage of the second DC power supply 512, i.e., the aforementioned final voltage level.

[0053] Therefore, in the first period T1, the voltage level of the voltage pulse VP reaches the above-mentioned final voltage level in two stages.

[0054] Next, the pulse control unit 54 sets the first switching element SW1 and the second switching element SW2 to the open state in the second period T2. The pulse control unit 54 may also set the switching element SWG to the closed state in the second period T2.

[0055] In the plasma processing apparatus 1 described above, the voltage level of the voltage pulse VP reaches the final voltage level in stages. Therefore, even if the substrate W is charged by ions from the plasma during application of the voltage pulse VP to the bias electrode BE, a decrease in the potential difference between the potential of the substrate W and the plasma is suppressed. Therefore, according to the plasma processing apparatus 1, even if the substrate W is charged during application of the voltage pulse VP to the bias electrode BE, a decrease in the energy of ions supplied from the plasma to the substrate W is suppressed.

[0056] Reference will now be made to FIG. 6 . FIG. 6 is a diagram schematically illustrating a bias power supply system according to another exemplary embodiment. A bias power supply system 50A illustrated in FIG. 6 can be employed in the plasma processing apparatus 1 in place of the bias power supply system 50. In the bias power supply system 50A, the positive electrode of the second DC power supply 512 is floating from the ground and connected to the negative electrode of the first DC power supply 511. Other configurations of the bias power supply system 50A are similar to the corresponding configurations of the bias power supply system 50. Furthermore, the control of the switching circuit 53 by the pulse control unit 54 in the bias power supply system 50A is similar to the control of the switching circuit 53 by the pulse control unit 54 in the bias power supply system 50.

[0057] In the bias power supply system 50A, the voltage level of the output voltage from the second DC power supply 512 is the sum of the voltage level of the output voltage of the first DC power supply 511 and the potential difference between the positive and negative terminals of the second DC power supply 512. Therefore, it is possible to use a DC power supply having a relatively small maximum output voltage level as the second DC power supply 512.

[0058] Reference will now be made to FIG. 7 . FIG. 7 is a schematic diagram illustrating a bias power supply system according to yet another exemplary embodiment. The bias power supply system 50B illustrated in FIG. 7 can be employed in the plasma processing apparatus 1 in place of the bias power supply system 50. In the bias power supply system 50B, the first DC power supply 511 is composed of a plurality of DC power supplies connected in series. Furthermore, in the bias power supply system 50B, the second DC power supply 512 is composed of the plurality of DC power supplies of the first DC power supply 511 and a plurality of DC power supplies connected in series with the first DC power supply 511. Other configurations of the bias power supply system 50B are similar to the corresponding configurations of the bias power supply system 50A. Furthermore, the control of the switching circuit 53 by the pulse control unit 54 in the bias power supply system 50B is similar to the control of the switching circuit 53 by the pulse control unit 54 in the bias power supply system 50.

[0059] Reference will now be made to Fig. 8, which is a diagram schematically illustrating a bias power supply system according to yet another exemplary embodiment. A bias power supply system 50C illustrated in Fig. 8 can be employed in the plasma processing apparatus 1 in place of the bias power supply system 50. The bias power supply system 50C will be described below from the perspective of differences from the bias power supply system 50.

[0060] The bias power supply system 50C includes a DC power supply 51C, a switching circuit 53C, and a pulse control unit 54C. The DC power supply 51C may be the only DC power supply in the bias power supply system 50C. The DC power supply 51C is capable of outputting an output voltage having an ultimate voltage level of the voltage pulse VP (see FIG. 9(a)). The DC power supply 51C may be a variable DC power supply. The positive terminal of the DC power supply 51C may be connected to ground. The negative terminal of the DC power supply 51C is connected to the switching circuit 53C.

[0061] The switching circuit 53C includes a switching element SWC and a switching element SWG.

[0062] The switching element SWC is electrically connected between the negative electrode of the DC power supply 51C and the bias electrode BE. When the switching element SWC is closed, the DC power supply 51C and the bias electrode BE are in a conductive state, and when the switching element SWC is open, the DC power supply 51C and the bias electrode BE are in a non-conductive state.

[0063] The switching element SWG is electrically connected between the ground and the bias electrode BE. When the switching element SWG is closed, the ground and the bias electrode BE are in a conductive state, and when the switching element SWG is open, the ground and the bias electrode BE are in a non-conductive state.

[0064] The pulse control unit 54C is configured to control the switching circuit 53C so that the voltage level of the voltage pulse VP gradually reaches the target voltage level having the maximum potential difference in the negative direction with respect to the reference potential. The pulse control unit 54C is configured to control the switching circuit 53C so that the switching element SWC is alternately opened and closed repeatedly when the voltage pulse VP is applied to the bias electrode BE.

[0065] An example of the operation of the pulse control unit 54C will be described below. (a) of Fig. 9 is a timing chart of an example related to a bias power supply system according to yet another exemplary embodiment. (b) of Fig. 9 is an enlarged view of a portion S of the timing chart of (a) of Fig. 9. In (a) and (b) of Fig. 9, the horizontal axis represents time. In (a) of Fig. 9, the vertical axis represents the states of the switching elements SWC and SWG and the voltage level of the voltage pulse VP. In Fig. 9, the reference potential of the voltage level of the voltage pulse VP is the ground potential.

[0066] 9(a) and 9(b), the pulse control unit 54C may be configured to periodically apply a voltage pulse VP to the bias electrode BE. The waveform cycle of the voltage pulse VP includes a first period T1C and a second period T2C. The second period T2C follows the first period T1C. During the first period T1C, the pulse control unit 54C controls the switching circuit 53C to gradually change the voltage level of the voltage pulse VP to the aforementioned target voltage level. During the second period T2C, the output voltage level of the bias power supply system 50C is set to a reference potential level (e.g., ground potential).

[0067] In the first period T1C, the pulse control unit 54C sets the switching element SWG to an open state. In the illustrated example, the first period T1C includes periods T11a to T14b. The duration of each of the periods T11a to T14b may be determined in advance.

[0068] Period T11a is the first subperiod within the first period T1C. During period T11a, the pulse control unit 54C sets the switching element SWC to a closed state. During period T11a, the voltage level of the voltage pulse VP reaches the first voltage level VC1. During the following period T11b, the pulse control unit 54C sets the switching element SWC to an open state. During period T11b, the bias electrode BE is floating from ground.

[0069] In the following period T12a, the pulse control unit 54C sets the switching element SWC to a closed state. In the period T12a, the voltage level of the voltage pulse VP reaches a second voltage level VC2. The difference between the second voltage level VC2 and the reference potential is equal to or greater than the difference between the first voltage level VC1 and the reference potential. In the following period T12b, the pulse control unit 54C sets the switching element SWC to an open state. In the period T12b, the bias electrode BE is floating from ground.

[0070] In the following period T13a, the pulse control unit 54C sets the switching element SWC to a closed state. In period T13a, the voltage level of the voltage pulse VP reaches a third voltage level VC3. The difference between the third voltage level VC3 and the reference potential is equal to or greater than the difference between the second voltage level VC2 and the reference potential. In period T13b, the pulse control unit 54C sets the switching element SWC to an open state. In period T13b, the bias electrode BE is floating from ground.

[0071] During the following period T14a, the pulse control unit 54C sets the switching element SWC to a closed state. During period T14a, the voltage level of the voltage pulse VP reaches a fourth voltage level VC4. The difference between the fourth voltage level VC4 and the reference potential is equal to or greater than the difference between the third voltage level VC3 and the reference potential. In the example shown in FIG. 9A, the fourth voltage level VC4 is the voltage level reached by the voltage pulse VP, which has the largest potential difference in the negative direction relative to the reference potential. During the following period T14b, the pulse control unit 54C sets the switching element SWC to an open state. During period T14b, the bias electrode BE is floating above ground.

[0072] 9A, in the first period T1C, the voltage level of the voltage pulse VP reaches the above-mentioned final voltage level in four stages. Note that the number of stages required for the voltage pulse VP to reach the final voltage level in the first period T1C is not limited to four.

[0073] In a second period T2C following the first period T1C, the pulse control unit 54C sets the switching element SWC to an open state. In the second period T2C, the pulse control unit 54C may set the switching element SWG to a closed state.

[0074] According to the bias power supply system 50C, a single DC power supply 51C can be used, reducing the number of switching elements in the switching circuit 53. Therefore, the bias power supply system 50C has a simpler structure.

[0075] Reference will now be made to Fig. 10. Fig. 10 is a diagram schematically illustrating a plasma processing apparatus 101 according to another exemplary embodiment. The plasma processing apparatus 101 shown in Fig. 10 will be described below from the perspective of differences from the plasma processing apparatus 1.

[0076] As shown in FIG. 10 , the substrate support portion 11 of the plasma processing apparatus 101 further includes a first bias electrode BE1 and a second bias electrode BE2. The first bias electrode BE1 extends below the substrate support surface 111a and is disposed within a first region R1. The first bias electrode BE1 is electrically coupled to the substrate W on the substrate support surface 111a. In the example shown in FIG. 10 , the first bias electrode BE1 is disposed within the dielectric portion 1111d and the first region R1. The first bias electrode BE1 may be a film formed of a conductive material. The first bias electrode BE1 may have a substantially circular planar shape. The first bias electrode BE1 may be disposed so that its center is located on the axis AX. The chuck electrode CE1 described above may extend between the substrate support surface 111a and the first bias electrode BE1. The chuck electrode CE1 may also be used as the first bias electrode BE1.

[0077] The second bias electrode BE2 is an electrode separate from the first bias electrode BE1. The second bias electrode BE2 extends below the ring support surface 111b and is disposed within the second region R2. The second bias electrode BE2 is electrically coupled to the edge ring ER. The edge ring ER is placed on the ring support surface 111b to surround the substrate W. In the example shown in FIG. 10 , the second bias electrode BE2 is disposed within the dielectric portion 1111d and the second region R2. The second bias electrode BE2 may be a film formed of a conductive material. The second bias electrode BE2 may have a substantially annular planar shape. The second bias electrode BE2 may be disposed such that its center is located on the axis AX. Each of the above-mentioned chuck electrodes CE2 and CE3 may extend between the ring support surface 111b and the second bias electrode BE2. The chuck electrodes CE2 and CE3 may be used as the second bias electrode BE2.

[0078] The plasma processing apparatus 101 includes a bias power supply system 50D. The bias power supply system 50D is electrically coupled to the first bias electrode BE1 via an electrical path 301p. The bias power supply system 50D is electrically coupled to the second bias electrode BE2 via an electrical path 302p.

[0079] The bias power supply system 50D intermittently or periodically applies a first voltage pulse VP1 to the first bias electrode BE1 and a second voltage pulse VP2 to the second bias electrode BE2.

[0080] 11 is a schematic diagram of a bias power supply system according to yet another exemplary embodiment. As shown in FIG. 11, a bias power supply system 50D includes a first DC power supply 511D, a second DC power supply 512D, a third DC power supply 513D, a fourth DC power supply 514D, a first switching circuit 531D, and a second switching circuit 532D. The first switching circuit 531D and the second switching circuit 532D may be configured as a single switching circuit.

[0081] The first DC power supply 511D can output an output voltage having a potential difference with respect to a reference potential that is smaller than a first final voltage level. The first final voltage level is the voltage level that the first voltage pulse VP1 finally reaches. The second DC power supply 512D can output an output voltage having a first final voltage level. The third DC power supply 513D can output an output voltage having a potential difference with respect to the reference potential that is smaller than a second final voltage level. The second final voltage level is the voltage level that the second voltage pulse VP2 finally reaches. The fourth DC power supply 514D can output an output voltage having a second final voltage level. The first DC power supply 511D, the second DC power supply 512D, the third DC power supply 513D, and the fourth DC power supply 514D can be variable DC power supplies. The positive electrodes of the first DC power supply 511D, the second DC power supply 512D, the third DC power supply 513D, and the fourth DC power supply 514D are connected to the ground.

[0082] The first switching circuit 531D is electrically connected between each of the first DC power supply 511D and the second DC power supply 512D and the first bias electrode BE1. A filter 301f (see FIG. 10 ) may be connected between the first switching circuit 531D and the first bias electrode BE1. The filter 301f is configured to block or attenuate high-frequency signals such as a source RF signal. The first switching circuit 531D may include a first switching element SW1, a second switching element SW2, and a switching element SWG1.

[0083] The first switching element SW1 is electrically connected between the negative electrode of the first DC power supply 511D and the first bias electrode BE1. The second switching element SW2 is electrically connected between the negative electrode of the second DC power supply 512D and the first bias electrode BE1. The switching element SWG1 is electrically connected between the ground and the first bias electrode BE1.

[0084] The second switching circuit 532D is electrically connected between each of the third DC power supply 513D and the fourth DC power supply 514D and the second bias electrode BE2. A filter 302f (see FIG. 10 ) may be connected between the second switching circuit 532D and the second bias electrode BE2. The filter 302f is configured to block or attenuate high-frequency signals such as a source RF signal. The second switching circuit 532D may include a third switching element SW3, a fourth switching element SW4, and a switching element SWG2.

[0085] The third switching element SW3 is electrically connected between the negative electrode of the third DC power supply 513D and the second bias electrode BE2. The fourth switching element SW4 is electrically connected between the negative electrode of the fourth DC power supply 514D and the second bias electrode BE2. The switching element SWG2 is electrically connected between ground and the second bias electrode BE2.

[0086] The pulse control unit 54D is electrically connected to the first switching element SW1, the second switching element SW2, the third switching element SW3, the fourth switching element SW4, the switching element SWG1, and the switching element SWG2. The pulse control unit 54D provides pulse control signals to the first switching element SW1, the second switching element SW2, the third switching element SW3, the fourth switching element SW4, the switching element SWG1, and the switching element SWG2. This enables the pulse control unit 54D to switch between open and closed states of these switching elements.

[0087] The pulse control unit 54D is configured to control the first switching circuit 531D so that the voltage level of the first voltage pulse VP1 applied to the first bias electrode BE1 gradually reaches its first target voltage level having a maximum potential difference in the negative direction relative to the reference potential.

[0088] The pulse control unit 54D is configured to control the second switching circuit 532D so that the voltage level of the second voltage pulse VP2 applied to the second bias electrode BE2 gradually reaches its second target voltage level having a maximum potential difference in the negative direction relative to the reference potential.

[0089] The pulse control unit 54D is configured to control the first switching circuit 531D so that, when the first voltage pulse VP1 is applied, the first switching element SW1 is set to a closed state and the second switching element SW2 is set to an open state, and then the second switching element SW2 is set to a closed state and the first switching element SW1 is set to an open state.

[0090] The pulse control unit 54D is configured to control the second switching circuit 532D so that, when the second voltage pulse VP2 is applied, the third switching element SW3 is set to a closed state and the fourth switching element SW4 is set to an open state, and then the fourth switching element SW4 is set to a closed state and the third switching element SW3 is set to an open state.

[0091] An example of the operation of the pulse control unit 54D will be described below. Fig. 12 is a timing chart of an example related to a bias power supply system according to yet another exemplary embodiment. In Fig. 12, the horizontal axis represents time. In Fig. 12, the vertical axis represents the states of the first switching element SW1, the second switching element SW2, the third switching element SW3, the fourth switching element SW4, the switching element SWG1, and the switching element SWG2, as well as the voltage levels of the first and second voltage pulses. In Fig. 12, the reference potential of each of the first and second voltage pulses is ground potential.

[0092] Each of the first switching element SW1, the second switching element SW2, the third switching element SW3, the fourth switching element SW4, the switching element SWG1, and the switching element SWG2 is in a closed state during a period corresponding to "On" shown in Fig. 12. Each of the first switching element SW1, the second switching element SW2, the third switching element SW3, the fourth switching element SW4, the switching element SWG1, and the switching element SWG2 is in an open state during a period corresponding to "Off" shown in Fig. 12.

[0093] As shown in FIG. 12 , the pulse control unit 54D may be configured to periodically generate first and second voltage pulses. The common waveform cycle of the first voltage pulse VP1 and the second voltage pulse VP2 includes a first period T1 and a second period T2. During the first period T1, the pulse control unit 54D controls the first switching circuit 531D to gradually change the voltage level of the first voltage pulse VP1 to a first target voltage level having a maximum potential difference in the negative direction relative to the reference potential. Also, during the first period T1, the pulse control unit 54D controls the second switching circuit 532D to gradually change the voltage level of the second voltage pulse VP2 to a second target voltage level having a maximum potential difference in the negative direction relative to the reference potential. During the second period T2 following the first period T1, the output voltage level of the bias power supply system 50D is set to a reference potential level (e.g., ground potential).

[0094] The first period T1 includes a period T11 and a period T12. The period T12 follows the period T11. During the period T11, the pulse control unit 54D sets the first switching element SW1 to a closed state and sets the second switching element SW2 to an open state. During the period T11, the pulse control unit 54D sets the switching element SWG1 to an open state. During the period T11, the voltage level of the first voltage pulse VP1 reaches the first voltage level VD1, which is the voltage level of the output voltage of the first DC power supply 511D.

[0095] During a period T11, the pulse control unit 54D closes the third switching element SW3 and opens the fourth switching element SW4. During the period T11, the pulse control unit 54D opens the switching element SWG2. During the period T11, the voltage level of the second voltage pulse VP2 reaches the third voltage level VD3, which is the voltage level of the output voltage of the third DC power supply 513D.

[0096] Next, during a period T12, the pulse control unit 54D closes the second switching element SW2 and opens the first switching element SW1. During the period T12, the pulse control unit 54D opens the switching element SWG1. During the period T12, the voltage level of the first voltage pulse VP1 reaches the second voltage level VD2, which is the voltage level of the output voltage of the second DC power supply 512D, i.e., the first final voltage level described above.

[0097] During period T12, the pulse control unit 54D closes the fourth switching element SW4 and opens the third switching element SW3. During period T12, the pulse control unit 54D opens the switching element SWG2. During period T12, the voltage level of the second voltage pulse VP2 reaches the fourth voltage level VD4, which is the voltage level of the output voltage of the fourth DC power supply 514D, i.e., the second ultimate voltage level described above.

[0098] Therefore, as shown in FIG. 12, in the first period T1, the voltage levels of the first voltage pulse VP1 and the second voltage pulse VP2 each reach their target voltage level in two stages.

[0099] Next, in the second period T2, the pulse control unit 54D sets the first switching element SW1, the second switching element SW2, the third switching element SW3, and the fourth switching element SW4 to the open state. The pulse control unit 54D may also set the switching element SWG1 and the switching element SWG2 to the closed state in the second period T2.

[0100] According to the plasma processing apparatus 101, it is possible to apply voltage pulses synchronized with each other to both the substrate W and the edge ring ER. Furthermore, it is possible to increase the potential difference between the reference potential and the ultimate voltage level of the second voltage pulse VP2 in accordance with the amount of wear of the edge ring ER. This allows the sheath thickness on the edge ring ER to be adjusted relative to the sheath thickness on the substrate W, thereby correcting the direction of travel of ions supplied from the plasma to the edge of the substrate W to the vertical direction. This also makes it possible to extend the replacement life of the edge ring ER.

[0101] 13 is a diagram schematically illustrating a bias power supply system according to yet another exemplary embodiment. The bias power supply system 50E illustrated in FIG. 13 can be employed in the plasma processing apparatus 101 in place of the bias power supply system 50D.

[0102] In the bias power supply system 50E, the positive electrode of the second DC power supply 512D is floating from ground and electrically connected to the negative electrode of the first DC power supply 511D. The positive electrode of the fourth DC power supply 514D is floating from ground and electrically connected to the negative electrode of the third DC power supply 513D. The positive electrode of the third DC power supply 513D may be floating from ground or may be electrically connected to the negative electrode of the first DC power supply 511D. Alternatively, the positive electrode of the third DC power supply 513D may be connected to ground. Other configurations of the bias power supply system 50E are similar to the corresponding configurations of the bias power supply system 50D. Furthermore, the control of the first switching circuit 531D and the second switching circuit 532D by the pulse control unit 54D in the bias power supply system 50E is similar to the control of the first switching circuit 531D and the second switching circuit 532D by the pulse control unit 54D in the bias power supply system 50D.

[0103] According to the bias power supply system 50E, it is possible to use DC power supplies having a relatively small maximum output voltage level as each of the second DC power supply 512D and the fourth DC power supply 514D. Furthermore, when the positive electrode of the third DC power supply 513D is floating from the ground and electrically connected to the negative electrode of the first DC power supply 511D, it is possible to use a DC power supply having a relatively small maximum output voltage level as the third DC power supply 513D.

[0104] Reference will now be made to FIG. 14 . FIG. 14 is a diagram schematically illustrating a bias power supply system according to yet another exemplary embodiment. The bias power supply system 50F illustrated in FIG. 14 can be employed in the plasma processing apparatus 101 in place of the bias power supply system 50D. In the bias power supply system 50F, the first DC power supply 511D is composed of a plurality of DC power supplies connected in series. In addition, in the bias power supply system 50F, the second DC power supply 512D is composed of the plurality of DC power supplies of the first DC power supply 511D and a plurality of DC power supplies connected in series with the first DC power supply 511D. In addition, in the bias power supply system 50F, the third DC power supply 513D is composed of a plurality of DC power supplies connected in series. In addition, in the bias power supply system 50F, the fourth DC power supply 514D is composed of the plurality of DC power supplies of the third DC power supply 513D and a plurality of DC power supplies connected in series with the third DC power supply 513D. Other configurations of the bias power supply system 50F are similar to the corresponding configurations of the bias power supply system 50E. Furthermore, the control of the first switching circuit 531D and the second switching circuit 532D by the pulse control unit 54D in the bias power supply system 50F is similar to the control of the first switching circuit 531D and the second switching circuit 532D by the pulse control unit 54D in the bias power supply system 50D.

[0105] Reference will now be made to Fig. 15 , which is a diagram schematically illustrating a bias power supply system according to yet another exemplary embodiment. A bias power supply system 50G illustrated in Fig. 15 can be employed in the plasma processing apparatus 101 in place of the bias power supply system 50D. The bias power supply system 50G will be described below from the perspective of differences from the bias power supply system 50D.

[0106] The bias power supply system 50G includes at least one DC power supply, namely, a first DC power supply 511G and a second DC power supply 512G. The bias power supply system 50G further includes a first switching circuit 531G and a second switching circuit 532G. The first switching circuit 531G and the second switching circuit 532G may be configured as a single switching circuit. The bias power supply system 50G further includes a pulse control unit 54G.

[0107] The first DC power supply 511G is capable of outputting an output voltage having a first ultimate voltage level of a first voltage pulse VP1 (see FIG. 16(a)). The second DC power supply 512G is capable of outputting an output voltage having a second ultimate voltage level of a second voltage pulse VP2 (see FIG. 16(a)). The positive electrodes of the first DC power supply 511G and the second DC power supply 512G may be connected to ground. The negative electrode of the first DC power supply 511G is connected to a first switching circuit 531G, and the negative electrode of the second DC power supply 512G is connected to a second switching circuit 532G.

[0108] The first switching circuit 531G includes a first switching element SW1 and a switching element SWG1. The first switching element SW1 is electrically connected between the negative electrode of the first DC power supply 511G and the first bias electrode BE1. The switching element SWG1 is connected between the first bias electrode BE1 and ground. The second switching circuit 532G includes a second switching element SW2 and a switching element SWG2. The second switching element SW2 is electrically connected between the negative electrode of the second DC power supply 512G and the second bias electrode BE2. The switching element SWG2 is connected between the second bias electrode BE2 and ground.

[0109] The pulse control unit 54G is configured to control the first switching circuit 531G and the second switching circuit 532G. The pulse control unit 54G is configured to control the first switching circuit 531G so that the voltage level of the first voltage pulse VP1 gradually reaches its first final voltage level, which has a maximum potential difference in the negative direction relative to the reference potential. The pulse control unit 54G is configured to control the second switching circuit 532G so that the voltage level of the second voltage pulse VP2 gradually reaches its final voltage level, which has a maximum potential difference in the negative direction relative to the reference potential.

[0110] The pulse control unit 54G is configured to control the first switching circuit 531G to alternately open and close the first switching element SW1 when applying a first voltage pulse VP1 to the first bias electrode BE1, and to control the second switching circuit 532G to alternately open and close the second switching element SW2 when applying a second voltage pulse VP2 to the second bias electrode BE2.

[0111] An example of the operation of the pulse control unit 54G will be described below. Fig. 16(a) is a timing chart of an example related to a bias power supply system according to yet another exemplary embodiment. Fig. 16(b) is an enlarged view of a portion S of Fig. 16(a). In Fig. 16(a), the vertical axis represents the states of the first switching element SW1, the second switching element SW2, the switching element SWG1, and the switching element SWG2, as well as the voltage levels of the first voltage pulse VP1 and the second voltage pulse VP2.

[0112] 16A, the pulse control unit 54G may be configured to periodically apply a first voltage pulse VP1 and a second voltage pulse VP2 to the first bias electrode BE1 and the second bias electrode BE2, respectively. The waveform cycles of the first voltage pulse VP1 and the second voltage pulse VP2 include a first period T1G and a second period T2G. During the first period T1G, the pulse control unit 54G controls the first switching circuit 531G to gradually increase the voltage level of the first voltage pulse VP1 to a first final voltage level. Furthermore, during the first period T1G, the pulse control unit 54G controls the second switching circuit 532G to gradually increase the voltage level of the second voltage pulse VP2 to a second final voltage level. In the second period T2G, the pulse control unit 54G sets the level of the output voltage from the bias power supply system 50G to the first bias electrode BE1 to a reference potential level (e.g., ground potential). Also, in the second period T2G, the pulse control unit 54G sets the level of the output voltage from the bias power supply system 50G to the second bias electrode BE2 to a reference potential level (e.g., ground potential).

[0113] In the first period T1G, the pulse control unit 54G sets the switching elements SWG1 and SWG2 to an open state. In the illustrated example, the first period T1G includes periods T11a to T14b. The duration of each of the periods T11a to T14b may be determined in advance.

[0114] Period T11a is the first subperiod within the first period T1G. During period T11a, the pulse control unit 54G sets the first switching element SW1 and the second switching element SW2 to the closed state. During period T11a, the voltage level of the first voltage pulse VP1 reaches the first voltage level VG1, and the voltage level of the second voltage pulse VP2 reaches the fifth voltage level VG5. During the following period T11b, the pulse control unit 54G sets the first switching element SW1 and the second switching element SW2 to the open state. During period T11b, the first bias electrode BE1 and the second bias electrode BE2 are floating from ground.

[0115] During the following period T12a, the pulse control unit 54G sets the first switching element SW1 and the second switching element SW2 to a closed state. During period T12a, the voltage level of the first voltage pulse VP1 reaches the second voltage level VG2, and the voltage level of the second voltage pulse VP2 reaches the sixth voltage level VG6. The difference between the second voltage level VG2 and the reference potential is equal to or greater than the difference between the first voltage level VG1 and the reference potential, and the difference between the sixth voltage level VG6 and the reference potential is equal to or greater than the difference between the fifth voltage level VG5 and the reference potential. During the following period T12b, the pulse control unit 54G sets the first switching element SW1 and the second switching element SW2 to an open state. During period T12b, the first bias electrode BE1 and the second bias electrode BE2 are floating from ground.

[0116] During the following period T13a, the pulse control unit 54G sets the first switching element SW1 and the second switching element SW2 to a closed state. During period T13a, the voltage level of the first voltage pulse VP1 reaches a third voltage level VG3, and the voltage level of the second voltage pulse VP2 reaches a seventh voltage level VG7. The difference between the third voltage level VG3 and the reference potential is equal to or greater than the difference between the second voltage level VG2 and the reference potential, and the difference between the seventh voltage level VG7 and the reference potential is equal to or greater than the difference between the sixth voltage level VG6 and the reference potential. During the following period T13b, the pulse control unit 54G sets the first switching element SW1 and the second switching element SW2 to an open state. During period T13b, the first bias electrode BE1 and the second bias electrode BE2 are floating from ground.

[0117] During the following period T14a, the pulse control unit 54G sets the first switching element SW1 and the second switching element SW2 to a closed state. During period T14a, the voltage level of the first voltage pulse VP1 reaches the fourth voltage level VG4, i.e., the first final voltage level, and the voltage level of the second voltage pulse VP2 reaches the eighth voltage level VG8, i.e., the second final voltage level. The difference between the fourth voltage level VG4, i.e., the first final voltage level, and the reference potential is equal to or greater than the difference between the third voltage level VG3 and the reference potential, and the difference between the eighth voltage level VG8, i.e., the second final voltage level, and the reference potential is equal to or greater than the difference between the seventh voltage level VG7 and the reference potential. During the following period T14b, the pulse control unit 54G sets the first switching element SW1 and the second switching element SW2 to an open state. In the period T14b, the first bias electrode BE1 and the second bias electrode BE2 are floating from the ground.

[0118] 16A, in the first period T1G, the voltage level of the first voltage pulse VP1 and the second voltage pulse VP2 reach the first and second ultimate voltage levels in four stages. Note that the number of stages through which the first voltage pulse VP1 and the second voltage pulse VP2 reach their ultimate voltage levels in the first period T1G is not limited to four.

[0119] In a second period T2G following the first period T1G, the pulse control unit 54G sets the first switching element SW1 and the second switching element SW2 to an open state. In addition, in the second period T2G, the pulse control unit 54G may set the switching element SWG1 and the switching element SWG2 to a closed state.

[0120] Reference will now be made to Fig. 17, which is a diagram schematically illustrating a bias power supply system according to yet another exemplary embodiment. A bias power supply system 50H illustrated in Fig. 17 can be employed in the plasma processing apparatus 101 in place of the bias power supply system 50D. The bias power supply system 50H will be described below from the perspective of differences from the bias power supply system 50G.

[0121] In the bias power supply system 50H, the positive terminal of the second DC power supply 512G is floating from the ground and connected to the negative terminal of the first DC power supply 511G. Other configurations of the bias power supply system 50H are similar to the corresponding configurations of the bias power supply system 50G. According to the bias power supply system 50H, it is possible to use a DC power supply having a relatively small maximum output voltage level as the second DC power supply 512G.

[0122] A plasma processing method according to one exemplary embodiment will be described in detail below with reference to Fig. 18. Fig. 18 is a flow chart of the plasma processing method according to one exemplary embodiment. The plasma processing method shown in Fig. 18 (hereinafter referred to as "method MT1") can be performed using plasma processing apparatus 1 or plasma processing apparatus 101. In each step of method MT1, each part of the plasma processing apparatus can be controlled by control unit 2 and / or the above-mentioned pulse control unit.

[0123] The method MT1 starts with step STa, in which a substrate W is prepared. In step STa, the substrate W is placed on the substrate support surface 111a of the substrate support 11 disposed in the chamber 10. Steps subsequent to step STa in the method MT1 are performed with the substrate W placed on the substrate support 11.

[0124] After the process STa, a process ST11 is performed. In the process ST11, plasma is generated in the chamber 10. In the process ST11, gas is supplied from the gas supply unit 20 to the internal space 10s. In the process ST11, the pressure in the chamber 10 is reduced to a specified pressure by the exhaust system 40. In the process ST11, plasma is generated from the gas in the chamber 10 by the plasma generating unit 12. In one embodiment, a source RF signal is supplied from the first RF generating unit 31a to generate plasma from the gas in the chamber 10.

[0125] Step ST11 is followed by step ST12. When the plasma processing apparatus 1 is used, in step ST12, a voltage pulse VP is intermittently or periodically applied to the bias electrode BE of the substrate support 11 to attract ions from the plasma to the substrate W. In step ST12, as described above with respect to the plasma processing apparatus 1, the switching circuit of the bias power supply system is controlled by the pulse controller so that the voltage pulse VP gradually reaches its target voltage level.

[0126] When the plasma processing apparatus 101 is used, in step ST12, a first voltage pulse VP1 and a second voltage pulse VP2 are intermittently or periodically applied to the first bias electrode BE1 and the second bias electrode BE2, respectively, to attract ions from the plasma to the substrate W. In step ST12, as described above with respect to the plasma processing apparatus 101, a first switching circuit of the bias power supply system is controlled by a pulse controller so that the first voltage pulse VP1 gradually reaches its first ultimate voltage level. Also, in step ST12, as described above with respect to the plasma processing apparatus 101, a second switching circuit of the bias power supply system is controlled by a pulse controller so that the second voltage pulse VP2 gradually reaches its second ultimate voltage level.

[0127] The method MT1 may further include a process STJ1. In the process STJ1, it is determined whether a stop condition is satisfied. The stop condition is satisfied, for example, when the number of times that the sequence SQ1 including the process ST11 and the process ST12 has been executed reaches a predetermined number. If it is determined that the stop condition is not satisfied in the process STJ1, the sequence SQ1 is executed again from the process ST11. On the other hand, if it is determined that the stop condition is satisfied in the process STJ1, the method MT1 ends.

[0128] The following describes examples of processing circuits that can be used as one or more processing circuits in a plasma processing apparatus, such as the control unit 2 and / or pulse control units 54, 54C-54G. FIG. 19 is a block diagram of a processing circuit for implementing the operations described herein on a computer. FIG. 19 illustrates a processing circuit 130 that can be used to control a control process on any computer. The descriptions or blocks in the flowcharts represent modules, segments, or portions of code that contain one or more executable instructions for implementing specific logical functions or steps of the process. As will be understood by those skilled in the art, other examples having functions that can be performed in a different order than that shown or described, such as substantially concurrently or in reverse order, depending on the functionality involved, are within the scope of the exemplary embodiments of the present disclosure. The various elements, features, and processes described herein may be used independently of one another or may be combined in various ways. All conceivable combinations and subcombinations are within the scope of the present disclosure.

[0129] In Figure 19, processing circuitry 130 includes a CPU 1200 that performs one or more of the control processes described above and / or below. Process data and instructions may be stored in memory 1202. These process data and instructions may be stored on a storage medium disk 1204, such as a hard disk drive (HDD) or a portable storage medium, or may be stored remotely. Furthermore, the claimed disclosure is not limited by the form of computer-readable medium on which instructions for processes according to the present invention are stored. For example, these instructions may be stored on a CD, DVD, flash memory, RAM, ROM, PROM, EPROM, EEPROM, hard disk, or any other information processing device, such as a server and / or computer, with which processing circuitry 130 communicates.

[0130] Additionally, the claimed disclosure may be provided as a utility application, a background daemon, a component of an operating system, or a combination thereof. The claimed disclosure may be executed in conjunction with a CPU 1200 and an operating system known to those skilled in the art, such as Microsoft Windows, UNIX, Solaris, LINUX, Apple MAC-OS, or the like.

[0131] The hardware elements making up the processing circuit 130 can be realized by various circuit elements. Furthermore, each function of the above-described embodiments can be implemented by a circuit including one or more processing circuits. As shown in FIG. 19, the processing circuit includes a specifically programmed processing unit, such as a processing unit (CPU) 1200. The processing circuit also includes devices such as application specific integrated circuits (ASICs) or conventional circuit components configured to perform the described functions.

[0132] 19, processing circuitry 130 includes a CPU 1200 that performs the above-described processing. Processing circuitry 130 may be a general-purpose computer or a specific dedicated machine. In one embodiment, processing circuitry 130 functions as a specific dedicated machine when processing device 1200 is programmed to control plasma generation unit 12 and gas supply unit 20 and / or to control bias power supply systems 50, 50A-50H.

[0133] Alternatively or additionally, CPU 1200 may be implemented on an FPGA, ASIC, PLD, or using discrete logic circuitry, as will be appreciated by those skilled in the art. Furthermore, CPU 1200 may be implemented as multiple processing units cooperating to perform in parallel the instructions of the processes of the present invention described above.

[0134] The processing circuitry 130 of FIG. 19 also includes a network controller 1206, such as an Intel Ethernet PRO network interface card from Intel Corporation of America, for interfacing with a network 1228. As can be appreciated, the network 1228 may be a public network such as the Internet, a private network such as a LAN or WAN, or any combination thereof, and may also include sub-networks such as PSTN or ISDN. The network 1228 may also be wired, such as an Ethernet network, or wireless, such as a cellular network including EDGE, 3G, and 4G wireless cellular systems. The wireless network may also be Wi-Fi, Bluetooth, or any other known form of wireless communication.

[0135] The processing circuitry 130 further includes a display device controller 1208, such as a graphics card or graphics adapter, for interfacing with a display device 1210, such as a monitor. A general-purpose I / O interface 1212 interfaces with a keyboard and / or mouse 1214 and a touch panel 1216, which may be integral with or separate from the display device 1210. The general-purpose I / O interface also connects to various peripheral devices 1218, such as printers and scanners.

[0136] The storage controller 1224 is connected to the storage media disk 1204 via a communication bus 1226, such as ISA, EISA, VESA, PCI, etc., and all components of the processing circuit 130 are connected to each other. The display device 1210, keyboard and / or mouse 1214, and the general features and functions of the display device controller 1208, storage controller 1224, network controller 1206, audio controller 1220, and general purpose I / O interface 1212 are not described herein for the sake of brevity, as they are well known.

[0137] The exemplary circuit elements described in this disclosure may be substituted with other elements and may have different structures than the examples described herein. Furthermore, circuits configured to implement the features described herein may be implemented in multiple circuit units (e.g., chips), or these features may be combined into the circuitry of a single chipset.

[0138] The functions and features described herein may also be performed by various distributed components on a system. For example, one or more processing devices may perform the functions of these systems, where the processing devices are distributed across multiple components communicating within a network. Distributed components may include various human interface and communication devices (e.g., display monitors, smartphones, tablets, personal digital assistants (PDAs)), as well as one or more client and server machines that can share processing. The network may be a private network, such as a LAN or WAN, or a public network, such as the Internet. Input to the system may be received directly by a user or remotely in real time or as a batch process. Furthermore, portions of the embodiments may be implemented on modules or hardware other than those described above. Accordingly, other embodiments are within the scope of the claims.

[0139] Although various exemplary embodiments have been described above, the present invention is not limited to the above-described exemplary embodiments, and various additions, omissions, substitutions, and modifications may be made. Furthermore, elements in different embodiments may be combined to form other embodiments.

[0140] In the bias power supply systems of the various exemplary embodiments described above, the switching operation of the switching circuit for gradually increasing the voltage level of the voltage pulse to the final voltage level is controlled by a pulse control unit of the bias power supply system. In another embodiment, the pulse control unit may not be part of the bias power supply system. Alternatively, the plasma processing apparatus may not include a pulse control unit, and the switching circuit may be configured to perform the switching operation for gradually increasing the voltage level of the voltage pulse to the final voltage level without relying on control from any control unit.

[0141] From the foregoing, it will be understood that various embodiments of the present disclosure have been described herein for purposes of illustration, and that various modifications may be made without departing from the scope and spirit of the present disclosure. Accordingly, the various embodiments disclosed herein are not intended to be limiting, with the true scope and spirit being indicated by the appended claims.

[0142] 1, 101...plasma processing apparatus, 10...chamber, 11...substrate support portion, BE1...first bias electrode, BE2...second bias electrode, BE...bias electrode, 12...plasma generation portion, 50...bias power supply system, 51...DC power supply, 53...switching circuit, 54...pulse control portion.

Claims

1. A plasma processing apparatus comprising: a chamber; a substrate support having a bias electrode and disposed within the chamber; a plasma generation unit configured to generate plasma within the chamber; and a bias power supply system electrically coupled to the bias electrode and configured to intermittently apply voltage pulses to the bias electrode to attract ions from the plasma to the substrate on the substrate support, wherein the bias power supply system includes: at least one DC power supply; a switching circuit electrically connected between the bias electrode and the at least one DC power supply; and a pulse control unit configured to control the switching circuit, wherein the pulse control unit is configured to control the switching circuit to gradually increase the voltage level of the voltage pulse to a target voltage level having a maximum potential difference in the negative direction with respect to a reference potential.

2. The plasma processing apparatus according to claim 1, wherein the at least one DC power supply includes: a first DC power supply capable of outputting an output voltage having a potential difference with respect to the reference potential that is smaller than the ultimate voltage level; and a second DC power supply capable of outputting an output voltage having the ultimate voltage level; the switching circuit includes: a first switching element electrically connected between a negative electrode of the first DC power supply and the bias electrode; and a second switching element electrically connected between a negative electrode of the second DC power supply and the bias electrode; and the pulse control unit is configured to control the switching circuit to, in applying the voltage pulse, set the first switching element to a closed state and the second switching element to an open state, and then set the second switching element to a closed state and the first switching element to an open state.

3. The plasma processing apparatus according to claim 2, wherein the positive electrode of the second DC power supply is floating from the ground and electrically connected to the negative electrode of the first DC power supply.

4. The plasma processing apparatus according to claim 2, wherein the first DC power supply includes one or more DC power supplies, and the second DC power supply includes the one or more DC power supplies of the first DC power supply and one or more DC power supplies connected in series with the one or more DC power supplies of the first DC power supply.

5. The bias electrode is a first bias electrode, the voltage pulse is a first voltage pulse, and the ultimate voltage level is a first ultimate voltage level; the substrate support portion includes: a substrate support surface; a ring support surface; the first bias electrode extending below the substrate support surface and electrically coupled to the substrate on the substrate support surface; and a second bias electrode separate from the first bias electrode, extending below the ring support surface and electrically coupled to an edge ring placed on the ring support surface to surround the substrate; the at least one DC power supply includes: a third DC power supply capable of outputting an output voltage having a potential difference with respect to the reference potential that is smaller than a second ultimate voltage level that has a maximum potential difference in the negative direction with respect to the reference potential; and a fourth DC power supply capable of outputting an output voltage having the second ultimate voltage level; and the switching circuit includes: a third switching element electrically connected between the negative pole of the third DC power supply and the second bias electrode; a fourth switching element electrically connected between a negative electrode of the fourth DC power supply and the second bias electrode, wherein the pulse control unit is configured to control the switching circuit to, in applying a second voltage pulse to the edge ring, set the third switching element to a closed state and set the fourth switching element to an open state, and then set the fourth switching element to a closed state and set the third switching element to an open state.

10. The plasma processing apparatus of claim 2, 6. The plasma processing apparatus according to claim 5, wherein the positive electrode of the fourth DC power supply is floating from the ground and electrically connected to the negative electrode of the third DC power supply.

7. The plasma processing apparatus according to claim 5, wherein the first DC power supply includes one or more DC power supplies, the second DC power supply includes the one or more DC power supplies of the first DC power supply and one or more DC power supplies connected in series with the one or more DC power supplies of the first DC power supply, the third DC power supply includes one or more DC power supplies, and the fourth DC power supply includes the one or more DC power supplies of the third DC power supply and one or more DC power supplies connected in series with the one or more DC power supplies of the third DC power supply.

8. The plasma processing apparatus according to claim 1, wherein the at least one DC power supply includes a single DC power supply, the switching circuit includes a switching element connected between the bias electrode and the single DC power supply, and the pulse control unit is configured to control the switching circuit so that the voltage level of the voltage pulse gradually reaches the target voltage level by alternately repeating opening and closing of the switching element.

9. A plasma processing apparatus as described in any one of claims 1 to 4 and 8, wherein the switching circuit further includes another switching element electrically connected between ground and the bias electrode, and the pulse control unit is configured to control the switching circuit so as to set the other switching element to an open state during a period when the voltage pulse is applied to the bias electrode, and to set the other switching element to a closed state during a period when the voltage pulse is not applied to the bias electrode.

10. The bias electrode is a first bias electrode, the voltage pulse is a first voltage pulse, and the ultimate voltage level is a first ultimate voltage level, the substrate support portion includes: a substrate support surface; a ring support surface; the first bias electrode extending below the substrate support surface and electrically coupled to the substrate on the substrate support surface; and a second bias electrode separate from the first bias electrode, extending below the ring support surface and electrically coupled to an edge ring placed on the ring support surface to surround the substrate, the at least one DC power supply includes: a first DC power supply capable of outputting an output voltage having the first ultimate voltage level; and a second DC power supply capable of outputting an output voltage having a second ultimate voltage level having a maximum potential difference in the negative direction with respect to the reference potential, and the switching circuit includes: a first switching element electrically connected between the negative pole of the first DC power supply and the first bias electrode, a second switching element electrically connected between the negative pole of the second DC power supply and the second bias electrode, wherein the pulse control unit is configured to control the switching circuit so that, in applying the first voltage pulse to the first bias electrode, the voltage level of the first voltage pulse reaches the first final voltage level in stages by alternately repeating opening and closing of the first switching element, and, in applying a second voltage pulse to the second bias electrode, the voltage level of the second voltage pulse reaches the second final voltage level in stages by alternately repeating opening and closing of the second switching element.

11. The plasma processing apparatus according to claim 10, wherein the positive electrode of the second DC power supply is floating from the ground and electrically connected to the negative electrode of the first DC power supply.

12. The plasma processing apparatus according to claim 5 or 10, wherein the switching circuit further includes a first other switching element connected between the first bias electrode and ground, and a second other switching element connected between the second bias electrode and ground, and the pulse control unit is configured to control the switching circuit to set the first other switching element to an open state during a period when the first voltage pulse is applied to the first bias electrode, and to set the first other switching element to a closed state during a period when the first voltage pulse is not applied to the first bias electrode, and to set the second other switching element to an open state during a period when the second voltage pulse is applied to the second bias electrode, and to set the second other switching element to a closed state during a period when the second voltage pulse is not applied to the second bias electrode.

13. A bias power supply system configured to apply intermittent voltage pulses to a bias electrode of a substrate support in order to attract ions from plasma in a chamber of a plasma processing apparatus to a substrate on the substrate support in the chamber, the bias power supply system comprising: at least one DC power supply; and a switching circuit electrically connected between the bias electrode and the at least one DC power supply, the switching circuit being configured to, by its switching operation, gradually cause the voltage level of the voltage pulse to reach an ultimate voltage level having a maximum potential difference in the negative direction relative to a reference potential.

14. A plasma processing method comprising: (a) preparing a substrate, the substrate being placed on a substrate support within a chamber of a plasma processing apparatus; (b) generating plasma within the chamber; and (c) intermittently applying voltage pulses to a bias electrode of the substrate support to attract ions to the substrate, wherein (c) includes controlling a switching circuit electrically connected between the bias electrode and at least one DC power supply so as to gradually increase the voltage level of the voltage pulse to a target voltage level having a maximum potential difference in the negative direction relative to a reference potential.

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