Multilayer device

Abstract

This multilayer device comprises: a first signal path which connects a pair of first external electrodes; a second signal path which connects a pair of second external electrodes; a first ground connection path which connects one of the first external electrodes and a first ground electrode; and a second ground connection path which connects one of the second external electrodes and a second ground electrode. The first signal path and the second signal path have a common mode choke coil. The first ground connection path has a first counter electrode which is capacitively coupled to one of the first external electrodes, and a first conductor line which connects the first counter electrode and the first ground electrode. The second ground connection path has a second counter electrode which is capacitively coupled to one of the second external electrodes, and a second conductor line which connects the second counter electrode and the second ground electrode.

Description

stacked devices

[0001] The present disclosure relates to stacked devices.

[0002] 2. Description of the Related Art Conventionally, filters that remove common-mode noise contained in differential signals have been known. Patent Document 1 discloses an electronic component that removes common-mode noise.

[0003] Patent No. 5516160

[0004] The electronic component described in Patent Document 1 can block the passage of common mode signals of specific frequencies, but has the problem that the frequency band that can be blocked is narrow.

[0005] A laminated device according to one aspect of the present disclosure includes an insulator formed by stacking a plurality of insulating layers, one first external electrode and the other first external electrode provided on an outer surface of the insulator, one second external electrode and the other second external electrode provided on the outer surface of the insulator, a first ground electrode and a second ground electrode provided on the outer surface of the insulator, and a plurality of paths provided inside the insulator, the plurality of paths including a first signal path connecting the one first external electrode and the other first external electrode, a second signal path connecting the one second external electrode and the other second external electrode, and a second signal path connecting the one first external electrode and the first ground electrode. the first signal path has a first coil, the second signal path has a second coil that forms a common mode choke coil together with the first coil, the first ground connection path has a first opposing electrode that is capacitively coupled to the one of the first external electrodes, and a first conductor line that electrically connects the first opposing electrode and the first ground electrode, and the second ground connection path has a second opposing electrode that is capacitively coupled to the one of the second external electrodes, and a second conductor line that electrically connects the second opposing electrode and the second ground electrode.

[0006] According to a stacked device according to an aspect of the present disclosure, it is possible to widen a stop band that blocks the passage of common mode signals.

[0007] FIG. 1 is a diagram showing an equivalent circuit of the multilayer device according to the first embodiment. FIG. 2 is a perspective view of the multilayer device according to the first embodiment. FIG. 3 is a diagram showing internal conductors of the multilayer device according to the first embodiment. FIG. 4 is a diagram showing internal conductors of the multilayer device according to the first embodiment as viewed from the top surface side. FIG. 5A is a diagram showing internal conductors of the multilayer device according to the first embodiment as viewed from a third side surface side. FIG. 5B is a diagram showing an equivalent circuit of another multilayer device according to the first embodiment. FIG. 6 is a diagram showing an equivalent circuit of a multilayer device according to a modification of the first embodiment. FIG. 7 is a diagram showing internal conductors of a multilayer device according to a modification of the first embodiment. FIG. 8 is a diagram showing an equivalent circuit of a multilayer device according to a comparative example. FIG. 9 is a diagram showing first signal paths and second signal paths of a multilayer device according to a comparative example. FIG. 10 is a diagram showing common mode signal transmission characteristics of the multilayer device according to the comparative example. FIG. 11 is a diagram showing common mode signal transmission characteristics of the multilayer device according to the modification of the first embodiment. FIG. 12 is a perspective view of a multilayer device according to the second embodiment. FIG. 13 is a diagram showing internal conductors of the multilayer device according to the second embodiment. FIG. 14 is a diagram showing internal conductors of the multilayer device according to the second embodiment as viewed from a second side surface side. Fig. 15 is a view of an internal conductor of the multilayer device according to embodiment 2 as viewed from a third side surface. Fig. 16 is a view showing an equivalent circuit of a multilayer device according to a modification of embodiment 2. Fig. 17 is a view showing an internal conductor of a multilayer device according to a modification of embodiment 2. Fig. 18 is a view showing the pass characteristics of a common mode signal of a multilayer device according to a modification of embodiment 2.

[0008] Hereinafter, embodiments will be described with reference to the drawings. Each of the embodiments described below represents a specific example of the present disclosure. The numerical values, shapes, materials, components, component placement positions, connection forms, steps, and step order shown in the following embodiments are merely examples and are not intended to limit the present disclosure. Furthermore, among the components in the following embodiments, components not recited in independent claims will be described as optional components.

[0009] Furthermore, in this specification, terms indicating the relationship between elements, such as parallelism, terms indicating the shape of elements, such as rectangular parallelepiped, and numerical ranges are not expressions that only express a strict meaning, but are expressions that also include a substantially equivalent range, for example, a difference of about a few percent.

[0010] In addition, each drawing is a schematic diagram in which emphasis, omission, or adjustment of proportions has been appropriately made to illustrate the present disclosure, and is not necessarily an exact illustration, and may differ from the actual shape, positional relationship, and proportion. In each drawing, substantially the same configuration is assigned the same reference numeral, and duplicated explanations may be omitted or simplified.

[0011] Furthermore, in this specification, the terms "top surface" and "bottom surface" in the configuration of a stacked device do not refer to the top surface (the surface on the vertically upper side) and bottom surface (the surface on the vertically lower side) in absolute spatial recognition, but are used as terms defined by the relative positional relationship of the components of the stacked device.

[0012] First Embodiment [Equivalent Circuit of Multilayer Device] An equivalent circuit of a multilayer device 1 according to a first embodiment will be described with reference to FIG.

[0013] FIG. 1 is a diagram showing an equivalent circuit of a stacked device 1 according to the first embodiment.

[0014] As shown in FIG. 1, the laminated device 1 includes a pair of first external electrodes, that is, one first external electrode P1a and the other first external electrode P1b, a pair of second external electrodes, that is, one second external electrode P2a and the other second external electrode P2b, and a first ground electrode G1 and a second ground electrode G2.

[0015] The laminated device 1 also has a first signal path R1 connecting one first external electrode P1a and the other first external electrode P1b, and a second signal path R2 connecting one second external electrode P2a and the other second external electrode P2b.

[0016] When the laminated device 1 is mounted on a substrate of an electronic device, the first ground electrode G1 and the second ground electrode G2 are set to ground potential. Differential signals are input to and output from the pair of first external electrodes P1a, P1b and the pair of second external electrodes P2a, P2b, and differential signals are transmitted through the first signal path R1 and the second signal path R2.

[0017] The first signal path R1 and the second signal path R2 are provided with a common mode choke coil 50. The common mode choke coil 50 is composed of a first coil 51 provided on the first signal path R1 and a second coil 52 provided on the second signal path R2. The first coil 51 is composed of two coils 51a and 51b connected in series, and the second coil 52 is composed of two coils 52a and 52b connected in series.

[0018] The first coil 51 and the second coil 52 are arranged so as to be electromagnetically coupled when a differential signal is transmitted to the first signal path R1 and the second signal path R2. In the multilayer device 1, the electromagnetic coupling between the first coil 51 and the second coil 52 makes it possible to remove common mode noise of a specific frequency contained in the differential signal.

[0019] Furthermore, the laminated device 1 includes a first ground connection path Rg1 connecting the first external electrode P1a and the first ground electrode G1 on one side, a second ground connection path Rg2 connecting the second external electrode P2a and the second ground electrode G2 on one side, a third ground connection path Rg3 connecting the first external electrode P1b and the first ground electrode G1 on the other side, and a fourth ground connection path Rg4 connecting the second external electrode P2b and the second ground electrode G2 on the other side.

[0020] That is, one end of the first ground connection path Rg1 is connected to one of the first external electrodes P1a, and the other end of the first ground connection path Rg1 is connected to the first ground electrode G1. One end of the second ground connection path Rg2 is connected to one of the second external electrodes P2a, and the other end of the second ground connection path Rg2 is connected to the second ground electrode G2. One end of the third ground connection path Rg3 is connected to the other first external electrode P1b, and the other end of the third ground connection path Rg3 is connected to the first ground electrode G1. One end of the fourth ground connection path Rg4 is connected to the other second external electrode P2b, and the other end of the fourth ground connection path Rg4 is connected to the other second ground electrode G2.

[0021] A first LC resonant circuit LC1 configured with a first capacitor C1 and a first inductor L1 connected in series is provided on the first ground connection path Rg1. A second LC resonant circuit LC2 configured with a second capacitor C2 and a second inductor L2 connected in series is provided on the second ground connection path Rg2. A third LC resonant circuit LC3 configured with a third capacitor C3 and a third inductor L3 connected in series is provided on the third ground connection path Rg3. A fourth LC resonant circuit LC4 configured with a fourth capacitor C4 and a fourth inductor L4 connected in series is provided on the fourth ground connection path Rg4.

[0022] The resonant frequency of the first LC resonant circuit LC1, the resonant frequency of the second LC resonant circuit LC2, the resonant frequency of the third LC resonant circuit LC3, and the resonant frequency of the fourth LC resonant circuit LC4 are set to predetermined frequencies different from the specific frequencies removed by the common mode choke coil 50.

[0023] In the multilayer device 1 of this embodiment, when a differential signal is transmitted to the first signal path R1 and the second signal path R2, the first LC resonant circuit LC1, the second LC resonant circuit LC2, the third LC resonant circuit LC3, and the fourth LC resonant circuit LC4 each resonate at a predetermined frequency. The first LC resonant circuit LC1, the second LC resonant circuit LC2, the third LC resonant circuit LC3, and the fourth LC resonant circuit LC4 each resonate at a predetermined frequency, thereby allowing common mode noise of the predetermined frequency to escape to ground. This allows the multilayer device 1 to remove common mode noise of a predetermined frequency different from the specific frequency, in addition to the specific frequency removed by the common mode choke coil 50.

[0024] [Structure of the Multilayer Device] The structure of the multilayer device 1 according to the first embodiment will be described with reference to FIGS. 2 to 5A.

[0025] Fig. 2 is a perspective view of the multilayer device 1. Fig. 3 is a diagram showing the internal conductors of the multilayer device 1. Fig. 4 is a diagram showing the internal conductors of the multilayer device 1 as viewed from the top surface 19 side. Fig. 5A is a diagram showing the internal conductors of the multilayer device 1 as viewed from the third side surface 13 side. In Figs. 3 to 5A, the internal conductors are shown with solid lines, and the insulators 10, external electrodes, and ground electrodes are shown with dashed lines.

[0026] The laminated device 1 is a surface-mounted common mode noise filter, and has dimensions of, for example, a length of 1.2 mm, a width of 1.0 mm, and a height of 0.3 mm.

[0027] The stacked device 1 shown in Figures 2 to 5A includes an insulator 10 formed from an insulating material, one first external electrode P1a and the other first external electrode P1b provided on the outer surface of the insulator 10, one second external electrode P2a and the other second external electrode P2b provided on the outer surface of the insulator 10, a first ground electrode G1 and a second ground electrode G2 provided on the outer surface of the insulator 10, and a plurality of paths provided inside the insulator 10.

[0028] The insulator 10 is formed, for example, by stacking multiple insulating layers 15 (see FIG. 5A ) in a stacking direction (direction D3) with multiple interfaces 95 interposed therebetween. That is, each insulating layer 15 has two interfaces 95 among the multiple interfaces 95 that face each other in the stacking direction. The insulating layers 15 are formed of a magnetic material or a non-magnetic material such as glass. The insulator 10 may be formed by stacking multiple magnetic insulating layers 15 and multiple non-magnetic insulating layers 15. The non-magnetic insulating layers 15 may be dielectric layers. The thickness of the insulating layers 15 is appropriately selected, for example, from a range of 10 μm to 100 μm. Note that FIG. 5A omits the illustration of some of the multiple insulating layers 15 for ease of explanation. Also, although the insulating layers 15 are indicated by dashed lines in the figure, in reality, the multiple insulating layers 15 are joined and integrated by sintering or the like to form the insulator 10, and the interfaces 95 of the insulating layers 15 are invisible.

[0029] The insulator 10 has a rectangular parallelepiped shape and includes a bottom surface 18, a top surface 19 facing away from the bottom surface 18, and a plurality of side surfaces connecting the bottom surface 18 and the top surface 19. The side surfaces include a first side surface 11 and a second side surface 12 facing away from each other, and a third side surface 13 and a fourth side surface 14 facing away from each other. The bottom surface 18 and the top surface 19 are parallel to each other, the first side surface 11 and the second side surface 12 are parallel to each other, and the third side surface 13 and the fourth side surface 14 are parallel to each other. The first side surface 11 and the second side surface 12 are perpendicular to the third side surface 13 and the fourth side surface 14, respectively. The bottom surface 18 and the top surface 19 are perpendicular to the first side surface 11, the second side surface 12, the third side surface 13, and the fourth side surface 14, respectively. Corners (ridges) where the surfaces of the insulator 10 intersect may be rounded.

[0030] Here, the direction in which the first side surface 11 and the second side surface 12 face each other is called the first direction D1, the direction in which the third side surface 13 and the fourth side surface 14 face each other is called the second direction D2, and the direction in which the bottom surface 18 and the top surface 19 face each other is called the third direction D3. In this example, the stacking direction in which the multiple insulating layers 15 are stacked is the same as the third direction D3. The stacking direction is the same as the direction in which the coil axis of the common mode choke coil 50 extends. In the following, the negative side of the first direction D1 may be referred to as "one side," and the positive side opposite the negative side may be referred to as "the other side."

[0031] 2 and 3 , the first external electrode P1a and the second external electrode P2a are each provided on a part of a first side surface 11, which is the outer surface of the insulator 10. The other first external electrode P1b and the other second external electrode P2b are each provided on a part of a second side surface 12, which is the outer surface of the insulator 10. The first ground electrode G1 is provided on a part of a third side surface 13, which is the outer surface of the insulator 10. The second ground electrode G2 is provided on a part of a fourth side surface 14, which is the outer surface of the insulator 10.

[0032] These external electrodes and ground electrodes are not limited to being formed on the side surfaces, but are also formed on parts of the bottom surface 18 and the top surface 19. For example, the first external electrode P1a, the first external electrode P1b, the second external electrode P2a, the second external electrode P2b, the first ground electrode G1, and the second ground electrode G2 are also formed on parts of the top surface 19 and the bottom surface 18, respectively. The first external electrode P1a, the second external electrode P2a, the first external electrode P1b, the second external electrode P2b, the first ground electrode G1, and the second ground electrode G2 are each provided at different positions on the outer surface of the insulator 10. The cross section of each external electrode and each ground electrode perpendicular to the width direction of the electrode has a square bracket ([, ]) shape.

[0033] 2, one first external electrode P1a is formed by a side electrode portion s1a provided on the first side surface 11, a bottom electrode portion b1a provided on the bottom surface 18 and connected to the end of the side electrode portion s1a on the bottom surface 18 side, and a top electrode portion t1a provided on the top surface 19 and connected to the end of the side electrode portion s1a on the top surface 19 side. The other first external electrode P1b is formed by a side electrode portion s1b provided on the second side surface 12, a bottom electrode portion b1b provided on the bottom surface 18 and connected to the end of the side electrode portion s1b on the bottom surface 18 side, and a top electrode portion t1b provided on the top surface 19 and connected to the end of the side electrode portion s1b on the top surface 19 side. One second external electrode P2a is formed by a side electrode portion s2a provided on the first side surface 11, a bottom electrode portion b2a provided on the bottom surface 18 and connected to the end of the side electrode portion s2a on the bottom surface 18 side, and a top electrode portion t2a provided on the top surface 19 and connected to the end of the side electrode portion s2a on the top surface 19 side. The other second external electrode P2b is formed by a side electrode portion s2b provided on the second side surface 12, a bottom electrode portion b2b provided on the bottom surface 18 and connected to the end of the side electrode portion s2b on the bottom surface 18 side, and a top electrode portion t2b provided on the top surface 19 and connected to the end of the side electrode portion s2b on the top surface 19 side.

[0034] As shown in FIG. 3, the multiple paths inside the insulator 10 include a first signal path R1, a second signal path R2, a first ground connection path Rg1, a second ground connection path Rg2, a third ground connection path Rg3, and a fourth ground connection path Rg4.

[0035] One end of the first signal path R1 is connected to one of the first external electrodes P1a, and the other end of the first signal path R1 is connected to the other first external electrode P1b. The first signal path R1 has a first coil 51, which is composed of two spiral coils 51a and 51b.

[0036] One end of the second signal path R2 is connected to one second external electrode P2a, and the other end of the second signal path R2 is connected to the other second external electrode P2b. The second signal path R2 has a first coil 51 and a second coil 52 that constitutes a common mode choke coil 50. The second coil 52 is composed of two spiral coils 52a and 52b.

[0037] The common mode choke coil 50 located on the first signal path R1 and the second signal path R2 is composed of multiple common mode choke coils 50a and 50b. Of the multiple common mode choke coils 50, the common mode choke coil 50a is formed by coils 51a and 52a, and the common mode choke coil 50b is formed by coils 51b and 52b. The multiple common mode choke coils 50a and 50b are arranged along the stacking direction (third direction D3) in which the multiple insulating layers 15 are stacked.

[0038] The first signal path R1 and the second signal path R2 have the same path length. More specifically, the first signal path R1 and the second signal path R2 are formed of metal materials such as connection electrodes, wiring, land electrodes, via conductors, and coils, which will be described below.

[0039] The first signal path R1 starts from a connection electrode a1 connected to one of the first external electrodes P1a, and is formed by connecting the connection electrode a1 to one end of the coil 51a via wiring, connecting the land b1 to the other end of the coil 51a, connecting the land b1, land c1, and land d1 in this order by via conductors, connecting one end of the coil 51b to the land d1, connecting the other end of the coil 51b to the connection electrode e1 via wiring, and connecting the connection electrode e1 to the other first external electrode P1b.

[0040] The second signal path R2 starts from a connection electrode a2 connected to one of the second external electrodes P2a, and is formed by connecting the connection electrode a2 to one end of the coil 52a via wiring, connecting the land b2 to the other end of the coil 52a, connecting the land b2, land c2, and land d2 in this order by via conductors, connecting one end of the coil 52b to the land d2, connecting the other end of the coil 52b to the connection electrode e2 via wiring, and connecting the connection electrode e2 to the other second external electrode P2b.

[0041] 4 are disposed outside the common mode choke coil 50 when viewed from the stacking direction (third direction D3). In other words, the first ground connection path Rg1, the second ground connection path Rg2, the third ground connection path Rg3, and the fourth ground connection path Rg4 do not overlap with the common mode choke coil 50 when viewed from the stacking direction (third direction D3).

[0042] The first ground connection path Rg1 includes a first opposing electrode 21 and a first conductor line 31 .

[0043] The first opposing electrode 21 is capacitively coupled to one of the first external electrodes P1a, thereby forming a capacitance in the first ground connection path Rg1. The first opposing electrode 21 is arranged to face a portion of one of the first external electrodes P1a via the insulating layer 15. In this example, the first opposing electrode 21 faces one of the first external electrodes P1a (i.e., the top surface electrode portion t1a) formed on the top surface 19. In other words, the top surface electrode portion t1a and the first opposing electrode 21 are electrodes for forming a first capacitance in the first ground connection path Rg1. The top surface electrode portion t1a and the first opposing electrode 21 face each other, thereby forming a first capacitor C1.

[0044] The first conductor line 31 is a line for forming a first inductance in the first ground connection path Rg1. The first conductor line 31 is formed by a plurality of wirings, land electrodes, via conductors, etc., and electrically connects the first opposing electrode 21 and the first ground electrode G1. The first conductor line 31 extends along a path from the first opposing electrode 21 to the first ground electrode G1. The first conductor line 31 has a predetermined length, cross-sectional area, and shape, and forms a first inductor L1. The length of the first conductor line 31 is the length along that path, and the cross-sectional area is the area of ​​a cross section perpendicular to that path.

[0045] The second ground connection path Rg2 includes a second opposing electrode 22 and a second conductor line 32 .

[0046] The second opposing electrode 22 is capacitively coupled to one of the second external electrodes P2a, thereby forming a capacitance in the second ground connection path Rg2. The second opposing electrode 22 is disposed so as to face a portion of one of the second external electrodes P2a via the insulating layer 15. In this example, the second opposing electrode 22 faces one of the second external electrodes P2a (i.e., the top surface electrode portion t2a) formed on the top surface 19. In other words, the top surface electrode portion t2a and the second opposing electrode 22 are electrodes for forming a second capacitance in the second ground connection path Rg2. The top surface electrode portion t2a and the second opposing electrode 22 facing each other form a second capacitor C2.

[0047] The second conductor line 32 is a line for forming a second inductance in the second ground connection path Rg2. The second conductor line 32 is formed by a plurality of wirings, land electrodes, via conductors, etc., and electrically connects the second opposing electrode 22 and the second ground electrode G2. The second conductor line 32 extends along a path from the second opposing electrode 22 to the second ground electrode G2. The second conductor line 32 has a predetermined length, cross-sectional area, and shape, and forms a second inductor L2. The length of the second conductor line 32 is the length along that path, and the cross-sectional area is the area of ​​a cross section perpendicular to that path.

[0048] The third ground connection path Rg3 includes a third opposing electrode 23 and a third conductor line 33 .

[0049] The third opposing electrode 23 is capacitively coupled to the other first external electrode P1b, thereby forming a capacitance in the third ground connection path Rg3. The third opposing electrode 23 is disposed so as to face a portion of the other first external electrode P1b via the insulating layer 15. In this example, the third opposing electrode 23 faces the other first external electrode P1b (i.e., the bottom surface electrode portion b1b) formed on the bottom surface 18. In other words, the bottom surface electrode portion b1b and the third opposing electrode 23 are electrodes for forming a third capacitance in the third ground connection path Rg3. The bottom surface electrode portion b1b and the third opposing electrode 23 facing each other form a third capacitor C3.

[0050] The third conductor line 33 is a line for forming a third inductance in the third ground connection path Rg3. The third conductor line 33 is formed by a plurality of wirings, land electrodes, via conductors, etc., and electrically connects the third opposing electrode 23 and the first ground electrode G1. The third conductor line 33 extends along a path from the third opposing electrode 23 to the first ground electrode G1. The third conductor line 33 has a predetermined length, cross-sectional area, and shape, and forms a third inductor L3. The length of the third conductor line 33 is the length along that path, and the cross-sectional area is the area of ​​a cross section perpendicular to that path.

[0051] The fourth ground connection path Rg4 includes a fourth opposing electrode 24 and a fourth conductor line 34 .

[0052] The fourth opposing electrode 24 is capacitively coupled to the other second external electrode P2b, thereby forming a capacitance in the fourth ground connection path Rg4. The fourth opposing electrode 24 is disposed so as to face a portion of the other second external electrode P2b via the insulating layer 15. In this example, the fourth opposing electrode 24 faces the other second external electrode P2b (i.e., the bottom electrode portion b2b) formed on the bottom surface 18. In other words, the bottom electrode portion b2b and the fourth opposing electrode 24 are electrodes for forming a fourth capacitance in the fourth ground connection path Rg4. The bottom electrode portion b2b and the fourth opposing electrode 24 face each other, thereby forming a fourth capacitor C4.

[0053] The fourth conductor line 34 is a line for forming a fourth inductance in the fourth ground connection path Rg4. The fourth conductor line 34 is formed by a plurality of wirings, land electrodes, via conductors, etc., and electrically connects the fourth opposing electrode 24 and the second ground electrode G2. The fourth conductor line 34 extends along a path from the fourth opposing electrode 24 to the second ground electrode G2. The fourth conductor line 34 has a predetermined length, cross-sectional area, and shape, and forms a fourth inductor L4. The length of the fourth conductor line 34 is the length along that path, and the cross-sectional area is the area of ​​a cross section perpendicular to that path.

[0054] More specifically, the first ground connection path Rg1, the second ground connection path Rg2, the third ground connection path Rg3, and the fourth ground connection path Rg4 are formed from metal materials such as counter electrodes, wiring, land electrodes, via conductors, and connection electrodes, which are shown below.

[0055] The first ground connection path Rg1 has a first opposing electrode 21 that faces one of the first external electrodes P1a, and is formed by connecting a land h1 to the first opposing electrode 21 by a via conductor, connecting a connection electrode i1 to the land h1 by a wiring, and connecting the connection electrode i1 to the first ground electrode G1. The first conductor line 31 is formed by the via conductor, the land h1, the wiring, and the connection electrode i1 that are located between the first opposing electrode 21 and the first ground electrode G1.

[0056] The second ground connection path Rg2 has a second opposing electrode 22 that faces one of the second external electrodes P2a, and is formed by connecting a land h2 to the second opposing electrode 22 by a via conductor, connecting a connection electrode i2 to the land h2 by a wiring, and connecting the connection electrode i2 to the second ground electrode G2. The second conductor line 32 is formed by the via conductor, the land h2, the wiring, and the connection electrode i2 that are located between the second opposing electrode 22 and the second ground electrode G2.

[0057] The third ground connection path Rg3 has a third opposing electrode 23 that faces the other first external electrode P1b, and is formed by connecting a land h3 to the third opposing electrode 23 by a via conductor, connecting a connection electrode i1 to the land h3 by a wiring, and connecting the connection electrode i1 to the first ground electrode G1. The third conductor line 33 is formed by the via conductor, the land h3, the wiring, and the connection electrode i1 that are located between the third opposing electrode 23 and the first ground electrode G1.

[0058] The fourth ground connection path Rg4 has a fourth opposing electrode 24 that faces the other second external electrode P2b, and is formed by connecting a land h4 to the fourth opposing electrode 24 by a via conductor, connecting a connection electrode i2 to the land h4 by a wiring, and connecting the connection electrode i2 to the second ground electrode G2. The fourth conductor line 34 is formed by the via conductor, the land h4, the wiring, and the connection electrode i2 that are located between the fourth opposing electrode 24 and the second ground electrode G2.

[0059] The first ground connection path Rg1 and the second ground connection path Rg2 are arranged symmetrically with respect to the reference plane sf (see FIG. 4 ), which is the central plane of the third side surface 13 and the fourth side surface 14 that face away from the second direction D2. That is, the first ground connection path Rg1 and the second ground connection path Rg2 are arranged symmetrically with respect to the reference plane sf.

[0060] For example, the opposing area between the top surface electrode portion t1a and the first opposing electrode 21 is the same as the opposing area between the top surface electrode portion t2a and the second opposing electrode 22. That is, the area of ​​the opposing portions of the top surface electrode portion t1a and the first opposing electrode 21 is the same as the area of ​​the opposing portions of the top surface electrode portion t2a and the second opposing electrode 22. The gap between the top surface electrode portion t1a and the first opposing electrode 21 is the same as the gap between the top surface electrode portion t2a and the second opposing electrode 22. The cross-sectional area of ​​the first conductor line 31 is the same as the cross-sectional area of ​​the second conductor line 32, and the length of the first conductor line 31 is the same as the length of the second conductor line 32. That is, the first capacitor C1 and the second capacitor C2 have the same capacitance, and the first inductor L1 and the second inductor L2 have the same inductance.

[0061] The third ground connection path Rg3 and the fourth ground connection path Rg4 are arranged symmetrically with respect to the reference plane sf, which is the central plane of the third side surface 13 and the fourth side surface 14 facing away from the second direction D2. In other words, the third ground connection path Rg3 and the fourth ground connection path Rg4 are arranged symmetrically with respect to the reference plane sf.

[0062] For example, the opposing area between bottom electrode portion b1b and third opposing electrode 23 is the same as the opposing area between bottom electrode portion b2b and fourth opposing electrode 24. In other words, the area of ​​the opposing portions of bottom electrode portion b1b and third opposing electrode 23 is the same as the area of ​​the opposing portions of bottom electrode portion b2b and fourth opposing electrode 24, and the gap between bottom electrode portion b1b and third opposing electrode 23 is the same as the gap between bottom electrode portion b2b and fourth opposing electrode 24. Furthermore, the cross-sectional area of ​​third conductor line 33 is the same as the cross-sectional area of ​​fourth conductor line 34, and the length of third conductor line 33 is the same as the length of fourth conductor line 34. In other words, third capacitor C3 and fourth capacitor C4 have the same capacitance, and third inductor L3 and fourth inductor L4 have the same inductance.

[0063] Furthermore, in this embodiment, the following relationships are satisfied. For example, the opposing area between the top surface electrode portion t1a and the first opposing electrode 21 is the same as the opposing area between the bottom surface electrode portion b1b and the third opposing electrode 23. In other words, the area of ​​the opposing portions of the top surface electrode portion t1a and the first opposing electrode 21 is the same as the area of ​​the opposing portions of the bottom surface electrode portion b1b and the third opposing electrode 23. The gap between the top surface electrode portion t1a and the first opposing electrode 21 is the same as the gap between the bottom surface electrode portion b1b and the third opposing electrode 23. Furthermore, the cross-sectional area of ​​the first conductor line 31 is the same as the cross-sectional area of ​​the third conductor line 33, and the length of the first conductor line 31 is the same as the length of the third conductor line 33. In other words, the first capacitor C1 and the third capacitor C3 have the same capacitance, and the first inductor L1 and the third inductor L3 have the same inductance.

[0064] The opposing area of ​​the top electrode portion t2a and the second opposing electrode 22 is the same as the opposing area of ​​the bottom electrode portion b2b and the fourth opposing electrode 24. That is, the area of ​​the opposing portions of the top electrode portion t2a and the second opposing electrode 22 is the same as the area of ​​the opposing portions of the bottom electrode portion b2b and the fourth opposing electrode 24, and the gap between the top electrode portion t2a and the second opposing electrode 22 is the same as the gap between the bottom electrode portion b2b and the fourth opposing electrode 24. The cross-sectional area of ​​the second conductor line 32 is the same as the cross-sectional area of ​​the fourth conductor line 34, and the length of the second conductor line 32 is the same as the length of the fourth conductor line 34. That is, the second capacitor C2 and the fourth capacitor C4 have the same capacitance, and the second inductor L2 and the fourth inductor L4 have the same inductance.

[0065] As described above, the stacked device 1 of this embodiment has a first signal path R1 connecting one first external electrode P1a and the other first external electrode P1b, a second signal path R2 connecting one second external electrode P2a and the other second external electrode P2b, a first ground connection path Rg1 connecting one first external electrode P1a and the first ground electrode G1, and a second ground connection path Rg2 connecting one second external electrode P2a and the second ground electrode G2.

[0066] The first signal path R1 has a first coil 51, and the second signal path R2 has a second coil 52 which constitutes a common mode choke coil 50 together with the first coil 51.

[0067] The first ground connection path Rg1 includes a first opposing electrode 21 that is capacitively coupled to one of the first external electrodes P1a, and a first conductor line 31 that electrically connects the first opposing electrode 21 and the first ground electrode G1. The second ground connection path Rg2 includes a second opposing electrode 22 that is capacitively coupled to one of the second external electrodes P2a, and a second conductor line 32 that electrically connects the second opposing electrode 22 and the second ground electrode G2.

[0068] According to this configuration, an LC resonant circuit is formed in each of the first ground connection path Rg1 and the second ground connection path Rg2. Therefore, when a differential signal is transmitted through the first signal path R1 and the second signal path R2, each LC resonant circuit resonates at a predetermined frequency. By each LC resonant circuit resonating at a predetermined frequency, common mode noise of the predetermined frequency can be diverted to ground. This allows common mode noise of a predetermined frequency different from the specific frequency to be further eliminated in addition to the specific frequency eliminated by the common mode choke coil 50, thereby widening the stop band that prevents common mode signals from passing through.

[0069] The laminated device 1 also has a third ground connection path Rg3 connecting the other first external electrode P1b and the first ground electrode G1, and a fourth ground connection path Rg4 connecting the other second external electrode P2b and the second ground electrode G2.

[0070] The third ground connection path Rg3 includes a third opposing electrode 23 that is capacitively coupled to the other first external electrode P1b, and a third conductor line 33 that electrically connects the third opposing electrode 23 and the first ground electrode G1. The fourth ground connection path Rg4 includes a fourth opposing electrode 24 that is capacitively coupled to the other second external electrode P2b, and a fourth conductor line 34 that electrically connects the fourth opposing electrode 24 and the second ground electrode G2.

[0071] According to this configuration, an LC resonant circuit is formed in each of the third ground connection path Rg3 and the fourth ground connection path Rg4. Therefore, when a differential signal is transmitted to the first signal path R1 and the second signal path R2, each LC resonant circuit resonates at a predetermined frequency. By each LC resonant circuit resonating at a predetermined frequency, common mode noise of the predetermined frequency can be diverted to ground. This allows common mode noise of a predetermined frequency different from the specific frequency to be further eliminated in addition to the specific frequency eliminated by the common mode choke coil 50, thereby widening the stop band that prevents common mode signals from passing through.

[0072] Although the above example shows that the multilayer device 1 has one first ground connection path Rg1 and one second ground connection path Rg2, the present invention is not limited to this. Also, the above example shows that the multilayer device 1 has one third ground connection path Rg3 and one fourth ground connection path Rg4, but the present invention is not limited to this.

[0073] 5B is a diagram showing an equivalent circuit of another multilayer device 1D according to the first embodiment. The multilayer device 1D shown in FIG. 5B includes a plurality of first ground connection paths Rg1 and Rg5, a plurality of second ground connection paths Rg2 and Rg6, a plurality of third ground connection paths Rg3 and Rg7, and a plurality of fourth ground connection paths Rg4 and Rg8. The first ground connection path Rg5 is configured with an LC resonant circuit LC5 including an inductor L5 and a capacitor C5 connected in the same manner as the first LC resonant circuit LC1 including the first inductor L1 and the first capacitor C1 of the first ground connection path Rg1, and functions in the same manner. The second ground connection path Rg6 is configured with an LC resonant circuit LC6 including an inductor L6 and a capacitor C6 connected in the same manner as the second LC resonant circuit LC2 including the second inductor L2 and the second capacitor C2 of the second ground connection path Rg2, and functions in the same manner. The third ground connection path Rg7 is configured with an LC resonant circuit LC7 including an inductor L7 and a capacitor C7 connected in the same manner as the third LC resonant circuit LC3 including the third inductor L3 and the first capacitor C3 of the third ground connection path Rg3, and functions in the same manner. The fourth ground connection path Rg8 is configured with an LC resonant circuit LC8 including an inductor L8 and a capacitor C8 connected in the same manner as the fourth LC resonant circuit LC4 including the fourth inductor L4 and the fourth capacitor C4 of the fourth ground connection path Rg4, and functions in the same manner.

[0074] 6 and 7, a multilayer device 1A according to a modification of the first embodiment will be described. In this modification, an example will be described in which the multilayer device 1A is provided with a line for checking continuity between the ground electrode and the internal conductor.

[0075] FIG. 6 is a diagram showing an equivalent circuit of a stacked device 1A according to a modification of the first embodiment.

[0076] As shown in FIG. 6 , the multilayer device 1A of the modified example includes, similarly to the multilayer device 1 of the first embodiment, one first external electrode P1a and the other first external electrode P1b, one second external electrode P2a and the other second external electrode P2b, a first ground electrode G1 and a second ground electrode G2, a first signal path R1, a second signal path R2, a first ground connection path Rg1, a second ground connection path Rg2, a third ground connection path Rg3, and a fourth ground connection path Rg4.

[0077] Furthermore, the multilayer device 1A of the modified example has a plurality of continuity check lines 35 a, 35 b for checking the continuity between the first ground electrode G1 and the internal conductor or the continuity between the second ground electrode G2 and the internal conductor. The plurality of continuity check lines 35 a, 35 b are provided to electrically connect the first ground electrode G1 and the second ground electrode G2, respectively.

[0078] Fig. 7 is a diagram showing the internal conductors of the multilayer device 1A. In Fig. 7, the insulators 10, external electrodes, and ground electrodes of the multilayer device 1A are indicated by dashed lines, and the internal conductors are indicated by solid lines.

[0079] 7 , the multilayer device 1A of the modified example includes an insulator 10, one first external electrode P1a and the other first external electrode P1b, one second external electrode P2a and the other second external electrode P2b, a first ground electrode G1 and a second ground electrode G2, and a plurality of paths provided inside the insulator 10. The plurality of paths includes a first signal path R1, a second signal path R2, a first ground connection path Rg1, a second ground connection path Rg2, a third ground connection path Rg3, and a fourth ground connection path Rg4.

[0080] The multilayer device 1A of the modified example further includes two continuity check lines 35a, 35b as the multiple paths. One end of the continuity check line 35a is connected to the first conductor line 31, and the other end of the continuity check line 35a is connected to the second conductor line 32. One end of the continuity check line 35b is connected to the third conductor line 33, and the other end of the continuity check line 35b is connected to the fourth conductor line 34. This configuration makes it possible to check the continuity between the first ground electrode G1 and the connection electrode i1 or the continuity between the second ground electrode G2 and the connection electrode i2.

[0081] For example, in the stacked device 1 of embodiment 1, the first capacitor C1 is provided in the first ground connection path Rg1, so it is difficult to confirm whether the first ground electrode G1 and the connection electrode i1 are electrically connected by checking the continuity between the external electrodes.

[0082] In contrast, in the multilayer device 1A of the modified example, the first ground electrode G1 and the second ground electrode G2 are electrically connected, making it possible to check the continuity between the ground electrodes and the connection electrodes. For example, the continuity check can be performed by contacting a measurement probe with each of the first ground electrode G1 and the second ground electrode G2. If the continuity check is successful, it can be determined that the first ground electrode G1 and the connection electrode i1 are electrically connected, and that the second ground electrode G2 and the connection electrode i2 are electrically connected. On the other hand, if the continuity check is unsuccessful, it can be inferred that the first ground electrode G1 and the connection electrode i1 are not electrically connected, and / or the second ground electrode G2 and the connection electrode i2 are not electrically connected.

[0083] In addition, in order to reduce the influence of the continuity check lines 35a, 35b on the electromagnetic coupling of the common mode choke coil 50, it is desirable to arrange the continuity check lines 35a, 35b in positions that do not overlap the common mode choke coil 50 when viewed from the stacking direction (third direction D3). In this example, when viewed from the stacking direction (third direction D3), each of the multiple continuity check lines 35a, 35b is provided outside the common mode choke coil 50. In other words, when viewed from the stacking direction (third direction D3), each of the multiple continuity check lines 35a, 35b does not overlap the common mode choke coil 50.

[0084] [Effects, etc.] The effects of the modified multilayer device 1A having the above configuration will be described in comparison with the multilayer device 101 of the comparative example.

[0085] Fig. 8 is a diagram showing an equivalent circuit of the comparative example stacked device 101. Fig. 9 is a diagram showing the first signal path R1 and the second signal path R2 of the comparative example stacked device 101.

[0086] The multilayer device 101 of the comparative example is the same as the multilayer device 1A of the modified example of the first embodiment in that it includes a first signal path R1 connecting one first external electrode P1a and the other first external electrode P1b, and a second signal path R2 connecting one second external electrode P2a and the other second external electrode P2b. On the other hand, the multilayer device 101 of the comparative example differs from the multilayer device 1A of the modified example of the first embodiment in that it does not include the first ground electrode G1 and the second ground electrode G2, and the first ground connection path Rg1 and the second ground connection path Rg2. The multilayer device 101 of the comparative example also differs from the multilayer device 1A of the modified example of the first embodiment in that it does not include the continuity check lines 35a and 35b.

[0087] Fig. 10 is a diagram showing the common-mode signal transmission characteristics of a comparative multilayer device 101. Fig. 11 is a diagram showing the common-mode signal transmission characteristics of a multilayer device 1A according to a modified example of the first embodiment. These diagrams show S-parameters (Scc21) that are characteristics when in-phase high-speed, high-frequency signals are input to one first external electrode P1a and one second external electrode P2a. The first ground electrode G1 and the second ground electrode G2 of the multilayer device 1A according to the modified example of the first embodiment are set to ground potential.

[0088] In this example, if Scc21 is smaller than −10 dB, it is determined that the common mode signal is sufficiently attenuated.

[0089] As shown in FIG. 10, the stacked device 101 of the comparative example can block the passage of common mode signals in the frequency range of 1.34 GHz to 9.04 GHz (7.7 GHz bandwidth).

[0090] 11 , in the multilayer device 1A of the modified example, an attenuation pole is formed by the LC resonant circuit on the higher frequency side of the attenuation band formed by the common mode choke coil 50. Therefore, the multilayer device 1A can block the passage of common mode signals in the frequency range of 2.13 GHz to 20 GHz or more (a bandwidth of 17.87 GHz or more). In this way, the multilayer device 1A of the modified example can widen the stop band that blocks the passage of common mode signals compared to the multilayer device 101 of the comparative example.

[0091] The frequencies of the attenuation poles formed by the LC resonant circuits can be shifted to higher or lower frequencies by changing the resonant frequencies of the first LC resonant circuit LC1, the second LC resonant circuit LC2, the third LC resonant circuit LC3, and the fourth LC resonant circuit LC4, which makes it possible to change the stop band of the common mode signal according to the required specifications of the multilayer device 1A.

[0092] Furthermore, in the multilayer device 1A, an LC resonant circuit is formed on each of the signal input side and the signal output side, which are both sides of the common mode choke coil 50. For example, if an LC resonant circuit is formed on only one side of the common mode choke coil 50, Scd12 and Scd21, which represent components of a differential mode signal converted into a common mode signal through the common mode choke coil 50, will exhibit different characteristics. In contrast, if an LC resonant circuit is formed on both sides of the common mode choke coil 50 as in the multilayer device 1A, it is possible to make Scd12 and Scd21 have approximately the same characteristics. Similarly, in the multilayer device 1, it is possible to make Scd12 and Scd21 have approximately the same characteristics.

[0093] Second Embodiment [Structure of Stacked Device] A stacked device 1B according to a second embodiment will be described with reference to Figures 12 to 15. In the stacked device 1 according to the first embodiment, the multiple insulating layers 15 are stacked vertically (vertically stacked), whereas in the stacked device 1B according to the second embodiment, the multiple insulating layers 15 are stacked horizontally (horizontally stacked).

[0094] The equivalent circuit of the stacked device 1B according to the second embodiment is the same as that of the first embodiment, and therefore a description of the equivalent circuit will be omitted.

[0095] Fig. 12 is a perspective view of a multilayer device 1B according to the second embodiment. Fig. 13 is a view showing internal conductors of the multilayer device 1B. Fig. 14 is a view of the multilayer device 1B seen from the second side surface 12 side. Fig. 15 is a view of the multilayer device 1B seen from the third side surface 13 side. In Figs. 13 to 15, the internal conductors of the multilayer device 1B are shown by solid lines, and the insulators 10, external electrodes, and ground electrodes are shown by dashed lines.

[0096] The stacked device 1B shown in Figures 12 to 15 includes an insulator 10 formed from an insulating material, one first external electrode P1a and the other first external electrode P1b provided on the outer surface of the insulator 10, one second external electrode P2a and the other second external electrode P2b provided on the outer surface of the insulator 10, a first ground electrode G1 and a second ground electrode G2 provided on the outer surface of the insulator 10, and a plurality of paths provided inside the insulator 10.

[0097] Insulator 10 is formed, for example, by stacking multiple insulating layers 15 (see FIG. 15 ). Insulator 10 has a rectangular parallelepiped shape and has a bottom surface 18, a top surface 19 facing away from bottom surface 18, and multiple side surfaces connecting bottom surface 18 and top surface 19. The multiple side surfaces include a first side surface 11 and a second side surface 12 facing away from each other, and a third side surface 13 and a fourth side surface 14 facing away from each other.

[0098] Here, the direction in which the first side surface 11 and the second side surface 12 face each other is called the first direction D1, the direction in which the third side surface 13 and the fourth side surface 14 face each other is called the second direction D2, and the direction in which the bottom surface 18 and the top surface 19 face each other is called the third direction D3. In the second embodiment, the stacking direction in which the multiple insulating layers 15 are stacked is the same as the first direction D1. The stacking direction is the same as the direction in which the coil axis of the common mode choke coil 50 extends.

[0099] The first external electrode P1a and the second external electrode P2a are each provided on a part of a first side surface 11, which is the outer surface of the insulator 10. The other first external electrode P1b and the other second external electrode P2b are each provided on a part of a second side surface 12, which is the outer surface of the insulator 10. The first ground electrode G1 is provided on a part of a third side surface 13, which is the outer surface of the insulator 10. The second ground electrode G2 is provided on a part of a fourth side surface 14, which is the outer surface of the insulator 10.

[0100] These external electrodes and ground electrodes are also provided on parts of the bottom surface 18 and the top surface 19. For example, the first external electrode P1a, the first external electrode P1b, the second external electrode P2a, the second external electrode P2b, the first ground electrode G1, and the second ground electrode G2 are also formed on parts of the top surface 19 and the bottom surface 18, respectively. The first external electrode P1a, the second external electrode P2a, the first external electrode P1b, the second external electrode P2b, the first ground electrode G1, and the second ground electrode G2 are each provided at different positions on the outer surface of the insulator 10. The cross section of each external electrode and each ground electrode perpendicular to the width direction of the electrode has a square bracket ([, ]) shape.

[0101] One first external electrode P1a is formed by a side electrode portion s1a, a bottom electrode portion b1a, and a top electrode portion t1a. The other first external electrode P1b is formed by a side electrode portion s1b, a bottom electrode portion b1b, and a top electrode portion t1b. One second external electrode P2a is formed by a side electrode portion s2a, a bottom electrode portion b2a, and a top electrode portion t2a. The other second external electrode P2b is formed by a side electrode portion s2b, a bottom electrode portion b2b, and a top electrode portion t2b.

[0102] The multiple paths inside the insulator 10 include a first signal path R1, a second signal path R2, a first ground connection path Rg1, a second ground connection path Rg2, a third ground connection path Rg3, and a fourth ground connection path Rg4.

[0103] One end of the first signal path R1 is connected to one of the first external electrodes P1a, and the other end of the first signal path R1 is connected to the other first external electrode P1b. The first signal path R1 has a first coil 51, which is composed of two spiral coils 51a and 51b.

[0104] One end of the second signal path R2 is connected to one second external electrode P2a, and the other end of the second signal path R2 is connected to the other second external electrode P2b. The second signal path R2 has a first coil 51 and a second coil 52 that constitutes a common mode choke coil 50. The second coil 52 is composed of two spiral coils 52a and 52b.

[0105] The common mode choke coil 50 located on the first signal path R1 and the second signal path R2 is composed of multiple common mode choke coils 50a, 50b. Of the multiple common mode choke coils 50, the common mode choke coil 50a is formed by coils 51a and 52a, and the common mode choke coil 50b is formed by coils 51b and 52b. The multiple common mode choke coils 50a, 50b are arranged along the stacking direction (first direction D1) in which the multiple insulating layers 15 are stacked.

[0106] The first signal path R1 and the second signal path R2 have the same path length and are formed of metal materials such as connection electrodes, wiring, land electrodes, via conductors, and coils.

[0107] 13 are arranged outside the common mode choke coil 50 when viewed from the stacking direction (first direction D1). In other words, the third ground connection path Rg3 and the fourth ground connection path Rg4 do not overlap with the common mode choke coil 50 when viewed from the stacking direction (first direction D1).

[0108] The first ground connection path Rg1 includes a first opposing electrode 21 and a first conductor line 31 .

[0109] The first opposing electrode 21 is capacitively coupled to one of the first external electrodes P1a, thereby forming a capacitance in the first ground connection path Rg1. The first opposing electrode 21 is disposed so as to face a portion of one of the first external electrodes P1a via the insulating layer 15. In this example, the first opposing electrode 21 faces one of the first external electrodes P1a (i.e., the side electrode portion s1a) formed on the first side surface 11. In other words, the side electrode portion s1a and the first opposing electrode 21 are electrodes for forming a first capacitance in the first ground connection path Rg1. The side electrode portion s1a and the first opposing electrode 21 face each other, thereby forming a first capacitor C1.

[0110] The first conductor line 31 is a line for forming a first inductance in the first ground connection path Rg1. The first conductor line 31 is formed by a plurality of wirings, land electrodes, via conductors, etc., and electrically connects the first opposing electrode 21 and the first ground electrode G1. The first conductor line 31 has a predetermined length, cross-sectional area, and shape and forms a first inductor L1.

[0111] The second ground connection path Rg2 includes a second opposing electrode 22 and a second conductor line 32 .

[0112] The second opposing electrode 22 is capacitively coupled to one of the second external electrodes P2a, thereby forming a capacitance in the second ground connection path Rg2. The second opposing electrode 22 is disposed so as to face a portion of one of the second external electrodes P2a via the insulating layer 15. In this example, the second opposing electrode 22 faces one of the second external electrodes P2a (i.e., the side electrode portion s2a) formed on the first side surface 11. In other words, the side electrode portion s2a and the second opposing electrode 22 are electrodes for forming a second capacitance in the second ground connection path Rg2. The side electrode portion s2a and the second opposing electrode 22 facing each other form a second capacitor C2.

[0113] The second conductor line 32 is a line for forming a second inductance in the second ground connection path Rg2. The second conductor line 32 is formed by a plurality of wirings, land electrodes, via conductors, etc., and electrically connects the second opposing electrode 22 and the second ground electrode G2. The second conductor line 32 has a predetermined length, cross-sectional area, and shape, and forms a second inductor L2.

[0114] The third ground connection path Rg3 includes a third opposing electrode 23 and a third conductor line 33 .

[0115] The third opposing electrode 23 is capacitively coupled to the other first external electrode P1b, thereby forming a capacitance in the third ground connection path Rg3. The third opposing electrode 23 is disposed so as to face a portion of the other first external electrode P1b via the insulating layer 15. In this example, the third opposing electrode 23 faces the other first external electrode P1b (i.e., the side electrode portion s1b) formed on the second side surface 12. In other words, the side electrode portion s1b and the third opposing electrode 23 are electrodes for forming a third capacitance in the third ground connection path Rg3. The side electrode portion s1b and the third opposing electrode 23 facing each other form a third capacitor C3.

[0116] The third conductor line 33 is a line for forming a third inductance in the third ground connection path Rg3. The third conductor line 33 is formed by a plurality of wirings, land electrodes, via conductors, etc., and electrically connects the third opposing electrode 23 and the first ground electrode G1. The third conductor line 33 has a predetermined length, cross-sectional area, and shape and forms a third inductor L3.

[0117] The fourth ground connection path Rg4 includes a fourth opposing electrode 24 and a fourth conductor line 34 .

[0118] The fourth opposing electrode 24 is capacitively coupled to the other second external electrode P2b, thereby forming a capacitance in the fourth ground connection path Rg4. The fourth opposing electrode 24 is disposed so as to face a portion of the other second external electrode P2b via the insulating layer 15. In this example, the fourth opposing electrode 24 faces the other second external electrode P2b (i.e., the side electrode portion s2b) formed on the second side surface 12. In other words, the side electrode portion s2b and the fourth opposing electrode 24 are electrodes for forming a fourth capacitance in the fourth ground connection path Rg4, and the side electrode portion s2b and the fourth opposing electrode 24 facing each other form a fourth capacitor C4.

[0119] The fourth conductor line 34 is a line for forming a fourth inductance in the fourth ground connection path Rg4. The fourth conductor line 34 is formed by a plurality of wirings, land electrodes, via conductors, etc., and electrically connects the fourth opposing electrode 24 and the second ground electrode G2. The fourth conductor line 34 has a predetermined length, cross-sectional area, and shape and forms a fourth inductor L4.

[0120] The first ground connection path Rg1 and the second ground connection path Rg2 are arranged symmetrically with respect to the reference plane sf (see FIG. 14 ), which is the central plane of the third side surface 13 and the fourth side surface 14 facing away from the second direction D2. That is, the first ground connection path Rg1 and the second ground connection path Rg2 are arranged symmetrically with respect to the reference plane sf.

[0121] For example, the opposing area of ​​the side electrode portion s1a and the first opposing electrode 21 is the same as the opposing area of ​​the side electrode portion s2a and the second opposing electrode 22. In other words, the area of ​​the opposing portions of the side electrode portion s1a and the first opposing electrode 21 is the same as the area of ​​the opposing portions of the side electrode portion s2a and the second opposing electrode 22. The gap between the side electrode portion s1a and the first opposing electrode 21 is the same as the gap between the side electrode portion s2a and the second opposing electrode 22. Furthermore, the cross-sectional area of ​​the first conductor line 31 is the same as the cross-sectional area of ​​the second conductor line 32, and the length of the first conductor line 31 is the same as the length of the second conductor line 32. In other words, the first capacitor C1 and the second capacitor C2 have the same capacitance, and the first inductor L1 and the second inductor L2 have the same inductance.

[0122] The third ground connection path Rg3 and the fourth ground connection path Rg4 are arranged symmetrically with respect to the reference plane sf, which is the central plane of the third side surface 13 and the fourth side surface 14 facing away from the second direction D2. In other words, the third ground connection path Rg3 and the fourth ground connection path Rg4 are arranged symmetrically with respect to the reference plane sf.

[0123] For example, the opposing area between side electrode portion s1b and third opposing electrode 23 is the same as the opposing area between side electrode portion s2b and fourth opposing electrode 24. In other words, the area of ​​the opposing portions of side electrode portion s1b and third opposing electrode 23 is the same as the area of ​​the opposing portions of side electrode portion s2b and fourth opposing electrode 24, and the gap between side electrode portion s1b and third opposing electrode 23 is the same as the gap between side electrode portion s2b and fourth opposing electrode 24. Furthermore, the cross-sectional area of ​​third conductor line 33 is the same as the cross-sectional area of ​​fourth conductor line 34, and the length of third conductor line 33 is the same as the length of fourth conductor line 34. In other words, third capacitor C3 and fourth capacitor C4 have the same capacitance value, and third inductor L3 and fourth inductor L4 have the same inductance value.

[0124] Furthermore, in this embodiment, the following relationship is satisfied: The first ground connection path Rg1 and the third ground connection path Rg3 are arranged symmetrically with respect to the reference plane, which is the central plane of the first side surface 11 and the second side surface 12 facing away from each other in the first direction D1. That is, the first ground connection path Rg1 and the third ground connection path Rg3 are arranged symmetrically with respect to each other with respect to the reference plane. For example, the opposing area between the side electrode portion s1a and the first opposing electrode 21 is the same as the opposing area between the side electrode portion s1b and the third opposing electrode 23. That is, the area of ​​the opposing portions of the side electrode portion s1a and the first opposing electrode 21 is the same as the area of ​​the opposing portions of the side electrode portion s1b and the third opposing electrode 23. Furthermore, the gap between the side electrode portion s1a and the first opposing electrode 21 is the same as the gap between the side electrode portion s1b and the third opposing electrode 23. The cross-sectional area of ​​the first conductor line 31 is the same as the cross-sectional area of ​​the third conductor line 33, and the length of the first conductor line 31 is the same as the length of the third conductor line 33. In other words, the first capacitor C1 and the third capacitor C3 have the same capacitance value, and the first inductor L1 and the third inductor L3 have the same inductance value.

[0125] The second ground connection path Rg2 and the fourth ground connection path Rg4 are arranged symmetrically with respect to the reference plane, which is the central plane of the first side surface 11 and the second side surface 12 facing away from each other in the first direction D1. That is, the second ground connection path Rg2 and the fourth ground connection path Rg4 are arranged symmetrically with respect to each other with respect to the reference plane. For example, the opposing area of ​​the side electrode portion s2a and the second opposing electrode 22 is the same as the opposing area of ​​the side electrode portion s2b and the fourth opposing electrode 24. That is, the area of ​​the opposing portions of the side electrode portion s2a and the second opposing electrode 22 is the same as the area of ​​the opposing portions of the side electrode portion s2b and the fourth opposing electrode 24. The gap between the side electrode portion s2a and the second opposing electrode 22 is the same as the gap between the side electrode portion s2b and the fourth opposing electrode 24. The cross-sectional area of ​​the second conductor line 32 is the same as the cross-sectional area of ​​the fourth conductor line 34, and the length of the second conductor line 32 is the same as the length of the fourth conductor line 34. In other words, the second capacitor C2 and the fourth capacitor C4 have the same capacitance value, and the second inductor L2 and the fourth inductor L4 have the same inductance value.

[0126] As described above, the stacked device 1B of this embodiment has a first signal path R1 connecting one first external electrode P1a and the other first external electrode P1b, a second signal path R2 connecting one second external electrode P2a and the other second external electrode P2b, a first ground connection path Rg1 connecting one first external electrode P1a and the first ground electrode G1, and a second ground connection path Rg2 connecting one second external electrode P2a and the second ground electrode G2.

[0127] The first signal path R1 has a first coil 51, and the second signal path R2 has a second coil 52 which constitutes a common mode choke coil 50 together with the first coil 51.

[0128] The first ground connection path Rg1 includes a first opposing electrode 21 that is capacitively coupled to one of the first external electrodes P1a, and a first conductor line 31 that electrically connects the first opposing electrode 21 and the first ground electrode G1. The second ground connection path Rg2 includes a second opposing electrode 22 that is capacitively coupled to one of the second external electrodes P2a, and a second conductor line 32 that electrically connects the second opposing electrode 22 and the second ground electrode G2.

[0129] According to this configuration, an LC resonant circuit is formed in each of the first ground connection path Rg1 and the second ground connection path Rg2. Therefore, when a differential signal is transmitted through the first signal path R1 and the second signal path R2, each LC resonant circuit resonates at a predetermined frequency. By each LC resonant circuit resonating at a predetermined frequency, common mode noise of the predetermined frequency can be diverted to ground. This allows common mode noise of a predetermined frequency different from the specific frequency to be further eliminated in addition to the specific frequency eliminated by the common mode choke coil 50, thereby widening the stop band that prevents common mode signals from passing through.

[0130] The laminated device 1B also has a third ground connection path Rg3 that connects the other first external electrode P1b and the first ground electrode G1, and a fourth ground connection path Rg4 that connects the other second external electrode P2b and the second ground electrode G2.

[0131] The third ground connection path Rg3 includes a third opposing electrode 23 that is capacitively coupled to the other first external electrode P1b, and a third conductor line 33 that electrically connects the third opposing electrode 23 and the first ground electrode G1. The fourth ground connection path Rg4 includes a fourth opposing electrode 24 that is capacitively coupled to the other second external electrode P2b, and a fourth conductor line 34 that electrically connects the fourth opposing electrode 24 and the second ground electrode G2.

[0132] According to this configuration, an LC resonant circuit is formed in each of the third ground connection path Rg3 and the fourth ground connection path Rg4. Therefore, when a differential signal is transmitted to the first signal path R1 and the second signal path R2, each LC resonant circuit resonates at a predetermined frequency. By each LC resonant circuit resonating at a predetermined frequency, common mode noise of the predetermined frequency can be diverted to ground. This allows common mode noise of a predetermined frequency different from the specific frequency to be further eliminated in addition to the specific frequency eliminated by the common mode choke coil 50, thereby widening the stop band that prevents common mode signals from passing through.

[0133] 16 to 18, a multilayer device 1C according to a modification of the second embodiment will be described. In this modification, an example will be described in which the multilayer device 1C is provided with a line for checking continuity between the ground electrode and the internal conductor.

[0134] FIG. 16 is a diagram showing an equivalent circuit of a stacked device 1C according to a modification of the second embodiment.

[0135] As shown in FIG. 16 , similar to the laminated device 1B of the second embodiment, the laminated device 1C of the modified example of the second embodiment includes one first external electrode P1a and the other first external electrode P1b, one second external electrode P2a and the other second external electrode P2b, a first ground electrode G1 and a second ground electrode G2, a first signal path R1, a second signal path R2, a first ground connection path Rg1, a second ground connection path Rg2, a third ground connection path Rg3, and a fourth ground connection path Rg4.

[0136] Furthermore, the multilayer device 1C of the modified example has a continuity check line 35a for checking the continuity between the first ground electrode G1 and the internal conductor or the continuity between the second ground electrode G2 and the internal conductor. The continuity check line 35a is provided to electrically connect the first ground electrode G1 and the second ground electrode G2.

[0137] Fig. 17 is a diagram showing the internal conductors of the multilayer device 1C. In Fig. 17, the insulators 10, external electrodes, and ground electrodes of the multilayer device 1C are indicated by dashed lines, and the internal conductors are indicated by solid lines.

[0138] 17 , a modified multilayer device 1C includes an insulator 10, one first external electrode P1a and the other first external electrode P1b, one second external electrode P2a and the other second external electrode P2b, a first ground electrode G1 and a second ground electrode G2, and a plurality of paths provided inside the insulator 10. The plurality of paths includes a first signal path R1, a second signal path R2, a first ground connection path Rg1, a second ground connection path Rg2, a third ground connection path Rg3, and a fourth ground connection path Rg4.

[0139] The multilayer device 1C of the modified example further includes a continuity check line 35a as one of the multiple paths. One end of the continuity check line 35a is connected to the first conductor line 31 and the third conductor line 33, and the other end of the continuity check line 35a is connected to the second conductor line 32 and the fourth conductor line 34. This configuration makes it possible to check the continuity between the first ground electrode G1 and the connection electrode i1 or the continuity between the second ground electrode G2 and the connection electrode i2.

[0140] Note that, in order to reduce the influence of the continuity check line 35a on the electromagnetic coupling of the common mode choke coil 50, it is desirable to position the continuity check line 35a in a position that does not overlap the common mode choke coil 50 when viewed from the stacking direction (first direction D1). In this example, the continuity check line 35a is provided outside the common mode choke coil 50 when viewed from the stacking direction (first direction D1). In other words, the continuity check line 35a does not overlap the common mode choke coil 50 when viewed from the stacking direction (first direction D1).

[0141] FIG. 18 is a diagram showing the common mode signal passing characteristics of the multilayer device 1C.

[0142] 18, the multilayer device 1C can block common mode signals in the frequency range of 1.43 GHz to 16.31 GHz (a bandwidth of 14.88 GHz). In this way, the multilayer device 1C according to the modification of the second embodiment can widen the stop band that blocks common mode signals compared to the multilayer device 101 according to the comparative example.

[0143] Furthermore, in the multilayer device 1C, an LC resonant circuit is formed on each of the signal input side and the signal output side, which are both sides of the common mode choke coil 50. When an LC resonant circuit is formed on both sides of the common mode choke coil 50 as in the multilayer device 1C, it becomes possible to make Scd12 and Scd21 have approximately the same characteristics. Similarly, in the multilayer device 1B, it becomes possible to make Scd12 and Scd21 have approximately the same characteristics.

[0144] (Summary) Examples of laminated devices including laminated devices 1, 1A, 1B, and 1C of the present disclosure will be described.

[0145] The laminated device of Example 1 comprises an insulator 10 formed by stacking multiple insulating layers 15, one first external electrode P1a and the other first external electrode P1b provided on the outer surface of the insulator 10, one second external electrode P2a and the other second external electrode P2b provided on the outer surface of the insulator 10, a first ground electrode G1 and a second ground electrode G2 provided on the outer surface of the insulator 10, and multiple paths provided inside the insulator 10.

[0146] The multiple paths include a first signal path R1 connecting one first external electrode P1a and the other first external electrode P1b, a second signal path R2 connecting one second external electrode P2a and the other second external electrode P2b, a first ground connection path Rg1 connecting one first external electrode P1a and the first ground electrode G1, and a second ground connection path Rg2 connecting one second external electrode P2a and the second ground electrode G2.

[0147] The first signal path R1 has a first coil 51, and the second signal path R2 has a second coil 52 which constitutes a common mode choke coil 50 together with the first coil 51.

[0148] The first ground connection path Rg1 includes a first opposing electrode 21 that is capacitively coupled to one of the first external electrodes P1a, and a first conductor line 31 that electrically connects the first opposing electrode 21 and the first ground electrode G1. The second ground connection path Rg2 includes a second opposing electrode 22 that is capacitively coupled to one of the second external electrodes P2a, and a second conductor line 32 that electrically connects the second opposing electrode 22 and the second ground electrode G2.

[0149] According to this configuration, an LC resonant circuit is formed in each of the first ground connection path Rg1 and the second ground connection path Rg2. Therefore, when a differential signal is transmitted through the first signal path R1 and the second signal path R2, each LC resonant circuit resonates at a predetermined frequency. By each LC resonant circuit resonating at a predetermined frequency, common mode noise of the predetermined frequency can be diverted to ground. This allows common mode noise of a predetermined frequency different from the specific frequency to be further eliminated in addition to the specific frequency eliminated by the common mode choke coil 50, thereby widening the stop band that prevents common mode signals from passing through.

[0150] The multilayer device of Example 2 is the multilayer device described in Example 1, wherein the paths further include a third ground connection path Rg3 connecting the other first external electrode P1b and the first ground electrode G1, and a fourth ground connection path Rg4 connecting the other second external electrode P2b and the second ground electrode G2. The third ground connection path Rg3 may include a third opposing electrode 23 capacitively coupled to the other first external electrode P1b, and a third conductor line 33 electrically connecting the third opposing electrode 23 and the first ground electrode G1. The fourth ground connection path Rg4 may include a fourth opposing electrode 24 capacitively coupled to the other second external electrode P2b, and a fourth conductor line 34 electrically connecting the fourth opposing electrode 24 and the second ground electrode G2.

[0151] According to this configuration, an LC resonant circuit is formed in each of the third ground connection path Rg3 and the fourth ground connection path Rg4. Therefore, when a differential signal is transmitted to the first signal path R1 and the second signal path R2, each LC resonant circuit resonates at a predetermined frequency. By each LC resonant circuit resonating at a predetermined frequency, common mode noise of the predetermined frequency can be diverted to ground. This allows common mode noise of a predetermined frequency different from the specific frequency to be further eliminated in addition to the specific frequency eliminated by the common mode choke coil 50, thereby widening the stop band that prevents common mode signals from passing through.

[0152] The multilayer device of Example 3 is the multilayer device described in Example 2, except that the first external electrode P1a and the first opposing electrode 21 on one side may be electrodes for forming a first capacitance in the first ground connection path Rg1, and the first conductor line 31 may be a line for forming a first inductance in the first ground connection path Rg1. The second external electrode P2a and the second opposing electrode 22 on the other side may be electrodes for forming a second capacitance in the second ground connection path Rg2, and the second conductor line 32 may be a line for forming a second inductance in the second ground connection path Rg2. The first external electrode P1b and the third opposing electrode 23 on the other side may be electrodes for forming a third capacitance in the third ground connection path Rg3, and the third conductor line 33 may be a line for forming a third inductance in the third ground connection path Rg3. The other second external electrode P2b and the fourth opposing electrode 24 are electrodes for forming a fourth capacitance in the fourth ground connection path Rg4, and the fourth conductor line 34 may be a line for forming a fourth inductance in the fourth ground connection path Rg4.

[0153] According to this configuration, an LC resonant circuit having capacitance and inductance is formed in each of the first ground connection path Rg1, the second ground connection path Rg2, the third ground connection path Rg3, and the fourth ground connection path Rg4. Therefore, when a differential signal is transmitted through the first signal path R1 and the second signal path R2, each LC resonant circuit resonates at a predetermined frequency. By each LC resonant circuit resonating at a predetermined frequency, common mode noise of the predetermined frequency can be diverted to ground. This allows common mode noise of a predetermined frequency different from the specific frequency to be further eliminated in addition to the specific frequency eliminated by the common mode choke coil 50, thereby widening the stop band that prevents common mode signals from passing through.

[0154] The stacked device of Example 4 is the stacked device described in Example 3, except that the facing area between the first external electrode P1a and the first opposing electrode 21 on one side is the same as the facing area between the second external electrode P2a and the second opposing electrode 22 on one side, and the gap between the first external electrode P1a and the first opposing electrode 21 is the same as the gap between the second external electrode P2a and the second opposing electrode 22 on one side. The cross-sectional area of ​​the first conductor line 31 is the same as the cross-sectional area of ​​the second conductor line 32, and the length of the first conductor line 31 is the same as the length of the second conductor line 32. The facing area between the first external electrode P1b and the third opposing electrode 23 on the other side is the same as the facing area between the second external electrode P2b and the fourth opposing electrode 24 on the other side, and the gap between the first external electrode P1b and the third opposing electrode 23 on the other side is the same as the gap between the second external electrode P2b and the fourth opposing electrode 24 on the other side. The cross-sectional area of ​​the third conductor line 33 may be the same as the cross-sectional area of ​​the fourth conductor line 34 , and the length of the third conductor line 33 may be the same as the length of the fourth conductor line 34 .

[0155] This allows the resonant frequencies of the LC resonant circuits of the first ground connection path Rg1 and the second ground connection path Rg2 to match, and also allows the resonant frequencies of the LC resonant circuits of the third ground connection path Rg3 and the fourth ground connection path Rg4 to match. This increases the attenuation of the attenuation pole formed at the resonant frequency of the LC resonant circuit, allowing common-mode noise of a predetermined frequency to escape to ground. This further removes common-mode noise of a predetermined frequency different from the specific frequency, in addition to the specific frequency removed by the common-mode choke coil 50, and widens the stop band that blocks common-mode signals from passing through.

[0156] The stacked device of Example 5 is the stacked device described in Example 3 or 4, except that the facing area between the first external electrode P1a on one side and the first opposing electrode 21 is the same as the facing area between the first external electrode P1b on the other side and the third opposing electrode 23, and the gap between the first external electrode P1a on one side and the first opposing electrode 21 is the same as the gap between the first external electrode P1b on the other side and the third opposing electrode 23. The cross-sectional area of ​​the first conductor line 31 is the same as the cross-sectional area of ​​the third conductor line 33, and the length of the first conductor line 31 is the same as the length of the third conductor line 33. The facing area between the second external electrode P2a on one side and the second opposing electrode 22 is the same as the facing area between the second external electrode P2b on the other side and the fourth opposing electrode 24, and the gap between the second external electrode P2a on one side and the second opposing electrode 22 is the same as the gap between the second external electrode P2b on the other side and the fourth opposing electrode 24. The cross-sectional area of ​​the second conductor line 32 may be the same as the cross-sectional area of ​​the fourth conductor line 34 , and the length of the second conductor line 32 may be the same as the length of the fourth conductor line 34 .

[0157] This configuration allows the resonant frequencies of the LC resonant circuits of the first ground connection path Rg1 and the third ground connection path Rg3 to match, and also allows the resonant frequencies of the LC resonant circuits of the second ground connection path Rg2 and the fourth ground connection path Rg4 to match. This increases the attenuation of the attenuation poles formed at the resonant frequencies of the LC resonant circuits, allowing common-mode noise of a predetermined frequency to escape to ground. This configuration further removes common-mode noise of a predetermined frequency different from the specific frequency removed by the common-mode choke coil 50, thereby widening the stop band that blocks the passage of common-mode signals. Furthermore, this configuration allows Scd12 and Scd21, which represent components of differential-mode signals converted into common-mode signals through the common-mode choke coil 50, to have substantially the same characteristics.

[0158] The laminated device of Example 6 is the laminated device according to any one of Examples 2 to 5, in which the common mode choke coil 50 is composed of a plurality of common mode choke coils 50a, 50b, the plurality of common mode choke coils 50a, 50b are arranged along the stacking direction in which the plurality of insulating layers 15 are stacked, and the first ground connection path Rg1, the second ground connection path Rg2, the third ground connection path Rg3, and the fourth ground connection path Rg4 may be arranged outside the common mode choke coil 50 when viewed from the stacking direction.

[0159] With this configuration, the LC resonant circuit can be formed in a position that has minimal effect on the electromagnetic coupling of the common mode choke coil 50. Therefore, when a differential signal is transmitted through the first signal path R1 and the second signal path R2, common mode noise of a predetermined frequency can be diverted to ground. This makes it possible to further eliminate common mode noise of a predetermined frequency different from the specific frequency, in addition to the specific frequency removed by the common mode choke coil 50, and to widen the stop band that prevents the passage of common mode signals.

[0160] The stacked devices 1A and 1C of Example 7 are stacked devices described in any of Examples 2 to 6, and the multiple paths may further include a continuity check line 35a connecting the first ground electrode G1 and the second ground electrode G2.

[0161] In this way, by providing the stacked devices 1A and 1C with the continuity check line 35a, it is possible to easily check whether the first ground electrode G1 and the first ground connection path Rg1 are electrically connected, and whether the second ground electrode G2 and the second ground connection path Rg2 are electrically connected.

[0162] The stacked devices 1A and 1C of Example 8 are the stacked devices described in Example 7, and one end of the continuity check line 35a may be connected to the first conductor line 31 and the third conductor line 33, and the other end of the continuity check line 35a may be connected to the second conductor line 32 and the fourth conductor line 34.

[0163] This makes it easy to check whether the connection electrode that should be connected to the first ground electrode G1 is securely connected to the first ground electrode G1, and whether the connection electrode that should be connected to the second ground electrode G2 is securely connected to the second ground electrode G2.

[0164] The stacked device of Example 9 is the stacked device according to any one of Examples 1 to 8, and may have a plurality of first ground connection paths Rg1 and a plurality of second ground connection paths Rg2.

[0165] This allows for the formation of an attenuation pole with a large amount of attenuation at the resonance frequency formed by each of the plurality of first ground connection paths Rg1 and the plurality of second ground connection paths Rg2.

[0166] The stacked device 1, 1A of Example 10 is the stacked device according to any one of Examples 2 to 9, in which the insulator 10 is rectangular parallelepiped and has a bottom surface 18, a top surface 19, and four side surfaces, the four side surfaces including a first side surface 11 and a second side surface 12 facing back to back, and a third side surface 13 and a fourth side surface 14 facing back to back. The insulating layers 15 are stacked in a direction in which the bottom surface 18 and the top surface 19 face back to back. One first external electrode P1a and one second external electrode P2a may be formed on the first side surface 11, the other first external electrode P1b and the other second external electrode P2b may be formed on the second side surface 12, the first ground electrode G1 may be formed on the third side surface 13, and the second ground electrode G2 may be formed on the fourth side surface 14.

[0167] This makes it possible to provide the multilayer device 1, 1A in which, when the multilayer device 1, 1A is mounted on a substrate, a plurality of insulating layers 15 are stacked in a direction perpendicular to the substrate.

[0168] The stacked devices 1 and 1A of Example 11 are the stacked devices described in Example 10, and further include one first external electrode P1a, one second external electrode P2a, the other first external electrode P1b, and the other second external electrode P2b, which are also formed on the bottom surface 18 and the top surface 19, respectively. The first opposing electrode 21 may face the one first external electrode P1a formed on the top surface 19, the second opposing electrode 22 may face the one second external electrode P2a formed on the top surface 19, the third opposing electrode 23 may face the other first external electrode P1b formed on the bottom surface 18, and the fourth opposing electrode 24 may face the other second external electrode P2b formed on the bottom surface 18.

[0169] This allows a capacitance to be formed between the first opposing electrode 21 and one of the first external electrodes P1a, a capacitance to be formed between the second opposing electrode 22 and one of the second external electrodes P2a, a capacitance to be formed between the third opposing electrode 23 and the other first external electrode P1b, and a capacitance to be formed between the fourth opposing electrode 24 and the other second external electrode P2b.

[0170] The stacked devices 1B and 1C of Example 12 are the stacked devices according to any one of Examples 2 to 9, in which the insulator 10 is rectangular and has a bottom surface 18, a top surface 19, and four side surfaces, the four side surfaces including a first side surface 11 and a second side surface 12 facing back to back, and a third side surface 13 and a fourth side surface 14 facing back to back. The insulating layers 15 are stacked in a direction in which the first side surface 11 and the second side surface 12 face back to back. One first external electrode P1a and one second external electrode P2a may be formed on the first side surface 11, the other first external electrode P1b and the other second external electrode P2b may be formed on the second side surface 12, the first ground electrode G1 may be formed on the third side surface 13, and the second ground electrode G2 may be formed on the fourth side surface 14.

[0171] This makes it possible to provide the multilayer devices 1B and 1C in which, when the multilayer devices 1B and 1C are mounted on a substrate, a plurality of insulating layers 15 are stacked in a direction parallel to the substrate.

[0172] The stacked devices 1B and 1C of Example 13 may be the stacked devices described in Example 12, in which the first opposing electrode 21 faces one of the first external electrodes P1a formed on the first side surface 11, the second opposing electrode 22 faces one of the second external electrodes P2a formed on the first side surface 11, the third opposing electrode 23 faces the other of the first external electrodes P1b formed on the second side surface 12, and the fourth opposing electrode 24 faces the other of the second external electrodes P2b formed on the second side surface 12.

[0173] This allows a capacitance to be formed between the first opposing electrode 21 and one of the first external electrodes P1a, a capacitance to be formed between the second opposing electrode 22 and one of the second external electrodes P2a, a capacitance to be formed between the third opposing electrode 23 and the other first external electrode P1b, and a capacitance to be formed between the fourth opposing electrode 24 and the other second external electrode P2b.

[0174] (Other Embodiments, etc.) While stacked devices and the like according to the embodiments and modifications of the present disclosure have been described above, the present disclosure is not limited to the above-described embodiments and modifications. As long as they do not deviate from the gist of the present disclosure, various modifications conceivable by a person skilled in the art to the embodiments and modifications, as well as other embodiments constructed by combining some of the components of the embodiments and modifications, are also included in the scope of the present disclosure.

[0175] Although the above example shows that the multilayer devices 1 to 1C include the first ground connection path Rg1, the second ground connection path Rg2, the third ground connection path Rg3, and the fourth ground connection path Rg4, this is not limiting. For example, the multilayer devices 1 to 1C may include only the first ground connection path Rg1 and the second ground connection path Rg2 as the multiple ground connection paths. The multilayer devices 1 to 1C may also include only the third ground connection path Rg3 and the fourth ground connection path Rg4 as the multiple ground connection paths. In the latter case, the third ground connection path Rg3 may be read as the first ground connection path Rg1, and the fourth ground connection path Rg4 may be read as the second ground connection path Rg2.

[0176] Although the above example shows that the first LC resonant circuit LC1, the second LC resonant circuit LC2, the third LC resonant circuit LC3, and the fourth LC resonant circuit LC4 have the same resonant frequency, this is not limiting. For example, the first LC resonant circuit LC1 and the second LC resonant circuit LC2 may have the same first resonant frequency, the third LC resonant circuit LC3 and the fourth LC resonant circuit LC4 may have the same second resonant frequency, and the first resonant frequency and the second resonant frequency may be different frequencies. Alternatively, the first LC resonant circuit LC1 and the third LC resonant circuit LC3 may have the same third resonant frequency, and the second LC resonant circuit LC2 and the fourth LC resonant circuit LC4 may have the same fourth resonant frequency, and the third resonant frequency and the fourth resonant frequency may be different frequencies.

[0177] The laminated device according to the present disclosure is useful as a common mode noise filter that suppresses the passage of common mode signals.

[0178] 1, 1A, 1B, 1C Multilayer device 10 Insulator 11 First side surface 12 Second side surface 13 Third side surface 14 Fourth side surface 15 Insulating layer 18 Bottom surface 19 Top surface 21 First opposing electrode 22 Second opposing electrode 23 Third opposing electrode 24 Fourth opposing electrode 31 First conductor line 32 Second conductor line 33 Third conductor line 34 Fourth conductor line 35a, 35b Continuity check line 50, 50a, 50b Common mode choke coil 51 First coil 51a, 51b Coil 52 Second coil 52a, 52b Coil C1 First capacitor C2 Second capacitor C3 Third capacitor C4 Fourth capacitor D1 First direction D2 Second direction D3 Third direction G1 First ground electrode G2 Second ground electrode L1 First inductor L2 Second inductor L3 Third inductor L4 Fourth inductor LC1 First LC resonant circuit LC2 Second LC resonant circuit LC3 Third LC resonant circuit LC4 Fourth LC resonant circuit P1a One of the first external electrodes P1b The other first external electrode P2a One of the second external electrodes P2b The other second external electrode R1 First signal path R2 Second signal path Rg1 First ground connection path Rg2 Second ground connection path Rg3 Third ground connection path Rg4 Fourth ground connection path b1a, b1b, b2a, b2b Bottom electrode portions s1a, s1b, s2a, s2b Side electrode portions t1a, t1b, t2a, t2b Top electrode portions

Claims

1. An insulator formed by laminating a plurality of insulating layers; one first external electrode and the other first external electrode provided on the outer surface of the insulator; one second external electrode and the other second external electrode provided on the outer surface of the insulator; a first ground electrode and a second ground electrode provided on the outer surface of the insulator; and a plurality of paths provided inside the insulator, wherein the plurality of paths include a first signal path connecting the one first external electrode and the other first external electrode, a second signal path connecting the one second external electrode and the other second external electrode, a first ground connection path connecting the one first external electrode and the first ground electrode, and a second ground connection path connecting the one second external electrode and the second ground electrode, wherein the first signal path includes a first coil, and the second signal path includes a second coil that forms a common mode choke coil with the first coil, the first ground connection path includes a first opposing electrode capacitively coupled to the one first external electrode, and a first conductor line electrically connecting the first opposing electrode and the first ground electrode; and the second ground connection path includes a second opposing electrode capacitively coupled to the one second external electrode, and a second conductor line electrically connecting the second opposing electrode and the second ground electrode.

2. The stacked device according to claim 1, wherein the plurality of paths further include: a third ground connection path connecting the other first external electrode and the first ground electrode; and a fourth ground connection path connecting the other second external electrode and the second ground electrode, wherein the third ground connection path includes a third opposing electrode capacitively coupled to the other first external electrode, and a third conductor line electrically connecting the third opposing electrode and the first ground electrode, and the fourth ground connection path includes a fourth opposing electrode capacitively coupled to the other second external electrode, and a fourth conductor line electrically connecting the fourth opposing electrode and the second ground electrode.

3. The laminated device according to claim 2, wherein the one first external electrode and the first opposing electrode are electrodes for forming a first capacitance in the first ground connection path, the first conductor line is a line for forming a first inductance in the first ground connection path, the one second external electrode and the second opposing electrode are electrodes for forming a second capacitance in the second ground connection path, the second conductor line is a line for forming a second inductance in the second ground connection path, the other first external electrode and the third opposing electrode are electrodes for forming a third capacitance in the third ground connection path, the third conductor line is a line for forming a third inductance in the third ground connection path, the other second external electrode and the fourth opposing electrode are electrodes for forming a fourth capacitance in the fourth ground connection path, and the fourth conductor line is a line for forming a fourth inductance in the fourth ground connection path.

4. The stacked device according to claim 3, wherein the facing area of ​​the one first external electrode and the first opposing electrode is the same as the facing area of ​​the one second external electrode and the second opposing electrode; the gap between the one first external electrode and the first opposing electrode is the same as the gap between the one second external electrode and the second opposing electrode; the cross-sectional area of ​​the first conductor line is the same as the cross-sectional area of ​​the second conductor line; the length of the first conductor line is the same as the length of the second conductor line; the facing area of ​​the other first external electrode and the third opposing electrode is the same as the facing area of ​​the other second external electrode and the fourth opposing electrode; the gap between the other first external electrode and the third opposing electrode is the same as the gap between the other second external electrode and the fourth opposing electrode; the cross-sectional area of ​​the third conductor line is the same as the cross-sectional area of ​​the fourth conductor line; and the length of the third conductor line is the same as the length of the fourth conductor line.

5. The laminated device according to claim 4, wherein the opposing area of ​​the one first external electrode and the first opposing electrode is the same as the opposing area of ​​the other first external electrode and the third opposing electrode, the gap between the one first external electrode and the first opposing electrode is the same as the gap between the other first external electrode and the third opposing electrode, the cross-sectional area of ​​the first conductor line is the same as the cross-sectional area of ​​the third conductor line, the length of the first conductor line is the same as the length of the third conductor line, the opposing area of ​​the one second external electrode and the second opposing electrode is the same as the opposing area of ​​the other second external electrode and the fourth opposing electrode, the gap between the one second external electrode and the second opposing electrode is the same as the gap between the other second external electrode and the fourth opposing electrode, the cross-sectional area of ​​the second conductor line is the same as the cross-sectional area of ​​the fourth conductor line, and the length of the second conductor line is the same as the length of the fourth conductor line.

6. The multilayer device according to any one of claims 2 to 5, wherein the common mode choke coil is constituted by a plurality of common mode choke coils, the plurality of common mode choke coils are arranged along a stacking direction in which the plurality of insulating layers are stacked, and the first ground connection path, the second ground connection path, the third ground connection path and the fourth ground connection path are arranged outside the common mode choke coil when viewed from the stacking direction.

7. The multilayer device according to any one of claims 2 to 5, wherein the plurality of paths further include a continuity check line connecting the first ground electrode and the second ground electrode.

8. The stacked device according to claim 7, wherein one end of the continuity check line is connected to the first conductor line and the third conductor line, and the other end of the continuity check line is connected to the second conductor line and the fourth conductor line.

9. The multilayer device according to any one of claims 1 to 5, comprising a plurality of the first ground connection paths and a plurality of the second ground connection paths.

10. The stacked device according to any one of claims 2 to 5, wherein the insulator is rectangular and has a bottom surface, a top surface, and four side surfaces, the four side surfaces including a first side surface and a second side surface facing back to back, and a third side surface and a fourth side surface facing back to back, the plurality of insulating layers are stacked in a direction in which the bottom surface and the top surface are facing back to back, the one first external electrode and the one second external electrode are formed on the first side surface, the other first external electrode and the other second external electrode are formed on the second side surface, the first ground electrode is formed on the third side surface, and the second ground electrode is formed on the fourth side surface.

11. The stacked device according to claim 10, further comprising: the one first external electrode, the one second external electrode, the other first external electrode, and the other second external electrode, which are also formed on the bottom surface and the top surface, respectively; the first opposing electrode faces the one first external electrode formed on the top surface; the second opposing electrode faces the one second external electrode formed on the top surface; the third opposing electrode faces the other first external electrode formed on the bottom surface; and the fourth opposing electrode faces the other second external electrode formed on the bottom surface.

12. The stacked device according to any one of claims 2 to 5, wherein the insulator is rectangular and has a bottom surface, a top surface, and four side surfaces, the four side surfaces including a first side surface and a second side surface facing back to back, and a third side surface and a fourth side surface facing back to back, the plurality of insulating layers are stacked in a direction in which the first side surface and the second side surface face back to back, the one first external electrode and the one second external electrode are formed on the first side surface, the other first external electrode and the other second external electrode are formed on the second side surface, the first ground electrode is formed on the third side surface, and the second ground electrode is formed on the fourth side surface.

13. The stacked device according to claim 12, wherein the first opposing electrode faces the one first external electrode formed on the first side surface, the second opposing electrode faces the one second external electrode formed on the first side surface, the third opposing electrode faces the other first external electrode formed on the second side surface, and the fourth opposing electrode faces the other second external electrode formed on the second side surface.

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