Semiconductor device

Abstract

A semiconductor device according to the present invention comprises: a chip that has a main surface; a first conductivity type semiconductor region that is formed in a surface layer part of the main surface; an active region that is provided in the inner part of the main surface; an outer peripheral region that is provided in the peripheral part of the main surface; a device structure that is formed in the active region; and a plurality of annular second conductivity type field regions that are formed in the outer peripheral region at intervals in the surface layer part of the semiconductor region and that surround the active region, wherein the intervals between the plurality of field regions each become wider in the direction from the active region toward the outer peripheral region, the widths of the plurality of field regions each decrease in the direction from the active region toward the outer peripheral region, the field regions each have a first upper end part on the main surface side and a first lower end part on the opposite side, and the field regions each have a concentration gradient which gradually decreases from the first upper end part toward the first lower end part.

Description

Semiconductor Devices Related Applications

[0001] This application corresponds to Japanese Patent Application No. 2024-042517 filed with the Japan Patent Office on March 18, 2024, the entire disclosure of which is incorporated herein by reference.

[0002] The present disclosure relates to semiconductor devices.

[0003] In the semiconductor device of Patent Document 1, an FLR structure is provided in the edge termination region, which is made up of a plurality of FLRs at a floating potential that concentrically surround the periphery of the active region. The FLR structure is divided into two or more FLR sections, with a predetermined FLR as a boundary. The n-th interval x between adjacent FLRs is n is p + The n-th distance x between adjacent FLRs is greater than the first distance x between the mold extension and the innermost FLR. n The width of the FLR section increases in an arithmetic progression with a constant increase for each FLR section as it is positioned further outward, and the increase width increases toward the outer FLR section.

[0004] Japanese Patent Application Laid-Open No. 2022-168904

[0005] [Summary] One embodiment of the present disclosure provides a semiconductor device including: a chip having a main surface; a semiconductor region of a first conductivity type formed in a surface layer portion of the main surface; an active region provided in an inner portion of the main surface; a peripheral region provided on a peripheral edge portion of the main surface; a device structure formed within the active region; and a plurality of annular field regions of a second conductivity type formed at intervals in the surface layer portion of the semiconductor region in the peripheral region and surrounding the active region, wherein the spacing between the plurality of field regions increases in a direction from the active region toward the peripheral region and the width of each of the plurality of field regions decreases in a direction from the active region toward the peripheral region, and each of the field regions has a first upper end on the side of the main surface and a first lower end on the opposite side, and wherein the field regions have a concentration gradient that gradually decreases from the first upper end toward the first lower end.

[0006] FIG. 1 is a plan view showing a semiconductor device according to a first embodiment of the present disclosure. FIG. 2 is a cross-sectional view taken along line II-II in FIG. 1 . FIG. 3 is a plan view showing an example of a chip layout. FIG. 4 is a perspective view showing an example of a chip layout. FIG. 5 is an enlarged plan view showing a main portion of a first main surface shown in FIG. 3 . FIG. 6 is an enlarged plan view showing a main portion of a first main surface shown in FIG. 3 . FIG. 7 is a cross-sectional view taken along line VII-VII in FIG. 5 . FIG. 8 is a cross-sectional view taken along line VIII-VIII in FIG. 5 . FIG. 9 is a cross-sectional view taken along line IX-IX in FIG. 6 . FIG. 10 is a cross-sectional view showing a cross-sectional structure of the peripheral region taken along line XX in FIG. 1 . FIG. 11 is an enlarged cross-sectional view of a region shown in FIG. 10 . FIG. 12 is a plan view showing an example of a chip layout. FIG. 13 is a graph showing an example of a concentration gradient of p-type impurities in a region taken along line XIII-XIII in FIG. 9 . FIG. 14 is a graph showing an example of the concentration gradient of p-type impurities in a region along line XIV-XIV shown in FIG. 11 . FIG. 15 is a cross-sectional view showing the cross-sectional structure of the peripheral region along line XV-XV shown in FIG. 1 . FIG. 16 is a cross-sectional view showing the cross-sectional structure of the peripheral region along line XVI-XVI shown in FIG. 1 . FIG. 17 is a graph showing the relationship between charge density and breakdown voltage. FIG. 18 is a cross-sectional view showing a main portion of a second embodiment. FIG. 19 is a cross-sectional view showing a main portion of a third embodiment. FIG. 20 is a cross-sectional view showing a main portion of a semiconductor device according to a second embodiment of the present disclosure. FIG. 21 is a cross-sectional view showing a main portion of the semiconductor device. FIG. 22 is a cross-sectional view showing a main portion of a semiconductor device according to a third embodiment of the present disclosure.

[0007] [Detailed Description] Specific embodiments will be described in detail below with reference to the accompanying drawings. The accompanying drawings are all schematic diagrams and are not strictly illustrative, and the relative positional relationships, scales, ratios, angles, etc. are not necessarily consistent. Corresponding structures among the accompanying drawings are given the same reference numerals, and duplicated descriptions are omitted or simplified. For structures whose descriptions are omitted or simplified, the descriptions given before the omission or simplification apply.

[0008] When the term "substantially" is used in this specification, this term includes a numerical value (form) equal to the numerical value (form) of the comparison target, as well as a numerical error (form error) within a range of ±10% based on the numerical value (form) of the comparison target. In the following description, terms such as "first," "second," and "third" are used, but these are symbols attached to the names of each structure to clarify the order of description, and are not intended to limit the names of each structure.

[0009] In the following description, the conductivity type of a semiconductor (impurity) is indicated using "p-type" or "n-type," but "p-type" may also be referred to as the "first conductivity type" and "n-type" as the "second conductivity type." "n-type" may also be referred to as the "first conductivity type" and "p-type" as the "second conductivity type." "p-type" is a conductivity type resulting from a trivalent element, and "n-type" is a conductivity type resulting from a pentavalent element. The trivalent element is at least one of boron, aluminum, gallium, and indium. The pentavalent element is at least one of nitrogen, phosphorus, arsenic, antimony, and bismuth.

[0010] Fig. 1 is a plan view showing a semiconductor device 1A according to a first embodiment of the present disclosure. Fig. 2 is a cross-sectional view taken along line II-II shown in Fig. 1. Fig. 3 is a plan view showing an example layout of a chip 2. Fig. 4 is a perspective view showing an example layout of the chip 2.

[0011] The semiconductor device 1A is a semiconductor switching device having an insulated gate transistor structure Tr as an example of a device structure. The transistor structure Tr has a trench gate vertical structure.

[0012] 1 to 4, semiconductor device 1A includes chip 2 formed in a hexahedral shape (specifically, a rectangular parallelepiped shape). In this embodiment, chip 2 includes a single crystal of a wide bandgap semiconductor. In other words, semiconductor device 1A is a "wide bandgap semiconductor device." Chip 2 may also be referred to as a "semiconductor chip," a "wide bandgap semiconductor chip," or the like.

[0013] A wide bandgap semiconductor is a semiconductor having a bandgap that exceeds the bandgap of Si (silicon). Examples of wide bandgap semiconductors include GaN (gallium nitride), SiC (silicon carbide), and C (diamond). In this embodiment, the chip 2 is a "SiC chip" that includes a hexagonal SiC single crystal as an example of a wide bandgap semiconductor. In other words, the semiconductor device 1A is a "SiC semiconductor device."

[0014] Hexagonal SiC single crystal has a plurality of polytypes including 2H (Hexagonal)-SiC single crystal, 4H-SiC single crystal, 6H-SiC single crystal, etc. In this embodiment, an example is shown in which the chip 2 includes a 4H-SiC single crystal, but the chip 2 may also include other polytypes.

[0015] The chip 2 has a first main surface (principal surface) 3 on one side, a second main surface 4 on the other side, and first to fourth side surfaces 5A to 5D connected to the first main surface 3 and the second main surface 4. The first main surface 3 and the second main surface 4 are formed in a quadrangular shape in a plan view seen from the vertical direction Z (hereinafter simply referred to as "plan view"). The vertical direction Z is also the thickness direction of the chip 2.

[0016] The first main surface 3 and the second main surface 4 are preferably formed by the c-plane of the SiC single crystal. In this case, it is preferable that the first main surface 3 is formed by the silicon surface ((0001) surface) of the SiC single crystal, and the second main surface 4 is formed by the carbon surface ((000-1) surface) of the SiC single crystal.

[0017] The first side surface 5A and the second side surface 5B extend in a first direction X along the first main surface 3 and face a second direction Y that intersects with the first direction X along the first main surface 3. Specifically, the second direction Y is perpendicular to the first direction X. The third side surface 5C and the fourth side surface 5D extend in the second direction Y and face the first direction X.

[0018] In this embodiment, the first direction X is the m-axis direction ([1-100] direction) of the SiC single crystal, and the second direction Y is the a-axis direction ([11-20] direction) of the SiC single crystal. The first direction X may be the a-axis direction of the SiC single crystal, and the second direction Y may be the m-axis direction of the SiC single crystal. Hereinafter, the direction extending along the first main surface 3 may be referred to as the "horizontal direction." The horizontal direction is also the XY plane (horizontal plane) formed by the first direction X and the second direction Y, and is perpendicular to the vertical direction Z.

[0019] 3, the chip 2 (first main surface 3 and second main surface 4) has an off angle α (FIG. 3) inclined at a predetermined angle in a predetermined off direction with respect to the c-plane of the SiC single crystal. That is, the c-axis ((0001) axis) of the SiC single crystal is inclined by the off angle α from a vertical line along the vertical direction Z toward the off direction. Furthermore, the c-plane of the SiC single crystal is inclined by the off angle α with respect to a horizontal plane.

[0020] The off-direction is preferably the a-axis direction of the SiC single crystal (second direction Y in this embodiment). The off-angle α may be greater than 0° and less than or equal to 10°. The off-angle α may have a value belonging to at least one of the ranges of greater than 0° and less than or equal to 1°, 1° to 2.5°, 2.5° to 5°, 5° to 7.5°, and 7.5° to 10°.

[0021] The off angle α is preferably 5° or less. The off angle α is particularly preferably 2° or more and 4.5° or less. The off angle α is typically set in the range of 4°±0.1°. This specification does not exclude a configuration in which the off angle α is 0° (i.e., a configuration in which the first main surface 3 is a just plane with respect to the c-plane).

[0022] 2, the semiconductor device 1A includes an n-type first semiconductor region 6 formed in a surface layer portion of the second main surface 4. A drain potential as a first potential (high potential) is applied to the first semiconductor region 6. The first semiconductor region 6 may also be referred to as a "base region (layer)," a "semiconductor region (layer)," a "drain region (layer)," or the like.

[0023] The first semiconductor region 6 extends in a layered form along the second main surface 4 and is exposed from the second main surface 4 and the first to fourth side surfaces 5A to 5D. In this embodiment, the first semiconductor region 6 is made of an n-type semiconductor layer. Specifically, the first semiconductor region 6 is made of a substrate (SiC substrate) including a SiC single crystal (semiconductor single crystal), and forms the second main surface 4 and the first to fourth side surfaces 5A to 5D. The first semiconductor region 6 (substrate) has the off direction and off angle α ( FIG. 3 ) described above.

[0024] The first semiconductor region 6 may have a thickness T1 of 10 μm to 500 μm inclusive. The thickness T1 of the first semiconductor region 6 may have a value belonging to at least one of the ranges of 10 μm to 50 μm inclusive, 50 μm to 100 μm inclusive, 100 μm to 150 μm inclusive, 150 μm to 200 μm inclusive, 200 μm to 300 μm inclusive, 300 μm to 400 μm inclusive, and 400 μm to 500 μm inclusive.

[0025] The semiconductor device 1A includes an n-type second semiconductor region 7 formed in a surface layer portion of the first main surface 3. The second semiconductor region 7 may also be referred to as a "semiconductor region (layer)," a "drift region (layer)," or the like. The second semiconductor region 7 has an n-type impurity concentration lower than the n-type impurity concentration of the first semiconductor region 6. The second semiconductor region 7 is formed in a region closer to the first main surface 3 than the first semiconductor region 6 in a cross-sectional view, and is electrically connected to the first semiconductor region 6.

[0026] The second semiconductor region 7 extends in a layered form along the first main surface 3 and is exposed from the first main surface 3 and the first to fourth side surfaces 5A to 5D. In this embodiment, the second semiconductor region 7 is made of an n-type semiconductor layer. Specifically, the second semiconductor region 7 is made of an epitaxial layer (SiC epitaxial layer) including a SiC single crystal (semiconductor single crystal), and forms the first main surface 3 and the first to fourth side surfaces 5A to 5D.

[0027] The second semiconductor region 7 (epitaxial layer) has the aforementioned off direction and off angle α. The second semiconductor region 7 preferably has a thickness T2 that is less than the thickness T1 of the first semiconductor region 6. The thickness T2 of the second semiconductor region 7 may be greater than the thickness T1 of the first semiconductor region 6.

[0028] The thickness T2 of the second semiconductor region 7 may be 5 μm or more and 15 μm or less. The thickness T2 of the second semiconductor region 7 may have a value belonging to at least one of the ranges of 5 μm or more and 7.5 μm or less, 7.5 μm or more and 10 μm or less, 10 μm or more and 12.5 μm or less, and 12.5 μm or more and 15 μm or less.

[0029] 2 to 4, semiconductor device 1A includes an active region 8 defined in chip 2. Active region 8 includes a device structure (transistor structure Tr) and is a region where an output current (drain current) is generated. Active region 8 is defined in an inner portion of chip 2 and spaced apart from the periphery of first main surface 3 (first to fourth side surfaces 5A to 5D).

[0030] The active region 8 is set to a polygonal shape (a quadrilateral shape in this embodiment) having four sides parallel to the periphery of the chip 2 in a plan view. The ratio (area ratio) of the planar area of ​​the active region 8 to the planar area of ​​the first main surface 3 may be 0.5 or more and 0.95 or less. The area ratio may be 0.5 or more and 0.6 or less, 0.6 or more and 0.7 or less, 0.7 or more and 0.8 or less, 0.8 or more and 0.9 or less, or 0.9 or more and 0.95 or less.

[0031] The semiconductor device 1A includes a peripheral region 9 set outside the active region 8 in the chip 2. The peripheral region 9 is a region that does not include a device structure (transistor structure Tr). The peripheral region 9 is set on the periphery of the chip 2. That is, the peripheral region 9 is provided in the region between the periphery of the chip 2 and the active region 8 in plan view. The peripheral region 9 extends in a strip shape along the active region 8 in plan view and is set in the shape of a polygonal ring (a square ring in this embodiment) that surrounds the active region 8.

[0032] The semiconductor device 1A includes a plurality of trench gate structures 15 of a trench type (trench electrode type) formed in the active region 8. The trench gate structures 15 may also be referred to as "trench structures," "trench gate structures," or the like.

[0033] The plurality of trench gate structures 15 are formed in an inner portion of the first main surface 3 at intervals from the periphery (first to fourth side surfaces 5A to 5D) of the first main surface 3, and are not formed in the outer peripheral region 9. The plurality of trench gate structures 15 are arranged at intervals in a first direction X (= m-axis direction) in a plan view, and each extend in a band shape in a second direction Y (= a-axis direction). The plurality of trench gate structures 15 are arranged in a stripe shape extending in the second direction Y in a plan view.

[0034] The semiconductor device 1A includes a p-type outer well region 42 formed in the peripheral region 9 .

[0035] 3 and 4 , the outer well region 42 is a quadrangular ring-shaped region defined by a thick solid line and a thick dashed line. The outer well region 42 has a portion extending in a first direction X and a portion extending in a second direction Y. In this embodiment, the outer well region 42 is formed in a polygonal ring shape (a quadrangular ring in this embodiment) having four sides parallel to the periphery of the chip 2 in a plan view, and surrounds a plurality of trench gate structures 15.

[0036] The outer well region 42 may have an edge portion that connects the portion extending in the first direction X and the portion extending in the second direction Y in an arc shape (preferably a quadrant arc shape). In this embodiment, the outer well region 42 is formed in the peripheral region 9 and surrounds the active region 8. In other words, the outer well region 42 is formed in the peripheral region 9, inside the multiple field regions 43, along the peripheral boundary 19 between the active region 8 and the peripheral region 9.

[0037] The semiconductor device 1A includes a plurality of p-type field regions 43 formed in the peripheral region 9.

[0038] Each of the plurality of field regions 43 has a portion extending in the first direction X and a portion extending in the second direction Y. In this embodiment, each field region 43 is formed in a polygonal ring shape (a square ring in this embodiment) having four sides parallel to the periphery of the chip 2 in a plan view, and surrounds the outer well region 42.

[0039] Each of the plurality of field regions 43 may have an edge portion that connects the portion extending in the first direction X and the portion extending in the second direction Y in an arc shape (preferably a quadrant arc shape). In this embodiment, the plurality of field regions 43 are arranged in the outer periphery region 9 at intervals outward from the outer well region 42.

[0040] 2, semiconductor device 1A includes an insulating interlayer film 47 formed on first main surface 3. Interlayer film 47 may be referred to as an "insulating film," an "interlayer insulating film," an "intermediate insulating film," or the like. Interlayer film 47 may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. Interlayer film 47 preferably includes a silicon oxide film.

[0041] 1 and 2 , semiconductor device 1A includes a source electrode 51 disposed on first main surface 3. Source electrode 51 is a terminal electrode to which a source potential is applied from the outside. Source electrode 51 may also be referred to as a "source pad electrode," a "first pad electrode," a "first main surface electrode," a "first terminal electrode," or the like. Source electrode 51 is disposed on a portion of interlayer film 47 that covers active region 8.

[0042] In this embodiment, the source electrode 51 has a first pad portion 51 a, a second pad portion 51 b, and a third pad portion 51 c. The first pad portion 51 a has a relatively large planar area and forms the main body of the source electrode 51. In this embodiment, the first pad portion 51 a is formed in a polygonal shape (a quadrangle in this embodiment) having four sides parallel to the periphery of the chip 2 in a plan view, and is located closer to the fourth side surface 5D than the center of the first main surface 3.

[0043] The second pad portion 51b has a planar area smaller than that of the first pad portion 51a, and extends in a strip shape (rectangular) from one end of the first pad portion 51a in the second direction Y (the end on the first side surface 5A side) toward the third side surface 5C. The third pad portion 51c has a planar area smaller than that of the first pad portion 51a, and extends in a strip shape (rectangular) from the other end of the first pad portion 51a in the second direction Y (the end on the second side surface 5B side) toward the third side surface 5C, and faces the second pad portion 51b in the second direction Y.

[0044] The plane area of ​​the third pad portion 51c may be approximately equal to the plane area of ​​the second pad portion 51b. The plane area of ​​the third pad portion 51c may be larger than the plane area of ​​the second pad portion 51b, or may be smaller than the plane area of ​​the second pad portion 51b. Either or both of the second pad portion 51b and the third pad portion 51c may be used as a terminal portion for monitoring current.

[0045] The source electrode 51 does not necessarily have to have both the second pad portion 51 b and the third pad portion 51 c at the same time. The source electrode 51 may have only one of the second pad portion 51 b and the third pad portion 51 c. The source electrode 51 may be composed of only the first pad portion 51 a, and may not have both the second pad portion 51 b and the third pad portion 51 c.

[0046] The semiconductor device 1A includes a source wiring 56 arranged around the source electrode 51 on the interlayer film 47. The same potential (source potential) as the potential (source potential) applied to the source electrode 51 is applied to the source wiring 56. The source wiring 56 may also be referred to as a "termination electrode (wiring)," "wiring," "first wiring," "finger electrode," "source finger," or the like.

[0047] The source wiring 56 has a wiring width less than the electrode width of the source electrode 51, and is selectively routed on the interlayer film 47. In this embodiment, the source wiring 56 is drawn from the source electrode 51 (first pad portion 51 a) to the fourth side surface 5D. The source wiring 56 is drawn from the active region 8 to the peripheral region 9.

[0048] The source wiring 56 extends in a strip shape along the periphery of the first main surface 3 (the periphery of the active region 8). In this embodiment, the source wiring 56 is formed in a polygonal ring shape (a square ring shape in this embodiment) having four sides parallel to the periphery of the chip 2 in a plan view, and surrounds the inner part of the first main surface 3 (the active region 8). The source wiring 56 may have an edge portion that connects the portion extending in the first direction X and the portion extending in the second direction Y in an arc shape (preferably a quadrant arc shape). The source wiring 56 may be either ended or endless.

[0049] The semiconductor device 1A includes a gate electrode 57 disposed on the first main surface 3. The gate electrode 57 is a terminal electrode to which a gate potential is applied from the outside. The gate electrode 57 may also be referred to as a "second pad electrode," a "second main surface electrode," a "second terminal electrode," or the like.

[0050] The gate electrode 57 is disposed on a portion of the interlayer film 47 that covers the active region 8, with a gap between it and the source electrode 51. In this embodiment, the gate electrode 57 is disposed in a region on the third side surface 5C side of the first pad portion 51a, and faces the first pad portion 51a in the first direction X. The gate electrode 57 is interposed in a region between the second pad portion 51b and the third pad portion 51c, and faces both the second pad portion 51b and the third pad portion 51c in the second direction Y.

[0051] The gate electrode 57 is formed in a polygonal shape (a quadrilateral shape in this embodiment) having four sides parallel to the periphery of the chip 2 in a plan view. The gate electrode 57 has a planar area less than the planar area of ​​the source electrode 51. The gate electrode 57 has a planar area less than the planar area of ​​the first pad portion 51a. The gate electrode 57 may also have a planar area less than the planar area of ​​the second pad portion 51b (third pad portion 51c).

[0052] The semiconductor device 1A includes a gate wiring 58 extending from the gate electrode 57 onto the first main surface 3. The gate wiring 58 may also be referred to as a "wiring," a "second wiring," a "finger electrode," a "gate finger," or the like. The gate wiring 58 transmits the gate potential applied to the gate electrode 57 to other regions.

[0053] The gate wiring 58 is drawn out from the gate electrode 57 onto the portion of the interlayer film 47 that covers the active region 8, and is routed to the region between the source electrode 51 and the source wiring 56 at a distance from the source electrode 51 and the source wiring 56.

[0054] The gate wiring 58 has a portion extending in a strip shape in the first direction X in a plan view and a portion extending in a strip shape in the second direction Y, and intersects (specifically, orthogonally intersects) with ends (both ends in this embodiment) of the plurality of trench gate structures 15. In this embodiment, the gate wiring 58 is formed in the shape of a strip with ends having four sides parallel to the periphery of the first main surface 3, and surrounds the source electrode 51.

[0055] The semiconductor device 1A includes a drain electrode 59 covering the second main surface 4. The drain electrode 59 is a terminal electrode to which a drain potential is applied from the outside. The drain electrode 59 may also be referred to as a "third pad electrode," a "third main surface electrode," a "third terminal electrode," or the like.

[0056] The drain electrode 59 is electrically connected to the first semiconductor region 6. The drain electrode 59 may cover the entire second main surface 4 so as to be continuous with the periphery (first to fourth side surfaces 5A to 5D) of the second main surface 4. The drain electrode 59 may also cover a portion of the second main surface 4 so as to expose the periphery of the second main surface 4.

[0057] A breakdown voltage that can be applied between source electrode 51 and drain electrode 59 (between first main surface 3 and second main surface 4) may be 500 V or more and 3000 V or less. The breakdown voltage may have a value belonging to at least one of the ranges of 500 V or more and 750 V or less, 750 V or more and 1000 V or less, 1000 V or more and 1250 V or less, 1250 V or more and 1500 V or less, 1500 V or more and 1750 V or less, 1750 V or more and 2000 V or less, 2000 V or more and 2250 V or less, 2250 V or more and 2500 V or less, 2500 V or more and 2750 V or less, and 2750 V or more and 3000 V or less.

[0058] FIG. 5 is an enlarged plan view showing a main portion of the first main surface 3 shown in FIG. 3. FIG. 6 is an enlarged plan view showing a main portion of the first main surface 3 shown in FIG. 3. FIG. 7 is a cross-sectional view taken along line VII-VII shown in FIG. 5. FIG. 8 is a cross-sectional view taken along line VIII-VIII shown in FIG. 5. FIG. 9 is a cross-sectional view taken along line IX-IX shown in FIG. 6. FIG. 10 is a cross-sectional view showing a cross-sectional structure of the outer peripheral region 9 taken along line XX shown in FIG. 1. FIG. 11 is an enlarged cross-sectional view of one region shown in FIG. 10. FIG. 12 is a plan view showing an example layout of the chip 2.

[0059] The transistor structure Tr formed in the active region 8 of the semiconductor device 1A and the configuration within the peripheral region 9 will be described with reference to FIGS.

[0060] The semiconductor device 1A includes a p-type body region 10 formed in the active region 8 (inner portion of the first main surface 3) in a surface layer portion of the first main surface 3. The body region 10 may also be referred to as an "impurity region," a "channel region," or the like. A source potential may be applied to the body region 10. The source potential may be a reference potential that serves as a reference for circuit operation. The reference potential may be a ground potential. The body region 10 has a p-type impurity concentration that is higher than the n-type impurity concentration of the second semiconductor region 7. The body region 10 has a p-type impurity concentration of, for example, 1×10 １７ cm －３ 1x10 or more １８ cm －３ The p-type impurity concentration may have the following peak value:

[0061] 10 , the body region 10 is formed in the inner portion of the first main surface 3 at a distance from the periphery (first to fourth side surfaces 5A to 5D) of the first main surface 3, and is not formed in the outer peripheral region 9. In this embodiment, the body region 10 is formed throughout the active region 8. The body region 10 is formed in the surface layer portion of the second semiconductor region 7, and extends in a layered form along the first main surface 3.

[0062] 7 to 10 , the body region 10 is formed at a distance from the bottom of the second semiconductor region 7 (first semiconductor region 6) toward the first main surface 3, and faces the first semiconductor region 6 across a part of the second semiconductor region 7. The body region 10 is formed at a distance from a depth position of the middle part of the second semiconductor region 7 toward the first main surface 3.

[0063] The body region 10 is formed in a region on the first main surface 3 side of the second semiconductor region 7 in a cross-sectional view, and is electrically connected to the second semiconductor region 7. The body region 10 forms a pn junction (body diode) with the second semiconductor region 7. The body region 10 spreads a depletion layer into the second semiconductor region 7 when a reverse bias voltage is applied. The depletion layer originating in the body region 10 spreads in the horizontal direction and thickness direction within the second semiconductor region 7.

[0064] 6 , 7 and 9 , semiconductor device 1A includes an n-type source region 11 formed in a surface layer portion of first main surface 3 in active region 8. A source potential is applied to source region 11. Source region 11 has an n-type impurity concentration higher than the n-type impurity concentration of second semiconductor region 7. The n-type impurity concentration of source region 11 is higher than the p-type impurity concentration of body region 10.

[0065] The source region 11 is formed in an inner portion of the first main surface 3 at a distance from the periphery (first to fourth side surfaces 5A to 5D) of the first main surface 3, and is not formed in the outer peripheral region 9. The source region 11 may be formed inwardly at a distance from the periphery of the body region 10. The source region 11 is formed in a surface layer portion of the body region 10, and extends in a layered form along the first main surface 3.

[0066] The source region 11 is formed at a distance from the bottom of the body region 10 toward the first main surface 3, and faces the second semiconductor region 7 across a part of the body region 10. The source region 11 is formed in a region on the first main surface 3 side of the body region 10 in a cross-sectional view, and is electrically connected to the body region 10.

[0067] 6 to 9 , the semiconductor device 1A includes a plurality of trench-type (trench electrode-type) trench gate structures 15 formed in an inner portion of the first main surface 3. The trench gate structures 15 may also be referred to as "trench structures," "gate structures," or the like. A gate potential (gate signal) serving as a control potential is applied to the plurality of trench gate structures 15. The plurality of trench gate structures 15 controls inversion and non-inversion of the channel in the body region 10 in response to the gate potential.

[0068] The plurality of trench gate structures 15 are formed in an inner portion of the first main surface 3 at intervals from the periphery (first to fourth side surfaces 5A to 5D) of the first main surface 3, and are not formed in the outer peripheral region 9. The plurality of trench gate structures 15 are arranged at intervals in a first direction X (= m-axis direction) in a plan view, and each extend in a band shape in a second direction Y (= a-axis direction). The plurality of trench gate structures 15 are arranged in a stripe shape extending in the second direction Y in a plan view.

[0069] The extension direction of the plurality of trench gate structures 15 coincides with the off-direction of the SiC single crystal. With respect to the second direction Y, both ends of the plurality of trench gate structures 15 may be located in a region between the peripheral edge of the body region 10 and the peripheral edge of the source region 11. The plurality of trench gate structures 15 may be arranged at intervals in the second direction Y in a plan view, and each extend in a strip shape in the first direction X.

[0070] The plurality of trench gate structures 15 penetrates the body region 10 and the source region 11 to reach the second semiconductor region 7. The plurality of trench gate structures 15 are formed at intervals from the depth position of the bottom of the second semiconductor region 7 toward the first main surface 3, and face the first semiconductor region 6 with a part of the second semiconductor region 7 in between.

[0071] The plurality of trench gate structures 15 may be formed at intervals from a depth position of an intermediate portion of the second semiconductor region 7 toward the first main surface 3, or may be located on the bottom side of the second semiconductor region 7 with respect to the depth position of the intermediate portion of the second semiconductor region 7. The plurality of trench gate structures 15 are formed substantially perpendicular to the first main surface 3. The plurality of trench gate structures 15 may be formed in a shape tapering toward the bottom of the second semiconductor region 7.

[0072] The side walls (long sides) of the plurality of trench gate structures 15 are formed by the m-plane ((1-100) plane) of the SiC single crystal. The side walls (long sides) of the plurality of trench gate structures 15 may be formed by the a-plane ((11-20) plane) of the SiC single crystal depending on the extension direction of the trench gate structures 15. The bottom walls of the plurality of trench gate structures 15 are formed by the c-plane (Si-plane) of the SiC single crystal. It is preferable that the bottom walls of the plurality of trench gate structures 15 extend substantially flat along the horizontal direction. The bottom walls of the plurality of trench gate structures 15 may be curved in an arc shape toward the second main surface 4.

[0073] The inclination angle (absolute value) of the sidewall (long side) of the trench gate structure 15 relative to the vertical line may be 85° or more and 95° or less. The inclination angle may have a value belonging to at least one of the ranges of 85° or more and 87.5° or less, 87.5° or more and 90° or less, 90° or more and 92.5° or less, and 92.5° or more and 95° or less. The inclination angle is preferably 87° or more and 93° or less.

[0074] The trench gate structure 15 may have a width of 0.1 μm to 2 μm, and may have a width in at least one range of 0.1 μm to 0.25 μm, 0.25 μm to 0.5 μm, 0.5 μm to 0.75 μm, 0.75 μm to 1 μm, 1 μm to 1.25 μm, 1.25 μm to 1.5 μm, 1.5 μm to 1.75 μm, or 1.75 μm to 2 μm.

[0075] The trench gate structure 15 may have a depth of 0.1 μm or more and 3 μm or less. The depth of the trench gate structure 15 is measured from the first main surface 3. The depth of the trench gate structure 15 may have a value belonging to at least one of the ranges of 0.1 μm or more and 0.5 μm or less, 0.5 μm or more and 1 μm or less, 1 μm or more and 1.5 μm or less, 1.5 μm or more and 2 μm or less, 2 μm or more and 2.5 μm or less, and 2.5 μm or more and 3 μm or less. The depth of the trench gate structure 15 is preferably 0.5 μm or more and 1.5 μm or less.

[0076] The trench gate structure 15 may have an aspect ratio of 1 to 3. The aspect ratio of the trench gate structure 15 is the ratio of the depth of the trench gate structure 15 to the width of the trench gate structure 15. The aspect ratio may have a value belonging to at least one of the ranges of 1 to 1.25, 1.25 to 1.5, 1.5 to 1.75, 1.75 to 2, 2 to 2.25, 2.25 to 2.5, 2.5 to 2.75, and 2.75 to 3. The aspect ratio is preferably 1.5 to 2.5.

[0077] Each of the trench gate structures 15 includes a gate trench 16, a gate insulating film 17, and a first buried electrode 18. The gate trench 16 is formed in the first main surface 3 and defines the wall surfaces (side walls and bottom wall) of the trench gate structure 15.

[0078] The gate insulating film 17 may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. In this embodiment, the gate insulating film 17 has a single-layer structure made of a silicon oxide film. It is particularly preferable that the gate insulating film 17 includes a silicon oxide film made of an oxide of the chip 2.

[0079] The gate insulating film 17 covers the wall surface of the gate trench 16. The gate insulating film 17 includes a first film portion and a second film portion. The first film portion covers the side wall of the gate trench 16 in a film-like manner. The second film portion covers the bottom wall of the gate trench 16 in a film-like manner and is continuous with the first film portion. The second film portion has a thickness greater than that of the first film portion. The thickness of the second film portion may be approximately equal to the thickness of the first film portion.

[0080] The gate insulating film 17 may have a thickness of 10 nm to 150 nm, and may have a thickness in at least one range of 10 nm to 25 nm, 25 nm to 50 nm, 50 nm to 75 nm, 75 nm to 100 nm, 100 nm to 125 nm, and 125 nm to 150 nm.

[0081] The first buried electrode 18 is buried in the gate trench 16 with the gate insulating film 17 sandwiched therebetween. The first buried electrode 18 may include either p-type conductive polysilicon or n-type conductive polysilicon, or both. The first buried electrode 18 faces the second semiconductor region 7, the body region 10, and the source region 11 with the gate insulating film 17 sandwiched therebetween.

[0082] The first buried electrode 18 has an electrode surface exposed from the gate trench 16. The electrode surface is located closer to the bottom wall of the gate trench 16 with respect to the height position of the first main surface 3. The electrode surface is located closer to the first main surface 3 with respect to the depth position of the bottom of the source region 11. The electrode surface has a recess in an inner portion that tapers toward the bottom wall of the gate trench 16.

[0083] 7 to 9, semiconductor device 1A includes gate well regions 25 formed in regions below a plurality of trench gate structures 15 in chip 2 (second semiconductor region 7) of active region 8. Gate well regions 25 may also be referred to as "first well regions" or the like.

[0084] A source potential is applied to the gate well region 25. The gate well region 25 has a p-type impurity concentration higher than the n-type impurity concentration of the second semiconductor region 7. The p-type impurity concentration of the gate well region 25 may be higher than the p-type impurity concentration of the body region 10, or may be lower than the p-type impurity concentration of the body region 10. The p-type impurity (trivalent element) of the gate well region 25 is preferably aluminum.

[0085] The multiple gate well regions 25 are formed in the second semiconductor region 7 in regions below (specifically, directly below) the multiple trench gate structures 15, spaced apart from one another in the horizontal direction (first direction X). The multiple gate well regions 25 are formed in the thickness range between the bottom of the second semiconductor region 7 and the bottom walls of the multiple trench gate structures 15, and overlap the multiple trench gate structures 15 in a one-to-one correspondence in the thickness direction.

[0086] The multiple gate well regions 25 each extend in a strip shape in the second direction Y in plan view, following the extension direction of the corresponding trench gate structure 15. In other words, the multiple gate well regions 25 are arranged in stripes extending in the second direction Y in plan view.

[0087] The extension direction of the multiple gate well regions 25 coincides with the off-direction of the SiC single crystal. The multiple gate well regions 25 may extend in the first direction X according to the extension direction of the multiple trench gate structures 15. In this case, the multiple gate well regions 25 intersect (specifically, are perpendicular to) the off-direction.

[0088] The plurality of gate well regions 25 are formed at intervals from the bottom of the second semiconductor region 7 toward the bottom wall sides of the plurality of trench gate structures 15, and face the first semiconductor region 6 across a part of the second semiconductor region 7. The plurality of gate well regions 25 each have an upper end located on the bottom wall side of the corresponding trench gate structure 15, and a bottom located on the bottom side of the second semiconductor region 7 (the side of the second main surface 4).

[0089] The upper ends of the plurality of gate well regions 25 are formed at intervals from the bottom of the body region 10 toward the bottom wall of the corresponding trench gate structure 15. The upper ends of the plurality of gate well regions 25 may be connected to the bottom wall of the corresponding trench gate structure 15. The upper ends of the plurality of gate well regions 25 may have portions that extend along the sidewall of the corresponding trench gate structure 15. The upper ends of the plurality of gate well regions 25 may be formed at intervals from the bottom wall of the corresponding trench gate structure 15 toward the bottom of the second semiconductor region 7.

[0090] The bottoms of the multiple gate well regions 25 may be located on the bottom wall side of the multiple trench gate structures 15 relative to the intermediate portion of the second semiconductor region 7, or may be located on the bottom side of the second semiconductor region 7 (the side facing the second main surface 4) relative to the intermediate portion of the second semiconductor region 7.

[0091] Each of the plurality of gate well regions 25 has a bulging portion 25 a. The bulging portion 25 a extends in an arc shape in the horizontal direction from a region directly below the corresponding trench gate structure 15 to both sides of the corresponding trench gate structure 15. Each of the plurality of gate well regions 25 is formed in a tapered shape from the bulging portion 25 a to the bottom.

[0092] The gate well region 25 may have a width greater than or less than the width of the trench gate structure 15. The width of the gate well region 25 may be 0.1 μm or more and 2 μm or less. The width of the gate well region 25 may have a value belonging to at least one of the ranges of 0.1 μm or more and 0.25 μm or less, 0.25 μm or more and 0.5 μm or less, 0.5 μm or more and 0.75 μm or less, 0.75 μm or more and 1 μm or less, 1 μm or more and 1.25 μm or less, 1.25 μm or more and 1.5 μm or less, 1.5 μm or more and 1.75 μm or less, and 1.75 μm or more and 2 μm or less.

[0093] The gate well region 25 may have a depth less than the depth of the trench gate structure 15, or may have a depth greater than the depth of the trench gate structure 15. The depth of the gate well region 25 is the depth of the gate well region 25 when the bottom wall of the trench gate structure 15 is used as the reference.

[0094] The depth of the gate well region 25 may be greater than 0 μm and less than or equal to 5 μm. The depth of the gate well region 25 may have a value belonging to at least one of the following ranges: greater than 0 μm and less than or equal to 1 μm, 1 μm to 1.5 μm, 1.5 μm to 2 μm, 2 μm to 2.5 μm, 2.5 μm to 3 μm, 3 μm to 3.5 μm, 3.5 μm to 4 μm, 4 μm to 4.5 μm, and 4.5 μm to 5 μm.

[0095] The gate well region 25 may have an aspect ratio greater than 0 and less than or equal to 2. The aspect ratio of the gate well region 25 is the ratio of the depth of the gate well region 25 to the width of the gate well region 25.

[0096] The aspect ratio may have a value belonging to at least one of the ranges of greater than 0 and less than or equal to 0.25, 0.25 or more and less than or equal to 0.5, 0.5 or more and less than or equal to 0.75, 0.75 or more and less than or equal to 1, 1 or more and less than or equal to 1.25, 1.25 or more and less than or equal to 1.5, 1.5 or more and less than or equal to 1.75, and 1.75 or more and less than or equal to 2.

[0097] The gate well region 25 forms a pn junction with the second semiconductor region 7. When a reverse bias voltage is applied, the gate well region 25 spreads a depletion layer into the second semiconductor region 7. The depletion layer originating from the gate well region 25 spreads in the horizontal and thickness directions, and reduces the electric field with respect to the active region 8 (trench gate structure 15).

[0098] 5, 6, and 8, the semiconductor device 1A includes a plurality of gate contact regions 27 formed in the chip 2 (second semiconductor region 7) in the active region 8. The gate contact regions 27 may also be referred to as "first contact regions," etc. A source potential is applied to the gate contact regions 27.

[0099] The gate contact region 27 has a p-type impurity concentration higher than the n-type impurity concentration of the second semiconductor region 7. The p-type impurity concentration of the gate contact region 27 is higher than the p-type impurity concentration of the body region 10. The p-type impurity concentration of the gate contact region 27 is higher than the p-type impurity concentration of the gate well region 25.

[0100] The plurality of gate contact regions 27 are formed at intervals in regions along the plurality of trench gate structures 15. The plurality of gate contact regions 27 are formed in a one-to-many correspondence with the plurality of trench gate structures 15. The plurality of gate contact regions 27 are formed at intervals in the second direction Y following the extension direction of the corresponding trench gate structures 15.

[0101] With respect to one and the other trench gate structures 15, the multiple gate contact regions 27 along one trench gate structure 15 face the multiple gate contact regions 27 along the other trench gate structure 15 in the first direction X in plan view. In other words, the multiple gate contact regions 27 are generally arranged in a matrix at intervals in the first direction X and the second direction Y in plan view.

[0102] In plan view, one of the plurality of gate contact regions 27 may face, in the first direction X, a region between the other of the plurality of gate contact regions 27. In other words, the plurality of gate contact regions 27 may be generally arranged in a staggered pattern at intervals in the first direction X and the second direction Y in plan view.

[0103] In this embodiment, the gate contact regions 27 extend in a strip shape along the trench gate structures 15 in a plan view. The lengths of the gate contact regions 27 in the second direction Y may be equal to or different from one another. The lengths of the gate contact regions 27 in the second direction Y are adjusted depending on the channel area to be formed.

[0104] The channel area is the total area of ​​the portions of the source region 11 exposed from the plurality of gate contact regions 27. That is, the channel area increases or decreases depending on the ratio of the total planar area of ​​the plurality of gate contact regions 27. The total planar area of ​​the plurality of gate contact regions 27 is preferably less than the channel area.

[0105] That is, in the region between a pair of adjacent trench gate structures 15, the total planar area of ​​the multiple gate contact regions 27 is preferably less than the planar area of ​​the source region 11. With this configuration, an increase in the resistance value (on-resistance) due to a short channel is suppressed.

[0106] The length of the gate contact region 27 may be greater than the width of the trench gate structure 15 or may be smaller than the width of the trench gate structure 15. The length of the gate contact region 27 may be greater than the pitch of the trench gate structures 15 or may be smaller than the pitch of the trench gate structures 15. The length of the gate contact region 27 may be greater than the pitch of two adjacent trench gate structures 15 or may be smaller than the pitch of two adjacent trench gate structures 15.

[0107] The interval between the multiple gate contact regions 27 may be greater than the width of the trench gate structures 15 or may be smaller than the width of the trench gate structures 15. The interval between the gate contact regions 27 may be greater than the pitch of the trench gate structures 15 or may be smaller than the pitch of the trench gate structures 15. The interval between the gate contact regions 27 may be greater than the pitch of two adjacent trench gate structures 15 or may be smaller than the pitch of two adjacent trench gate structures 15.

[0108] The plurality of gate contact regions 27 are respectively interposed in regions between the bottom walls of the plurality of trench gate structures 15 and the bottoms of the plurality of gate well regions 25. The plurality of gate contact regions 27 are connected to the bottom walls of the corresponding trench gate structures 15 and the corresponding gate well regions 25.

[0109] The plurality of gate contact regions 27 increase the p-type impurity concentration at the upper end of the corresponding gate well region 25. The gate contact regions 27 extend from the region directly below the trench gate structure 15 to both sides of the trench gate structure 15 and have extensions that extend along the sidewalls of the trench gate structure 15.

[0110] The thickness in the horizontal direction (first direction X) of the portion (extension) of the gate contact region 27 that runs along the side wall of the trench gate structure 15 may be less than the thickness in the vertical direction Z of the portion of the gate contact region 27 that runs along the bottom wall of the trench gate structure 15.

[0111] The extension of the gate contact region 27 is electrically connected to the body region 10 in the surface layer portion of the first main surface 3, and electrically connects the corresponding gate well region 25 to the body region 10. This prevents the gate well region 25 from being electrically floating, and improves the electrical response characteristics of the gate well region 25.

[0112] The gate contact region 27 has an upper end exposed from the first main surface 3. In this embodiment, the upper end of the gate contact region 27 is exposed from the sidewall of the gate trench 16 at the opening end of the gate trench 16. The upper end of the gate contact region 27 may extend horizontally in the surface portion of the body region 10.

[0113] The second semiconductor region 7 of the semiconductor device 1A includes a stacked structure of a base region 71 and a high concentration region 72 .

[0114] The base region 71 is formed closer to the second main surface 4 than the gate well region 25 and away from the body region 10. The base region 71 is formed in a layer shape extending along the first main surface 3 at a position away from the body region 10 and the gate trench 16 toward the second main surface 4. The base region 71 is formed over the entire surface layer portion of the second semiconductor region 7 on the second main surface 4 side, and may be exposed from the first to fourth side surfaces 5A to 5D. The base region 71 forms a boundary surface between the second semiconductor region 7 and the first semiconductor region 6.

[0115] The thickness of the base region 71 may be, for example, not less than 0.5 μm and not more than 20 μm, and is preferably not less than 1 μm and not more than 10 μm.

[0116] The n-type impurity concentration of the base region 71 is preferably lower than the n-type impurity concentration of the first semiconductor region 6. The base region 71 has a dopant concentration of 1×10 １６ cm －３ 1x10 or more １７ cm －３ The n-type impurity concentration of the base region 71 may have a peak value of the following: The n-type impurity concentration of the base region 71 may be substantially constant in the thickness direction. Of course, the n-type impurity concentration of the base region 71 may have a concentration gradient that gradually increases and / or decreases in the thickness direction (crystal growth direction) of the chip 2.

[0117] The high concentration region 72 is formed between the base region 71 and the body region 10, on the side of the gate trench 16 and the gate well region 25. The high concentration region 72 is in contact with the body region 10 and the gate well region 25 and is formed in a layer shape extending along the first main surface 3. The high concentration region 72 is formed in the entire surface layer portion of the second semiconductor region 7 on the first main surface 3 side, and may be exposed from the first to fourth side surfaces 5A to 5D. In this embodiment, the high concentration region 72 forms a boundary surface between the second semiconductor region 7 and the body region 10.

[0118] The thickness of the high concentration region 72 may be 0.1 μm or more and 0.5 μm or less, and is preferably 0.15 μm or more and 0.4 μm or less.

[0119] The n-type impurity concentration of the high concentration region 72 is preferably higher than the n-type impurity concentration of the base region 71. The high concentration region 72 has a concentration of 1×10 １７ cm －３ 1x10 or more １８ cm －３ The n-type impurity concentration of the high-concentration region 72 may have a peak value of the following: The n-type impurity concentration of the high-concentration region 72 may be substantially constant in the thickness direction. Of course, the n-type impurity concentration of the high-concentration region 72 may have a concentration gradient that gradually increases and / or decreases in the thickness direction (crystal growth direction) of the chip 2.

[0120] In this embodiment, the n-type impurity concentrations of the base region 71 and the high-concentration region 72 are adjusted by nitrogen. The base region 71 and the high-concentration region 72 may have n-type impurity concentrations adjusted by at least one pentavalent element. For example, the n-type impurity concentrations of the base region 71 and the high-concentration region 72 may be adjusted by at least one of nitrogen, phosphorus, arsenic, antimony, and bismuth.

[0121] 9, the outermost trench gate structure 15 among the plurality of trench gate structures 15 is a terminal trench gate structure 15A. In this embodiment, the plurality of trench gate structures 15 arranged in stripes extending along the second direction Y have one terminal trench gate structure 15A formed at the end of each of both sides (the third side surface 5C side and the fourth side surface 5D side) in the first direction X (see also FIGS. 3 and 4). FIG. 9 shows the terminal trench gate structure 15A on the fourth side surface 5D side.

[0122] In this embodiment, the terminal trench gate structure 15A includes a terminal gate trench 16A, a terminal gate insulating film 17A, and a terminal first buried electrode 18A. The terminal gate trench 16A is a boundary trench that forms a peripheral boundary 19, which is the boundary between the active region 8 and the peripheral region 9. The terminal trench gate structure 15A has the same structure as the remaining trench gate structures 15, except for its arrangement in stripes.

[0123] 10 and 11, the plurality of field regions 43 are formed in an electrically floating state. A source potential may be applied to the plurality of field regions 43.

[0124] The number of field regions 43 is arbitrary. The number of field regions 43 may be 1 or more and 15 or less. The number of field regions 43 may be 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, or 15. The number of field regions 43 is typically 1 or more and 10 or less. In this embodiment, the semiconductor device 1A includes, as an example, four field regions 43.

[0125] One field region 43 has a p-type impurity concentration higher than the n-type impurity concentration of the second semiconductor region 7. In this embodiment, the concentration of the field region 43 is 1×10 １５ cm －３ That is all. The p-type impurity concentration of the field region 43 may be approximately equal to the p-type impurity concentration of the outer well region 42. The p-type impurity concentration of the field region 43 may be higher than the p-type impurity concentration of the outer well region 42, or may be lower than the p-type impurity concentration of the outer well region 42.

[0126] The p-type impurity concentration of one field region 43 may be lower than the p-type impurity concentration of the gate contact region 27. The p-type impurity concentration of the field region 43 may be higher than the p-type impurity concentration of the gate well region 25, or may be lower than the p-type impurity concentration of the gate well region 25. The p-type impurity concentration of the field region 43 may be higher than the p-type impurity concentration of the body region 10, or may be lower than the p-type impurity concentration of the body region 10.

[0127] In this embodiment, the p-type impurity concentrations of the multiple field regions 43 are approximately equal to each other. The p-type impurity concentrations of the multiple field regions 43 are arbitrary and can take various values ​​depending on the electric field to be relaxed. The p-type impurity concentrations of the multiple field regions 43 may also be different from each other.

[0128] The plurality of field regions 43 are formed in a surface layer portion of the second semiconductor region 7 and are electrically connected to the second semiconductor region 7. The plurality of field regions 43 are formed at intervals from the bottom of the second semiconductor region 7 toward the first main surface 3, and face the first semiconductor region 6 across a part of the second semiconductor region 7. The plurality of field regions 43 are preferably formed at intervals from a depth position in the middle of the second semiconductor region 7 toward the first main surface 3.

[0129] 11 , the depth D2 of one field region 43 may be approximately equal to the depth D1 ( FIG. 9 ) of the outer well region 42. The depth D2 of the field region 43 may be deeper than the depth D1 of the outer well region 42, or may be shallower than the depth D1 of the outer well region 42.

[0130] Depth D2 of field region 43 may be, for example, greater than 0 μm and less than or equal to 4 μm. Depth D2 of field region 43 may have a value belonging to at least one of the following ranges: greater than 0 μm and less than or equal to 0.25 μm, 0.25 μm to 0.5 μm, 0.5 μm to 0.75 μm, 0.75 μm to 1 μm, 1 μm to 1.25 μm, 1.25 μm to 1.5 μm, 1.5 μm to 1.75 μm, 1.75 μm to 2 μm, 2 μm to 2.5 μm, 2.5 μm to 3 μm, 3 μm to 3.5 μm, 3.5 μm to 4 μm, 4 μm to 4.5 μm, 4.5 μm to 5 μm, 5 μm to 5.5 μm, and 4.5 μm to 5 μm. The depth D2 of the field region 43 is preferably 2.0 μm or more, and more preferably 4.0 μm to 5.0 μm.

[0131] When the field region 43 is spaced apart from the first major surface 3 toward the bottom side of the second semiconductor region 7 (when the field region 43 is not exposed from the first major surface 3), the depth D2 of the field region 43 may also be referred to as the thickness of the field region 43.

[0132] In this embodiment, the depths D2 of the field regions 43 are approximately equal to each other. The depths D2 of the field regions 43 are arbitrary and can take various values ​​depending on the electric field to be relaxed. The depths D2 of the field regions 43 may also be different from each other.

[0133] The depth D2 of the plurality of field regions 43 may increase sequentially toward the periphery of the first main surface 3. The depth D2 of the plurality of field regions 43 may increase toward the periphery of the first main surface 3 in units of two or more groups, each group including two or more field regions 43.

[0134] The depth D2 of the plurality of field regions 43 may decrease sequentially toward the periphery of the first main surface 3. The depth D2 of the plurality of field regions 43 may decrease toward the periphery of the first main surface 3 in units of two or more groups, each group including two or more field regions 43.

[0135] 10 and 11 , a plurality of field regions 43 are formed at intervals in the region between the periphery of the first main surface 3 and the terminal trench gate structure 15A (peripheral boundary portion 19). The plurality of field regions 43 are formed at intervals in the region between the periphery of the first main surface 3 and the outer well region 42.

[0136] The multiple field regions 43 include a first field region 43P, a second field region 43Q, a third field region 43R, and a fourth field region 43S. The first to fourth field regions 43P to 43S are arranged in this order in the direction from the active region 8 toward the peripheral region 9.

[0137] Referring to Figure 11, the field region 43 has a first upper end 43a on the first main surface 3 side, a first lower end 43b on the opposite side, and a first main body portion 43c between the first lower end 43b and the first upper end 43a.

[0138] The first upper end 43a extends horizontally along the first main surface 3 and is exposed from the first main surface 3. The first upper end 43a is located on the first main surface 3 side with respect to the depth position of the bottom of the trench gate structure 15. The first upper end 43a is located on the first main surface 3 side with respect to the depth position of the bottom of the gate well region 25 ( FIG. 10 ). The first upper end 43a is located on the first main surface 3 side with respect to the depth position of the bottom of the body region 10 ( FIG. 10 ). The first upper end 43a is located on the first main surface 3 side with respect to the depth position of a boundary 62 ( FIG. 10 ) between the high-concentration region 72 and the base region 71.

[0139] The first upper end 43a is formed in a shape that protrudes in an arc from the first body portion 43c toward the first main surface 3. The first upper end 43a includes a central portion 66 exposed from the first main surface 3, and an end portion 67 that is disposed at a position spaced from the first main surface 3 toward the bottom of the second semiconductor region 7.

[0140] A gap 68 is formed between an end 67 of the first upper end 43a and the first main surface 3. The gap 68 is a region defined between the flat first main surface 3 and the arc-shaped first upper end 43a. A part of the second semiconductor region 7 (in this embodiment, the base region 71) fits into the gap 68. This part of the second semiconductor region 7 is sandwiched between the first main surface 3 and the first upper end 43a.

[0141] The first lower end 43b extends horizontally along the first major surface 3 and forms a pn junction with the second semiconductor region 7. In this embodiment, the first lower end 43b forms a pn junction with the base region 71. The first lower end 43b is located on the bottom side of the second semiconductor region 7 relative to the depth position of the bottom of the trench gate structure 15. The first lower end 43b is located on the bottom side of the second semiconductor region 7 relative to the depth position of the bottom of the gate well region 25 ( FIG. 10 ). The first lower end 43b is located on the bottom side of the second semiconductor region 7 relative to the depth position of the bottom of the body region 10 ( FIG. 10 ). The first lower end 43b may have the same depth as the depth position of the boundary 62 between the high-concentration region 72 and the base region 71 as shown in FIG. 10 , or may be located on the bottom side of the second semiconductor region 7.

[0142] The first lower end 43b is formed in a flat shape that is approximately parallel to the first main surface 3. The first lower end 43b may be formed in a flat shape that extends in a direction perpendicular to the thickness direction of the second semiconductor region 7.

[0143] The first main body portion 43c is sandwiched between the first upper end portion 43a and the first lower end portion 43b. The first main body portion 43c includes a pair of first side portions 43d, 43e connecting the first upper end portion 43a and the first lower end portion 43b. The pair of first side portions 43d, 43e includes an inner side portion 43d close to the active region 8 and an outer side portion 43e far from the active region 8. In this embodiment, the inner side portion 43d is inclined from the first upper end portion 43a toward the first lower end portion 43b. The outer side portion 43e is inclined from the first upper end portion 43a toward the first lower end portion 43b.

[0144] 11 shows a cross-sectional view of the chip 2 taken along the X direction (the m-axis direction ([1-100] direction) of the SiC single crystal) across the active region 8, in which cross sections of multiple field regions 43 appear on both sides of the active region 8. In this cross-sectional view, the pair of first side portions 43d, 43e approach each other at an equal inclination angle from the first upper end portion 43a toward the first lower end portion 43b.

[0145] 10 and 11, for example, the field region 43 may be formed in a mesa shape in cross section having first side portions 43d, 43e that slope so that the width W narrows from the first upper end portion 43a toward the first lower end portion 43b.

[0146] The field regions 43 may have a width W that is less than the width W11 ( FIG. 9 ) of the outer well region 42. The width W of the field regions 43 is arbitrary and may take various values ​​depending on the electric field to be relaxed. The width W of each of the field regions 43 (e.g., the width of the first lower end 43 b) may be smaller than the width of the trench gate structure 15 ( FIG. 10 ) or larger than the width of the trench gate structure 15. The width W of the field region 43 may be smaller than the width of the gate well region 25 ( FIG. 10 ) or larger than the width of the gate well region 25.

[0147] The width W of field region 43 may be greater than 0 μm and less than or equal to 5 μm. The width W of field region 43 may have a value belonging to at least one of the following ranges: greater than 0 μm and less than or equal to 0.25 μm, 0.25 μm to 0.5 μm, 0.5 μm to 0.75 μm, 0.75 μm to 1 μm, 1 μm to 1.25 μm, 1.25 μm to 1.5 μm, 1.5 μm to 1.75 μm, 1.75 μm to 2 μm, 2 μm to 2.5 μm, 2.5 μm to 3 μm, 3 μm to 3.5 μm, 3.5 μm to 4 μm, 4 μm to 4.5 μm, and 4.5 μm to 5 μm.

[0148] The width W of the first field region 43P (e.g., the width of the first bottom end 43b) is a first width W1. The width W of the second field region 43Q (e.g., the width of the first bottom end 43b) is a second width W2. The width W of the third field region 43R (e.g., the width of the first bottom end 43b) is a third width W3. The width W of the fourth field region 43S (e.g., the width of the first bottom end 43b) is a fourth width W4.

[0149] The spacing W between the multiple field regions 43 decreases successively toward the peripheral edge of the first main surface 3. Specifically, the second width W2 is narrower than the first width W1 (W2<W1). The third width W3 is narrower than the second width W2 (W3<W2). The fourth width W4 is narrower than the third width W3 (W4<W3). In other words, the width W of each of the multiple field regions 43 narrows in the direction from the active region 8 toward the peripheral region 9.

[0150] The spacing S between the plurality of field regions 43 is arbitrary and can take various values ​​depending on the electric field to be relaxed.

[0151] The spacing S between field regions 43 may be greater than 0 μm and less than or equal to 5 μm. The spacing may have a value belonging to at least one of the following ranges: greater than 0 μm and less than or equal to 0.5 μm, 0.5 μm to 1 μm, 1 μm to 1.5 μm, 1.5 μm to 2 μm, 2 μm to 2.5 μm, 2.5 μm to 3 μm, 3 μm to 3.5 μm, 3.5 μm to 4 μm, 4 μm to 4.5 μm, and 4.5 μm to 5 μm.

[0152] The distance S between the first field region 43P and the second field region 43Q (for example, the distance between adjacent first bottom ends 43b) is a first distance S1. The distance S between the second field region 43Q and the third field region 43R (for example, the distance between adjacent first bottom ends 43b) is a second distance S2. The distance S between the third field region 43R and the fourth field region 43S (for example, the distance between adjacent first bottom ends 43b) is a third distance S3.

[0153] The spacing S between the multiple field regions 43 increases sequentially toward the peripheral edge of the first main surface 3. Specifically, the second spacing S2 is wider than the first spacing S1 (S2>S1). The third spacing S3 is wider than the second spacing S2 (S3>S2). In other words, the spacing W between the multiple field regions 43 increases in the direction from the active region 8 toward the peripheral region 9.

[0154] In this embodiment, the total length TL of the spacing S and width W of the multiple field regions 43 is constant in the direction from the active region 8 toward the peripheral region 9. Specifically, the total length TL of the first spacing S1 and first width W1 is equal to the total length TL of the second spacing S2 and second width W2. The total length TL of the second spacing S2 and second width W2 is equal to the total length TL of the third spacing S3 and third width W3.

[0155] The multiple field regions 43 expand the depletion layer into the second semiconductor region 7 when a reverse bias voltage is applied. The depletion layer originating from the multiple field regions 43 expands in the horizontal and thickness directions and merges with the depletion layer originating from the outer well region 42. The multiple field regions 43 expand the depletion layer originating from the outer well region 42 toward the periphery of the first main surface 3, thereby alleviating the electric field in the periphery (outer peripheral region 9) of the first main surface 3.

[0156] 10 , the distance between the first field region 43P, which is the innermost of the plurality of field regions 43, and the outer well region 42 (for example, the distance between the second lower end 42b and the first lower end 43b) is S0. In this embodiment, the distance S0 is narrower than the first distance S1 (S0<S1).

[0157] 6, 9 and 10, a source potential is applied to the p-type outer well region 42. The outer well region 42 has a p-type impurity concentration higher than the n-type impurity concentration of the second semiconductor region 7.

[0158] The p-type impurity concentration of the outer well region 42 is lower than the p-type impurity concentration of the gate well region 25. The p-type impurity concentration of the outer well region 42 is lower than the p-type impurity concentration of the gate contact region 27.

[0159] The p-type impurity concentration of the outer well region 42 may be approximately equal to the p-type impurity concentration of the gate well region 25. The p-type impurity concentration of the outer well region 42 may be higher than the p-type impurity concentration of the gate well region 25, or may be lower than the p-type impurity concentration of the gate well region 25.

[0160] The p-type impurity concentration of the outer well region 42 may be approximately equal to the p-type impurity concentration of the body region 10. It may be higher than the p-type impurity concentration of the body region 10, or may be lower than the p-type impurity concentration of the body region 10.

[0161] The outer well region 42 is formed in a surface layer portion of the second semiconductor region 7 and is electrically connected to the second semiconductor region 7. The outer well region 42 is formed at a distance from the bottom of the second semiconductor region 7 toward the first main surface 3, and faces the first semiconductor region 6 across a part of the second semiconductor region 7. The outer well region 42 is preferably formed at a distance from a depth position in the middle of the second semiconductor region 7 toward the first main surface 3.

[0162] The outer well region 42 is formed along the outer boundary portion 19, inside the plurality of field regions 43 in the outer periphery region 9. The outer well region 42 is formed deeper than the gate well region 25.

[0163] The depth D1 of the outer well region 42 may be, for example, greater than 0 μm and less than or equal to 4 μm. The depth D1 of the outer well region 42 may have a value belonging to at least one of the ranges of greater than 0 μm and less than or equal to 0.25 μm, 0.25 μm to 0.5 μm, 0.5 μm to 0.75 μm, 0.75 μm to 1 μm, 1 μm to 1.25 μm, 1.25 μm to 1.5 μm, 1.5 μm to 1.75 μm, 1.75 μm to 2 μm, 2 μm to 2.5 μm, 2.5 μm to 3 μm, 3 μm to 3.5 μm, and 3.5 μm to 4 μm.

[0164] When the outer well region 42 is disposed at a distance from the first main surface 3 toward the bottom of the second semiconductor region 7 (when the outer well region 42 is not exposed from the first main surface 3), the depth D1 of the outer well region 42 may be referred to as the thickness of the outer well region 42. Furthermore, the outer well region 42 may have approximately the same depth as the gate well region 25.

[0165] In the horizontal direction along the first main surface 3, the outer well region 42 at least partially covers the gate well region 25 of the terminal gate trench 16A.

[0166] More specifically, the gate well region 25 includes a well side portion (in this embodiment, a bulging portion 25a ( FIG. 9 )) extending in the thickness direction of the second semiconductor region 7, and a well bottom portion 25b extending from the bulging portion 25a in a direction along the first main surface 3. The outer well region 42 selectively covers the bulging portion 25a on the outer peripheral region 9 side (outside) of the gate well region 25 of the terminal gate trench 16A. The bulging portion 25a and the well bottom portion 25b on the active region 8 side (inside) that are not covered by the outer well region 42 are covered by the second semiconductor region 7 (high concentration region 72 in this embodiment).

[0167] Referring to Figure 9, the outer well region 42 has a second upper end portion 42a on the first main surface 3 side, a second lower end portion 42b on the opposite side, and a second main body portion 42c between the second lower end portion 42b and the second upper end portion 42a.

[0168] The second upper end 42a extends horizontally along the first main surface 3 and is exposed from the first main surface 3. The second upper end 42a is located on the first main surface 3 side with respect to the depth position of the bottom of the trench gate structure 15. The second upper end 42a is located on the first main surface 3 side with respect to the depth position of the bottom of the gate well region 25. The second upper end 42a is located on the first main surface 3 side with respect to the depth position of the bottom of the body region 10. The second upper end 42a is located on the first main surface 3 side with respect to the depth position of a boundary 62 between the high-concentration region 72 and the base region 71.

[0169] The second upper end 42a is formed in a shape that protrudes in an arc from the second body portion 42c toward the first main surface 3. The second upper end 42a includes a central portion 63 exposed from the first main surface 3, and an end 64 that is disposed at a position spaced from the first main surface 3 toward the bottom of the second semiconductor region 7.

[0170] A gap 65 is formed between an end 64 of the second upper end 42a and the first main surface 3. The gap 65 is a region defined between the flat first main surface 3 and the arc-shaped second upper end 42a. A part of the second semiconductor region 7 (in this embodiment, the base region 71) fits into the gap 65. This part of the second semiconductor region 7 is sandwiched between the first main surface 3 and the second upper end 42a.

[0171] The second lower end 42b extends horizontally along the first main surface 3 and forms a pn junction with the second semiconductor region 7. In this embodiment, the second lower end 42b forms a pn junction with the base region 71. The second lower end 42b is located on the bottom side of the second semiconductor region 7 with respect to the depth position of the bottom of the trench gate structure 15. The second lower end 42b is located on the bottom side of the second semiconductor region 7 with respect to the depth position of the bottom of the gate well region 25. The second lower end 42b is located on the bottom side of the second semiconductor region 7 with respect to the depth position of the bottom of the body region 10.

[0172] The second lower end 42b is formed in a flat shape that is approximately parallel to the first main surface 3. The second lower end 42b may be formed in a flat shape that extends in a direction perpendicular to the thickness direction of the second semiconductor region 7.

[0173] The second body portion 42c is sandwiched between the second upper end portion 42a and the second lower end portion 42b. The second body portion 42c may be a portion of the outer well region 42 that covers the trench gate structure 15 and the gate well region 25.

[0174] The second body portion 42c includes a second side portion 42d connecting the second upper end portion 42a and the second lower end portion 42b. In this embodiment, the second side portion 42d is inclined toward the active region 8 from the second upper end portion 42a toward the second lower end portion 42b. For example, the outer well region 42 may be formed in a mesa shape in cross section, having the second side portion 42d inclined such that the width W11 narrows from the second upper end portion 42a toward the second lower end portion 42b.

[0175] The outer well region 42 has a width W11 (for example, the width of the second lower end 42b) that is larger than the width of the trench gate structure 15. The width W11 of the outer well region 42 is larger than the width of the terminal trench gate structure 15A. The width W11 of the outer well region 42 may be larger than the total width of the multiple terminal trench gate structures 15A. The width W11 of the outer well region 42 may be larger than the total width of the multiple gate well regions 25.

[0176] The width W11 of the outer well region 42 may be greater than 0 μm and less than 300 μm. The width W11 of the outer well region 42 may have a value belonging to at least one of the ranges of greater than 0 μm and less than 25 μm, 25 μm to 50 μm, 50 μm to 75 μm, 75 μm to 100 μm, 100 μm to 125 μm, 125 μm to 150 μm, 150 μm to 175 μm, 175 μm to 200 μm, 200 μm to 225 μm, 225 μm to 250 μm, 250 μm to 275 μm, and 275 μm to 300 μm.

[0177] When a reverse bias voltage is applied, the outer well region 42 spreads a depletion layer into the second semiconductor region 7. The depletion layer originating in the outer well region 42 spreads in the horizontal and thickness directions, and alleviates the electric field in the vicinity of the peripheral boundary 19 between the active region 8 and the peripheral region 9.

[0178] The outer edge of the outer contact region 41 is formed at a distance from the outer edge of the outer well region 42 toward the terminal trench gate structure 15A. The outer contact region 41 may have a portion that crosses the outer edge of the outer well region 42 and is connected to the second semiconductor region 7.

[0179] The outer contact region 41 has a width greater than that of the gate well region 25. The width of the outer contact region 41 is greater than that of the terminal trench gate structure 15A. The width of the outer contact region 41 may be less than that of the outer well region 42. The width of the outer contact region 41 may be greater than that of the outer well region 42.

[0180] The width of the outer contact region 41 may be greater than 0 μm and less than 300 μm. The width of the outer contact region 41 may have a value belonging to at least one of the following ranges: greater than 0 μm and less than 25 μm, 25 μm to 50 μm, 50 μm to 75 μm, 75 μm to 100 μm, 100 μm to 125 μm, 125 μm to 150 μm, 150 μm to 175 μm, 175 μm to 200 μm, 200 μm to 225 μm, 225 μm to 250 μm, 250 μm to 275 μm, and 275 μm to 300 μm.

[0181] The outer contact region 41 has an upper end located on the first main surface 3 side and a bottom located on the bottom side of the outer well region 42. The upper end of the outer contact region 41 is exposed from the first main surface 3. The bottom of the outer contact region 41 is located on the first main surface 3 side with respect to the depth position of the bottom of the gate well region 25.

[0182] The bottom of the outer contact region 41 is located closer to the first main surface 3 than the depth position of the bottom of the outer well region 42. The bottom of the outer contact region 41 may be located closer to the first main surface 3 than the depth position of the bottom of the body region 10, or may be located closer to the bottom of the outer well region 42.

[0183] The depth (thickness) of the outer contact region 41 may be greater than 0 μm and less than or equal to 1 μm. The depth of the outer contact region 41 may have a value belonging to at least one of the following ranges: greater than 0 μm and less than or equal to 0.1 μm, 0.1 μm to 0.2 μm, 0.2 μm to 0.3 μm, 0.3 μm to 0.4 μm, 0.4 μm to 0.5 μm, 0.5 μm to 0.6 μm, 0.6 μm to 0.7 μm, 0.7 μm to 0.8 μm, 0.8 μm to 0.9 μm, and 0.9 μm to 1 μm.

[0184] 7 to 9, the semiconductor device 1A includes a main surface insulating film 45 that selectively covers the first main surface 3. The main surface insulating film 45 may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. The main surface insulating film 45 preferably includes the same type of insulating material as the gate insulating film 17. In this embodiment, the main surface insulating film 45 has a single-layer structure made of a silicon oxide film. It is particularly preferable that the main surface insulating film 45 includes a silicon oxide film made of an oxide of the chip 2.

[0185] The main surface insulating film 45 is connected to the gate insulating films 17 of the plurality of trench gate structures 15 in the active region 8 , and exposes the first buried electrodes 18 of the plurality of trench gate structures 15 .

[0186] The main surface insulating film 45 covers the second semiconductor region 7, the outer well region 42, the outer contact region 41, and the field region 43 in the peripheral region 9. In this embodiment, the main surface insulating film 45 is continuous with the first to fourth side surfaces 5A to 5D in the peripheral portion of the first main surface 3. The main surface insulating film 45 may be formed at a distance inward from the peripheral portion of the first main surface 3, exposing the peripheral portion of the first main surface 3 (the second semiconductor region 7).

[0187] The semiconductor device 1A includes an insulating interlayer film 47 that selectively covers the first main surface 3 with the main surface insulating film 45 sandwiched therebetween. The interlayer film 47 may also be referred to as an "insulating film," an "interlayer insulating film," an "intermediate insulating film," or the like. The interlayer film 47 may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. The interlayer film 47 preferably includes a silicon oxide film.

[0188] The interlayer film 47 covers the trench gate structures 15 (first buried electrodes 18) on the active region 8 side. The interlayer film 47 covers the second semiconductor region 7, the outer well region 42, the outer contact region 41, and the field region 43 on the peripheral region 9 side, with the main surface insulating film 45 sandwiched therebetween.

[0189] In this embodiment, the interlayer film 47 is continuous with the first to fourth side surfaces 5A to 5D at the peripheral portion of the first main surface 3. The interlayer film 47 may be formed at a distance inward from the peripheral portion of the first main surface 3, exposing the peripheral portion of the first main surface 3 (the second semiconductor region 7).

[0190] The interlayer film 47 may have a thickness of 0.5 μm or more and 3 μm or less. The thickness of the interlayer film 47 may have a value belonging to at least one of the ranges of 0.5 μm or more and 1 μm or less, 1 μm or more and 1.5 μm or less, 1.5 μm or more and 2 μm or less, 2 μm or more and 2.5 μm or less, and 2.5 μm or more and 3 μm or less.

[0191] The semiconductor device 1A includes a plurality of gate openings (not shown) formed in the interlayer film 47 in the active region 8. The plurality of gate openings are formed in a one-to-many correspondence with a corresponding one of the trench gate structures 15. In this embodiment, the plurality of gate openings penetrate the interlayer film 47 and expose one end or the other end of each of the plurality of trench gate structures 15 (first buried electrodes 18).

[0192] The plurality of gate openings may each have an opening end curved in an arc shape. The plurality of gate openings may be formed in a quadrangular shape, a rectangular shape (strip shape) extending in the first direction X, a rectangular shape (strip shape) extending in the second direction Y, a circular shape, or the like in a plan view. The plurality of gate openings may each have an opening end curved in an arc shape.

[0193] The semiconductor device 1A includes a plurality of source openings 49 formed in the interlayer film 47 in the active region 8. For clarity, the source openings 49 are omitted from FIG. 10 . The source openings 49 are formed in portions of the interlayer film 47 that cover the active region 8. In this embodiment, the source openings 49 are formed in regions between adjacent trench gate structures 15, respectively, and expose the source regions 11 and the gate contact regions 27, respectively.

[0194] The plurality of source openings 49 penetrate the main surface insulating film 45 and the interlayer film 47, and expose the corresponding plurality of source regions 11 and the corresponding plurality of gate contact regions 27. Each of the plurality of source openings 49 may have an opening end that is curved in an arc shape.

[0195] The source openings 49 may be formed in a one-to-many correspondence with the regions between adjacent trench gate structures 15. In this case, the source openings 49 may be formed at intervals along the regions between the corresponding trench gate structures 15. In this case, the source openings 49 may be formed in a quadrangular, rectangular (strip-like), circular, or other shape in plan view.

[0196] 9 and 10 , semiconductor device 1A includes at least one outer opening 50 (one in this embodiment) formed in interlayer film 47 in peripheral region 9. Outer opening 50 penetrates main surface insulating film 45 and interlayer film 47 to expose outer contact region 41. Outer opening 50 extends in a strip shape along outer contact region 41 in plan view.

[0197] In this embodiment, the outer opening 50 is formed in a polygonal ring shape (specifically, a square ring shape) in plan view that surrounds the inner portion (active region 8) of the first main surface 3 along the outer contact region 41. The outer opening 50 may have an opening end that is curved in an arc shape.

[0198] The semiconductor device 1A may have a plurality of outer openings 50. In this case, the plurality of outer openings 50 may be formed at intervals along the outer contact region 41 so as to surround the inner portion (active region 8) of the first main surface 3. In this case, the plurality of outer openings 50 may be formed in a quadrangular (square), rectangular, hexagonal, circular, or other shape in plan view.

[0199] 7 and 8 , semiconductor device 1A includes a source electrode 51 disposed on first main surface 3. Source electrode 51 extends into a plurality of source openings 49 from above interlayer film 47, and is electrically connected to a plurality of source regions 11 and a plurality of gate contact regions 27 within the plurality of source openings 49.

[0200] In this embodiment, the source electrode 51 has a layered structure including a lower electrode film 52 and a main electrode film 53, which are layered in this order from the chip 2 side. In this embodiment, the lower electrode film 52 has a layered structure including a first electrode film and a second electrode film. In this embodiment, the first electrode film includes a Ti film, and the second electrode film includes a TiN film. The lower electrode film 52 does not necessarily have to have a layered structure, and may have a single-layer structure consisting of either the first electrode film (Ti film) or the second electrode film (TiN film).

[0201] The lower electrode film 52 collectively covers the region of the interlayer film 47 where the plurality of source openings 49 are formed, and extends into the plurality of source openings 49 from above the interlayer film 47. The lower electrode film 52 has a portion that covers the insulating main surface of the interlayer film 47 in a film-like manner, a portion that covers the wall surfaces of the plurality of source openings 49 in a film-like manner, and a portion that covers the first main surface 3 in the plurality of source openings 49. The lower electrode film 52 is mechanically and electrically connected to the plurality of source regions 11 and the plurality of gate contact regions 27 in the source openings 49.

[0202] The main electrode film 53 contains a different conductive material from that of the lower electrode film 52. The main electrode film 53 may contain at least one of an Al film, an Al alloy film, a Cu film, and a Cu alloy film. The Al alloy film may contain at least one of an AlSi alloy film, an AlCu alloy film, and an AlSiCu alloy film. The main electrode film 53 has a thickness greater than the thickness (total thickness) of the lower electrode film 52. The thickness of the main electrode film 53 is preferably greater than the thickness of the interlayer film 47.

[0203] The thickness of the main electrode film 53 may be 0.5 μm or more and 5 μm or less. The thickness of the main electrode film 53 may have a value belonging to at least one of the ranges of 0.5 μm or more and 1 μm or less, 1 μm or more and 1.5 μm or less, 1.5 μm or more and 2 μm or less, 2 μm or more and 2.5 μm or less, 2.5 μm or more and 3 μm or less, 3 μm or more and 3.5 μm or less, 3.5 μm or more and 4 μm or less, 4 μm or more and 4.5 μm or less, and 4.5 μm or more and 5 μm or less.

[0204] The main electrode film 53 directly covers the lower electrode film 52. The main electrode film 53 collectively covers the region of the interlayer film 47 where the plurality of source openings 49 are formed, and backfills the plurality of source openings 49.

[0205] The main electrode film 53 has a portion that covers the insulating main surface of the interlayer film 47 with the lower electrode film 52 sandwiched therebetween, a portion that covers the wall surfaces of the plurality of source openings 49 with the lower electrode film 52 sandwiched therebetween, and a portion that covers the first main surface 3 with the lower electrode film 52 sandwiched therebetween. The main electrode film 53 is electrically connected to the plurality of source regions 11 and the plurality of gate contact regions 27 via the lower electrode film 52 within the plurality of source openings 49.

[0206] 9 and 10, the semiconductor device 1A includes a source wiring 56 arranged on the interlayer film 47 around the source electrode 51.

[0207] The source wiring 56 is drawn out from the active region 8 to the peripheral region 9, and has a portion facing the outer contact region 41 across the interlayer film 47. The source wiring 56 enters the outer opening 50 from above the interlayer film 47, and is electrically connected to the outer contact region 41 within the outer opening 50. In other words, the source wiring 56 is electrically connected to the outer well region 42 via the outer contact region 41.

[0208] The source wiring 56 has an inner edge portion on the inner side (active region 8 side) of the first main surface 3 and an outer edge portion on the peripheral side of the first main surface 3. The inner edge portion of the source wiring 56 is located within the active region 8 and faces one or more (multiple in this embodiment) trench gate structures 15 with the interlayer film 47 interposed therebetween. The inner edge portion of the source wiring 56 faces at least the terminal trench gate structure 15A with the interlayer film 47 interposed therebetween.

[0209] The outer edge of source wiring 56 is formed at a distance inward (toward active region 8) from the periphery of first main surface 3. The outer edge of source wiring 56 is formed at a distance inward from the innermost field region 43 of the plurality of field regions 43. In other words, source wiring 56 does not face the plurality of field regions 43 across interlayer film 47.

[0210] With this configuration, the source wiring 56 is prevented from blocking the electric field dispersion path in the region above the plurality of field regions 43, and the electric field (electric force lines) is dispersed appropriately by the plurality of field regions 43.

[0211] Like the source electrode 51, the source wiring 56 has a laminated structure including a lower electrode film 52 and a main electrode film 53 laminated in this order from the chip 2 side.

[0212] The lower electrode film 52 collectively covers the region of the interlayer film 47 where the outer opening 50 is formed, and extends into the outer opening 50 from above the interlayer film 47. The lower electrode film 52 has a portion that covers the insulating main surface of the interlayer film 47 in a film-like manner, a portion that covers the wall surface of the outer opening 50 in a film-like manner, and a portion that covers the first main surface 3 within the outer opening 50 in a film-like manner. The lower electrode film 52 is mechanically and electrically connected to the outer contact region 41 within the outer opening 50.

[0213] The main electrode film 53 directly covers the lower electrode film 52. The main electrode film 53 collectively covers the region of the interlayer film 47 where the outer opening 50 is formed, and backfills the outer opening 50.

[0214] The main electrode film 53 has a portion that covers the insulating main surface of the interlayer film 47 with the lower electrode film 52 in between, a portion that covers the wall surface of the outer opening 50 with the lower electrode film 52 in between, and a portion that covers the first main surface 3 with the lower electrode film 52 in between. The main electrode film 53 is electrically connected to the outer contact region 41 within the outer opening 50 via the lower electrode film 52.

[0215] Although the cross-sectional structure is omitted, the aforementioned gate electrode 57 and gate wiring 58 (see Figure 1) also have a laminated structure including a lower electrode film 52 and a main electrode film 53 laminated in this order from the chip 2 side, similar to the source electrode 51 and source wiring 56.

[0216] The concentration gradient of the p-type impurity concentration in the impurity region in the chip 2 will be specifically described below.

[0217] The numerical values ​​of impurity concentration, thickness, etc. shown below are examples for explaining the basic configuration of the outer contact region 41, outer well region 42, and second semiconductor region 7 (base region 71 and high concentration region 72) based on the concentration gradient, and are not intended to uniquely limit the configuration of the outer contact region 41, outer well region 42, and second semiconductor region 7 (base region 71 and high concentration region 72). The impurity concentration, thickness, etc. are adjusted to various values ​​depending on the implantation conditions (dose amount, implantation temperature, implantation energy, etc.) of the trivalent or pentavalent element. Furthermore, the term "concentration gradient" may be completely replaced with the term "concentration profile."

[0218] Fig. 13 is a graph showing an example of the concentration gradient of p-type impurities in the region along line XIII-XIII shown in Fig. 9. In Fig. 13, the vertical axis represents the p-type impurity concentration of the outer contact region 41 and the outer well region 42, and the horizontal axis represents the depth in the thickness direction of the second semiconductor region 7, with the upper end (first main surface 3) of the second semiconductor region 7 as the reference (zero point).

[0219] 13, the outer contact region 41 has a concentration gradient specific to an impurity region formed by random implantation. Fig. 13 shows the concentration gradient of the outer contact region 41 when a predetermined trivalent element (here, aluminum) is introduced into the second semiconductor region 7 in a random direction with an implantation energy of 190 KeV. The random direction is a direction (for example, the vertical direction Z) that is not parallel (almost parallel) to the axial channel of the second semiconductor region 7. The depth (thickness) of the outer contact region 41 is about 0.5 μm, and the dose of the trivalent element is 1×10 １３ cm －２ is.

[0220] The outer contact region 41 has a sudden increase portion 73, a peak portion 74 (peak value P0), and a sudden decrease portion 75 within a range of 0.5 μm.

[0221] The sudden increase portion 73 is a portion where the impurity concentration suddenly increases from the first main surface 3 toward the peak portion 74. The sudden decrease portion 75 is a portion where the impurity concentration suddenly decreases from the peak portion 74 toward the second lower end 42b of the outer well region 42. For example, the depth position of the peak portion 74 is 0.2 μm or more and 0.3 μm or less. The outer contact region 41 may have the sudden increase portion 73 and the sudden decrease portion 75 in the range of 0.1 μm or more and 0.2 μm or less on the shallower and deeper sides from the peak portion 74, respectively.

[0222] The sudden increase portion 73 has a thickness of 0.1 μm or more and 0.2 μm or less, and has a density change rate of 100% or more within this thickness range.Similarly, the sudden decrease portion 75 has a thickness of 0.1 μm or more and 0.2 μm or less, and has a density change rate of 100% or more within this thickness range.

[0223] The outer well region 42 has a concentration gradient specific to an impurity region formed by channeling implantation. Fig. 13 shows the concentration gradient of the outer well region 42 when a predetermined trivalent element (here, aluminum) is introduced into the second semiconductor region 7 parallel or nearly parallel to the axial channel of the second semiconductor region 7 with an implantation energy of 650 KeV.

[0224] The p-type impurity concentration of the outer well region 42 has a concentration gradient from the second upper end 42a side toward the second lower end 42b, including a gradually increasing portion 20, a peak portion 21, a second gradual portion 22, and a gradually decreasing portion 23. The gradually increasing portion 20 is a portion that forms the second upper end 42a of the outer well region 42, and is a portion where the p-type impurity concentration gradually increases from the second upper end 42a side toward the second lower end 42b side up to the peak portion 21 at a relatively steep rate of increase.

[0225] The peak portion 21 is a portion having a peak value (second peak value) P2 of the p-type impurity concentration. The peak portion 21 is also a convex main concentration transition portion including a series of concentration changes (inflection points) where the p-type impurity concentration changes from an increase (increasing trend) to a decrease (decreasing trend). The depth position of the peak portion 21 is 0.5 μm or more and 1 μm or less.

[0226] The second gradual portion 22 is formed in a region closer to the second lower end 42b than the peak portion 21, and is a portion where the impurity concentration gradually decreases at a relatively gradual rate. In other words, the second gradual portion 22 is a portion that maintains a constant p-type impurity concentration within a certain depth range, and forms the second main portion 42c (FIG. 9) of the outer well region 42. The second gradual portion 22 occupies a thickness range of 15% to 60% of the outer well region 42. It is preferable that the second gradual portion 22 occupies a thickness range of at least one-quarter of the outer well region 42.

[0227] The second gradual region 22 is defined by a region having a concentration drop rate of 50% or less in a thickness range of at least 1 μm. In this example, the second gradual region 22 has a thickness of 0.7 μm or more and 1.5 μm or less, and has a concentration drop rate of 50% or less in this thickness range. In this example, the p-type impurity concentration of the second gradual region 22 is 4.5×10 １６ cm －３ 9 x 10 or more １６ cm －３ The concentration range is as follows:

[0228] The gradually decreasing portion 23 is a portion that forms the second lower end 42b of the outer well region 42. The gradually decreasing portion 23 has a concentration decrease rate that is greater than the concentration decrease rate in the second gradual portion 22, and is a portion where the p-type impurity concentration gradually decreases from the second gradual portion 22 toward the second lower end 42b. The concentration decrease rate per unit thickness of the gradually decreasing portion 23 is greater than the concentration decrease rate per unit thickness of the second gradual portion 22. The p-type impurity concentration of the gradually decreasing portion 23 is 1×10 １５ cm －３ It is gradually decreasing to.

[0229] Fig. 14 is a graph showing an example of the concentration gradient of the p-type impurity concentration in the region along line XIV-XIV shown in Fig. 11. In Fig. 14, the vertical axis represents the p-type impurity concentration in the field region 43, and the horizontal axis represents the depth in the thickness direction of the second semiconductor region 7, with the upper end (first main surface 3) of the second semiconductor region 7 as the reference (zero point).

[0230] 14, the field region 43 has a concentration gradient specific to an impurity region formed by channeling implantation. Fig. 14 shows the concentration gradient of the field region 43 when a predetermined trivalent element (here, aluminum) is introduced into the second semiconductor region 7 parallel or nearly parallel to the axial channel of the second semiconductor region 7 with an implantation energy of 650 KeV. The depth (thickness) of the field region 43 is about 3 μm, and the dose of the trivalent element is 1×10 １３ cm －２ is.

[0231] The p-type impurity concentration of field region 43 has a concentration gradient from first upper end 43a to first lower end 43b, including a gradually increasing portion 85, a peak portion 86, a first gradual portion 87, and a gradually decreasing portion 88. Gradually increasing portion 85 is a portion that forms first upper end 43a of field region 43, and is a portion where the p-type impurity concentration gradually increases from first upper end 43a toward first lower end 43b to peak portion 86 at a relatively steep rate of increase.

[0232] The peak portion 86 is a portion having a peak value (first peak value) P4 of the p-type impurity concentration. The peak portion 86 is also a convex main concentration transition portion including a series of concentration changes (inflection points) where the p-type impurity concentration changes from an increase (increasing trend) to a decrease (decreasing trend). The depth position of the peak portion 86 is 0.5 μm or more and 1 μm or less.

[0233] The first gradual portion 87 is formed in a region closer to the first lower end 43b than the peak portion 86, and is a portion where the impurity concentration gradually decreases at a relatively gradual rate. In other words, the first gradual portion 87 is a portion where a constant p-type impurity concentration is maintained within a certain depth range, and forms the first main portion 43c (FIG. 11) of the field region 43. The p-type impurity concentration of the first gradual portion 87 gradually decreases within a concentration range that is less than the p-type impurity concentration of the peak portion 86.

[0234] The first gradual region 87 is defined by a region having a concentration drop rate of 50% or less in a thickness range of at least 1 μm. In this example, the first gradual region 87 has a thickness of 1.0 μm or more and 4.0 μm or less, and has a concentration drop rate of 50% or less in this thickness range. In this example, the p-type impurity concentration of the first gradual region 87 is 4.5×10 １６ cm －３ 9 x 10 or more １６ cm －３ The concentration range is as follows:

[0235] The gradually decreasing portion 88 is a portion that forms the first lower end 43b of the field region 43. The gradually decreasing portion 88 has a concentration decrease rate that is greater than the concentration decrease rate in the first gradual portion 87, and is a portion where the p-type impurity concentration gradually decreases from the first gradual portion 87 toward the first lower end 43b. The concentration decrease rate per unit thickness of the gradually decreasing portion 88 is greater than the concentration decrease rate per unit thickness of the first gradual portion 87. The p-type impurity concentration of the gradually decreasing portion 88 is 1×10 １５ cm －３ It is gradually decreasing to.

[0236] 11 , in a cross-sectional view ( FIG. 11 ) of chip 2 taken along the X direction (the m-axis direction ([1-100] direction) of the SiC single crystal) across active region 8, cross sections of multiple field regions 43 appear on both sides of active region 8. In this cross-sectional view, inner side portion 43 d and outer side portion 43 e are inclined so as to approach each other from first upper end portion 43 a toward first lower end portion 43 b.

[0237] In this embodiment, the inclination angle θ1 of the inner side portion 43 d with respect to the first main surface 3 is equal to the inclination angle θ2 of the outer side portion 43 e with respect to the first main surface 3 (θ1 = θ2). That is, the pair of first side portions 43 d, 43 e approach each other at the same inclination from the first upper end portion 43 a to the first lower end portion 43 b.

[0238] In the cross-sectional view shown in Figure 11, a gap 68 is formed between the first main surface 3 and both the portion of the end 67 of the first upper end 43a that connects to the outer side portion 43e and the portion of the end 67 of the first upper end 43a that connects to the outer side portion 43e.

[0239] Fig. 15 is a cross-sectional view showing the cross-sectional structure of the outer peripheral region along line XV-XV shown in Fig. 1. Fig. 16 is a cross-sectional view showing the cross-sectional structure of the outer peripheral region along line XVI-XVI shown in Fig. 1.

[0240] As described above, the chip 2 (first main surface 3) has an off-angle α ( FIG. 3 ) that is tilted at a predetermined angle in a predetermined off-axis direction with respect to the c-plane of the SiC single crystal. The shape of the diffusion region formed by the channeling implantation method is affected by the off-angle α. Therefore, the shape of the field region 43 formed by the channeling implantation method varies depending on the cross-sectional view.

[0241] 15 and 16 , in a cross-sectional view of chip 2 across active region 8 along the Y direction (the a-axis direction ([11-20] direction) of the SiC single crystal), cross sections of multiple field regions 43 appear on both sides of active region 8. Semiconductor device 1A includes a first cross-sectional image CS1 ( FIG. 15 ) showing the multiple field regions 43 on one side, and a second cross-sectional image CS2 ( FIG. 16 ) showing the multiple field regions 43 on the other side.

[0242] 15 , in the first cross-sectional image CS1, the inner side portion 43 d and the outer side portion 43 e are inclined so as to approach each other from the first upper end portion 43 a to the first lower end portion 43 b. In this configuration, the inclination angle θ1 of the inner side portion 43 d with respect to the first main surface 3 is smaller than the inclination angle θ2 of the outer side portion 43 e with respect to the first main surface 3 (θ1<θ2). That is, in the first cross-sectional image CS1, the inner side portion 43 d is inclined at a gentler angle than the outer side portion 43 e.

[0243] In this embodiment, in the first cross-sectional image CS1, a gap 68 is formed between the first main surface 3 and a portion of the end 67 of the first upper end 43 a that is continuous with the inner side portion 43 d. No gap 68 is formed between the first main surface 3 and a portion of the end 67 of the first upper end 43 a that is continuous with the outer side portion 43 e.

[0244] 16 , in the second cross-sectional image CS2, the inner side portion 43 d and the outer side portion 43 e are inclined so as to approach each other from the first upper end portion 43 a to the first lower end portion 43 b. In this configuration, the inclination angle θ2 of the outer side portion 43 e with respect to the first principal surface 3 is smaller than the inclination angle θ1 of the inner side portion 43 d with respect to the first principal surface 3 (θ2<θ1). That is, in the second cross-sectional image CS2, the outer side portion 43 e is inclined at a gentler angle than the inner side portion 43 d.

[0245] In this embodiment, in the second cross-sectional image CS2, a gap 68 is formed between the first main surface 3 and the portion of the end 67 of the first upper end 43 a that is continuous with the outer side portion 43 e. No gap 68 is formed between the first main surface 3 and the portion of the end 67 of the first upper end 43 a that is continuous with the inner side portion 43 d.

[0246] 17 is a graph showing the relationship between charge density and breakdown voltage. This graph shows the relationship between charge density and breakdown voltage for semiconductor device 1A and a semiconductor device according to a comparative example. The spacing between the multiple field regions in the semiconductor device according to the comparative example is constant in the direction from the active region (active region 8) toward the peripheral region (peripheral region 9). Furthermore, the width of each of the multiple field regions in the semiconductor device according to the comparative example is constant in the direction from the active region (active region 8) toward the peripheral region (peripheral region 9).

[0247] 17, it can be seen that the breakdown voltage is low when the charge density is low in the semiconductor device according to the comparative example. From this, it is considered that when the charge density is low, impact ionization occurs in the field region (corresponding to field region 43), causing dielectric breakdown (avalanche breakdown) in at least a part of the semiconductor device according to the comparative example.

[0248] In contrast, it can be seen that the semiconductor device 1A can achieve a high breakdown voltage regardless of the magnitude of the charge density. That is, it can be seen from Fig. 17 that the semiconductor device 1A can maintain a high breakdown voltage over a wide charge range. From this, it can be considered that the semiconductor device 1A can prevent impact ionization from occurring in the field region 43 even when the charge density is low, and can prevent the occurrence of dielectric breakdown (avalanche breakdown).

[0249] 18 and 19 are cross-sectional views showing field regions 43 according to the second and third embodiments, respectively. Figures 18 and 19 correspond to Figures 11 and 10, respectively. Semiconductor device 1A may include at least one of field regions 43 according to the first to third embodiments. Semiconductor device 1A may also include at least two of field regions 43 according to the first to third embodiments simultaneously, in the same cross-sectional region or different cross-sectional regions.

[0250] 18 (second embodiment), semiconductor device 1A may include field region 43 having first side portions 43d, 43e extending vertically from first upper end 43a to first lower end 43b. That is, the pair of first side portions 43d, 43e may not be inclined with respect to first main surface 3.

[0251] 19 (third embodiment), in the third embodiment, the total length TL of the spacing W and width S of the plurality of field regions 43 increases in the direction from the active region 8 toward the peripheral region 9. Specifically, the total length TL of the spacing W2 and width S2 of the second field region 43Q is greater than the total length TL of the spacing W1 and width S1 of the first field region 43P. The total length TL of the spacing W3 and width S3 of the third field region 43R is greater than the total length TL of the spacing W2 and width S2 of the second field region 43Q.

[0252] 19 , the total length TL of the spacing W and width S of the multiple field regions 43 does not have to be constant in the direction from the active region 8 toward the peripheral region 9. The total length TL may decrease in the direction from the active region 8 toward the peripheral region 9.

[0253] As described above, according to the semiconductor device 1A, as shown in Figures 10 and 11, the spacing S between the multiple field regions 43 becomes wider in the direction from the active region 8 toward the peripheral region 9, and the width W of each of the multiple field regions 43 becomes narrower in the direction from the active region 8 toward the peripheral region 9.

[0254] The spacing S between the multiple field regions 43 widens in the direction from the active region 8 toward the peripheral region 9. That is, in the outer field regions 43 of the multiple field regions 43, a wide spacing is ensured between adjacent field regions 43. This makes it possible to suppress the occurrence of impact ionization in the outer field regions 43 (for example, the outermost field region 43 (fourth field region 43S)). Therefore, it is possible to reliably avoid the occurrence of dielectric breakdown (avalanche breakdown) in the outer field regions 43 (for example, the outermost field region 43 (fourth field region 43S)).

[0255] Furthermore, in the innermost field regions 43 among the multiple field regions 43, the spacing S between adjacent field regions 43 is narrow. Moreover, the spacing S0 between the innermost field region 43 (first field region 43P) and the outer well region 42 is also narrow. This makes it possible to suppress the occurrence of impact ionization in the inner field regions 43 (e.g., the outermost field region 43 (fourth field region 43S)) and the outer well region 42. Therefore, it is possible to reliably avoid the occurrence of dielectric breakdown (avalanche breakdown) in the inner field regions 43 (e.g., the innermost field region 43 (first field region 43P)) and / or the outer well region 42.

[0256] As a result, it is possible to increase the dielectric breakdown field value of the plurality of field regions 43. As a result, it is possible to improve the avalanche resistance.

[0257] Also, consider a case where the width W of the plurality of field regions 43 is constant or increases in the direction from the active region 8 toward the peripheral region 9. In this case, if the spacing S between the plurality of field regions 43 is widened in the direction from the active region 8 toward the peripheral region 9, it may become necessary to reduce the number of the plurality of field regions 43 due to layout considerations when the width of the peripheral region 9 is narrow.

[0258] In contrast, in this embodiment, the width W of each of the plurality of field regions 43 narrows in the direction from the active region 8 toward the peripheral region 9. Therefore, even if the width of the peripheral region 9 is narrow, a layout can be realized in which the spacing S between the plurality of field regions 43 widens in the direction from the active region 8 toward the peripheral region 9 without reducing the number of the plurality of field regions 43.

[0259] The p-type impurity concentration of the field region 43 formed by channeling implantation has a gradually increasing portion 85, a peak portion 86, a first gradual portion 87, and a gradually decreasing portion 88. The first gradual portion 87 occupies a thickness range of at least one-quarter of the field region 43 and is located within the second semiconductor region 7. Specifically, the proportion of the field region 43 occupied by the first gradual portion 87 is at least one-third. The proportion of the field region 43 occupied by the first gradual portion 87 is typically at most one-half (less than one-half). The proportion of the field region 43 occupied by the first gradual portion 87 may be at least one-half. The first gradual portion 87 has a thickness of at least 1.0 μm and at most 4.0 μm. The first gradual portion 87 has a concentration decrease rate of 50% or less within the above thickness range.

[0260] The p-type impurity concentration of each field region 43 has a gradually increasing portion 85 , a peak portion 86 , a first gradual portion 87 and a gradually decreasing portion 88 , so that the electric field strength of the plurality of field regions 43 can be improved.

[0261] On the other hand, if multiple field regions 43 are formed by random injection, it is difficult to create a concentration gradient similar to the concentration gradient having the aforementioned gradually increasing portion 85, peak portion 86, first slow portion 87, and gradually decreasing portion 88.

[0262] Therefore, when forming the multiple field regions 43 shown in FIG. 10 by the random implantation method, it is necessary to employ a multi-stage random implantation method. In the multi-stage random implantation method, a process is performed in which a trivalent element is introduced into the second semiconductor region 7 at different depths using multiple implantation energies. For example, the trivalent element is introduced into the second semiconductor region 7 at different implantation energies, such as three, five, or seven stages. In this process, the trivalent element can be introduced to the desired depth, but the thickness of the region into which the trivalent element can be introduced is narrow. Therefore, to implant the element deeper, the number of steps in the random implantation method must be increased, complicating the manufacturing process. As a result, the design of the outer well region 42 becomes complicated, and the increased number of ion implantation steps also increases the burden on the device.

[0263] In contrast, with the channeling implantation method, a single ion implantation step can be used to form multiple field regions 43 each having a relatively thick first gentle portion 87. This allows multiple field regions 43 for improving breakdown voltage to be formed with fewer steps than would be required with the random implantation method. As a result, the design of the multiple field regions 43 can be simplified, and the burden on the device can be reduced.

[0264] Similarly, the p-type impurity concentration of the outer well region 42 also has a gradually increasing portion 20, a peak portion 21, a second gradual portion 22, and a gradually decreasing portion 23. Therefore, the design of the outer well region 42 can be simplified, and the load on the device can also be reduced.

[0265] The second gradual portion 22 occupies a thickness range of at least one-quarter of the outer well region 42 and is located within the second semiconductor region 7. Specifically, the proportion of the second gradual portion 22 in the outer well region 42 is at least one-third. The proportion of the second gradual portion 22 in the outer well region 42 is typically at most one-half (less than one-half). The proportion of the second gradual portion 22 in the outer well region 42 may be at least one-half. The second gradual portion 22 has a thickness of at least 1.0 μm and at most 4.0 μm. The second gradual portion 22 has a concentration reduction rate of 50% or less within the above thickness range.

[0266] Fig. 20 is a cross-sectional view of a main portion of a semiconductor device 1B according to a second embodiment of the present disclosure. Fig. 20 shows a cut surface at the same position as Fig. 9. Fig. 21 is a cross-sectional view showing a main portion of the semiconductor device 1B, showing a cut surface at the same position as Fig. 10.

[0267] 20 , semiconductor device 1B has a configuration in which the configurations of the gate structures of semiconductor device 1A are modified. More specifically, semiconductor device 1B includes a planar gate structure 100 instead of trench gate structure 15 as the gate structure.

[0268] Prior to describing the planar gate structure 100, the semiconductor device 1B includes a plurality of p-type body regions 101 formed in a surface layer portion of the first main surface 3 in the active region 8. The body regions 101 are arranged at intervals in the first direction X and are each formed in a strip shape extending in the second direction Y. In other words, the body regions 101 are arranged in stripes extending in the second direction Y.

[0269] The plurality of body regions 101 are formed at intervals from the bottom of the second semiconductor region 7 toward the first main surface 3, and face the first semiconductor region 6 with a portion of the second semiconductor region 7 sandwiched between them. The plurality of body regions 101 are preferably formed at intervals from the middle of the second semiconductor region 7 toward the first main surface 3. The plurality of body regions 101 are exposed from the first main surface 3. In this embodiment, the plurality of body regions 101 are formed at intervals from the bottom of the high-concentration region 72 toward the first main surface 3, and face the base region 71 with a portion of the high-concentration region 72 sandwiched between them.

[0270] The body regions 101 are formed shallower than the outer well region 42. The body regions 101 may be formed deeper than the outer contact region 41.

[0271] The semiconductor device 1B includes n-type source regions 102 formed in the surface layer portions of the plurality of body regions 101. The source regions 102 have a higher n-type impurity concentration than the n-type impurity concentration of the first semiconductor region 6. A source potential is applied to the source regions 102.

[0272] The semiconductor device 1B includes a plurality of p-type channel regions 103 formed in a surface layer portion of the first main surface 3. The plurality of channel regions 103 are defined in the surface layer portions of the plurality of body regions 101 in regions between ends of the plurality of body regions 101 and peripheral edges of the source regions 102. In this embodiment, the plurality of channel regions 103 are arranged at intervals in the first direction X and are each formed in a strip shape extending in the second direction Y. In other words, the plurality of channel regions 103 are arranged in stripes extending in the second direction Y.

[0273] The planar gate structure 100 is disposed on at least one channel region 103. In this embodiment, each planar gate structure 100 is disposed across the region between two adjacent body regions 101 to straddle the two body regions 101, and covers a plurality of channel regions 103. Specifically, each planar gate structure 100 is disposed across a source region 102 on one body region 101 side and a source region 102 on the other body region 101 side, and covers a portion of the source region 102 and the channel region 103.

[0274] The planar gate structure 100 has a layered structure including an insulating film 104 and a gate electrode 105. The insulating film 104 may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. In this embodiment, the insulating film 104 has a single-layer structure made of a silicon oxide film. It is particularly preferable that the insulating film 104 includes a silicon oxide film made of an oxide of the chip 2.

[0275] The insulating film 104 covers the first main surface 3 in a film form and is disposed on at least one channel region 103. In this embodiment, the insulating film 104 is disposed so as to straddle two adjacent body regions 101 and covers the multiple channel regions 103.

[0276] Specifically, the insulating film 104 is arranged across the source region 102 on one body region 101 side and the source region 102 on the other body region 101 side, and covers part of the source region 102 and the channel region 103.

[0277] The gate electrode 105 is disposed on the insulating film 104 and faces at least one channel region 103 across the insulating film 104. A gate potential as a control potential is applied to the gate electrode 105. The gate electrode 105 controls inversion and non-inversion of the at least one channel region 103 in response to the gate potential.

[0278] The gate electrode 105 includes a conductive semiconductor polycrystalline. The gate electrode 105 may include either or both of p-type conductive polysilicon and n-type conductive polysilicon. The conductivity type of the gate electrode 105 is adjusted depending on the gate threshold voltage to be achieved. The gate electrode 105 may also be referred to as a "polysilicon gate," a "poly gate," or the like.

[0279] The semiconductor device 1B includes a low-concentration region 106 stacked on the high-concentration region 72. The low-concentration region 106 is a part of the second semiconductor region 7. In other words, the second semiconductor region 7 of the semiconductor device 1B includes a stacked structure of the base region 71, the high-concentration region 72, and the low-concentration region 106.

[0280] The low-concentration region 106 is formed on the side of the body region 101 between the high-concentration region 72 and the first major surface 3. The low-concentration region 106 is formed in a layer shape that contacts the body region 101 and extends along the first major surface 3. The body region 101 crosses the boundary between the high-concentration region 72 and the low-concentration region 106 in the thickness direction of the second semiconductor region 7 and contacts both side portions of the high-concentration region 72 and the low-concentration region 106.

[0281] The n-type impurity concentration of the low concentration region 106 is preferably lower than the n-type impurity concentration of the high concentration region 72. The n-type impurity concentration of the low concentration region 106 may be the same as the n-type impurity concentration of the base region 71. The low concentration region 106 has an n-type impurity concentration of 1×10 １５ cm －３ 5x10 or more １６ cm －３The n-type impurity concentration of the low-concentration region 106 may have a peak value of the following: The n-type impurity concentration of the low-concentration region 106 may be approximately constant in the thickness direction. Of course, the n-type impurity concentration of the low-concentration region 106 may have a concentration gradient that gradually increases and / or decreases in the thickness direction (crystal growth direction) of the chip 2.

[0282] The outer well region 42 is formed deeper than the body regions 101 along the peripheral boundary 19 between the active region 8 and the peripheral region 9. The outer well region 42 may have approximately the same depth as the body regions 101.

[0283] More specifically, the body region 101 includes a well side portion 101a extending in the thickness direction of the second semiconductor region 7, and a well bottom portion 101b extending from the well side portion 101a in a direction along the first main surface 3. The outer well region 42 is in contact with the well side portion 101a.

[0284] 21 , a plurality of field regions 43 are arranged in the peripheral region 9 at intervals outward from the outer well region 42, similar to the semiconductor device 1A according to the first embodiment. In this embodiment, each field region 43 is formed in a polygonal ring shape (a square ring shape in this embodiment) having four sides parallel to the periphery of the chip 2 in a plan view, and surrounds the outer well region 42. The shape of each field region 43 is the same as that of the semiconductor device 1A according to the first embodiment.

[0285] The widths W of the field regions 43 decrease successively toward the periphery of the first main surface 3. Specifically, the second width W2 of the second field region 43Q is narrower than the first width W1 of the first field region 43P (W2<W1). The third width W3 of the third field region 43R is narrower than the second width W2 (W3<W2). The fourth width W4 of the fourth field region 43S is narrower than the third width W3 (W4<W3). In other words, the widths W of the field regions 43 decrease in the direction from the active region 8 toward the peripheral region 9.

[0286] The spacing S between the multiple field regions 43 increases sequentially toward the peripheral edge of the first main surface 3. Specifically, the second spacing S2 between the second field region 43Q and the third field region 43R is wider than the first spacing S1 between the first field region 43P and the second field region 43Q (S2 > S1). The third spacing S3 between the third field region 43R and the fourth field region 43S is wider than the second spacing S2 (S3 > S2). In other words, the spacing S between the multiple field regions 43 increases in the direction from the active region 8 toward the peripheral region 9.

[0287] Furthermore, the distance S0 between the first field region 43P, which is the innermost of the plurality of field regions 43, and the outer well region 42 is narrower than the first distance S1.

[0288] The total length TL of the spacing S and width W of the multiple field regions 43 is constant in the direction from the active region 8 toward the peripheral region 9. Specifically, the total length TL of the first spacing S1 and first width W1 is equal to the total length TL of the second spacing S2 and second width W2. The total length TL of the second spacing S2 and second width W2 is equal to the total length TL of the third spacing S3 and third width W3.

[0289] The semiconductor device 1B provides the same effects as those described in relation to the semiconductor device 1A according to the first embodiment.

[0290] The field region 43 according to the second and third embodiment examples of the semiconductor device 1A according to the first embodiment may be applied to the semiconductor device 1B.

[0291] 22 is a cross-sectional view of a main part of a semiconductor device 1C according to a third embodiment of the present disclosure, and corresponds to FIG.

[0292] 22, the semiconductor device 1C has a modified configuration of the device structure of the semiconductor device 1A. More specifically, the semiconductor device 1C includes a Schottky barrier diode 200 in the active region 8 as the device structure, instead of the insulated gate transistor structure Tr.

[0293] Similar to semiconductor device 1A, semiconductor device 1C includes chip 2, first semiconductor region 6, second semiconductor region 7, active region 8, peripheral region 9, and multiple field regions 43. The multiple field regions 43 include, for example, in order from the inside out, first field region 43P, second field region 43Q, third field region 43R, and fourth field region 43S.

[0294] The semiconductor device 1C includes an interlayer insulating film 201 that selectively covers the first main surface 3. The interlayer insulating film 201 may have a single layer structure or a multilayer structure including at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. In this embodiment, the interlayer insulating film 201 has a single layer structure including a silicon oxide film.

[0295] The interlayer insulating film 201 covers the multiple field regions 43 in the peripheral region 9. In this embodiment, the interlayer insulating film 201 is continuous with the periphery (first to fourth side surfaces 5A to 5D) of the first main surface 3. Of course, the interlayer insulating film 201 may be formed at a distance inward from the periphery of the first main surface 3, exposing the second semiconductor region 7 from the periphery of the first main surface 3.

[0296] Interlayer insulating film 201 has contact opening 202 that exposes active region 8. In this embodiment, contact opening 202 has an opening wall surface positioned above first field region 43P (innermost field region 43), exposing the entire active region 8 and the inner edge of first field region 43P.

[0297] The semiconductor device 1C includes a Schottky electrode 203 covering the first main surface 3 in the active region 8. The Schottky electrode 203 is formed as an anode pad. The Schottky electrode 203 is disposed inward from the periphery of the chip 2 at a distance. The Schottky electrode 203 is formed in a polygonal shape (a quadrangle in this embodiment) that follows the periphery of the chip 2 in a plan view.

[0298] The Schottky electrode 203 extends from above the interlayer insulating film 201 into the contact opening 202 and is electrically connected to the first main surface 3 and the first field region 43P within the contact opening 202. The Schottky electrode 203 forms a Schottky junction with the first main surface 3. As a result, a Schottky barrier diode 200 (Schottky Barrier Diode structure) is formed in the active region 8 as a device structure.

[0299] The first field region 43P has a function as the field region 43 and a function as the anode region 204. That is, in this embodiment, the first field region 43P is the anode region 204.

[0300] The semiconductor device 1C includes a pad electrode 205 covering the second main surface 4. The pad electrode 205 is formed as a cathode pad. The pad electrode 205 forms ohmic contact with the first semiconductor region 6 exposed from the second main surface 4. In other words, the pad electrode 205 is electrically connected to the anode region 204 (first field region 43P).

[0301] The pad electrode 205 may cover the entire second main surface 4 so as to be continuous with the periphery (first to fourth side surfaces 5A to 5D) of the chip 2. The pad electrode 205 may cover the second main surface 4 at a distance inward from the periphery of the chip 2 so as to expose the periphery of the chip 2.

[0302] The breakdown voltage that can be applied between Schottky electrode 203 and pad electrode 205 (between first main surface 3 and second main surface 4) may be 500 V or more and 3000 V or less. The breakdown voltage may have a value belonging to any one of the ranges of 500 V or more and 1000 V or less, 1000 V or more and 1500 V or less, 1500 V or more and 2000 V or less, 2000 V or more and 2500 V or less, and 2500 V or more and 3000 V or less.

[0303] Schottky electrode 203 is mechanically and electrically connected to second semiconductor region 7 and anode region 204 (first field region 43P) at first main surface 3. In this case, Schottky electrode 203 forms a Schottky junction with anode region 204 (first field region 43P).

[0304] In semiconductor device 1C, similar to semiconductor device 1A according to the first embodiment, the widths of the field regions 43 decrease sequentially toward the periphery of first main surface 3. Specifically, the width of second field region 43Q is narrower than the width of first field region 43P. The width of third field region 43R is narrower than the width of second field region 43Q. The width of fourth field region 43S is narrower than the width of third field region 43R. In other words, the widths of the field regions 43 decrease in the direction from active region 8 toward peripheral region 9.

[0305] In semiconductor device 1C, similar to semiconductor device 1A according to the first embodiment, the spacing between the plurality of field regions 43 increases sequentially toward the periphery of first main surface 3. In other words, the spacing between the plurality of field regions 43 increases in the direction from active region 8 toward peripheral region 9.

[0306] In the semiconductor device 1C, similarly to the semiconductor device 1A according to the first embodiment, the total length TL of the spacing S and width W of the plurality of field regions 43 is constant in the direction from the active region 8 toward the peripheral region 9.

[0307] The semiconductor device 1C provides the same effects as those described in relation to the semiconductor device 1A according to the first embodiment.

[0308] The field region 43 according to the second and third embodiment examples of the semiconductor device 1A according to the first embodiment may be applied to the semiconductor device 1C.

[0309] The above-described embodiments (including variations) can be implemented in other embodiments. For example, in the above-described embodiments, the chip 2 includes a SiC single crystal. However, the chip 2 may include a silicon single crystal. Similarly, the first semiconductor region 6 may include a silicon single crystal. Similarly, the second semiconductor region 7 may include a silicon single crystal.

[0310] In each of the above-described embodiments, a structure may be adopted in which the conductivity type of an “n-type” semiconductor region is inverted to “p-type” and the conductivity type of a “p-type” semiconductor region is inverted to “n-type.” A specific configuration in this case can be obtained by replacing “n-type” with “p-type” and “p-type” with “n-type” in the above description and accompanying drawings.

[0311] In the first and second embodiments, a p-type collector region may be formed in a surface layer portion of the second main surface 4 of the chip 2. In this case, the transistor structure Tr includes an IGBT (Insulated Gate Bipolar Transistor) structure instead of the MISFET structure. A specific configuration in this case can be obtained by replacing the "source" of the MISFET structure with the "emitter" of the IGBT structure and the "drain" of the MISFET structure with the "collector" of the IGBT structure in the above description. In this case, the chip 2 may have a single-layer structure made of an n-type semiconductor substrate.

[0312] Below, examples of features extracted from this specification and the drawings are shown. Below, alphanumeric characters in parentheses represent corresponding components in the above-mentioned embodiments, but are not intended to limit the scope of each clause to the embodiments. The "semiconductor device" in the following items may be replaced with "semiconductor device," "wide bandgap semiconductor device," "semiconductor switching device," "semiconductor rectifier device," "MISFET device," "IGBT device," "diode device," etc., as necessary.

[0313] [Supplementary Note 1-1] A chip (2) having a main surface (3), a semiconductor region (7) of a first conductivity type formed in a surface layer portion of the main surface (3), an active region (8) provided in an inner portion of the main surface (3), a peripheral region (9) provided in a peripheral portion of the main surface (3), a device structure (Tr, 200) formed in the active region (8), and a plurality of annular field regions (43) of a second conductivity type formed at intervals in the surface layer portion of the semiconductor region (7) in the peripheral region (9) and surrounding the active region (8), wherein the spacing (S) between the plurality of field regions (43) increases in a direction from the active region (8) toward the peripheral region (9), and the widths (W) of the plurality of field regions (43) decrease in a direction from the active region (8) toward the peripheral region (9), Each of the field regions (43) has a first upper end (43a) on the main surface (3) side and a first lower end (43b) on the opposite side thereof, and has a concentration gradient that gradually decreases from the first upper end (43a) toward the first lower end (43b).

[0314] [Appendix 1-2] The semiconductor device (1A, 1B, 1C) described in Appendix 1-1, wherein the concentration gradient includes a first peak value (P4) on the first upper end (43 a) side, and a first gradual portion (87) in which the impurity concentration gradually decreases at a gradual rate of decrease in a region on the first lower end (43 b) side of the first peak value (P4).

[0315] [Supplementary Note 1-3] The semiconductor device (1A, 1B, 1C) according to Supplementary Note 1-2, wherein the first gentle portion (87) occupies a thickness range of at least ¼ of the field region (43).

[0316] [Appendix 1-4] The semiconductor device (1A, 1B, 1C) according to Appendix 1-3, wherein the first gentle portion (87) has a thickness of 1.0 μm or more and 4.0 μm or less, and has a concentration reduction rate of 50% or less within that thickness range.

[0317] [Supplementary Note 1-5] The semiconductor device (1A, 1B, 1C) according to any one of Supplementary Note 1-2 to Supplementary Note 1-4, wherein the chip (2) is a SiC chip, each of the field regions (43) has a pair of first side portions (43d, 43e) that connect the first upper end portion (43a) and the first lower end portion (43b) and are inclined from the first upper end portion (43a) toward the first lower end portion (43b), and in a cross-sectional view that crosses the active region (8) along an m-axis direction ([1-100] direction) of the SiC single crystal and in which cross sections of the plurality of field regions (43) appear on both sides of the active region (8), the pair of first side portions (43d, 43e) approach each other at an equal inclination from the first upper end portion (43a) toward the first lower end portion (43b).

[0318] [Supplementary Note 1-6] The semiconductor device (1A, 1B, 1C) according to Supplementary Note 1-5, wherein the semiconductor device (1A, 1B, 1C) includes a first cross-sectional image (CS1) showing the plurality of field regions (43) on one side and a second cross-sectional image (CS2) showing the plurality of field regions (43) on the other side in a cross-sectional view taken along the a-axis direction ([11-20] direction) of the SiC single crystal across the active region (8), with cross sections of the plurality of field regions (43) appearing on both sides of the active region (8), wherein in the first cross-sectional image (CS1), an inner side (43d) of the pair of first side portions (43d, 43e) closer to the active region (8) is inclined at a gentler inclination than an outer side (43e) farther from the active region (8), and in the second cross-sectional image (CS2), the outer side portion (43e) is inclined at a gentler inclination than the inner side portion (43d).

[0319] [Appendix 1-7] The semiconductor device (1A, 1B, 1C) according to Appendix 1-5 or Appendix 1-6, wherein the first upper end (43a) is formed in a shape that protrudes in an arc from the first side portions (43d, 43e) toward the main surface (3), and the first upper end (43a) is arranged such that a central portion in the width direction (X) of the field region (43) is exposed from the main surface (3) and an end portion in the width direction (X) is positioned at a distance from the main surface (3).

[0320] [Supplementary Note 1-8] The semiconductor device (1A, 1B, 1C) according to any one of Supplementary Note 1-1 to Supplementary Note 1-7, wherein the depth (D2) of each of the field regions (43) is 2 μm or more.

[0321] [Appendix 1-9] The semiconductor device (1A, 1B, 1C) according to appendix 1-8, wherein the depth (D2) of each of the field regions (43) is 4 μm or more and 5 μm or less.

[0322] [Appendix 1-10] The semiconductor device (1A, 1B, 1C) according to any one of Appendices 1-1 to 1-9, wherein a total length (TL) of the spacing (W) and width (S) of the plurality of field regions (43) is constant in a direction from the active region (8) toward the peripheral region (9).

[0323] [Note 1-11] The density of each of the field regions (43) is 1×10 １５ cm －３ The semiconductor device (1A, 1B, 1C) according to any one of Supplementary Notes 1-1 to 1-10 is as described above.

[0324] [Supplementary Note 1-12] The semiconductor device (1A) according to any one of Supplementary Note 1-1 to Supplementary Note 1-11, wherein the device structure (Tr) includes: a body region (10) of a second conductivity type formed in a surface layer portion of the semiconductor region (7); a source region (11) of a first conductivity type formed in a surface layer portion of the body region (10); a plurality of gate trenches (16) arranged in a stripe pattern, which penetrate the source region (11) and the body region (10) to reach the semiconductor region (7); gate insulating films (17) formed on the inner surfaces of the plurality of gate trenches (16); and a plurality of trench gate structures (15) having gate electrodes (57) embedded in the plurality of gate trenches (16) via the gate insulating films (17).

[0325] [Appendix 1-13] The semiconductor device (1B) according to any one of Appendices 1-1 to 1-11, wherein the device structure (Tr) includes a plurality of planar gate structures (100) having a plurality of gate electrodes (105) arranged in a stripe pattern on the main surface (3) and a gate insulating film (104) between the plurality of gate electrodes (105) and the main surface (3), a plurality of body regions (101) of a second conductivity type formed in a surface layer portion of the semiconductor region (7) and facing the gate electrodes (105), and a first conductivity type source region (102) formed in a surface layer portion of each of the body regions (101).

[0326] [Appendix 1-14] The semiconductor device (1C) according to any one of Appendices 1-1 to 1-11, wherein the device structure (200) includes a Schottky barrier diode (200) including an anode region (204) of a second conductivity type formed in a surface layer portion of the semiconductor region (7), and a Schottky electrode (203) in Schottky junction with the anode region (204).

[0327] [Supplementary Note 1-15] The semiconductor device (1A, 1B, 1C) according to any one of Supplementary Note 1-1 to Supplementary Note 1-14, further including an outer well region (42) formed inside the plurality of field regions (43) in the peripheral region (9) and along a peripheral boundary (19) between the active region (8) and the peripheral region (9), wherein the outer well region (42) has a second upper end (42a) on the main surface (3) side and a second lower end (42b) on the opposite side thereof, and has a second concentration gradient that gradually decreases from the second upper end (42a) to the second lower end (42b).

[0328] [Appendix 1-16] The semiconductor device (1A, 1B, 1C) described in Appendix 1-15, wherein the second concentration gradient includes a second peak value (P2) on the second upper end (42a) side, and a second gradual portion (22) in which the impurity concentration gradually decreases at a gradual rate of decrease in a region closer to the second lower end (42b) than the second peak value (P2).

[0329] 1A: Semiconductor device 1B: Semiconductor device 1C: Semiconductor device 2: Chip 3: First main surface (main surface) 4: Second main surface 5A: First side surface 5B: Second side surface 5C: Third side surface 5D: Fourth side surface 6: First semiconductor region 7: Second semiconductor region 8: Active region 9: Peripheral region 10: Body region 11: Source region 15: Trench gate structure 15A: Terminal trench gate structure 16: Gate trench 16A: Terminal gate trench 17: Gate insulating film 17A: Terminal gate insulating film 18: First buried electrode 18A: Terminal first buried electrode 19: Peripheral boundary portion 20: Gradual increase portion 21: Peak portion 22: Second gradual decrease portion 23: Gradual decrease portion 25: Gate well region 25a : Bulging portion 25b : Well bottom 27 : Gate contact region 40 : Outer well region 41 : Outer contact region 42 : Outer well region 42a : Second upper end 42b : Second lower end 42c : Second main body portion 42d : First side portion 43 : Field region 43P : First field region 43Q : Second field region 43R : Third field region 43S : Fourth field region 43a : First upper end 43b : First lower end 43c : First main body portion 43d : Inner side portion (first side portion) 43e : Outer side portion (first side portion) 45 : Main surface insulating film 47 : Interlayer film 49 : Source opening 50 : Outer opening 51 : Source electrode 51a : First pad portion 51b : Second pad portion 51c : Third pad portion 52 : Lower electrode film 53 : Main electrode film 56 : Source wiring 57 : Gate electrode 58 : Gate wiring 59 : Drain electrode 62 : Boundary portion 63 : Center portion 64 : Edge portion 65 : Gap 66 : Center portion 67 : Edge portion 68 : Gap 71 : Base region 72 : High concentration region 73 : Sudden increase portion 74 : Peak portion 75 : Sudden decrease portion 85 : Gradual increase portion 86 : Peak portion 87 : First gradual portion 88 : Gradual decrease portion100: Planar gate structure 101: Body region 101a: Well side 101b: Well bottom 102: Source region 103: Channel region 104: Insulating film 105: Gate electrode 106: Low concentration region 200: Schottky barrier diode (device structure) 201: Interlayer insulating film 202: Contact opening 203: Schottky electrode 204: Anode region 205: Pad electrode CS1: First cross-sectional image CS2: Second cross-sectional image D1: Depth D2: Depth P0: Peak value P2: Peak value (second peak value) P4: Peak value (first peak value) S: Spacing S0: Spacing S1: First spacing S2: Second spacing S3: Third spacing T1: Thickness T2 : Thickness Tr: Transistor structure (device structure) W: Width W1: First width W2: Second width W3: Third width W4: Fourth width X: First direction Y: Second direction Z: Vertical direction α: Off angle θ1: Tilt angle θ2: Tilt angle

Claims

1. A semiconductor device comprising: a chip having a main surface; a semiconductor region of a first conductivity type formed in a surface layer portion of said main surface; an active region provided in an inner portion of said main surface; a peripheral region provided on the periphery of said main surface; a device structure formed within said active region; and a plurality of annular field regions of a second conductivity type formed at intervals in the surface layer portion of said semiconductor region in said peripheral region and surrounding said active region, wherein the spacing between said plurality of field regions increases in a direction from said active region toward said peripheral region, and the width of each of said plurality of field regions decreases in a direction from said active region toward said peripheral region, and each of said field regions has a first upper end on the side of said main surface and a first lower end on the opposite side, and wherein said field regions have a concentration gradient that gradually decreases from said first upper end toward said first lower end.

2. The semiconductor device of claim 1, wherein the concentration gradient includes a first peak value on the first upper end side, and a first gradual portion in which the impurity concentration gradually decreases at a gradual rate of decrease in a region on the first lower end side of the first peak value.

3. The semiconductor device according to claim 2, wherein said first loose portion occupies a thickness range of at least one-fourth of said field region.

4. The semiconductor device according to claim 3, wherein the first gradual portion has a thickness of 1.0 μm or more and 4.0 μm or less, and has a concentration reduction rate of 50% or less within this thickness range.

5. The semiconductor device according to any one of claims 2 to 4, wherein the chip is a SiC chip, and each of the field regions has a pair of first side portions that connect the first upper end and the first lower end and are inclined from the first upper end toward the first lower end, and in a cross-sectional view that crosses the active region along the m-axis direction ([1-100] direction) of the SiC single crystal and in which cross sections of the plurality of field regions appear on both sides of the active region, the pair of first side portions approach each other at an equal inclination from the first upper end toward the first lower end.

6. The semiconductor device according to claim 5, comprising a first cross-sectional image showing the plurality of field regions on one side and a second cross-sectional image showing the plurality of field regions on the other side in a cross-sectional view that crosses the active region along the a-axis direction ([11-20] direction) of the SiC single crystal and in which cross sections of the plurality of field regions appear on both sides of the active region, wherein in the first cross-sectional image, an inner side of the pair of first sides that is closer to the active region is inclined at a gentler inclination than an outer side that is farther from the active region, and in the second cross-sectional image, the outer side is inclined at a gentler inclination than the inner side.

7. A semiconductor device as described in claim 5 or 6, wherein the first upper end is formed in a shape that protrudes in an arc from the first side portion toward the main surface, and the first upper end is arranged such that the center portion in the width direction of the field region is exposed from the main surface, and the end portion in the width direction is positioned at a distance from the main surface.

8. The semiconductor device according to any one of claims 1 to 7, wherein the depth of each of said field regions is 2 μm or more.

9. The semiconductor device according to claim 8, wherein the depth of each of said field regions is not less than 4 μm and not more than 5 μm.

10. The semiconductor device according to any one of claims 1 to 9, wherein the total length of the spacing and width of said plurality of field regions is constant in the direction from said active region toward said peripheral region.

11. The density of each of the field regions is 1 x 10 １５ cm －３ The semiconductor device according to any one of claims 1 to 10, wherein:

12. A semiconductor device according to any one of claims 1 to 11, wherein the device structure includes a body region of a second conductivity type formed in a surface layer portion of the semiconductor region, a source region of a first conductivity type formed in a surface layer portion of the body region, a plurality of gate trenches arranged in a stripe pattern, which penetrate the source region and the body region to reach the semiconductor region, gate insulating films formed on the inner surfaces of the plurality of gate trenches, and a plurality of trench gate structures each having gate electrodes embedded in the plurality of gate trenches via the gate insulating films.

13. A semiconductor device according to any one of claims 1 to 11, wherein the device structure includes a plurality of planar gate structures having a plurality of gate electrodes arranged in a stripe pattern on the main surface and a gate insulating film between the plurality of gate electrodes and the main surface, a plurality of body regions of a second conductivity type formed in a surface layer portion of the semiconductor region and facing the gate electrodes, and a source region of a first conductivity type formed in a surface layer portion of each of the body regions.

14. A semiconductor device according to any one of claims 1 to 11, wherein the device structure includes a Schottky barrier diode including an anode region of the second conductivity type formed in a surface layer portion of the semiconductor region, and a Schottky electrode that is Schottky junctioned to the anode region.

15. A semiconductor device according to any one of claims 1 to 14, further comprising an outer well region formed inward of the plurality of field regions in the peripheral region and along the peripheral boundary between the active region and the peripheral region, the outer well region having a second upper end on the main surface side and a second lower end on the opposite side, and having a second concentration gradient that gradually decreases from the second upper end toward the second lower end.

16. The semiconductor device described in claim 15, wherein the second concentration gradient includes a second peak value on the second upper end side, and a second gradual portion in which the impurity concentration gradually decreases at a gradual rate of decrease in a region on the second lower end side of the second peak value.

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