Semiconductor device

Abstract

A semiconductor device including: a chip having a main surface; a trench electrode type gate structure formed on the main surface, the gate structure including a trench formed on the main surface, a trench insulating film that covers an inner surface of the trench, and a buried conductive layer embedded in the trench via the trench insulating film; a recess defined by an upper surface of the buried conductive layer and side surfaces of the trench; and a buried insulating layer embedded in the recess. The buried conductive layer is formed of a conductive material having a lower resistance than polysilicon.

Description

Semiconductor Devices Related Applications

[0001] This application corresponds to Japanese Patent Application No. 2024-043780 filed with the Japan Patent Office on March 19, 2024, the entire disclosure of which is incorporated herein by reference.

[0002] The present disclosure relates to semiconductor devices.

[0003] Patent Document 1 (US2003 / 0227051A1) discloses a semiconductor device having an active groove formed in an n-type semiconductor layer, in which a p-type buried region is disposed on the bottom side of the active groove, and a gate electrode is disposed on the opening side of the active groove via a gate insulating film.

[0004] US Patent Application Publication No. 2003 / 0227051

[0005] [Summary] One embodiment of the present disclosure provides a semiconductor device including: a chip having a main surface; and a trench electrode type gate structure formed on the main surface, the gate structure including a trench formed on the main surface, a trench insulating film covering an inner surface of the trench, a buried conductive layer buried in the trench via the trench insulating film; a recess defined by an upper surface of the buried conductive layer and a side surface of the trench; and a buried insulating layer buried in the recess, wherein the buried conductive layer is formed of a conductive material having a lower resistance than polysilicon.

[0006] FIG. 1 is a plan view showing a semiconductor device according to an embodiment of the present disclosure. FIG. 2 is a cross-sectional view taken along line II-II in FIG. 1 . FIG. 3 is a plan view showing an example chip layout. FIG. 4 is a perspective view showing an example chip layout. FIG. 5 is a perspective view showing an active region and a gate structure. FIG. 6 is a cross-sectional view taken along line VI-VI in FIG. 5 . FIG. 7 is a cross-sectional view taken along line VII-VII in FIG. 5 . FIG. 8 is the same cross-sectional view as FIG. 6 , mainly showing dimensions of various components. FIG. 9 is the same cross-sectional view as FIG. 7 , mainly showing dimensions of various components. FIG. 10 is an enlarged plan view showing a main portion of an active region. FIG. 11 is a cross-sectional view taken along line XI-XI in FIG. 10 . FIG. 12 is a cross-sectional view showing a peripheral region. FIG. 13A is a diagram illustrating a part of a manufacturing process of the semiconductor device. FIG. 13B is a diagram illustrating a process subsequent to FIG. 13A . FIG. 13C is a diagram illustrating a process subsequent to FIG. 13B . FIG. 13D is a diagram illustrating a process subsequent to FIG. 13C . FIG. 13E is a diagram showing a step subsequent to FIG. 13D. FIG. 14 shows another embodiment of the semiconductor device and is a cross-sectional view corresponding to FIG. 6. FIG. 15 shows another embodiment of the semiconductor device and is a cross-sectional view corresponding to FIG. 11. FIG. 16A is a diagram for explaining a part of the manufacturing process of the semiconductor device of FIG. 14. FIG. 16B is a diagram showing a step subsequent to FIG. 16A. FIG. 16C is a diagram showing a step subsequent to FIG. 16B. FIG. 16D is a diagram showing a step subsequent to FIG. 16C. FIG. 16E is a diagram showing a step subsequent to FIG. 16D. FIG. 17 shows another embodiment of the semiconductor device and is a cross-sectional view corresponding to FIG. 6. FIG. 18 shows another embodiment of the semiconductor device and is a cross-sectional view corresponding to FIG. 6. FIG. 19 shows another embodiment of the semiconductor device and is a cross-sectional view corresponding to FIG. 11. FIG. 20 shows another embodiment of the semiconductor device and is a cross-sectional view corresponding to FIG. 11.

[0007] DETAILED DESCRIPTION Next, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

[0008] The accompanying drawings are all schematic diagrams and are not strictly illustrated, and the scale, ratio, angle, etc. are not necessarily consistent. Corresponding structures among the accompanying drawings are given the same reference numerals, and duplicated explanations have been omitted or simplified. For structures whose explanations have been omitted or simplified, the explanation given before the omission or simplification applies.

[0009] When the term "substantially" is used in this specification, this term includes a numerical value (form) equal to the numerical value (form) of the comparison target, as well as a numerical error (form error) within a range of ±10% based on the numerical value (form) of the comparison target. In the following description, terms such as "first," "second," and "third" are used, but these are symbols attached to the names of each structure to clarify the order of description, and are not intended to limit the names of each structure.

[0010] In the following description, the conductivity type of a semiconductor (impurity) is indicated using "p-type" or "n-type," but "n-type" may also be referred to as the "first conductivity type" and "p-type" as the "second conductivity type." Of course, "p-type" may also be referred to as the "first conductivity type" and "n-type" as the "second conductivity type." "n-type" is a conductivity type resulting from a pentavalent element, and "p-type" is a conductivity type resulting from a trivalent element. Unless otherwise specified, the trivalent element is at least one of boron, aluminum, gallium, and indium. Unless otherwise specified, the pentavalent element is at least one of nitrogen, phosphorus, arsenic, antimony, and bismuth.

[0011] [Overall Configuration of Semiconductor Device 1] Fig. 1 is a plan view showing a semiconductor device 1 according to an embodiment of the present disclosure. Fig. 2 is a cross-sectional view taken along line II-II shown in Fig. 1. Fig. 3 is a plan view showing an example layout of a chip 2. Fig. 4 is a perspective view showing an example layout of the chip 2.

[0012] 1 to 4, a semiconductor device 1 is a semiconductor switching device having an insulated gate transistor structure Tr as an example of a device structure. The transistor structure Tr has a trench gate vertical structure.

[0013] The semiconductor device 1 includes a chip 2 formed in a hexahedral shape (specifically, a rectangular parallelepiped shape). In this embodiment, the chip 2 includes a single crystal of a wide bandgap semiconductor. In other words, the semiconductor device 1 is a "wide bandgap semiconductor device." The chip 2 may also be referred to as a "semiconductor chip," a "wide bandgap semiconductor chip," or the like.

[0014] A wide bandgap semiconductor is a semiconductor having a bandgap that exceeds the bandgap of Si (silicon). Examples of wide bandgap semiconductors include GaN (gallium nitride), SiC (silicon carbide), and C (diamond). In this embodiment, the chip 2 is a "SiC chip" that includes a hexagonal SiC single crystal as an example of a wide bandgap semiconductor. In other words, the semiconductor device 1 is a "SiC semiconductor device."

[0015] Hexagonal SiC single crystal has a plurality of polytypes including 2H (Hexagonal)-SiC single crystal, 4H-SiC single crystal, 6H-SiC single crystal, etc. In this embodiment, an example is shown in which the chip 2 includes a 4H-SiC single crystal, but the chip 2 may also include other polytypes.

[0016] The chip 2 has a first main surface 3 on one side, a second main surface 4 on the other side, and first to fourth side surfaces 5A to 5D connecting the first main surface 3 and the second main surface 4. The first main surface 3 and the second main surface 4 are formed in a quadrangular shape in a plan view seen from the vertical direction Z (hereinafter simply referred to as a "plan view"). The vertical direction Z is also the thickness direction of the chip 2 and the normal direction to the first main surface 3 (second main surface 4). The first main surface 3 and the second main surface 4 may be formed in a square or rectangular shape in a plan view.

[0017] The first main surface 3 and the second main surface 4 are preferably formed by the c-plane of the SiC single crystal. In this case, it is preferable that the first main surface 3 is formed by the silicon surface ((0001) surface) of the SiC single crystal, and the second main surface 4 is formed by the carbon surface ((000-1) surface) of the SiC single crystal.

[0018] The first side surface 5A and the second side surface 5B extend in a first direction X along the first main surface 3 and face a second direction Y that intersects with the first direction X along the first main surface 3. Specifically, the second direction Y is perpendicular to the first direction X. The third side surface 5C and the fourth side surface 5D extend in the second direction Y and face the first direction X.

[0019] In this embodiment, the first direction X is the m-axis direction ([1-100] direction) of the SiC single crystal, and the second direction Y is the a-axis direction ([11-20] direction) of the SiC single crystal. Of course, the first direction X may be the a-axis direction of the SiC single crystal, and the second direction Y may be the m-axis direction of the SiC single crystal.

[0020] The XY plane including the first direction X and the second direction Y forms a horizontal plane perpendicular to the vertical direction Z. Hereinafter, an axis extending along the vertical direction Z may be referred to as a "vertical axis." Also, below, the first direction X and the second direction Y may be referred to as a "horizontal direction." The horizontal direction is also a direction extending along the first main surface 3.

[0021] 4, the chip 2 (first main surface 3 and second main surface 4) has an off angle θo inclined at a predetermined angle in a predetermined off direction Do with respect to the c-plane of the SiC single crystal. That is, the c-axis ((0001) axis) of the SiC single crystal is inclined from the vertical axis toward the off direction Do by the off angle θo. Furthermore, the c-plane of the SiC single crystal is inclined with respect to the horizontal plane by the off angle θo.

[0022] The off-direction Do is preferably the a-axis direction of the SiC single crystal (i.e., the second direction Y). The off-angle θo may be greater than 0° and less than or equal to 10°. The off-angle θo may have a value belonging to any one of the ranges of greater than 0° and less than or equal to 1°, 1° or more and less than or equal to 2.5°, 2.5° or more and less than or equal to 5°, 5° or more and less than or equal to 7.5°, and 7.5° or more and less than or equal to 10°.

[0023] The off angle θo is preferably 5° or less. The off angle θo is particularly preferably 2° or more and 4.5° or less. The off angle θo is typically set in the range of 4°±0.1°. Of course, this specification does not exclude a configuration in which the off angle θo is 0° (i.e., a configuration in which the first main surface 3 is a just plane with respect to the c-plane).

[0024] The semiconductor device 1 includes an n-type first semiconductor layer 6 formed in a surface layer portion of the second main surface 4. A drain potential is applied to the first semiconductor layer 6 as a first potential (high potential). The first semiconductor layer 6 may also be referred to as a "semiconductor region (layer)," a "base region (layer)," a "drain region (layer)," or the like.

[0025] The first semiconductor layer 6 extends in a layered form along the second main surface 4, and forms the second main surface 4 and first to fourth side surfaces 5A to 5D. In this embodiment, the first semiconductor layer 6 is made of an n-type semiconductor layer. Specifically, the first semiconductor layer 6 is made of a substrate (SiC substrate) containing SiC single crystal (semiconductor single crystal), and has the second main surface 4 and first to fourth side surfaces 5A to 5D. In this embodiment, the first semiconductor layer 6 is made of a substrate (i.e., a SiC substrate) made of SiC single crystal. The first semiconductor layer 6 has the off direction Do and off angle θo described above.

[0026] The first semiconductor layer 6 is 1×10 １８ cm －３ 1x10 or more ２１ cm －３ The first semiconductor layer 6 may have the following n-type impurity concentration as a peak value. The first semiconductor layer 6 preferably has an n-type impurity concentration that is approximately constant in the thickness direction. The n-type impurity concentration of the first semiconductor layer 6 is preferably adjusted by a single type of pentavalent element. It is particularly preferable that the n-type impurity concentration of the first semiconductor layer 6 is adjusted by a pentavalent element other than phosphorus. In this embodiment, the n-type impurity concentration of the first semiconductor layer 6 is adjusted by nitrogen.

[0027] The first semiconductor layer 6 may have a first thickness T1 of 10 μm to 500 μm. The first thickness T1 may have a value belonging to at least one of the ranges of 10 μm to 50 μm, 50 μm to 100 μm, 100 μm to 150 μm, 150 μm to 200 μm, 200 μm to 300 μm, 300 μm to 400 μm, and 400 μm to 500 μm.

[0028] The semiconductor device 1 includes an n-type second semiconductor layer 7 formed in a surface layer portion of the first main surface 3. The second semiconductor layer 7 may also be referred to as a "semiconductor region (layer)," a "drift region (layer)," or the like. The second semiconductor layer 7 extends in a layered form along the first main surface 3, and forms the first main surface 3 and the first to fourth side surfaces 5A to 5D.

[0029] In this embodiment, the second semiconductor layer 7 is made of an n-type semiconductor layer. Specifically, the second semiconductor layer 7 is made of an epitaxial layer (SiC epitaxial layer) including a SiC single crystal (semiconductor single crystal). The second semiconductor layer 7 (epitaxial layer) has the off-direction Do and off-angle θo described above. The second semiconductor layer 7 is made of an epitaxial layer (i.e., a SiC epitaxial layer) that is crystal-grown starting from the first semiconductor layer 6.

[0030] The second semiconductor layer 7 has a lower end and an upper end. The lower end of the second semiconductor layer 7 is the starting point of crystal growth, and the upper end of the second semiconductor layer 7 is the ending point of crystal growth. The lower end of the second semiconductor layer 7 is also the bottom of the second semiconductor layer 7. Since the second semiconductor layer 7 is grown continuously from the first semiconductor layer 6, the lower end of the second semiconductor layer 7 coincides with the upper end of the first semiconductor layer 6.

[0031] The second semiconductor layer 7 includes an n-type drift region 8. In this embodiment, the drift region 8 is formed by a part (n-type portion) of the second semiconductor layer 7.

[0032] The boundary between the first semiconductor layer 6 and the second semiconductor layer 7 is not necessarily visible, but can be indirectly evaluated and / or determined from other configurations or elements. The second semiconductor layer 7 has an off-direction Do and an off-angle θo that are substantially identical to the off-direction Do and the off-angle θo of the first semiconductor layer 6.

[0033] The second semiconductor layer 7 has a second thickness T2 that is less than the first thickness T1. The second thickness T2 may be 5 μm or more and 15 μm or less. The second thickness T2 may have a value that belongs to at least one of the ranges of 5 μm or more and 7.5 μm or less, 7.5 μm or more and 10 μm or less, 10 μm or more and 12.5 μm or less, and 12.5 μm or more and 15 μm or less.

[0034] The semiconductor device 1 includes an active region 9 defined in a chip 2. The active region 9 includes a device structure (transistor structure Tr) and is a region where an output current (drain current) is generated.

[0035] The active region 9 is set in the interior of the chip 2 at a distance from the periphery (first to fourth side surfaces 5A to 5D) of the chip 2 in plan view. The active region 9 is set in a polygonal shape (a quadrangle in this embodiment) having four sides parallel to the periphery of the chip 2 in plan view.

[0036] The ratio (area ratio) of the planar area of ​​the active region 9 to the planar area of ​​the first main surface 3 may be 0.5 or more and 0.95 or less. The area ratio may be 0.5 or more and 0.6 or less, 0.6 or more and 0.7 or less, 0.7 or more and 0.8 or less, 0.8 or more and 0.9 or less, or 0.9 or more and 0.95 or less.

[0037] The semiconductor device 1 includes a peripheral region 10 set outside the active region 9 in the chip 2. The peripheral region 10 is a region that does not include a device structure (transistor structure Tr). The peripheral region 10 is provided in a region between the periphery of the chip 2 and the active region 9 in a planar view. The peripheral region 10 extends in a strip shape along the active region 9 in a planar view, and is set in a polygonal ring shape (a square ring in this embodiment) that surrounds the active region 9.

[0038] The semiconductor device 1 includes a plurality of trench electrode type gate structures 11 formed on the first main surface 3 in the active region 9. The gate structures 11 may also be referred to as "trench structures," "trench gate structures," etc. A gate potential is applied to the plurality of gate structures 11 as a control potential.

[0039] The multiple gate structures 11 are arranged at intervals inward from the periphery of the active region 9. In this embodiment, the multiple gate structures 11 are arranged at intervals in the first direction X and are each formed in a strip shape extending in the second direction Y. In other words, the multiple gate structures 11 are arranged at intervals in the m-axis direction and each extend in the a-axis direction.

[0040] In this embodiment, the multiple gate structures 11 are arranged in stripes extending in the a-axis direction (second direction Y). The extending direction of the multiple gate structures 11 coincides with the off-direction Do of the second semiconductor layer 7. The multiple gate structures 11 are formed at intervals from the lower end (first semiconductor layer 6) of the second semiconductor layer 7 toward the first major surface 3, and face the first semiconductor layer 6 with a part of the second semiconductor layer 7 in between.

[0041] The semiconductor device 1 includes a plurality of p-type well regions 12 formed at intervals in the horizontal direction in the second semiconductor layer 7 of the active region 9. Specifically, the plurality of well regions 12 are formed at the bottom of the gate structure 11, respectively.

[0042] The semiconductor device 1 includes a p-type outer well region 13 and a p-type field region 14 formed in a surface layer portion of the first main surface 3 in a peripheral region 10 (the peripheral portion of the first main surface 3).

[0043] The semiconductor device 1 includes a surface insulating film 15 that selectively covers the first main surface 3. The surface insulating film 15 may also be referred to as an "outer surface insulating film," etc. The surface insulating film 15 covers the first main surface 3 in the peripheral region 10 in a film-like manner.

[0044] Specifically, the surface insulating film 15 covers the outer well region 13 and the plurality of field regions 14 in the peripheral region 10. The surface insulating film 15 is continuous with the first to fourth side surfaces 5A to 5D. The surface insulating film 15 may be formed at intervals inward from the first to fourth side surfaces 5A to 5D, exposing the peripheral edge portion of the first main surface 3.

[0045] The semiconductor device 1 includes one or more (one in this embodiment) gate wirings 66 arranged on the first main surface 3 in the peripheral region 10. The gate wiring 66 is arranged on the surface insulating film 15.

[0046] 3 , the gate wiring 66 extends in a strip shape along the periphery of the plurality of gate structures 11. The gate wiring 66 has a portion extending in a first direction X and a portion extending in a second direction Y. The gate wiring 66 extends in a strip shape so as to intersect (specifically, perpendicular to) the ends (both ends in this embodiment) of the plurality of gate structures 11.

[0047] In this embodiment, the gate wiring 66 is formed in an endless polygonal ring shape (e.g., a square ring shape) having four sides parallel to the periphery of the first main surface 3, and surrounds the plurality of gate structures 11 (active regions 9). Of course, the gate wiring 66 may be formed in a strip shape with ends. The gate wiring 66 may have an edge portion that connects the portion extending in the first direction X and the portion extending in the second direction Y in a planar view in an arc shape (preferably a quarter arc shape).

[0048] The semiconductor device 1 includes a gate pad wiring 67 arranged on the first main surface 3 in the peripheral region 10. The gate pad wiring 67 is electrically connected to the gate wiring 66 and applies a gate potential to the gate wiring 66.

[0049] The semiconductor device 1 includes an insulating interlayer film 65 that covers the surface insulating film 15. The interlayer film 65 may be referred to as an "insulating film," an "interlayer insulating film," an "intermediate insulating film," or the like. The interlayer film 65 may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film.

[0050] The semiconductor device 1 includes the aforementioned source pad electrode 70 disposed on the first main surface 3. The source pad electrode 70 may also be referred to as a "first main surface electrode," a "first terminal (electrode)," a "first pad (electrode)," a "source electrode," or the like. The source pad electrode 70 is disposed on the interlayer film 65.

[0051] In this embodiment, the source pad electrode 70 has a first pad portion 70a, a second pad portion 70b, and a third pad portion 70c. The first pad portion 70a has a relatively large planar area and forms the main body of the source pad electrode 70. In this embodiment, the first pad portion 70a is formed in a polygonal shape (a quadrangle in this embodiment) having four sides parallel to the periphery of the chip 2 in a plan view, and is located closer to the fourth side surface 5D than the center of the first main surface 3.

[0052] The second pad portion 70b has a planar area smaller than that of the first pad portion 70a, and is drawn out in a strip (rectangular) shape from one end of the first pad portion 70a in the second direction Y (the end on the first side surface 5A side) toward the third side surface 5C. The third pad portion 70c has a planar area smaller than that of the first pad portion 70a, and is drawn out in a strip (rectangular) shape from the other end of the first pad portion 70a in the second direction Y (the end on the second side surface 5B side) toward the third side surface 5C, and faces the second pad portion 70b in the second direction Y.

[0053] The planar area of ​​the third pad portion 70c may be approximately equal to the planar area of ​​the second pad portion 70b. The planar area of ​​the third pad portion 70c may be larger or smaller than the planar area of ​​the second pad portion 70b. Either or both of the second pad portion 70b and the third pad portion 70c may be used as a terminal portion for monitoring a current.

[0054] The source pad electrode 70 does not necessarily have to have both the second pad portion 70b and the third pad portion 70c at the same time. The source pad electrode 70 may have only one of the second pad portion 70b and the third pad portion 70c. The source pad electrode 70 may be composed of only the first pad portion 70a, and may not have both the second pad portion 70b and the third pad portion 70c.

[0055] The source pad electrode 70 covers the entire region of the interlayer film 65 where the source opening 68 is formed, and extends into the source opening 68 from above the interlayer film 65. The source pad electrode 70 has a portion that covers the interlayer film 65 in a film-like manner, a portion that covers the wall surface of the source opening 68 in a film-like manner, and a portion that covers the first main surface 3 within the source opening 68 in a film-like manner.

[0056] The semiconductor device 1 includes a gate pad electrode 80 disposed on the first main surface 3 at a distance from the source pad electrode 70. The gate pad electrode 80 may also be referred to as a "second main surface electrode," a "second terminal (electrode)," a "second pad (electrode)," a "gate electrode," or the like. The gate pad electrode 80 is disposed on the interlayer film 65 at a distance from the source pad electrode 70.

[0057] In this embodiment, the gate pad electrode 80 is disposed on a portion of the interlayer film 65 that covers the gate pad wiring 67, and faces the gate pad wiring 67 across the interlayer film 65. In this embodiment, the gate pad electrode 80 does not have a direct electrical connection to the gate pad wiring 67. Of course, the gate pad electrode 80 may be mechanically and electrically connected to the gate pad wiring 67 via one or more gate openings.

[0058] The gate pad electrode 80 is disposed in a region on the third side surface 5C side of the first pad portion 70a, and faces the center of the third side surface 5C and the first pad portion 70a in the first direction X. The gate pad electrode 80 is interposed in a region between the second pad portion 70b and the third pad portion 70c, and faces both the second pad portion 70b and the third pad portion 70c in the second direction Y.

[0059] The gate pad electrode 80 is formed in a polygonal shape (a quadrilateral shape in this embodiment) having four sides parallel to the periphery of the chip 2 in a plan view. The gate pad electrode 80 has a planar area smaller than the planar area of ​​the source pad electrode 70. The gate pad electrode 80 has a planar area smaller than the planar area of ​​the first pad portion 70a. The gate pad electrode 80 may have a planar area smaller than the planar area of ​​the second pad portion 70b (third pad portion 70c).

[0060] The gate pad electrode 80 faces the outer well region 13 across the interlayer film 65 and the gate pad wiring 67. In this embodiment, the gate pad electrode 80 is formed at a distance from the ends (both ends) of the plurality of gate structures 11. In other words, the gate pad electrode 80 does not face the plurality of gate structures 11 in the stacking direction. Of course, the gate structure 11 may have a portion that faces a part (for example, an end) of the gate structure 11 across the interlayer film 65.

[0061] The semiconductor device 1 includes a gate finger electrode 81 extending from the gate pad electrode 80 onto the first main surface 3. The gate finger electrode 81 may also be referred to as a "gate wiring" or a "gate finger." The gate finger electrode 81 transmits the gate potential applied to the gate pad electrode 80 to other regions.

[0062] The gate finger electrode 81 is drawn out from the gate pad electrode 80 onto a portion of the interlayer film 65 that covers the gate wiring 66. The gate finger electrode 81 is routed in a strip shape around the periphery of the first main surface 3 and in the region between the source pad electrode 70. The gate finger electrode 81 has a portion that extends in a strip shape in the first direction X and a portion that extends in a strip shape in the second direction Y in plan view.

[0063] In this embodiment, the gate finger electrode 81 is formed in a band shape with four sides parallel to the periphery of the first main surface 3, and surrounds the source pad electrode 70. The gate finger electrode 81 is arranged closer to the periphery of the first main surface 3 than both ends of the multiple gate structures 11. The gate finger electrode 81 may have an edge portion that connects the portion extending in the first direction X and the portion extending in the second direction Y in an arc shape (preferably a quarter arc shape).

[0064] The semiconductor device 1 includes a first slit portion 82 defined in a region between the source pad electrode 70 and the gate finger electrode 81. The first slit portion 82 exposes the interlayer film 65.

[0065] The semiconductor device 1 includes source finger electrodes 85 extending from the source pad electrode 70 onto the first main surface 3. The source finger electrodes 85 may also be referred to as "source wiring," "source fingers," etc. The source finger electrodes 85 transmit the gate potential applied to the source pad electrode 70 to other regions.

[0066] The source finger electrodes 85 are arranged at intervals from the gate pad electrode 80 and the gate finger electrodes 81. The source finger electrodes 85 are arranged in regions on the peripheral edge side of the first main surface 3 with respect to both end portions of the plurality of gate structures 11.

[0067] The source finger electrodes 85 are drawn out from the source pad electrode 70 onto the interlayer film 65. The source finger electrodes 85 are routed in a strip shape around the periphery of the first main surface 3 and in the region between the source pad electrodes 70. The source finger electrodes 85 have a portion extending in a strip shape in the first direction X and a portion extending in a strip shape in the second direction Y in plan view.

[0068] In this embodiment, the source finger electrode 85 is formed in a band shape with four sides parallel to the periphery of the first main surface 3, and surrounds the source pad electrode 70 and the gate finger electrode 81. The outer well region 13 may have an edge portion that connects the portion extending in the first direction X and the portion extending in the second direction Y in an arc shape (preferably a quarter arc shape).

[0069] The semiconductor device 1 includes a second slit portion 86 defined in a region between the gate finger electrode 81 and the source finger electrode 85. The second slit portion 86 is defined in a region between the outer edge of the gate wiring 66 and the outer edge of the outer well region 13, and overlaps the first main surface 3 in the stacking direction.

[0070] The semiconductor device 1 includes a drain pad electrode 87 covering the second main surface 4. The drain pad electrode 87 may also be referred to as a "third main surface electrode," a "third terminal (electrode)," a "third pad (electrode)," a "drain electrode," or the like. The drain pad electrode 87 is mechanically and electrically connected to the first semiconductor layer 6. The drain pad electrode 87 forms ohmic contact with the first semiconductor layer 6.

[0071] The drain pad electrode 87 may cover the entire second main surface 4 so as to be continuous with the periphery (first to fourth side surfaces 5A to 5D) of the second main surface 4. The drain pad electrode 87 may also cover a portion of the second main surface 4 so as to expose the periphery of the second main surface 4.

[0072] A breakdown voltage that can be applied between source pad electrode 70 and drain pad electrode 87 (between first main surface 3 and second main surface 4) may be 500 V or more and 3000 V or less. The breakdown voltage may have a value belonging to at least one of the ranges of 500 V or more and 750 V or less, 750 V or more and 1000 V or less, 1000 V or more and 1250 V or less, 1250 V or more and 1500 V or less, 1500 V or more and 1750 V or less, 1750 V or more and 2000 V or less, 2000 V or more and 2250 V or less, 2250 V or more and 2500 V or less, and 2500 V or more and 3000 V or less.

[0073] [Detailed Structure of Active Region 9 of Semiconductor Device 1] Fig. 5 is a perspective view showing the active region 9 and gate structure 11. Fig. 6 is a cross-sectional view taken along line VI-VI in Fig. 5. Fig. 7 is a cross-sectional view taken along line VII-VII in Fig. 5. Fig. 8 is the same cross-sectional view as Fig. 6, mainly showing the dimensions of each part. Fig. 9 is the same cross-sectional view as Fig. 7, mainly showing the dimensions of each part.

[0074] In the following, for clarity of the drawings, the dimensions (thickness, width, depth, etc.) of each part of the semiconductor device 1 are shown in Figures 8 and 9, and are omitted from Figures 5 to 7. In Figures 8 and 9, in addition to the dimensions of each part, reference numerals are used to denote the main components.

[0075] 5 to 9, semiconductor device 1 includes p-type body region 18 formed in a surface layer portion of drift region 8. In this embodiment, body region 18, which is an example of a second impurity region, is formed in a layer shape extending along first main surface 3. Referring to Fig. 5, body region 18 is formed at an interval from the lower end of second semiconductor layer 7 toward first main surface 3.

[0076] The body region 18 is 1×10 １５ cm －３ 1x10 or more１８ cm －３ The p-type impurity concentration of the body region 18 may have the following peak value: The p-type impurity concentration of the body region 18 is preferably adjusted by at least one trivalent element. The trivalent element of the body region 18 may be at least one of boron, aluminum, gallium, and indium.

[0077] As described above, the semiconductor device 1 includes gate structures 11. With reference to Figures 8 and 9, each gate structure 11 has a trench width WT in the arrangement direction and a trench depth DT in the vertical direction Z. The trench width WT is preferably less than the second thickness T2 (see Figure 4) of the second semiconductor layer 7. The trench width WT may be not less than 0.1 µm and not more than 5 µm.

[0078] The trench width WT may have a value belonging to any one of the ranges of 0.1 μm to 0.25 μm, 0.25 μm to 0.5 μm, 0.5 μm to 0.75 μm, 0.75 μm to 1 μm, 1 μm to 1.5 μm, 1.5 μm to 2 μm, 2 μm to 2.5 μm, 2.5 μm to 3 μm, 3 μm to 3.5 μm, 3.5 μm to 4 μm, 4 μm to 4.5 μm, and 4.5 μm to 5 μm.

[0079] The trench depth DT is preferably less than the second thickness T2 of the second semiconductor layer 7. The trench depth DT is preferably greater than the trench width WT. In other words, the multiple gate structures 11 preferably each have an aspect ratio DT / WT such that they extend in a vertically elongated columnar shape. The aspect ratio DT / WT is the ratio of the trench width WT to the trench depth DT. The aspect ratio DT / WT may be, for example, 1 or more and 5 or less, and is preferably 1 or more and 3 or less.

[0080] The trench depth DT may be 0.1 μm or more and 5 μm or less. The trench depth DT may have a value belonging to any one of the ranges of 0.1 μm or more and 0.25 μm or less, 0.25 μm or more and 0.5 μm or less, 0.5 μm or more and 1 μm or less, 1 μm or more and 1.5 μm or less, 1.5 μm or more and 2 μm or less, 2 μm or more and 3 μm or less, 3 μm or more and 4 μm or less, and 4 μm or more and 5 μm or less. The trench depth DT is preferably 0.1 μm or more and 1.5 μm or less, and more preferably 0.5 μm or more and 1.5 μm or less.

[0081] The multiple gate structures 11 are arranged at intervals of a trench pitch PT in the first direction X. The trench pitch PT is preferably less than the second thickness T2 of the second semiconductor layer 7. The trench pitch PT is preferably less than the trench depth DT. The trench pitch PT may be 0.1 μm or more and 5 μm or less.

[0082] The trench pitch PT may have a value belonging to any one of the following ranges: 0.1 μm to 0.25 μm, 0.25 μm to 0.5 μm, 0.5 μm to 0.75 μm, 0.75 μm to 1 μm, 1 μm to 1.5 μm, 1.5 μm to 2 μm, 2 μm to 2.5 μm, 2.5 μm to 3 μm, 3 μm to 3.5 μm, 3.5 μm to 4 μm, 4 μm to 4.5 μm, and 4.5 μm to 5 μm. The trench pitch PT is preferably 0.5 μm to 3 μm, and more preferably 0.5 μm to 1.5 μm.

[0083] 5 to 7 , each gate structure 11 includes a trench 19, a trench insulating film 20, and a buried conductive layer 21. The trench 19 may be referred to as an "element trench," a "gate trench," or the like. The trench insulating film 20 may be referred to as an "element insulating film," a "gate insulating film," or the like. The buried conductive layer 21 may be referred to as a "buried electrode," a "gate electrode," or the like.

[0084] The trenches 19 are formed in the first main surface 3 and define the inner surfaces (side surfaces 22 and bottom surfaces 23 shown in FIGS. 6 and 7 ) of the gate structure 11. The bottom surfaces 23 of the trenches 19 preferably have flat portions. Between adjacent trenches 19, mesa portions 24 are formed by part of the second semiconductor layer 7. The mesa portions 24 may also be referred to as "element mesa portions."

[0085] 5, the gate structures 11 (trenches 19) and mesa portions 24 are strip-shaped extending along the second direction Y and are arranged alternately in the first direction X. The trenches 19 and mesa portions 24 are arranged in a stripe pattern as a whole.

[0086] 6 and 7 , it is particularly preferable that the flat portion of bottom surface 23 of trench 19 extends substantially parallel to first main surface 3. That is, it is preferable that the bottom wall of trench 19 has an off angle θo inclined at a predetermined angle in a predetermined off direction Do (see FIG. 4 ) with respect to the c-plane. That is, it is preferable that bottom surface 23 of trench 19 has a flat portion extending in off direction Do. Of course, bottom surface 23 of trench 19 may be curved in an arc shape toward the lower end side of second semiconductor layer 7.

[0087] The trench insulating film 20 covers the inner surface of the trench 19. The trench insulating film 20 may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. In this embodiment, the trench insulating film 20 has a single-layer structure made of a silicon oxide film. The trench insulating film 20 may also include a silicon oxide film made of an oxide of the chip 2. It is more preferable that the trench insulating film 20 be made of a high-dielectric material (high-k insulating material).

[0088] High-dielectric materials (high-k insulating materials) are a general term for materials having a higher relative dielectric constant k than, for example, silicon oxide. Examples of high-dielectric materials (high-k insulating materials) include HfSiO, HfSiON, and HfO. ２ , HfAl ｘ O ｙ Hafnium-based materials such as AlSiO, Al ２ O３ Aluminum-based materials such as ZrO ２ Examples of zirconium-based high dielectric materials include:

[0089] The thickness of trench insulating film 20 may be, for example, 0.020 μm to 0.090 μm, or may have a value belonging to at least one of the ranges of 0.020 μm to 0.040 μm, 0.040 μm to 0.060 μm, and 0.060 μm to 0.090 μm.

[0090] The buried conductive layer 21 is buried in the trench 19 and faces the channel across the trench insulating film 20. In this embodiment, the buried conductive layer 21 faces the body region 18 across the trench insulating film 20.

[0091] 6 and 7 , the buried conductive layer 21 is buried up to the middle of the trench 19 in the depth direction. The buried conductive layer 21 has an upper surface 25 located closer to the second main surface 4 than the first main surface 3. A low step 26 is formed on the second main surface 4 side between the upper surface 25 of the buried conductive layer 21 and the first main surface 3. This step 26 forms a recess 27 in the upper part of the trench 19, which is defined by the upper surface 25 of the buried conductive layer 21 and the side surface 22 of the trench 19.

[0092] The recess 27 is a space sandwiched between both side surfaces 22 of the trench 19 and an upper surface 25 of the buried conductive layer 21. As shown in FIG. 5 , the recess 27 is formed in a continuous strip shape in the depth direction (second direction Y) of the trench 19. The trench insulating film 20 is selectively formed in a region sandwiched between the inner surface of the trench 19 and the buried conductive layer 21, and the side surface 22 of the recess 27 (part of the side surface 22 of the trench 19) is exposed from the trench insulating film 20.

[0093] Due to the formation of the recess 27, a part of the mesa portion 24 in the depth direction of the trench 19 protrudes as a protrusion 28 toward the first main surface 3 (upward) beyond the buried conductive layer 21. As shown in Fig. 5 , the protrusion 28 of the mesa portion 24 is a part of the mesa portion 24 sandwiched between adjacent recesses 27, and is formed in a continuous band shape in the depth direction of the trench 19.

[0094] The buried conductive layer 21 is formed of a conductive material having a lower resistance than polysilicon. The buried conductive layer 21 may be a metal layer. The buried conductive layer 21 may be formed of at least one selected from the group consisting of tungsten, nickel, molybdenum, platinum, titanium, and cobalt. The buried conductive layer 21 may be formed of at least one metal silicide selected from the group consisting of tungsten, nickel, molybdenum, platinum, titanium, and cobalt. Specifically, the buried conductive layer 21 may be tungsten silicide represented by WSix (x is an integer of 1 or more), nickel silicide represented by NiSix (x is an integer of 1 or more), molybdenum silicide, platinum silicide, titanium silicide, cobalt silicide, or the like.

[0095] As described above, the semiconductor device 1 includes the well region 12. The well region 12 is formed in the bottom of the gate structure 11. More specifically, the well region 12 is formed in the bottom of the trench 19. The well region 12 is exposed from the bottom surface 23 of the trench 19 and is in contact with the trench insulating film 20. Therefore, the upper end of the well region 12 is exposed at the bottom surface 23 of the gate structure 11 (trench 19). The well region 12 may also be referred to as an "electric field relaxation layer."

[0096] The well region 12 faces the buried conductive layer 21 via the trench insulating film 20 in the depth direction of the trench 19. At the bottom of the trench 19, the trench insulating film 20 is sandwiched between the buried conductive layer 21 and the well region 12.

[0097] 5, well region 12 is formed in the bottom of trench 19 over the entire depth of trench 19, and is formed in a strip shape extending in the depth direction of trench 19. With reference to FIGS. 6 and 7, well region 12 is formed across one end and the other end of trench 19 in the width direction of trench 19. In this embodiment, well region 12 has, in the depth direction of trench 19, one side surface 29 formed on approximately the same plane as one side surface 22 of trench 19 in the width direction, and the other side surface 29 formed on approximately the same plane as the other side surface 22 of trench 19 in the width direction.

[0098] In other words, each well region 12 has a side surface 29 that is flush with both side surfaces 22 of the trench 19 in the depth direction of the gate structure 11. The side surface 29 of the well region 12 extends in the depth direction of the gate structure 11 and forms a boundary surface with the second semiconductor layer 7 (drift region 8). Therefore, the well region 12 is physically separated from the body region 18 in the depth direction of the gate structure 11 and forms the entire bottom surface 23 of the gate structure 11.

[0099] In this embodiment, the well region 12 has a stacked structure of a first layer 30 and a second layer 31. The first layer 30 is a layer formed away from the bottom of the trench 19 (bottom surface 23 in this embodiment) toward the second main surface 4. The second layer 31 is a layer formed between the first layer 30 and the bottom of the trench 19 (bottom surface 23 in this embodiment). The second layer 31 is exposed from the bottom surface 23 of the trench 19 and contacts the trench insulating film 20. The second layer 31 is sandwiched between the first layer 30 and the trench 19 portion.

[0100] Regarding the impurity concentration of the well region 12, the first layer 30 has a first impurity concentration, and the second layer 31 has a second impurity concentration. In this embodiment, the second impurity concentration of the second layer 31 is higher than the first impurity concentration of the first layer 30. Furthermore, the first impurity concentration of the first layer 30 may be equal to the impurity concentration of the body region 18. The second impurity concentration of the second layer 31 may be higher than the impurity concentration of the body region 18.

[0101] For example, the first impurity concentration of the first layer 30 is 1×10１５ cm －３ 1x10 or more １８ cm －３ The second layer 31 may have a p-type impurity concentration of 1×10 or less as a peak value. １８ cm －３ 1x10 or more ２１ cm －３ The p-type impurity concentration of the first layer 30 and the second layer 31 may have the following peak value. The p-type impurity concentration of the first layer 30 and the second layer 31 is preferably adjusted by at least one trivalent element. The trivalent element of the first layer 30 and the second layer 31 may be at least one of boron, aluminum, gallium, and indium.

[0102] The stacked structure of the first layer 30 and the second layer 31 is continuous in the depth direction of the trench 19. In this embodiment, as shown in FIG. 5 , the well region 12 is formed in a strip shape extending in the depth direction of the trench 19 so that the stacked structure of the first layer 30 and the second layer 31 is continuous throughout the entire depth direction of the trench 19. For example, the multiple well regions 12 are arranged at intervals in the m-axis direction and extend in the a-axis direction of the SiC single crystal. The multiple well regions 12 are formed in a stripe shape extending in the a-axis direction (second direction Y), and the extending direction of the multiple well regions 12 coincides with the off-direction Do (see FIG. 4 ) of the second semiconductor layer 7.

[0103] The multiple well regions 12 overlap the multiple gate structures 11 in the depth direction of the trench 19. Specifically, the multiple well regions 12 overlap the multiple gate structures 11 in a one-to-one correspondence in the thickness direction of the chip 2. In this configuration, the multiple well regions 12 are connected to the bottom surfaces 23 of the corresponding gate structures 11.

[0104] 8 and 9, well region 12 has a relaxation depth DR in the vertical direction Z.

[0105] The relaxation depth DR may have a value in any one of the ranges of more than 0.25 μm to 0.5 μm, 0.5 μm to 1 μm, 1 μm to 1.5 μm, 1.5 μm to 2 μm, 2 μm to 3 μm, 3 μm to 4 μm, and 4 μm to 5 μm. The relaxation depth DR is preferably 1.5 μm to 2.5 μm.

[0106] Each of the multiple well regions 12 has a relaxed width WR in the arrangement direction. The relaxed width WR may be 0.25 μm or more and 5 μm or less. The relaxed width WR may have a value belonging to any one of the following ranges: 0.25 μm or more and 0.5 μm or less, 0.5 μm or more and 0.75 μm or less, 0.75 μm or more and 1 μm or less, 1 μm or more and 1.5 μm or less, 1.5 μm or more and 2 μm or less, 2 μm or more and 2.5 μm or less, 2.5 μm or more and 3 μm or less, 3 μm or more and 3.5 μm or less, 3.5 μm or more and 4 μm or less, 4 μm or more and 4.5 μm or less, and 4.5 μm or more and 5 μm or less.

[0107] 5 and 6 , semiconductor device 1 includes a source region 32 as an example of a third impurity region in a surface layer portion of first main surface 3. Source region 32 is formed in a region between a plurality of gate structures 11. Source region 32 is formed in a surface layer portion of body region 18.

[0108] In this embodiment, a plurality of source regions 32 are formed across the mesa portion 24 in the width direction, extending from one side surface 22 of the mesa portion 24 to the other side surface 22 (one side surface 22 and the other side surface 22 of the trench 19). The plurality of source regions 32 are arranged at intervals in each mesa portion 24 along the depth direction of the trench 19. As a result, in each mesa portion 24, a plurality of channel sections 33 are arranged at intervals in the second direction Y (depth direction of the trench 19). In the channel sections 33, channels are formed on both side surfaces 22 of the trench 19 on both sides of the mesa portion 24 in the first direction X.

[0109] The source region 32 has a higher n-type impurity concentration (peak value) than the second semiconductor layer 7 (drift region 8). １８ cm －３ 1x10 or more ２１cm －３ The n-type impurity concentration may have the following peak value:

[0110] 8 , source region 32 has a source thickness ST1. Source thickness ST1 may be the thickness of source region 32 in vertical direction Z from first main surface 3. Source thickness ST1 may be, for example, not less than 0.2 μm and not more than 1.0 μm, preferably not less than 0.4 μm and not more than 0.8 μm.

[0111] 5 and 7 , semiconductor device 1 includes first contact region 34 in a surface layer portion of first main surface 3. First contact region 34 is formed in a region between a plurality of gate structures 11. First contact region 34 is formed adjacent to source region 32 in a surface layer portion of body region 18.

[0112] In this embodiment, a plurality of first contact regions 34 are formed across the mesa portion 24 in the width direction, from one side surface 22 to the other side surface 22 of the mesa portion 24. In each mesa portion 24, the plurality of source regions 32 and the plurality of first contact regions 34 are alternately arranged along the depth direction of the trench 19. Each source region 32 and each first contact region 34 is exposed from both side surfaces 22 of the trench 19 (both side surfaces 22 of the mesa portion 24).

[0113] 6 and 7 , the body region 18 includes a first body portion 35 ( FIG. 6 ) formed directly below the source region 32 and a second body portion 36 ( FIG. 7 ) formed directly below the first contact region 34. The first body portion 35 is a portion of the body region 18 that is sandwiched between the source region 32 and the drift region 8 in the depth direction of the trench 19. The second body portion 36 is a portion of the body region 18 that is sandwiched between the first contact region 34 and the drift region 8 in the depth direction of the trench 19.

[0114] 8 and 9, the first body portion 35 has a first body thickness BT1, and the second body portion 36 has a second body thickness BT2. The second body thickness BT2 is greater than the first body thickness BT1. Referring to FIGS. 5 to 7, the body region 18 forms a base interface 37 with the drift region 8. The base interface 37 is located at a certain depth from the bottom surface 23 of the trench 19 along the depth direction of the trench 19. As shown in FIG. 5, the body region 18 has a body protrusion 38 that selectively protrudes toward the first main surface 3 directly below the first contact region 34. The body protrusion 38 causes the body region 18 to have a second body portion 36 that is selectively thicker than the base interface 37.

[0115] 6, a first boundary surface 39 between the first body portion 35 and the source region 32 is located closer to the second main surface 4 than the upper surface 25 of the buried conductive layer 21. The first boundary surface 39 is formed at a position lower than the upper surface 25 of the buried conductive layer 21, and a first step 40 is formed between the upper surface 25 of the buried conductive layer 21 and the first boundary surface 39. A part of the source region 32 (for example, the lower end) faces the buried conductive layer 21 via the trench insulating film 20. This ensures the formation of a channel between the source and the drain.

[0116] 7 , a second boundary surface 41 between the second body portion 36 and the first contact region 34 is located closer to the first main surface 3 than the upper surface 25 of the buried conductive layer 21. The second boundary surface 41 is formed at a position higher than the upper surface 25 of the buried conductive layer 21, and a second step 42 is formed between the upper surface 25 of the buried conductive layer 21 and the second boundary surface 41. A part (for example, an upper end) of the second body portion 36 protrudes toward the first main surface 3 (upper side) beyond the buried conductive layer 21. The first contact region 34 does not directly contribute to the formation of a channel between the source and drain, and therefore, unlike the source region 32, does not need to face the buried conductive layer 21 via the trench insulating film 20.

[0117] 5 and 7 , the semiconductor device 1 includes a second contact region 43 in a surface layer portion of the first main surface 3. The second contact region 43 is connected to the first contact region 34 and the well region 12. The second contact region 43 is formed along the side surface 22 of the trench 19 from the first contact region 34 toward the second main surface 4 and is connected to the well region 12. In this embodiment, the second contact region 43 is formed from the first contact region 34 exposed from both side surfaces 22 of the mesa portion 24 along both the one side surface 22 and the other side surface 22 of the mesa portion 24.

[0118] The second contact region 43 is formed over the entire depth direction of the trench 19 from the top to the bottom of the trench 19. The second contact region 43 has a lower end near the bottom of the trench 19 and an upper end near the top of the trench 19.

[0119] The second contact region 43 penetrates the body region 18 and straddles the gap between the body region 18 and the well region 12. The second contact region 43 forms a boundary with the body region 18 and is connected to the body region 18. The second contact region 43 is further connected to the second semiconductor layer 7 (drift region 8) below the body region 18. That is, a pn junction is formed by the second contact region 43 and the drift region 8 in the section between the body region 18 and the well region 12.

[0120] 7 , the second contact region 43 is exposed from the side surface 22 of the trench 19 and is in contact with the trench insulating film 20 at the side surface 22 of the trench 19. The lower end of the second contact region 43 is in contact with the second layer 31 of the well region 12. As a result, a p-type integral impurity region 44 is formed in the second semiconductor layer 7 by the first contact region 34, the second contact region 43, and the second layer 31.

[0121] 7 , on the side surface 22 and the bottom surface 23 of the trench 19, the integral impurity region 44 partially covers the buried conductive layer 21 via the trench insulating film 20. More specifically, both end corners 45 of the trench 19 in the width direction are covered by the integral impurity region 44 having a generally Z-shaped cross section in the second relaxation portion 47. This makes it possible to suppress electric field concentration at the corners 45 of the trench 19.

[0122] 6 , in the first relaxation portion 46, a part of the well region 12 (second layer 31) may be spaced apart from the corner of the trench 19. That is, in the depth direction of the trench 19, the corner 45 of the trench 19 may have a part that is covered by the well region 12 and a part that is not covered by the well region 12.

[0123] In this embodiment, a plurality of integral impurity regions 44 are formed at intervals along the depth direction of the trench 19. The first contact region 34 and the second contact region 43 have the same width along the depth direction of the trench 19, and form strip-shaped integral impurity regions 44 of a constant width on the top surface (first main surface 3) of the mesa portion 24 and on the side surface 22 of the mesa portion 24 (side surface 22 of the trench 19).

[0124] 6 and 7, the integrated impurity region 44 has a width greater than that of the first layer 30 of the well region 12 in the width direction of the trench 19. This is because the second contact region 43 is connected to the side of the second layer 31, and the portion of the second layer 31 that is integrated with the second contact region 43 is selectively wider.

[0125] 9 , the second contact region 43 has a second contact thickness CT2. The second contact thickness CT2 may be the thickness of the second contact region 43 in the horizontal direction from the side surface 22 of the trench 19. The second contact thickness CT2 may be, for example, not less than 10 nm and not more than 200 nm, preferably not less than 20 nm and not more than 100 nm.

[0126] 9 , the first contact region 34 has a first contact thickness CT1. The first contact thickness CT1 may be the thickness of the first contact region 34 in the vertical direction Z from the first main surface 3. In this embodiment, the first contact thickness CT1 is greater than the second contact thickness CT2. The first contact thickness CT1 may be, for example, not less than 0.1 μm and not more than 1.0 μm, preferably not less than 0.2 μm and not more than 0.5 μm.

[0127] 8 and 9, in this embodiment, the ratio of the thickness of the first layer 30 to the second layer 31 of the well region 12 is different between the first relaxation portion 46 (FIG. 6) formed directly below the source region 32 and the second relaxation portion 47 (FIG. 7) formed directly below the first contact region 34.

[0128] More specifically, it is assumed that the first layer 30 has a first relaxation thickness RT1A (RT1B) and the second layer 31 has a second relaxation thickness RT2A (RT2B). In this case, the thickness ratio (RT2A / RT1A) of the second relaxation thickness RT2A to the first relaxation thickness RT1A in the first relaxation portion 46 shown in Figure 8 is smaller than the thickness ratio (RT2B / RT1B) in the second relaxation portion 47 shown in Figure 9. Of course, the thickness ratio (RT2A / RT1A) may be the same as the thickness ratio (RT2B / RT1B).

[0129] For example, if the total thickness RT0 (RT1A+RT2A or RT1B+RT2B) defined by the relaxation depth DR of well region 12 is the same in first relaxation portion 46 and second relaxation portion 47, the first relaxation thickness RT1A in first relaxation portion 46 is greater than the first relaxation thickness RT1B in second relaxation portion 47. Conversely, the second relaxation thickness RT2A in first relaxation portion 46 is less than the second relaxation thickness RT2B in second relaxation portion 47. However, if the thickness ratio (RT2A / RT1A) is the same as the thickness ratio (RT2B / RT1B), the first relaxation thickness RT1A may be equal to the first relaxation thickness RT1B, and the second relaxation thickness RT2A may be equal to the second relaxation thickness RT2B.

[0130] In this embodiment, the first relaxation thickness RT1A may be 0.2 μm or more and 1.0 μm or less, and the second relaxation thickness RT2A may be 0.2 μm or more and 1.0 μm or less. The first relaxation thickness RT1A is preferably 0.4 μm or more and 0.8 μm or less, and the second relaxation thickness RT2A is preferably 0.4 μm or more and 0.8 μm or less.

[0131] The first relaxation thickness RT1B may be 0.1 μm or more and 0.6 μm or less, and the second relaxation thickness RT2B may be 0.1 μm or more and 0.6 μm or less. The first relaxation thickness RT1B is preferably 0.2 μm or more and 0.5 μm or less, and the second relaxation thickness RT2B is preferably 0.2 μm or more and 0.5 μm or less.

[0132] 6 and 7 , a first boundary surface 48 between the first layer 30 and the second layer 31 in the first relaxation section 46 is located closer to the first main surface 3 than a second boundary surface 49 between the first layer 30 and the second layer 31 in the second relaxation section 47. Conversely, the second boundary surface 49 is located closer to the second main surface 4 than the first boundary surface 48.

[0133] 5 to 7, drift region 8 includes a stacked structure of base region 50 and high concentration region 51.

[0134] The base region 50 is formed closer to the second main surface 4 than the well region 12 and away from the body region 18. The base region 50 is formed in a layer shape extending along the first main surface 3 at a position away from the body region 18 and the trench 19 toward the second main surface 4. The base region 50 is formed over the entire surface portion of the second semiconductor layer 7 on the second main surface 4 side, and may be exposed from the first to fourth side surfaces 5A to 5D. The base region 50 forms the boundary surface of the second semiconductor layer 7 with the first semiconductor layer 6.

[0135] 8 and 9, base region 50 has a base thickness BT. Base thickness BT may be equal to or greater than 0.5 μm and equal to or less than 20 μm. Base thickness BT is preferably equal to or greater than 1 μm and equal to or less than 10 μm.

[0136] The n-type impurity concentration of the base region 50 is preferably lower than the n-type impurity concentration of the first semiconductor layer 6. The base region 50 has a dopant concentration of 1×10１５ cm －３ 5x10 or more １６ cm －３ The n-type impurity concentration of the base region 50 may have a peak value of the following: The n-type impurity concentration of the base region 50 may be approximately constant in the thickness direction. Of course, the n-type impurity concentration of the base region 50 may have a concentration gradient that gradually increases and / or decreases in the thickness direction (crystal growth direction) of the chip 2.

[0137] 5 to 7, regarding the relationship between the well region 12 and the base region 50, the first layer 30 of the well region 12 is formed to a depth that reaches the base region 50 in the thickness direction of the chip 2. More specifically, the bottom of the first layer 30 of the well region 12 is in contact with the base region 50, forming a boundary between the well region 12 and the base region 50.

[0138] The high-concentration region 51 is formed between the base region 50 and the body region 18, on the side of the trench 19 and the well region 12. The high-concentration region 51 is in contact with the body region 18 and is formed in a layer shape extending along the first main surface 3. The high-concentration region 51 is formed in the entire surface portion of the drift region 8 on the first main surface 3 side, and may be exposed from the first to fourth side surfaces 5A to 5D. In this embodiment, the high-concentration region 51 forms the boundary surface between the drift region 8 and the body region 18.

[0139] In this embodiment, the high-concentration region 51 contacts the sides of the first layer 30 and the second layer 31 of the well region 12 over the entire thickness direction of the chip 2, from the first main surface 3 side to the second main surface 4 side. The high-concentration region 51 also covers the boundary between the bottom of the trench 19 and the well region 12 (see FIG. 6 ).

[0140] The n-type impurity concentration of the high concentration region 51 is preferably higher than the n-type impurity concentration of the base region 50. The high concentration region 51 has a concentration of 1×10 １８ cm －３ 1x10 or more １９ cm －３The n-type impurity concentration of the high-concentration region 51 may have a peak value of the following: The n-type impurity concentration of the high-concentration region 51 may be substantially constant in the thickness direction. Of course, the n-type impurity concentration of the high-concentration region 51 may have a concentration gradient that gradually increases and / or decreases in the thickness direction (crystal growth direction) of the chip 2.

[0141] 8 and 9, regarding the thickness of high concentration region 51, first thickness HT1 of high concentration region 51 may be not less than 0.6 μm and not more than 2.5 μm.

[0142] In this embodiment, the n-type impurity concentrations of the base region 50 and the high-concentration region 51 are adjusted by nitrogen. The base region 50 and the high-concentration region 51 may have n-type impurity concentrations adjusted by at least one pentavalent element. For example, the n-type impurity concentrations of the base region 50 and the high-concentration region 51 may be adjusted by at least one of nitrogen, phosphorus, arsenic, antimony, and bismuth.

[0143] The semiconductor device 1 includes a buried insulating layer 55 buried in the recess 27 of the second semiconductor layer 7. The buried insulating layer 55 may also be referred to as an "interlayer insulating layer," an "insulating film," an "interlayer film," an "intermediate insulating film," or the like. In this form, the buried insulating layer 55 may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film.

[0144] 6 and 7 , the buried insulating layer 55 is buried in the recess 27 so that an upper edge 56 of the trench 19 is exposed from the first main surface 3. The upper edge 56 of the trench 19 may be a portion at the top of the trench 19 where the side surface 22 of the trench 19 intersects with the first main surface 3. In other words, the buried insulating layer 55 does not cover the periphery of the trench 19 on the first main surface 3, but is contained within the inner region of the trench 19 in the width direction of the trench 19. In this form, the upper surface 57 of the buried insulating layer 55 is located closer to the bottom of the trench 19 than the first main surface 3 in the depth direction of the trench 19.

[0145] 5, buried insulating layer 55 is embedded in recess 27 over the entire depth direction of trench 19, and is formed in a strip shape extending in the depth direction of trench 19. Referring to Figures 6 and 7, buried insulating layer 55 contacts source region 32 and first contact region 34 on side surface 22 of recess 27 (side surface 22 of trench 19).

[0146] 8 and 9 , the thickness IT of the buried insulating layer 55 may be, for example, 0.2 μm or more and 0.6 μm or less. The thickness IT may have a value belonging to at least one of the ranges of 0.2 μm or more and 0.3 μm or less, 0.3 μm or more and 0.4 μm or less, 0.4 μm or more and 0.5 μm or less, and 0.5 μm or more and 0.6 μm or less.

[0147] 6 and 7 , semiconductor device 1 includes silicide layers 58 formed on the surfaces of source region 32 and first contact region 34. Formation of silicide layer 58 can reduce contact resistance with source region 32 and first contact region 34.

[0148] In this embodiment, the silicide layer 58 is selectively formed on the protruding portion 28 of each mesa portion 24. More specifically, the silicide layer 58 is formed along the upper surface (first main surface 3) and the side surface 22 (side surface 22 of the recess 27) of the protruding portion 28 of the mesa portion 24. A non-silicide portion 59 defined by the silicide layer 58 (surrounded on three sides) may be formed in the inner portion of the protruding portion 28 of the mesa portion 24 away from the upper surface (first main surface 3) and the side surface 22 of the mesa portion 24 inward.

[0149] The silicide layer 58 may be, for example, nickel silicide, titanium silicide, aluminum silicide, copper silicide, etc. The thickness ST2 of the silicide layer 58 may be, for example, 50 nm or more and 500 nm or less in the vertical direction Z from the upper surface (first main surface 3) and side surface 22 of the protruding portion 28 of the mesa portion 24. The thickness ST2 of the silicide layer 58 is preferably 80 nm or more and 300 nm or less.

[0150] 6 and 7 , semiconductor device 1 includes a first principal surface electrode 60. First principal surface electrode 60 is formed on first principal surface 3 so as to cover buried insulating layer 55. First principal surface electrode 60 has a laminated structure including a barrier layer 61 and a main body layer 62 laminated in this order from the first principal surface 3 side.

[0151] The barrier layer 61 is formed in a film shape along the first main surface 3 and the inner surfaces of the recess 27 (the side surfaces 22 of the recess 27 and the upper surface 57 of the buried insulating layer 55). The barrier layer 61 is in ohmic contact with the silicide layer 58. The barrier layer 61 further defines a second recess 63 within the recess 27.

[0152] The barrier layer 61 may include at least one of a Ti layer, a Pd layer, a Cr layer, a V layer, a Mo layer, a W layer, a Pt layer, and a Ni layer. The thickness of the barrier layer 61 may be 0.05 μm or more and 0.3 μm or less. The thickness of the barrier layer 61 is preferably 0.1 μm or more and 0.2 μm or less.

[0153] The main body layer 62 is formed on the barrier layer 61. The main body layer 62 covers the entire main surface of the barrier layer 61. The main body layer 62 is partially embedded in the second recess 63. The main body layer 62 is electrically connected to the source region 32 and the first contact region 34 via the barrier layer 61 and the silicide layer 58. In this embodiment, the first main surface electrode 60 is connected to the source region 32 and the first contact region 34 at the side surface 22 of the recess 27 and the first main surface 3. Therefore, in the semiconductor device 1, the first main surface electrode 60 may include the source pad electrode 70 described above. The well region 12 is fixed to the source potential via the first contact region 34 and the second contact region 43.

[0154] The main body layer 62 includes at least one of a pure Al layer (meaning an Al layer made of Al with a purity of 99% or more), an AlSi alloy layer, an AlCu alloy layer, and an AlSiCu alloy layer.

[0155] The thickness of the main layer 62 exceeds the thickness of the barrier layer 61. The thickness of the main layer 62 may be 1 μm or more and 10 μm or less. The thickness of the main layer 62 is preferably 3 μm or more and 6 μm or less.

[0156] The semiconductor device 1 includes a resin layer 64 that covers the first principal surface electrode 60. The resin layer 64 is formed in the form of a film along the principal surface of the first principal surface electrode 60. The resin layer 64 may include a photosensitive resin. The photosensitive resin may be a negative type or a positive type. The resin layer 64 may include at least one of polyimide, polyamide, and polybenzoxazole. In this embodiment, the resin layer 64 includes polybenzoxazole.

[0157] [Detailed Structure of the Vicinity of the Peripheral Region 10 of the Semiconductor Device 1] Fig. 10 is an enlarged plan view showing a main portion of the active region 9. Fig. 11 is a cross-sectional view taken along line XI-XI shown in Fig. 10. Fig. 12 is a cross-sectional view showing the peripheral region 10. With reference to Figs. 10 to 12, the detailed structure of the peripheral region 10 and the vicinities of the peripheral region 10 of the active region 9 will be described.

[0158] 11 and 12 , the aforementioned outer well region 13 is formed in the surface layer portion of the first main surface 3 in the peripheral region 10 (the peripheral portion of the first main surface 3). A source potential is applied to the outer well region 13. The outer well region 13 has a p-type impurity concentration higher than the n-type impurity concentration of the second semiconductor layer 7. The p-type impurity concentration of the outer well region 13 may be higher or lower than the p-type impurity concentration of the body region 18.

[0159] The p-type impurity concentration of the outer well region 13 is lower than the p-type impurity concentration of the first contact region 34. The p-type impurity concentration of the outer well region 13 is lower than the p-type impurity concentration of the second layer 31 of the well region 12. The p-type impurity concentration of the outer well region 13 may be higher or lower than the p-type impurity concentration of the first layer 30 of the well region 12.

[0160] The outer well region 13 is formed in a surface layer portion of the second semiconductor layer 7. The outer well region 13 extends in a layered manner along the first main surface 3. The outer well region 13 is formed at intervals from the periphery (first to fourth side surfaces 5A to 5D) of the first main surface 3 toward the multiple gate structures 11. The outer well region 13 extends in a strip shape along the periphery of the first main surface 3 (the periphery of the active region 9) in a plan view.

[0161] In this embodiment, the outer well region 13 is formed in a polygonal ring shape (a square ring shape in this embodiment) having four sides parallel to the periphery of the chip 2 in a plan view, and surrounds the inner portion (active region 9) of the first main surface 3. In other words, the outer well region 13 collectively surrounds the multiple gate structures 11.

[0162] The outer well region 13 may have an edge portion that connects the portion extending in the first direction X and the portion extending in the second direction Y in an arc shape (preferably a quadrant arc shape). The outer well region 13 has an inner edge portion on the side of the multiple gate structures 11 and an outer edge portion on the peripheral side of the first main surface 3. The inner edge portion of the outer well region 13 defines the boundary between the active region 9 and the outer periphery region 10.

[0163] The inner edge of the outer well region 13 is connected to the ends of the multiple gate structures 11 in a portion extending in the first direction X. The inner edge of the outer well region 13 faces the buried conductive layer 21 with the trench insulating film 20 interposed therebetween.

[0164] The inner edge of the outer well region 13 may be located closer to the inner side of the plurality of gate structures 11 than the ends of the plurality of gate structures 11. The inner edge of the outer well region 13 may have a portion located in a region between the plurality of gate structures 11 and connected to the body region 18. The outer edge of the outer well region 13 is formed spaced inward from the periphery of the chip 2 and extends approximately parallel to the inner edge of the outer well region 13.

[0165] The outer well region 13 may have a width greater than 0 μm and less than 300 μm. The width of the outer well region 13 may have a value belonging to at least one of the ranges greater than 0 μm and less than 25 μm, 25 μm to 50 μm, 50 μm to 75 μm, 75 μm to 100 μm, 100 μm to 125 μm, 125 μm to 150 μm, 150 μm to 175 μm, 175 μm to 200 μm, 200 μm to 225 μm, 225 μm to 250 μm, 250 μm to 275 μm, and 275 μm to 300 μm.

[0166] The outer well region 13 is formed at a distance from the bottom of the second semiconductor layer 7 toward the first main surface 3, and faces the first semiconductor layer 6 across a part of the second semiconductor layer 7. The outer well region 13 may be formed at a distance from the depth position of the intermediate portion of the second semiconductor layer 7 toward the first main surface 3, or may be located on the bottom side of the second semiconductor layer 7 (toward the second main surface 4) with respect to the depth position of the intermediate portion of the second semiconductor layer 7.

[0167] In this embodiment, the outer well region 13 is formed at an interval toward the first main surface 3 from the depth position of the bottom walls of the plurality of gate structures 11. The depth of the outer well region 13 may be greater or smaller than the depth of the body region 18.

[0168] The outer well region 13 may have a portion located on the bottom side of the second semiconductor layer 7 relative to the depth positions of the bottom walls of the plurality of gate structures 11. In this case, the outer well region 13 may be connected to either or both of the second layer 31 of the well region 12 and the first layer 30 of the well region 12.

[0169] The outer well region 13 forms a pn junction with the second semiconductor layer 7. The outer well region 13 spreads a depletion layer into the second semiconductor layer 7 when a reverse bias voltage is applied. The depletion layer in the outer well region 13 spreads in the horizontal and thickness directions and integrates with the depletion layers spreading from the body region 18 and the well region 12. The outer well region 13 expands the depletion layers spreading from the body region 18 and the well region 12 toward the peripheral edge of the first main surface 3, thereby reducing the electric field intensity (electric field concentration) in the peripheral portion (peripheral region 10) of the first main surface 3.

[0170] The semiconductor device 1 includes a p-type outer contact region 71 formed in a surface layer portion of the outer well region 13. The outer contact region 71 has a p-type impurity concentration higher than the p-type impurity concentration of the outer well region 13. The p-type impurity concentration of the outer contact region 71 is higher than the p-type impurity concentration of the body region 18.

[0171] The p-type impurity concentration of the outer contact region 71 may be approximately equal to the p-type impurity concentration of the first contact region 34. The p-type impurity concentration of the outer contact region 71 may be higher or lower than the p-type impurity concentration of the first contact region 34.

[0172] The outer contact region 71 is formed at a distance from the bottom of the outer well region 13 toward the first main surface 3, and faces the second semiconductor layer 7 across a part of the outer well region 13. The outer contact region 71 extends in a strip shape along the outer well region 13 (active region 9) in a plan view.

[0173] In this embodiment, the outer contact region 71 is formed in a polygonal ring shape (a square ring shape in this embodiment) having four sides parallel to the periphery of the chip 2 in a plan view, and surrounds the multiple gate structures 11 (active regions 9). The outer contact region 71 may have an edge portion that connects the portion extending in the first direction X and the portion extending in the second direction Y in an arc shape (preferably a quadrant arc shape).

[0174] The semiconductor device 1 may include a plurality of outer contact regions 71 arranged at intervals along the extension direction of the outer well region 13 so as to surround the plurality of gate structures 11. In this case, the plurality of outer contact regions 71 may each extend in a strip shape along the extension direction of the outer well region 13.

[0175] The outer contact region 71 has a width less than the width of the outer well region 13, and is formed in the outer well region 13. The outer contact region 71 is formed in the inner part of the outer well region 13 with a gap between both edges of the outer well region 13. The outer contact region 71 is biased toward the outer edge of the outer well region 13 relative to the central part of the outer well region 13. The outer contact region 71 may be formed in the central part of the outer well region 13.

[0176] 11 and 12 , the above-mentioned surface insulating film 15 extends from the peripheral region 10 to the active region 9 and covers the peripheries of the ends of the plurality of gate structures 11 in the active region 9. The surface insulating film 15 is connected to the trench insulating film 20 of the plurality of gate structures 11 and exposes the buried conductive layer 21 and the buried insulating layer 55. The surface insulating film 15 has a portion located in a region between the plurality of gate structures 11. The surface insulating film 15 is connected to the trench insulating film 20 at both the portion extending in the first direction X and the portion extending in the second direction Y of the ends of the plurality of gate structures 11.

[0177] The surface insulating film 15 directly covers the first main surface 3 around the plurality of gate structures 11. The surface insulating film 15 selectively covers the peripheral region of the first main surface 3 relative to the plurality of gate structures 11 in a film-like manner.

[0178] The surface insulating film 15 covers the outer well region 13 and the plurality of field regions 14. The surface insulating film 15 may have a portion extending in a strip shape in the first direction X and a portion extending in a strip shape in the second direction Y. The surface insulating film 15 may be formed in a polygonal ring shape (quadratic ring shape) surrounding the plurality of gate structures 11 (active regions 9) in plan view.

[0179] The surface insulating film 15 may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film.

[0180] The semiconductor device 1 includes a main surface insulating film 69 formed on the first main surface 3. The main surface insulating film 69 extends from the peripheral region 10 toward the active region 9 to the gate structure 11, and is formed integrally with the trench insulating film 20. The main surface insulating film 69 may be an extension portion that is extended from the gate structure 11 toward the peripheral region 10.

[0181] The main surface insulating film 69 covers the first main surface 3 and the surface insulating film 15 exposed between the gate structure 11 and the surface insulating film 15. The main surface insulating film 69 is continuous with the first to fourth side surfaces 5A to 5D. The main surface insulating film 69 may be formed at an interval inward from the first to fourth side surfaces 5A to 5D.

[0182] The main surface insulating film 69 may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film.

[0183] The aforementioned gate wiring 66 is disposed on the main surface insulating film 69 and the surface insulating film 15. The gate wiring 66 is selectively routed on the main surface insulating film 69 and the surface insulating film 15 at intervals from the periphery of the first main surface 3 toward the plurality of gate structures 11, and faces the outer well region 13 with the main surface insulating film 69 and the surface insulating film 15 interposed therebetween.

[0184] The gate wiring 66 has an inner edge portion on the inner side of the first main surface 3 and an outer edge portion on the peripheral side of the first main surface 3. The inner edge portion of the gate wiring 66 is disposed on the main surface insulating film 69 and faces the outer well region 13 with the main surface insulating film 69 in between. The inner edge portion of the gate wiring 66 covers the ends (both ends in this embodiment) of the multiple gate structures 11 and is mechanically and electrically connected to the multiple gate structures 11.

[0185] Specifically, the inner edge of the gate wiring 66 is mechanically and electrically connected to the plurality of buried conductive layers 21. In this embodiment, the inner edge of the gate wiring 66 is integrally formed with the plurality of buried conductive layers 21. In other words, the gate wiring 66 is formed as an extension of the plurality of buried conductive layers 21, and is drawn out from the trench 19 onto the main surface insulating film 69.

[0186] The outer edge of the gate wiring 66 is formed as an extension portion that is extended from above the main surface insulating film 69 onto the laminated structure of the main surface insulating film 69 and the surface insulating film 15, and is disposed on this laminated structure. The outer edge of the gate wiring 66 faces the outer well region 13 with the main surface insulating film 69 and the surface insulating film 15 sandwiched therebetween.

[0187] The outer edge of the gate wiring 66 is formed at a distance from the plurality of field regions 14 toward the plurality of gate structures 11. Specifically, the outer edge of the gate wiring 66 is formed at a distance from the outer edge of the outer well region 13 toward the plurality of gate structures 11. The outer edge of the gate wiring 66 is formed at a distance from the inner edge of the outer contact region 71 toward the plurality of gate structures 11.

[0188] The semiconductor device 1 may include a plurality of gate wirings 66. In this case, the plurality of gate wirings 66 may be arranged at least at both ends of the plurality of gate structures 11. One of the gate wirings 66 may have a portion extending in a strip shape in the first direction X and intersect (specifically, orthogonal to) one end of the plurality of gate structures 11. The other of the gate wirings 66 may have a portion extending in a strip shape in the first direction X and intersect (specifically, orthogonal to) the other end of the plurality of gate structures 11. Of course, the plurality of gate wirings 66 may have a portion extending in the second direction Y.

[0189] The interlayer film 65 described above covers the main surface insulating film 69 in a film form in the peripheral region 10. Specifically, the interlayer film 65 directly covers the main surface insulating film 69 in a film form, and faces the outer well region 13, the outer contact region 71, and the plurality of field regions 14 with the main surface insulating film 69 in between.

[0190] The interlayer film 65 covers the gate wiring 66 and the gate pad wiring 67. The interlayer film 65 covers the entire gate wiring 66 and the entire gate pad wiring 67. The interlayer film 65 has a portion facing the main surface insulating film 69 with the gate wiring 66 interposed therebetween, and a portion facing the main surface insulating film 69 with the gate wiring 66 interposed therebetween. The interlayer film 65 has a portion facing the outer well region 13 with the gate wiring 66 interposed therebetween, and a portion facing the outer well region 13 with the gate pad wiring 67 interposed therebetween.

[0191] The interlayer film 65 has an inner edge portion on the inward side of the first main surface 3 and an outer edge portion on the peripheral side of the first main surface 3. The inner edge portion of the interlayer film 65 is disposed in the active region 9. The inner edge portion of the interlayer film 65 is positioned on the inner side of the first main surface 3 with respect to the inner edge portion of the gate wiring 66 and the peripheral edge portion of the gate pad wiring 67, and covers the ends of the multiple gate structures 11.

[0192] The inner edge of the interlayer film 65 covers the buried conductive layer 21 at the ends of the multiple gate structures 11 and is connected to the buried insulating layer 55. In this embodiment, the interlayer film 65 is formed integrally with the buried insulating layer 55. The portion of the interlayer film 65 located within the trench 19 is formed as the buried insulating layer 55. The connection portion of the interlayer film 65 to the buried insulating layer 55 may be considered as part of the buried insulating layer 55 or may be considered as part of the interlayer film 65.

[0193] The inner edge of the interlayer film 65 has a portion located in a region between the plurality of gate structures 11. The inner edge of the interlayer film 65 covers either or both of the body region 18 and the outer well region 13 in the region between the plurality of gate structures 11, with the surface insulating film 15 sandwiched therebetween.

[0194] The outer edge of the interlayer film 65 is continuous with the first to fourth side surfaces 5A to 5D. The outer edge of the interlayer film 65 is formed at a distance inward from the first to fourth side surfaces 5A to 5D, and may expose either or both of the peripheral edge of the first main surface 3 and the surface insulating film 15.

[0195] The semiconductor device 1 includes one or more (one in this embodiment) source openings 68 formed in the interlayer film 65. The source opening 68 penetrates the interlayer film 65 in the inner portion of the active region 9, collectively exposing the plurality of gate structures 11 and the plurality of mesa portions 24. In this embodiment, the source opening 68 is formed in a polygonal shape having four sides parallel to the periphery of the first main surface 3 in a plan view (in this embodiment, a quadrilateral shape having a recessed portion recessed along the gate pad wiring 67).

[0196] The source openings 68 are formed at intervals from the ends (both ends in this embodiment) of the plurality of gate structures 11 toward the inner portion of the first main surface 3, and expose the inner portions of the plurality of gate structures 11 and the inner portions of the plurality of mesa portions 24. Specifically, the source openings 68 expose the trench insulating film 20 and the buried insulating layer 55 in the inner portions of the plurality of gate structures 11.

[0197] The above-described gate finger electrode 81 may be a part of the first main surface electrode 60. Like the source pad electrode 70, the gate finger electrode 81 has a laminated structure including a barrier layer 61 and a main body layer 62 laminated in this order from the first main surface 3 side.

[0198] The gate finger electrodes 81 extend into the plurality of gate openings 79 from above the interlayer film 65, and are mechanically and electrically connected to the gate wiring 66 within the plurality of gate openings 79. As a result, the gate potential applied to the gate pad electrode 80 is applied to the plurality of gate structures 11 via the gate finger electrodes 81. More specifically, the gate finger electrodes 81 are mechanically and electrically connected to the gate wiring 66 through the gate openings 79.

[0199] The plurality of gate openings 79 penetrate the interlayer film 65 and selectively expose the gate wiring 66. In this embodiment, the plurality of gate openings 79 extend in a strip shape following the direction in which the gate wiring 66 extends.

[0200] The plurality of gate openings 79 may be formed at intervals along the extension direction of the gate wiring 66. The plurality of gate openings 79 may be formed in a polygonal or circular shape in a plan view. For example, the plurality of gate structures 11 may be formed in a quadrangular or hexagonal shape in a plan view.

[0201] The plurality of gate openings 79 may have a portion extending in a band shape in the first direction X in a plan view and a portion extending in a band shape in the second direction Y. The plurality of gate openings 79 may have an edge portion connecting the portion extending in the first direction X and the portion extending in the second direction Y in a circular arc shape (preferably a quarter arc shape) in a plan view.

[0202] The gate finger electrode 81 has an inner edge portion on the inward side of the first main surface 3 and an outer edge portion on the peripheral side of the first main surface 3. The inner edge portion of the gate finger electrode 81 is formed at a distance from the ends of the multiple gate structures 11 toward the peripheral side of the first main surface 3. In other words, the gate finger electrode 81 does not face the multiple gate structures 11 in the stacking direction.

[0203] The inner edge of the gate finger electrode 81 is disposed on the gate wiring 66. The inner edge of the gate finger electrode 81 faces the peripheral edge of the source pad electrode 70 in the horizontal direction above the gate wiring 66. The inner edge of the gate finger electrode 81 is formed at a distance from the middle of the gate wiring 66 towards the peripheral edge of the first main surface 3.

[0204] The outer edge of the gate finger electrode 81 is drawn out from above the gate wiring 66 toward the peripheral edge of the first main surface 3, and is disposed on the interlayer film 65 in a region outside the gate wiring 66. In other words, the outer edge of the gate finger electrode 81 does not face the gate wiring 66 in the stacking direction. The outer edge of the gate finger electrode 81 is disposed at a distance from the innermost field region 14 toward the inside of the first main surface 3.

[0205] The outer edge of the gate finger electrode 81 is disposed at a distance from the outer edge of the outer well region 13 toward the inside of the first main surface 3, and faces the outer well region 13 across the surface insulating film 15 and the interlayer film 65. The outer edge of the gate finger electrode 81 is disposed on the peripheral side of the first main surface 3 relative to the outer edge of the outer well region 13, and may face the second semiconductor layer 7 in the stacking direction.

[0206] The above-described source finger electrode 85 may be a part of the first principal surface electrode 60. Like the source pad electrode 70, the source finger electrode 85 has a laminated structure including a barrier layer 61 and a main body layer 62 laminated in this order from the first principal surface 3 side.

[0207] The source finger electrodes 85 extend into the plurality of outer openings 83 from above the interlayer film 65, and are mechanically and electrically connected to the outer contact regions 71 within the plurality of outer openings 83. As a result, the gate potential applied to the source pad electrode 70 is applied to the plurality of gate structures 11 via the source finger electrodes 85.

[0208] The outer opening 83 is formed at a distance from the gate wiring 66 toward the peripheral edge of the first main surface 3. The outer opening 83 penetrates the surface insulating film 15 and the interlayer film 65 to expose the outer contact region 71.

[0209] The outer opening 83 has a width less than the width of the outer contact region 71, and exposes an inner portion of the outer contact region 71 at a distance from the inner and outer edges of the outer contact region 71. The outer opening 83 may expose the outer well region 13.

[0210] In this embodiment, the outer opening 83 extends in a strip shape following the extension direction of the outer contact region 71. In this embodiment, the outer opening 83 is formed in a polygonal ring shape (a square ring shape in this embodiment) having four sides parallel to the periphery of the chip 2 in a plan view, and surrounds the multiple gate structures 11 (active regions 9). The outer contact region 71 may have an edge portion that connects the portion extending in the first direction X and the portion extending in the second direction Y in an arc shape (preferably a quadrant arc shape).

[0211] The semiconductor device 1 may have a plurality of outer openings 83. In this case, the plurality of outer openings 83 may be formed at intervals following the extension direction of the outer contact region 71. Furthermore, the plurality of outer openings 83 may each extend in a strip shape following the extension direction of the outer contact region 71.

[0212] The source finger electrodes 85 have inner edges on the inward side of the first main surface 3 and outer edges on the peripheral side of the first main surface 3. The inner edges of the source finger electrodes 85 are spaced apart from the gate finger electrodes 81 on the peripheral side of the first main surface 3, and face the gate finger electrodes 81 in the horizontal direction.

[0213] The inner edge of the source finger electrode 85 is formed at a distance from the middle of the outer contact region 71 toward the inside of the first main surface 3. The inner edge of the source finger electrode 85 may be disposed on the outer well region 13 or on the outer contact region 71.

[0214] The outer edge of the source finger electrode 85 is drawn out from above the outer contact region 71 toward the peripheral edge of the first main surface 3, and is disposed on the interlayer film 65 in a region outside the outer contact region 71. The outer edge of the source finger electrode 85 is disposed at a distance from the innermost field region 14 toward the inside of the first main surface 3.

[0215] The outer edge of the source finger electrode 85 is disposed at a distance from the outer edge of the outer well region 13 toward the inside of the first main surface 3, and faces the outer well region 13 across the interlayer film 65. The outer edge of the source finger electrode 85 may be drawn out from the outer edge of the outer well region 13 toward the periphery of the first main surface 3, and faces the second semiconductor layer 7 across the interlayer film 65.

[0216] 13A to 13E are cross-sectional views showing a part of an example of a manufacturing method of the semiconductor device 1. Figures 13A to 13E are views corresponding to Figure 6.

[0217] 13A , a wafer for providing a first semiconductor layer 6 is prepared. Next, a step of forming a second semiconductor layer 7 is performed. The second semiconductor layer 7 is formed by epitaxial growth. Next, n-type impurities are introduced into the entire second semiconductor layer 7. As a result, a high concentration region 51 is formed throughout the surface portion of the second semiconductor layer 7. At the same time, a base region 50 isolated from the high concentration region 51 is formed.

[0218] Next, a process for forming the body region 18 is performed. In the process for forming the body region 18, p-type impurities are introduced into the entire region of the second semiconductor layer 7. As a result, the body region 18 is formed throughout the entire surface portion of the second semiconductor layer 7. Next, a process for forming the source region 32 is performed. In the process for forming the source region 32, n-type impurities are selectively introduced into the second semiconductor layer 7 (surface portion of the body region 18). As a result, the source region 32 is formed in the surface portion of the body region 18. At this time, the region where the first contact region 34 is to be formed is selectively covered with a mask (not shown) to prevent the introduction of the n-type impurities.

[0219] Next, a step of forming a plurality of trenches 19 is performed. Unnecessary portions of the second semiconductor layer 7 are removed by etching using a mask with a predetermined pattern. The etching method may be either wet etching or dry etching, or both. The etching method is preferably RIE (Reactive Ion Etching). As a result, a plurality of trenches 19 are formed at the upper end of the second semiconductor layer 7. At the same time, mesa portions 24 are formed between adjacent trenches 19.

[0220] Next, a step of forming a plurality of well regions 12 is performed. In the step of forming the well regions 12, p-type impurities are selectively introduced into the second semiconductor layer 7. As a result, the well regions 12 are formed at the bottom of each trench 19.

[0221] More specifically, a first step is performed in which p-type impurities are introduced at a relatively high first energy and a relatively low first dose, and a second step is performed in which p-type impurities are introduced at a second energy lower than the first energy and a second dose higher than the first dose. First, by performing the first step, a first layer 30 is formed at the bottom of the trench 19. Next, by performing the second step, a second layer 31 is formed in the surface layer portion of the first layer 30.

[0222] Next, the first contact region 34 and the second contact region 43 are formed in positions not shown in FIG. 13A . P-type impurities are introduced into the surface layer of the second semiconductor layer 7 by ion implantation using a mask having a predetermined pattern. As a result, the p-type impurities are introduced into the surface of the mesa portion 24 and the inner surface of the trench 19, forming the first contact region 34 and the second contact region 43. In this embodiment, oblique implantation is performed at a predetermined angle with respect to the first main surface 3. This allows ions to be implanted into the side surface 22 of the trench 19 in addition to the first main surface 3 and the bottom surface 23 of the trench 19.

[0223] Next, a step of forming the insulating film 76 is performed. The step of forming the insulating film 76 also serves as a step of forming the trench insulating film 20 and the main surface insulating film 69. The insulating film 76 may be formed by either or both of a CVD (Chemical Vapor Deposition) method and an oxidation treatment method. In this embodiment, the insulating film 76 is formed by the CVD method. The insulating film 76 is formed in a film shape on the wall surfaces of the plurality of trenches 19 and is formed over the entire first main surface 3.

[0224] 13B , a buried conductive layer 21 formation step is performed. In this step, if the buried conductive layer 21 is a metal silicide layer, a first base electrode film 90 is formed on the insulating film 76. In this embodiment, the first base electrode film 90 includes conductive polysilicon. The first base electrode film 90 backfills the plurality of trenches 19 and covers the first main surface 3 of the second semiconductor layer 7. The first base electrode film 90 may be formed by a CVD method.

[0225] 13C , unnecessary portions of the first base electrode film 90 are removed by etching. The unnecessary portions of the first base electrode film 90 are removed until the insulating film 76 is exposed and the upper surface of the first base electrode film 90 is positioned at the middle of the trench 19 in the depth direction. The etching method may be either wet etching or dry etching, or both. As a result, the plurality of first base electrode films 90 are respectively embedded in the plurality of trenches 19, and recesses 27 are formed in each trench 19.

[0226] Next, referring to FIG. 13D , a step of forming a second base electrode film 91 on the first base electrode film 90 is performed. The second base electrode film 91 includes a conductive material with a lower resistance than polysilicon. The second base electrode film 91 may be a metal layer. The second base electrode film 91 may include at least one selected from the group consisting of tungsten, nickel, molybdenum, platinum, titanium, and cobalt. The second base electrode film 91 partially backfills the recess 27 and completely covers the upper surface of the first base electrode film 90. The second base electrode film 91 may be formed by a sputtering method or a CVD method. Note that if the buried conductive layer 21 is a metal layer, the step of forming the first base electrode film 90 can be omitted, and the trench 19 can be backfilled with the second base electrode film 91 and a portion of the second base electrode film 91 can be etched away. This results in a buried conductive layer 21 made of a metal layer.

[0227] Next, if the buried conductive layer 21 is a metal silicide layer, a silicide process is performed as shown in FIG. 13E . An annealing process (e.g., RTA: Rapid Thermal Anneal) is performed to react the second base electrode film 91 (metal) with the silicon in the first base electrode film 90 (polysilicon). The silicide may progress downward at a substantially uniform rate from the boundary 89 between the first base electrode film 90 and the second base electrode film 91 toward the bottom surface 23 of the trench 19. By controlling the conditions of the annealing process, it is possible to silicide the entire stacked structure of the first base electrode film 90 and the second base electrode film 91. This allows the buried conductive layer 21 made of metal silicide to be formed.

[0228] Next, a buried insulating layer 55 formation step is performed. In this step, a base insulating film (not shown) is formed on the first main surface 3. In this embodiment, the base insulating film includes at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. The base insulating film backfills the recesses 27 of the multiple trenches 19, becomes integrated with the insulating film 76, and covers the first main surface 3 of the second semiconductor layer 7. The base insulating film may be formed by a CVD method. As a result, the insulating film 76 remaining between the buried conductive layer 21 and the inner surface of the trench 19 is formed as the trench insulating film 20.

[0229] Next, unnecessary portions of the base insulating film are removed by etching, thereby burying a plurality of buried insulating layers 55 in the plurality of trenches 19. Next, a step of forming a silicide layer 58 is performed. Specifically, a metal film for forming silicide (e.g., a nickel film, a titanium film, etc.) is formed on the first main surface 3. The metal film is deposited over the entire first main surface 3 by, for example, a sputtering method. Next, an annealing process (e.g., RTA: Rapid Thermal Anneal) is performed to cause the metal film to react with silicon in the second semiconductor layer 7, thereby forming a silicide layer 58 (metal silicide, see FIG. 6 ). Thereafter, the metal film is peeled off.

[0230] Next, processes for forming the interlayer film 65, the first main surface electrode 60, the resin layer 64, etc. are carried out. Next, a process for forming the drain pad electrode 87 is carried out. The drain pad electrode 87 is formed by depositing a metal film on the second main surface 4 by a sputtering method. Thereafter, the wafer is cut along a plurality of planned cutting lines. Through processes including those described above, a plurality of semiconductor devices 1 are manufactured from a single wafer.

[0231] [Operation and Effect of Semiconductor Device 1] The semiconductor device 1 is a device intended for miniaturization, for example. For example, miniaturization can be achieved by miniaturizing the trench width WT and trench pitch PT shown in FIGS. 8 and 9 . As the trench width WT is miniaturized, the volume of the buried conductive layer 21 buried in the trench 19 decreases. Therefore, the gate resistance of the buried conductive layer 21 tends to increase compared to a gate electrode buried in a wide trench 19.

[0232] Therefore, according to the semiconductor device 1, the buried conductive layer 21 is not provided as a single layer structure of polysilicon, but is made of a metal or metal silicide having a lower resistance than polysilicon. This makes it possible to reduce the resistance of the buried conductive layer 21 compared to the case of polysilicon alone. As a result, it is possible to reduce the gate resistance in devices aimed at miniaturization.

[0233] In this embodiment, the buried insulating layer 55 is filled in the recess 27 above the buried conductive layer 21, and a portion of the side surface 22 of the trench 19 remains exposed. This ensures a wide contact area between the source pad electrode 70 and the mesa portion 24. The volume of the buried conductive layer 21 is limited to ensure the recess 27, making it difficult to reduce the gate resistance by increasing the volume of the buried conductive layer 21. However, since a low-resistance buried conductive layer 21 is provided, it is possible to sufficiently reduce the gate resistance.

[0234] When the buried conductive layer 21 is polysilicon, depletion of the polysilicon occurs near the interface between the trench insulating film 20 and the polysilicon. The depletion layer generated by this depletion functions as a capacitive insulating film, so the thickness of the gate insulating film is effectively increased by the thickness of the depletion layer. Therefore, it is necessary to thin the trench insulating film 20 to avoid an increase in the gate threshold voltage. However, thinning the trench insulating film 20 can cause gate leakage current. Therefore, if the buried conductive layer 21 is a metal layer or a metal silicide layer, depletion can be suppressed, and the trench insulating film 20 can be maintained thick while reducing the gate resistance. As a result, gate leakage current can be suppressed.

[0235] 14 to 20, another embodiment of the semiconductor device 1 will be described. The following mainly describes parts that differ from the structure of the semiconductor device 1 shown in Figures 5 to 12, and a description of parts that are common to Figures 5 to 12 will be omitted.

[0236] (1) Embodiments of Fig. 14 and Fig. 15 Fig. 14 shows another embodiment of semiconductor device 1 and is a cross-sectional view corresponding to Fig. 6. Fig. 15 shows another embodiment of semiconductor device 1 and is a cross-sectional view corresponding to Fig. 11. Referring to Fig. 14 and Fig. 15, buried conductive layer 21 has a laminated structure including a first conductive layer 52 and a second conductive layer 53.

[0237] In this embodiment, the first conductive layer 52 is formed of a metal layer. The first conductive layer 52 is formed along the inner surface of the trench 19. The first conductive layer 52 is formed so that one surface (for example, the surface in contact with the inner surface of the trench 19) and the other surface on the opposite side thereof are formed along the inner surface of the trench 19.

[0238] The first conductive layer 52 extends integrally from the bottom surface 23 of the trench 19 along the side surface 22 toward the first main surface 3 and reaches the top surface 25 of the buried conductive layer 21. As a result, the first conductive layer 52 provides the outer periphery of the top surface 25 of the buried conductive layer 21.

[0239] The first conductive layer 52 partially covers the surface of the trench insulating film 20. The first conductive layer 52 forms a contact surface between the buried conductive layer 21 and the trench insulating film 20. An electrode recess 54 is defined inside the first conductive layer 52. The electrode recess 54 is a space surrounded by the first conductive layer 52 from both the lower and lateral directions.

[0240] The first conductive layer 52 is formed as a layer of approximately constant thickness along the bottom surface 23 and side surface 22 of the trench 19 so that an electrode recess 54 remains in the trench 19. "A substantially constant thickness along the bottom surface 23 and side surface 22 of the trench 19" is defined as the thickness of the trench 19 being approximately constant in the width direction (first direction X) and depth direction (third direction Z).

[0241] The thickness XT1 of the first conductive layer 52 in the first direction X may be, for example, 0.006 μm or more and 0.2 μm or less. The thickness XT1 may have a value belonging to at least one of the ranges of 0.01 μm or more and 0.05 μm or less, 0.05 μm or more and 0.1 μm or less, 0.1 μm or more and 0.15 μm or less, and 0.15 μm or more and 0.2 μm or less.

[0242] The thickness ZT1 of the first conductive layer 52 in the third direction Z may be, for example, 0.006 μm or more and 0.2 μm or less. The thickness ZT1 may have a value belonging to at least one of the ranges of 0.01 μm or more and 0.05 μm or less, 0.05 μm or more and 0.1 μm or less, 0.1 μm or more and 0.15 μm or less, and 0.15 μm or more and 0.2 μm or less.

[0243] In this embodiment, the second conductive layer 53 is formed of a metal silicide layer. The second conductive layer 53 is buried in the electrode recess 54. The second conductive layer 53 extends from the bottom of the electrode recess 54 toward the first main surface 3 and reaches the upper surface 25 of the buried conductive layer 21. The second conductive layer 53 is sandwiched between the first conductive layers 52 in the width direction of the trench 19, and provides the central portion of the upper surface 25 of the buried conductive layer 21.

[0244] The thickness ZT2 of the second conductive layer 53 in the third direction Z is greater than the thickness XT1 and the thickness ZT1 of the first conductive layer 52 and may be, for example, 0.2 μm to 0.7 μm. The thickness ZT2 may have a value belonging to at least one of the ranges of 0.2 μm to 0.3 μm, 0.3 μm to 0.4 μm, 0.4 μm to 0.5 μm, 0.5 μm to 0.6 μm, and 0.6 μm to 0.7 μm.

[0245] A first boundary 16 and a second boundary 17 are provided between the second conductive layer 53 and the first conductive layer 52. The first boundary 16 and the second boundary 17 extend in different directions. In this embodiment, the first boundary 16 extends in the horizontal direction (first direction X and second direction Y) along the first main surface 3, and the second boundary 17 extends in the vertical direction Z (third direction Z) perpendicular to the first main surface 3. The first boundary 16 and the second boundary 17 may be connected to each other and intersect as shown in FIG. 14 , or may be physically separated from each other.

[0246] In this embodiment, the first boundary portion 16 and the second boundary portion 17 are the "first boundary surface" and the "second boundary surface," which are the contact surfaces between the first conductive layer 52 and the second conductive layer 53. When the first conductive layer 52 and the second conductive layer 53 are not in contact with each other, the first boundary portion 16 and the second boundary portion 17 may represent the region between the first conductive layer 52 and the second conductive layer 53, or a layer or film sandwiched between the first conductive layer 52 and the second conductive layer 53.

[0247] The first boundary 16 and the second boundary 17 may be referred to as a "horizontal boundary" and a "vertical boundary", respectively, or as a "lateral boundary" and a "vertical boundary".

[0248] The constituent materials of the first conductive layer 52 and the second conductive layer 53 may be reversed. The first conductive layer 52 may be formed of a metal silicide layer, and the second conductive layer 53 may be formed of a metal layer.

[0249] 15 , in this embodiment, the gate wiring 66 is formed of a laminated structure including a first extension 72 of the first conductive layer 52 and a second extension 73 of the second conductive layer 53. The gate finger electrode 81 is mechanically and electrically connected to the second extension 73 through a gate opening 79.

[0250] The semiconductor device 1 of this embodiment can be manufactured, for example, according to the manufacturing steps shown in FIGS. 16A to 16E.

[0251] 16A, the same process as that shown in Fig. 13A is performed. After the body region 18, the source region 32, and the first contact region 34 are formed in this order in the second semiconductor layer 7, a plurality of trenches 19 are formed. Then, the well region 12 and the insulating film 76 are formed.

[0252] 16B , a step of forming a buried conductive layer 21 is performed. In this step, a first base electrode film 77 is formed on the insulating film 76. In this embodiment, the first base electrode film 77 may be a metal layer. The first base electrode film 77 is formed in a layer shape along the inner surfaces of the plurality of trenches 19. This defines electrode recesses 54 inside the trenches 19. The first base electrode film 77 may be formed by a sputtering method or a CVD method.

[0253] 16C , a step of forming a second base electrode film 78 on the first base electrode film 77 is performed. The second base electrode film 78 may be conductive polysilicon. The second base electrode film 78 backfills the electrode recess 74 and covers the first main surface 3 of the second semiconductor layer 7. The second base electrode film 78 may be formed by a CVD method.

[0254] Next, referring to FIG. 16D , a silicidation process is performed. An annealing process (e.g., RTA: Rapid Thermal Anneal) is performed to react the second base electrode film 78 (polysilicon) with the silicon in the first base electrode film 77 (metal). The silicidation may proceed both upward and laterally from the interface between the second base electrode film 78 and the first base electrode film 77 toward the second base electrode film 78 at a substantially uniform rate. By controlling the conditions of the annealing process, it is possible to silicidize the entire second base electrode film 78. This allows the second conductive layer 53 made of metal silicide to be formed.

[0255] 13E are then performed, with reference to Fig. 16E . After the body region 18, the source region 32, and the first contact region 34 are formed in the second semiconductor layer 7 in this order, a plurality of trenches 19 are formed. Then, the well region 12 and the insulating film 76 are formed. After the buried insulating layer 55, the silicide layer 58, the interlayer film 65, the first main surface electrode 60, the resin layer 64, the drain pad electrode 87, and the like are formed in this order, the wafer is cut along a plurality of planned cutting lines to manufacture a plurality of semiconductor devices 1.

[0256] The semiconductor device 1 of this embodiment can also achieve the same effects as the semiconductor device 1 shown in FIGS.

[0257] (2) Embodiment of Fig. 17 Fig. 17 shows another embodiment of the semiconductor device 1 and is a cross-sectional view corresponding to Fig. 6. Referring to Fig. 17, the first conductive layer 52 (metal layer) is a first buried conductive layer 52B, and the second conductive layer 53 (metal silicide layer) is a second buried conductive layer 53B.

[0258] The first buried conductive layer 52B is buried from the bottom surface 23 of the trench 19 to partway in the depth direction. The first buried conductive layer 52B backfills the entire space on the bottom surface 23 side of the intermediate portion in the depth direction of the trench 19. In this embodiment, the first buried conductive layer 52B straddles between the drift region 8 and the source region 32 in the depth direction of the trench 19 and faces the channel (body region 18) with the trench insulating film 20 interposed therebetween.

[0259] The second buried conductive layer 53B is buried in a portion of the trench 19 above the first buried conductive layer 52B. The second buried conductive layer 53B provides the entire upper surface 25 of the buried conductive layer 21. The boundary between the first buried conductive layer 52B and the second buried conductive layer 53B is only a boundary 89 extending in the horizontal direction (first direction X and second direction Y) along the first main surface 3. Therefore, in the embodiment of FIG. 17 , the buried conductive layer 21 has a two-layer structure divided into upper and lower layers by the boundary 89 extending in the horizontal direction, with the lower layer being the first buried conductive layer 52B and the upper layer being the second buried conductive layer 53B.

[0260] In this embodiment, the boundary portion 89 is a "boundary surface" that is a contact surface between the first buried conductive layer 52B and the second buried conductive layer 53B. When the first buried conductive layer 52B and the second buried conductive layer 53B are not in contact with each other, the boundary portion 89 may refer to a region between the first buried conductive layer 52B and the second buried conductive layer 53B, or a layer or film sandwiched between the first buried conductive layer 52B and the second buried conductive layer 53B. The boundary portion 89 may also be referred to as a "horizontal boundary portion" or a "lateral boundary portion." The boundary portion 89 is located closer to the first main surface 3 than the first boundary surface 39 between the first body portion 35 and the source region 32.

[0261] In the depth direction of the trench 19, the depth range occupied by the first buried conductive layer 52B with respect to the entire buried conductive layer 21 is, for example, 45% to 75% and preferably 60% to 70%. In the depth direction of the trench 19, the depth range occupied by the second buried conductive layer 53B with respect to the entire buried conductive layer 21 is, for example, 5% to 25% and preferably 10% to 20%.

[0262] 13B to 13D, a first base electrode film 90 made of a metal layer is buried, and a second base electrode film 91 made of polysilicon is buried. Then, in the silicidation step of Fig. 13E, the annealing conditions are controlled so that the entire second base electrode film 91 is silicided while the entire first base electrode film 90 is not silicided.

[0263] The semiconductor device 1 of this embodiment can also achieve the same effects as the semiconductor device 1 shown in FIGS.

[0264] (3) Configuration of FIG. 18 FIG. 18 shows another embodiment of the semiconductor device 1 and is a cross-sectional view corresponding to FIG. 6 . Referring to FIG. 18 , the first buried conductive layer 52B has an upper surface closer to the bottom surface 23 than the base interface 37 between the drift region 8 and the body region 18 in the depth direction of the trench 19. The second buried conductive layer 53B is buried in a portion above the first buried conductive layer 52B. The second buried conductive layer 53B straddles the drift region 8 and the source region 32 in the depth direction of the trench 19 and faces the channel (body region 18) with the trench insulating film 20 interposed therebetween. A boundary 89 between the first buried conductive layer 52B and the second buried conductive layer 53B is located closer to the bottom surface 23 than the base interface 37.

[0265] In the depth direction of the trench 19, the depth range occupied by the first buried conductive layer 52B with respect to the entire buried conductive layer 21 is, for example, 5% to 25% and preferably 10% to 20%. In the depth direction of the trench 19, the depth range occupied by the second buried conductive layer 53B with respect to the entire buried conductive layer 21 is, for example, 45% to 75% and preferably 60% to 70%.

[0266] The semiconductor device 1 of this embodiment can also achieve the same effects as the semiconductor device 1 shown in FIGS.

[0267] 19 shows another embodiment of the semiconductor device 1, and is a cross-sectional view corresponding to Fig. 11. Referring to Fig. 19, in the semiconductor device 1 of Figs. 14 and 15, the gate wiring 66 does not have the first extension 72, but is formed by the second extension 73 of the second conductive layer 53.

[0268] 20 shows another embodiment of the semiconductor device 1, and is a cross-sectional view corresponding to FIG. 11. Referring to FIG. 20, in the semiconductor device 1 of FIGS. 14 and 15, the gate wiring 66 does not have the second extension 73, and is formed by the first extension 72 of the first conductive layer 52.

[0269] Although embodiments of the present disclosure have been described, the present disclosure may be embodied in other forms.

[0270] For example, in the semiconductor device 1 of Figures 14 and 15, the gate wiring 66 may include two or more structures: a wiring formed by a stacked structure including a first extension 72 and a second extension 73 extending from a portion of the multiple gate structures 11, a wiring formed only by the first extension 72 extending from another portion of the multiple gate structures 11, and a wiring formed only by the second extension 73 extending from another portion of the multiple gate structures 11.

[0271] For example, in each of the above-described embodiments, the first semiconductor layer 6 and the second semiconductor layer 7 each contain a SiC single crystal. However, at least one or all of the first semiconductor layer 6 and the second semiconductor layer 7 may contain a single crystal of a wide bandgap semiconductor other than a SiC single crystal.

[0272] The first semiconductor layer 6 and the second semiconductor layer 7 may be made of the same type of single crystal or different types of single crystal, and at least one of the first semiconductor layer 6 and the second semiconductor layer 7 or all of them may be made of silicon (Si).

[0273] Below, examples of features extracted from this specification and the drawings are shown. Below, alphanumeric characters in parentheses represent corresponding components in the above-mentioned embodiments, but are not intended to limit the scope of each clause to the embodiments. The "semiconductor device" in the following items may be replaced with "SiC semiconductor device," "wide bandgap semiconductor device," "semiconductor switching device," "semiconductor rectifier device," "MISFET device," "IGBT device," "diode device," etc., as necessary.

[0274] [Appendix 1-1] A semiconductor device (1) comprising: a chip (2) having a main surface (3); a trench electrode type gate structure (11) formed on the main surface (3), the gate structure (11) including a trench (19) formed in the main surface (3), a trench insulating film (20) covering the inner surface of the trench (19), and a buried conductive layer (21) buried in the trench (19) via the trench insulating film (20); a recess (27) defined by an upper surface (25) of the buried conductive layer (21) and a side surface (22) of the trench (19); and a buried insulating layer (55) buried in the recess (27), wherein the buried conductive layer (21) is formed of a conductive material having a lower resistance than polysilicon.

[0275] [Appendix 1-2] The semiconductor device (1) according to appendix 1-1, wherein the buried conductive layer (21) is formed of a single layer of a metal layer.

[0276] [Appendix 1-3] The semiconductor device (1) according to appendix 1-2, wherein the metal layer is formed of at least one selected from the group consisting of tungsten, nickel, molybdenum, platinum, titanium, and cobalt.

[0277] [Appendix 1-4] The semiconductor device (1) according to appendix 1-1, wherein the buried conductive layer (21) is formed of a single layer of a metal silicide layer.

[0278] [Appendix 1-5] The semiconductor device (1) according to appendix 1-4, wherein the metal silicide layer is formed of at least one selected from the group consisting of tungsten silicide, nickel silicide, molybdenum silicide, platinum silicide, titanium silicide, and cobalt silicide.

[0279] [Appendix 1-6] The semiconductor device (1) according to appendix 1-1, wherein the buried conductive layer (21) has a laminated structure including a first conductive layer (52) formed of a metal layer and a second conductive layer (53) formed of a metal silicide layer.

[0280] [Appendix 1-7] The semiconductor device (1) according to appendix 1-6, wherein the first conductive layer (52) is formed along the inner surface of the trench (19) and defines an electrode recess (54) within the trench (19), and the second conductive layer (53) is buried in the electrode recess (54).

[0281] [Appendix 1-8] The semiconductor device (1) according to Appendix 1-6, wherein the second conductive layer (53) is formed along the inner surface of the trench (19) and defines an electrode recess (54) within the trench (19), and the first conductive layer (52) is buried in the electrode recess (54).

[0282] [Appendix 1-9] The semiconductor device (1) according to appendix 1-6, wherein the first conductive layer (52) is a first buried conductive layer (52B) buried partway in the depth direction of the trench (19), and the second conductive layer (53) is a second buried conductive layer (53B) buried in a portion of the trench (19) above the first buried conductive layer (52B).

[0283] [Appendix 1-10] The semiconductor device (1) according to appendix 1-6, wherein the second conductive layer (53) is a second buried conductive layer (53B) buried partway in the depth direction of the trench (19), and the first conductive layer (52) is a first buried conductive layer (52B) buried in a portion of the trench (19) above the first buried conductive layer (52B).

[0284] [Supplementary Note 1-11] The semiconductor device (1) according to any one of Supplementary Note 1-1 to Supplementary Note 1-10, wherein the trench insulating film (20) is made of a high dielectric material.

[0285] [Supplementary Note 1-12] The high dielectric material is HfSiO, HfSiON, HfO ２ , HfAl ｘ O ｙ , AlSiO, Al ２ O ３ and ZrO ２ The semiconductor device (1) according to appendix 1-11, wherein the semiconductor device (1) is at least one selected from the group consisting of:

[0286] [Supplementary Note 1-13] The semiconductor device further includes a first impurity region (8) of a first conductivity type formed in a surface layer portion of the main surface (3), a second impurity region (18) of a second conductivity type formed in a surface layer portion of the first impurity region (8), and a third impurity region (32) of the first conductivity type formed in a surface layer portion of the second impurity region (18), wherein the buried insulating layer (55) has an upper surface (57) located closer to the bottom in the depth direction of the trench (19) than the main surface (3), and a second recess (27) is defined by the upper surface (57) of the buried insulating layer (55) and a side surface (22) of the trench (19), and the third impurity region (32) is exposed from the second recess (27), The semiconductor device (1) according to any one of Appendices 1-1 to 1-12, further comprising a main surface electrode (60) covering the buried insulating layer (55) and connected to the third impurity region (32) within the second recess (27).

[0287] [Appendix 1-14] The semiconductor device (1) according to any one of Appendices 1-1 to 1-13, further comprising a gate wiring (66) arranged around an end of the gate structure (11) on the main surface (3) and electrically connected to the gate structure (11), wherein the gate wiring (66) is formed by an extension of the buried conductive layer (21).

[0288] [Appendix 1-15] The semiconductor device (1) according to any one of Appendices 1-1 to 1-14, wherein the chip (2) includes a SiC chip (2).

[0289] 1: Semiconductor device 2: Chip 3: First main surface 4: Second main surface 5A: First side surface 5B: Second side surface 5C: Third side surface 5D: Fourth side surface 6: First semiconductor layer 7: Second semiconductor layer 8: Drift region 9: Active region 10: Peripheral region 11: Gate structure 12: Well region 13: Outer well region 14: Field region 15: Surface insulating film 16: First boundary portion 17: Second boundary portion 18: Body region 19: Trench 20: Trench insulating film 21: Buried conductive layer 22: Side surface 23: Bottom surface 24: Mesa portion 25: Top surface 26: Step 27: Recess 28: Protrusion 29: Side surface 30: First layer 31 : Second layer 32 : Source region 33 : Channel section 34 : First contact region 35 : First body portion 36 : Second body portion 37 : Base boundary surface 38 : Body protrusion 39 : First boundary surface 40 : First step 41 : Second boundary surface 42 : Second step 43 : Second contact region 44 : Integrated impurity region 45 : Corner portion 46 : First relaxation portion 47 : Second relaxation portion 48 : First boundary surface 49 : Second boundary surface 50 : Base region 51 : High concentration region 52 : First conductive layer 52B : First buried conductive layer 53 : Second conductive layer 53B : Second buried conductive layer 54 : Electrode recess 55 : Buried insulating layer 56 : Upper edge 57 : Upper surface 58: Silicide layer 59: Non-silicide portion 60: First main surface electrode 61: Barrier layer 62: Main body layer 63: Second recess 64: Resin layer 65: Interlayer film 66: Gate wiring 67: Gate pad wiring 68: Source opening 69: Main surface insulating film 70: Source pad electrode 70a: First pad portion 70b: Second pad portion 70c: Third pad portion 71: Outer contact region 72: First extension portion 73: Second extension portion 74: Electrode recess 76: Insulating film77: First base electrode film 78: Second base electrode film 79: Gate opening 80: Gate pad electrode 81: Gate finger electrode 82: First slit portion 83: Outer opening 85: Source finger electrode 86: Second slit portion 87: Drain pad electrode 89: Boundary portion 90: First base electrode film 91: Second base electrode film

Claims

1. A semiconductor device comprising: a chip having a main surface; a trench electrode type gate structure formed on the main surface, the gate structure including a trench formed in the main surface, a trench insulating film covering the inner surface of the trench, and a buried conductive layer buried in the trench via the trench insulating film; a recess defined by an upper surface of the buried conductive layer and a side surface of the trench; and a buried insulating layer buried in the recess, wherein the buried conductive layer is formed of a conductive material having a lower resistance than polysilicon.

2. The semiconductor device according to claim 1, wherein said buried conductive layer is formed of a single layer of metal.

3. The semiconductor device according to claim 2, wherein said metal layer is formed of at least one selected from the group consisting of tungsten, nickel, molybdenum, platinum, titanium and cobalt.

4. The semiconductor device according to claim 1, wherein said buried conductive layer is formed of a single layer of metal silicide.

5. The semiconductor device according to claim 4, wherein said metal silicide layer is formed of at least one material selected from the group consisting of tungsten silicide, nickel silicide, molybdenum silicide, platinum silicide, titanium silicide and cobalt silicide.

6. The semiconductor device according to claim 1, wherein said buried conductive layer has a laminated structure including a first conductive layer formed of a metal layer and a second conductive layer formed of a metal silicide layer.

7. The semiconductor device according to claim 6, wherein the first conductive layer is formed along the inner surface of the trench to define an electrode recess within the trench, and the second conductive layer is buried in the electrode recess.

8. The semiconductor device according to claim 6, wherein the second conductive layer is formed along the inner surface of the trench to define an electrode recess within the trench, and the first conductive layer is buried in the electrode recess.

9. The semiconductor device according to claim 6, wherein the first conductive layer is a first buried conductive layer buried partway in the depth direction of the trench, and the second conductive layer is a second buried conductive layer buried in a portion of the trench above the first buried conductive layer.

10. The semiconductor device described in claim 6, wherein the second conductive layer is a second buried conductive layer buried partway through the depth direction of the trench, and the first conductive layer is a first buried conductive layer buried in a portion of the trench above the first buried conductive layer.

11. The semiconductor device according to any one of claims 1 to 10, wherein the trench insulating film is made of a high dielectric material.

12. The high dielectric material is HfSiO, HfSiON, HfO ２ , HfAl ｘ O ｙ , AlSiO, Al ２ O ３ and ZrO ２ The semiconductor device according to claim 11, wherein the semiconductor device is at least one selected from the group consisting of:

13. The semiconductor device according to any one of claims 1 to 12, further comprising: a first impurity region of a first conductivity type formed in a surface layer portion of said main surface; a second impurity region of a second conductivity type formed in a surface layer portion of said first impurity region; and a third impurity region of the first conductivity type formed in a surface layer portion of said second impurity region; said buried insulating layer having an upper surface that is closer to a bottom in a depth direction of said trench than said main surface, a second recess being defined by the upper surface of said buried insulating layer and a side surface of said trench, said third impurity region being exposed from said second recess, and a main surface electrode covering said buried insulating layer and connected to said third impurity region within said second recess.

14. The semiconductor device according to any one of claims 1 to 13, further comprising a gate wiring arranged on said main surface around an edge of said gate structure and electrically connected to said gate structure, said gate wiring being formed by an extension of said buried conductive layer.

15. The semiconductor device according to any one of claims 1 to 14, wherein the chip includes a SiC chip.

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