Photodetection element and electronic apparatus

Abstract

Provided is a photodetection element with which saturation performance and image quality can be improved while achieving expansion of dynamic range. The photodetection element comprises a pixel array unit, a control unit, and a pixel signal reading unit. The pixel array unit is composed of a plurality of pixels. The pixels each have a photoelectric conversion unit and a floating diffusion region for temporarily storing charge. The control unit controls the pixel array unit. The pixel signal reading unit reads a pixel signal based on the charge from the floating diffusion region of a pixel under the control of the control unit. Each of the plurality of pixels includes a first charge storage capacitor and second charge storage capacitor, a first switching switch for electrically coupling the floating diffusion region to the first charge storage capacitor, and a second switching switch for electrically coupling the floating diffusion region to the second charge storage capacitor. The control unit controls the first switching switch and the second switching switch so as to switch between the first charge storage capacitor and the second charge storage capacitor.

Description

Photodetector element and electronic device

[0001] The technology according to the present disclosure (the present technology) relates to a photodetector element and an electronic device including the photodetector element.

[0002] In order for a photodetector element to obtain good image quality in an environment with large differences in brightness (differences in brightness), it is required to have a wide dynamic range. The solid-state imaging device disclosed in Patent Document 1 below achieves high saturation performance and a high S / N (Signal to Noise Ratio) and a wide dynamic range by accumulating charge overflowing from a photoelectric conversion element (photodiode) in a floating diffusion region (FD section). Furthermore, the solid-state imaging device can achieve an even wider dynamic range by incorporating a high-density capacitance element using a high-k material in the FD section.

[0003] Japanese Patent Application Laid-Open No. 2006-245522

[0004] Incidentally, when a high-density capacitance element made of high-k material is used in the FD section, dielectric absorption occurs. Dielectric absorption is a phenomenon in which it takes time for a capacitance element to discharge after being charged for a long time. This phenomenon is caused by the time it takes for the polarization of molecules in the insulating film to dissipate.

[0005] Dielectric absorption causes image degradation, particularly in the case of a moving bright light source, resulting in the appearance of an afterimage. Furthermore, there has been a strong demand for further improvements in saturation performance. However, if the number of saturation electrons is further increased to expand the dynamic range, the effects of dielectric absorption become more apparent.

[0006] The present disclosure has been made in consideration of the above circumstances, and aims to provide a photodetector element and electronic device that enable improved saturation performance and improved image quality while realizing an expanded dynamic range.

[0007] One aspect of the present disclosure is a photodetector element comprising: a pixel array unit consisting of a plurality of pixels each having a photoelectric conversion unit that performs photoelectric conversion in response to received light and a floating diffusion region that temporarily stores charge photoelectrically converted by the photoelectric conversion unit; a control unit that controls the pixel array unit; and a pixel signal readout unit that reads out pixel signals based on the charge from the floating diffusion region of the pixel under the control of the control unit, wherein each of the plurality of pixels comprises a first charge storage capacitance unit, a second charge storage capacitance unit, and a switching unit that selectively connects the first charge storage capacitance unit and the second charge storage capacitance unit to the floating diffusion region under the control of the control unit.

[0008] Another aspect of the present disclosure is an electronic device comprising: a pixel array unit consisting of a plurality of pixels each having a photoelectric conversion unit that performs photoelectric conversion in response to received light and a floating diffusion region that temporarily accumulates charge photoelectrically converted by the photoelectric conversion unit; a control unit that controls the pixel array unit; and a pixel signal readout unit that reads out pixel signals based on the charge from the floating diffusion region of the pixel under the control of the control unit, wherein each of the plurality of pixels comprises a photodetector element having a first charge storage capacitance unit, a second charge storage capacitance unit, and a switching unit that selectively connects the first charge storage capacitance unit and the second charge storage capacitance unit to the floating diffusion region under the control of the control unit.

[0009] 1 is a block diagram showing an example of a schematic configuration of a photodetector according to a first embodiment of the present disclosure. FIG. 1 is an example of a circuit configuration diagram of a unit pixel according to the first embodiment of the present disclosure. FIG. 2 is a diagram for explaining an example of a planar layout of each element constituting a unit pixel of the photodetector according to the first embodiment of the present disclosure. FIG. 3 is a partial vertical cross-sectional view showing an example of a semiconductor structure in a schematic cross section taken along dashed dotted line A-B of the unit pixel shown in FIG. 3. FIG. 4 is a schematic potential diagram showing an example of an operation of a pixel in a photodetector according to a comparative example of the first embodiment of the present disclosure. FIG. 5 is a diagram showing an example of a captured image in a comparative example in which dielectric absorption charge is recognized as an afterimage. FIG. 6 is a timing chart showing an example of an operation of a unit pixel of the photodetector according to the first embodiment of the present disclosure. FIG. 7 is an example of a circuit configuration diagram of a unit pixel of a photodetector according to a second embodiment of the present disclosure. FIG. 8 is a diagram for explaining an example of a planar layout of each element constituting a unit pixel of the photodetector according to the second embodiment of the present disclosure. FIG. 9 is a partial vertical cross-sectional view showing an example of a semiconductor structure in a schematic cross section taken along dashed dotted line A-B of the unit pixel shown in FIG. 10. FIG. 11 is a partial vertical cross-sectional view showing an example of a semiconductor structure of a unit pixel of a photodetector according to a third embodiment of the present disclosure. 11B is a partial cross-sectional view of a first charge storage capacitor taken along dashed dotted line E-F shown in FIG. 11A. FIG. 11C is an example of a circuit configuration diagram of a unit pixel of a photodetector according to a fourth embodiment of the present disclosure. FIG. 11D is an example of a circuit configuration diagram of a unit pixel of a photodetector according to a fifth embodiment of the present disclosure. FIG. 11E is an example of a circuit configuration diagram of a unit pixel of a photodetector according to a sixth embodiment of the present disclosure. FIG. 11F is an example of a circuit configuration diagram of a unit pixel of a photodetector according to a seventh embodiment of the present disclosure. FIG. 11G is an example of a circuit configuration diagram of a unit pixel of a photodetector according to an eighth embodiment of the present disclosure. FIG. 11H is an example of a circuit configuration diagram of a unit pixel of a photodetector according to a ninth embodiment of the present disclosure. FIG. 11I is an example of a circuit configuration diagram of a unit pixel of a photodetector according to an eleventh embodiment of the present disclosure. FIG. 11I is a timing chart showing an example of the operation of a unit pixel in a photodetector according to a twelfth embodiment of the present disclosure. FIG. 11I is an example of a circuit configuration diagram of a unit pixel of a photodetector according to a thirteenth embodiment of the present disclosure. FIG. 11I is an example of a circuit configuration diagram of a unit pixel of a photodetector according to a fourteenth embodiment of the present disclosure.24 is a diagram for explaining an example of a planar layout of each element constituting a unit pixel of a photodetector according to a fourteenth embodiment of the present disclosure. 25 is a partial longitudinal cross-sectional view showing an example of a semiconductor structure in a schematic cross section taken along dashed dotted line A-B of the unit pixel shown in FIG. 23. 26 is a partial longitudinal cross-sectional view showing an example of a semiconductor structure in a schematic cross section of a unit pixel of a photodetector according to a modified example of the fourteenth embodiment of the present disclosure. 27 is an example of a circuit configuration diagram of a unit pixel of a photodetector according to a fifteenth embodiment of the present disclosure. 28 is a timing chart (part 1) showing an example of an operation of a unit pixel in a photodetector according to a sixteenth embodiment of the present disclosure. 29 is a timing chart (part 2) showing an example of an operation of a unit pixel in a photodetector according to a seventeenth embodiment of the present disclosure. 29 is a timing chart (part 1) showing an example of an operation of a unit pixel in a photodetector according to a seventeenth embodiment of the present disclosure. 30 is a block diagram showing an example of the configuration of an imaging device as an electronic device to which the present technology is applied. 31 is a block diagram showing an example of the schematic configuration of a vehicle control system which is an example of a mobile body control system to which the technology according to the present disclosure can be applied. 32 is a diagram showing an example of an installation position of the imaging unit shown in FIG. 30.

[0010] Hereinafter, embodiments of the present disclosure will be described with reference to the drawings. In the drawings referred to in the following description, identical or similar parts will be designated by identical or similar reference numerals, and redundant description will be omitted. However, it should be noted that the drawings are schematic, and the relationship between thickness and planar dimensions, the thickness ratio of each device and each component, etc., may differ from the actual ones. Therefore, specific thicknesses and dimensions should be determined with reference to the following description. Furthermore, it goes without saying that the drawings may include parts with different dimensional relationships and ratios.

[0011] In this specification, the term "first conductivity type" refers to either p-type or n-type, and the term "second conductivity type" refers to either p-type or n-type, which is different from the "first conductivity type." Furthermore, the definitions of directions such as up and down in the following description are merely for the sake of convenience and do not limit the technical concept of the present disclosure. For example, if an object is rotated 90 degrees and observed, up and down are read as being converted to left and right, and if an object is rotated 180 degrees and observed, up and down are read as being reversed.

[0012] The effects described in this specification are merely examples and are not limiting, and other effects may also be present.

[0013] <First Embodiment> (Overall Configuration of Photodetector) Fig. 1 is a block diagram showing an example of a schematic configuration of a photodetector according to a first embodiment of the present disclosure. The photodetector 1 (an example of a photodetector element) is a semiconductor device configured as, for example, a CMOS image sensor, which uses photoelectric conversion elements such as photodiodes constituting each pixel to convert the amount of charge corresponding to the intensity of light imaged on the pixel into an electrical signal and outputs this as image data. The photodetector 1 can be configured as an integrated system-on-chip (SoC) such as a CMOS LSI, for example. However, for example, some of the components shown below may be configured as separate LSIs.

[0014] As shown in the figure, the photodetection device 1 is configured to include components such as a pixel array unit 11, a vertical drive unit 12, a column processing unit 13 (an example of a pixel signal readout unit), a horizontal drive unit 14, a system control unit 15 (an example of a control unit), a signal processing unit 16, and a data storage unit 17.

[0015] The pixel array unit 11 includes a group of photoelectric conversion elements such as photodiodes that constitute unit pixels 110 arrayed in the horizontal direction (row direction) and the vertical direction (column direction). The pixel array unit 11 converts the amount of charge corresponding to the intensity of incident light focused on each unit pixel 110 into an electrical signal and outputs it as a pixel signal. The pixel array unit 11 may include, for example, effective pixels arranged in an area capable of receiving actual light and dummy pixels arranged outside this area and shielded by metal or the like. Note that optical elements such as a micro-on-chip lens that focuses incident light and a color filter (not shown) are formed on each unit pixel 110 of the pixel array unit 11.

[0016] The vertical drive unit 12 is configured to include a shift register, an address decoder, etc. The vertical drive unit 12 supplies drive signals, etc. to each unit pixel 110 via a plurality of pixel drive lines 18, thereby driving each unit pixel 110 of the pixel array unit 11, for example, simultaneously or row by row.

[0017] The column processing unit 13 reads out pixel signals from each pixel for each pixel column of the pixel array unit 11 via vertical signal lines (VSL) 19, and performs noise removal processing, correlated double sampling (CDS) processing, A / D (Analog-to-Digital) conversion processing, etc. The pixel signals processed by the column processing unit 13 are output to the signal processing unit 16.

[0018] The horizontal driving unit 14 is configured to include a shift register, an address decoder, etc. The horizontal driving unit 14 sequentially selects the unit pixels 110 corresponding to the pixel columns of the column processing unit 13. By the selective scanning by this horizontal driving unit 14, pixel signals processed for each unit pixel 110 in the column processing unit 13 are output sequentially to the signal processing unit 16.

[0019] The system control unit 15 includes a timing generator that generates various timing signals, etc. The system control unit 15 controls the driving of the vertical driving unit 12, the column processing unit 13, and the horizontal driving unit 14 based on timing signals generated by, for example, a timing generator (not shown).

[0020] The signal processing unit 16 performs signal processing such as arithmetic processing on the pixel signals supplied from the column processing unit 13, while temporarily storing data in the data storage unit 17 as necessary, and outputs an image signal based on each pixel signal. The signal processing unit 16 also performs signal processing in accordance with the flags output from the column processing unit 13.

[0021] It should be noted that the photodetector 1 to which the present technology is applied is not limited to the configuration described above. For example, the photodetector 1 may be configured such that the data storage unit 17 is disposed after the column processing unit 13, and pixel signals output from the column processing unit 13 are supplied to the signal processing unit 16 via the data storage unit 17. Alternatively, the photodetector 1 may be configured such that the column processing unit 13, the data storage unit 17, and the signal processing unit 16 are cascade-connected to process the pixel signals in parallel.

[0022] 2 is an example of a circuit configuration diagram of a unit pixel 110. That is, the diagram shows an example of the circuit configuration of any one unit pixel 110 among the plurality of unit pixels 110 that constitute the pixel array section 11 of the photodetector 1 shown in FIG.

[0023] The unit pixel 110 of this example includes a first photoelectric conversion unit 1101, a first transfer transistor 1102, a first floating diffusion region (FD1) 1103, an amplification transistor (AMP) 1104, a selection transistor 1105, a conversion efficiency switching transistor 1106 (an example of an additional switching transistor), a second floating diffusion region (FD2) 1107, a reset transistor 1108, a third floating diffusion region (FD3A) 1109 (hereinafter referred to as a first charge storage capacitance unit 1109), a third floating diffusion region (FD3B) 1110 (hereinafter referred to as a second charge storage capacitance unit 1110), a first changeover switch 1111, and a second changeover switch 1112. In this example, each transistor is an NMOS transistor, but is not limited to this.

[0024] 1, a plurality of drive lines for supplying various drive signals TG, FDG, RST, SEL, etc. to the unit pixels 110 are wired for each pixel row. These drive signals are, for example, pulse signals that turn on an NMOS transistor at a high potential level and turn off an NMOS transistor at a low potential level.

[0025] The first photoelectric conversion unit 1101 is, for example, a PN junction photodiode, which generates and accumulates charges according to the amount of light received. The first transfer transistor 1102 is an NMOS transistor provided between the first photoelectric conversion unit 1101 and the first floating diffusion region 1103. A drive signal TG is applied to the gate electrode of the first transfer transistor 1102. That is, when the drive signal TG becomes a high potential level, the first transfer transistor 1102 becomes conductive, and the charges accumulated in the first photoelectric conversion unit 1101 are transferred to the first floating diffusion region 1103 via the first transfer transistor 1102.

[0026] The conversion efficiency switching transistor 1106 is an NMOS transistor provided between the first floating diffusion region 1103 and the second floating diffusion region 1107. A drive signal FDG is applied to a gate electrode of the conversion efficiency switching transistor 1106. When the drive signal FDG becomes a high potential level, the conversion efficiency switching transistor 1106 becomes conductive, and the potential of the first floating diffusion region 1103 and the potential of the second floating diffusion region 1107 are coupled. The conversion efficiency switching transistor 1106 controls charge retention by the first floating diffusion region 1103 and the second floating diffusion region 1107, and adjusts the voltage multiplication factor according to the potential amplified by the amplification transistor 1104.

[0027] In the first embodiment of the present disclosure, a first changeover switch 1111 and a second changeover switch 1112 are connected in parallel to the second floating diffusion region 1107. The first changeover switch 1111 is an NMOS transistor provided between the second floating diffusion region 1107 and the first charge storage capacitor 1109. A drive signal SWA is applied to the gate electrode of the first changeover switch 1111. When the drive signal SWA becomes a high potential level, the first changeover switch 1111 becomes conductive, and the potential of the first charge storage capacitor 1109 and the potential of the second floating diffusion region 1107 are coupled.

[0028] The second changeover switch 1112 is an NMOS transistor provided between the second floating diffusion region 1107 and the second charge storage capacitor 1110. A drive signal SWB is applied to the gate electrode of the second changeover switch 1112. When the drive signal SWB becomes a high potential level, the second changeover switch 1112 becomes conductive, and the potential of the second charge storage capacitor 1110 and the potential of the second floating diffusion region 1107 are coupled.

[0029] The reset transistor 1108 is an NMOS transistor provided between a connection line 1113 of a power supply voltage VDD (an example of a first power supply connection portion) and the second floating diffusion region 1107. A drive signal RST is applied to the gate electrode of the reset transistor 1108. When the drive signal RST becomes a high potential level, the reset transistor 1108 becomes conductive. As a result, depending on the potential level of the drive signal FDG, the potential of the region where the first floating diffusion region 1103 and the second floating diffusion region 1107 are coupled, the potential of the region where the first charge storage capacitance section 1109 and the second floating diffusion region 1107 are coupled, the potential of the region where the second charge storage capacitance section 1110 and the second floating diffusion region 1107 are coupled, the potential of the region where the first charge storage capacitance section 1109, the first floating diffusion region 1103, and the second floating diffusion region 1107 are coupled, or the potential of the region where the second charge storage capacitance section 1110, the first floating diffusion region 1103, and the second floating diffusion region 1107 are coupled is reset to the level of the power supply voltage VDD.

[0030] The first floating diffusion region 1103 is a diffusion region capable of holding a predetermined amount of charge. The first floating diffusion region 1103 is connected to the drain electrode of the first transfer transistor 1102, the drain electrode of the conversion efficiency switching transistor 1106, and the gate electrode of the amplification transistor 1104. The charge accumulated in the first floating diffusion region 1103 is converted into a voltage signal and read out.

[0031] The second floating diffusion region 1107 is also a diffusion region capable of holding a predetermined amount of charge. In the first embodiment of the present disclosure, the charge accumulated in the second floating diffusion region 1107 is either an overflow charge among the charge photoelectrically converted by the first photoelectric conversion unit 1101 or a charge that flows directly from the first photoelectric conversion unit 1101. The charge accumulated in the second floating diffusion region 1107 is converted into a voltage signal and read out.

[0032] The first charge storage capacitor 1109 is made of a metal insulator metal (MIM) capacitor. One electrode of the first charge storage capacitor 1109 is connected to a connection line 1114 (an example of a second power supply connection section) for a power supply voltage FCVDD, and the other electrode is connected to the drain electrode of the first changeover switch 1111. The first charge storage capacitor 1109 stores overflow charges among the charges photoelectrically converted by the first photoelectric conversion section 1101.

[0033] The second charge storage capacitor 1110 is made of an MIM capacitor. One electrode of the second charge storage capacitor 1110 is connected to a connection line 1114 of a power supply voltage FCVDD, and the other electrode is connected to a drain electrode of a second changeover switch 1112. The second charge storage capacitor 1110 stores overflow charges among the charges photoelectrically converted by the first photoelectric conversion unit 1101.

[0034] The amplifier transistor 1104 is an NMOS transistor having a gate electrode connected to the first floating diffusion region 1103 and a drain electrode connected to a connection line 1113 for a power supply voltage VDD. The connection line 1113 for the power supply voltage VDD may be a separate line for supplying a power supply voltage for the amplifier transistor 1104 and a power supply voltage for the reset transistor 1108, or may be a common line for supplying a power supply voltage for the amplifier transistor 1104, a power supply voltage for the reset transistor 1108, and the connection line 1114 for supplying a power supply voltage FCVDD. The amplifier transistor 1104 generates, as a pixel signal, a signal having a voltage corresponding to the level of charge accumulated in the first floating diffusion region 1103 or the second floating diffusion region 1107. The amplifier transistor 1104 forms a source follower amplifier and outputs a pixel signal having a voltage corresponding to the level of charge generated in the first photoelectric conversion unit 1101. When the selection transistor 1105 is turned on, the amplification transistor 1104 amplifies the potential of the first floating diffusion region 1103, the second floating diffusion region 1107, the first charge storage capacitance section 1109, or the second charge storage capacitance section 1110, and outputs a voltage corresponding to that potential to the vertical signal line 19 (VSL).

[0035] The selection transistor 1105 is an NMOS transistor provided between the source electrode of the amplification transistor 1104 and the vertical signal line 19. A drive signal SEL is applied to the gate electrode of the selection transistor 1105. When the drive signal SEL becomes a high potential level, the selection transistor 1105 becomes conductive, and the unit pixel 110 becomes a selected state. As a result, the pixel signal output from the amplification transistor 1104 is read out to the vertical signal line 19 via the selection transistor 1105.

[0036] Fig. 3 is a diagram illustrating an example of the planar layout of each element constituting the unit pixel 110 of the photodetector 1 according to the first embodiment of the present disclosure. This diagram illustrates the planar layout as viewed from the surface (front surface) opposite to the light incident surface of the unit pixel 110. Fig. 4 is a partial vertical cross-sectional view illustrating an example of a semiconductor structure of the unit pixel 110, taken along dashed dotted line A-B in Fig. 3. In this disclosure, a plane parallel to the front surface of the unit pixel 110 is referred to as the XY plane, and a direction perpendicular to the XY plane is referred to as the Z direction or depth direction.

[0037] Island-shaped element formation regions (active regions) 301, 302, and 303 are provided on the front surface of the unit pixel 110. A first transfer transistor 1102, an amplification transistor 1104, a selection transistor 1105, a conversion efficiency switching transistor 1106, and a reset transistor 1108 are formed in the element formation region 301. When a drive signal is applied to a gate electrode 1102a of the first transfer transistor 1102, a gate electrode 1105a of the selection transistor 1105, a gate electrode 1106a of the conversion efficiency switching transistor 1106, and a gate electrode 1108a of the reset transistor 1108, the first transfer transistor 1102, the selection transistor 1105, the conversion efficiency switching transistor 1106, and the reset transistor 1108 are electrically connected on the element formation region 301.

[0038] A first charge storage capacitor 1109, a second charge storage capacitor 1110, a first changeover switch 1111, and a second changeover switch 1112 are formed in the element formation region 302. When a drive signal is supplied to a gate electrode 1111a of the first changeover switch 1111 and a gate electrode 1112a of the second changeover switch 1112, the first charge storage capacitor 1109, the second charge storage capacitor 1110, the first changeover switch 1111, and the second changeover switch 1112 are electrically connected on the element formation region 302.

[0039] A reference potential (e.g., VSS) is supplied to the element formation region 303, and the potential of a p-well (described later) is set to the reference potential. The element formation region 301 between the first transfer transistor 1102 and the conversion efficiency switching transistor 1106 is connected to the gate electrode 1104a of the amplification transistor 1104 by a wiring 311 that constitutes the first floating diffusion region 1103. The element formation region 302 between the first changeover switch 1111 and the second changeover switch 1112 is connected to the element formation region 301 between the conversion efficiency switching transistor 1106 and the reset transistor 1108 by a wiring 312 that constitutes the first floating diffusion region 1103.

[0040] The semiconductor structure 40 of the unit pixel 110 is generally configured to include a photoelectric conversion layer 41, a wiring layer 42, and a semiconductor support substrate 43. The wiring layer 42 is stacked on the front surface 41a of the photoelectric conversion layer 41. The wiring layer 42 is a layer on which metal wiring constituting the element formation region 302 is formed. In this example, the wiring layer 42 is formed on the semiconductor support substrate 43. The wiring layer 42 is typically configured by stacking multiple layers of metal wiring with an interlayer insulating film sandwiched between them. The stacked metal wiring is electrically connected, for example, by vias. The wiring layer 42 is formed of a metal such as aluminum (Al) or copper (Cu). Meanwhile, the interlayer insulating film is formed of, for example, a low-k material (SiOC: carbon-doped glass), silicon oxide, or the like. The semiconductor support substrate 43 is a substrate for supporting various layers formed in the semiconductor manufacturing process. Furthermore, logic circuits that realize some of the various components described above are formed on the semiconductor support substrate 43, for example.

[0041] A first changeover switch 1111 and a second changeover switch 1112 are provided for each unit pixel 110 on the front surface 41a side of the photoelectric conversion layer 41. The drain of the first changeover switch 1111 is a high-concentration n-type layer 51, and the drain of the second changeover switch 1112 is a high-concentration n-type layer 52. The sources of the first changeover switch 1111 and the second changeover switch 1112 are high-concentration n-type layers 53. The high-concentration n-type layer 53 is electrically connected to metal wiring 422a via silicon contacts 421a, and forms a second floating diffusion region 1107.

[0042] The back surface side opposite to the front surface 41 a of the photoelectric conversion layer 41 is the light incident surface. Therefore, the photodetector 1 is a back-illuminated solid-state imaging device, and a color filter and an on-chip lens are provided on the back surface side, which is the light incident surface. Each of the color filter and the on-chip lens is provided for each unit pixel 110, for example.

[0043] The photoelectric conversion layer 41 is made of, for example, a silicon substrate. A p-type layer 44 (hereinafter referred to as p-well 44) serving as a well layer is provided in and near a portion of the front surface 41a of the photoelectric conversion layer 41. An n-type layer 45 constituting a photodiode PD is provided in a region deeper than the p-well 44. A high-concentration p-type layer 54 serving as a contact portion of the p-well 44 is provided in the p-well 44. The high-concentration p-type layer 54 is electrically connected to metal wiring 422b via silicon contact 421b. That is, a reference potential VSS is supplied to the high-concentration p-type layer 54 via the metal wiring 422b, and the potential of the p-well 44 is set to the reference potential VSS.

[0044] The photoelectric conversion layer 41 is provided with a pixel isolation layer 55 that electrically isolates adjacent unit pixels 110 from each other. The pixel isolation layer 55 has, for example, a deep trench isolation (DTI) structure and extends in the depth direction of the photoelectric conversion layer 41 (the direction indicated by arrow Z in FIG. 4 ). The pixel isolation layer 55 is made of, for example, silicon oxide. Furthermore, in the photoelectric conversion layer 41, an element isolation portion 56 is provided between the high-concentration n-type layer 52 and the high-concentration p-type layer 54. The element isolation portion 56 has, for example, a shallow trench isolation (STI) structure.

[0045] The high-concentration n-type layer 51 is electrically connected to the first charge storage capacitor 1109 via a silicon contact 421c and a metal wiring 422c, and via a metal wiring that constitutes the element formation region 302. The high-concentration n-type layer 52 is electrically connected to the second charge storage capacitor 1110 via a silicon contact 421d and a metal wiring 422d, and via a metal wiring that constitutes the element formation region 302.

[0046] The gate electrode 1111a of the first changeover switch 1111 is made of, for example, polysilicon (Poly-Si) and is connected to the pixel drive line 18 via a silicon contact 421e and a metal wiring 422e, and a drive signal for controlling the first changeover switch 1111 is supplied from the vertical drive unit 12. The gate electrode 1112a of the second changeover switch 1112 is made of, for example, polysilicon and is connected to the pixel drive line 18 via a silicon contact 421f and a metal wiring 422f, and a drive signal for controlling the first changeover switch 1111 is supplied from the vertical drive unit 12. A gate insulating film 57 is provided between the gate electrode 1111a and the p-well 44. In addition, a gate insulating film 58 is provided between the gate electrode 1112a and the p-well 44.

[0047] The first charge storage capacitor 1109 is an MIM capacitor, and has an upper electrode 61 located on the semiconductor support substrate 43 side, a high-k insulating film 62, and a lower electrode 63 located on the photoelectric conversion layer 41 side. Similarly to the first charge storage capacitor 1109, the second charge storage capacitor 1110 is an MIM capacitor, and has an upper electrode 61 located on the semiconductor support substrate 43 side, a high-k insulating film 62, and a lower electrode 63 located on the photoelectric conversion layer 41 side.

[0048] The lower electrode 63 is part of the metal wiring of the wiring layer 42. The high-k insulating film 62 is provided, for example, in a bellows shape so as to cover the upper surface and side surfaces of the lower electrode 63. The high-k insulating film 62 is also provided so as to cover the lower surface and side surfaces of the upper electrode 61.

[0049] 5A and 5B are timing charts showing an example of the operation of a pixel in a photodetector according to a comparative example of the first embodiment of the present disclosure. In Fig. 5A, charge B100 (shown by dots in Fig. 5A) generated in a first photoelectric conversion unit 1101 overflows a first transfer transistor 1102 and is accumulated in a first floating diffusion region 1103, a second floating diffusion region 1107, and a third floating diffusion region B1101.

[0050] 5B, the shutter is pressed to read out the signal, and then the first photoelectric conversion unit 1101, the first floating diffusion region 1103, the second floating diffusion region 1107, and the third floating diffusion region B 1101 are reset, thereby discharging the charges accumulated in the first floating diffusion region 1103, the second floating diffusion region 1107, and the third floating diffusion region B 1101.

[0051] However, when a high-density capacitor made of a high-k material is used for the third floating diffusion region B1101, dielectric absorption occurs. That is, in FIG. 5C, overflowed charge B100 flows into the third floating diffusion region B1101 during the accumulation period of the first frame, causing a prolonged electric field in the third floating diffusion region B1101. In the second frame, due to the dark state, only dark current B110 (shown by black circles in FIG. 5) normally occurs. However, in reality, dielectric absorption occurs, and charge (dielectric absorption charge) B200 (shown by diagonal lines in FIG. 5) discharged from the capacitance element flows into the third floating diffusion region B1101. Because the dielectric absorption charge B200 depends on the signal from the previous frame, it degrades imaging characteristics. As shown in FIG. 6, in an image captured with a moving bright light source B300, the dielectric absorption charge B200 appears as an afterimage, resulting in image quality degradation.

[0052] 7 is a timing chart showing an example of the operation of the unit pixel 110 in the photodetector 1 according to the first embodiment of the present disclosure. This figure shows a timing chart of drive signals TG, FDG, RST, SWA, and SWB for the unit pixel 110. This processing is performed, for example, for each unit pixel row of the pixel array section 11 or for each of a plurality of unit pixel rows, in a predetermined scanning order a predetermined time after the exposure processing. Furthermore, a frame is assumed to be composed of, for example, a plurality of unit pixels 110 required by the pixel array section 11.

[0053] At time t11, the drive signals TG, FDG, RST, SWA, and SWB go to a high potential level, and the first transfer transistor 1102, the conversion efficiency switching transistor 1106, the reset transistor 1108, the first changeover switch 1111, and the second changeover switch 1112 are each turned on. As a result, the potentials of the first floating diffusion region 1103, the second floating diffusion region 1107, the first charge storage capacitance unit 1109, and the second charge storage capacitance unit 1110 are reset to the power supply voltage VDD.

[0054] Next, at time t12, the system control unit 15 controls the vertical drive unit 12 to set the drive signal SWA to an intermediate potential level between the high potential level and the low potential level, and supply it to the gate electrode 1111a of the first changeover switch 1111. This allows the charge A100 (shown by dots in FIG. 7 ) that has overflowed from the second floating diffusion region 1107 to be stored in the first charge storage capacitor 1109. At this time, the drive signals TG, FDG, RST, and SWB are set to low potential levels, and the first transfer transistor 1102, the conversion efficiency changeover transistor 1106, the reset transistor 1108, and the second changeover switch 1112 are each set to a non-conductive state. From time t12 to time t13, the drive signal TG is set to a high potential level at predetermined intervals, and the first transfer transistor 1102 is set to a conductive state. As a result, the charge A100 generated in the first photoelectric conversion unit 1101 is transferred to the first floating diffusion region 1103 and stored therein.

[0055] Next, at time t13, the drive signal FDG goes to a high potential level, and the conversion efficiency switching transistor 1106 becomes conductive. This couples the potentials of the first floating diffusion region 1103 and the second floating diffusion region 1107. Then, a reset signal M / P for the medium efficiency mode based on the coupled potential of the first floating diffusion region 1103 and the second floating diffusion region 1107 is output to the vertical signal line 19 via the amplification transistor 1104 and the selection transistor 1105.

[0056] Next, at time t14, the drive signal FDG goes to a low potential level, and the conversion efficiency switching transistor 1106 goes into a non-conductive state. This cancels the potential coupling between the first floating diffusion region 1103 and the second floating diffusion region 1107. Then, a high-efficiency mode reset signal H / P based on the potential of the first floating diffusion region 1103 is output to the vertical signal line 19 via the amplification transistor 1104 and the selection transistor 1105.

[0057] Next, at time t15, the drive signal TG goes to a high potential level, and the first transfer transistor 1102 goes into a conductive state. This allows the charges accumulated in the first photoelectric conversion unit 1101 to be transferred to and stored in the first floating diffusion region 1103. Next, at time t16, the drive signal TG goes to a low potential level, and the first transfer transistor 1102 goes into a non-conductive state. This causes a D-phase pixel signal H / D in the high-efficiency mode based on the potential of the first floating diffusion region 1103 to be output to the vertical signal line 19 via the amplification transistor 1104 and the selection transistor 1105.

[0058] Next, at time t17, the drive signal FDG goes to a high potential level, and the conversion efficiency switching transistor 1106 becomes conductive. This couples the potentials of the first floating diffusion region 1103 and the second floating diffusion region 1107. Then, a D-phase pixel signal M / D in the medium efficiency mode based on the coupled potential of the first floating diffusion region 1103 and the second floating diffusion region 1107 is output to the vertical signal line 19 via the amplification transistor 1104 and the selection transistor 1105.

[0059] Next, at time t18, the drive signal SWA goes to a high potential level, and the first changeover switch 1111 goes into a conductive state. This couples the potentials of the first floating diffusion region 1103, the second floating diffusion region 1107, and the first charge storage capacitor 1109. Then, a D-phase pixel signal L / D in the low-efficiency mode based on the coupled potential of the first floating diffusion region 1103, the second floating diffusion region 1107, and the first charge storage capacitor 1109 is output to the vertical signal line 19 via the amplification transistor 1104 and the selection transistor 1105.

[0060] Next, at time t19, the drive signals RST, SWA, and SWB go to a high potential level, and the reset transistor 1108, the first changeover switch 1111, and the second changeover switch 1112 are each turned on, thereby resetting the potentials of the first floating diffusion region 1103, the second floating diffusion region 1107, the first charge storage capacitor 1109, and the second charge storage capacitor 1110 to the power supply voltage VDD.

[0061] Next, at time t20, the drive signal RST goes to a low potential level, and the reset transistor 1108 goes into a non-conducting state. As a result, a low-efficiency mode reset signal L / P based on the combined potential of the first floating diffusion region 1103, the second floating diffusion region 1107, the first charge storage capacitor 1109, and the second charge storage capacitor 1110 is output to the vertical signal line 19 via the amplification transistor 1104 and the selection transistor 1105.

[0062] Next, at time t21, the drive signals FDG, SWA, and SWB go to a low potential level, and the conversion efficiency switching transistor 1106, the first switch 1111, and the second switch 1112 each go into a non-conducting state, thereby completing the processing in the first frame.

[0063] At time t22 of the second frame following the first frame, the drive signals TG, FDG, RST, SWA, and SWB become high potential levels, and the first transfer transistor 1102, the conversion efficiency switching transistor 1106, the reset transistor 1108, the first changeover switch 1111, and the second changeover switch 1112 are each turned on. As a result, the potentials of the first floating diffusion region 1103, the second floating diffusion region 1107, the first charge storage capacitor 1109, and the second charge storage capacitor 1110 are reset to the power supply voltage VDD.

[0064] Next, at time t23, the system control unit 15 controls the vertical drive unit 12 to set the drive signal SWB to a medium potential level and supply it to the gate electrode 1112a of the second changeover switch 1112. This makes it possible to accumulate charge that has overflowed from the second floating diffusion region 1107 in the second charge storage capacitor 1110. At this time, the drive signals TG, FDG, RST, and SWA become low potential levels, and the first transfer transistor 1102, the conversion efficiency changeover transistor 1106, the reset transistor 1108, and the first changeover switch 1111 each become non-conductive.

[0065] Next, at time t24, the drive signal FDG goes to a high potential level, and the conversion efficiency switching transistor 1106 becomes conductive. This couples the potentials of the first floating diffusion region 1103 and the second floating diffusion region 1107. Then, a reset signal M / P for the medium efficiency mode based on the coupled potential of the first floating diffusion region 1103 and the second floating diffusion region 1107 is output to the vertical signal line 19 via the amplification transistor 1104 and the selection transistor 1105.

[0066] Next, at time t25, the drive signal FDG goes to a low potential level, and the conversion efficiency switching transistor 1106 goes into a non-conductive state. This cancels the potential coupling between the first floating diffusion region 1103 and the second floating diffusion region 1107. Then, a high-efficiency mode reset signal H / P based on the potential of the first floating diffusion region 1103 is output to the vertical signal line 19 via the amplification transistor 1104 and the selection transistor 1105.

[0067] Next, at time t26, the drive signal TG goes to a high potential level, and the first transfer transistor 1102 goes into a conductive state. This allows the charges accumulated in the first photoelectric conversion unit 1101 to be transferred to and stored in the first floating diffusion region 1103. Next, at time t27, the drive signal TG goes to a low potential level, and the first transfer transistor 1102 goes into a non-conductive state. This causes the D-phase pixel signal H / D in the high-efficiency mode, based on the potential of the first floating diffusion region 1103, to be output to the vertical signal line 19 via the amplification transistor 1104 and the selection transistor 1105.

[0068] Next, at time t28, the drive signal FDG goes to a high potential level, and the conversion efficiency switching transistor 1106 becomes conductive. This couples the potentials of the first floating diffusion region 1103 and the second floating diffusion region 1107. Then, a D-phase pixel signal M / D in the medium efficiency mode based on the coupled potential of the first floating diffusion region 1103 and the second floating diffusion region 1107 is output to the vertical signal line 19 via the amplification transistor 1104 and the selection transistor 1105.

[0069] Next, at time t29, the drive signal SWB goes to a high potential level, and the second changeover switch 1112 goes into a conductive state. This couples the potentials of the first floating diffusion region 1103, the second floating diffusion region 1107, and the second charge storage capacitor 1110. Then, a D-phase pixel signal L / D in the low-efficiency mode based on the coupled potential of the first floating diffusion region 1103, the second floating diffusion region 1107, and the second charge storage capacitor 1110 is output to the vertical signal line 19 via the amplification transistor 1104 and the selection transistor 1105.

[0070] Next, at time t30, the drive signals RST, SWA, and SWB go to a high potential level, and the reset transistor 1108, the first changeover switch 1111, and the second changeover switch 1112 are each turned on, thereby resetting the potentials of the first floating diffusion region 1103, the second floating diffusion region 1107, the first charge storage capacitor 1109, and the second charge storage capacitor 1110 to the power supply voltage VDD.

[0071] Next, at time t31, the drive signal RST goes to a low potential level, and the reset transistor 1108 goes into a non-conducting state, whereby a reset signal L / P in the low-efficiency mode based on the combined potential of the first floating diffusion region 1103, the second floating diffusion region 1107, the first charge storage capacitor 1109, and the second charge storage capacitor 1110 is output to the vertical signal line 19 via the amplification transistor 1104 and the selection transistor 1105.

[0072] Thereafter, the drive signals FDG, SWA, and SWB become low potential levels, and the conversion efficiency switching transistor 1106, the first switch 1111, and the second switch 1112 become non-conductive, thereby completing the processing in the second frame.

[0073] In this way, by switching the overflow destination for each frame, even if a dielectric absorption charge A200 (shown by diagonal lines in FIG. 7) is generated, it does not affect the output. Since the dielectric absorption charge A200 can be discharged using one frame period, the influence of dielectric absorption can be suppressed when the first charge storage capacitor 1109 or the second charge storage capacitor 1110 is selected in the third frame.

[0074] <Effects of the First Embodiment> As described above, according to the first embodiment, charge overflowing from the first photoelectric conversion unit 1101 flows sequentially into the first floating diffusion region 1103, the second floating diffusion region 1107, the first charge storage capacitor 1109, and the second charge storage capacitor 1110. In the first frame, the voltage of the first selector switch 1111 is set higher than that of the second selector switch 1112, thereby adjusting the current so that it flows into the first charge storage capacitor 1109 and not into the second charge storage capacitor 1110. In the second frame, the relationship between the first selector switch 1111 and the second selector switch 1112 is switched. Therefore, by switching the overflow destination every frame, even if dielectric absorption occurs, the output is not affected. Furthermore, since the dielectric absorption charge A200 can be discharged using one frame period, the influence of dielectric absorption can be suppressed when the first charge storage capacitor 1109 is selected in the third frame.

[0075] Furthermore, according to the first embodiment, the first charge storage capacitor 1109 and the second charge storage capacitor 1110 can be configured as high-density capacitors using the high-k insulating film 62, and high saturation performance can be achieved.

[0076] Second Embodiment A second embodiment of the present disclosure is a modified example of the first embodiment. Fig. 8 is an example of a circuit configuration diagram of a unit pixel 110A in a photodetector 1A according to the second embodiment of the present disclosure. In Fig. 8, the same parts as those in Fig. 2 are denoted by the same reference numerals, and detailed description thereof will be omitted.

[0077] The unit pixel 110A shown in Figure 8 differs from the unit pixel 110 shown in Figure 2 in that the third charge storage capacitance section 1115 and the third changeover switch 1116 are connected in parallel to the first charge storage capacitance section 1109 and the second charge storage capacitance section 1110.

[0078] The third changeover switch 1116 is an NMOS transistor provided between the second floating diffusion region 1107 and the third charge storage capacitor 1115. A drive signal SWC is applied to the gate electrode of the third changeover switch 1116. When the drive signal SWC becomes a high potential level, the third changeover switch 1116 becomes conductive, and the potential of the third charge storage capacitor 1115 and the potential of the second floating diffusion region 1107 are coupled.

[0079] The third charge storage capacitor 1115 is made of an MIM capacitor. One electrode of the third charge storage capacitor 1115 is connected to a connection line 1114 of a power supply voltage FCVDD, and the other electrode is connected to a drain electrode of a third changeover switch 1116. The third charge storage capacitor 1115 stores overflow charges among the charges photoelectrically converted by the first photoelectric conversion unit 1101.

[0080] Fig. 9 is a diagram illustrating an example of a planar layout of each element constituting a unit pixel 110A in a photodetector 1A according to a second embodiment of the present disclosure. This diagram illustrates the planar layout as viewed from the surface (front surface) opposite to the light incident surface of the unit pixel 110A. Fig. 10 is a partial vertical cross-sectional view illustrating an example of a semiconductor structure of the unit pixel 110A shown in Fig. 9 , taken along dashed dotted line A-B. In Fig. 10, the same components as those in Fig. 4 are designated by the same reference numerals, and detailed description thereof will be omitted.

[0081] The front surface of the unit pixel 110A is provided with island-shaped element formation regions (active regions) 321, 322, 323, and 324. An amplifier transistor 1104, a select transistor 1105, a reset transistor 1108, a first charge storage capacitor 1109, and a first changeover switch 1111 are formed in the element formation region 321. When a drive signal is applied to a gate electrode 1104a of the amplifier transistor 1104, a gate electrode 1105a of the select transistor 1105, a gate electrode 1108a of the reset transistor 1108, and a gate electrode 1111a of the first changeover switch 1111, the amplifier transistor 1104, the select transistor 1105, the reset transistor 1108, and the first changeover switch 1111 are electrically connected on the element formation region 321.

[0082] A second charge storage capacitor 1110, a second changeover switch 1112, a third charge storage capacitor 1115, and a third changeover switch 1116 are formed in the element formation region 322. When a drive signal is supplied to a gate electrode 1112a of the second changeover switch 1112 and a gate electrode 1116a of the third changeover switch 1116, the second charge storage capacitor 1110, the second changeover switch 1112, the third charge storage capacitor 1115, and the third changeover switch 1116 are electrically connected on the element formation region 322.

[0083] A first transfer transistor 1102 and a conversion efficiency switching transistor 1106 are formed in the element formation region 323. When a drive signal is applied to a gate electrode 1102 a of the first transfer transistor 1102 and a gate electrode 1106 a of the conversion efficiency switching transistor 1106, the first transfer transistor 1102 and the conversion efficiency switching transistor 1106 are electrically connected on the element formation region 323.

[0084] A reference potential (e.g., VSS) is supplied to the element formation region 324, and the potential of the p-well is set to the reference potential VSS. The element formation region 323 between the first transfer transistor 1102 and the conversion efficiency switching transistor 1106 is connected to the gate electrode 1104a of the amplification transistor 1104 by a wiring 331 that constitutes the first floating diffusion region 1103. The element formation region 322 between the second changeover switch 1112 and the third changeover switch 1116 is connected to the element formation region 323 by a wiring 332 that constitutes the second floating diffusion region 1107. In addition, the element formation region 321 between the first changeover switch 1111 and the reset transistor 1108 is connected to the element formation region 323 by a wiring 332.

[0085] The semiconductor structure 40A of the unit pixel 110A generally includes a photoelectric conversion layer 41, a wiring layer 42, and a semiconductor support substrate 43. The wiring layer 42 is stacked on the front surface 41a of the photoelectric conversion layer 41. A first changeover switch 1111, a second changeover switch 1112, and a third changeover switch 1116 are provided for each unit pixel 110A on the front surface 41a of the photoelectric conversion layer 41. The drain of the third changeover switch 1116 is the high-concentration n-type layer 71, and the source is the high-concentration n-type layer 53. The high-concentration n-type layer 53 is electrically connected to the metal wiring 422a via a silicon contact 421a, forming a second floating diffusion region 1107. In the photoelectric conversion layer 41, an element isolation portion 72 is provided between the high-concentration n-type layer 51 and the high-concentration n-type layer 52. The element isolation portion 72 has, for example, an STI (Shallow Trench Isolation) structure.

[0086] The high-concentration n-type layer 71 is electrically connected to the third charge storage capacitor 1115 via a silicon contact 421 g and a metal wiring 422 g and via a metal wiring that constitutes the element formation region 322 .

[0087] The gate electrode 1116a of the third changeover switch 1116 is made of, for example, polysilicon (Poly-Si) and is connected to the pixel drive line 18 via a silicon contact 421h and a metal wiring 422h, and a drive signal for controlling the third changeover switch 1116 is supplied from the vertical drive unit 12. A gate insulating film 57 is provided between the gate electrode 1116a and the p-well 44. In addition, a gate insulating film 73 is provided between the gate electrode 1112a and the p-well 44.

[0088] <Effects of the Second Embodiment> As described above, according to the second embodiment, by using the first charge storage capacitor 1109, the second charge storage capacitor 1110, and the third charge storage capacitor 1115, the first charge storage capacitor 1109, the second charge storage capacitor 1110, or the third charge storage capacitor 1115 is used once every three frames, thereby ensuring a discharge time of two frame periods. Furthermore, when the time constant of dielectric absorption is one frame period or more, the influence of dielectric absorption can be reduced.

[0089] Third Embodiment A third embodiment of the present disclosure is a modified example of the first embodiment. Fig. 11A is a partial vertical cross-sectional view showing an example of a semiconductor structure of a unit pixel 110B of a photodetector 1B according to a third embodiment of the present disclosure. In Fig. 11A, the same parts as those in Fig. 4 are designated by the same reference numerals, and detailed description thereof will be omitted.

[0090] The first charge storage capacitor 1109 is an MIM capacitor having a cylindrical shape with a three-dimensional structure. Similarly to the first charge storage capacitor 1109, the second charge storage capacitor 1110 is an MIM capacitor having a cylindrical shape with a three-dimensional structure. Here, the first charge storage capacitor 1109 will be described as a representative.

[0091] 11B is a partial cross-sectional view of the first charge storage capacitor 1109 taken along dashed dotted line E-F. The first charge storage capacitor 1109 has a cylindrical shape when viewed from an XY plane parallel to the front surface 41a of the unit pixel 110B. The first charge storage capacitor 1109 has an upper electrode 81 located on the semiconductor support substrate 43 side, a high-k insulating film 82, and a lower electrode 83 located on the photoelectric conversion layer 41 side.

[0092] The lower electrode 83 is part of the metal wiring of the wiring layer 42. The high-k insulating film 82 is provided so as to cover the lower surface and side surfaces of the upper electrode 81. The lower electrode 83 is also provided so as to cover the high-k insulating film 82.

[0093] <Effects of the Third Embodiment> As described above, according to the third embodiment, the same effects as those of the first embodiment can be obtained, and the first charge storage capacitance section 1109 and the second charge storage capacitance section 1110 can be configured as an even higher density capacitance, thereby achieving high saturation performance.

[0094] <Fourth Embodiment> A fourth embodiment of the present disclosure is a modification of the first embodiment. Fig. 12 is an example of a circuit configuration diagram of a unit pixel 110C of a photodetector 1C according to the fourth embodiment of the present disclosure. In Fig. 12, the same parts as those in Fig. 2 are denoted by the same reference numerals, and detailed description thereof will be omitted.

[0095] The unit pixel 110C shown in Figure 12 differs from the unit pixel 110 shown in Figure 2 in that the first charge storage capacitance section 1109 is connected to a connection line 1117 of the power supply voltage FCVDDA (an example of a third power supply connection section), and the second charge storage capacitance section 1110 is connected to a connection line 1118 of the power supply voltage FCVDDBA (an example of a fourth power supply connection section).

[0096] <Effects of Fourth Embodiment> As described above, according to the fourth embodiment, by connecting the first charge storage capacitance unit 1109 to the connection line 1117 of the power supply voltage FCVDDA and connecting the second charge storage capacitance unit 1110 to the connection line 1118 of the power supply voltage FCVDDBA that is different from the power supply voltage FCVDDA, it is possible to set the voltage so that the unit is pulse-driven to reduce dark current when selected and accelerates discharge when not selected.

[0097] Fifth Embodiment A fifth embodiment of the present disclosure is a modification of the first embodiment. Fig. 13 is an example of a circuit configuration diagram of a unit pixel 110D of a photodetector 1D according to the fifth embodiment of the present disclosure. In Fig. 13, the same parts as those in Fig. 2 are denoted by the same reference numerals, and detailed description thereof will be omitted.

[0098] 13 differs from the unit pixel 110 shown in FIG. 2 in that an additional changeover switch 1119 is provided for electrically connecting the power supply voltage VDD connection line 1113 and the power supply voltage FCVDD connection line 1114. The additional changeover switch 1119 is an NMOS transistor. That is, when the drive signal DSW becomes a high potential level, the additional changeover switch 1119 becomes conductive and connects the power supply voltage VDD connection line 1113 and the power supply voltage FCVDD connection line 1114.

[0099] <Effects of the Fifth Embodiment> As described above, according to the fifth embodiment, by keeping the additional changeover switch 1119 in a non-conducting state, when overflow charge flows into the first charge storage capacitance section 1109 and the second charge storage capacitance section 1110, the power supply voltage FCVDD transiently fluctuates, and this effect can be prevented from being transmitted to the connection line 1113 of the power supply voltage VDD.

[0100] Furthermore, when resetting the first charge storage capacitor 1109 and the second charge storage capacitor 1110, in order to reduce the wiring resistance as much as possible, the additional changeover switch 1119 can be turned on to use the power supply voltage VDD.

[0101] Sixth Embodiment A sixth embodiment of the present disclosure is a modification of the first embodiment. Fig. 14 is an example of a circuit configuration diagram of a unit pixel 110E of a photodetector 1E according to the sixth embodiment of the present disclosure. In Fig. 14, the same parts as those in Fig. 2 are denoted by the same reference numerals, and detailed description thereof will be omitted.

[0102] The unit pixel 110E shown in Figure 14 differs from the unit pixel 110 shown in Figure 2 in that it is provided with a third floating diffusion region (FD3) 1120, a charge discharge transistor 1121 (an example of an additional transfer transistor), and an additional conversion efficiency switching transistor 1122.

[0103] The third floating diffusion region 1120 is a diffusion region capable of holding a predetermined amount of charge. A first changeover switch 1111 and a second changeover switch 1112 are connected in parallel to the third floating diffusion region 1120 in the sixth embodiment of the present disclosure.

[0104] The charge discharging transistor 1121 is an NMOS transistor provided between the first photoelectric conversion unit 1101 and the third floating diffusion region 1120. A suitable potential OFG is always applied to the gate electrode of the charge discharging transistor 1121.

[0105] The additional conversion efficiency switching transistor 1122 is an NMOS transistor provided between the second floating diffusion region 1107 and the third floating diffusion region 1120. A drive signal FCG is applied to a gate electrode of the additional conversion efficiency switching transistor 1122. That is, when the drive signal FCG becomes a high potential level, the additional conversion efficiency switching transistor 1122 becomes conductive, and the potential of the second floating diffusion region 1107 and the potential of the third floating diffusion region 1120 are coupled. The additional conversion efficiency switching transistor 1122 controls charge retention by the second floating diffusion region 1107 and the third floating diffusion region 1120, and adjusts the multiplication factor of the voltage according to the potential amplified by the amplification transistor 1104.

[0106] <Effects of Sixth Embodiment> As described above, according to the sixth embodiment, by using the first transfer transistor 1102 and the charge drain transistor 1121, it is possible to separately transfer the charges to be transferred from the first photoelectric conversion unit 1101 to the first floating diffusion region 1103 and the charges that have overflowed in the first photoelectric conversion unit 1101. This makes it possible to reset the first floating diffusion region 1103 and the second floating diffusion region 1107 before reading out the reset signal H / P in the high efficiency mode and the reset signal M / P in the medium efficiency mode, and to align the potential of the P phase every time.

[0107] Seventh Embodiment The seventh embodiment of the present disclosure is a modification of the sixth embodiment. Fig. 15 is an example of a circuit configuration diagram of a unit pixel 110F of a photodetector 1F according to the seventh embodiment of the present disclosure. In Fig. 15, the same parts as those in Fig. 14 are denoted by the same reference numerals, and detailed description thereof will be omitted.

[0108] The unit pixel 110F shown in FIG. 15 differs from the unit pixel 110E shown in FIG. 14 in that it does not include the charge drain transistor 1121 and includes a second photoelectric conversion unit 1123. The second photoelectric conversion unit 1123 is connected to the third floating diffusion region 1120. The second photoelectric conversion unit 1123 generates and accumulates charges according to the amount of light received. In the seventh embodiment of the present disclosure, the area of ​​the light-receiving surface of the first photoelectric conversion unit 1101 is configured to be larger than the area of ​​the light-receiving surface of the second photoelectric conversion unit 1123. Therefore, the first photoelectric conversion unit 1101 is configured to have a higher sensitivity than the second photoelectric conversion unit 1123. By using these two types of photodiodes with different sensitivities, the photodetector 1F can achieve a wide dynamic range of the output level of the pixel signal.

[0109] <Operation and Effects of Seventh Embodiment> As described above, according to the seventh embodiment, high saturation performance can be achieved by using the first photoelectric conversion unit 1101 and the second photoelectric conversion unit 1123 that have different sensitivities.

[0110] Eighth Embodiment An eighth embodiment of the present disclosure is a modification of the seventh embodiment. Fig. 16 is an example of a circuit configuration diagram of a unit pixel 110G of a photodetector 1G according to the eighth embodiment of the present disclosure. In Fig. 16, the same parts as those in Fig. 15 are denoted by the same reference numerals, and detailed description thereof will be omitted.

[0111] The unit pixel 110G shown in Figure 16 differs from the unit pixel 110F shown in Figure 15 in that a second transfer transistor 1124, which is an NMOS transistor, is provided between the second photoelectric conversion unit 1123 and the third floating diffusion region 1120.

[0112] A drive signal TG2 is applied to the gate electrode of the second transfer transistor 1124. That is, when the drive signal TG2 becomes a high potential level, the second transfer transistor 1124 becomes conductive, and the charges accumulated in the second photoelectric conversion unit 1123 are transferred to the third floating diffusion region 1120 via the second transfer transistor 1124.

[0113] <Effects of Eighth Embodiment> As described above, according to the eighth embodiment, the same effects as those of the seventh embodiment can be obtained.

[0114] Ninth Embodiment A ninth embodiment of the present disclosure is a modification of the first embodiment. Fig. 17 is an example of a circuit configuration diagram of a unit pixel 110H of a photodetector 1H according to the ninth embodiment of the present disclosure. In Fig. 17, the same parts as those in Fig. 2 are denoted by the same reference numerals, and detailed description thereof will be omitted.

[0115] The unit pixel 110H shown in Figure 17 differs from the unit pixel 110 shown in Figure 2 in that it does not have the conversion efficiency switching transistor 1106 and has a first switching switch 1111 and a second switching switch 1112 connected in parallel to the first floating diffusion region 1103.

[0116] <Operational Effects of Ninth Embodiment> As described above, according to the ninth embodiment, the same operational effects as those of the seventh embodiment can be obtained, and the number of pixel transistors can be reduced.

[0117] Tenth Embodiment A tenth embodiment of the present disclosure is a modified example of the first embodiment. Fig. 18 is an example of a circuit configuration diagram of a unit pixel 110I of a photodetector 1I according to the tenth embodiment of the present disclosure. In Fig. 18, the same parts as those in Fig. 2 are denoted by the same reference numerals, and detailed description thereof will be omitted.

[0118] The unit pixel 110I shown in Figure 18 differs from the unit pixel 110 shown in Figure 2 in that it has an additional capacitance element 1125 connected to the second floating diffusion region 1107 in parallel with the first charge storage capacitance section 1109 and the second charge storage capacitance section 1110.

[0119] The additional capacitance element 1125 accumulates overflowing charges among the charges photoelectrically converted by the first photoelectric conversion unit 1101. When the drive signal SWA becomes high potential level, the first changeover switch 1111 becomes conductive, and the potential of the first charge storage capacitance unit 1109, the potential of the second floating diffusion region 1107, and the potential of the additional capacitance element 1125 are coupled. Also, when the drive signal SWB becomes high potential level, the first changeover switch 1112 becomes conductive, and the potential of the second charge storage capacitance unit 1110, the potential of the second floating diffusion region 1107, and the potential of the additional capacitance element 1125 are coupled.

[0120] <Operational Effects of Tenth Embodiment> As described above, according to the tenth embodiment, operational effects similar to those of the first embodiment can be obtained.

[0121] Eleventh Embodiment An eleventh embodiment of the present disclosure is a modification of the first embodiment. Fig. 19 is an example of a circuit configuration diagram of a unit pixel 110J of a photodetector 1J according to the eleventh embodiment of the present disclosure. In Fig. 19, the same parts as those in Fig. 2 are denoted by the same reference numerals, and detailed description thereof will be omitted.

[0122] The unit pixel 110J shown in Figure 19 differs from the unit pixel 110 shown in Figure 2 in that it does not have the first transfer transistor 1102 and the conversion efficiency switching transistor 1106, and has a first switching switch 1111 and a second switching switch 1112 connected in parallel to the first floating diffusion region 1103.

[0123] <Operational Effects of Eleventh Embodiment> As described above, according to the eleventh embodiment, the same operational effects as those of the first embodiment can be obtained, and the number of pixel transistors can be reduced.

[0124] 20 is a timing chart showing an example of the operation of a unit pixel 110K in a photodetector 1K according to the twelfth embodiment of the present disclosure. The timing chart shows drive signals TG, FDG, RST, SWA, and SWB for the unit pixel 110K.

[0125] At time t41, the drive signals TG, FDG, RST, SWA, and SWB go to a high potential level, and the first transfer transistor 1102, the conversion efficiency switching transistor 1106, the reset transistor 1108, the first changeover switch 1111, and the second changeover switch 1112 are each turned on. As a result, the potentials of the first floating diffusion region 1103, the second floating diffusion region 1107, the first charge storage capacitance unit 1109, and the second charge storage capacitance unit 1110 are reset to the power supply voltage VDD.

[0126] Next, at time t42, the drive signals TG, FDG, and RST go to low potential levels, and the first transfer transistor 1102, the conversion efficiency switching transistor 1106, the reset transistor 1108, the first changeover switch 1111, and the second changeover switch 1112 each go into a non-conductive state. At this time, the system control unit 15 controls the vertical drive unit 12 to set the drive signals SWA and SWB to an intermediate potential level between high and low potential levels, and supply them to the gate electrode 1111a of the first changeover switch 1111 and the gate electrode 1111a of the second changeover switch 1112. This makes it possible to accumulate charge C100 (shown by dots in FIG. 20 ) overflowing from the second floating diffusion region 1107 in the first charge storage capacitor 1109.

[0127] Next, at time t43, the drive signal FDG goes to a high potential level, and the conversion efficiency switching transistor 1106 becomes conductive. This couples the potentials of the first floating diffusion region 1103 and the second floating diffusion region 1107. Then, a reset signal M / P for the medium efficiency mode based on the coupled potential of the first floating diffusion region 1103 and the second floating diffusion region 1107 is output to the vertical signal line 19 via the amplification transistor 1104 and the selection transistor 1105.

[0128] Next, at time t44, the drive signal FDG goes to a low potential level, and the conversion efficiency switching transistor 1106 goes into a non-conductive state. This cancels the potential coupling between the first floating diffusion region 1103 and the second floating diffusion region 1107. Then, a high-efficiency mode reset signal H / P based on the potential of the first floating diffusion region 1103 is output to the vertical signal line 19 via the amplification transistor 1104 and the selection transistor 1105.

[0129] Next, at time t45, the drive signal TG goes to a high potential level, and the first transfer transistor 1102 goes into a conductive state. This allows the charges accumulated in the first photoelectric conversion unit 1101 to be transferred to and stored in the first floating diffusion region 1103. Next, at time t46, the drive signal TG goes to a low potential level, and the first transfer transistor 1102 goes into a non-conductive state. This causes the D-phase pixel signal H / D in the high-efficiency mode, based on the potential of the first floating diffusion region 1103, to be output to the vertical signal line 19 via the amplification transistor 1104 and the selection transistor 1105.

[0130] Next, at time t47, the drive signal FDG goes to a high potential level, and the conversion efficiency switching transistor 1106 becomes conductive. This couples the potentials of the first floating diffusion region 1103 and the second floating diffusion region 1107. Then, a D-phase pixel signal M / D in the medium efficiency mode based on the coupled potential of the first floating diffusion region 1103 and the second floating diffusion region 1107 is output to the vertical signal line 19 via the amplification transistor 1104 and the selection transistor 1105.

[0131] Next, at time t48, the drive signals SWA and SWB go to a high potential level, and the first changeover switch 1111 and the second changeover switch 1112 are brought into a conductive state. This couples the potentials of the first floating diffusion region 1103, the second floating diffusion region 1107, the first charge storage capacitor 1109, and the second charge storage capacitor 1110. A D-phase pixel signal L / D in the low-efficiency mode based on the coupled potential of the first floating diffusion region 1103, the second floating diffusion region 1107, the first charge storage capacitor 1109, and the second charge storage capacitor 1110 is output to the vertical signal line 19 via the amplification transistor 1104 and the selection transistor 1105.

[0132] Next, at time t49, the drive signals RST, SWA, and SWB go to a high potential level, and the reset transistor 1108, the first changeover switch 1111, and the second changeover switch 1112 are each turned on, thereby resetting the potentials of the first floating diffusion region 1103, the second floating diffusion region 1107, the first charge storage capacitor 1109, and the second charge storage capacitor 1110 to the power supply voltage VDD.

[0133] Next, at time t50, the drive signal RST goes to a low potential level, and the reset transistor 1108 goes into a non-conducting state. As a result, a low-efficiency mode reset signal L / P based on the combined potential of the first floating diffusion region 1103, the second floating diffusion region 1107, the first charge storage capacitor 1109, and the second charge storage capacitor 1110 is output to the vertical signal line 19 via the amplification transistor 1104 and the selection transistor 1105.

[0134] Next, at time t51, the drive signals FDG, SWA, and SWB go to a low potential level, and the conversion efficiency switching transistor 1106, the first switch 1111, and the second switch 1112 each go into a non-conducting state, thereby completing the processing in the first frame.

[0135] At time t52 of the second frame following the first frame, the drive signals TG, FDG, RST, SWA, and SWB become high potential levels, and the first transfer transistor 1102, the conversion efficiency switching transistor 1106, the reset transistor 1108, the first changeover switch 1111, and the second changeover switch 1112 are each turned on. As a result, the potentials of the first floating diffusion region 1103, the second floating diffusion region 1107, the first charge storage capacitor 1109, and the second charge storage capacitor 1110 are reset to the power supply voltage VDD.

[0136] <Effects of the twelfth embodiment> As described above, according to the twelfth embodiment, by using the first charge storage capacitance section 1109 and the second charge storage capacitance section 1110 in combination to hold overflowing charges, it is possible to further improve saturation performance even in imaging situations where there is no dielectric absorption effect.

[0137] <Thirteenth Embodiment> A thirteenth embodiment of the present disclosure is a modification of the first embodiment. Fig. 21 is an example of a circuit configuration diagram of a unit pixel 110L of a photodetector 1L according to the thirteenth embodiment of the present disclosure. In Fig. 21, the same parts as those in Fig. 2 above are denoted by the same reference numerals, and detailed description thereof will be omitted.

[0138] 21 , a first reset transistor 1131 is connected between a connection line 1113 of the power supply voltage VDD and a connection point between a first charge storage capacitor 1109 and a first changeover switch 1111. In addition, a second reset transistor 1132 is connected between the connection line 1113 of the power supply voltage VDD and a connection point between a second charge storage capacitor 1110 and a second changeover switch 1112.

[0139] The first reset transistor 1131 and the second reset transistor 1132 are NMOS transistors. A drive signal RSA is applied to the gate electrode of the first reset transistor 1131. When the drive signal RSA becomes a high potential level, the first reset transistor 1131 becomes conductive.

[0140] A drive signal RSB is applied to the gate electrode of the second reset transistor 1132. When the drive signal RSB goes to a high potential level, the second reset transistor 1132 becomes conductive.

[0141] <Effects of the Thirteenth Embodiment> As described above, according to the thirteenth embodiment, it is possible to select the first charge storage capacitor 1109 and the second charge storage capacitor 1110 without using three-value driving for the drive signal SWA to the first changeover switch 1111 and the drive signal SWB to the second changeover switch 1112, which makes control relatively easy. In addition, signal charge leakage to the first reset transistor 1131 and the second reset transistor 1132 is eliminated.

[0142] <Fourteenth Embodiment> A fourteenth embodiment of the present disclosure is a modification of the first embodiment. Fig. 22 is an example of a circuit configuration diagram of a unit pixel 110M of a photodetector 1M according to the fourteenth embodiment of the present disclosure. In Fig. 22, the same parts as those in Fig. 2 above are denoted by the same reference numerals, and detailed description thereof will be omitted.

[0143] 22, the unit pixel 110M has a first charge storage capacitance 1141 (C_A) and a second charge storage capacitance 1142 (C_B) connected in series between the second floating diffusion region 1107 and the connection line 1114 for the power supply voltage FCVDD. A signal line 1143 is connected between the connection point between the first charge storage capacitance 1141 and the second charge storage capacitance 1142 and the connection point between the reset transistor 1108 and the additional conversion efficiency switching transistor 1122. The signal line 1143 constitutes a third floating diffusion region, which will be described later. In other words, the first charge storage capacitance 1141 is connected between the second floating diffusion region 1107 and the third floating diffusion region, which are different from each other.

[0144] In the fourteenth embodiment of the present disclosure, the first changeover switch 1111 and the second changeover switch 1112 are eliminated, and the first charge storage capacitance unit 1141 and the second charge storage capacitance unit 1142 are switched by the reset transistor 1108 and the additional conversion efficiency switching transistor 1122. This eliminates the need for cutoff adjustment of the first changeover switch 1111 and the second changeover switch 1112, further simplifying the driving.

[0145] When the first charge storage capacitor 1141 is selected, the reset transistor 1108 is in a conductive state (on state), and the additional conversion efficiency switching transistor 1122 is in a non-conductive state (off state). Then, the lower electrode of the second charge storage capacitor 1142 is connected to the connection line 1113 of the power supply voltage VDD, and the upper electrode is connected to the connection line 1114 of the power supply voltage FCVDD. This makes the dielectric absorption charge invisible.

[0146] When the second charge storage capacitor 1142 is selected, the reset transistor 1108 is turned off and the additional conversion efficiency switching transistor 1122 is turned on. Then, since the upper electrode and the lower electrode of the first charge storage capacitor 1141 are short-circuited, the dielectric absorption charges of the first charge storage capacitor 1141 cancel each other out.

[0147] Fig. 23 is a diagram illustrating an example of the planar layout of each element constituting a unit pixel 110M of a photodetector 1M according to a fourteenth embodiment of the present disclosure. This diagram illustrates the planar layout as viewed from the surface (front surface) opposite to the light incident surface of the unit pixel 110. Fig. 24 is a partial vertical cross-sectional view illustrating an example of a semiconductor structure of the unit pixel 110M shown in Fig. 23 , taken along dashed dotted line A-B. In this disclosure, a plane parallel to the front surface of the unit pixel 110M is referred to as the XY plane, and a direction perpendicular to the XY plane is referred to as the Z direction or depth direction.

[0148] The front surface of the unit pixel 110M is provided with island-shaped element formation regions (active regions) 341, 342, and 343. A first transfer transistor 1102, a conversion efficiency switching transistor 1106, a reset transistor 1108, and an additional conversion efficiency switching transistor 1122 are formed in the element formation region 341. By applying a drive signal to a gate electrode 1102a of the first transfer transistor 1102, a gate electrode 1105a of the selection transistor 1105, a gate electrode 1106a of the conversion efficiency switching transistor 1106, a gate electrode 1108a of the reset transistor 1108, and a gate electrode 1122a of the additional conversion efficiency switching transistor 1122, the first transfer transistor 1102, the selection transistor 1105, the conversion efficiency switching transistor 1106, the reset transistor 1108, and the additional conversion efficiency switching transistor 1122 are electrically connected on the element formation region 341.

[0149] An amplifier transistor 1104 and a selection transistor 1105 are formed in the element formation region 342. When a drive signal is applied to a gate electrode 1105a of the selection transistor 1105, the selection transistor 1105 is electrically connected on the element formation region 342.

[0150] A reference potential (e.g., VSS) is supplied to the element formation region 343, and the potential of the p-well is set to the reference potential. The element formation region 341 between the first transfer transistor 1102 and the conversion efficiency switching transistor 1106 is connected to the gate electrode 1104 a of the amplification transistor 1104 by a wiring 344 that forms the first floating diffusion region 1103.

[0151] The semiconductor structure 40 of the unit pixel 110M is generally configured to include a photoelectric conversion layer 41 and a wiring layer 42. In Fig. 24, the same parts as those in Fig. 11A are denoted by the same reference numerals, and detailed description thereof will be omitted.

[0152] The first charge storage capacitor 1141 has a cylindrical shape when viewed from an XY plane parallel to the front surface 41 a of the unit pixel 110M. The first charge storage capacitor 1141 has an upper electrode 81, a high-k insulating film 82, and a lower electrode 83 located on the photoelectric conversion layer 41 side. The second charge storage capacitor 1142 has the same configuration as the first charge storage capacitor 1141.

[0153] A reset transistor 1108 and an additional conversion efficiency switching transistor 1122 are provided for each unit pixel 110M on the front surface 41a side of the photoelectric conversion layer 41. The drain of the additional conversion efficiency switching transistor 1122 is a high-concentration n-type layer 91, and the drain of the reset transistor 1108 is a high-concentration n-type layer 92. The sources of the reset transistor 1108 and the additional conversion efficiency switching transistor 1122 are high-concentration n-type layers 93. The high-concentration n-type layer 93 is electrically connected to a metal wiring 422g via a silicon contact 421g, and forms a third floating diffusion region 1144 including a signal line 1143.

[0154] A gate electrode 1122a of the additional conversion efficiency switching transistor 1122 is made of, for example, polysilicon (Poly-Si) and is connected to the pixel drive line 18 via a silicon contact 421h and a metal wiring 422h, and a drive signal for controlling the additional conversion efficiency switching transistor 1122 is supplied from the vertical drive unit 12. A gate insulating film 94 is provided between the gate electrode 1122a and the p-well 44.

[0155] A gate electrode 1108a of the reset transistor 1108 is made of, for example, polysilicon (Poly-Si) and is connected to the pixel drive line 18 via a silicon contact 421i and a metal wiring 422i, and a drive signal for controlling the reset transistor 1108 is supplied from the vertical drive unit 12. A gate insulating film 95 is provided between the gate electrode 1108a and the p-well 44.

[0156] The high-concentration n-type layer 91, which is the drain of the additional conversion efficiency switching transistor 1122, is electrically connected to the second floating diffusion region 1107 via a silicon contact 421j and a metal wiring 422j. The high-concentration n-type layer 92, which is the drain of the reset transistor 1108, is electrically connected to the connection line 1133 of the power supply voltage VDD via a silicon contact 421k and a metal wiring 422k.

[0157] <Effects of the Fourteenth Embodiment> As described above, according to the fourteenth embodiment, the reset transistor 1108 and the additional conversion efficiency switching transistor 1122 are used to switch between the first charge storage capacitance section 1141 and the second charge storage capacitance section 1142, which eliminates the need to adjust the cutoff of the first changeover switch 1111 and the second changeover switch 1112, thereby further simplifying the driving.

[0158] 25 is a partial vertical cross-sectional view showing an example of a semiconductor structure of a unit pixel 110MA of a photodetector 1MA according to a modification of the fourteenth embodiment of the present disclosure. In Fig. 25, the same parts as those in Fig. 24 are designated by the same reference numerals and detailed description thereof will be omitted.

[0159] In a modification of the fourteenth embodiment of the present disclosure, the lower electrode 83 of the first charge storage capacitor 1141 is connected to the second floating diffusion region 1107, and the upper electrode 81 of the first charge storage capacitor 1141 is connected to the second floating diffusion region 1144. Also, in a modification of the fourteenth embodiment of the present disclosure, the lower electrode 83 of the second charge storage capacitor 1142 is connected to the third floating diffusion region 1144, and the upper electrode 81 of the second charge storage capacitor 1142 is connected to the connection line 1114 of the power supply voltage FCVDD.

[0160] Even with the modified example of the fourteenth embodiment of the present disclosure, the same effects as those of the fourteenth embodiment can be obtained.

[0161] <Fifteenth Embodiment> A fifteenth embodiment of the present disclosure is a modification of the fourteenth embodiment. Fig. 26 is an example of a circuit configuration diagram of a unit pixel 110N of a photodetector 1N according to the fifteenth embodiment of the present disclosure. In Fig. 26, the same parts as those in Fig. 22 are designated by the same reference numerals, and detailed description thereof will be omitted.

[0162] In the fifteenth embodiment of the present disclosure, a dummy transistor 1151 is connected to the first charge storage capacitor 1141. The dummy transistor 1151 has a semiconductor laminated structure made of polysilicon.

[0163] FD dark current occurs when the first charge storage capacitance unit 1141 is used and when the second charge storage capacitance unit 1142 is used, resulting in a difference in the diffusion capacitance of the additional conversion efficiency switching transistor 1122 (FCG). Therefore, in a fifteenth embodiment of the present disclosure, a difference is provided in advance between the capacitance of the first charge storage capacitance unit 1141 and the capacitance of the second charge storage capacitance unit 1142 so as to satisfy the following equation: CA = CB + CFCG, where CA is the capacitance of the first charge storage capacitance unit 1141 and CB is the capacitance of the second charge storage capacitance unit 1142.

[0164] In the fifteenth embodiment of the present disclosure, when the first charge storage capacitor 1141 is in use, the dummy transistor 1151 is brought into a conductive state (on state) to balance things out.

[0165] <Effects of the Fifteenth Embodiment> As described above, the fifteenth embodiment also provides the same effects as the fourteenth embodiment. Furthermore, the fifteenth embodiment can address this issue by turning on / off the conversion efficiency switching transistor 1106 without using the dummy transistor 1151. In this case, when the first charge storage capacitance unit 1141 is used, the conversion efficiency switching transistor 1106 is set to a conductive state (on state), and when the second charge storage capacitance unit 1142 is used, the conversion efficiency switching transistor 1106 is set to a non-conductive state (off state), allowing adjustment by driving.

[0166] <Sixteenth Embodiment> The sixteenth embodiment of the present disclosure is a modified example of the fourteenth embodiment. Figures 27A and 27B are timing charts showing an example of the operation of a unit pixel 110P in a photodetector 1P according to the sixteenth embodiment of the present disclosure. The figures show timing charts of drive signals TG, FDG, FCG, and RST for the unit pixel 110P. Furthermore, the unit pixel 110P in the photodetector 1P according to the sixteenth embodiment of the present disclosure has the same circuit configuration as the unit pixel 110M in the photodetector 1M according to the fourteenth embodiment.

[0167] 27A , when the first charge storage capacitor 1141 is used, at time t61, the drive signal RST goes high, turning on the reset transistor 1108. This resets the potentials of the first floating diffusion region 1103, the second floating diffusion region 1107, the first charge storage capacitor 1141, and the second charge storage capacitor 1142 to the power supply voltage VDD.

[0168] Next, at time t62, the drive signal RST goes to a low potential level, and the reset transistor 1108 goes into a non-conductive state.

[0169] Next, at time t63, the drive signal FDG goes to a high potential level, and the conversion efficiency switching transistor 1106 becomes conductive. This couples the potentials of the first floating diffusion region 1103 and the second floating diffusion region 1107. Then, a reset signal M / P for the medium efficiency mode based on the coupled potential of the first floating diffusion region 1103 and the second floating diffusion region 1107 is output to the vertical signal line 19 via the amplification transistor 1104 and the selection transistor 1105.

[0170] Next, at time t64, the drive signal FDG goes to a low potential level, and the conversion efficiency switching transistor 1106 goes into a non-conductive state. This cancels the potential coupling between the first floating diffusion region 1103 and the second floating diffusion region 1107. Then, a high-efficiency mode reset signal H / P based on the potential of the first floating diffusion region 1103 is output to the vertical signal line 19 via the amplification transistor 1104 and the selection transistor 1105.

[0171] Next, at time t65, the drive signal TG goes to a high potential level, and the first transfer transistor 1102 goes into a conductive state. This allows the charges accumulated in the first photoelectric conversion unit 1101 to be transferred to and stored in the first floating diffusion region 1103. Next, at time t66, the drive signal TG goes to a low potential level, and the first transfer transistor 1102 goes into a non-conductive state. This causes the D-phase pixel signal H / D in the high-efficiency mode, based on the potential of the first floating diffusion region 1103, to be output to the vertical signal line 19 via the amplification transistor 1104 and the selection transistor 1105.

[0172] Next, at time t67, the drive signal FDG goes to a high potential level, and the conversion efficiency switching transistor 1106 becomes conductive. This couples the potentials of the first floating diffusion region 1103 and the second floating diffusion region 1107. Then, a D-phase pixel signal M / D in the medium efficiency mode based on the coupled potential of the first floating diffusion region 1103 and the second floating diffusion region 1107 is output to the vertical signal line 19 via the amplification transistor 1104 and the selection transistor 1105.

[0173] Next, at time t68, the drive signals FDG and FCG go to a high potential level, and the conversion efficiency switching transistor 1106 and the additional conversion efficiency switching transistor 1122 become conductive. This couples the potentials of the first floating diffusion region 1103, the second floating diffusion region 1107, the first charge storage capacitance unit 1141, and the second charge storage capacitance unit 1142. A D-phase pixel signal L / D in the low-efficiency mode based on the coupled potential of the first floating diffusion region 1103, the second floating diffusion region 1107, the first charge storage capacitance unit 1141, and the second charge storage capacitance unit 1142 is output to the vertical signal line 19 via the amplification transistor 1104 and the selection transistor 1105.

[0174] Next, at time t69, the drive signals FDG and FCG change from low potential level to high potential level, and the conversion efficiency switching transistor 1106 and the additional conversion efficiency switching transistor 1122 become conductive. As a result, a reset signal L / P for the low efficiency mode based on the combined potential of the first floating diffusion region 1103, the second floating diffusion region 1107, the first charge storage capacitance unit 1141, and the second charge storage capacitance unit 1142 is output to the vertical signal line 19 via the amplification transistor 1104 and the selection transistor 1105.

[0175] 27B , when the second charge storage capacitor 1142 is used, at time t71, the drive signal FCG goes high, turning on the additional conversion efficiency switching transistor 1122. This resets the potentials of the first floating diffusion region 1103, the second floating diffusion region 1107, the first charge storage capacitor 1141, and the second charge storage capacitor 1142 to the power supply voltage VDD.

[0176] Next, at time t72, the drive signal FCG goes to a low potential level, and the additional conversion efficiency switching transistor 1122 goes into a non-conductive state.

[0177] Next, at time t73, the drive signal FDG goes to a high potential level, and the conversion efficiency switching transistor 1106 becomes conductive. This couples the potentials of the first floating diffusion region 1103 and the second floating diffusion region 1107. Then, a reset signal M / P for the medium efficiency mode based on the coupled potential of the first floating diffusion region 1103 and the second floating diffusion region 1107 is output to the vertical signal line 19 via the amplification transistor 1104 and the selection transistor 1105.

[0178] Next, at time t74, the drive signal FDG goes to a low potential level, and the conversion efficiency switching transistor 1106 goes into a non-conductive state. This cancels the potential coupling between the first floating diffusion region 1103 and the second floating diffusion region 1107. Then, a high-efficiency mode reset signal H / P based on the potential of the first floating diffusion region 1103 is output to the vertical signal line 19 via the amplification transistor 1104 and the selection transistor 1105.

[0179] Next, at time t75, the drive signal TG goes to a high potential level, and the first transfer transistor 1102 goes into a conductive state. This allows the charge accumulated in the first photoelectric conversion unit 1101 to be transferred to and stored in the first floating diffusion region 1103. Next, at time t76, the drive signal TG goes to a low potential level, and the first transfer transistor 1102 goes into a non-conductive state. This causes the D-phase pixel signal H / D in the high-efficiency mode, based on the potential of the first floating diffusion region 1103, to be output to the vertical signal line 19 via the amplification transistor 1104 and the selection transistor 1105.

[0180] Next, at time t77, the drive signal FDG goes to a high potential level, and the conversion efficiency switching transistor 1106 becomes conductive. This couples the potentials of the first floating diffusion region 1103 and the second floating diffusion region 1107. Then, a D-phase pixel signal M / D in the medium efficiency mode based on the coupled potential of the first floating diffusion region 1103 and the second floating diffusion region 1107 is output to the vertical signal line 19 via the amplification transistor 1104 and the selection transistor 1105.

[0181] Next, at time t78, the drive signals FDG and FCG go to a high potential level, and the conversion efficiency switching transistor 1106 and the additional conversion efficiency switching transistor 1122 become conductive. This couples the potentials of the first floating diffusion region 1103, the second floating diffusion region 1107, the first charge storage capacitance unit 1141, and the second charge storage capacitance unit 1142. A D-phase pixel signal L / D in the low-efficiency mode based on the coupled potential of the first floating diffusion region 1103, the second floating diffusion region 1107, the first charge storage capacitance unit 1141, and the second charge storage capacitance unit 1142 is output to the vertical signal line 19 via the amplification transistor 1104 and the selection transistor 1105.

[0182] Next, at time t79, the drive signals FDG and FCG change from low potential level to high potential level, and the conversion efficiency switching transistor 1106 and the additional conversion efficiency switching transistor 1122 become conductive. As a result, a reset signal L / P for the low efficiency mode based on the coupled potential of the first floating diffusion region 1103, the second floating diffusion region 1107, the first charge storage capacitance unit 1141, and the second charge storage capacitance unit 1142 is output to the vertical signal line 19 via the amplification transistor 1104 and the selection transistor 1105.

[0183] As described above, the sixteenth embodiment also provides the same effects as the fourteenth embodiment.

[0184] 17th Embodiment The 17th embodiment of the present disclosure is a modification of the above-described 16th embodiment. Figures 28A and 28B are timing charts showing an example of the operation of a unit pixel 110Q in a photodetector 1Q according to the 17th embodiment of the present disclosure. The figures show timing charts of drive signals TG, FDG, FCG, and RST for the unit pixel 110Q. Furthermore, the unit pixel 110QP in the photodetector 1Q according to the 17th embodiment of the present disclosure has the same circuit configuration as the unit pixel 110M in the photodetector 1M according to the 14th embodiment.

[0185] 28A , when the first charge storage capacitor 1141 is used, at time t81, the drive signals FDG and RST become high potential levels, and the conversion efficiency switching transistor 1106 and the reset transistor 1108 become conductive. As a result, the potentials of the first floating diffusion region 1103, the second floating diffusion region 1107, the first charge storage capacitor 1141, and the second charge storage capacitor 1142 are reset to the power supply voltage VDD.

[0186] Next, at time t82, the drive signal RST goes to a low potential level, and the reset transistor 1108 goes into a non-conductive state.

[0187] Next, at time t83, the drive signal FDG goes to a high potential level, and the conversion efficiency switching transistor 1106 becomes conductive. This couples the potentials of the first floating diffusion region 1103 and the second floating diffusion region 1107. Then, a reset signal M / P for the medium efficiency mode based on the coupled potential of the first floating diffusion region 1103 and the second floating diffusion region 1107 is output to the vertical signal line 19 via the amplification transistor 1104 and the selection transistor 1105.

[0188] Next, at time t84, the drive signal FDG goes to a low potential level, and the conversion efficiency switching transistor 1106 goes into a non-conductive state. This cancels the potential coupling between the first floating diffusion region 1103 and the second floating diffusion region 1107. Then, a high-efficiency mode reset signal H / P based on the potential of the first floating diffusion region 1103 is output to the vertical signal line 19 via the amplification transistor 1104 and the selection transistor 1105.

[0189] Next, at time t85, the drive signal TG goes to a high potential level, and the first transfer transistor 1102 goes into a conductive state. This allows the charges accumulated in the first photoelectric conversion unit 1101 to be transferred to and stored in the first floating diffusion region 1103. Next, at time t86, the drive signal TG goes to a low potential level, and the first transfer transistor 1102 goes into a non-conductive state. This causes the D-phase pixel signal H / D in the high-efficiency mode, based on the potential of the first floating diffusion region 1103, to be output to the vertical signal line 19 via the amplification transistor 1104 and the selection transistor 1105.

[0190] Next, at time t87, the drive signal FDG goes to a high potential level, and the conversion efficiency switching transistor 1106 becomes conductive. This couples the potentials of the first floating diffusion region 1103 and the second floating diffusion region 1107. Then, a D-phase pixel signal M / D in the medium efficiency mode based on the coupled potential of the first floating diffusion region 1103 and the second floating diffusion region 1107 is output to the vertical signal line 19 via the amplification transistor 1104 and the selection transistor 1105.

[0191] Next, at time t88, the drive signals FDG and FCG go to a high potential level, and the conversion efficiency switching transistor 1106 and the additional conversion efficiency switching transistor 1122 become conductive. This couples the potentials of the first floating diffusion region 1103, the second floating diffusion region 1107, the first charge storage capacitance unit 1141, and the second charge storage capacitance unit 1142. A D-phase pixel signal L / D in the low-efficiency mode based on the coupled potential of the first floating diffusion region 1103, the second floating diffusion region 1107, the first charge storage capacitance unit 1141, and the second charge storage capacitance unit 1142 is output to the vertical signal line 19 via the amplification transistor 1104 and the selection transistor 1105.

[0192] Next, at time t89, the drive signals FDG and FCG change from low potential level to high potential level, and the conversion efficiency switching transistor 1106 and the additional conversion efficiency switching transistor 1122 become conductive. As a result, a low-efficiency mode reset signal L / P based on the coupled potential of the first floating diffusion region 1103, the second floating diffusion region 1107, the first charge storage capacitance unit 1141, and the second charge storage capacitance unit 1142 is output to the vertical signal line 19 via the amplification transistor 1104 and the selection transistor 1105.

[0193] 28B , when the second charge storage capacitor 1142 is used, at time t91, the drive signal FCG goes high, turning on the additional conversion efficiency switching transistor 1122. This resets the potentials of the first floating diffusion region 1103, the second floating diffusion region 1107, the first charge storage capacitor 1141, and the second charge storage capacitor 1142 to the power supply voltage VDD.

[0194] Next, at time t92, the drive signal FCG goes to a low potential level, and the additional conversion efficiency switching transistor 1122 goes into a non-conductive state.

[0195] Next, at time t93, the drive signal FDG goes to a high potential level, and the conversion efficiency switching transistor 1106 becomes conductive. This couples the potentials of the first floating diffusion region 1103 and the second floating diffusion region 1107. Then, a reset signal M / P for the medium efficiency mode based on the coupled potential of the first floating diffusion region 1103 and the second floating diffusion region 1107 is output to the vertical signal line 19 via the amplification transistor 1104 and the selection transistor 1105.

[0196] Next, at time t94, the drive signal FDG goes to a low potential level, and the conversion efficiency switching transistor 1106 goes into a non-conductive state. This cancels the potential coupling between the first floating diffusion region 1103 and the second floating diffusion region 1107. Then, a high-efficiency mode reset signal H / P based on the potential of the first floating diffusion region 1103 is output to the vertical signal line 19 via the amplification transistor 1104 and the selection transistor 1105.

[0197] Next, at time t95, the drive signal TG goes to a high potential level, and the first transfer transistor 1102 goes into a conductive state. This allows the charges accumulated in the first photoelectric conversion unit 1101 to be transferred to and stored in the first floating diffusion region 1103. Next, at time t96, the drive signal TG goes to a low potential level, and the first transfer transistor 1102 goes into a non-conductive state. This causes the D-phase pixel signal H / D in the high-efficiency mode, based on the potential of the first floating diffusion region 1103, to be output to the vertical signal line 19 via the amplification transistor 1104 and the selection transistor 1105.

[0198] Next, at time t97, the drive signal FDG goes to a high potential level, and the conversion efficiency switching transistor 1106 becomes conductive. This couples the potentials of the first floating diffusion region 1103 and the second floating diffusion region 1107. Then, a D-phase pixel signal M / D in the medium efficiency mode based on the coupled potential of the first floating diffusion region 1103 and the second floating diffusion region 1107 is output to the vertical signal line 19 via the amplification transistor 1104 and the selection transistor 1105.

[0199] Next, at time t98, the drive signals FDG and FCG go to a high potential level, and the conversion efficiency switching transistor 1106 and the additional conversion efficiency switching transistor 1122 become conductive. This couples the potentials of the first floating diffusion region 1103, the second floating diffusion region 1107, the first charge storage capacitance unit 1141, and the second charge storage capacitance unit 1142. A D-phase pixel signal L / D in the low-efficiency mode based on the coupled potential of the first floating diffusion region 1103, the second floating diffusion region 1107, the first charge storage capacitance unit 1141, and the second charge storage capacitance unit 1142 is output to the vertical signal line 19 via the amplification transistor 1104 and the selection transistor 1105.

[0200] Next, at time t99, the drive signals FDG and FCG change from low potential level to high potential level, and the conversion efficiency switching transistor 1106 and the additional conversion efficiency switching transistor 1122 become conductive. As a result, a reset signal L / P for the low efficiency mode based on the combined potential of the first floating diffusion region 1103, the second floating diffusion region 1107, the first charge storage capacitance unit 1141, and the second charge storage capacitance unit 1142 is output to the vertical signal line 19 via the amplification transistor 1104 and the selection transistor 1105.

[0201] As described above, the seventeenth embodiment also provides the same effects as the fourteenth embodiment.

[0202] <Other Embodiments> As described above, the present technology has been described using the first to seventeenth embodiments. However, the descriptions and drawings that form part of this disclosure should not be understood to limit the present technology. Upon understanding the gist of the technical content disclosed in the first to seventeenth embodiments, it will be apparent to those skilled in the art that various alternative embodiments, examples, and operational techniques may be included in the present technology. Furthermore, the configurations disclosed in the first to seventeenth embodiments may be appropriately combined within a range that does not cause contradictions. For example, configurations disclosed in multiple different embodiments may be combined, or configurations disclosed in multiple different modified examples of the same embodiment may be combined.

[0203] <Application Example to Electronic Devices> The above-described photodetector device can be applied to various electronic devices, such as imaging devices such as digital still cameras and digital video cameras, mobile phones with imaging functions, or other devices with imaging functions. Fig. 29 is a block diagram showing a configuration example of an imaging device as an electronic device to which the present technology is applied.

[0204] The imaging device 2201 shown in Figure 29 is configured with an optical system 2202, a shutter device 2203, a solid-state imaging element 2204 as a photodetector, a control circuit 2205, a signal processing circuit 2206, a monitor 2207, and two memories 2208, and is capable of capturing still images and moving images.

[0205] The optical system 2202 is configured to have one or more lenses, and guides light from a subject (incident light) to the solid-state image sensor 2204 to form an image on the light-receiving surface of the solid-state image sensor 2204 .

[0206] The shutter device 2203 is disposed between the optical system 2202 and the solid-state image sensor 2204 , and controls the light irradiation period and light blocking period for the solid-state image sensor 2204 under the control of the control circuit 2205 .

[0207] The solid-state imaging element 2204 is configured by a package including the above-mentioned solid-state imaging element. The solid-state imaging element 2204 accumulates signal charges for a certain period of time in response to light that is imaged on the light-receiving surface via the optical system 2202 and the shutter device 2203. The signal charges accumulated in the solid-state imaging element 2204 are transferred in accordance with a drive signal (timing signal) supplied from the control circuit 2205.

[0208] The control circuit 2205 outputs a drive signal that controls the transfer operation of the solid-state image sensor 2204 and the shutter operation of the shutter device 2203 , thereby driving the solid-state image sensor 2204 and the shutter device 2203 .

[0209] The signal processing circuit 2206 performs various signal processing on the signal charges output from the solid-state imaging element 2204. The image (image data) obtained by performing the signal processing by the signal processing circuit 2206 is supplied to a monitor 2207 to be displayed, or supplied to a memory 2208 to be stored (recorded). Even in the imaging device 2201 configured in this manner, it is possible to apply the photodetectors 1, 1A, 1B, 1C, 1D, 1E, 1F, 1G, 1H, 1I, 1J, 1K, 1L, 1M, 1MA, 1N, 1P, and 1Q in place of the above-described solid-state imaging element 2204.

[0210] <Application to a Mobile Body> The technology according to the present disclosure (the present technology) can be applied to various products. For example, the technology according to the present disclosure may be realized as a device mounted on any type of mobile body, such as an automobile, an electric vehicle, a hybrid electric vehicle, a motorcycle, a bicycle, personal mobility, an airplane, a drone, a ship, or a robot.

[0211] Fig. 30 is a block diagram showing a schematic configuration example of a vehicle control system, which is an example of a mobile object control system to which the technology according to the present disclosure can be applied. The vehicle control system 12000 includes a plurality of electronic control units connected via a communication network 12001. In the example shown in Fig. 30, the vehicle control system 12000 includes a drive system control unit 12010, a body system control unit 12020, an outside-vehicle information detection unit 12030, an inside-vehicle information detection unit 12040, and an integrated control unit 12050. The functional configuration of the integrated control unit 12050 also includes a microcomputer 12051, an audio / video output unit 12052, and an in-vehicle network I / F (interface) 12053.

[0212] The drivetrain control unit 12010 controls the operation of devices related to the drivetrain of the vehicle in accordance with various programs. For example, the drivetrain control unit 12010 functions as a control device for a drive force generating device for generating a drive force of the vehicle, such as an internal combustion engine or a drive motor, a drive force transmission mechanism for transmitting the drive force to the wheels, a steering mechanism for adjusting the steering angle of the vehicle, and a braking device for generating a braking force of the vehicle.

[0213] The body system control unit 12020 controls the operation of various devices equipped in the vehicle body according to various programs. For example, the body system control unit 12020 functions as a control device for a keyless entry system, a smart key system, a power window device, or various lamps such as headlamps, backup lamps, brake lamps, turn signals, and fog lamps. In this case, radio waves transmitted from a portable device that serves as a key or signals from various switches can be input to the body system control unit 12020. The body system control unit 12020 receives these radio waves or signals and controls the vehicle's door lock device, power window device, lamps, etc.

[0214] The outside-vehicle information detection unit 12030 detects information outside the vehicle equipped with the vehicle control system 12000. For example, an imaging unit 12031 is connected to the outside-vehicle information detection unit 12030. The outside-vehicle information detection unit 12030 causes the imaging unit 12031 to capture images outside the vehicle and receives the captured images. The outside-vehicle information detection unit 12030 may perform object detection processing or distance detection processing for people, cars, obstacles, signs, characters on the road surface, etc. based on the received images.

[0215] The imaging unit 12031 is an optical sensor that receives light and outputs an electrical signal corresponding to the amount of light received. The imaging unit 12031 can output the electrical signal as an image or as distance measurement information. The light received by the imaging unit 12031 may be visible light or invisible light such as infrared light.

[0216] The in-vehicle information detection unit 12040 detects information inside the vehicle. For example, a driver state detection unit 12041 that detects the state of the driver is connected to the in-vehicle information detection unit 12040. The driver state detection unit 12041 includes, for example, a camera that captures an image of the driver, and the in-vehicle information detection unit 12040 may calculate the degree of fatigue or concentration of the driver based on the detection information input from the driver state detection unit 12041, or may determine whether the driver is dozing off.

[0217] The microcomputer 12051 can calculate control target values ​​for the driving force generating device, steering mechanism, or braking device based on the information inside and outside the vehicle acquired by the outside-vehicle information detection unit 12030 or the inside-vehicle information detection unit 12040, and output control commands to the drive system control unit 12010. For example, the microcomputer 12051 can perform cooperative control aimed at realizing the functions of an ADAS (Advanced Driver Assistance System), including vehicle collision avoidance or impact mitigation, following driving based on the inter-vehicle distance, vehicle speed maintenance driving, vehicle collision warning, vehicle lane departure warning, etc.

[0218] In addition, the microcomputer 12051 can perform cooperative control for the purpose of autonomous driving, which allows the vehicle to travel autonomously without relying on driver operation, by controlling the driving force generating device, steering mechanism, braking device, etc. based on information about the surroundings of the vehicle obtained by the outside vehicle information detection unit 12030 or the inside vehicle information detection unit 12040.

[0219] Furthermore, the microcomputer 12051 can output a control command to the body system control unit 12020 based on the information outside the vehicle acquired by the outside information detection unit 12030. For example, the microcomputer 12051 can control the headlamps according to the position of a preceding vehicle or an oncoming vehicle detected by the outside information detection unit 12030, and perform cooperative control aimed at preventing glare, such as switching from high beams to low beams.

[0220] The audio / video output unit 12052 transmits at least one of audio and video output signals to an output device capable of visually or audibly notifying the passengers of the vehicle or the outside of the vehicle of information. In the example of Fig. 19, the output devices are exemplified by an audio speaker 12061, a display unit 12062, and an instrument panel 12063. The display unit 12062 may include, for example, at least one of an on-board display and a head-up display.

[0221] Fig. 31 is a diagram showing an example of the installation position of the image capturing unit 12031. In Fig. 31, a vehicle 12100 has image capturing units 12101, 12102, 12103, 12104, and 12105 as the image capturing unit 12031.

[0222] The imaging units 12101, 12102, 12103, 12104, and 12105 are provided, for example, at positions such as the front nose, side mirrors, rear bumper, back door, and the top of the windshield inside the vehicle cabin of the vehicle 12100. The imaging unit 12101 provided on the front nose and the imaging unit 12105 provided on the top of the windshield inside the vehicle cabin mainly acquire images of the front of the vehicle 12100. The imaging units 12102 and 12103 provided on the side mirrors mainly acquire images of the sides of the vehicle 12100. The imaging unit 12104 provided on the rear bumper or back door mainly acquires images of the rear of the vehicle 12100. The forward images acquired by the imaging units 12101 and 12105 are mainly used to detect preceding vehicles, pedestrians, obstacles, traffic lights, traffic signs, lanes, etc.

[0223] 31 shows an example of the imaging ranges of the imaging units 12101 to 12104. Imaging range 12111 indicates the imaging range of the imaging unit 12101 provided on the front nose, imaging ranges 12112 and 12113 indicate the imaging ranges of the imaging units 12102 and 12103 provided on the side mirrors, respectively, and imaging range 12114 indicates the imaging range of the imaging unit 12104 provided on the rear bumper or back door. For example, by overlaying the image data captured by the imaging units 12101 to 12104, an overhead image of the vehicle 12100 viewed from above can be obtained.

[0224] At least one of the image capturing units 12101 to 12104 may have a function of acquiring distance information. For example, at least one of the image capturing units 12101 to 12104 may be a stereo camera made up of multiple image capturing elements, or may be an image capturing element having pixels for phase difference detection.

[0225] For example, based on the distance information obtained from the imaging units 12101 to 12104, the microcomputer 12051 can calculate the distance to each three-dimensional object within the imaging ranges 12111 to 12114 and the change in this distance over time (relative speed with respect to the vehicle 12100), thereby extracting as a preceding vehicle, in particular, the three-dimensional object that is the closest three-dimensional object on the path of the vehicle 12100 and traveling in approximately the same direction as the vehicle 12100 at a predetermined speed (e.g., 0 km / h or higher). Furthermore, the microcomputer 12051 can set a vehicle-to-vehicle distance to be maintained in advance in front of the preceding vehicle, and perform automatic braking control (including follow-up stop control), automatic acceleration control (including follow-up start control), etc. In this way, cooperative control can be performed for the purpose of autonomous driving, which runs autonomously without relying on driver operation.

[0226] For example, the microcomputer 12051 classifies and extracts three-dimensional object data regarding three-dimensional objects into two-wheeled vehicles, ordinary vehicles, large vehicles, pedestrians, utility poles, and other three-dimensional objects based on distance information obtained from the imaging units 12101 to 12104, and can use the data for automatic obstacle avoidance. For example, the microcomputer 12051 distinguishes obstacles around the vehicle 12100 into obstacles that are visible to the driver of the vehicle 12100 and obstacles that are difficult to see. The microcomputer 12051 then determines a collision risk that indicates the risk of collision with each obstacle, and when the collision risk is equal to or greater than a set value and a collision is possible, the microcomputer 12051 can provide driving assistance for collision avoidance by outputting an alarm to the driver via the audio speaker 12061 or the display unit 12062, or by performing forced deceleration or avoidance steering via the drive system control unit 12010.

[0227] At least one of the image capturing units 12101 to 12104 may be an infrared camera that detects infrared rays. For example, the microcomputer 12051 can recognize a pedestrian by determining whether a pedestrian is present in the images captured by the image capturing units 12101 to 12104. The pedestrian recognition is performed, for example, by extracting feature points from the images captured by the image capturing units 12101 to 12104 as infrared cameras and performing pattern matching on a series of feature points that indicate the outline of an object to determine whether the object is a pedestrian. When the microcomputer 12051 determines that a pedestrian is present in the images captured by the image capturing units 12101 to 12104 and recognizes the pedestrian, the audio / image output unit 12052 controls the display unit 12062 to superimpose a rectangular outline on the recognized pedestrian for emphasis. The audio / image output unit 12052 may also control the display unit 12062 to display an icon or the like indicating the pedestrian at a desired position.

[0228] The present disclosure may also be configured as follows: (1) A photodetector element comprising: a pixel array unit configured of a plurality of pixels each having a photoelectric conversion unit that performs photoelectric conversion in response to received light and a floating diffusion region that temporarily accumulates charge photoelectrically converted by the photoelectric conversion unit; a control unit that controls the pixel array unit; and a pixel signal readout unit that reads out pixel signals based on the charge from the floating diffusion region of the pixel under the control of the control unit, wherein each of the plurality of pixels comprises: a first charge storage capacitor unit; a second charge storage capacitor unit; and a switching unit that selectively connects the first charge storage capacitor unit and the second charge storage capacitor unit to the floating diffusion region under the control of the control unit. (2) The photodetector according to (1), wherein the first charge storage capacitance is connected in parallel to the floating diffusion region, the second charge storage capacitance is connected in parallel to the floating diffusion region and the first charge storage capacitance, the switching unit comprises: a first changeover switch for electrically coupling the floating diffusion region to the first charge storage capacitance, and a second changeover switch for electrically coupling the floating diffusion region to the second charge storage capacitance, and the control unit controls the first changeover switch and the second changeover switch to switch between the first charge storage capacitance and the second charge storage capacitance. (3) The photodetector according to (1), wherein the floating diffusion region includes a plurality of floating diffusion regions, and the first charge storage capacitance and the second charge storage capacitance are connected in parallel to at least one of the plurality of floating diffusion regions. (4) The photodetector element according to (1), wherein the control unit controls the switching unit to switch between the first charge storage capacitor and the second charge storage capacitor for one or more frames formed by the plurality of pixels. (5) The photodetector element according to (2), wherein the control unit controls the first changeover switch and the second changeover switch to switch between the first charge storage capacitor and the second charge storage capacitor for one or more frames formed by the plurality of pixels.(6) The photodetector element according to (5), wherein the first changeover switch is switched by the control unit to one of a first voltage that sets the first changeover switch to an ON state, a second voltage that sets the first changeover switch to an OFF state and that is lower than the first voltage, and a third voltage that sets the first changeover switch to a state between the first voltage and the second voltage and that causes the charge to overflow from the floating diffusion region to the first charge storage capacitor, and the second changeover switch is switched by the control unit to one of the first voltage, the second voltage, and the third voltage. (7) The photodetector element according to (6), wherein the control unit controls the first changeover switch to the third voltage and the second changeover switch to the second voltage in a first frame, and controls the second changeover switch to the third voltage and the first changeover switch to the second voltage in a second frame following the first frame. (8) The photodetector according to (1), wherein the first charge storage capacitor and the second charge storage capacitor have MIM (Metal Insulator Metal) capacitors. (9) The photodetector according to (8), wherein the MIM capacitor uses a high-k material as an insulating film. (10) The photodetector according to (8), wherein the MIM capacitor has a three-dimensional structure. (11) The photodetector according to (1), further comprising an additional switch for electrically coupling the floating diffusion region to the first charge storage capacitor or the second charge storage capacitor. (12) The photodetector according to (1), further comprising a transfer transistor for transferring charges photoelectrically converted by the photoelectric conversion unit to the floating diffusion region. (13) The photodetector element according to (12), wherein the floating diffusion region is provided in a plurality of regions, the transfer transistor transfers the charge photoelectrically converted by the photoelectric conversion unit to one of the plurality of floating diffusion regions, and further includes an additional transfer transistor for transferring the charge overflowing in the photoelectric conversion unit to the other floating diffusion region separately from the transfer transistor. (14) The photodetector element according to (1), wherein each of the plurality of pixels has a first photoelectric conversion unit that photoelectrically converts received light according to a first sensitivity, and a second photoelectric conversion unit that photoelectrically converts received light according to a second sensitivity that is lower than the first sensitivity.(15) The photodetector element according to (14), further comprising: a first transfer transistor for transferring charges photoelectrically converted by the first photoelectric conversion unit to one of the plurality of floating diffusion regions; and a second transfer transistor for transferring charges photoelectrically converted by the second photoelectric conversion unit to the other floating diffusion region. (16) The photodetector element according to (1), further comprising: an additional capacitance element connected to the floating diffusion region in parallel with the first charge storage capacitance unit and the second charge storage capacitance unit. (17) The photodetector element according to (1), further comprising: a third charge storage capacitance unit connected in parallel to the floating diffusion region, the first charge storage capacitance unit, and the second charge storage capacitance unit; and a third selector switch for electrically coupling the floating diffusion region to the third charge storage capacitance unit. (18) The photodetector element according to (1), further comprising: a first power supply connection for supplying power to the photoelectric conversion unit and the floating diffusion region; and a second power supply connection for supplying power to the first charge storage capacitance unit and the second charge storage capacitance unit. (19) The photodetector element according to (18), further comprising: an additional selector switch for electrically coupling the first power supply connection unit and the second power supply connection unit. (20) The photodetector element according to (18), wherein the second power supply connection unit comprises: a third power supply connection unit for supplying power to the first charge storage capacitance unit; and a fourth power supply connection unit for supplying power to the second charge storage capacitance unit separately from the third power supply connection unit. (21) The photodetector element according to (1), further comprising: a plurality of floating diffusion regions; and at least one of the first charge storage capacitance unit and the second charge storage capacitance unit is connected between different floating diffusion regions.(22) An electronic device comprising: a pixel array unit consisting of a plurality of pixels each having a photoelectric conversion unit that performs photoelectric conversion in response to received light and a floating diffusion region that temporarily accumulates charge photoelectrically converted by the photoelectric conversion unit; a control unit that controls the pixel array unit; and a pixel signal readout unit that reads out pixel signals based on the charge from the floating diffusion region of the pixel under the control of the control unit, wherein each of the plurality of pixels comprises a photodetector element having: a first charge storage capacitance unit; a second charge storage capacitance unit; and a switching unit that selectively connects the first charge storage capacitance unit and the second charge storage capacitance unit to the floating diffusion region under the control of the control unit.

[0229] DESCRIPTION OF SYMBOLS 1, 1A, 1B, 1C, 1D, 1E, 1F, 1G, 1H, 1I, 1J, 1K, 1L, 1M, 1MA, 1N, 1P, 1Q Photodetector device 11 Pixel array section 12 Vertical drive section 13 Column processing section 14 Horizontal drive section 15 System control section 16 Signal processing section 17 Data storage section 18 Pixel drive line 19 Vertical signal line (VSL) 40, 40A Semiconductor structure 41 Photoelectric conversion layer 41a Front surface 42 Wiring layer 43 Semiconductor support substrate 44 P-type layer 44 P-well 45 N-type layer 51, 52, 53, 71 Highly-doped n-type layer 54 Highly-doped p-type layer 55 Pixel isolation layer 56, 72 Element isolation section 57, 58, 73 Gate insulating film 61, 81 Upper electrode 62, 82 high-k insulating film 63, 83 lower electrode 110, 110A, 110B, 110C, 110D, 110E, 110F, 110G, 110H, 110I, 110J, 110K, 110L, 110M, 110MA, 110N, 110P, 110Q unit pixel 301, 302, 303, 321, 322, 323, 324 element formation region (active region) 311, 312, 331, 332 wiring 332 element formation region 421a, 421b, 421c, 421d, 421e, 421f, 421g, 421h silicon contact 422a, 422b, 422c, 422d, 422e, 422f, 422g, 422h Metal wiring 1101 First photoelectric conversion unit (PD1) 1102 First transfer transistor 1102a, 1104a, 1105a, 1106a, 1108a, 1111a, 1112a, 1116a Gate electrode 1103 First floating diffusion region (FD1) 1104 Amplification transistor (AMP) 1105 Selection transistor 1106 Conversion efficiency switching transistor 1107 Second floating diffusion region (FD2) 1108 Reset transistor 1109 First charge storage capacitance unit (FD3A) 1110 Second charge storage capacitance unit (FD3B) 1111 First changeover switch 1112 Second changeover switch 1113, 1114, 1117,1118 Connection line 1115 Third charge storage capacitance section 1116 Third changeover switch 1119 Additional changeover switch 1120 Third floating diffusion region (FD3) 1121 Charge discharge transistor 1122 Additional conversion efficiency changeover transistor 1123 Second photoelectric conversion section 1124 Second transfer transistor 1125 Additional capacitance element 1141 First charge storage capacitance section (C_A) 1142 Second charge storage capacitance section (C_B) 1151 Dummy transistor 2201 Imaging device 2202 Optical system 2203 Shutter device 2204 Solid-state imaging element 2205 Control circuit 2206 Signal processing circuit 2207 Monitor 2208 Memory 11109 Voltage generation circuit 12000 Vehicle control system 12001 Communication network 12010 Drive system control unit 12020 Body system control unit 12030 Outside vehicle information detection unit 12031 Imaging unit 12040 Inside vehicle information detection unit 12041 Driver state detection unit 12050 Integrated control unit 12051 Microcomputer 12052 Audio and image output unit 12061 Audio speaker 12062 Display unit 12063 Instrument panel 12100 Vehicle 12101 to 12105 Imaging units 12111 to 12114 Imaging range,

Claims

1. A photodetector comprising: a pixel array section consisting of a plurality of pixels, each having a photoelectric conversion section that performs photoelectric conversion in response to received light and a floating diffusion region that temporarily stores the charge photoelectrically converted by the photoelectric conversion section; a control section that controls the pixel array section; and a pixel signal readout section that reads out pixel signals based on the charge from the floating diffusion region of the pixel under the control of the control section, wherein each of the plurality of pixels comprises: a first charge storage capacitor section; a second charge storage capacitor section; and a switching section that selectively connects the first charge storage capacitor section and the second charge storage capacitor section to the floating diffusion region under the control of the control section.

2. The photodetector element of claim 1, wherein the first charge storage capacitance section is connected in parallel to the floating diffusion region, the second charge storage capacitance section is connected in parallel to the floating diffusion region and the first charge storage capacitance section, the switching section comprises a first changeover switch for electrically coupling the floating diffusion region to the first charge storage capacitance section, and a second changeover switch for electrically coupling the floating diffusion region to the second charge storage capacitance section, and the control section controls the first changeover switch and the second changeover switch to switch between the first charge storage capacitance section and the second charge storage capacitance section.

3. The photodetector element according to claim 1, wherein the floating diffusion region is provided in a plurality of regions, and the first charge storage capacitance section and the second charge storage capacitance section are connected in parallel to at least one of the plurality of floating diffusion regions.

4. The photodetector element of claim 1, wherein the control unit controls the switching unit to switch between the first charge storage capacitance unit and the second charge storage capacitance unit for each of one or more frames formed by the plurality of pixels.

5. The photodetector element described in claim 2, wherein the control unit controls the first changeover switch and the second changeover switch so as to switch between the first charge storage capacitance unit and the second charge storage capacitance unit for one or more frames formed by the plurality of pixels.

6. The photodetector element of claim 5, wherein the first changeover switch is switchable by the control unit to a first voltage that sets the first switch to an on state, a second voltage that sets the first switch to an off state and is lower than the first voltage, and a third voltage that sets the first switch to a state between the first voltage and the second voltage such that the charge overflows from the floating diffusion region to the first charge storage capacitor, and the second changeover switch is switchable by the control unit to the first voltage, the second voltage, and the third voltage.

7. The photodetector element of claim 6, wherein the control unit controls the first changeover switch to the third voltage and the second changeover switch to the second voltage in a first frame, and controls the second changeover switch to the third voltage and the first changeover switch to the second voltage in a second frame following the first frame.

8. The photodetector element according to claim 1, wherein the first charge storage capacitor and the second charge storage capacitor have MIM (Metal Insulator Metal) capacitors.

9. The light-detecting element according to claim 8, wherein the MIM capacitor uses a high-k material for the insulating film.

10. The photodetector element according to claim 8, wherein the MIM capacitor has a three-dimensional structure.

11. The photodetector element of claim 1, further comprising an additional changeover switch for electrically coupling said floating diffusion region to said first charge storage capacitor or said second charge storage capacitor.

12. The photodetector element according to claim 1, further comprising a transfer transistor for transferring charges photoelectrically converted by said photoelectric conversion portion to said floating diffusion region.

13. The photodetector element according to claim 12, further comprising: a plurality of said floating diffusion regions; said transfer transistor transfers charges photoelectrically converted by said photoelectric conversion unit to one of said plurality of floating diffusion regions; and an additional transfer transistor for transferring charges overflowing from said photoelectric conversion unit to the other floating diffusion region separately from said transfer transistor.

14. A photodetector element according to claim 1, wherein each of the plurality of pixels has a first photoelectric conversion unit that photoelectrically converts received light according to a first sensitivity, and a second photoelectric conversion unit that photoelectrically converts received light according to a second sensitivity that is lower than the first sensitivity.

15. The photodetector element according to claim 14, further comprising: a first transfer transistor that transfers charges photoelectrically converted by the first photoelectric conversion unit to one of the plurality of floating diffusion regions; and a second transfer transistor that transfers charges photoelectrically converted by the second photoelectric conversion unit to the other floating diffusion region.

16. The photodetector element according to claim 1, further comprising an additional capacitance element connected to the floating diffusion region in parallel with the first charge storage capacitance portion and the second charge storage capacitance portion.

17. The photodetector element of claim 1, further comprising: a third charge storage capacitance section connected in parallel to the floating diffusion region, the first charge storage capacitance section, and the second charge storage capacitance section; and a third selector switch for electrically coupling the floating diffusion region to the third charge storage capacitance section.

18. The photodetector element of claim 1, further comprising: a first power supply connection portion for supplying power to the photoelectric conversion portion and the floating diffusion region; and a second power supply connection portion for supplying power to the first charge storage capacitance portion and the second charge storage capacitance portion.

19. The photodetector element of claim 18, further comprising an additional changeover switch for electrically coupling said first power connection and said second power connection.

20. The photodetector element of claim 18, wherein the second power supply connection comprises a third power supply connection for supplying power to the first charge storage capacitance, and a fourth power supply connection for supplying power to the second charge storage capacitance separately from the third power supply connection.

21. The photodetector element according to claim 1, wherein the floating diffusion region is provided in a plurality of regions, and at least one of the first charge storage capacitance section and the second charge storage capacitance section is connected between different floating diffusion regions.

22. An electronic device comprising: a pixel array unit consisting of a plurality of pixels each having a photoelectric conversion unit that performs photoelectric conversion in response to received light and a floating diffusion region that temporarily stores charge photoelectrically converted by the photoelectric conversion unit; a control unit that controls the pixel array unit; and a pixel signal readout unit that reads out pixel signals based on the charge from the floating diffusion region of the pixel under the control of the control unit, wherein each of the plurality of pixels comprises a photodetector element having a first charge storage capacitance unit and a second charge storage capacitance unit, and a switching unit that selectively connects the first charge storage capacitance unit and the second charge storage capacitance unit to the floating diffusion region under the control of the control unit.

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