Doherty amplifier

Abstract

A main amplifier (1) and an auxiliary amplifier (2) of a Doherty amplifier are respectively constituted by epitaxial laminates (401 to 407) different from each other, transistors of the same size are respectively formed on the different epitaxial laminates, and, when the transistors are subjected to a class-C operation, the epitaxial laminate constituting the transistor having a higher gain is used for the auxiliary amplifier (2).

Description

Doherty Amplifier

[0001] The present disclosure relates to a Doherty amplifier using GaN HEMTs.

[0002] In recent years, base stations for fifth-generation (5G) high-speed wireless communications need to transmit large volumes of data with low distortion. To achieve this, the base station's transmitting power amplifiers have a large backoff amount from the saturated output point. Since a large backoff amount reduces the efficiency of the power amplifier, Doherty amplifiers, which can maintain high efficiency even during backoff, are used to reduce power consumption.

[0003] 1 shows the circuit block of the Doherty amplifier. In the Doherty amplifier, a main amplifier 1 (also referred to as a carrier amplifier) ​​and an auxiliary amplifier 2 (also referred to as a peak amplifier) ​​are connected in parallel. When the back-off amount is large, the transistor size of the auxiliary amplifier 2 is often designed to be larger than the transistor size of the main amplifier 1. In other words, the saturated output performance of the Doherty amplifier is mainly borne by the auxiliary amplifier 2. The Doherty amplifier includes a power divider 3 that distributes a signal input from a signal input unit 7 to the main amplifier 1 and the auxiliary amplifier 2, and a power combiner 4 that combines the outputs of the main amplifier 1 and the auxiliary amplifier 2 and outputs the combined amplified signal from an amplified signal combined output unit 8.

[0004] An impedance conversion circuit 5 is provided between the main amplifier 1 and the power combiner 4, and a phase adjustment circuit 6 is provided between the auxiliary amplifier 2 and the power divider 3. The impedance conversion circuit 5 is, for example, a transmission line with an electrical length of λ / 4, where λ is the electrical length at the operating frequency, and is capable of converting impedance from 25 Ω to 100 Ω.

[0005] The amplifier operating classes are set to Class AB for the main amplifier 1 and Class C for the auxiliary amplifier 2. In Class AB, the class is set to less than half the saturation current of the transistor, and in Class C, the class is set so that the current is completely turned off. This allows the operation shown in Figures 2A to 2D to be achieved. First, Figure 2A shows the output characteristics of the main amplifier 1 (2-1-M) and auxiliary amplifier 2 (2-1-A) versus input power, and Figure 2B shows the gain characteristics of the main amplifier 1 (2-2-M) and auxiliary amplifier 2 (2-2-A) versus input power. In Figures 2A to 2D, PinS indicates the input power at the gain compression point where the gain of the main amplifier 1 begins to drop significantly.

[0006] As shown in Figure 2A, the output of the main amplifier 1 also tends to saturate at the gain compression point PinS. Generally, amplifiers are most efficient near output saturation, so it is advantageous to use the main amplifier 1 in a range close to this point. On the other hand, the auxiliary amplifier 2 is biased in class C, so it is off when the input power is low and turns on due to self-bias as the input power increases. The bias of the auxiliary amplifier 2 is set so that it turns on at the gain compression point PinS. Because the transistor size of the auxiliary amplifier 2 is larger than that of the main amplifier 1, the saturated output of the auxiliary amplifier 2 is higher than that of the main amplifier 1, as shown in Figure 2A.

[0007] On the other hand, as the transistor size increases, the parasitic feedback capacitance increases, and as shown in Figure 2B, the gain of auxiliary amplifier 2 becomes lower than the gain of main amplifier 1. Figure 2C shows the output characteristics obtained by combining the output (2-3-M) of main amplifier 1 and the output (2-3-A) of auxiliary amplifier 2 (i.e., the output characteristics of the Doherty amplifier), and Figure 2D shows the gain characteristics obtained by combining the output (2-4-M) of main amplifier 1 and the output (2-4-A) of auxiliary amplifier 2 (i.e., the gain characteristics of the Doherty amplifier). In Figure 2C, PoutS is the output power corresponding to PinS.

[0008] As shown in Figure 2C, even after the main amplifier 1 is saturated, the auxiliary amplifier 2 supplements the output, thereby extending the overall saturated output. This effect ensures the required antenna output. Meanwhile, the efficiency and distortion of the entire Doherty amplifier are determined by the average output point of the output probability distribution of the transmission signal, so performance near the gain compression point PinS is important. As shown in Figure 2D, gain compression of the main amplifier 1 begins at the gain compression point PinS, and the overall gain compression can be compensated for by combining the gain of the auxiliary amplifier 2 that rises from PinS. This effect depends on the gain performance of the auxiliary amplifier in class C operation.

[0009] In this way, the Doherty amplifier is used at the saturated output point where the efficiency of the main amplifier 1 is highest, while the auxiliary amplifier 2 compensates for its drawback of gain compression characteristics and also improves the overall output characteristics. Due to this feature, the Doherty amplifier has become the industry standard for achieving both the efficiency characteristics and distortion characteristics at the large back-off point required for transmission power amplifiers in 5G base stations. Furthermore, to reduce distortion, many current base stations also use a method of extracting a portion of the output signal of the Doherty amplifier and performing distortion compensation using DPD (digital predistortion).

[0010] GaN high electron mobility transistors (HEMTs) are promising semiconductor devices suitable for transmission power amplifiers in 5G base stations. This is because GaN HEMTs have the following characteristics: low on-resistance (Ron) and high transconductance (gm) utilizing the high mobility of two-dimensional electron gas (2DEG), high breakdown voltage due to a wide bandgap, and high current drivability due to the piezoelectric effect. A low Ron contributes to efficiency performance, while a high gm contributes to high gain. High breakdown voltage and current drivability contribute to high output. These characteristics make GaN HEMTs the device with the greatest industrial growth potential in the base station field.

[0011] WO 2024 / 263968

[0012] Table 1 shows the requirements for the main amplifier and auxiliary amplifier based on the operating principle of the Doherty amplifier.

[0013]

[0014] The main amplifier is required to have high efficiency in class AB operation, followed by low distortion. Meanwhile, the auxiliary amplifier is required to have high gain in class C operation to supplement the main amplifier, followed by high output power. In conventional Doherty amplifiers, GaN HEMTs made of the same epitaxial stack have been used for the main and auxiliary amplifiers. This is to streamline the manufacturing process. GaN HEMTs made of epitaxial layers optimized for the main amplifier have also been used for the auxiliary amplifier. However, because the main and auxiliary amplifiers operate at different operating classes, there is a trade-off in performance. A device that maximizes the requirements for the main amplifier operating in class AB must never maximize the requirements for the auxiliary amplifier operating in class C.

[0015] Figures 3A to 3C show an example of the relationship between efficiency and distortion characteristics in class AB operation and gain and output characteristics in class C operation when using the same epitaxial stack. First, Figure 3A shows the relationship between efficiency performance in class AB operation and output characteristics in class C operation. A device that prioritizes efficiency in class AB operation is not good for output performance in class C operation. This is because reducing parasitic capacitance, which leads to power loss, for high efficiency and increasing current density to improve output performance are incompatible. In class C operation, output performance is inferior to class AB operation, so improving current density is particularly effective. However, if the same epitaxial stack is used for class AB operation, the high density current and increased parasitic capacitance between the transistor electrodes lead to a decrease in efficiency.

[0016] Next, Figure 3B shows the trade-off between efficiency performance in class AB operation and gain performance in class C operation. A device that prioritizes efficiency in class AB operation is not good for gain performance in class C operation. This is because reducing parasitic capacitance and improving gm to improve gain performance are incompatible. Since class C operation is less favorable for gain performance than class AB operation, increasing gm is particularly effective. However, if the same epitaxial layer is used for class AB operation, increasing gm will increase parasitic capacitance, resulting in a decrease in efficiency.

[0017] Finally, Figure 3C shows the trade-off between distortion performance in class AB operation and gain performance in class C operation. The vertical axis of distortion performance is measured using adjacent channel leakage power ratio (ACLR), with better distortion performance indicated in the downward direction of the vertical axis. ACLR indicates the proportion of leakage power that occurs outside the transmission frequency range due to the nonlinearity of a semiconductor device when a modulated signal is input. As shown in Figure 3C, a device that prioritizes distortion performance in class AB operation is not good for gain performance in class C operation. Distortion performance is determined by the flatness of the gm characteristic relative to gate-source voltage (Vgs) fluctuations. Trying to flatten this characteristic lowers the gm peak and reduces gain. Thus, distortion performance and gain performance are incompatible. 3A to 3C and Table 1, it can be seen that there is a trade-off between the high efficiency and low distortion performance of class AB required for the main amplifier and the high gain and high output performance of class C required for the auxiliary amplifier. For this reason, selecting the optimal device for the main amplifier, as in the past, may not be optimal for the auxiliary amplifier, and vice versa. The conventional method of applying GaN HEMTs made of the same epitaxial layer stack to the main amplifier and auxiliary amplifier has its own problems. The present disclosure solves the above problems.

[0018] A Doherty amplifier according to one aspect of the present disclosure is a Doherty amplifier comprising a main amplifier that operates in class AB and an auxiliary amplifier that operates in class C, and is characterized in that each amplifier is provided with a GaN HEMT made of two different materials, and after comparing performance by changing the operating class while keeping the size common, the material that provides the higher gain during class C operation is selected for the auxiliary amplifier, and the material that provides the higher saturated drain efficiency during class AB operation is selected for the main amplifier.

[0019] In the Doherty amplifier according to one aspect of the present disclosure, the two different types of materials are different GaN epitaxial stacks, and the GaN channel layer and the Al Ｘ Ga １－Ｘ This Doherty amplifier has a structure in which an AlN layer is inserted between barrier layers made of N (0<x<1), and the thickness of the AlN layer is different. However, the thickness of the AlN layer of the main amplifier may include zero. In other words, the AlN layer of the main amplifier does not need to be inserted.

[0020] Although the use of different epitaxial layers for the main amplifier and auxiliary amplifier of a Doherty amplifier has already been proposed in the above-mentioned Patent Document 1, that document describes a structure in which the gain of the main amplifier is made higher than that of the auxiliary amplifier. On the other hand, the present disclosure describes a structure in which the gain of the auxiliary amplifier is made higher than that of the main amplifier, and thus the purpose and structure are different.

[0021] In the Doherty amplifier configuration of the present disclosure, an auxiliary amplifier with excellent high gain and high output performance in class C operation and a main amplifier with excellent high efficiency and low distortion performance in class AB operation can be obtained without trade-off, and the Doherty amplifier as a whole can achieve high efficiency and low distortion characteristics.

[0022] FIG. 1 is a block diagram of a Doherty amplifier, which is a technical field of the present disclosure. FIG. 2A is a diagram showing the operating principle of the Doherty amplifier (input power and output characteristics of the main amplifier and auxiliary amplifier). FIG. 2B is a diagram showing the operating principle of the Doherty amplifier (input power and gain characteristics of the main amplifier and auxiliary amplifier). FIG. 2C is a diagram showing the operating principle of the Doherty amplifier (input power and output characteristics of the Doherty amplifier). FIG. 2D is a diagram showing the operating principle of the Doherty amplifier (input power and gain characteristics of the Doherty amplifier). FIG. 3A is a diagram showing trade-off characteristics depending on the operating class (saturated output power during class-C operation and saturated efficiency characteristics during class-AB operation), which is a problem to be solved by the present disclosure. FIG. 3B is a diagram showing trade-off characteristics depending on the operating class (saturated gain during class-C operation and saturated efficiency characteristics during class-AB operation), which is a problem to be solved by the present disclosure. FIG. 3C is a diagram showing trade-off characteristics depending on the operating class (saturated gain during class-C operation and distortion (ACLR) characteristics during class-AB operation), which is a problem to be solved by the present disclosure. FIG. 4A is a diagram showing an epitaxial stack and potential energy of the conduction band (showing a cross-sectional view of the epitaxial stack). FIG. 4B is a diagram showing potential energy of the epitaxial stack and potential energy of the conduction band (showing potential energy of the conduction band). FIG. 5 is a diagram showing a structural cross-sectional view of a GaN HEMT using an epitaxial stack. FIG. 6A is a diagram showing epitaxial stacks (epi 1) of different main amplifiers and auxiliary amplifiers according to an embodiment. FIG. 6B is a diagram showing epitaxial stacks (epi 2) of different main amplifiers and auxiliary amplifiers according to an embodiment. FIG. 6C is a diagram showing epitaxial stacks (comparison of saturation efficiency when epi 1 and epi 2 are operated in class AB) of different main amplifiers and auxiliary amplifiers according to an embodiment. FIG. 6D is a diagram showing epitaxial stacks (comparison of saturation gain when epi 1 and epi 2 are operated in class C) of different main amplifiers and auxiliary amplifiers according to an embodiment. Fig. 7 is a diagram showing experimental results of a GaN HEMT having epitaxial stacks with different AlN layers according to embodiment 1. Fig. 8A is a diagram showing experimental results of RF characteristics according to embodiment 1 (RF characteristics during class AB operation). Fig. 8B is a diagram showing experimental results of RF characteristics according to embodiment 1 (RF characteristics during class C operation).9A is a diagram showing experimental results (gate-source voltage Vgs and gate-source current Igs) illustrating the difference in characteristics between the presence and absence of the AlN layer according to embodiment 2. FIG. 9B is a diagram showing experimental results (gate-source voltage Vgs and transconductance g. ｍｍａｘ FIG. 9C is a diagram showing experimental results (results of drain-source voltage Vds and parasitic drain-source capacitance) showing the difference in characteristics between the presence and absence of an AlN layer according to the second embodiment. FIG. 10A is a diagram showing a combination of semiconductor substrates of an epitaxial stack according to the third embodiment (showing a case where the same semiconductor substrate is used for the main amplifier and the auxiliary amplifier). FIG. 10B is a diagram showing a combination of semiconductor substrates of an epitaxial stack according to the third embodiment (showing a combination where semiconductor substrates with different thermal conductivities are used for the main amplifier and the auxiliary amplifier. The thermal conductivity of the main amplifier is greater than that of the auxiliary amplifier).

[0023] (Summary of the Present Disclosure) Hereinafter, embodiments will be specifically described with reference to the drawings.

[0024] The embodiments described below are all comprehensive or specific examples. The numerical values, shapes, materials, components, component placement and connection configurations, characteristic examples, steps, and step order shown in the following embodiments are merely examples and are not intended to limit the present disclosure. Furthermore, among the components in the following embodiments, components not described in independent claims are described as optional components.

[0025] Furthermore, each figure is a schematic diagram and is not necessarily an exact illustration. Therefore, for example, the scales of the figures do not necessarily match. Furthermore, in each figure, substantially the same components are given the same reference numerals, and redundant explanations are omitted or simplified.

[0026] Furthermore, in this specification, terms indicating the relationship between elements, such as parallel or perpendicular, terms indicating the shape of elements, such as rectangle, and numerical ranges are not expressions that only express a strict meaning, but are expressions that also include a substantially equivalent range, for example, a difference of about a few percent.

[0027] In addition, in this specification and drawings, the x-axis, y-axis, and z-axis represent the three axes of a three-dimensional Cartesian coordinate system. Specifically, the x-axis and y-axis are two axes parallel to the main surface (top surface) of the substrate of the Doherty amplifier, and the z-axis is a direction perpendicular to this main surface. Specifically, the direction in which the source electrode, gate electrode, and drain electrode are arranged in this order, i.e., the so-called gate length direction, is the x-axis. In the embodiments described below, the positive direction of the z-axis may be referred to as "upward," and the negative direction of the z-axis may be referred to as "downward." In addition, in this specification, "planar view" refers to the main surface (top surface) of the substrate of the Doherty amplifier as viewed from the positive direction of the z-axis, unless otherwise specified.

[0028] In this specification, a group III nitride semiconductor is a semiconductor containing one or more group III elements and nitrogen. Examples of group III elements include aluminum (Al), gallium (Ga), and indium (In). Examples of group III nitride semiconductors include GaN, AlN, InN, AlGaN, InGaN, and AlInGaN. Group III nitride semiconductors may also contain one or more elements other than group III elements, such as silicon (Si) and phosphorus (P). In the following description, unless otherwise specified, the term "AlInGaN" means that the group III nitride semiconductor contains all of Al, In, Ga, and N. The same applies to other designations such as AlGaN and GaN.

[0029] Furthermore, a layer made of material A such as a Group III nitride semiconductor such as GaN or AlGaN, silicon nitride or silicon oxide, and a layer constituted by material A mean that the layer contains substantially only material A. However, the layer may contain other elements as impurities, such as elements that are unavoidable in the manufacturing process, at a rate of 1 atm % or less.

[0030] In this specification, the composition ratio (composition rate) of a group III element in a nitride semiconductor (layer) refers to the ratio of the number of atoms of a target group III element among a plurality of group III elements contained in the nitride semiconductor. ａ In ｂ Gaｃ In the case where the nitride semiconductor layer is made of N (a+b+c=1, a≧0, b≧0, c≧0), the Al composition ratio of the nitride semiconductor layer can be expressed as a / (a+b+c). Similarly, the In composition ratio and the Ga composition ratio can be expressed as b / (a+b+c) and c / (a+b+c), respectively.

[0031] Furthermore, in this specification, ordinal numbers such as "first" and "second" do not refer to the number or order of components unless otherwise specified, but are used for the purpose of avoiding confusion and distinguishing between components of the same type.

[0032] 4A and 4B, an epitaxial stack having an AlN layer inserted therein, which is a feature of the present disclosure, will be described. The circuit configuration of the Doherty amplifier according to the present disclosure is the same as the block diagram shown in FIG.

[0033] 4A , the epitaxial stack includes a substrate 401, a buffer layer 402, a channel layer 403, a barrier layer 404, and a cap layer 407. A 2DEG 406 is formed near the interface between the channel layer 403 and the barrier layer 404. The buffer layer 402, the channel layer 403, the barrier layer 404, and the cap layer 407 are an epitaxial stack formed by epitaxial growth.

[0034] The substrate 401 is a substrate made of Si. Alternatively, the substrate 401 may be a SiC substrate. The substrate 401 may also be a substrate made of sapphire, diamond, SOI (Silicon on Insulator), GaN, AlN, or the like. The buffer layer 402 is provided above the substrate 401. For example, the buffer layer 402 is provided in contact with the upper surface of the substrate 401. The buffer layer 402 is, for example, a layer made of a Group III nitride semiconductor. As an example, the buffer layer 402 has a multi-layer structure of AlN and AlGaN, each having a thickness of 2 μm. The buffer layer 402 may also be composed of a single layer or multiple layers of a Group III nitride semiconductor, such as GaN, AlGaN, AlN, InGaN, or AlInGaN.

[0035] The provision of the buffer layer 402 can reduce adverse effects such as crystal dislocations and lattice defects caused by the difference in lattice spacing between the substrate 401 and the channel layer 403. Furthermore, even if the substrate 401 has defects, the provision of the buffer layer 402 can suppress the effects of the defects on the channel layer 403. This reduces defects in the channel layer 403, improves crystallinity, and increases electron mobility in the channel layer 403. The buffer layer 402 does not necessarily have to be provided.

[0036] The channel layer 403 is provided above the substrate 401. Specifically, the channel layer 403 is provided in contact with the upper surface of the buffer layer 402. The channel layer 403 is a layer made of a nitride semiconductor containing Ga elements. For example, the channel layer 403 is made of GaN. The film thickness of the channel layer 403 is, for example, 50 nm to 300 nm, and is 150 nm as an example. Note that the channel layer 403 is not limited to GaN, and may be made of a group III nitride semiconductor such as InGaN, AlGaN, or AlInGaN. Furthermore, the channel layer 403 may contain n-type impurities. The film thickness of the channel layer 403 is not limited to the above example.

[0037] The barrier layer 404 is provided above the channel layer 403. The barrier layer 404 may be provided in contact with the upper surface of the channel layer 403. The barrier layer 404 has a larger band gap than the channel layer 403 and is a layer made of a nitride semiconductor containing Ga. The barrier layer 404 is made of, for example, AlGaN. The Al composition ratio of the barrier layer 404 is, for example, 10% to 30%, but may be 20% to 30%. The Al composition ratio of the barrier layer 404 is, for example, 27%. The film thickness of the barrier layer 404 is, for example, 3 nm to 30 nm, for example, 13 nm. The barrier layer 404 is not limited to AlGaN, and may be made of a group III nitride semiconductor such as AlInGaN. The barrier layer 404 may also contain n-type impurities. A high concentration of 2DEG 406 is generated on the channel layer 403 side of the heterointerface between the barrier layer 404 and the channel layer 403 due to the piezoelectric stress of the barrier layer 404 on the channel layer 403. The 2DEG 406 is used as a channel of a transistor.

[0038] The cap layer 407 covers and contacts the upper surface of the barrier layer 404. The cap layer 407 is a layer made of a group III nitride semiconductor. The cap layer 407 is made of, for example, GaN. The thickness of the cap layer 407 is, for example, not less than about 1 nm and not more than about 2 nm. By providing the cap layer 407, oxidation of Al in the barrier layer 404 can be suppressed. Note that the cap layer 407 does not necessarily have to be provided.

[0039] An AlN layer 405 having a thickness of, for example, about 0 nm to about 2 nm, which is characteristic of the present disclosure, is provided between the barrier layer 404 and the channel layer 403. This AlN layer 405 is inserted to increase the mobility and saturation velocity of the 2DEG 406. This effect will be explained with reference to FIG. 4B . FIG. 4B shows the potential energy of conduction band electrons in the top-to-bottom direction of FIG. 4A (the direction of the dashed line from TOP to BOTTOM in the figure). Because the AlN layer 405 has high potential energy, electrons in the 2DEG 406 are confined in potential energy valleys, resulting in good two-dimensionality. This means that the spread of the electron wave function is narrow. Without the AlN layer 405, the electron wave function would diffuse from the 2DEG 406 region to the barrier layer 404 and be scattered by ions in the barrier layer, resulting in a decrease in mobility. The presence of the AlN layer 405 suppresses the broadening of the wave function, resulting in high mobility and, as a result, high saturation velocity. The high mobility allows for a high peak value of gm, which is advantageous for achieving high gain, and the high saturation velocity allows for a high saturation current, which is advantageous for achieving high output.

[0040] In addition, the AlN layer 405 has the effect of suppressing leakage current from the 2DEG 406 to the gate side (the TOP side in FIG. 4A) due to its high potential barrier. ｆ Since the gate amplitude of the input RF signal can be increased, this is advantageous for achieving high output.

[0041] Next, a GaN HEMT formed using the epitaxial stack of FIG. 4A will be described with reference to FIG. 5. FIG. 5 is a diagram showing a structural cross-sectional view of a GaN HEMT using an epitaxial stack. The meanings of the layers indicated by the reference numerals (i.e., 501 to 507) of the epitaxial stack in FIG. 5 are the same as those explained in FIGS. 4A to 4B (i.e., 401 to 407), and the suffixes of the reference numerals correspond to those in FIGS. 4A to 4B. The GaN HEMT includes a source electrode 511, a drain electrode 512, a gate electrode 513, and a source field plate 514. The GaN HEMT may be formed using, for example, Si ３N ４ The semiconductor device includes a first insulating layer 521 and a second insulating layer 522 (collectively referred to as an insulating film 520) made of a material selected from the group consisting of: a source electrode 511 and a drain electrode 512, which are spaced apart from each other above the substrate 501; a gate electrode 513 sandwiched between the source electrode 511 and the drain electrode 512; and a conductive material for the source electrode 511 and the drain electrode 512. For example, the source electrode 511 and the drain electrode 512 are multilayer electrode films having a laminated structure in which a Ti film and an Al film are laminated in this order, but this is not limiting. The source electrode 511 and the drain electrode 512 may be alloy layers formed by annealing a laminated structure of a Ti film and an Al film at a temperature of 500°C or higher. The source electrode 511 and the drain electrode 512 may also be made of a transition metal, a transition metal nitride, or a transition metal carbide. Specifically, the source electrode 511 and the drain electrode 512 may be made of Ta, Hf, W, Ni, TiN, TaN, HfN, WN, TiC, TaC, HfC, Au, Cu, etc., or may be a compound containing these elements, or may be a multilayer electrode film consisting of a multiple layer structure.

[0042] The source electrode 511 and the drain electrode 512 are also called ohmic electrodes, and are electrically connected to the 2DEG 506 through an ohmic connection. In this embodiment, the source electrode 511 and the drain electrode 512 are provided so as to be in contact with the 2DEG 506.

[0043] Specifically, the GaN HEMT has two recesses that penetrate the cap layer 507 and the barrier layer 504 and reach the channel layer 503. The two recesses are also referred to as a source opening and a drain opening, respectively. A source electrode 511 is provided so as to contact and cover the inner surface of the source opening, and a drain electrode 512 is provided so as to contact and cover the inner surface of the drain opening. The bottom surface of each of the two recesses is located below the interface between the channel layer 503 and the barrier layer 504. Therefore, the 2DEG 506 is exposed on the side surface of each of the two recesses. The source electrode 511 and the drain electrode 512 are in contact with the 2DEG 506 on the side surface of the recess. This reduces the channel contact resistance. Note that instead of the recesses, source contact regions and drain contact regions with low resistance may be provided by adding n-type impurities to portions of the cap layer 507, the barrier layer 504, and the channel layer 503. The source and drain contact regions are formed by, for example, plasma treatment, ion implantation, and crystal regrowth.

[0044] The gate electrode 513 is provided above the barrier layer 504 between the source electrode 511 and the drain electrode 512 and spaced apart from each other.

[0045] The gate electrode 513 has a multilayer structure, and the gate electrode lower portion 513L is formed using a conductive material capable of forming a Schottky junction with a nitride semiconductor containing Ga. For example, the gate electrode lower portion 513L is formed using Ni, Ti, TiN, TaN, W, Pd, or the like.

[0046] The upper gate electrode portion 513U is formed using a material with a lower resistivity than the lower gate electrode portion 513L. For example, the upper gate electrode portion 513U is formed using Au or Al. The upper gate electrode portion 513U is provided so as to contact and cover the upper surface of the lower gate electrode portion 513L. The thickness of the upper gate electrode portion 513U is, for example, 450 nm to 650 nm, e.g., 500 nm, but is not limited thereto. In plan view, the shape and size of the upper gate electrode portion 513U are substantially the same as those of the lower gate electrode portion 513L. Thus, the multilayer structure of the gate electrode 513 can reduce the gate resistance Rg in the z-axis direction while ensuring a Schottky junction. The reduced gate resistance Rg can improve high-frequency gain. The gate electrode 513 does not have to have a multilayer structure, and may instead have a single-layer structure formed using a conductive material capable of forming a Schottky junction with a nitride semiconductor containing Ga.

[0047] The distance along the x-axis of the junction 513a between the gate electrode 513 and the epitaxial stack is the so-called gate length Lg, and Lg is, for example, 0.2 μm. The distance along the x-axis from the drain side end of the junction 513a to the drain electrode 512 is called the gate-drain distance Lgd. The distance along the x-axis from the source side end of the junction 513a to the source electrode 511 is called the gate-source distance Lgs. In this embodiment, Lgs<Lgd. For example, Lgd is 3.2 μm and Lgs is 1.3 μm. By making the gate-drain distance Lgd longer than the gate-source distance Lgs, it is possible to alleviate electric field concentration between the gate and drain. Note that it is not essential to satisfy Lgs<Lgd; Lgs=Lgd or Lgs>Lgd may also be satisfied.

[0048] The source field plate 514 is provided above the gate electrode 513 and is set to the same potential as the source electrode 511. Specifically, the source field plate 514 is provided above the insulating layer 522. The source field plate 514 is provided so that at least a portion thereof is located between the gate electrode 513 and the drain electrode 512 in a planar view. In the example shown in FIG. 5 , the source field plate 514 is arranged so that a portion thereof overlaps the gate electrode 513 in a planar view. The source field plate 514 is electrically insulated from the gate electrode 513 and the drain electrode 512, and is set to the potential (source potential) applied to the source electrode 511.

[0049] During operation of the GaN HEMT, a high voltage of approximately 90 V to 150 V is applied to the drain electrode 512. At this time, a high electric field is applied between the drain electrode 512 and the gate electrode 513. Specifically, electric field lines from the drain electrode 512 concentrate at the end of the drain-side overhang of the gate electrode 513, increasing the peak value of the electric field and reducing reliability. By providing the source field plate 514, this peak value of the electric field can be reduced. The source field plate 514 can alleviate the high electric field peak by dispersing it in the x-axis direction. This improves the gate-drain breakdown voltage and reliability by suppressing gate leakage current.

[0050] The source field plate 514 is formed using a conductive material. The source field plate 514 has a multilayer electrode film configuration, for example, a laminated structure in which a TiN film and an Al film are stacked in order. The thickness of the source field plate 514 is, for example, 500 nm, but is not limited to this. The source field plate 514 is not limited to a laminated structure of a TiN film and an Al film, and may also be a transition metal nitride or carbide formed by sputtering. Specifically, the source field plate 514 may be made of Ti, Ta, W, Ni, TiN, TaN, WN, W, Au, Cu, etc., or a compound containing these elements, or a multilayer electrode film consisting of a multilayer structure. As an example, the source field plate 514 has a multilayer structure in which Ti, TiN, and Al are stacked in this order from the bottom up. Alternatively, the source field plate 514 may include Au in the top layer.

[0051] The first insulating layer 521 is, for example, a Si layer having a thickness of 100 nm. ３ N ４ The insulating layer 521 is provided above the epitaxial stack, between the gate electrode 513 and the drain electrode 512. Specifically, the insulating layer 521 is in contact with and covers the upper surface of the cap layer 507 between the gate electrode 513 and the drain electrode 512. The insulating layer 521 is provided over the entire area from the drain side end of the junction 513a of the gate electrode 513 to the drain electrode 512. In this embodiment, the insulating layer 521 is also provided between the gate electrode 513 and the source electrode 511. Specifically, the insulating layer 521 is in contact with and covers the upper surface of the cap layer 507 between the gate electrode 513 and the source electrode 511. The insulating layer 521 is provided over the entire area from the source side end of the junction 513a of the gate electrode 513 to the source electrode 511.

[0052] The second insulating layer 522 is, for example, a Si layer having a thickness of 150 nm. ３ N ４The insulating layer 522 is provided between the gate electrode 513 and the source field plate 514. Specifically, the insulating layer 522 is provided so as to cover the entire area of ​​the GaN HEMT. The insulating layer 522 has openings for ensuring wiring contacts to the source electrode 511 and the drain electrode 512, respectively.

[0053] The insulating layers 521 and 522 are made of Si ３ N ４ Not limited to, SiO ２ , SiON may be used. The source field plate 514 does not necessarily have to be provided.

[0054] Next, FIGS. 6A to 6D will explain how to select the auxiliary amplifier and main amplifier of a Doherty amplifier based on the performance comparison results of GaN HEMTs with different operating classes formed using two types of epitaxial stacks, which is the present disclosure.

[0055] As shown in Figures 6A and 6B, epitaxial stacks Epi 1 and Epi 2 having different AlN layer thicknesses are prepared. ２ The thickness of the AlN film on epitaxial layer D １ Thicker. That is, D １ <D ２ and D １ includes 0 nm.

[0056] Using these two different types of epitaxial stacks, a semiconductor chip containing a GaN HEMT is obtained using the same semiconductor mask and the same semiconductor process. When the same chip is operated under RF conditions under the same measurement conditions, the saturated efficiency of class AB operation and the saturated gain of class C operation are compared, as shown in Figures 6C and 6D.

[0057] As a result, the present disclosure is characterized in that Epi2, which has a high saturated gain in class C operation, is used for the auxiliary amplifier 632, and Epi1, which has a high saturated efficiency in class AB operation, is used for the main amplifier 631.

[0058] A prototype sample of the GaN HEMT according to this embodiment was prepared, and the data obtained will be specifically described below with reference to FIGS. 7, 8A to 8B, and 9A to 9C.

[0059] (Embodiment 1) The prototype samples according to embodiment 1 are of two types, one with a thinner AlN layer thickness of 1.5 nm and one with a thicker AlN layer thickness of 2.0 nm. The thickness of the AlN layer can be adjusted by controlling the growth time of epitaxial growth, and the thickness can be easily increased by extending the deposition time.

[0060] First, the difference in DC characteristics is shown in FIG. 7, and the results are compared with the requirements for the main amplifier and auxiliary amplifier of the Doherty amplifier.

[0061] The device used for DC characteristic evaluation is a so-called TEG (Test Element Group) with a finger length of 100 μm. As shown in (7-1), (7-2), and (7-3) in Figure 7, the thicker AlN layer of 2 nm has a higher saturation current I ｍａｘ , forward rise voltage V ｆ , maximum mutual conductance g ｍｍａｘ High values ​​were obtained in ｍａｘ and high V ｆ contributes to the saturated output during class C operation, and the high maximum transconductance g ｍｍａｘ contributes to the saturated gain during class C operation.

[0062] On the other hand, as shown in (7-4) of Figure 7, a thicker AlN layer increases the gate-drain leakage current, which is detrimental to the efficiency characteristics during class AB operation. Conversely, a thinner AlN layer reduces the gate-drain leakage current, which is advantageous for the efficiency characteristics during class AB operation.

[0063] When compared with Table 1, which summarizes the requirements for the amplifiers that make up the Doherty amplifier described above, it can be seen that a thicker AlN layer has characteristics that are more suitable for use as an auxiliary amplifier, while a thinner AlN layer has characteristics that are more suitable for use as a main amplifier.

[0064] 8A and 8B show the difference in characteristics when actually operating with a large RF signal. The results are compared with the requirements for the main amplifier and auxiliary amplifier of the Doherty amplifier.

[0065] The device used for evaluating the RF large signal characteristics was a TEG with a total gate width of 400 μm and two parallel finger lengths of 200 μm, mounted on a metal plate via a die attach adhesive. The metal plate is made of a material with excellent thermal conductivity, such as copper or brass, and the die attach adhesive is made of a material with excellent thermal conductivity, such as Ag particles.

[0066] The RF large signal measurement conditions were a drain operating voltage of 28 V, a center frequency of 4.1 GHz, and input power as a pulse input with a duty cycle of 10%, and the input and output impedances were fixed for comparison. This fixed impedance was determined in advance to allow for a balanced comparison of efficiency, gain, and output characteristics. The bias conditions were measured with a drain current of 6 mA for class AB operation and a gate voltage 1 V below the pinch-off voltage for class C operation.

[0067] The RF input was gradually increased up to the saturated output, and the output, gain, and efficiency performance were measured. Here, the efficiency index was not the power load efficiency, but the drain efficiency, which is suitable for comparing the performance of a single transistor. The saturation values ​​of the above three items for class AB operation are shown in (8-1), (8-2), and (8-3) of Figure 8A, and the saturation values ​​for class C operation are shown in (8-4), (8-5), and (8-6) of Figure 8B. In other words, (8-1) of Figure 8A shows the relationship between the thickness of the AlN layer and the saturated power P during class AB operation. ｓａｔ The results of (8-2) in FIG. 8A show the relationship between the thickness of the AlN layer and the saturated gain Gain during class AB operation. Ｍａｘ (Maximum Gain), and (8-3) in FIG. 8A shows the relationship between the thickness of the AlN layer and the saturated efficiency η ｄｍａｘ 8B shows the results of the saturation power Psat during class C operation and the thickness of the AlN layer. FIG. 8B (8-5) shows the results of the saturation gain Gain during class C operation and the thickness of the AlN layer. Ｍａｘ The results of (8-6) in FIG. 8B show the relationship between the thickness of the AlN layer and the saturated efficiency η ｄｍａｘThe results are shown below.

[0068] First, the following can be seen from a comparison of (8-2) in FIG. 8A and (8-5) in FIG. 8B.

[0069] In class AB operation, the thicker AlN layer has a slightly higher gain than the thinner one, but in class C operation, the thicker AlN layer has a significantly higher gain than the thinner one. Specifically, the gain difference in class AB operation is about 0.1 dB, but the difference in class C operation is actually more than 1 dB. From this result, it can be seen that a thicker AlN layer is more suitable as an auxiliary amplifier, since, as already mentioned, the most important requirement for an auxiliary amplifier in class C operation is the saturated gain during class C operation.

[0070] On the other hand, the following can be seen from a comparison of (8-3) in FIG. 8A and (8-6) in FIG. 8B.

[0071] In class C operation, both the thin and thick AlN layers have a high level of efficiency well above 70%, but in class AB operation, the thin AlN layer has a significantly higher efficiency than the thick AlN layer. From this result, it can be seen that the greatest requirement for a main amplifier operating in class AB is saturation efficiency during class AB operation, and therefore a thin AlN layer is more suitable as a main amplifier.

[0072] This disclosure focuses on the fact that differences in gain and efficiency due to differences in epitaxial stacks constituting the same GaN HEMT magnify the performance difference due to differences in the operating class. In particular, the present disclosure emphasizes the difficulty of obtaining gain during class C operation of the auxiliary amplifier. If an epitaxial stack with a thick AlN layer is selected as the main amplifier in order to ensure this class C operating gain, as shown in (8-5) of FIG. 8B, the efficiency during class AB operation will decrease, as shown in (8-3) of FIG. 8A, and the overall efficiency of the combined Doherty amplifier will decrease.

[0073] Based on the above results, we concluded that preparing two epitaxial stacks with different AlN layer thicknesses and using the epitaxial stack with the thicker AlN layer for the auxiliary amplifier and the epitaxial stack with the thinner AlN layer for the main amplifier would be effective in improving the performance of the Doherty amplifier.

[0074] Second Embodiment The distortion characteristics during class AB operation, which is a requirement for the main amplifier of a Doherty amplifier, will be described with reference to Figures 9A to 9C. In Figures 9A to 9C, the solid lines show the characteristics with an AlN layer, and the dashed lines show the characteristics without an AlN layer.

[0075] In this experiment, the device used to compare the performance of GaN HEMTs made of two types of epitaxial stacks was one with a thin AlN layer thickness of zero, i.e., no AlN layer, in order to make the effect of strain on the AlN layer more pronounced. The device with the AlN layer was 2 nm thick, the same as in embodiment 1. The TEG used for the measurements had one 100 μm finger.

[0076] FIG. 9A shows the relationship between the gate-source voltage Vgs and the gate-source leakage current Igs when an AlN layer is present (solid line) and when it is not present (dashed line).

[0077] As shown in Figure 9A, the linearity of Igs differs on the positive side of Vgs. This linearity is the rise characteristic of the Schottky junction between the gate electrode and the semiconductor, and the N value, which is the amount of incorporation of the Richardson equation, a thermal electron model of the Schottky junction, is an appropriate performance index. In the case of an ideal Schottky junction, the N value is close to 1. In the experimental results, without the AlN layer, the N value was approximately 1, while with the AlN layer, the N value significantly deviated from 1 and exceeded 2, resulting in a significant degradation of the linearity of Igs. This degradation of linearity affects the strain characteristics, so the presence of the AlN layer is detrimental to the strain characteristics.

[0078] Figure 9B also shows the results of the Vgs vs. transconductance gm curve. While this varies depending on the applied drain voltage, the curve for 20 V is shown as a representative example. The presence of the AlN layer is characterized by a higher gm peak. On the other hand, the absence of the AlN layer shows a lower gm peak, but a wider gm flat region relative to the gate-source voltage Vgs. The distortion characteristics are strongly affected by this gm flatness, and a wider gm flat region is more important than a high gm peak. This also shows that the absence of the AlN layer is better in terms of distortion characteristics. On the other hand, the presence of the AlN layer, which has a higher gm peak, allows for a sharper gm peak when Vgs is turned on, making it preferable for an amplifier operating in class C. This is because, as shown in FIG. 2B , which illustrates the operating principle of a Doherty amplifier, if the gain of the main amplifier drops sharply from the gain compression point PinS while the gain of the auxiliary amplifier rises sharply to compensate, when the two amplifiers are combined, the linearity of the combined gain is more easily maintained and distortion characteristics are less likely to deteriorate.

[0079] Also, in FIG. 9C, the parasitic drain-source capacitance C ｄｓ The drain-source voltage V ｄｓ This shows the dependency of the parasitic capacitance C ｄｓ If is large, it will result in power loss on the transistor output side, so the parasitic capacitance C ｄｓ The results in this figure show that not having an AlN layer is desirable for efficiency performance, while having an AlN layer is detrimental to efficiency performance.

[0080] The experimental results according to the first and second embodiments of the present disclosure are summarized in Table 2 below. The table is organized based on how each characteristic item obtained from the experiment changes depending on the film thickness of the AlN layer. Since each characteristic item has both DC and RF characteristics, the characteristic classification (RF, DC) is also shown in the second column from the left. The rightmost column of the table lists the drawing numbers showing the experimental data for this embodiment, as already described.

[0081]

[0082] The following becomes clear from Table 2 and Table 1 which summarizes the requirements for each amplifier in the Doherty amplifier.

[0083] The characteristics of the upper region with a thick AlN layer, surrounded by a dashed line in Table 2, satisfy the requirements for an auxiliary amplifier, while the characteristics of the lower region with a thin AlN layer, surrounded by a solid line, satisfy the requirements for a main amplifier. It can be concluded that dividing the thickness of the AlN layer into those for the auxiliary amplifier and those for the main amplifier, and using the thicker AlN layer as the auxiliary amplifier and the thinner one (including a thickness of zero) as the main amplifier, is effective for a Doherty amplifier.

[0084] Table 2, which summarizes the experiments and considerations related to the embodiment of the present disclosure, provides a guideline for optimizing devices for the main amplifier and auxiliary amplifier that constitute the Doherty amplifier.

[0085] Third Embodiment Finally, the semiconductor substrate that serves as the growth base for the epitaxial stack will be described.

[0086] In the above explanation, it was assumed that the semiconductor substrate of the epitaxial stack in which the AlN layer thickness is changed between the main amplifier and the auxiliary amplifier is the same, but this does not necessarily have to be the same. As long as the thermal conductivity of the semiconductor substrate of the main amplifier, which has a high average power consumption, is better than the thermal conductivity of the semiconductor substrate of the auxiliary amplifier, there is no restriction within that range. Further explanation will be given using Figures 10A and 10B.

[0087] 10A shows an example in which the main amplifier and the auxiliary amplifier are configured on a common semiconductor substrate A. Examples of the semiconductor substrate A include SiC, Si, sapphire, SOI, and GaN. The thermal conductivity κ of each is 300 W / mK for SiC, 150 W / mK for Si, 130 W / mK for GaN, 42 W / mK for sapphire, and 1.3 W / mK for SOI. For base station applications, SiC, which has the best thermal conductivity, is often used, but because SiC is expensive, Si is used when cost reduction is the goal.

[0088] FIG. 10B shows an example in which the main amplifier is configured with different types of semiconductor substrates. The thermal conductivity of the semiconductor substrate B of the main amplifier is κ Ｂand the thermal conductivity of the semiconductor substrate C of the auxiliary amplifier is κ Ｃ The semiconductor substrates B and C are κ Ｂ >κ Ｃ In Figure 10B, the combination of (B, C) = (SiC, Si) is a combination that balances performance and cost. Generally, the better the thermal conductivity, the higher the cost, so the substrate material can be selected based on the required performance and cost depending on the application.

[0089] As described above, the Doherty amplifier according to the present disclosure is a Doherty amplifier having a main amplifier and an auxiliary amplifier, wherein the main amplifier and the auxiliary amplifier are constituted by transistors each formed with different epitaxial stacks, and the transistors forming the main amplifier and the transistors forming the auxiliary amplifier are of the same size, and the epitaxial stack forming the transistor with the higher gain when operated in class C constitutes the auxiliary amplifier. In other words, the main amplifier and the auxiliary amplifier of the Doherty amplifier are each formed with different epitaxial stacks, transistors of the same size are formed on different epitaxial stacks, and the epitaxial stack forming the transistor with the higher gain when the transistors are operated in class C is used for the auxiliary amplifier.

[0090] This makes it possible to obtain an auxiliary amplifier with excellent high gain and high output performance in class C operation and a main amplifier with excellent high efficiency and low distortion performance in class AB operation without any trade-off, and the Doherty amplifier as a whole achieves high efficiency and low distortion characteristics.

[0091] Each of the different epitaxial stacks may include a semiconductor substrate, a channel layer containing a Group III nitride provided above the semiconductor substrate, an AlN layer provided above the channel layer, and a barrier layer containing a Group III nitride provided above the AlN layer, and the AlN layer constituting the auxiliary amplifier may have a thickness greater than the thickness of the AlN layer constituting the main amplifier.

[0092] Furthermore, the channel layer may be made of GaN, and the barrier layer may be made of Al. Ｘ Ga １－Ｘ N (0<x<1), the thickness of the AlN layer constituting the main amplifier may be zero, the thermal conductivity of the semiconductor substrate constituting the auxiliary amplifier may be lower than the thermal conductivity of the semiconductor substrate constituting the main amplifier, the semiconductor substrate constituting the auxiliary amplifier may be a Si substrate, or the semiconductor substrate constituting the main amplifier may be a SiC substrate.

[0093] Furthermore, various modifications, substitutions, additions, omissions, etc. can be made to the above-described embodiments within the scope of the claims or their equivalents.

[0094] The present disclosure can be used, for example, in a power amplifier for high-output or high-frequency applications, a wireless communication base station or terminal device in which the power amplifier is used, or a wireless power supply device that transmits power using microwaves.

[0095] 1, 631 Main amplifier 2, 632 Auxiliary amplifier 3 Power divider 4 Power combiner 5 Impedance conversion circuit 6 Phase adjustment circuit 7 Signal input section 8 Amplified signal combined output section 2-1-M Output characteristics of main amplifier 2-1-A Output characteristics of auxiliary amplifier 2-2-M Gain characteristics of main amplifier 2-2-A Gain characteristics of auxiliary amplifier 2-3-M Portion of combined amplifier output characteristics mainly contributed by main amplifier 2-3-A Portion of combined amplifier output characteristics mainly contributed by auxiliary amplifier 2-4-M Portion of combined amplifier gain characteristics mainly contributed by main amplifier 2-4-A Portion of combined amplifier gain characteristics mainly contributed by auxiliary amplifier PinS Input power at gain compression point of main amplifier PoutS Output power corresponding to PinS 401, 501, 611, 621, A, B, C Semiconductor substrate (Substrate) 402, 502, 612, 622, 1012, 1022, 1112, 1122 Buffer layer (Buffer) 403, 503, 613, 623, 1013, 1023, 1113, 1123 GaN channel layer (Channel) 404, 504, 614, 624, 1014, 1024, 1114, 1124 Barrier layer (Barrier) 405, 505, 615, 625, 1015, 1025, 1115, 1125 AlN layer (AlN layer) 406, 506, 616, 626, 1016, 1026, 1116, 1126 2DEG 407, 507, 617, 627, 1017, 1027, 1117, 1127 Cap layer (Cap) D, D １ , D ２ , D Ｍａｉｎ , D ＡｕｘThickness of AlN layer TOP Indicates the upper layer direction of the epitaxial laminated body Bottom Indicates the lower layer direction of the epitaxial laminated body 511 Source electrode 512 Drain electrode 513 Gate electrode 513L Lower part of gate electrode 513U Upper part of gate electrode 513a Junction part of gate electrode and epitaxial laminated body 514 Source field plate 521 First insulating layer (insulating layer) 522 Second insulating layer (insulating layer) 520 Insulating film Lg Gate length Lgs Gate-source distance Lgd Gate-drain distance

Claims

1. A Doherty amplifier having a main amplifier and an auxiliary amplifier, wherein the main amplifier and the auxiliary amplifier are composed of transistors each formed with a different epitaxial laminate, and the transistors forming the main amplifier and the auxiliary amplifier, among the different epitaxial laminates, are made the same size, and the epitaxial laminate forming the transistor with the higher gain when operated in class C constitutes the auxiliary amplifier.

2. The Doherty amplifier according to claim 1, wherein each of the different epitaxial stacks comprises a semiconductor substrate, a channel layer containing a Group III nitride provided above the semiconductor substrate, an AlN layer provided above the channel layer, and a barrier layer containing a Group III nitride provided above the AlN layer, and the AlN layer constituting the auxiliary amplifier has a thickness greater than the thickness of the AlN layer constituting the main amplifier.

3. The Doherty amplifier of claim 2, wherein the channel layer is made of GaN.

4. The barrier layer is Al Ｘ Ga １－Ｘ 3. The Doherty amplifier of claim 2, wherein N, 0<x<1.

5. The Doherty amplifier according to claim 2, wherein the thickness of the AlN layer constituting the main amplifier is zero.

6. The Doherty amplifier according to claim 2, wherein the thermal conductivity of the semiconductor substrate constituting the auxiliary amplifier is lower than the thermal conductivity of the semiconductor substrate constituting the main amplifier.

7. The Doherty amplifier according to claim 6, wherein the semiconductor substrate forming the auxiliary amplifier is a Si substrate.

8. The Doherty amplifier according to claim 6, wherein the semiconductor substrate constituting the main amplifier is a SiC substrate.

Images