Diamond semiconductor device and method for manufacturing diamond semiconductor device

Abstract

Provided is a diamond semiconductor device which has a trench part and a mesa part on a front surface. The diamond semiconductor device may comprise: a diamond layer; an epitaxial layer of diamond, which is provided on the diamond layer; a front surface-side insulating film which is provided above the epitaxial layer; a front surface-side electrode which is provided on the front surface-side insulating film; a gate pad which is provided above the diamond layer; and a source pad which is provided above the diamond layer and covers the upper part of the trench part and the upper part of the mesa part. The front surface-side electrode may be a gate electrode which is electrically connected to the gate pad, or a source electrode which is electrically connected to the source pad. The epitaxial layer may be provided along the inner wall of a trench in the trench part. A recess part of the trench part, which is constituted by the inner wall of the epitaxial layer, may be filled with at least one of the front surface-side insulating film and the front surface-side electrode.

Description

Diamond semiconductor device and method for manufacturing diamond semiconductor device

[0001] The present invention relates to a diamond semiconductor device and a method for manufacturing a diamond semiconductor device.

[0002] Patent Document 1 discloses a diamond semiconductor device having a trench structure. [Prior art documents] [Patent documents] Patent Document 1: JP 2017-092398 A (general disclosure)

[0003] (Problem to be solved) It is desirable to highly integrate diamond semiconductor devices. (Means for solving the problem)

[0004] A first aspect of the present invention provides a diamond semiconductor device having a trench portion and a mesa portion on its front surface. The diamond semiconductor device may include a diamond layer, a diamond epitaxial layer provided on the diamond layer, a front-side insulating film provided above the epitaxial layer, a front-side electrode provided on the front-side insulating film, a gate pad provided above the diamond layer, and a source pad provided above the diamond layer and covering the trench portion and the mesa portion. The front-side electrode may be a gate electrode electrically connected to the gate pad or a source electrode electrically connected to the source pad. The epitaxial layer may be provided along the inner wall of the trench. The recess of the trench portion defined by the inner wall of the epitaxial layer may be filled with at least one of the front-side insulating film or the front-side electrode.

[0005] A second aspect of the present invention provides a method for manufacturing a diamond semiconductor device having a trench portion and a mesa portion on its front surface. The method for manufacturing a diamond semiconductor device may include the steps of forming an epitaxial layer of diamond on a diamond layer, forming a front-side insulating film above the epitaxial layer, forming a front-side electrode on the front-side insulating film, forming a gate pad above the diamond layer, and forming a source pad above the diamond layer to cover the trench portion and the mesa portion. The step of forming the front-side electrode may include forming a gate electrode electrically connected to the gate pad or forming a source electrode electrically connected to the source pad. The epitaxial layer may be provided along the inner wall of the trench. The recess of the trench portion defined by the inner wall of the epitaxial layer may be filled with at least one of the front-side insulating film or the front-side electrode.

[0006] The above summary of the invention does not list all of the features of the present invention, and subcombinations of these features may also be inventions.

[0007] 1A shows an example of the configuration of the diamond semiconductor device 100. 1A shows an example of a top view of the diamond semiconductor device 100. 1A shows an example of a top view and a cross-sectional view of the diamond semiconductor device 100. 1A shows a modified configuration of the diamond semiconductor device 100. 1A shows a modified configuration of the diamond semiconductor device 100. 1A shows a modified configuration of the diamond semiconductor device 100. 1A shows a modified top view and a cross-sectional view of the diamond semiconductor device 100. 1A shows a modified configuration of the diamond semiconductor device 100. 1A shows an example of a top view of the diamond semiconductor device 100. 1A shows a modified top view of the diamond semiconductor device 100. 1A shows a flowchart of a method for manufacturing the diamond semiconductor device 100 of FIG. 1A. 1A shows an example of a method for manufacturing the diamond semiconductor device 100 of FIG. 1A. 1A shows an example of a method for manufacturing the diamond semiconductor device 100 of FIG. 1A. 1A shows an example of a method for manufacturing the diamond semiconductor device 100 of FIG. 1A. 1A shows an example of a method for manufacturing the diamond semiconductor device 100 of FIG. 2. An example of a method for manufacturing the diamond semiconductor device 100 of Figure 2 is shown. An example of a method for manufacturing the diamond semiconductor device 100 of Figure 2 is shown. A flowchart of a method for manufacturing the diamond semiconductor device 100 of Figure 3 is shown. An example of a method for manufacturing the diamond semiconductor device 100 of Figure 3 is shown. A flowchart of a method for manufacturing the diamond semiconductor device 100 of Figure 4A is shown. An example ... A flowchart of a method for manufacturing the diamond semiconductor device 100 of Figure 5 is shown. An example of a method for manufacturing the diamond semiconductor device 100 of Figure 5 is shown. An example of a method for manufacturing the diamond semiconductor device 100 of Figure 5 is shown. An example of a method for manufacturing the diamond semiconductor device 100 of Figure 5 is shown. An example of a method for manufacturing the diamond semiconductor device 100 of Figure 5 is shown. An example of a method for manufacturing the diamond semiconductor device 100 of Figure 5 is shown.6 shows an example of a method for manufacturing the diamond semiconductor device 100 of Fig. 5. An outline of the configuration of a semiconductor module 200 is shown.

[0008] The present invention will be described below through embodiments of the invention, but the following embodiments do not limit the scope of the invention as claimed. Furthermore, not all of the combinations of features described in the embodiments are necessarily essential to the solution of the invention.

[0009] 1A shows an example of the configuration of a diamond semiconductor device 100. The diamond semiconductor device 100 of this example has a trench portion 50 and a mesa portion 152 on the front surface 11. The diamond semiconductor device 100 of this example has a plurality of unit structures 80, each including a trench portion 50 and a mesa portion 152. The diamond semiconductor device 100 is an example of a semiconductor device that functions as a MOSFET (metal oxide semiconductor field effect transistor). The diamond semiconductor device 100 has a diamond layer 15. The diamond layer 15 has a diamond substrate 10 and a doped region 20. The diamond layer 15 has the diamond substrate 10 on the back surface 12 side, and the doped region 20 on the front surface 11 side.

[0010] The diamond substrate 10 is a P-type substrate made of diamond. The doping concentration of the diamond substrate 10 is 3×10 １９ cm －３ That's it, 1 x 10 ２１ cm －３ The diamond substrate 10 may be of the following type. The diamond substrate 10 may contain a P-type dopant. In one example, the P-type dopant is a Group III element such as boron (B), aluminum (Al), or gallium (Ga). The diamond substrate 10 in this example is P+ type, but is not limited to this. The diamond semiconductor device 100 in this example has a gate structure on the front surface 11 side.

[0011] In this specification, one side in a direction parallel to the depth direction of the diamond substrate 10 is referred to as "upper" and the other side as "lower." Of the two main surfaces of a substrate, layer, or other member, one surface is referred to as the upper surface, and the other surface is referred to as the lower surface. The directions of "upper," "lower," "front," and "back" are not limited to the direction of gravity or the direction of attachment to a substrate or the like when mounting a semiconductor device.

[0012] In this specification, technical matters may be explained using orthogonal coordinate axes of the X-axis, Y-axis, and Z-axis. In this specification, the axes parallel to the upper and lower surfaces of the diamond substrate 10 are defined as the X-axis and Y-axis. Furthermore, the axis perpendicular to the upper and lower surfaces of the diamond substrate 10 is defined as the Z-axis. The Z-axis direction is the depth direction of the diamond substrate 10. In this specification, a top view refers to a viewpoint seen from the positive side to the negative side in the Z-axis direction.

[0013] In this specification, the doping concentration of a dopant may refer to the concentration of a dopant that is intentionally introduced. That is, the doping concentration of a dopant does not necessarily include the doping concentration of unintentionally remaining impurities. The dopant may be introduced during epitaxial growth or may be implanted after growth.

[0014] The doped region 20 is provided above the diamond substrate 10. In this example, the doped region 20 contains an N-type dopant. The N-type dopant may be a Group V element such as nitrogen (N), phosphorus (P), arsenic (As), or antimony (Sb). In this example, the N-type dopant is nitrogen. The doping concentration of the N-type dopant in the doped region 20 is 1×10 １５ cm －３ That's it, 1 x 10 ２３ cm －３ It may be the following:

[0015] The doped region 20 may be a region epitaxially grown on the diamond substrate 10. The doped region 20 may be formed by microwave plasma chemical vapor deposition (MPCVD). The N-type dopant may be introduced during epitaxial growth or by other methods such as ion implantation after epitaxial growth of an undoped diamond layer.

[0016] In this example, the doped region 20 includes a first region 21 and a second region 22. The doped region 20 may include a region containing a P-type dopant. In this example, the first region 21 contains a P-type dopant.

[0017] The first region 21 is provided above the diamond substrate 10. In this example, the first region 21 is provided in contact with the upper surface of the diamond substrate 10. In this example, the first region 21 contains a P-type dopant. In this example, the first region 21 is P-type, but is not limited to this. The doping concentration of the P-type dopant in the first region 21 is 1×10 １６ cm －３ That's it, 1 x 10 ２１ cm －３ The thickness of the first region 21 may be thinner than the thickness of the diamond substrate 10. The thickness of the first region 21 may be thicker than the thickness of the second region 22.

[0018] The first region 21 is a P-type region in contact with the epitaxial layer 30. The first region 21 may be in contact with the epitaxial layer 30 provided on the sidewall of the trench portion 50, or may be in contact with the epitaxial layer 30 provided on the bottom surface of the trench portion 50. The upper end of the first region 21 may be provided above the bottom surface of the trench portion 50. The lower end of the first region 21 may be provided below or above the bottom surface of the trench portion 50. In the diamond semiconductor device 100 of this example, the lower end of the first region 21 is provided above the bottom surface of the trench portion 50.

[0019] The second region 22 is provided above the diamond substrate 10. In this example, the second region 22 is provided in contact with the upper surface of the first region 21. In this example, the second region 22 contains an N-type dopant. The doping concentration of the N-type dopant in the second region 22 is 1×10 １５ cm －３ That's it, 1 x 10 ２１ cm －３ or less. The doping concentration of the N-type dopant in the second region 22 may have a concentration gradient in the depth direction of the diamond semiconductor device 100. The second region 22 may include two or more layers having different doping concentrations of the N-type dopant. The thickness of the second region 22 may be thinner than the thickness of the diamond substrate 10 and may be thinner than the thickness of the first region 21. The doping concentration and thickness of the N-type dopant in the second region 22 may be determined taking into account the withstand voltage of the diamond semiconductor device 100. By providing the second region 22 of the first conductivity type, it becomes easier to suppress leakage current in the off state.

[0020] The epitaxial layer 30 is provided on the diamond layer 15. In this example, the epitaxial layer 30 is provided on the doped region 20, but it may also be provided on the diamond substrate 10. The epitaxial layer 30 is made of diamond. The epitaxial layer 30 may be formed after a trench T is formed in the doped region 20 to provide the trench portion 50. The epitaxial layer 30 is provided along the inner wall of the trench T in the trench portion 50. The epitaxial layer 30 contacts the diamond substrate 10 at the bottom of the trench T, but may also contact the first region 21. In this specification, the trench T may be a depression formed by etching the diamond layer 15. The sidewalls and bottom surface of the trench T may be made of the diamond layer 15.

[0021] The thickness of the epitaxial layer 30 may be 10 nm or more and less than 200 nm. The thickness of the epitaxial layer 30 may be 10 nm or more and 100 nm or less. The thickness of the epitaxial layer 30 may be 30 nm or more and 100 nm or less. By reducing the thickness of the epitaxial layer 30, the distance that holes penetrate through the epitaxial layer 30 when the diamond semiconductor device 100 is on is shortened, and the on-resistance can be reduced.

[0022] The epitaxial layer 30 may include an N-type dopant. The N-type dopant may be nitrogen. The epitaxial layer 30 may have a lower doping concentration of the N-type dopant than the doped region 20. The doping concentration of the N-type dopant in the epitaxial layer 30 may be 1×10 １３ cm －３ That's it, 1 x 10 １６ cm －３ By reducing the doping concentration of the N-type dopant in the epitaxial layer 30, when holes from the termination layer 40 flow into the epitaxial layer 30 and then pass through the epitaxial layer 30 to the diamond substrate 10, the potential barrier in the epitaxial layer 30 becomes smaller, thereby reducing the on-resistance.

[0023] The epitaxial layer 30 may contain a P-type dopant. The doping concentration of the P-type dopant in the epitaxial layer 30 may be set to a range that allows the gate to be turned on and off. In one example, the doping concentration of the P-type dopant in the epitaxial layer 30 is 1×10 １５ cm －３ That's it, 1 x 10 １９ cm －３ The epitaxial layer 30 in this example includes a termination layer 40 .

[0024] The termination layer 40 is provided on the surface of the epitaxial layer 30. In this example, the termination layer 40 is provided between the epitaxial layer 30 and the gate insulating film 170. The termination layer 40 may be a layer that induces a two-dimensional hole gas (2DHG) in the epitaxial layer 30. The termination layer 40 may be a layer that has almost no conductivity when no gate voltage is applied, in order to achieve normally-off characteristics. The thickness of the termination layer 40 may be 20 nm or less, or 0.1 nm or more.

[0025] Termination layer 40 may be a hydrogen-terminated layer, a silicon oxide-terminated layer, or may include both a hydrogen-terminated region and a silicon oxide-terminated region. Termination layer 40 may be hydrogen-terminated by hydrogen radical irradiation, or may be silicon oxide-terminated by a reduction reaction of silicon dioxide and diamond in a high-temperature atmosphere.

[0026] The termination layer 40 includes a C-H bond, a C-O bond, a C-Si bond, a C-Si-O bond, a C-F bond, a C-OH bond, a C-N bond, or a C-NH bond. ２ The termination layer 40 may have at least one of the following bonds. The termination layer 40 may have the same bonds throughout the entire region of the termination layer 40, or different bonds in different regions. The termination layer 40 may have the same bonds over the entire surface between the epitaxial layer 30 and the gate insulating film 170. The termination layer 40 may have C—H bonds over the entire surface between the epitaxial layer 30 and the gate insulating film 170.

[0027] The front surface-side insulating film 70 is provided above the epitaxial layer 30. The front surface-side insulating film 70 is provided on the front surface 11 side of the diamond layer 15. The front surface-side insulating film 70 may be provided on the termination layer 40. The front surface-side insulating film 70 may be provided on the sidewalls and bottom surface of the recess 55 formed by the inner wall of the epitaxial layer 30 in the trench T of the trench portion 50. The thickness of the front surface-side insulating film 70 may be 50 nm or more and 200 nm or less. The thickness of the front surface-side insulating film 70 may be 50 nm or more and 100 nm or less. The thickness of the front surface-side insulating film 70 is, for example, 100 nm.

[0028] The front surface insulating film 70 is made of aluminum oxide (Al ２ O ３ ), silicon oxide (SiO ２ ), silicon nitride (SiNx), hafnium oxide (HfO ２ ), hafnium silicate (HfSiO ４ ) or boron nitride (BN). ２ O ３ The composition of the insulating film 70 does not necessarily have to be Al:O=2:3. The insulating film 70 may be a single layer or may have a layered structure in which different materials are layered. The insulating film 70 of this example includes a gate insulating film 170 and an interlayer insulating film 270.

[0029] The gate insulating film 170 is provided in contact with the recess 55 formed in the epitaxial layer 30 in the trench T of the trench portion 50. The gate insulating film 170 may be provided above the mesa portion 152. The gate insulating film 170 of this example is provided above the trench portion 50, the source contact layer 60, and the source electrode 120. The front gate insulating film 170 of this example is a single layer of Al formed by atomic layer deposition (ALD). ２ O ３ is.

[0030] The interlayer insulating film 270 is provided above the trench portion 50 and the mesa portion 152. The interlayer insulating film 270 insulates the gate electrode 110, to which a gate potential is applied, from the source electrode 120, to which a source potential is applied. The interlayer insulating film 270 in this example includes a first insulating portion 271 and a second insulating portion 272. However, the second insulating portion 272 may be omitted.

[0031] The material of the gate insulating film 170 may be the same as or different from the material of the interlayer insulating film 270. In this example, the material of the gate insulating film 170 is the same as the material of the interlayer insulating film 270. For example, the material of the gate insulating film 170 and the interlayer insulating film 270 is Al. ２ O ３ If there are dangling bonds on the surface of the epitaxial layer 30, electrons are trapped. ２ O ３By bonding with the dangling bonds, electron trapping can be suppressed, thereby improving the conductivity of the termination layer 40 .

[0032] The material of the gate insulating film 170 is SiO ２ , SiNx, HfO ２ , HfSiO ４ or BN, and the material of the interlayer insulating film 270 is Al ２ O ３ , SiO ２ The material of the gate insulating film 170 may include at least one of Al, SiNx, and AlN. ２ O ３ , SiO ２ , SiNx, HfO ２ , HfSiO ４ or BN, and the material of the interlayer insulating film 270 is Al ２ O ３ , SiO ２ Alternatively, it may contain at least one of SiNx.

[0033] The trench portion 50 is provided so as to extend in the depth direction of the diamond layer 15. The trench portion 50 is provided inside a trench T formed by the sidewalls and bottom of a depression formed by etching the diamond layer 15. The trench portion 50 includes an epitaxial layer 30, a termination layer 40, a front surface side electrode 150, and a front surface side insulating film 70 provided inside the trench T. The termination layer 40 may be omitted. The lower end of the trench portion 50 may be deeper than the lower end of the first region 21. That is, the trench portion 50 may extend through the first region 21 to the inside of the diamond substrate 10. The lower end of the trench portion 50 may be shallower than the lower end of the first region 21.

[0034] The trench width of the trench portion 50 may be 100 nm or more and 1.5 μm or less. The trench width of the trench portion 50 may be the width of the trench portion 50 at the upper end of the trench portion 50. In this example, the upper end of the trench portion 50 is the same height as the front surface 11. The depth of the trench T may be 60 nm or more and 20 μm or less. The aspect ratio of the trench portion 50 may be 2 or more and 10 or less.

[0035] The bottom surface of the trench portion 50 may be in contact with the diamond substrate 10. The entire bottom surface of the trench portion 50 may be in contact with the diamond substrate 10, or only a portion of the bottom surface of the trench portion 50 may be in contact with the diamond substrate 10. The sidewall of the trench portion 50 may be in contact with the diamond substrate 10.

[0036] The recess 55 of the trench portion 50 is formed by the inner wall of the epitaxial layer 30. When the termination layer 40 is formed, the recess 55 of the trench portion 50 may be formed by the inner wall of the termination layer 40. The recess 55 of the trench portion 50 is filled with at least one of the front surface side insulating film 70 or the front surface side electrode 150. In this example, the recess 55 is filled with the front surface side insulating film 70 and the front surface side electrode 150. As an example, the recess 55 is filled with the gate insulating film 170, the gate electrode 110, and the interlayer insulating film 270.

[0037] The source contact layer 60 is provided above the epitaxial layer 30. The source contact layer 60 may be provided in contact with the source electrode 120. The source contact layer 60 is provided in contact with the lower surface of the source electrode 120.

[0038] The source contact layer 60 may contain a P-type dopant. In this example, the source contact layer 60 is P+ type, but is not limited to this. The doping concentration of the source contact layer 60 in this example may be the same as or different from the doping concentration of the diamond substrate 10. The doping concentration of the source contact layer 60 may be higher or lower than the doping concentration of the diamond substrate 10. The P-type dopant may be a Group III element such as boron (B), aluminum (Al), or gallium (Ga). The P-type dopant may be introduced during epitaxial growth, or may be introduced by other methods such as ion implantation after epitaxial growth of an undoped diamond layer.

[0039] The thickness of the source contact layer 60 may be greater than the thickness of the epitaxial layer 30. The thickness of the source contact layer 60 may be less than the thickness of the epitaxial layer 30.

[0040] The front surface side electrode 150 is provided on the front surface side insulating film 70. In this example, the front surface side electrode is a gate electrode 110 electrically connected to a gate pad 115 or a source electrode 120 electrically connected to a source pad 125. The gate pad 115 will be described later.

[0041] The gate electrode 110 is provided above the diamond layer 15. In this example, the gate electrode 110 is provided on the gate insulating film 170. At least a portion of the gate electrode 110 may be provided inside the trench portion 50. At least a portion of the gate electrode 110 may be located above the source electrode 120. This allows the channel length to be longer than when a portion of the gate electrode 110 is not located above the source electrode 120, facilitating miniaturization without deteriorating the on / off ratio of the diamond semiconductor device 100. Furthermore, when at least a portion of the gate electrode 110 is provided above the source electrode 120, the source electrode 120 is formed before the gate insulating film 170 is formed. This does not limit the temperature due to the gate insulating film 170, allowing annealing at an optimal temperature for the source electrode 120 and reducing contact resistance. The gate electrode 110 may have any electrode material, such as aluminum (Al). In this example, the gate electrode 110 includes a first gate electrode portion 111 and a second gate electrode portion 112.

[0042] The first gate electrode portion 111 is provided on the gate insulating film 170. The first gate electrode portion 111 may be provided so that at least a portion thereof is located above the source electrode 120. The second gate electrode portion 112 is provided on the first gate electrode portion 111. The second gate electrode portion 112 may be provided so that at least a portion thereof is located on the first insulating portion 271. The second gate electrode portion 112 may electrically connect the first gate electrode portion 111 and the gate pad 115. The first gate electrode portion 111 and the second gate electrode portion 112 may be formed of the same material or different materials.

[0043] The gate electrode 110 may extend from above one sidewall of the trench portion 50 to above the other sidewall, and may be provided so as to cover the upper part of the gate insulating film 170. The gate electrode 110 may be provided so as to cover the entire upper surface of the trench portion 50, or may be provided so as to cover a part of the upper surface of the trench portion 50.

[0044] The source electrode 120 is provided above the diamond layer 15. The source electrode 120 may be provided on the front surface 11 side of the diamond layer 15. The source electrode 120 may be provided on the source contact layer 60. The source electrode 120 may be provided in the same region as the source contact layer 60 when viewed from above, or may be provided inside the source contact layer 60. The source electrode 120 may be a laminated film formed by laminating titanium (Ti) and gold (Au). The source electrode 120 may be a laminated film formed by laminating titanium (Ti), platinum (Pt), and gold (Au). A source voltage may be applied to the source electrode 120 provided on the front surface 11 side of the diamond layer 15.

[0045] The source pad 125 is provided above the diamond layer 15. The source pad 125 is provided so as to cover the trench portion 50 and the mesa portion 152. The source pad 125 is electrically connected to the source electrode 120 using a plurality of contact holes 56.

[0046] The back surface electrode 130 is provided in contact with the diamond substrate 10. The back surface electrode 130 in this example functions as a drain electrode. The back surface electrode 130 is provided on the back surface 12 side of the diamond layer 15. The back surface electrode 130 may be provided on the entire back surface 12, or on a part of the back surface 12. The back surface electrode 130 may be a laminated film formed by laminating titanium (Ti) and gold (Au). The back surface electrode 130 may be a laminated film formed by laminating titanium (Ti), platinum (Pt), and gold (Au). The back surface electrode 130 is provided in contact with the back surface 12 of the diamond substrate 10. A drain-source voltage may be applied to the back surface electrode 130 provided on the back surface 12 side of the diamond layer 15.

[0047] Diamond semiconductor device 100 of this example has gate electrode 110 and source electrode 120 on the front surface 11 side of diamond layer 15, and has back surface electrode 130 on the back surface 12 side of diamond layer 15. When diamond semiconductor device 100 is turned on, current flows from source electrode 120 to source contact layer 60 and termination layer 40 in this order, and holes pass through epitaxial layer 30 and move into diamond substrate 10, causing current to flow to back surface electrode 130.

[0048] In this example, the case where the diamond semiconductor device 100 is a P-type channel field effect transistor has been described, but the diamond semiconductor device 100 may be an N-type channel field effect transistor. When the diamond semiconductor device 100 functions as an N-type channel field effect transistor, the P-type dopant may be replaced with an N-type dopant, and the N-type dopant may be replaced with a P-type dopant.

[0049] Fig. 1B shows an example of a top view of the diamond semiconductor device 100. Fig. 1B shows positions where the gate electrode 110, gate pad 115, and source pad 125 are formed in the top view. In the top view, the region where the gate electrode 110 and gate pad 115 are formed and the region where the source pad 125 is formed are hatched differently. In the region where both the gate electrode 110 or gate pad 115 and the source pad 125 are provided, both hatchings are used.

[0050] The gate pad 115 is provided above the diamond layer 15. The gate pad 115 is formed with at least a portion exposed on the upper surface of the diamond semiconductor device 100. The gate pad 115 may be provided in a region outside the region in which a plurality of unit structures 80 are repeatedly provided in the diamond semiconductor device 100. In this example, the gate pad 115 is provided at the end in the positive direction of the Y-axis. The gate pad 115 may be electrically connected to a configuration provided outside the diamond semiconductor device 100, and a gate voltage may be applied to the gate pad 115.

[0051] The gate electrode 110 includes a first gate electrode portion 111 and a second gate electrode portion 112. The first gate electrode portion 111 in this example is provided so as to overlap the region in which the trench portion 50 is provided in a top view. The second gate electrode portion 112 in this example extends in the Y-axis direction from below the gate pad 115 and is provided to a region that overlaps the region in which the first gate electrode portion 111 is provided in a top view. The arrangement of the gate pad 115 and the gate electrode 110 is not limited thereto. When the gate pad 115 is provided at the end of the diamond semiconductor device 100 on the X-axis side, the second gate electrode portion 112 may be provided so as to extend in the X-axis direction. Alternatively, the second gate electrode portion 112 may be omitted, and the first gate electrode portion 111 may be provided so as to extend below the gate pad 115.

[0052] The source pad 125 covers the upper parts of the unit features 80. When viewed from above, the source pad 125 is formed in both the region where the trench portion 50 is provided and the region where the mesa portion 152 is provided. When viewed from above, the source pad 125 may be provided in a region overlapping with the gate electrode 110. The source pad 125 is electrically insulated from the gate electrode 110 and the gate pad 115 by the front surface-side insulating film 70.

[0053] 1C shows an example of a top view and a cross-sectional view of the diamond semiconductor device 100. In the diamond semiconductor device 100 of this example, the outer periphery of the trench portion 50 is surrounded by the mesa portion 152 when viewed from above. That is, the diamond semiconductor device 100 may include a trench portion 50 surrounded on its periphery by the source electrode 120. The diamond semiconductor device 100 of this example includes a plurality of square unit structures 80, each of which has the outer periphery of the trench portion 50 surrounded by the mesa portion 152. In the top view, only representative components such as the trench portion 50 and the source electrode 120 are shown, and other components are omitted.

[0054] The source electrode 120 has a ring-shaped configuration in top view. The source electrode 120 in this example has a square ring shape. That is, both the outer and inner peripheries of the source electrode 120 are square in top view. However, the shape of the source electrode 120 may be a ring-shaped configuration of other shapes, such as a rectangle, a polygon, a circle, or an ellipse, in top view. If the shape of the source electrode 120 has corners, the vertices of the corners may be rounded. For example, the polygonal source electrode 120 may be a polygon with rounded vertices.

[0055] The pitch Pt indicates the repeat pitch of the trench portions 50 in the diamond semiconductor device 100. The pitch Pt may be the distance from the center of one trench portion 50 to the center of an adjacent trench portion 50. The pitch Pt may be 1 μm or more and 15 μm or less. The multiple trench portions 50 may be arranged at equal intervals in each of the X-axis direction and the Y-axis direction. The diamond semiconductor device 100 of this example has the same pitch Pt in the X-axis direction and the Y-axis direction, but may have different pitches Pt in the X-axis direction and the Y-axis direction. The multiple trench portions 50 may be arranged in an oblique direction at any angle. The multiple trench portions 50 of this example are arranged periodically, but may also be arranged randomly at any density.

[0056] The trench width Wt may be the width of the trench portion 50 in the repeating direction. The shape of the trench portion 50 in this example is a square with four sides whose lengths are the trench width Wt when viewed from above. The shape of the trench portion 50 may be other shapes, such as a rectangle, a polygon, a circle, or an ellipse, when viewed from above. When the shape of the trench portion 50 has corners, the vertices of the corners may be rounded. For example, a polygonal trench portion 50 may be a polygon with rounded vertices. The trench width Wt may be 50 nm or more and 7.5 μm or less, or 100 nm or more and 1.5 μm or less.

[0057] The pitch Pt and trench width Wt satisfy Pt<2Wt. In this example, the area of ​​the mesa portion 152 relative to the area of ​​the trench portion 50 in a top view is greater than 0 and less than 3. This makes it possible to improve the channel density compared to a diamond semiconductor device 100 having a structure in which a plurality of trench portions 50 extending in one of the X-axis direction or the Y-axis direction are arranged in the other of the X-axis direction or the Y-axis direction.

[0058] The total channel width of the region of the epitaxial layer 30 that functions as a channel is 1×10 －１ mm or more, 1×10 ６ The total channel width of the region of the epitaxial layer 30 that functions as a channel may be 1×10 －１ mm or more, 1×10 ４ mm or less. The diamond semiconductor device 100 has higher heat dissipation efficiency than silicon semiconductor devices and the like, and can increase the total channel width. The region of the epitaxial layer 30 that functions as a channel may be a region in which the electrical conductivity of the termination layer 40 changes when a gate voltage is applied to the gate electrode 110 provided in the trench portion 50. In the diamond semiconductor device 100 of this example, the channel width of the unit structure 80 is the region of the mesa portion 152 adjacent to the trench portion 50, which has a perimeter of 4 × Wch. When the diamond semiconductor device 100 has n unit structures 80, the total channel width of the epitaxial layer 30 may be calculated as 4 × Wch × n.

[0059] The total channel width of the epitaxial layer 30 is not limited to the above example. When the unit structures 80 are provided in a shape other than a square, the channel width of the unit structures 80 may be the perimeter length of the region through which the main current flows in the unit structures 80 when viewed from above. When the diamond semiconductor device 100 includes a plurality of unit structures 80 of different shapes, the total channel width of the epitaxial layer 30 may be the sum of the channel widths of the individual unit structures 80.

[0060] The pitch P80 indicates the repeat pitch of the unit features 80 in the diamond semiconductor device 100. The pitch P80 may be the width of the unit features 80 in the repeat direction. The pitch of the unit features 80 is 5×10－１ μm or more, 5×10 ４ The pitch of the unit features 80 may be 5×10 －１ μm or more, 5×10 ３ It may be less than μm.

[0061] Figure 2 shows a modified example of the diamond semiconductor device 100. The diamond semiconductor device 100 of this example differs from the diamond semiconductor device 100 of Figure 1A in that the lower end of the source electrode 120 is provided within the contact hole 56. That is, in the diamond semiconductor device 100 of this example, the contact hole 56 is not formed above the source electrode 120, but the source electrode 120 is provided inside the contact hole 56 formed in the front surface side insulating film 70. In this example, the differences from the diamond semiconductor device 100 of Figure 1A will be particularly described.

[0062] The source electrode 120 and the source pad 125 are connected within the contact hole 56. In the diamond semiconductor device 100 of this example, the source electrode 120 and the source pad 125 have the same width inside the contact hole 56. If the wall surface of the contact hole 56 is tapered, the width of the upper surface of the source electrode 120 may be the same as the width of the lower surface of the source pad 125 at the interface between the source electrode 120 and the source pad 125. By forming the source electrode 120 inside the contact hole 56 formed in the front surface-side insulating film 70, it is no longer necessary to align the source electrode 120 and the source pad 125 during the manufacture of the diamond semiconductor device 100, making it easier to miniaturize the diamond semiconductor device 100.

[0063] In the diamond semiconductor device 100 of this example, the recess 55 of the trench portion 50 is filled with the front surface side insulating film 70 and the front surface side electrode 150. The recess 55 of this example is filled with the gate insulating film 170 and the gate electrode 110. With this structure, the diamond semiconductor device 100 can be easily integrated.

[0064] Figure 3 is a modified example of the diamond semiconductor device 100. The diamond semiconductor device 100 of this example differs from the diamond semiconductor device 100 of Figure 2 in that the width of the source electrode 120 is larger than the width of the source pad 125 provided in the contact hole 56 above the source electrode 120. That is, at the interface between the source electrode 120 and the source pad 125, the width of the upper surface of the source electrode 120 is larger than the width of the lower surface of the source pad 125. With this structure, the source electrode 120 can be formed at an early stage in the manufacturing process of the diamond semiconductor device 100, so that the source electrode 120 can be annealed at an optimum temperature and contact resistance can be reduced.

[0065] Figure 4A is a modified example of diamond semiconductor device 100. Diamond semiconductor device 100 of this example differs from diamond semiconductor device 100 of Figure 1A in that front surface side electrode 150 is located above front surface 11 and is not provided inside trench portion 50. In this example, differences from diamond semiconductor device 100 of Figure 1A will be particularly described.

[0066] In the diamond semiconductor device 100 of this example, the recess 55 of the trench portion 50 is filled with a front surface side insulating film 70. The recess 55 of this example is filled with a gate insulating film 170. The recess 55 may be filled with a plurality of front surface side insulating films 70. As an example, the front surface side insulating film 70 filled in the recess 55 may be filled with two or more types of insulating films having different dielectric constants.

[0067] The front surface side insulating film 70 filled in the recess 55 is Al ２ O ３ , HfO ２ , HfSiO ４ For example, the front surface side insulating film 70 may include at least one of Al and BN formed by the ALD method. ２ O ３ This allows the resistivity of the termination layer 40 on the trench sidewall to be reduced, for example, when the resistivity of the trench sidewall becomes dominant due to miniaturization of the diamond semiconductor device 100.

[0068] In the diamond semiconductor device 100 of this example, the gate electrode 110 does not have a second gate electrode portion 112. The gate electrode 110 of this example is formed only by a first gate electrode portion 111 provided on a gate insulating film 170. By forming the gate electrode 110 only by the first gate electrode portion 111, the number of processes can be reduced.

[0069] In the diamond semiconductor device 100 of this example, the interlayer insulating film 270 does not have the second insulating portion 272. The interlayer insulating film 270 may have a single-layer structure formed from a single material, which allows the number of steps to be reduced.

[0070] 4B shows an example of a top view and a cross-sectional view of the diamond semiconductor device 100. In the diamond semiconductor device 100 of this example, the outer periphery of the mesa portion 152 is surrounded by the trench portion 50 when viewed from above. That is, the diamond semiconductor device 100 may be provided with a source electrode 120 that is surrounded on its periphery by the trench portion 50. The diamond semiconductor device 100 of this example is provided with a plurality of square unit structures 80, each of which has a mesa portion 152 that is surrounded on its periphery by the trench portion 50. In the top view, only representative components such as the trench portion 50 and the source electrode 120 are shown, and other components are omitted.

[0071] The trench portion 50 has a ring-shaped configuration in top view. In this example, the trench portion 50 has a square ring shape. That is, both the outer and inner peripheries of the trench portion 50 are square in top view. However, the shape of the trench portion 50 may be a ring-shaped configuration of other shapes, such as a rectangle, a polygon, a circle, or an ellipse, in top view. If the trench portion 50 has corners, the vertices of the corners may be rounded. For example, the polygonal trench portion 50 may be a polygon with rounded vertices.

[0072] The pitch Pm indicates the repeat pitch of the mesa portions 152 in the diamond semiconductor device 100. The pitch Pm may be the distance from the center of one mesa portion 152 to the center of an adjacent mesa portion 152. The pitch Pm may be 1 μm or more and 15 μm or less. The multiple mesa portions 152 may be arranged at equal intervals in each of the X-axis direction and the Y-axis direction. The diamond semiconductor device 100 of this example has the same pitch Pm in the X-axis direction and the Y-axis direction, but may have different pitches Pm in the X-axis direction and the Y-axis direction. The multiple mesa portions 152 may be arranged in an oblique direction at any angle. The multiple mesa portions 152 of this example are arranged periodically, but may also be arranged randomly at any density.

[0073] The pitch Pm and the trench width Wt satisfy Pm>2Wt. In this example, the area of ​​the trench portion 50 relative to the area of ​​the mesa portion 152 when viewed from above is greater than 0 and less than 3. This makes it possible to improve the channel density compared to the diamond semiconductor device 100 having a structure in which a plurality of trench portions 50 extending in one of the X-axis direction or the Y-axis direction are arranged in the other of the X-axis direction or the Y-axis direction.

[0074] The total channel width of the region of the epitaxial layer 30 that functions as a channel is 1×10 －１ mm or more, 1×10 ６ The total channel width of the region of the epitaxial layer 30 that functions as a channel may be 1×10 －１ mm or more, 1×10 ４ mm or less. The region of the epitaxial layer 30 that functions as a channel may be a region in which the electrical conductivity of the termination layer 40 changes when a gate voltage is applied to the gate electrode 110 provided in the trench portion 50. In the diamond semiconductor device 100 of this example, the channel width of the unit structure 80 is the region adjacent to the trench portion 50 in the mesa portion 152, which has a perimeter of 4 × Wch. When the diamond semiconductor device 100 has n unit structures 80, the total channel width of the epitaxial layer 30 may be calculated as 4 × Wch × n.

[0075] The pitch P80 indicates the repeat pitch of the unit features 80 in the diamond semiconductor device 100. The pitch P80 may be the width of the unit features 80 in the repeat direction. The pitch of the unit features 80 is 5×10 －１ μm or more, 5×10 ４ The pitch of the unit features 80 may be 5×10 －１ μm or more, 5×10 ３ It may be less than μm.

[0076] Fig. 5 shows a modified example of the diamond semiconductor device 100. Differences from the diamond semiconductor device 100 of Fig. 4A will be described using Fig. 5.

[0077] In the diamond semiconductor device 100 of this example, the gate electrode 110 does not have the second gate electrode portion 112. The gate electrode 110 of this example is provided inside the recess 55 of the trench portion 50. The gate electrode 110 may be provided inside or outside the recess 55. By forming the gate electrode 110 with only the first gate electrode portion 111, the number of processes can be reduced.

[0078] The diamond semiconductor device 100 of this example includes a buried insulating film 370 provided inside the recess 55 of the trench portion 50. The buried insulating film 370 is an example of the front surface-side insulating film 70. The material of the buried insulating film 370 may be the same as or different from the material of the gate insulating film 170. The buried insulating film 370 may be the gate insulating film 170.

[0079] The buried insulating film 370 of this example may be buried in the trench portion 50 so that its upper end is at the same height as the interface between the first region 21 and the second region 22. In the diamond semiconductor device 100 of this example, the position of the lower end of the gate electrode 110 inside the trench portion 50 is adjusted to be the same as the position of the boundary between the first region 21 and the second region 22. This makes it possible to improve the breakdown voltage of the diamond semiconductor device 100.

[0080] In the diamond semiconductor device 100 of this example, the interlayer insulating film 270 does not have the second insulating portion 272. The interlayer insulating film 270 may have a single-layer structure formed from a single material, which allows the number of steps to be reduced.

[0081] Fig. 6 shows a modified example of the diamond semiconductor device 100. Differences from the diamond semiconductor device 100 of Fig. 4A will be described using Fig. 6.

[0082] The gate electrode 110 may be provided both inside and outside the recess 55 of the trench portion 50. In the diamond semiconductor device 100 of this example, the first gate electrode portion 111 of the gate electrode 110 is provided from above one source electrode 120, through the recess 55 of the trench portion 50, to above the other source electrode 120. By providing the gate electrode 110 both inside and outside the recess 55 of the trench portion 50, the channel length can be increased, and miniaturization can be facilitated without deteriorating the on / off ratio of the diamond semiconductor device 100.

[0083] The sidewalls of the trench T in the trench portion 50 in this example are tapered. The trench T is formed with sidewalls inclined at an angle θ from the horizontal direction. The angle θ may be 60° or more, or 90° or less. By tapering the sidewalls of the trench T, the embedding depth of the gate electrode 110 can be adjusted without changing the depth of the trench portion 50. The angle θ may be 90° or more. In other words, the trench T may be formed in a shape that flares out toward the end.

[0084] The angle θ may be adjusted so that the position of the lower end of the gate electrode 110 inside the trench portion 50 is a predetermined position, taking into account the width of the trench portion 50, the thickness of the epitaxial layer 30, and the thickness of the gate insulating film 170. In the diamond semiconductor device 100 of this example, the angle θ is adjusted so that the position of the lower end of the gate electrode 110 inside the trench portion 50 is the same as the position of the boundary between the first region 21 and the second region 22. This can improve the breakdown voltage of the diamond semiconductor device 100. Note that the position of the lower end of the gate electrode 110 inside the trench portion 50 may be adjusted to a predetermined position by changing the width of the trench portion 50, the thickness of the epitaxial layer 30, and the thickness of the gate insulating film 170.

[0085] 7A shows an example of a top view of the diamond semiconductor device 100. This figure shows a top view of the diamond semiconductor device 100 functioning as a MOSFET. In this figure, only representative components such as the trench portion 50 and the source electrode 120 are shown, and other components are omitted.

[0086] The diamond semiconductor device 100 of this example comprises a plurality of trench portions 50 extending in a predetermined extension direction (Y-axis direction). The diamond semiconductor device 100 of this example also comprises a plurality of source electrodes 120 extending in a predetermined extension direction (Y-axis direction). That is, the trench portions 50 and the source electrodes 120 of this example extend in the same direction. The plurality of source electrodes 120 may be electrically connected to a common source pad 125.

[0087] The pitch Pm indicates the repeat pitch of the mesa portions 152 in the diamond semiconductor device 100. The diamond semiconductor device 100 of this example has a plurality of mesa portions 152 repeatedly arranged in a predetermined repeat direction (X-axis direction). The pitch Pm may be the distance from the center of a source electrode 120 to the center of an adjacent source electrode 120.

[0088] The pitch Pt indicates the repeat pitch of the trench portions 50 in the diamond semiconductor device 100. The diamond semiconductor device 100 of this example has a plurality of trench portions 50 repeatedly arranged in a predetermined repeat direction (X-axis direction). The pitch Pt may be the distance from the center of a trench portion 50 to the center of an adjacent trench portion 50.

[0089] The repeat pitch Pm of the mesa portions 152 and the repeat pitch Pt of the trench portions 50 may be the same or different. In the diamond semiconductor device 100 of this example, the pitch Pm and the pitch Pt are the same. The repeat pitch Pm of the mesa portions 152 and the repeat pitch Pt of the trench portions 50 may be changed in accordance with the on-resistance, etc. required for the diamond semiconductor device 100.

[0090] 7B shows a modified top view of the diamond semiconductor device 100. In the diamond semiconductor device 100 of this example, the outer periphery of the trench portion 50 is surrounded by the mesa portion 152 when viewed from above. In other words, the diamond semiconductor device 100 may include a trench portion 50 surrounded on all sides by the source electrode 120. In this figure, only representative components such as the trench portion 50 and the source electrode 120 are shown, and other components are omitted.

[0091] The pitch Pt indicates the repeat pitch of the trench portions 50 in the diamond semiconductor device 100. The pitch Pt may be the distance from the center of a trench portion 50 to the center of an adjacent trench portion 50. The diamond semiconductor device 100 of this example has a plurality of trench portions 50 repeatedly arranged in predetermined directions (the Y-axis direction and a direction tilted 30° clockwise or counterclockwise from the X-axis direction).

[0092] The diamond semiconductor device 100 of this example has a plurality of hexagonal trench portions 50. The plurality of trench portions 50 may be arranged to form a so-called honeycomb structure when viewed from above. That is, the plurality of trench portions 50 may be arranged so that there are six adjacent trench portions 50 for one trench portion 50. By arranging them in this manner, the manufacturing process of the diamond semiconductor device 100 becomes easier than when square trench portions 50 are repeatedly arranged.

[0093] The trench portion 50 has a predetermined width Wt. The width Wt may be the distance between two opposing sides of the trench portion 50, or may be the length of a diagonal line of the trench portion 50. In this example, the width Wt is the distance between the two opposing sides of the trench portion 50.

[0094] The pitch Pt and the trench width Wt satisfy Pt<2Wt. In this example, the ratio of the area of ​​the mesa portion 152 to the area of ​​the trench portion 50 in top view is greater than 0 and less than 3. By forming the multiple trench portions 50 in a hexagonal shape and setting this ratio, even when they are arranged to form a honeycomb structure in top view, the channel density can be improved compared to the modified example shown in FIG. 7A.

[0095] 7C shows a modified top view of the diamond semiconductor device 100. In the diamond semiconductor device 100 of this example, the outer periphery of the mesa portion 152 is surrounded by the trench portion 50 when viewed from above. In other words, the diamond semiconductor device 100 may be provided with a source electrode 120 whose periphery is surrounded by the trench portion 50. In this figure, only representative components such as the trench portion 50 and the source electrode 120 are shown, and other components are omitted.

[0096] The pitch Pm indicates the repeat pitch of the mesa portions 152 in the diamond semiconductor device 100. The pitch Pm may be the distance from the center of a mesa portion 152 to the center of an adjacent mesa portion 152. The diamond semiconductor device 100 of this example has a plurality of mesa portions 152 repeatedly arranged in predetermined directions (the Y-axis direction and directions tilted 30° clockwise or counterclockwise from the X-axis direction).

[0097] The diamond semiconductor device 100 of this example includes a plurality of hexagonal mesa portions 152. In the diamond semiconductor device 100 of this example, the trench portion 50 may be formed so that the plurality of mesa portions 152 are arranged to form a so-called honeycomb structure when viewed from above. That is, the plurality of mesa portions 152 may be arranged so that there are six mesa portions 152 adjacent to one mesa portion 152. By arranging them in this manner, the manufacturing process of the diamond semiconductor device 100 becomes easier than when square mesa portions 152 are arranged repeatedly.

[0098] The trench portion 50 has a predetermined width Wt. In this example, the width Wt is the distance between two opposing sides of the trench portion 50. The pitch Pm and the trench width Wt satisfy Pm > 2Wt. In this example, the area of ​​the trench portion 50 relative to the area of ​​the mesa portion 152 in a top view is greater than 0 and less than 3. By setting this ratio, even when multiple mesa portions 152 are formed in a hexagonal shape and arranged to form a honeycomb structure in a top view, the channel density can be improved compared to the modification shown in FIG. 7A.

[0099] Fig. 8A shows an example of a flow chart of a method for manufacturing a diamond semiconductor device 100. Fig. 8A shows an example of a method for manufacturing a diamond semiconductor device having a trench portion and a mesa portion on the front surface. Fig. 8A shows an example of a method for manufacturing a diamond semiconductor device 100 having the cross section shown in Fig. 1A.

[0100] The method for manufacturing the diamond semiconductor device 100 may include step S100 of forming a diamond layer 15, step S102 of forming a mask 91 on the diamond layer 15, step S104 of forming a trench T in the diamond layer 15, and step S106 of removing the mask 91. The method for manufacturing the diamond semiconductor device 100 of this example includes step S108 of forming a diamond epitaxial layer on the diamond layer.

[0101] The method for manufacturing the diamond semiconductor device 100 may include step S110 of forming a mask 92 on the epitaxial layer 30, step S112 of forming a source contact layer 60 on the epitaxial layer 30, step S114 of removing the mask 92, and step S116 of forming a front surface side electrode 150. The front surface side electrode 150 formed in step S116 may be the source electrode 120.

[0102] The method for manufacturing the diamond semiconductor device 100 of this example includes step S118 of forming a front surface side insulating film 70 above the epitaxial layer 30. The front surface side insulating film 70 formed in step S118 may be the gate insulating film 170.

[0103] The manufacturing method of diamond semiconductor device 100 of this example includes step S120 of forming front surface side electrode 150 on front surface side insulating film 70. In step S120, front surface side insulating film 70 may be gate insulating film 170. In step S120, front surface side electrode 150 may be gate electrode 110 or may be first gate electrode portion 111.

[0104] The method for manufacturing the diamond semiconductor device 100 may include step S122 of etching the front surface side insulating film 70 and the front surface side electrode 150. In step S122, the front surface side insulating film 70 may be the gate insulating film 170. In step S120, the front surface side electrode 150 may be the gate electrode 110 or the first gate electrode portion 111.

[0105] The method for manufacturing the diamond semiconductor device 100 of this example includes step S124 of forming an interlayer insulating film 270 above the front surface 11 of the diamond layer 15. In step S124, the interlayer insulating film 270 may be a first insulating portion 271.

[0106] The manufacturing method of the diamond semiconductor device 100 of this example includes step S126 of forming a gate pad 115 above the diamond layer 15. In step S126, the front surface side electrode 150 may be formed simultaneously with the step of forming the gate pad 115. In one example, in the step of forming the gate pad 115, a second gate electrode portion 112 is formed to electrically connect the gate pad 115 and the first gate electrode portion 111 of the gate electrode 110.

[0107] The method for manufacturing the diamond semiconductor device 100 may include step S128 of forming an interlayer insulating film 270 above the front surface 11 of the diamond layer 15. The interlayer insulating film 270 formed in step S128 may be the second insulating portion 272. Step S128 may be omitted.

[0108] The method for manufacturing the diamond semiconductor device 100 of this example includes step S130 of forming contact holes 56 in the interlayer insulating film 270, and step S132 of forming a source pad 125 above the diamond layer 15 to cover the trench portion 50 and the mesa portion 152. The source pad 125 may be electrically connected to the source contact layer 60 inside the plurality of contact holes 56 formed in step S130.

[0109] 8B shows an example of a method for manufacturing the diamond semiconductor device 100. In step S100, a diamond layer 15 is formed. Step S100 includes preparing a P-type diamond substrate 10 and forming a doped region 20 above the diamond substrate 10. The doped region 20 may be formed by epitaxial growth on the diamond substrate 10 and introducing a dopant. In this example, the first region 21 is formed by introducing a P-type dopant during epitaxial growth. In this example, the second region 22 is formed by introducing an N-type dopant during epitaxial growth. The doped region 20 may be formed by epitaxially growing the first region 21 and then epitaxially growing the second region 22 consecutively. The first region 21 and the second region 22 may be formed to have a concentration gradient by adjusting the amount of dopant during epitaxial growth.

[0110] In step S102, a mask 91 is formed on the diamond layer 15. The mask 91 may be formed over the entire surface of the diamond layer 15 and then selectively etched. A trench T is formed in the area of ​​the diamond layer 15 where the mask 91 is not formed.

[0111] In step S104, trenches T are formed. The trenches T are formed by etching the diamond layer 15. In this example, the trenches T are formed by etching the first region 21, the second region 22, and the diamond substrate 10. After the trenches T are formed, the mask 91 is removed in the subsequent step S106. Through steps S102 to S106, the trenches T are selectively formed in the diamond layer 15.

[0112] Fig. 8C shows an example of a method for manufacturing the diamond semiconductor device 100. This figure shows a process subsequent to step S106 in Fig. 8B.

[0113] After forming the trench T, in step S108, the epitaxial layer 30 is formed. The epitaxial layer 30 may be formed on the diamond layer 15 by epitaxial growth. The epitaxial layer 30 may be formed along the inner wall of the trench T. This forms a recess 55 in the trench portion 50 defined by the inner wall of the epitaxial layer 30. The epitaxial layer 30 may be formed on the upper surface of the second region 22.

[0114] In step S110, a mask 92 is formed on the epitaxial layer 30. The material of the mask 92 may be the same as or different from the material of the mask 91. The mask 92 may be formed over the entire surface of the epitaxial layer 30 and then selectively etched. A source contact layer 60 is formed in the region of the epitaxial layer 30 where the mask 92 is not formed.

[0115] In step S112, a source contact layer 60 is formed. The source contact layer 60 may be formed by epitaxial growth on the epitaxial layer 30. The source contact layer 60 may be P+ type. The source contact layer 60 may also be omitted. After the source contact layer 60 is formed, the mask 92 is removed in the subsequent step S114. Through steps S110 to S114, the source contact layer 60 is selectively formed on the epitaxial layer 30.

[0116] Fig. 8D shows an example of a method for manufacturing the diamond semiconductor device 100. This figure shows a process subsequent to step S114 in Fig. 8C.

[0117] In step S116, a front surface electrode 150 is formed. The front surface electrode 150 formed in step S116 may be the source electrode 120. The source electrode 120 may be selectively formed on the source contact layer 60. The source electrode 120 may be selectively formed on the source contact layer 60 by masking using a mask, or may be selectively formed on the source contact layer 60 by selectively etching the source electrode 120 after its formation. The mask may be a resist mask. The source electrode 120 may be electrically connected to a source pad 125 in a later process.

[0118] In step S116, a termination layer 40 may be formed. The termination layer 40 may be formed after the source electrode 120 is formed. The termination layer 40 may be formed on the epitaxial layer 30 by introducing an optional gas during annealing. The termination layer 40 may be formed by hydrogen terminating the epitaxial layer 30 or by terminating the epitaxial layer 30 with silicon oxide.

[0119] In step S118, a front-side insulating film 70 is formed above the epitaxial layer 30. The front-side insulating film 70 formed in step S118 may be the gate insulating film 170. In this example, the front-side insulating film 70 is formed above the termination layer 40. The front-side insulating film 70 may be formed on the source electrode 120, the source contact layer 60, and the termination layer 40. The front-side insulating film 70 may be formed over the entire surface above the diamond layer 15 in a top view. The front-side insulating film 70 may be formed by a method such as an ALD method or a CVD method. After the front-side insulating film 70 is formed, the interface between the termination layer 40 and the front-side insulating film 70 may be improved by annealing or the like.

[0120] In this example, the termination layer 40 is formed on the epitaxial layer 30 before forming the front-side insulating film 70. However, the termination layer 40 may be formed between the front-side insulating film 70 and the epitaxial layer 30 after the front-side insulating film 70 is formed on the epitaxial layer 30.

[0121] In step S120, a front surface side electrode 150 is formed on the front surface side insulating film 70. The front surface side electrode 150 formed in step S120 may be the gate electrode 110. In this example, the front surface side electrode 150 formed in step S120 is the first gate electrode portion 111 of the gate electrode 110. The gate electrode 110 may be electrically connected to a gate pad 115 in a later process.

[0122] In step S120, the front surface side electrode 150 may be formed on the entire surface of the region where the front surface side insulating film 70 is formed. In step S120, an etch-back process may be performed after the front surface side electrode 150 is formed.

[0123] Fig. 8E shows an example of a method for manufacturing the diamond semiconductor device 100. This figure shows a process subsequent to step S120 in Fig. 8D.

[0124] In step S122, the front surface side insulating film 70 and the front surface side electrode 150 are etched. In step S122, the front surface side insulating film 70 may be the gate insulating film 170, and the front surface side electrode 150 may be the gate electrode 110. In this example, the gate insulating film 170 and the first gate electrode portion 111 of the gate electrode 110 are etched. In step S122, the front surface side insulating film 70 and the front surface side electrode 150 formed on the source electrode 120 are selectively etched.

[0125] In step S124, an interlayer insulating film 270 is formed above the front surface 11. The interlayer insulating film 270 is an example of the front surface-side insulating film 70. The interlayer insulating film 270 formed in step S124 may be a first insulating portion 271.

[0126] The interlayer insulating film 270 may be formed on the front surface side electrode 150. In this example, the interlayer insulating film 270 is formed on the source electrode 120 and the first gate electrode portion 111. The interlayer insulating film 270 may be selectively formed on the front surface side electrode 150 by masking during formation, etching after formation, or the like.

[0127] In step S126, a gate pad 115 is formed above the diamond layer 15. As described above, the gate pad 115 is formed in an area outside the area where the plurality of unit structures 80 are repeatedly formed, and therefore is not shown in the cross section shown in Figure 8E. In step S126 shown in Figure 8E, the second gate electrode portion 112 electrically connected to the gate pad 115 is shown. This allows the gate pad 115 and the gate electrode 110 to be electrically connected.

[0128] Figure 8F shows an example of a method for manufacturing the diamond semiconductor device 100. This figure shows a process subsequent to step S126 in Figure 8E.

[0129] In step S128, an interlayer insulating film 270 is formed above the front surface 11. The interlayer insulating film 270 formed in step S128 may be a second insulating portion 272. The interlayer insulating film 270 may be formed on the front surface side electrode 150 and the already formed interlayer insulating film 270. In this example, the second insulating portion 272 is formed on the second gate electrode portion 112 and the first insulating portion 271.

[0130] By forming the interlayer insulating film 270 in step S128, the recess 55 of the trench portion 50 is filled with at least one of the front surface side insulating film 70 or the front surface side electrode 150. In this example, the recess 55 is filled with both the front surface side insulating film 70 and the front surface side electrode 150. In this example, the recess 55 is filled with the gate insulating film 170, the second insulating portion 272, the first gate electrode portion 111, and the second gate electrode portion 112.

[0131] In step S130, a contact hole 56 is formed in the interlayer insulating film 270. The contact hole 56 may be formed by selective etching using a mask. In this example, the contact hole 56 is selectively formed above the source electrode 120 to expose the top surface of the source electrode 120.

[0132] In step S132, a source pad 125 is formed above the diamond layer 15. The source pad 125 in this example is formed so as to cover the trench portion 50 and the mesa portion 152. The source pad 125 may also be formed inside the contact hole 56. The source pad 125 in this example is formed up to the inside of the plurality of contact holes 56 and is electrically connected to the source electrode 120. After step S132, a back surface electrode 130 is formed, thereby manufacturing the diamond semiconductor device 100 shown in FIG. 1A.

[0133] Figure 9A shows a modified flowchart of the manufacturing method of the diamond semiconductor device 100. To explain the differences from the embodiment of Figure 8A, the last two digits of the numbers of the corresponding steps in Figure 8A correspond to those in Figure 8A. Steps S200 to S214 shown in Figure 9A correspond to steps S100 to S114 described above, so their explanation will be omitted. The flowchart shown in Figure 9A differs from the embodiment of Figure 8A in that step S216 for forming the front surface electrode 150 is performed later than in Figure 8A, and in that it includes steps S221 and S231.

[0134] Figure 9B shows one example of a method for manufacturing the diamond semiconductor device 100. In this example, the description will begin with the step of forming the front surface-side insulating film 70. The steps up to the step of forming the source contact layer 60 may be the same as other manufacturing methods. This method differs from the manufacturing method for the diamond semiconductor device 100 described with reference to Figures 8A to 8F in that after the mask 92 is removed in step S214, the front surface-side insulating film 70 is formed without forming the source electrode 120.

[0135] In step S218, a front surface side insulating film 70 is formed above the epitaxial layer 30. In step S220, a front surface side electrode 150 is formed on the front surface side insulating film 70. The front surface side insulating film 70 formed in step S218 may be the gate insulating film 170. The front surface side electrode 150 formed in step S220 may be the gate electrode 110. In this example, the front surface side electrode 150 formed in step S220 is the first gate electrode portion 111 of the gate electrode 110. Steps S218 and S220 correspond to steps S118 and S120, respectively, and therefore will not be described again.

[0136] In step S221, the front electrode 150 is etched back, thereby removing a portion of the first gate electrode portion 111 of the gate electrode 110 that is formed outside the trench portion 50. In step S221, the etch-back process may be performed using a method such as dry etching.

[0137] Figure 9C shows an example of a method for manufacturing the diamond semiconductor device 100. This figure shows a process subsequent to step S221 in Figure 9B.

[0138] In step S224, an interlayer insulating film 270 is formed above the front surface 11. In step S226, a gate pad 115 is formed above the diamond layer 15. Steps S224 and S226 correspond to steps S124 and S126, respectively, and therefore will not be described further.

[0139] By forming the second gate electrode portion 112 in step S226, the recess 55 of the trench portion 50 is filled with at least one of the front surface side insulating film 70 or the front surface side electrode 150. In this example, the recess 55 is filled with both the front surface side insulating film 70 and the front surface side electrode 150. In this example, the recess 55 is filled with the gate insulating film 170, the first gate electrode portion 111, and the second gate electrode portion 112.

[0140] In step S228, an interlayer insulating film 270 is formed above the front surface 11. The interlayer insulating film 270 formed in step S228 may be a second insulating portion 272. The interlayer insulating film 270 may be formed on the front surface side electrode 150 and the already formed interlayer insulating film 270. In this example, the second insulating portion 272 is formed on the second gate electrode portion 112 and the first insulating portion 271.

[0141] In step S231, contact holes 56 are formed. The contact holes 56 are formed using the same mask. In the manufacturing method of the diamond semiconductor device 100 shown in Figures 8A to 8F, after the gate insulating film 170 of the front surface-side insulating film 70 is etched in step S122, the interlayer insulating film 270 is formed, and the contact holes 56 are formed in step S130, so that the sidewalls of the contact holes 56 are formed only by the interlayer insulating film 270. On the other hand, in step S231 shown in Figure 9C, both the gate insulating film 170 and the interlayer insulating film 270 of the front surface-side insulating film 70 are etched using the same mask, and the contact holes 56 are formed in one step. That is, the sidewalls of the contact holes 56 are formed by both the gate insulating film 170 and the interlayer insulating film 270.

[0142] In the following step S216, the source electrode 120 is formed in the contact hole 56. This eliminates the need for alignment when exposing the top surface of the source electrode 120, making it easier to miniaturize the diamond semiconductor device 100.

[0143] In step S232, a source pad 125 is formed above the diamond layer 15. The source pad 125 may be formed in the contact hole 56. In this example, the source pad 125 is formed up to the inside of the plurality of contact holes 56 and is electrically connected to the source electrode 120. After step S232, a back electrode 130 is formed, thereby manufacturing the diamond semiconductor device 100 shown in FIG.

[0144] Figure 10A shows a modified flowchart of the manufacturing method of the diamond semiconductor device 100. In order to explain the differences from the embodiments of Figures 8A and 9A, the last two digits of the numbers of the steps corresponding to those of Figures 8A and 9A correspond to each other. Steps S300 to S318 shown in Figure 10A correspond to steps S100 to S118, so their explanation will be omitted. The flowchart shown in Figure 10A differs from the embodiment of Figure 9A in that step S316, in which the source electrode 120 is formed, is located earlier than in Figure 9A.

[0145] Figure 10B shows one example of a method for manufacturing diamond semiconductor device 100. In this example, the description will begin with the process of forming gate electrode 110, which is front surface side electrode 150. The process up to the process of forming front surface side insulating film 70 may be the same as other manufacturing methods. This method differs from the manufacturing method for diamond semiconductor device 100 described with reference to Figures 9A to 9C in that source electrode 120 is formed in step S316 before first gate electrode portion 111 of gate electrode 110 is formed in step S320.

[0146] In step S320, a front surface side electrode 150 is formed on the front surface side insulating film 70. The front surface side electrode 150 formed in step S320 may be the gate electrode 110. In this example, the front surface side electrode 150 formed in step S320 is the first gate electrode portion 111 of the gate electrode 110. In step S321, the front surface side electrode 150 is etched back. In step S324, an interlayer insulating film 270 is formed above the front surface 11. In step S326, a gate pad 115 is formed above the diamond layer 15. Steps S320 to S326 correspond to steps S220 to S226, respectively, and therefore will not be described further.

[0147] By forming the second gate electrode portion 112 in step S326, the recess 55 of the trench portion 50 is filled with at least one of the front surface side insulating film 70 or the front surface side electrode 150. In this example, the recess 55 is filled with both the front surface side insulating film 70 and the front surface side electrode 150. In this example, the recess 55 is filled with the gate insulating film 170, the first gate electrode portion 111, and the second gate electrode portion 112.

[0148] In step S328, an interlayer insulating film 270 is formed above the front surface 11. The interlayer insulating film 270 formed in step S328 may be the second insulating portion 272. In step S331, a contact hole 56 is formed. The contact hole 56 is formed using the same mask. That is, the sidewalls of the contact hole 56 formed in step S331 are formed by both the gate insulating film 170 and the interlayer insulating film 270.

[0149] In step S332, a source pad 125 is formed above the diamond layer 15. The source pad 125 may be formed in the contact hole 56. In this example, the source pad 125 is formed up to the inside of the plurality of contact holes 56 and is electrically connected to the source electrode 120. After step S332, a back electrode 130 is formed, thereby manufacturing the diamond semiconductor device 100 shown in FIG.

[0150] Figure 11A shows a modified flowchart of the manufacturing method of diamond semiconductor device 100. In Figure 11A, the steps corresponding to those shown in Figures 8A to 10A are indicated by the corresponding last two digits of the numbers of each step. The example shown in Figure 11A differs from the examples described so far in that it does not have a step corresponding to step S128 of forming interlayer insulating film 270, and in that it has step S425 of patterning interlayer insulating film 270. Steps S400 to S416 are the same as steps S100 to S116 already described, so their description will be omitted.

[0151] FIG. 11B shows an example of a method for manufacturing the diamond semiconductor device 100. In FIG. 11B, the description continues from step S416, in which the source electrode 120 is formed. From FIG. 11B onwards, both cross-sectional views and top views of the diamond semiconductor device 100 at each stage are described as necessary. The cross-sectional views in each drawing show the cross section at the position indicated by the two-dot chain line in the top view. In the diamond semiconductor device 100 whose manufacturing method is described in FIGS. 8B to 8F, the periphery of the trench portion 50 is surrounded by the mesa portion 152 when viewed from above. On the other hand, the diamond semiconductor device 100 whose manufacturing method is described in FIG. 11B differs in that the periphery of the mesa portion 152 is surrounded by the trench portion 50 when viewed from above.

[0152] In step S418, the front surface-side insulating film 70 is formed. The front surface-side insulating film 70 formed in step S418 may be the gate insulating film 170. The gate insulating film 170 may be formed to fill the entire interior of the recess 55 of the trench portion 50. In this example, the recess 55 is filled only with the front surface-side insulating film 70.

[0153] Figure 11C shows an example of a method for manufacturing the diamond semiconductor device 100. Figure 11C shows a process subsequent to step S418 shown in Figure 11B.

[0154] In step S420, a front surface side electrode 150 is formed on the front surface side insulating film 70. The front surface side electrode 150 formed in step S420 may be the gate electrode 110. The gate electrode 110 may be formed on the entire surface of the gate insulating film 170 formed in steps S418. Since the inside of the recess 55 of the trench portion 50 is filled with the front surface side insulating film 70 in step S418, the front surface side electrode 150 is formed above the trench portion 50 in step S420.

[0155] Next, in step S422, the front surface-side insulating film 70 and the front surface-side electrode 150 are etched. In this example, the gate insulating film 170 and the gate electrode 110 are etched in step S422. In step S422, the front surface-side insulating film 70 and the front surface-side electrode 150 formed on the source electrode 120 are selectively etched.

[0156] Figure 11D shows an example of a method for manufacturing the diamond semiconductor device 100. Figure 11D shows a process subsequent to step S422 shown in Figure 11C.

[0157] In step S424, an interlayer insulating film 270 is formed above the front surface 11. The interlayer insulating film 270 may be formed on the entire surface of the gate electrode 110 and the source electrode 120 formed in steps S422. After step S424, in step S425, the interlayer insulating film 270 is removed from the region where the gate pad 115 will be formed, thereby forming an opening 275. In this example, the opening 275 is formed to extend in the X-axis direction. The opening 275 may be formed in a region different from the region where the source pad 125 will be formed later. That is, the opening 275 may be formed to extend in the Y-axis direction. The opening 275 is formed to expose at least a portion of the top surface of the gate electrode 110.

[0158] Figure 11E shows an example of a method for manufacturing the diamond semiconductor device 100. Figure 11E shows a process subsequent to step S425 shown in Figure 11D.

[0159] In step S426, a gate pad 115 is formed above the diamond layer 15. The gate pad 115 is formed to cover at least a portion of the opening 275 formed in step S425. The gate pad 115 may be electrically connected to the gate electrode 110 inside the opening 275. In this example, the step of forming the second gate electrode portion 112 can be omitted, thereby reducing the number of processes.

[0160] In this example, since the second gate electrode portion 112 electrically connecting the gate pad 115 and the first gate electrode portion 111 is not formed, there is no need to form an additional insulating film to insulate the second gate electrode portion 112 from the source pad 125. As a result, a step corresponding to step S128 of forming the interlayer insulating film 270 can be omitted, thereby reducing the number of processes.

[0161] Figure 11F shows an example of a method for manufacturing the diamond semiconductor device 100. Figure 11F shows a process subsequent to step S426 shown in Figure 11E.

[0162] In step S430, a contact hole 56 is formed in the interlayer insulating film 270. The contact hole 56 may be formed by selective etching using a mask. In this example, the contact hole 56 is selectively formed above the source electrode 120 to expose the top surface of the source electrode 120.

[0163] In step S432, a source pad 125 is formed above the diamond layer 15. In this example, the source pad 125 is formed so as to cover the trench portion 50 and the mesa portion 152. The source pad 125 may also be formed inside the contact hole 56. In this example, the source pad 125 is formed up to the inside of the plurality of contact holes 56 and is electrically connected to the source electrode 120. After step S432, a back surface electrode 130 is formed, thereby manufacturing the diamond semiconductor device 100 shown in FIG. 4A.

[0164] Figure 12A shows a modified flowchart of the manufacturing method of the diamond semiconductor device 100. In Figure 12A, the last two digits of the numbers of the steps correspond to the steps shown in Figures 8A to 11A. The example shown in Figure 12A differs from the example described in Figures 11A to 11F in that the recess 55 of the trench portion 50 is filled with the gate electrode 110. Steps S500 to S516 are the same as steps S100 to S116 already described, and therefore their description will be omitted.

[0165] Figure 12B shows an example of a method for manufacturing the diamond semiconductor device 100. In Figure 12B, the explanation will continue from step S516 of forming the source electrode 120. From Figure 12B onwards, both cross-sectional views and top views of the diamond semiconductor device 100 at each stage will be explained as necessary. The cross-sectional views in each drawing show the cross section at the position indicated by the two-dot chain line in the top view.

[0166] In step S518, a front-side insulating film 70 is formed on the epitaxial layer 30. The front-side insulating film 70 formed in step S518 may be the gate insulating film 170 and the buried insulating film 370. The front-side insulating film 70 is formed on the entire surface of the epitaxial layer 30, the source contact layer 60, and the source electrode 120.

[0167] The gate insulating film 170 and the buried insulating film 370 may be formed in the same process or in different processes. As an example, after the buried insulating film 370 is formed on the entire surface of the gate insulating film 170, the buried insulating film 370 can be selectively removed by etch-back or the like, so that the buried insulating film 370 is formed only inside the trench portion 50.

[0168] Figure 12C shows an example of a method for manufacturing the diamond semiconductor device 100. Figure 12C shows a process subsequent to step S518 shown in Figure 12B.

[0169] In step S520, a front surface side electrode 150 is formed on the front surface side insulating film 70. The front surface side electrode 150 formed in step S520 may be the gate electrode 110. In step S521, the front surface side electrode 150 is processed by etching back or the like. In step S521, the gate electrode 110 formed in step S520 is etched back. As a result, the gate electrode 110 may be formed only inside the recess 55 of the trench portion 50.

[0170] Figure 12D shows an example of a method for manufacturing the diamond semiconductor device 100. Figure 12D shows a process subsequent to step S521 shown in Figure 12C.

[0171] In step S524, an interlayer insulating film 270 is formed above the front surface 11. The interlayer insulating film 270 may be formed on the entire surface of the gate electrode 110 and the gate insulating film 170 formed in steps S521. After step S524, in step S525, the interlayer insulating film 270 is removed from the region where the gate pad 115 will be formed, thereby forming an opening 275. In this example, the opening 275 is formed to extend in the X-axis direction. The opening 275 may be formed in a region different from the region where the source pad 125 will be formed later. That is, the opening 275 may be formed to extend in the Y-axis direction. The opening 275 is formed to expose at least a portion of the top surface of the gate electrode 110.

[0172] Figure 12E shows an example of a method for manufacturing the diamond semiconductor device 100. Figure 12E shows a process subsequent to step S525 shown in Figure 12D.

[0173] In step S526, a gate pad 115 is formed above the diamond layer 15. The gate pad 115 is formed to cover at least a portion of the opening 275 formed in step S525. The gate pad 115 may be electrically connected to the gate electrode 110 inside the opening 275. In this example, the step of forming the second gate electrode portion 112 can be omitted, thereby reducing the number of processes.

[0174] In this example, since the second gate electrode portion 112 electrically connecting the gate pad 115 and the first gate electrode portion 111 is not formed, there is no need to form an additional insulating film to insulate the second gate electrode portion 112 from the source pad 125. As a result, a step corresponding to step S128 of forming the interlayer insulating film 270 can be omitted, thereby reducing the number of processes.

[0175] Figure 12F shows an example of a method for manufacturing the diamond semiconductor device 100. Figure 12F shows a process subsequent to step S526 shown in Figure 12E.

[0176] In step S531, a contact hole 56 is formed above the source electrode 120. In step S531, the gate insulating film 170 and the interlayer insulating film 270 may be etched using the same mask to form the contact hole 56. In step S532, a source pad 125 is formed above the diamond layer 15 and inside the contact hole 56. In this example, the source pad 125 is formed up to the inside of the multiple contact holes 56 and is electrically connected to the source electrode 120. After step S532, a back side electrode 130 is formed, thereby manufacturing the diamond semiconductor device 100 shown in FIG. 5.

[0177] 13 shows an outline of the configuration of the semiconductor module 200. The semiconductor module 200 includes the diamond semiconductor device 100 that functions as a MOSFET. The semiconductor module 200 includes a gate terminal 210, a source terminal 220, and a drain terminal 230. The gate terminal 210, the source terminal 220, and the drain terminal 230 may be external connection terminals for electrically connecting the semiconductor module 200 to the outside.

[0178] The gate terminal 210 is connected to the gate electrode 110 of the diamond semiconductor device 100. The source terminal 220 is connected to the source electrode 120 of the diamond semiconductor device 100. The drain terminal 230 is connected to the back surface electrode 130 of the diamond semiconductor device 100. The diamond semiconductor device 100 may be provided on the insulating substrate of the semiconductor module 200 with the back surface electrode 130 facing downward. The back surface electrode 130 may be electrically connected to the drain terminal 230 via metal wiring on the insulating substrate.

[0179] The semiconductor module 200 may have a single diamond semiconductor device 100, or may have a plurality of diamond semiconductor devices 100. The semiconductor module 200 may have an inverter circuit. The semiconductor module 200 may have an inverter circuit that combines a P-type channel diamond semiconductor device 100 and an N-type channel semiconductor element. The N-type channel semiconductor element may be the N-type channel diamond semiconductor device 100, or may be another semiconductor element such as GaN or SiC.

[0180] Although the present invention has been described above using embodiments, the technical scope of the present invention is not limited to the scope described in the above embodiments. It will be apparent to those skilled in the art that various modifications and improvements can be made to the above embodiments. It is clear from the claims that such modifications and improvements can also be included within the technical scope of the present invention.

[0181] It should be noted that the order of execution of each process, such as operations, procedures, steps, and stages, in the devices, systems, programs, and methods shown in the claims, specifications, and drawings is not specifically stated as "before," "prior to," etc., and that the processes can be performed in any order unless the output of a previous process is used in a subsequent process. Even if the operational flow in the claims, specifications, and drawings is described using "first," "next," etc. for convenience, this does not mean that the processes must be performed in this order.

[0182] 10... diamond substrate, 11... front surface, 12... back surface, 15... diamond layer, 20... doped region, 21... first region, 22... second region, 30... epitaxial layer, 40... termination layer, 50... trench portion, 55... recess, 56... contact hole, 60... source contact layer, 70... front surface side insulating film, 80... unit structure, 91... mask, 92... mask, 100... diamond semiconductor device, 110... gate electrode, 111... First gate electrode portion, 112... Second gate electrode portion, 115... Gate pad, 120... Source electrode, 125... Source pad, 130... Rear surface side electrode, 150... Front surface side electrode, 152... Mesa portion, 170... Gate insulating film, 200... Semiconductor module, 210... Gate terminal, 220... Source terminal, 230... Drain terminal, 270... Interlayer insulating film, 271... First insulating portion, 272... Second insulating portion, 275... Opening, 370... Buried insulating film

Claims

1. A diamond semiconductor device having a trench portion and a mesa portion on a front surface, comprising: a diamond layer; an epitaxial layer of diamond provided on the diamond layer; a front surface side insulating film provided above the epitaxial layer; a front surface side electrode provided on the front surface side insulating film; a gate pad provided above the diamond layer; and a source pad provided above the diamond layer and covering the trench portion and the mesa portion, wherein the front surface side electrode is a gate electrode electrically connected to the gate pad or a source electrode electrically connected to the source pad, and the epitaxial layer is provided along the inner wall of the trench of the trench portion, and the total channel width of a region of the epitaxial layer functioning as a channel is 1×10 －１ mm or more, 1×10 ６ mm or less, and a recess in the trench portion defined by an inner wall of the epitaxial layer is filled with at least one of the front surface side insulating film and the front surface side electrode.

2. A plurality of unit structures including the trench portion and the mesa portion are provided, and the pitch of the unit structures is 5×10 －１ μm or more, 5×10 ４ The diamond semiconductor device according to claim 1 , wherein the source pad covers the top of a plurality of the unit structures.

3. The diamond semiconductor device according to claim 2, wherein the source pad is electrically connected to the source electrode using a plurality of contact holes.

4. A diamond semiconductor device according to claim 1 or 2, wherein the front surface electrode is the gate electrode.

5. A diamond semiconductor device according to claim 1 or 2, wherein the outer periphery of the trench portion is surrounded by the mesa portion when viewed from above.

6. The diamond semiconductor device according to claim 5, wherein Pt<2Wt is satisfied, where Pt is the pitch of the trench portion and Wt is the trench width of the trench portion.

7. A diamond semiconductor device according to claim 5, wherein the ratio of the area of ​​said mesa portion to the area of ​​said trench portion when viewed from above is greater than 0 and less than 3.

8. A diamond semiconductor device according to claim 1 or 2, wherein the outer periphery of the mesa portion is surrounded by the trench portion when viewed from above.

9. The diamond semiconductor device according to claim 8, wherein Pm>2Wt is satisfied, where Pm is the pitch of the mesa portion and Wt is the trench width of the trench portion.

10. A diamond semiconductor device according to claim 8, wherein the ratio of the area of ​​the trench portion to the area of ​​the mesa portion when viewed from above is greater than 0 and less than 3.

11. A diamond semiconductor device according to claim 1 or 2, wherein the recess of the trench portion is filled with the front surface side insulating film and the front surface side electrode.

12. The diamond semiconductor device according to claim 1 or 2, wherein at least a portion of the gate electrode is located above the source electrode.

13. A diamond semiconductor device according to claim 1 or 2, wherein the sidewalls of the trench of the trench portion are tapered.

14. A diamond semiconductor device according to claim 1 or 2, wherein the recess of the trench portion is filled with the front surface side insulating film.

15. A diamond semiconductor device according to claim 1 or 2, further comprising a P-type source contact layer in contact with the lower surface of the source electrode, the source contact layer being provided on the epitaxial layer.

16. A diamond semiconductor device according to claim 1 or 2, wherein the width of the source electrode is greater than the width of the source pad provided in the contact hole above the source electrode.

17. A diamond semiconductor device according to claim 1 or 2, wherein the source electrode and the source pad are connected within a contact hole, and the lower end of the source electrode is provided within the contact hole.

18. A method for manufacturing a diamond semiconductor device having a trench portion and a mesa portion on a front surface, comprising the steps of: forming an epitaxial layer of diamond on a diamond layer; forming a front surface side insulating film above the epitaxial layer; forming a front surface side electrode on the front surface side insulating film; forming a gate pad above the diamond layer; and forming a source pad above the diamond layer to cover the trench portion and the mesa portion, wherein the step of forming the front surface side electrode includes the step of forming a gate electrode electrically connected to the gate pad or the step of forming a source electrode electrically connected to the source pad, and the epitaxial layer is provided along an inner wall of the trench of the trench portion, and the total channel width of a region of the epitaxial layer that functions as a channel is 1×10 －１ mm or more, 1×10 ６ mm or less, and a recess in the trench portion defined by an inner wall of the epitaxial layer is filled with at least one of the front surface side insulating film or the front surface side electrode.

19. A method for manufacturing a diamond semiconductor device as set forth in claim 18, comprising the steps of: forming an interlayer insulating film above the front surface of the diamond layer; and forming contact holes in the interlayer insulating film, wherein the source electrode and the source pad are formed in the contact holes.

20. A method for manufacturing a diamond semiconductor device as described in claim 18 or 19, comprising the steps of: forming an interlayer insulating film above the front surface of the diamond layer; and forming contact holes in the front surface-side insulating film and the interlayer insulating film using the same mask; and the source pad is formed in the contact hole.

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