Printed circuit board

Abstract

This printed circuit board comprises: an insulation layer which has a first surface and a second surface that is positioned on the opposite side from the first surface; a first conductor layer which is positioned on the first surface; a metal foil which is positioned on the second surface and which has a third surface that is positioned on the second surface side and a fourth surface that is positioned on the opposite side from the third surface; a hole which passes through the metal foil and the insulation layer and at the bottom of which is positioned the first conductor layer; a via conductor which is positioned in the hole; and a second conductor layer which is positioned on the fourth surface and which is connected to the via conductor. The metal foil has a first inner peripheral edge which is positioned on the third surface and which surrounds the hole and a second inner peripheral edge which is positioned on the fourth surface and which surrounds the hole. The second inner peripheral edge is closer than the first inner peripheral edge to the central axis of the via conductor. The metal foil has a tapered surface which becomes increasingly closer to the fourth surface as proximity to the central axis increases and faces the second surface or an imaginary extended surface of the second surface on the side further toward the central axis than the first inner peripheral edge.

Description

printed wiring board

[0001] The present disclosure relates to printed wiring boards.

[0002] WO 2016 / 163049 and JP 2023-170276 A describe printed wiring boards having via conductors.

[0003] In detail, WO 2016 / 163049 discloses a configuration in which a metal foil protrusion is present at the opening of a through-hole, the shape of the metal foil protrusion is rectangular, and the periphery of the rectangular protrusion is covered with the first stage of electrolytic filling plating that is divided into two stages.

[0004] Japanese Patent Application Laid-Open No. 2023-170276 discloses a configuration in which no metal foil protrudes from the opening of the through hole in the resin insulating layer (i.e., a hole filled with a via conductor, which is synonymous with the opening of the through-hole hole in WO 2016 / 163049), but the upper end of the insulating resin layer is removed in a direction outward from the central axis of the through hole in the metal foil and resin insulating layer, and the removed portion is filled with an electroless plating film or a sputtering film.

[0005] a via conductor located in the hole; and a second conductor layer located on the fourth surface and connected to the via conductor; wherein the metal foil has a first inner peripheral edge located on the third surface and surrounding the hole, and a second inner peripheral edge located on the fourth surface and surrounding the hole, the second inner peripheral edge being closer to the central axis of the via conductor than the first inner peripheral edge; and the metal foil further has a tapered surface that faces the second surface or an imaginary extended plane of the second surface on the central axis side of the first inner peripheral edge, and gradually approaches the fourth surface as it approaches the central axis.

[0006] FIG. 1 is a longitudinal sectional view showing a printed wiring board according to embodiment 1 of the present disclosure. FIG. 2 is an enlarged sectional view of a via conductor. FIG. 3 is an enlarged view of a main portion of a via conductor. FIG. 4 is a diagram illustrating an action in a manufacturing stage of a via conductor. FIG. 5 is a diagram illustrating an example of a manufacturing method of a via conductor according to embodiment 1. FIG. 6 is an enlarged sectional view of a modified example 1 of a via conductor main portion according to embodiment 1. FIG. 7 is an enlarged sectional view of a modified example 2 of a via conductor main portion according to embodiment 1. FIG. 8 is an enlarged sectional view of a modified example 3 of a via conductor main portion according to embodiment 1. FIG. 9 is an enlarged sectional view of a modified example 4 of a via conductor main portion according to embodiment 1. FIG. 10 is an enlarged sectional view of a modified example 5 of a via conductor main portion according to embodiment 1. FIG. 11 is an enlarged sectional view of a via conductor according to embodiment 2. FIG. 12 is an enlarged view of a main portion of a via conductor according to embodiment 2. FIG. 13 is a diagram illustrating an example of a manufacturing method of a via conductor according to embodiment 2. FIG. 14 is an enlarged sectional view of a modified example 7 of a via conductor main portion according to embodiment 2. FIG. 15 is an enlarged sectional view of a modified example 8 of a via conductor main portion according to embodiment 2. FIG. 16 is an enlarged sectional view of a modified example 9 of a via conductor main portion according to embodiment 2. FIG. 17 is an enlarged sectional view of a modified example 10 of a via conductor main portion according to embodiment 2. FIG. 18 is an enlarged sectional view of a modified example 11 of a via conductor main portion according to embodiment 2.

[0007] Hereinafter, embodiments will be described with reference to the drawings, but the dimensions and dimensional ratios of the components in the drawings do not faithfully represent the dimensions and dimensional ratios of the actual components.

[0008] (Embodiment 1) Fig. 1 is a cross-sectional view of a printed wiring board 1 according to embodiment 1. The printed wiring board 1 may be a buildup printed wiring board including a core substrate C having IVHs (interstitial via holes) 10, and a plurality of buildup layers B having conductor layers 20 and via conductors 40. Fig. 1 shows the printed wiring board 1 having the core substrate C, buildup layers B stacked on one side of the core substrate C, and buildup layers B stacked on the other side of the core substrate C. The number of stacked buildup layers B, and the positions of the IVHs 10 and via conductors 40 can be changed in various ways.

[0009] Each of the plurality of conductor layers 20 may be a layer having a wiring pattern when viewed from above. In the thickness direction of the printed wiring board 1, two adjacent conductor layers 20 are positioned with one insulating layer 30 therebetween, and the via conductor 40 may be a conductor connecting the two adjacent conductor layers 20.

[0010] The material of the insulating layer 30 may be a resin, a mixture of a resin and an inorganic filler, a resin containing a fibrous reinforcing material, or a mixture of the above containing a fibrous reinforcing material.

[0011] The material of the conductor layer 20 and the via conductor 40 may be a metal such as copper.

[0012] <Via Conductor> Fig. 2A shows an enlarged cross-sectional view of the via conductor. Fig. 2B shows an enlarged view of a main portion c1 of the via conductor. Fig. 2A shows a cross-section of the via conductor 40 taken along the central axis A1, but the peripheral configuration of the via conductor 40 may have the same cross-sectional configuration as Fig. 2A in any cross-section taken along the central axis A1.

[0013] Hereinafter, the via conductor 40 and the surrounding parts may be described using the up, down, left, and right directions on the paper surface of Figure 2A. The up and down direction is the direction along the central axis A1 of the via conductor 40, and the left and right direction is the direction perpendicular to the central axis A1. The up, down, left, and right directions in the description may differ from the directions in the used state.

[0014] 2A , when focusing on one via conductor 40, an insulating layer 30, a hole 31, a first conductor layer 21, a second conductor layer 22, and a metal foil 24 may be located around the via conductor 40. The first conductor layer 21, the second conductor layer 22, and the metal foil 24 correspond to two adjacent conductor layers 20 among the plurality of conductor layers 20 (see FIG. 1 ). The first conductor layer 21 may be a conductor layer 20 located closer to the core substrate C than the second conductor layer 22.

[0015] Hereinafter, the surface of the insulating layer 30 facing the first conductor layer 21 will be referred to as the first surface S30a, and the surface facing the second conductor layer 22 will be referred to as the second surface S30b. The surface of the metal foil 24 facing the insulating layer 30 will be referred to as the third surface S24a, and the surface facing the second conductor layer 22 will be referred to as the fourth surface S24b.

[0016] The metal foil 24 may be located on the second surface S30b of the insulating layer 30, and the second conductor layer 22 may be located on the fourth surface S24b of the metal foil 24. The hole 31 may be configured to penetrate the metal foil 24 and the insulating layer 30 from the second conductor layer 22 to the first conductor layer 21. A via conductor 40 may be located in the hole 31. The via conductor 40 may be filled in the hole 31. The first conductor layer 21 may be located at the bottom of the hole 31.

[0017] The metal foil 24 may be a copper foil. The second conductor layer 22 and the via conductors 40 may be metal plating such as copper plating.

[0018] The via conductor 40 may have a shape that is symmetrical or asymmetrical with respect to a virtual central axis A1 extending from the second conductor layer 22 to the first conductor layer 21. The central axis A1 is defined as a straight line connecting, for example, the center of the opening of the hole 31 on the second surface S30b side and the center of the opening of the hole 31 on the first surface S30a.

[0019] <Shape of Metal Foil> The metal foil 24 may have a first inner peripheral edge E24a located on the third surface S24a and surrounding the hole 31, and a second inner peripheral edge E24b located on the fourth surface S24b and surrounding the hole 31. The second inner peripheral edge E24b may be closer to the central axis A1 of the via conductor 40 than the first inner peripheral edge E24a. Furthermore, the metal foil 24 may further have a tapered surface S24f that faces the second surface S30b or an imaginary extended surface S30bx of the second surface S30b on the central axis A1 side of the first inner peripheral edge E24a and gradually approaches the fourth surface S24b as it approaches the central axis A1.

[0020] The tapered surface S24f is distinguished from a small inclined surface due to tolerance or error by either or both of the following two factors: the thickness T1 of the tapered surface S24f is 5% or more of the thickness T24 of the metal foil 24, and the length L1 of the tapered surface S24f is 200% or more of the thickness T24 of the metal foil 24 (see FIG. 2B).

[0021] According to the printed wiring board 1 of the first embodiment, the second inner peripheral edge E24b is located closer to the central axis A1 than the first inner peripheral edge E24a, so that the second conductor layer 22 and some of the conductors of the via conductors 40 are located below the tapered surface S24f. This increases the engagement force between the metal foil 24 and the second conductor layer 22 and the via conductors 40, reducing the likelihood of the via conductors 40 breaking relative to the first conductor layer 21 when force is applied to the via conductors 40.

[0022] FIG. 3 is a diagram illustrating the operation of the via conductor during its manufacturing process. Generally, when the metal foil 24 simply has a rectangular cross-section and protrudes toward the central axis A1, poor circulation of the plating solution occurs below the protruding portion when the via conductor 40 is formed by metal plating. In particular, poor circulation of the electrolytic filling plating solution causes plating deposition to begin below the protruding portion of the metal foil, resulting in the protruding portion of the metal foil being blocked by plating while plating deposition at the bottom of the hole is insufficient. When the protruding portion of the metal foil is blocked by plating, the plating electric field is not applied to the plating solution in the center of the hole, and the metal ions in the plating solution cannot accept electrons and do not metallize. In other words, voids are formed in the via conductor. On the other hand, in embodiment 1, as shown in FIG. 3, a tapered surface S24f is located on the underside of the protruding portion. Therefore, even if a protruding portion is present, the plating solution circulates well below the protruding portion and throughout the entire hole 31.

[0023] The arrows in Figure 3 represent the circulation of the plating solution. By improving the circulation of the plating solution, plating deposition does not begin below the protruding portion of the metal foil, but begins from the bottom of the hole, preventing the protruding portion of the metal foil from being blocked by plating. This makes it less likely that voids will form in the via conductor 40.

[0024] The above-mentioned multiple effects make it possible to realize a via conductor 40 with high connection reliability.

[0025] The insulating layer 30 may have a third inner peripheral edge E30a located on the second surface S30b and surrounding the hole 31. The second inner peripheral edge E24b of the metal foil 24 may be located closer to the central axis A1 than the third inner peripheral edge E30a of the insulating layer 30. This configuration improves the circulation of plating solution below the tapered surface S24f, more effectively than when the protruding shape of the metal foil is rectangular. This increases the connection reliability of the via conductors 40.

[0026] In a cross section taken along the central axis A1, a corner X1 (see FIG. 2B ) where the second surface S30b of the insulating layer 30 intersects with the inner peripheral surface S31 of the hole 31 (i.e., the inner surface) may be steep. That is, the corner X1 does not need to have a shape that reduces the steepness (e.g., a rounded shape, a C-shaped shape, a rounded shoulder shape, etc.). However, the corner X1 may include a rounded or C-shaped shape due to tolerance or error. A rounded or C-shaped shape due to tolerance or error means that the vertical length of the rounded or C-shaped shape is 1 / 20 or less of the thickness T30 (i.e., the vertical width) of the insulating layer 30.

[0027] <Manufacturing Method> Figure 4 is a diagram illustrating an example of a manufacturing method for the via conductor 40 of embodiment 1. Figure 4 shows a part of the process of forming the buildup layer B (see Figure 1), and more specifically, shows the process from step J1 of laminating the insulating layer 30 and metal foil 24 of one buildup layer B to the formation of the conductor layer 20 in that buildup layer B. Included between these steps are a window forming step J2, a hole forming step J3, a post-hole forming step J4, an electroless plating step J5, and an electrolytic plating step J6.

[0028] In the window forming process J2, an opening h24 for the via conductor 40 is formed in the metal foil 24. In the subsequent hole forming process J3, a hole 31 is formed in the insulating layer 30. The upper opening of the hole 31 in the insulating layer 30 is formed larger than the opening h24 in the metal foil 24. The window forming process J2 may be performed by laser processing or etching. The hole forming process J3 is preferably performed by laser processing. After the hole forming process J3, the edge of the opening in the metal foil 24 protrudes inward beyond the hole 31 in the insulating layer 30.

[0029] In the post-process J4, a desmear process is performed to remove resin residue of the insulating layer 30 remaining at the bottom of the hole 31 in the insulating layer 30 after the laser processing, and an etching process is performed to wash away and remove resin residue of the insulating layer 30 that was not completely removed by the desmear process and remains at the bottom of the hole 31 in the insulating layer 30 by dissolving the first conductor layer 21. As a result of the etching process, the bottom b31 of the hole 31 becomes wider than the lower opening of the insulating layer 30, and a part of the bottom b31 of the hole 31 overlaps with the insulating layer 30 in a plan view.

[0030] In the desmearing and etching processes, the liquid agent reaches the holes 31, and the third surface S24a of the protruding portion of the metal foil 24 is scraped from the corners, thereby forming a tapered surface S24f. Because the third surface S24a of the metal foil 24 has a higher roughness than the fourth surface S24b at the time of etching, the area that comes into contact with the etching solution is larger, and the proportion of the third surface S24a that dissolves during the etching process is higher, thereby forming a tapered surface S24f on the third surface S24a. The angle, length L1, and thickness T1 (see FIG. 2B ) of the tapered surface S24f can be adjusted by setting the roughness of the third surface S24a of the metal foil 24 and the times of the desmearing and etching processes, etc.

[0031] The electroless plating process J5 and the electrolytic plating process J6 integrally (specifically, as one continuous piece) form the second conductor layer 22 and the via conductor 40. First, in the electroless plating process J5, copper plating 51 is applied to the inner circumferential surface of the hole 31 in the insulating layer 30, the bottom surface of the hole 31 in the first conductor layer 21, and the exposed portion of the metal foil 24. In the subsequent electrolytic plating process J6, the hole 31 is filled with copper plating to form the via conductor 40, and the upper surface of the metal foil 24 is copper plated to a predetermined thickness to form the second conductor layer 22.

[0032] By the above-described steps J1 to J6, the metal foil 24 having the tapered surface S24f, the via conductor 40, and the second conductor layer 22 can be formed.

[0033] <Modifications of Metal Foil Shape> FIGS. 5A to 5C are diagrams showing modifications of a main portion of the via conductor 40. The main portion is the same as the main portion c1 in FIG. 2A. As shown in FIG. 5A, the tapered surface S24f may be conical, i.e., the outer contour of the tapered surface S24f may be linear in cross section. As shown in FIG. 5B, the tapered surface S24f may include a concavely curved curved portion C24, i.e., a curved portion C24 that is concavely curved in cross section. The curved portion C24 may be included in the entire range from the outer peripheral end to the inner peripheral end of the tapered surface S24f, or may be included in a partial range. The curved portion C24 may be continuous around the entire circumference around the central axis A1 (see FIG. 2A), or may be located only partially in the circumferential direction.

[0034] The inclusion of the curved portion C24 increases the contact area with the second conductor layer 22 or the via conductor 40, thereby further improving the contact strength between the tapered surface S24f and the second conductor layer 22 or the via conductor 40. Furthermore, the inclusion of the curved portion C24 further improves the circulation of the plating solution in the above-mentioned electrolytic plating step J6, thereby achieving a high-quality via conductor 40 with fewer voids.

[0035] As shown in FIG. 5C , the angle θ of the protruding portion of the metal foil 24 may be 50° or greater. Alternatively, the angle θ may be 90° or greater. The angle θ corresponds to the angle formed between the line segment M connecting the first inner peripheral edge E24a and the second inner peripheral edge E24b and the inner peripheral surface S31 (corresponding to the inner surface) of the hole 31 in a first cross section cs1 that is outward from the central axis A1 among cross sections along the central axis A1. By increasing the angle θ as described above, the circulation of the plating solution is further improved in the electrolytic plating step J6, resulting in a high-quality via conductor 40 with reduced voids.

[0036] 6A to 6C are diagrams showing modified examples of a main part of the via conductor 40. The main part is the same as the main part c1 in FIG. 2A. As shown in FIG. 6A, the first inner peripheral edge E24a of the metal foil 24 and the third inner peripheral edge E30a of the insulating layer 30 may be located in the same place. This configuration allows for easy circulation of the plating solution, resulting in the formation of a via conductor 40 with high connection reliability.

[0037] 6B and 6C , the first inner peripheral edge E24a of the metal foil 24 and the third inner peripheral edge E30a of the insulating layer 30 may be spaced apart in the left-right direction. The distances L11 and L12 may be 100% or less of the length L1 of the tapered surface S24f (e.g., 3 μm or less). This configuration improves connection reliability while maintaining high adhesion between the via conductor 40 and the metal foil 24 or the insulating layer 30 for a long period of time.

[0038] (Embodiment 2) Fig. 7A is an enlarged cross-sectional view of a via conductor of embodiment 2. Fig. 7B is an enlarged view of a main portion c2 of the via conductor. The printed wiring board 1A of embodiment 2 may be similar to embodiment 1 except for the configuration around the upper opening of the hole 31. The configuration different from embodiment 1 will be described in detail below. Fig. 7A shows a cross section along the central axis A1 of the via conductor 40, but the peripheral configuration of the via conductor 40 may have the same cross-sectional configuration as Fig. 7A in any cross section along the central axis A1.

[0039] In the following description, each part around the via conductor 40 may be described using the up, down, left, and right directions on the paper surface of Figure 7A. The up and down direction is the direction along the central axis A1 of the via conductor 40, and the left and right direction is the direction perpendicular to the central axis A1. The up, down, left, and right directions in the description may differ from the directions in the used state.

[0040] The metal foil 24 may have a first inner peripheral edge E24a located on the third surface S24a and surrounding the hole 31, and a second inner peripheral edge E24b located on the fourth surface S24b and surrounding the hole 31. The second inner peripheral edge E24b may be closer to the central axis A1 of the via conductor 40 than the first inner peripheral edge E24a. Furthermore, the metal foil 24 may further have a tapered surface S24f that faces the second surface S30b on the central axis A1 side of the first inner peripheral edge E24a and gradually approaches the fourth surface S24b as it approaches the central axis A1.

[0041] The insulating layer 30 may have a third inner peripheral edge E30a located on the second surface S30b and surrounding the hole 31. In the second embodiment, the third inner peripheral edge E30a may be located closer to the central axis A1 of the via conductor 40 than the second inner peripheral edge E24b of the metal foil 24.

[0042] According to the printed wiring board 1A of the second embodiment, the second inner peripheral edge E24b is closer to the central axis A1 than the first inner peripheral edge E24a, and furthermore, due to the tapered surface S24f, the second conductor layer 22 and a portion of the conductor of the via conductor 40 are located below the tapered surface S24f. Therefore, the engagement force between the second conductor layer 22 and the via conductor 40 and the metal foil 24 is increased, and the via conductor 40 is less likely to break relative to the insulating layer 30 when a force is applied to the via conductor 40.

[0043] Furthermore, the conductor located below the tapered surface S24f is bonded to the metal foil 24 and the insulating layer 30 over a wide range of the insulating layer 30, i.e., a wide range extending from the second surface S30b across the third inner peripheral edge E30a to the inner peripheral surface S31 of the hole 31. Therefore, the adhesive strength between the metal foil 24, the second conductor layer 22, and the via conductor 40 and the insulating layer 30 can be further improved.

[0044] Furthermore, according to the printed wiring board 1A of the second embodiment, the second inner peripheral edge E24b of the metal foil 24 is located farther from the central axis A1 than the third inner peripheral edge E30a of the insulating layer 30. In other words, the metal foil 24 does not protrude inward much at the upper opening of the hole 31. Therefore, when the via conductor 40 is formed by metal plating, good circulation of plating solution is achieved within the hole 31. Therefore, voids are less likely to form in the hole 31. Due to the above-mentioned multiple effects, the printed wiring board 1A of the second embodiment can achieve a high-quality via conductor 40 with few voids.

[0045] <Manufacturing Method> Fig. 8 is a diagram illustrating an example of a manufacturing method for the via conductor 40 of embodiment 2. Fig. 8 shows a part of the process of forming the buildup layer B, that is, from step J1 of laminating the insulating layer 30 and the metal foil 24 of one buildup layer B (see Fig. 1 ) to the formation of the conductor layer 20 in the buildup layer B. Included between these steps are a window forming step J2, a hole forming step J3, a post-hole forming step J4, an electroless plating step J5, and an electrolytic plating step J6.

[0046] In the window forming process J2, an opening h24 for the via conductor 40 is formed in the metal foil 24. The opening h24 in the metal foil 24 is formed to a size similar to the upper opening of the hole 31 in the insulating layer 30. In the subsequent hole forming process J3, the hole 31 is formed in the insulating layer 30. The window forming process J2 may be performed by laser processing or etching. The hole forming process J3 is preferably performed by laser processing.

[0047] The post-process J4 involves a desmear process to remove resin residue from the insulating layer 30 remaining at the bottom of the hole 31 in the insulating layer 30 after laser processing, and an etching process to dissolve the first conductor layer 21 to wash away and remove any resin residue from the insulating layer 30 that was not completely removed by the desmear process and remains at the bottom b31 of the hole 31 in the insulating layer 30. During the desmear and etching processes, the liquid agent that has entered the hole 31 penetrates into the interface between the metal foil 24 exposed on the inner surface of the hole 31 and the insulating layer 30, scraping the metal foil 24 from the lower corner, thereby forming the tapered surface S24f. Penetration of the liquid agent into the interface is promoted by lowering the roughness of the third surface S24a of the metal foil 24 compared to that in the first embodiment. Therefore, the angle, length, and thickness of the tapered surface S24f can be adjusted by adjusting the roughness of the third surface S24a and setting the etching time, etc.

[0048] In the electroless plating process J5 and the electrolytic plating process J6, the second conductor layer 22 and the via conductor 40 are formed integrally (specifically, as one continuous piece). First, in the electroless plating process J5, electroless copper plating is applied to the inner circumferential surface of the hole 31 in the insulating layer 30, the bottom surface of the hole 31 in the first conductor layer 21, the exposed portion of the metal foil 24, and the inner surface of the space located between the metal foil 24 and the insulating layer 30. In the subsequent electrolytic plating process J6, the hole 31 and the space located between the metal foil 24 and the insulating layer 30 are filled with electrolytic copper plating to form the via conductor 40, and the upper surface of the metal foil 24 is copper-plated to a predetermined thickness to form the second conductor layer 22.

[0049] By performing the above-described steps J1 to J6, a metal foil 24 can be formed in which the third inner peripheral edge E30a of the insulating layer 30 is closer to the central axis A1 than the second inner peripheral edge E24b of the metal foil 24, and which has a tapered surface S24f facing the second surface S30b of the insulating layer 30.

[0050] <Modifications of Metal Foil Shape> Figures 9A and 9B show modifications of a key portion of the via conductor 40. The key portion is the same as the key portion c2 in Figure 7A. As shown in Figure 9A, the tapered surface S24f may be conical, i.e., the outline of the tapered surface S24f may be linear in cross section. With this configuration, the tapered surface S24f contacts the second conductor layer 22 or the conductor of the via conductor 40 located below the tapered surface S24f with a nearly flat surface, thereby reducing the unevenness of the stress distribution at the contact surface. For example, if the tapered surface S24f has many irregularities, the unevenness may cause the unevenness in the stress distribution, resulting in the creation of areas where the stress distribution is concentrated. On the other hand, with the configuration of Figure 9A, the unevenness in the stress distribution is reduced, resulting in high adhesive strength at the contact surface and reducing the possibility of localized fracture of the conductor around the tapered surface S24f.

[0051] As shown in Fig. 9B, the tapered surface S24f may include a concavely curved curved portion C24, i.e., a curved portion C24 that is concavely curved in cross section. The curved portion C24 may be included in the entire range from the outer circumferential end to the inner circumferential end of the tapered surface S24f, or may be included in a partial range. The curved portion C24 may be continuous around the entire circumferential direction about the central axis A1 (see Fig. 7A), or may be located only partially in the circumferential direction.

[0052] 10A to 10C are diagrams showing modified examples of a main portion of the via conductor 40. The main portion is the same as the main portion c2 in FIG. 7A. As shown in FIG. 10A, the second inner peripheral edge E24b of the metal foil 24 and the third inner peripheral edge E30a of the insulating layer 30 may be positioned equidistant from the central axis A1. "Equidistant" does not only mean strictly equidistant, but also includes equidistant within a tolerance or error range. The tolerance or error is set to 1 / 30 or less of the thickness T30 of the insulating layer 30 (i.e., the vertical width; see FIG. 7A).

[0053] Because the second inner peripheral edge E24b and the third inner peripheral edge E30a are equidistant from the central axis A1, the conductor located below the tapered surface S24f contacts the metal foil 24 over a wider area than when the second inner peripheral edge E24b is farther from the third inner peripheral edge E30a. This provides a stronger locking force between the second conductor layer 22 or the conductor of the via conductor 40 and the metal foil 24. Furthermore, because the third inner peripheral edge E30a of the insulating layer 30 is closer to the central axis A1 than the first inner peripheral edge E24a of the metal foil 24, as described above, the conductor located below the tapered surface S24f adheres to the insulating layer 30 over a wider area around the second surface S30b of the insulating layer 30. This provides a high adhesive strength between the second conductor layer 22 or the conductor of the via conductor 40 and the insulating layer 30. These two effects enable the realization of a via conductor 40 with high connection reliability.

[0054] As shown in FIGS. 10B and 10C, the tapered surface S24f may be connected to the second inner peripheral edge E24b of the metal foil 24. With this configuration, the second inner peripheral edge E24b may have a pointed shape in vertical cross section. With this configuration, the tapered surface S24f may have a shape that connects the first inner peripheral edge E24a and the second inner peripheral edge E24b with a straight line in vertical cross section. According to the above configuration, the contact area between the conductor located below the tapered surface S24f and the metal foil 24 is increased. The reason for this increased contact area is as follows. FIGS. 10A to 10C sequentially show examples in which the etching amount in the above-mentioned post-process J4 is gradually increased. As shown in FIGS. 10A to 10B, as the etching amount is gradually increased, the length of the tapered surface S24f (i.e., the length from the outer peripheral edge to the inner peripheral edge) increases, and the tapered surface S24f approaches the second inner peripheral edge E24b. The length of tapered surface S24f is maximized where tapered surface S24f connects to second inner peripheral edge E24b. This increases the contact area between the conductor located below tapered surface S24f and metal foil 24, and the tapered surface S24f penetrates the surrounding structure like a wedge, thereby providing a stronger locking force between second conductor layer 22 and via conductor 40 and metal foil 24. The portion that penetrates the surrounding structure like a wedge is made of electrolytic copper plating, which has higher toughness than other metals such as electroless plating or sputtered film, thereby more effectively realizing a via conductor with high connection reliability.

[0055] The above describes the embodiments of the present disclosure. However, the printed wiring board of the present disclosure is not limited to the above embodiments, and the details shown in the embodiments can be modified as appropriate without departing from the spirit of the invention. Furthermore, the configurations, structures, positional relationships, and shapes shown in the above embodiments can be combined as appropriate without departing from the spirit of the present disclosure.

[0056] An embodiment of the present disclosure will be described below. In one embodiment, (1) a printed wiring board comprises: an insulating layer having a first surface and a second surface located opposite the first surface; a first conductor layer located on the first surface; a metal foil located on the second surface and having a third surface located on the second surface side and a fourth surface located opposite the third surface; a hole that penetrates the metal foil and the insulating layer and has the first conductor layer located at the bottom; a via conductor located in the hole; and a second conductor layer that is located on the fourth surface and is continuous with the via conductor, wherein the metal foil has a first inner peripheral edge located on the third surface and surrounding the hole, and a second inner peripheral edge located on the fourth surface and surrounding the hole, the second inner peripheral edge being closer to the central axis of the via conductor than the first inner peripheral edge, and the metal foil further has a tapered surface that faces the second surface or an imaginary extended plane of the second surface on the central axis side of the first inner peripheral edge, and gradually approaches the fourth surface as it approaches the central axis.

[0057] (2) In the printed wiring board of (1) above, the insulating layer has a third inner peripheral edge located on the second surface and surrounding the hole, and the second inner peripheral edge is closer to the central axis than the third inner peripheral edge.

[0058] (3) In the printed wiring board of (1) or (2) above, the tapered surface includes a curved portion that is concavely curved.

[0059] (4) In any one of the printed wiring boards (1) to (3) above, in a first cross section along the central axis on one side of the central axis, the angle formed by the line segment connecting the first inner peripheral edge and the second inner peripheral edge and the inner surface of the hole is 50° or more.

[0060] (5) In the printed wiring board according to any one of (1) to (4) above, the first inner peripheral edge and the third inner peripheral edge are located at the same position in at least one cross section along the central axis.

[0061] (6) In the printed wiring board of (1) above, the insulating layer has a third inner peripheral edge located on the second surface and surrounding the hole, and the third inner peripheral edge is closer to the central axis than the second inner peripheral edge.

[0062] (7) In the printed wiring board of (6) above, the tapered surface has a straight line portion at least in one cross section along the central axis.

[0063] (8) In the printed wiring board of (1) above, the insulating layer has a third inner peripheral edge located on the second surface and surrounding the hole, and in at least one cross section along the central axis, the third inner peripheral edge and the second inner peripheral edge are located equidistant from the central axis.

[0064] (9) In the printed wiring board according to any one of (6) to (8), the tapered surface and the second inner peripheral edge are connected to each other.

[0065] The present disclosure can be used in printed wiring boards.

[0066] 1, 1A Printed wiring board 10 IVH 20 Conductor layer 21 First conductor layer 22 Second conductor layer 24 Metal foil 30 Insulating layer 31 Hole portion 40 Via conductor S30a First surface S30b Second surface S30bx Virtual extension surface S31 Inner peripheral surface (inner surface) S24a Third surface S24b Fourth surface S24f Tapered surface C24 Curved portion E24a First inner peripheral edge E24b Second inner peripheral edge E30a Third inner peripheral edge A1 Central axis X1 Corner portion M Line segment

Claims

1. A printed wiring board comprising: an insulating layer having a first surface and a second surface located opposite the first surface; a first conductor layer located on the first surface; a metal foil located on the second surface, and having a third surface located on the second surface side and a fourth surface located opposite the third surface; a hole penetrating the metal foil and the insulating layer and with the first conductor layer located at the bottom; a via conductor located in the hole; and a second conductor layer located on the fourth surface and continuous with the via conductor; wherein the metal foil has a first inner periphery located on the third surface and surrounding the hole, and a second inner periphery located on the fourth surface and surrounding the hole, the second inner periphery being closer to the central axis of the via conductor than the first inner periphery; and the metal foil further has a tapered surface facing the second surface or an imaginary extended plane of the second surface on the central axis side of the first inner periphery, and gradually approaching the fourth surface as it approaches the central axis.

2. The printed wiring board according to claim 1, wherein the insulating layer has a third inner periphery located on the second surface and surrounding the hole, and the second inner periphery is closer to the central axis than the third inner periphery.

3. The printed wiring board according to claim 1 or 2, wherein the tapered surface includes a concavely curved portion.

4. A printed wiring board as described in any one of claims 1 to 3, wherein in a first cross section on one side of the central axis among cross sections along the central axis, the angle formed between the line segment connecting the first inner peripheral edge and the second inner peripheral edge and the inner surface of the hole is 50° or greater.

5. A printed wiring board according to any one of claims 1 to 4, wherein the first inner peripheral edge and the third inner peripheral edge are located at the same location in at least one cross section along the central axis.

6. The printed wiring board according to claim 1, wherein the insulating layer has a third inner periphery located on the second surface and surrounding the hole, the third inner periphery being closer to the central axis than the second inner periphery.

7. The printed wiring board according to claim 6, wherein said tapered surface has a straight portion in at least one cross section along said central axis.

8. The printed wiring board according to claim 1, wherein the insulating layer has a third inner periphery located on the second surface and surrounding the hole, and the third inner periphery and the second inner periphery are located equidistant from the central axis in at least one cross section along the central axis.

9. The printed wiring board according to any one of claims 6 to 8, wherein the tapered surface and the second inner peripheral edge are connected.

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