Pulse current-based battery charging device

Abstract

A pulse current-based battery charging device according to an embodiment of the disclosed invention may comprise: a clock generator for generating a clock signal; a reference generator for generating a reference voltage; a latch comparator for receiving an input of the reference voltage and a feedback voltage and operating on the basis of the clock signal; a D flip-flop connected to an output terminal of the latch comparator and outputting an end of charge (EOC) signal; a multiplexer for selecting one of the EOC signal and the clock signal, and outputting the selected signal; and a charging circuit for outputting a pulse current for charging a battery, on the basis of the clock signal.

Description

Pulse current based battery charger

[0001] The present invention relates to a pulse current-based battery charging device, and more specifically, to an invention that can extend the life of a battery compared to a conventional method by dividing a pulse current applied for battery charging into a charging phase and a reset phase.

[0002] In general, lithium batteries can have high energy, density, and low self-discharge rate.

[0003] In particular, lithium polymer (Lipo) batteries have the advantages of being thinner, safer, thinner, and having superior mechanical strength compared to lithium-ion (Li-ion) batteries.

[0004] As a charging method for these lithium polymer batteries, the CC / CV (constant current / constant voltage) method is widely used.

[0005] However, in constant current mode, if the movement speed of lithium ions exceeds the diffusion and insertion speed into the layered graphite structure, a phenomenon called lithium plating occurs, which causes a problem in that the overall lifespan of the battery is shortened.

[0006] In addition, battery elements experience a voltage drop phenomenon due to BIR (Built in Resistance) that cannot be physically accessed from the outside. However, since the BIR (Built in Resistance) compensation circuit according to conventional technology uses a digital circuit that implements a complex calculation process, there is a limitation that the complexity of the system and the size of the circuit increase.

[0007] Accordingly, a pulse current-based battery charging device according to one embodiment of the disclosed invention is an invention created to solve the problems of the above-described prior art, and more specifically, a battery charging device capable of feeding back the charging voltage of a battery by configuring the current applied to the battery as a pulse current rather than a constant current can be provided.

[0008] In addition, a pulse current-based battery charging device according to one embodiment of the disclosed invention can provide a battery charging device capable of compensating for a voltage drop phenomenon due to BIR (Built In Resistance) of a battery.

[0009] In addition, a pulse current-based battery charging device according to one embodiment of the disclosed invention can provide a battery charging device that can reduce the size and complexity of a system by utilizing a pulse current and a latch comparator that performs the role of a 1-bit ADC.

[0010] A pulse current-based battery charging device according to one embodiment of the disclosed invention may include a clock generator for generating a clock signal, a reference generator for generating a reference voltage, a latch comparator for receiving the reference voltage and a feedback voltage and operating based on the clock signal, a D flip-flop connected to an output terminal of the latch comparator for outputting an EOC (End Of Charge) signal, a multiplexer for selecting and outputting one of the EOC signal and the clock signal, and a charging circuit for outputting a pulse current for charging a battery based on the clock signal.

[0011] The above pulse current may include alternating charging and reset periods.

[0012] In the above reset section, the value of the pulse current may be 0 A.

[0013] The charging circuit may include a first transistor, a second transistor having a gate node connected to a gate node of the first transistor, a third transistor having one end connected to the multiplexer and the other end connected to one end of the first transistor, a first resistor connected to one end of the second transistor, and a second resistor connected in series with the first resistor.

[0014] The input terminal of the above battery can be connected to one end of the second transistor.

[0015] The above feedback voltage may be a node voltage between the first resistor and the second resistor.

[0016] When the feedback voltage is lower than the reference voltage, the EOC signal can be output as a Low value.

[0017] When the feedback voltage is higher than the reference voltage, the EOC signal can be output as a High value.

[0018] When the above multiplexer outputs the EOC signal having a High value, charging of the battery may be terminated.

[0019] A pulse current-based battery charging device according to one embodiment of the disclosed invention may include a clock generator for generating a clock signal, a charging circuit for outputting a pulse current for charging a battery based on the clock signal, a latch comparator for receiving a reference voltage and a feedback voltage of the charging circuit, operating based on the clock signal to output a first output voltage and a second output voltage, and a multiplexer for applying an EOC (End of Charge) signal or the clock signal to the charging circuit based on the first output voltage and the second output voltage of the latch comparator.

[0020] The pulse current includes a charging section and a reset section that operate alternately, and the value of the pulse current in the reset section may be 0 A.

[0021] The charging circuit may include a first transistor, a second transistor having a gate node connected to a gate node of the first transistor, a third transistor having one end connected to the multiplexer and the other end connected to one end of the first transistor, a first resistor connected to one end of the second transistor, and a second resistor connected in series with the first resistor.

[0022] The above feedback voltage may be a node voltage between the first resistor and the second resistor.

[0023] When the feedback voltage is higher than the reference voltage, the EOC signal is output as a High value, and the multiplexer can select the EOC signal and apply it to the charging circuit.

[0024] A pulse current-based battery charging device according to one embodiment of the disclosed invention may include a latch comparator that receives a reference voltage and a feedback voltage and operates based on a clock signal generated by a clock generator, a multiplexer that selects and outputs an EOC (End of Charge) signal or the clock signal based on an output voltage of the latch comparator, and a charging circuit that, when receiving the clock signal from the multiplexer, outputs a pulse current that alternately includes a charging section and a reset section having a value of 0 A.

[0025] A pulse current-based battery charging device according to one embodiment of the disclosed invention has an advantage in that the current applied to the battery can be configured as a pulse current rather than a constant current, thereby feeding back the charging voltage of the battery.

[0026] In addition, a pulse current-based battery charging device according to one embodiment of the disclosed invention has an advantage of being able to compensate for a voltage drop phenomenon due to the BIR (Built In Resistance) of the battery.

[0027] In addition, a pulse current-based battery charging device according to one embodiment of the disclosed invention has the advantage of reducing the size and complexity of the system by utilizing a latch comparator that performs the role of a 1-bit ADC and a pulse current.

[0028] FIG. 1 is a block diagram of a pulse current-based battery charging system according to one embodiment of the disclosed invention.

[0029] FIG. 2 is a diagram illustrating a pulse current-based battery charging process according to one embodiment of the disclosed invention.

[0030] FIG. 3 is a diagram illustrating a circuit used in a pulse current-based battery charging device according to one embodiment of the disclosed invention.

[0031] FIG. 4 is a diagram showing the state of the battery charging device circuit shown in FIG. 3 at a time when the battery is being charged.

[0032] FIG. 5 is a diagram showing the state at the end of battery charging in the circuit of the battery charging device illustrated in FIG. 3.

[0033] FIG. 6 is a flow chart illustrating a pulse current-based battery charging method according to one embodiment of the disclosed invention.

[0034] FIG. 7 is a diagram illustrating a pulse current-based battery charging device according to one embodiment of the disclosed invention, separately illustrating a latch comparator, a D-flip-flop, and a MUX.

[0035] FIG. 8 is a diagram illustrating digital signal timing at a transition point in a pulse current-based battery charging device according to one embodiment of the disclosed invention.

[0036] FIG. 9 is a diagram comparing the area of ​​a pulse current-based battery charging device according to one embodiment of the disclosed invention and a BIR compensation battery charging device according to the prior art.

[0037] FIG. 10 is a diagram comparing the complexity of a pulse current-based battery charging device according to one embodiment of the disclosed invention and a pulse current-based battery charging device according to the prior art.

[0038] FIG. 11 is a diagram comparing the charging times of a pulse current-based battery charging device according to one embodiment of the disclosed invention and a CC / CV charging device according to the prior art.

[0039] The embodiments described in this specification and the configurations illustrated in the drawings are merely preferred examples of the disclosed invention, and there may be various modified examples that can replace the embodiments and drawings of this specification at the time of filing of this application.

[0040] Additionally, the same reference numbers or symbols presented in each drawing of this specification represent parts or components that perform substantially the same function.

[0041] Additionally, the terminology used herein is for the purpose of describing embodiments and is not intended to limit and / or restrict the disclosed invention. Singular expressions include plural expressions unless the context clearly dictates otherwise.

[0042] In this specification, terms such as “include” or “have” are intended to specify the presence of a feature, number, step, operation, component, part or combination thereof described in the specification, but do not preclude the possibility of the presence or addition of one or more other features, numbers, steps, operations, components, parts or combinations thereof.

[0043] Additionally, terms including ordinal numbers such as “first,” “second,” etc., used herein may be used to describe various components, but the components are not limited by the terms, and the terms are used only for the purpose of distinguishing one component from another.

[0044] For example, without departing from the scope of the present invention, a first component could be referred to as a second component, and similarly, a second component could also be referred to as a first component. The term "and / or" includes any combination of a plurality of related listed items or any one of a plurality of related listed items.

[0045] Hereinafter, embodiments according to the present invention will be described in detail with reference to the attached drawings.

[0046]

[0047] FIG. 1 is a block diagram of a pulse current-based battery charging system according to one embodiment of the disclosed invention. FIG. 2 is a graph illustrating a pulse current-based battery charging process according to one embodiment of the disclosed invention.

[0048] Referring to FIG. 1, in a pulse current-based battery charging system according to one embodiment of the disclosed invention, a peak value of a pulse current applied to a battery is defined as IPC, an input voltage of a charging circuit is defined as VIN, a battery supply voltage is defined as VBAT, and when a battery is modeled as an RC circuit having a battery resistor and a battery capacitor, a battery charging voltage excluding the BIR (Built in Resistance) effect can be defined as VCELL.

[0049] More specifically, the pulse current (IPC) of a pulse current-based battery charging system according to one embodiment of the disclosed invention may include alternating charging periods and reset periods.

[0050] For example, in a pulse current-based battery charging circuit according to one embodiment of the disclosed invention, in the charging section, a pulse current IPC flows constantly at a peak value, and a voltage difference occurs between the battery supply voltage VBAT and the battery charging voltage VCELL due to the influence of the BIR (Built in Resistance) resulting therefrom.

[0051] Additionally, in a pulse current-based battery charging circuit according to one embodiment of the disclosed invention, the value of the pulse current in the reset section is 0 A.

[0052] Accordingly, the battery can obtain an open circuit voltage, and at this point, the potential of the node of the battery supply voltage VBAT and the node of the battery charge voltage VCELL are the same, so the BIR effect can be ignored.

[0053] Therefore, in the pulse current-based battery charging circuit according to the disclosed invention, the comparator compares the reference voltage VREF with the battery charging voltage VCELL, and based on the comparison result, the charge control block (CCB) adjusts the gate voltage of the transistor to determine whether to continue or stop charging.

[0054] In other words, as illustrated in FIG. 2, in a charging section where the pulse current IPC is applied at a peak value other than 0 A, a voltage difference due to BIR occurs between the battery supply voltage VBAT and the battery charge voltage VCELL, but the disclosed invention has a technical effect of being able to receive feedback of VCELL by designing a reset section where the pulse current IPC is 0 A so that the battery supply voltage VBAT and the battery charge voltage VCELL have the same value.

[0055] In addition, the pulse current-based battery charging circuit according to the disclosed invention has a technical effect of eliminating the process of performing complex calculations by utilizing only a latch comparator (LC) that acts as a 1-bit ADC and pulse current to compensate for the problem phenomenon caused by the BIR (Built in Resistance) of a physically inaccessible battery, and at the same time, significantly reducing the system size and complexity without using external components, thereby drastically reducing the impact on the form factor of the device.

[0056] In addition, the pulse current-based battery charging circuit according to the disclosed invention has a technical effect of improving the convenience of use of the battery by utilizing pulse current with parameters such as frequency and duty cycle that can extend the life of the battery compared to the constant current / constant voltage (CC / CV) method.

[0057] Hereinafter, a circuit diagram of a pulse current-based battery charging device according to the disclosed invention will be described.

[0058]

[0059] FIG. 3 is a circuit diagram illustrating a pulse current-based battery charging device according to one embodiment of the disclosed invention. FIG. 4 is a circuit diagram illustrating a state of the battery charging device illustrated in FIG. 3 at a point in time when the battery is being charged. FIG. 5 is a circuit diagram illustrating a state of the battery charging device illustrated in FIG. 3 at a point in time when the battery charging is complete.

[0060] Referring to FIG. 3, a pulse current-based battery charging device according to one embodiment of the disclosed invention may include a clock generator (CG) for generating a clock signal, a reference generator (RG) for generating a reference voltage, a latch comparator (LC) for receiving a reference voltage and a feedback voltage and operating based on a clock signal generated by the clock generator (CG), a multiplexer (MUX) for selecting and outputting one of an EOC (End Of Charge) signal and a clock signal, and a charging circuit (100) for outputting a pulse current for charging a battery based on the clock signal.

[0061] More specifically, the battery charging device according to the disclosed invention can utilize a latch comparator (LC) that operates based on a system clock of a clock generator (CG) as a comparator, so as to simplify the system structure and eliminate the need for complex calculations.

[0062] Additionally, a pulse current based battery charging device according to one embodiment of the disclosed invention may include a D flip flop (D-FF) connected to an output terminal of a latch comparator (LC) to output an EOC (End Of Charge) signal.

[0063] Specifically, the charging circuit (100) of the battery charging device according to the disclosed invention may include a first transistor (M1) and a second transistor (M2) to which the gate node of the first transistor (M1) is connected.

[0064] Therefore, the first transistor (M1) and the second transistor (M2) can be configured as mirroring transistors, thereby preventing immediate termination of charging.

[0065] Additionally, the charging circuit (100) of the battery charging device according to the disclosed invention may include a third transistor (M3) having one end connected to a multiplexer (MUX) and the other end connected to one end of a first transistor (M1).

[0066] Additionally, the charging circuit (100) of the battery charging device according to the disclosed invention may include a first resistor (R1) connected to one end of a second transistor (M2) and a second resistor (R2) connected in series with the first resistor (R1).

[0067] These first resistor (R1) and second resistor (R2) can be connected in parallel with a battery configured as an RC circuit.

[0068] In addition, the charging circuit (100) of the battery charging device according to the disclosed invention can be connected to the input terminal of the battery and apply a pulse current IPC to the battery.

[0069] More specifically, the input terminal of the battery can be connected to one end of the second transistor (M2) of the charging circuit (100).

[0070] Accordingly, the battery charging device according to the disclosed invention can receive VFB, which is a feedback voltage and VREF, which is a voltage of a node between a first resistor (R1) and a second resistor (R2), as inputs to a latch comparator (LC), and output an EOC signal to a charging circuit (100) according to the relative magnitudes of VFB and VREF.

[0071] Details regarding the operation of these charging devices are described below.

[0072] Referring to FIG. 4, the latch comparator (LC) compares the feedback voltage VFB, which is divided by R1 and R2 in VBAT, with VREF at the falling edge of the clock signal generated by the clock generator (CG).

[0073] Next, the output voltages VOP and VON of the latch comparator (LC) are transmitted to the NOR gate and the D flip-flop (D-FF).

[0074] At this time, if the feedback voltage VFB is lower than the reference voltage VREF, the EOC signal can be output as a LOW value.

[0075] Accordingly, the multiplexer (MUX) selects the selection signal (S) of the multiplexer (MUX) as a LOW value based on the EOC signal, which is an output signal of the D flip-flop (D-FF) and a selection signal of the MUX, so that a pulse voltage based on a clock signal can be selected and transmitted to the charging circuit (100).

[0076] Accordingly, the first transistor (M1) and the second transistor (M2), which are mirroring transistors, can be controlled by the transmitted pulse voltage and pulse current flow.

[0077] Also, referring to FIG. 5, the latch comparator (LC) compares the feedback voltage VFB, which is divided by R1 and R2, with VREF for the battery supply voltage VBAT at the falling edge of the clock signal generated by the clock generator (CG).

[0078] Next, the output voltages VOP and VON of the latch comparator (LC) are transmitted to the NOR gate and the D flip-flop (D-FF).

[0079] At this time, if the feedback voltage VFB is higher than the reference voltage VREF, the EOC signal can be output as a HIGH value.

[0080] Accordingly, the multiplexer (MUX) can select the selection signal (S) of the multiplexer (MUX) as a HIGH value and output the EOC signal based on the EOC signal, which is an output signal of the D flip-flop (D-FF) and a selection signal of the MUX, being a HIGH value.

[0081] Therefore, the EOC signal, which is an output signal of the multiplexer (MUX), turns off the first transistor (M1) and the second transistor (M2), and the charging process can be terminated.

[0082]

[0083] Fig. 6 is a flow chart illustrating a pulse current-based battery charging method according to one embodiment of the disclosed invention. Fig. 7 is a diagram illustrating a latch comparator, a D-flip-flop, and a MUX separately in a pulse current-based battery charging device according to one embodiment of the disclosed invention. Fig. 8 is a diagram illustrating digital signal timing at a transition point in a pulse current-based battery charging device according to one embodiment of the disclosed invention.

[0084] Referring to FIGS. 6 to 8, VOP and VON, which are output voltages of a latch comparator (LC) of a battery charging device according to one embodiment of the disclosed invention, may have HIGH values ​​when the feedback voltage VFB exceeds the reference voltage VREF and when the reference voltage VREF exceeds the feedback voltage VFB, respectively.

[0085] Specifically, when the feedback voltage VFB is lower than the reference voltage VREF, the NEGATIVE output voltage of the latch comparator (LC) can have a HIGH value, and the POSITIVE output voltage of the latch comparator (LC) can have a LOW value.

[0086] Conversely, when the feedback voltage VFB is higher than the reference voltage VREF, the NEGATIVE output voltage of the latch comparator (LC) can have a LOW value, and the POSITIVE output voltage of the latch comparator (LC) can have a HIGH value.

[0087] Afterwards, the output voltage VOP of the latch comparator (LC) is transmitted to the NOR and D-FF, and the output voltage VON can be transmitted to another input node of the NOR.

[0088] The D flip-flop (D-FF) can operate to generate an EOC signal based on the output voltage of the latch comparator (LC) immediately after it is generated.

[0089] Specifically, the battery charging device according to the disclosed invention can use a D-pulse signal generated later than a clock signal as a clock source of a D flip-flop (D-FF) to ensure the reliability of such operation.

[0090] More specifically, the D flip-flop (D-FF) outputs a VOP signal at each falling edge of the D-pulse, and maintains the output signal when it is not the falling edge, thereby generating a stable EOC signal.

[0091] If the EOC signal is LOW, the selection signal (S) of the multiplexer (MUX) also becomes LOW, so that the clock signal can be transmitted to the charging circuit (100).

[0092] More specifically, when the feedback voltage VFB is lower than the reference voltage VREF, the EOC signal can have a LOW value.

[0093] Conversely, when the EOC signal is High, the selection signal (S) of the multiplexer (MUX) also becomes High, so that the EOC signal can be directly transmitted to the charging circuit (100), and can indicate that charging is complete.

[0094] More specifically, when the feedback voltage VFB is higher than the reference voltage VREF, the EOC signal can have a HIGH value.

[0095] In addition, referring to FIG. 8, the battery charging device according to the disclosed invention can compare the reference voltage VREF and the feedback voltage VFB at the falling edge of the clock signal of the clock generator (CG).

[0096] More specifically, the latch comparator (LC) can accurately monitor VCELL by comparing the reference voltage VREF and the feedback voltage VFB at the falling edge of the system clock (CLK).

[0097] Typically, kickback noise occurs in latch comparators (LCs), which is caused by parasitic capacitance between the drain and gate of the input MOSFET.

[0098] Additionally, this kickback noise can create a path for current flow to the input node, which can in turn affect the input voltage and cause erroneous output voltages from the comparator.

[0099] Therefore, the charging device according to the disclosed invention can prevent interference due to kickback noise by adding an amplifier before the latch comparator (LC).

[0100] More specifically, the amplifier can be configured to amplify two input signals to a sufficient level for the next latch comparator to generate a more accurate output voltage.

[0101] Additionally, these amplifiers have a larger input impedance than the comparator, which reduces the sensitivity to the output impedance of the previous circuit, thus reducing kickback noise.

[0102] Additionally, in the charging device of the disclosed invention, the comparator is designed to have a relatively small width in order to mitigate the influence of current flowing through parasitic capacitance.

[0103] Accordingly, the disclosed invention has a technical effect of effectively reducing noise of the feedback voltage VFB node and accurately detecting the battery charging voltage VCELL.

[0104]

[0105] FIG. 9 is a diagram comparing the area of ​​a pulse current-based battery charging device according to an embodiment of the disclosed invention and a BIR compensation battery charging device according to the prior art. FIG. 10 is a diagram comparing the complexity of a pulse current-based battery charging device according to an embodiment of the disclosed invention and a pulse current type battery charging device according to the prior art. FIG. 11 is a diagram comparing the charging time of a pulse current-based battery charging device according to an embodiment of the disclosed invention and a CC / CV charging device according to the prior art.

[0106] Referring to FIG. 9, the performance of a pulse current-based battery charging device according to one embodiment of the disclosed invention can be compared with that of an existing charging system.

[0107] More specifically, it can be seen that the charging device according to the disclosed invention has a much smaller chip area compared to the BIR compensation system according to the prior art.

[0108] Also, referring to FIG. 10, compared to a charging system according to the prior art, the charging device according to the disclosed invention has a technical effect that it can be implemented with a much simpler structure.

[0109] In addition, the charging device according to the disclosed invention has a technical effect of ensuring improved battery life by applying parameters optimized for the battery model to the charging current.

[0110] Additionally, as illustrated in FIG. 11, in order to compare the performance of a charging system according to the prior art and a charging device according to the disclosed invention, a charging time of approximately 32.7 ms was estimated assuming an ICC of 5 mA for charging from 0 V to 4.2 V.

[0111] Therefore, as can be seen in FIG. 11, the pulse current-based charging device according to the disclosed invention has a technical effect of reducing the charging time by about 20% compared to the charging system according to the prior art.

[0112] A pulse current-based battery charging device according to one embodiment of the disclosed invention has an advantage in that the current applied to the battery can be configured as a pulse current rather than a constant current, thereby feeding back the charging voltage of the battery.

[0113] In addition, a pulse current-based battery charging device according to one embodiment of the disclosed invention has an advantage of being able to compensate for a voltage drop phenomenon due to the BIR (Built In Resistance) of the battery.

[0114] In addition, a pulse current-based battery charging device according to one embodiment of the disclosed invention has the advantage of reducing the size and complexity of the system by utilizing a latch comparator that performs the role of a 1-bit ADC and a pulse current.

[0115] The devices described above may be implemented as hardware components, software components, and / or a combination of hardware components and software components. For example, the devices and components described in the embodiments may be implemented using one or more general-purpose computers or special-purpose computers, such as, for example, a processor, a controller, an arithmetic logic unit (ALU), a digital signal processor, a microcomputer, a field programmable array (FPA), a programmable logic unit (PLU), a microprocessor, or any other device capable of executing instructions and responding to them. The processing device may execute an operating system (OS) and one or more software applications running on the operating system. Furthermore, the processing device may access, store, manipulate, process, and generate data in response to the execution of the software. For ease of understanding, the processing device is sometimes described as being used singly; however, those skilled in the art will appreciate that the processing device may include multiple processing elements and / or multiple types of processing elements. For example, the processing device may include multiple processors, or one processor and one controller. Additionally, other processing configurations, such as parallel processors, are also possible.

[0116] Software may include a computer program, code, instructions, or a combination of one or more of these, which may configure a processing device to perform a desired operation or may independently or collectively command the processing device. The software and / or data may be embodied in any type of machine, component, physical device, virtual equipment, computer storage medium, or device for interpretation by the processing device or for providing instructions or data to the processing device. The software may also be distributed over networked computer systems and stored or executed in a distributed manner. The software and data may be stored on one or more computer-readable recording media.

[0117] The method according to the embodiment may be implemented in the form of program commands that can be executed through various computer means and recorded on a computer-readable medium. The computer-readable medium may include program commands, data files, data structures, etc., alone or in combination. The program commands recorded on the medium may be those specially designed and configured for the embodiment or may be those known and available to those skilled in the art of computer software. Examples of the computer-readable recording medium include magnetic media such as hard disks, floppy disks, and magnetic tapes, optical media such as CD-ROMs and DVDs, magneto-optical media such as floptical disks, and hardware devices specially configured to store and execute program commands such as ROMs, RAMs, and flash memories. Examples of program commands include not only machine language codes such as those generated by a compiler, but also high-level language codes that can be executed by a computer using an interpreter, etc.

[0118] Although the embodiments have been described with limited examples and drawings, those skilled in the art will appreciate that various modifications and variations can be made based on the above teachings. For example, appropriate results can be achieved even if the described techniques are performed in a different order than described, and / or components of the described systems, structures, devices, circuits, etc. are combined or combined in a different manner than described, or are replaced or substituted with other components or equivalents. Therefore, other implementations, other embodiments, and equivalents of the claims also fall within the scope of the claims described below.

Claims

1. A clock generator that generates a clock signal; A reference generator that generates a reference voltage; A latch comparator that receives the reference voltage and feedback voltage and operates based on the clock signal; A D flip-flop connected to the output terminal of the above latch comparator and outputting an EOC (End Of Charge) signal; A multiplexer that selects and outputs one of the EOC signal and the clock signal; and A charging circuit for outputting a pulse current for charging a battery based on the clock signal; characterized in that it includes; Pulse current based battery charger.

2. In paragraph 1, The above pulse current is characterized by including a charging section and a reset section that operate alternately, Pulse current based battery charger.

3. In paragraph 2, Characterized in that the value of the pulse current in the reset section is 0 A. Pulse current based battery charger.

4. In paragraph 1, The above charging circuit 1st transistor; A second transistor having a gate node connected to the gate node of the first transistor; A third transistor having one end connected to the multiplexer and the other end connected to one end of the first transistor; a first resistor connected to one end of the second transistor; and characterized in that it comprises a second resistor connected in series with the first resistor; Pulse current based battery charger.

5. In paragraph 4, The input terminal of the above battery is characterized in that it is connected to one end of the second transistor. Pulse current based battery charger.

6. In paragraph 4, The above feedback voltage is characterized in that it is a node voltage between the first resistor and the second resistor. Pulse current based battery charger.

7. In paragraph 1, When the feedback voltage is lower than the reference voltage, the EOC signal is output as a Low value. Pulse current based battery charger.

8. In paragraph 1, When the feedback voltage is higher than the reference voltage, the EOC signal is output as a High value. Pulse current based battery charger.

9. In paragraph 8, When the multiplexer outputs the EOC signal having a High value, charging of the battery is terminated, Pulse current based battery charger.

10. A clock generator that generates a clock signal; A charging circuit that outputs a pulse current for charging a battery based on the above clock signal; A latch comparator that receives a reference voltage and a feedback voltage of the charging circuit and operates based on the clock signal to output a first output voltage and a second output voltage; and A multiplexer for applying an EOC (End of Charge) signal or the clock signal to the charging circuit based on the first output voltage and the second output voltage of the latch comparator, characterized in that it includes; Pulse current based battery charger.

11. In paragraph 10, The pulse current includes a charging section and a reset section that operate alternately, and the value of the pulse current in the reset section is characterized in that it is 0 A. Pulse current based battery charger.

12. In paragraph 10, The above charging circuit 1st transistor; A second transistor having a gate node connected to the gate node of the first transistor; A third transistor having one end connected to the multiplexer and the other end connected to one end of the first transistor; a first resistor connected to one end of the second transistor; and characterized in that it comprises a second resistor connected in series with the first resistor; Pulse current based battery charger.

13. In paragraph 12, The above feedback voltage is characterized in that it is a node voltage between the first resistor and the second resistor. Pulse current based battery charger.

14. In paragraph 13, When the feedback voltage is higher than the reference voltage, the EOC signal is output as a High value, and the multiplexer selects the EOC signal and applies it to the charging circuit. Pulse current based battery charger.

15. A latch comparator that receives a reference voltage and a feedback voltage and operates based on a clock signal generated by a clock generator; A multiplexer that selects and outputs an EOC (End of Charge) signal or the clock signal based on the output voltage of the latch comparator; and A charging circuit that, when receiving the clock signal from the multiplexer, outputs a pulse current that alternately includes a charging section and a reset section having a value of 0A; Pulse current based battery charger.

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