Semiconductor device and manufacturing method therefor

Abstract

A semiconductor device and a manufacturing method therefor are disclosed. The semiconductor device comprises: a substrate; a first active pattern on the substrate; a first gate structure surrounding at least a portion of the first active pattern; a first source / drain area and a second source / drain area, which are respectively disposed on a first side and a second side of the first gate structure, the first side and the second side facing each other; and a first dielectric pattern disposed on a third side different from each of the first side and the second side of the first gate structure, wherein the first dielectric pattern includes a first portion of the first dielectric pattern disposed between the first source / drain area and the first side of the first gate structure and a second portion of the first dielectric pattern disposed between the second source / drain area and the second side of the first gate structure.

Description

Semiconductor device and manufacturing method thereof

[0001] The present invention relates to a semiconductor device and a method for manufacturing the same.

[0002]

[0003] The content described in this section merely provides background information for the present embodiment and does not constitute prior art.

[0004] Advances in semiconductor technology have led to increasing demands for higher storage capacity, faster processing systems, and higher performance. To meet these demands, the semiconductor industry continues to shrink the size of semiconductor devices, such as metal-oxide semiconductor field-effect transistors (MOSFETs), including planar MOSFETs and fin-type field-effect transistors (finFETs). This shrinking has increased the complexity of semiconductor manufacturing processes.

[0005] Meanwhile, in line with the trend of shrinking the size of semiconductor devices, various studies are being conducted to reduce the cell height of field-effect transistors.

[0006] In the case of forksheet FETs (FSFETs), cell height can be reduced by placing a dielectric between the N-type transistor and the P-type transistor. However, since one sidewall of the channel is in contact with the dielectric, the forksheet FET has the problem that a silicide pattern may not form in the source / drain region in contact with the dielectric, and the part of the sidewall of the channel in contact with the dielectric is not covered by the gate, which degrades electrical performance.

[0007]

[0008] An object of the present invention is to provide a semiconductor device and a method for manufacturing the same for including a dielectric pattern between transistors of the same type.

[0009] In addition, an object of the present invention is to provide a semiconductor device and a method for manufacturing the same so that a channel region is completely surrounded by a gate electrode in a gate all-around structure.

[0010] In addition, an object of the present invention is to provide a semiconductor device and a method for manufacturing the same in which a silicide pattern can be arranged to surround a source / drain region.

[0011] The purposes of the present invention are not limited to those mentioned above. Other purposes and advantages of the present invention not mentioned above can be understood through the following description and will be more clearly understood through the embodiments of the present invention. Furthermore, it will be readily apparent that the purposes and advantages of the present invention can be realized by the means and combinations thereof set forth in the claims.

[0012]

[0013] A semiconductor device according to an embodiment of the present invention includes a substrate, a first active pattern on the substrate, a first gate structure surrounding at least a portion of the first active pattern, a first source / drain region and a second source / drain region respectively disposed on first and second sides of the first gate structure facing each other, and a first dielectric pattern disposed on a third side different from each of the first and second sides of the first gate structure, wherein the first dielectric pattern includes a first portion of the first dielectric pattern disposed between the first source / drain region and the first side of the first gate structure, and a second portion of the first dielectric pattern disposed between the second source / drain region and the second side of the first gate structure.

[0014] Additionally, the first gate structure includes a portion of the first gate structure disposed between the first active pattern and the first dielectric pattern along a second direction intersecting a first direction perpendicular to the first gate structure and the substrate.

[0015] Additionally, the part of the first gate structure is disposed between the first part and the second part of the first dielectric pattern.

[0016] In addition, it further includes a first silicide pattern disposed between the first source / drain region and the first dielectric pattern, and a second silicide pattern disposed between the second source / drain region and the first dielectric pattern.

[0017] In addition, the substrate further includes a second active pattern and a second gate structure surrounding at least a portion of the second active pattern, wherein the first dielectric pattern is disposed between the first gate structure and the second gate structure, and is disposed between the first active pattern and the second active pattern, a first region of the first dielectric pattern between the first active pattern and the second active pattern has a first width, a second region of the first dielectric pattern between the first gate structure and the second gate structure has a second width, and the first width and the second width are different, and the first region of the first dielectric pattern includes the first portion.

[0018] Additionally, the first width is greater than the second width.

[0019] In addition, the second gate structure further includes a third source / drain region and a fourth source / drain region respectively disposed on the fifth and sixth sides facing each other, and the first dielectric pattern includes a third portion of the first dielectric pattern disposed between the third source / drain region and the fifth side of the second gate structure and a fourth portion of the first dielectric pattern disposed between the fourth source / drain region and the sixth side of the second gate structure, and the first region of the first dielectric pattern includes the third portion.

[0020] Additionally, a third region of the first dielectric pattern between the first source / drain region and the third source / drain region has a third width, a fourth region of the first dielectric pattern between the second source / drain region and the fourth source / drain region has a fourth width, and the third width and the fourth width are different.

[0021] Additionally, a first portion of the first gate structure disposed between the first portion and the second portion of the first dielectric pattern has a first width, a second portion of the first gate structure disposed between the first source / drain and the second source / drain and disposed on the first active pattern has a second width, and the first width of the first portion of the first gate structure and the second width of the second portion of the first gate structure are different.

[0022] Additionally, the first portion of the first dielectric pattern further includes a first indented portion that is indented into the first source / drain region.

[0023] Additionally, the second portion of the first dielectric pattern further includes a second indented portion that is indented into the first source / drain region.

[0024] A semiconductor device according to an embodiment of the present invention includes a first type first transistor including a substrate, a first active pattern on the substrate, and a first gate structure surrounding the first active pattern, a second type second transistor including a second active pattern on the substrate, and a second gate structure surrounding the second active pattern, a third transistor of the second type including a patterned first dielectric pattern disposed between the first transistor and the second transistor, a third active pattern on the substrate, and a third gate structure surrounding the third active pattern, and a patterned second dielectric pattern disposed between the second transistor and the third transistor, wherein a first region of the second dielectric pattern between the second active pattern and the third active pattern has a first width, a second region of the second dielectric pattern between the second gate structure and the third gate structure has a second width, and the first width and the second width are different.

[0025] In addition, the first gate structure further includes a first source / drain region and a second source / drain region respectively disposed on first and second sides facing each other, and the first dielectric pattern is disposed on a third side different from each of the first side and the second side, and the first dielectric pattern includes a first portion of the first dielectric pattern disposed between the first source / drain region and the first side of the first gate structure, and a second portion of the first dielectric pattern disposed between the second source / drain region and the second side of the first gate structure.

[0026] In addition, the second gate structure further includes a third source / drain region and a fourth source / drain region respectively disposed on the fifth and sixth sides facing each other, and the first dielectric pattern includes a third portion of the first dielectric pattern disposed between the third source / drain region and the fifth side of the second gate structure, and a fourth portion of the first dielectric pattern disposed between the fourth source / drain region and the sixth side of the second gate structure.

[0027] Additionally, the second dielectric pattern includes a fifth portion of the second dielectric pattern disposed between the third source / drain region and the fifth side of the second gate structure, and a sixth portion of the second dielectric pattern disposed between the fourth source / drain region and the sixth side of the second gate structure.

[0028] Additionally, a third region of the first dielectric pattern between the first source / drain region and the third source / drain region has a third width, a fourth region of the first dielectric pattern between the second source / drain region and the fourth source / drain region has a fourth width, and the third width and the fourth width are different.

[0029] Additionally, a first portion of the first gate structure disposed between the first portion and the second portion of the first dielectric pattern has a first width, a second portion of the first gate structure disposed between the first source / drain and the second source / drain and disposed on the first active pattern has a second width, and the first width of the first portion of the first gate structure and the second width of the second portion of the first gate structure are different.

[0030] Additionally, the first portion of the first dielectric pattern further includes a first indented portion that is indented into the first source / drain region.

[0031] Additionally, the second portion of the first dielectric pattern further includes a second indented portion that is indented into the first source / drain region.

[0032] A method for manufacturing a semiconductor device according to an embodiment of the present invention includes the steps of forming a fin pattern by alternately stacking a first layer and a second layer on a substrate and then patterning them, forming a dummy wall on the substrate that surrounds the fin pattern, patterning the dummy wall to form a first dummy pattern and a second dummy pattern that are spaced apart from each other, forming a first dielectric pattern that is formed between the first dummy pattern and the second dummy pattern and covers sidewalls of each of the first dummy pattern and the second dummy pattern, removing a portion of the fin pattern on the side of the first dummy pattern to form a first source / drain region, removing the second dummy pattern and the second layer to form a first gate structure that surrounds the first layer, and removing the first dummy pattern.

[0033] Additionally, after the first dummy pattern is removed, the method further includes forming a silicide pattern between the first dielectric pattern and the first source / drain region.

[0034] Additionally, the first dielectric pattern includes a first portion of the first dielectric pattern disposed between the first source / drain region and the first gate structure.

[0035] In addition, the step of forming the first dummy pattern and the second dummy pattern further includes the step of forming a third dummy pattern spaced apart from the first dummy pattern and the second dummy pattern, wherein the first dielectric pattern is further formed between the second dummy pattern and the third dummy pattern and further formed to cover a sidewall of the third dummy pattern, and further includes the step of forming a second source / drain region by removing another part of the fin pattern on the side of the third dummy pattern, and the step of removing the third dummy pattern.

[0036] Additionally, the first dielectric pattern includes a first portion of the first dielectric pattern disposed between the first source / drain region and the first side of the first gate structure, and a second portion of the first dielectric pattern disposed between the second source / drain region and the second side of the first gate structure.

[0037]

[0038] The semiconductor device of the present invention and its manufacturing method can reduce the chip size by including a dielectric pattern between transistors of the same type.

[0039] In addition, the semiconductor device of the present invention and its manufacturing method can improve electrical performance by ensuring that the channel region is completely surrounded by the gate electrode in a gate all-around structure.

[0040] In addition to the above-described contents, the specific effects of the present invention are described together with the specific matters for carrying out the invention below.

[0041]

[0042] FIG. 1 is a perspective view of a portion of a semiconductor device according to some embodiments of the present invention.

[0043] Figure 2 is a cross-sectional view taken along line AA' of Figure 1.

[0044] Figure 3 is a cross-sectional view taken along line BB' of Figure 1.

[0045] Figure 4 is a cross-sectional view taken along line CC' of Figure 1.

[0046] Figure 5 is a cross-sectional view taken along line CC' of Figure 1.

[0047] Figure 6 is a cross-sectional view taken along line CC' of Figure 1.

[0048] Figure 7 is a cross-sectional view taken along line CC' of Figure 1.

[0049] Figure 8 is a cross-sectional view taken along line CC' of Figure 1.

[0050] Figure 9 is a cross-sectional view taken along line CC' of Figure 1.

[0051] Figure 10 is a cross-sectional view taken along line CC' of Figure 1.

[0052] Fig. 11 is a cross-sectional view taken along line CC' of Fig. 1.

[0053] Fig. 12 is a cross-sectional view taken along line CC' of Fig. 1.

[0054] FIG. 13 is a flowchart illustrating a method for manufacturing a semiconductor device according to some embodiments of the present invention.

[0055] FIG. 14 and FIG. 15 are drawings for explaining step S100 of FIG. 13, and may be perspective views of a semiconductor device.

[0056] FIG. 16 is a drawing for explaining step S200 of FIG. 13, and may be a perspective view of a semiconductor device.

[0057] FIG. 17 is a drawing for explaining step S300 of FIG. 13, and may be a perspective view of a semiconductor device.

[0058] FIG. 18 is a drawing for explaining step S400 of FIG. 13, and may be a perspective view of a semiconductor device.

[0059] FIG. 19 and FIG. 20 are drawings for explaining step S500 of FIG. 13, and may be perspective views of a semiconductor device.

[0060] Figures 21 to 24 are drawings for explaining step S600 of Figure 13.

[0061] Figures 25 to 27 are cross-sectional views taken along line YY of Figure 21.

[0062]

[0063] The terms and words used in this specification and claims should not be interpreted based on their general or dictionary meanings. In accordance with the principle that inventors can define the concepts of terms and words to best describe their inventions, they should be interpreted in a way that is consistent with the technical concept of the present invention. Furthermore, the embodiments described in this specification and the configurations depicted in the drawings are merely examples of how the present invention can be realized and do not fully represent the technical concept of the present invention. Therefore, it should be understood that various equivalents, modifications, and applicable examples may exist as of the time of filing.

[0064] The terms first, second, A, B, etc. used in this specification and claims may be used to describe various components, but the components should not be limited by these terms. These terms are used only for the purpose of distinguishing one component from another. For example, without departing from the scope of the present invention, the first component may be referred to as the second component, and similarly, the second component may also be referred to as the first component. The term "and / or" includes any combination of a plurality of related listed items or any item among a plurality of related listed items.

[0065] The terminology used in this specification and claims is for the purpose of describing specific embodiments only and is not intended to limit the present invention. Singular expressions include plural expressions unless the context clearly dictates otherwise. It should be understood that terms such as "comprise" or "have" in this application do not preclude the presence or addition of features, numbers, steps, operations, components, parts, or combinations thereof described in the specification.

[0066] Unless otherwise defined, all terms used herein, including technical or scientific terms, have the same meaning as commonly understood by one of ordinary skill in the art to which the present invention belongs.

[0067] Terms defined in commonly used dictionaries should be interpreted as having meanings consistent with their meanings within the context of the relevant technology, and should not be interpreted in an idealized or overly formal sense unless explicitly defined herein. Furthermore, each component, process, procedure, or method included in each embodiment of the present invention may be shared within the scope of non-contradictory technical aspects.

[0068]

[0069] Hereinafter, semiconductor devices according to some embodiments of the present invention will be described with reference to FIGS. 1 to 4.

[0070] FIG. 1 is a perspective view of a portion of a semiconductor device according to some embodiments of the present invention. FIG. 2 is a cross-sectional view taken along line AA' of FIG. 1. FIG. 3 is a cross-sectional view taken along line BB' of FIG. 1. FIG. 4 is a cross-sectional view taken along line CC' of FIG. 1. FIG. 4 is a cross-sectional view illustrating not only the first transistor of FIG. 1 but also other transistors included in a semiconductor device according to some embodiments of the present invention, taken in a direction parallel to the upper surface of the substrate.

[0071]

[0072] Referring to FIGS. 1 to 4, a semiconductor device according to some embodiments of the present invention may include at least one transistor. FIG. 1 is a perspective view of a first transistor (TR1), which is one transistor included in the semiconductor device. The semiconductor device according to some embodiments of the present invention may further include a transistor of the same or different type as the first transistor (TR1). For example, when a second transistor (TR2 of FIG. 4) is further included, the second transistor (TR2) may be arranged such that a first dielectric pattern (200) is arranged between the first transistor (TR1) and the second transistor (TR2). In addition, for example, when a third transistor (TR3 of FIG. 4) is further included, the third transistor (TR3) may be arranged such that a second dielectric pattern (300 of FIG. 4) is arranged between the second transistor (TR2) and the third transistor (TR3). Each transistor may include a shape described with reference to FIGS. 1 to 3, respectively. In Fig. 4, the illustrations of the first silicide pattern and the second silicide pattern are omitted to simplify the illustration.

[0073]

[0074] A first transistor (TR1) of a semiconductor device according to some embodiments of the present invention may include a substrate (100), a first active pattern (141), a first gate structure (111), a first source / drain region (121), a second source / drain region (122), and a first dielectric pattern (200).

[0075] The substrate (100) may include a first region (101) of the substrate (100) and a second region (102) of the substrate (100). The first region (101) of the substrate (100) may be a PTS (Punch Through Stop) ion implantation region. The second region (102) of the substrate (100) may include an insulating material.

[0076]

[0077] A first transistor (TR1) of a semiconductor device according to some embodiments of the present invention may include a first active pattern (141) on a substrate (100). The first active pattern (141) may be a channel region. A first source / drain region (121) and a second source / drain region (122) may be disposed at both ends of the first active pattern (141). That is, the first active pattern (141) may be disposed between the first source / drain region (121) and the second source / drain region (122). For example, a plurality of first active patterns (141) may be disposed to be spaced apart from each other along a first direction (D1) that is perpendicular to the substrate (100) between the first source / drain region (121) and the second source / drain region (122).

[0078]

[0079] The first active pattern (141) may be surrounded by the first gate structure (111). For example, the first gate structure (111) may surround at least a portion of the first active pattern (141).

[0080] The first gate structure (111) may include a first gate electrode (111e) and a first gate insulating film (161).

[0081] The first gate electrode (111e) can surround at least a portion of the first active pattern (141). The first gate electrode (111e) can be spaced apart from each of the first source / drain region (121) and the second source / drain region (122). The first gate electrode (111e) can be disposed between the first active pattern (141) and the substrate (100). The first gate electrode (111e) can be disposed between the first dielectric pattern (200) and the first active pattern (141).

[0082] The first gate insulating film (161) can surround at least a portion of the first gate electrode (111e). The first gate insulating film (161) can surround the first active pattern (141). The first gate insulating film (161) can be disposed between the first dielectric pattern (200) and the first gate electrode (111e). The first gate insulating film (161) can be disposed between the substrate (100) and the first gate electrode (111e). The first gate insulating film (161) can be disposed between the first gate electrode (111e) and the first active pattern (141).

[0083] The first gate electrode (111e) may include, for example, at least one of TiN, WN, TaN, Ru, TiC, TaC, Ti, Ag, Al, TiAl, TiAlN, TiAlC, TaCN, TaSiN, Mn, Zr, W, and Al. Alternatively, the first gate electrode (111e) may be made of Si, SiGe, or the like, which are not metals.

[0084]

[0085] The first gate insulating film (161) may include at least one film. The first gate insulating film (161) may include, for example, a silicon oxide film, a silicon oxynitride film, or a silicon nitride film. The first gate insulating film (161) may include, for example, a high-k dielectric insulating film including a high-k dielectric material having a higher dielectric constant than the silicon oxide film. For example, the high dielectric material may include, but is not limited to, one or more of hafnium oxide, hafnium silicon oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, or lead zinc niobate.

[0086]

[0087] The first gate structure (111) may include a first side (1111S) and a second side (1112S) that face each other. A first source / drain region (121) may be arranged on the first side (1111S) of the first gate structure (111). A second source / drain region (122) may be arranged on the second side (1112S) of the first gate structure (111).

[0088]

[0089] At least a portion of the first source / drain region (121) may be surrounded by a first silicide pattern (131). The first silicide pattern (131) may be disposed on both side walls and an upper surface of the first source / drain region (121) on the substrate (100). The second silicide pattern (132) may be disposed on both side walls and an upper surface of the second source / drain region (122) on the substrate (100). The first silicide pattern (131) may be disposed between the first source / drain region (121) and the first dielectric pattern (200). The second silicide pattern (132) may be disposed between the second source / drain region (122) and the first dielectric pattern (200).

[0090]

[0091] A spacer material (170) may be disposed between the first gate structure (111) and the first source / drain region (121). A spacer material (170) may be disposed between the first gate structure (111) and the second source / drain region (122). The spacer material (170) may surround a region of the first active pattern (141) other than a region surrounded by the first gate structure (111). For example, the spacer material (170) may surround a portion of the first active pattern (141) exposed by the first gate structure (111). The spacer material (170) may be disposed on the first dielectric pattern (200) and on the first gate structure (111).

[0092]

[0093] Each of the first source / drain region (121), the second source / drain region (122), and the first gate structure (111) may include a contact (150). The contact (150) may be disposed on each of the first source / drain region (121), the second source / drain region (122), and the first gate structure (111). A spacer material (170) may be disposed between the contacts (150).

[0094] The spacer material (170) may include, for example, at least one of silicon nitride (SiN), silicon oxynitride (SiON), silicon oxide (SiO2), silicon oxycarbonitride (SiOCN), and combinations thereof.

[0095]

[0096] The first dielectric pattern (200) may be arranged on the third side (1113S) and the fourth side (1114S) of the first gate structure (111). The third side (1113S) of the first gate structure (111) may be a side of the first gate structure (111) that is different from each of the first side (1111S) and the second side (1112S). The third side (1113S) and the fourth side (1114S) of the first gate structure (111) may face each other.

[0097] Between the first dielectric pattern (200) of the third side (1113S) of the first gate structure (111) and the first dielectric pattern (200) of the fourth side (1114S), a first source / drain region (121), a second source / drain region (122), a first active pattern (141), and a first gate structure (111) can be arranged.

[0098] The first dielectric pattern (200) may include a first portion (2001) disposed between the first source / drain region (121) and the first side (1111S) of the first gate structure (111). For example, a portion of the first active pattern (141) and the first portion (2001) of the first dielectric pattern (200) may be disposed between the first source / drain region (121) and the first gate structure (111). The first portion (2001) of the first dielectric pattern (200) may overlap the first gate structure (111) and the first source / drain region (121) along a third direction (D3) intersecting the first direction (D1).

[0099] The third direction (D3) may be a direction that coincides with the direction in which the first active pattern (141) extends between the first source / drain region (121) and the second source / drain region (122).

[0100] The first dielectric pattern (200) may include a second portion (2002) disposed between the second source / drain region (122) and the second side (1112S) of the first gate structure (111). For example, a portion of the first active pattern (141) and the second portion (2002) of the first dielectric pattern (200) may be disposed between the second source / drain region (122) and the first gate structure (111). The second portion (2002) of the first dielectric pattern (200) may overlap the first gate structure (111) and the second source / drain region (122) along the third direction (D3).

[0101]

[0102] The dielectric pattern of the semiconductor device according to an embodiment of the present invention includes a first portion (2001) and a second portion (2002) of a first dielectric pattern (200) that are arranged to be inserted between a source / drain region (121, 122) and a first gate structure (111), thereby allowing the first active pattern (141) to be surrounded by the first gate structure (111), and allowing the first active pattern (141) and the first dielectric pattern (200) to come into contact so that there is no portion of the first active pattern (141) that is not surrounded by the first gate structure (111).

[0103]

[0104] The first gate structure (111) may include a portion (111P) of the first gate structure (111) disposed between the first active pattern (141) and the first dielectric pattern (200). The portion (111P) of the first gate structure (111) may overlap the first active pattern (141) and the first dielectric pattern (200) along a second direction (D2). The second direction (D2) may be a direction intersecting the first direction (D1). The second direction (D2) may be a direction intersecting a direction (e.g., a third direction (D3)) in which the first active pattern (141) extends between the first source / drain region (121) and the second source / drain region (122).

[0105] A portion (111P) of the first gate structure (111) may be placed between the first portion (2001) and the second portion (2002) of the first dielectric pattern (200).

[0106]

[0107] The first gate structure (111) may include a first portion (1111) of the first gate structure (111) disposed between a first portion (2001) of the first dielectric pattern (200) and a second portion (2002) of the first dielectric pattern (200). The first portion (1111) of the first gate structure (111) may be disposed on a portion (111P) of the first gate structure (111). The portion (111P) of the first gate structure (111) may be disposed above or below the first portion (1111) of the first gate structure (111). The first portion (1111) of the first gate structure (111) may be a portion that does not overlap the first active pattern (141) along the first direction (D1).

[0108] The second portion (1112) of the first gate structure (111) may be a portion of the first gate structure (111) disposed on the first active pattern (141). The second portion (1112) of the first gate structure (111) may be a portion that overlaps the first active pattern (141) along the first direction (D1). The second portion (1112) of the first gate structure (111) may be disposed between the first source / drain region (121) and the second source / drain region (122).

[0109]

[0110] A first portion (1111) of the first gate structure (111) may have a first width (Wg1), and a second portion (1112) of the first gate structure (111) may have a second width (Wg2). Here, the first width (Wg1) and the second width (Wg2) may be values ​​measured along a third direction (D3).

[0111]

[0112] In some embodiments, the first width (Wg1) of the first portion (1111) of the first gate structure (111) may be equal to the second width (Wg2) of the second portion (1112) of the first gate structure (111).

[0113]

[0114] The first dielectric pattern (200) may be disposed between the first transistor (TR1) and the second transistor (TR2). The second dielectric pattern (300) may be disposed between the second transistor (TR2) and the third transistor (TR3). The first transistor (TR1) may be of the first type, and the second transistor (TR2) may be of a second type different from the first type. The third transistor (TR3) may be of the second type.

[0115] A semiconductor device according to an embodiment of the present invention can reduce the distance that must be spaced between transistors of the same type by arranging a patterned dielectric pattern (200, 300) between transistors of the same type, thereby reducing the chip size.

[0116]

[0117] The first dielectric pattern (200) may be disposed between the first source / drain region (121) and the third source / drain region (123). The first dielectric pattern (200) may be disposed between the first active pattern (141) and the second active pattern (142). The first dielectric pattern (200) may be disposed between the first gate structure (111) and the second gate structure (112). The first dielectric pattern (200) may be disposed between the second source / drain region (122) and the fourth source / drain region (124).

[0118] The first silicide pattern (131) (not shown in FIG. 4) may be disposed between the first dielectric pattern (200) and the first source / drain region (121). The second silicide pattern (132) (not shown in FIG. 4) may be disposed between the first dielectric pattern (200) and the second source / drain region (122). The silicide patterns disposed in each of the third source / drain region (123) and the fourth source / drain region (124) may also be disposed between the first dielectric pattern (200) and the third source / drain region (123) and the fourth source / drain region (124), respectively.

[0119]

[0120] A second transistor (TR2) of a semiconductor device according to some embodiments of the present invention may include a second active pattern (142), a second gate structure (112), a third source / drain region (123), and a fourth source / drain region (124) on a substrate (100).

[0121] The descriptions of the first transistor (TR1) can be applied to the descriptions of the second transistor (TR2) and the third transistor (TR3). In the following, any details that overlap with those described above will be simplified or omitted.

[0122] The second gate structure (112) may surround at least a portion of the second active pattern (142). The second gate structure (112) may include a second gate electrode (112e) and a second gate insulating film (162).

[0123] A third source / drain region (123) and a fourth source / drain region (124) may be arranged on the fifth side (1125S) and sixth side (1126S) facing each other of the second gate structure (112), respectively.

[0124] A third transistor (TR3) of a semiconductor device according to some embodiments of the present invention may include a third active pattern (143), a third gate structure (113), a fifth source / drain region (125), and a sixth source / drain region (126) on a substrate (100).

[0125] The third gate structure (113) may surround at least a portion of the third active pattern (143). The third gate structure (113) may include a third gate electrode (113e) and a third gate insulating film (163).

[0126] Between the fifth source / drain region (125) and the sixth source / drain region (126), a third active pattern (143) and a third gate structure (113) can be placed.

[0127]

[0128] The first dielectric pattern (200) may include a third portion (2003) of the first dielectric pattern (200) disposed between the third source / drain region (123) and the fifth side (1125S) of the second gate structure (112). The third portion (2003) of the first dielectric pattern (200) may overlap the third source / drain region (123) and the second gate structure (112) along the third direction (D3).

[0129] The first dielectric pattern (200) may include a fourth portion (2004) of the first dielectric pattern (200) disposed between the fourth source / drain region (124) and the sixth side (1126S) of the second gate structure (112). The fourth portion (2004) of the first dielectric pattern (200) may overlap the fourth source / drain region (124) and the second gate structure (112) along the third direction (D3).

[0130]

[0131] The first dielectric pattern (200) may include a first region (200R1) of the first dielectric pattern (200) that is positioned between the first active pattern (141) and the second active pattern (142). The first region (200R1) of the first dielectric pattern (200) may include a first portion (2001) and a third portion (2003) of the first dielectric pattern (200).

[0132] The first dielectric pattern (200) may include a second region (200R2) of the first dielectric pattern (200) disposed between the first gate structure (111) and the second gate structure (112).

[0133] The first dielectric pattern (200) may include a third region (200R3) of the first dielectric pattern (200) disposed between the first source / drain region (121) and the third source / drain region (123).

[0134] The first dielectric pattern (200) may include a fourth region (200R4) of the first dielectric pattern (200) disposed between the second source / drain region (122) and the fourth source / drain region (124).

[0135]

[0136] The first length (W1) of the first region (200R1) of the first dielectric pattern (200) may be different from the second length (W2) of the second region (200R2) of the first dielectric pattern (200).

[0137] In some embodiments, the first length (W1) of the first region (200R1) of the first dielectric pattern (200) may be greater than the second length (W2) of the second region (200R2) of the first dielectric pattern (200).

[0138] In some embodiments, the third length (W3) of the third region (200R3) of the first dielectric pattern (200) may be equal to or different from the fourth length (W4) of the fourth region (200R4) of the first dielectric pattern (200).

[0139] The first length (W1) of the first genetic pattern (200) may be greater than the second length (W2), the third length (W3), and the fourth length (W4).

[0140] Here, the first length (W1), the second length (W2), the third length (W3), and the fourth length (W4) may be values ​​measured along the second direction (D2).

[0141]

[0142] The second dielectric pattern (300) may include a fifth portion (3001) of the second dielectric pattern (300) disposed on the third source / drain region (123) and the fifth side (1125S) of the second gate structure (112). The second dielectric pattern (300) may include a sixth portion (3002) of the second dielectric pattern (300) disposed on the fourth source / drain region (124) and the sixth side (1126S) of the second gate structure (112).

[0143] The fifth portion (3001) of the second dielectric pattern (300) may overlap with the third source / drain region (123) and the second gate structure (112) along the third direction (D3). The sixth portion (3002) of the second dielectric pattern (300) may overlap with the fourth source / drain region (124) and the second gate structure (112) along the third direction (D3).

[0144]

[0145] The second dielectric pattern (300) may include a first region (300R1) of the second dielectric pattern (300) disposed between the second active pattern (142) and the third active pattern (143). The second dielectric pattern (300) may include a second region (300R2) of the second dielectric pattern (300) disposed between the second gate structure (112) and the third gate structure (113). The second region (300R2) of the second dielectric pattern (300) may include a fifth portion (3001) of the second dielectric pattern (300).

[0146]

[0147] The first region (300R1) of the second dielectric pattern (300) may have a fifth length (W5), and the second region (300R2) of the second dielectric pattern (300) may have a sixth length (W6). The fifth length (W5) and the sixth length (W6) may be different from each other. For example, the fifth length (W5) may be greater than the sixth length (W6). Here, the fifth length (W5) and the sixth length (W6) may be values ​​measured along the second direction (D2).

[0148]

[0149] Hereinafter, semiconductor devices according to some embodiments of the present invention will be described with reference to FIGS. 1, 2, 3, and 5. For clarity of explanation, details that overlap with those described above will be simplified or omitted.

[0150] Figure 5 is a cross-sectional view taken along line CC' of Figure 1.

[0151] Referring to FIGS. 1, 2, 3, and 5, the gate structure included in the semiconductor device according to some embodiments of the present invention may have different widths for each portion. For example, the first width (Wg1) of the first portion (1111) of the first gate structure (111) may be different from the second width (Wg2) of the second portion (1112) of the first gate structure (111).

[0152] In the first gate structure (111), the first width (Wg1) of the first portion (1111) overlapping the first portion (2001) and the second portion (2002) of the first dielectric pattern (200) along the third direction (D3) and the second width (Wg2) of the second portion (1112) on the first active pattern (141) may be different from each other.

[0153] In some embodiments, the first width (Wg1) may be smaller than the second width (Wg2).

[0154] The description of the first gate structure (111) can also be applied to the second gate structure (112) and the third gate structure (113).

[0155]

[0156] Hereinafter, semiconductor devices according to some embodiments of the present invention will be described with reference to FIGS. 1, 2, 3, and 6. For clarity of explanation, details that overlap with those described above will be simplified or omitted.

[0157] Figure 6 is a cross-sectional view taken along line CC' of Figure 1.

[0158] Referring to FIGS. 1, 2, 3, and 6, the gate structure included in the semiconductor device according to some embodiments of the present invention may have different widths for each portion. For example, the first width (Wg1) of the first portion (1111) of the first gate structure (111) may be different from the second width (Wg2) of the second portion (1112) of the first gate structure (111).

[0159] In the first gate structure (111), the first width (Wg1) of the first portion (1111) overlapping the first portion (2001) and the second portion (2002) of the first dielectric pattern (200) along the third direction (D3) and the second width (Wg2) of the second portion (1112) on the first active pattern (141) may be different from each other.

[0160] In some embodiments, the first width (Wg1) may be greater than the second width (Wg2).

[0161] The description of the first gate structure (111) can also be applied to the second gate structure (112) and the third gate structure (113).

[0162]

[0163] Hereinafter, semiconductor devices according to some embodiments of the present invention will be described with reference to FIGS. 1, 2, 3, and 7. For clarity of explanation, details that overlap with those described above will be simplified or omitted.

[0164] Figure 7 is a cross-sectional view taken along line CC' of Figure 1.

[0165] Referring to FIGS. 1, 2, 3, and 7, the source / drain region included in the semiconductor device according to some embodiments of the present invention may have different widths for each portion. For example, a portion of the first source / drain region (121) that overlaps with the first portion (2001) of the first dielectric pattern (200) along the third direction (D3) may have a first width (Ws1). Another portion of the first source / drain region (121) that overlaps with the first active pattern along the third direction (D3) may have a second width (Ws2). Here, the first width (Ws1) and the second width (Ws2) may be values ​​measured along the third direction (D3).

[0166] In some embodiments, the first width (Ws1) may be smaller than the second width (Ws2).

[0167] A first portion (2001) of the first dielectric pattern (200) may include a first recessed portion (2001i) that is recessed into a first source / drain region (121). A second portion (2002) of the first dielectric pattern (200) may include a second recessed portion (2002i) that is recessed into a second source / drain region (122).

[0168] Due to the first indentation portion (2001i) and the second indentation portion (2002i), the source / drain region can have different widths for each portion.

[0169] The description of the first dielectric pattern (200) can also be applied to the second dielectric pattern (300). The description of the first source / drain region (121) and the second source / drain region (122) can also be applied to the third source / drain region (123), the fourth source / drain region (124), the fifth source / drain region (125), and the sixth source / drain region (126).

[0170]

[0171] Hereinafter, semiconductor devices according to some embodiments of the present invention will be described with reference to FIGS. 1, 2, 3, and 8. For clarity of explanation, details that overlap with those described above will be simplified or omitted.

[0172] Figure 8 is a cross-sectional view taken along line CC' of Figure 1.

[0173] Referring to FIGS. 1, 2, 3, and 8, a semiconductor device according to some embodiments of the present invention may further include a spacer material disposed between a source / drain region and a dielectric pattern.

[0174] For example, a spacer material (170) may be further disposed between the first source / drain region (121) and the third region (200R3) of the first dielectric pattern (200). For example, a spacer material (170) may be further disposed between the second source / drain region (122) and the fourth region (200R4) of the first dielectric pattern (200). For example, a spacer material (170) may be further disposed between the third source / drain region (123) and the second dielectric pattern (300). For example, a spacer material (170) may be further disposed between the fourth source / drain region (124) and the second dielectric pattern (300).

[0175] Although the city is omitted, in this embodiment, the silicide pattern (131, 132) may be placed between the source / drain region and the spacer material.

[0176] The third length (W3) of the third region (200R3) of the first genetic pattern (200) and the fourth length (W4) of the fourth region (200R4) may be the same or different from each other.

[0177] As the spacer material (170) is placed between the dielectric pattern and the source / drain region, a space as large as the spacer material (170) is placed can be secured, thereby securing a margin in the manufacturing process of the semiconductor device.

[0178]

[0179] Hereinafter, semiconductor devices according to some embodiments of the present invention will be described with reference to FIGS. 1, 2, 3, and 9. For clarity of explanation, details that overlap with those described above will be simplified or omitted.

[0180] Figure 9 is a cross-sectional view taken along line CC' of Figure 1.

[0181] Referring to FIGS. 1, 2, 3, and 9, the source / drain regions of the semiconductor devices according to some embodiments of the present invention may have different lengths depending on the position at which they are arranged. For example, a portion of the first source / drain region (121) that overlaps the first portion (2001) of the first dielectric pattern (200) along the third direction (D3) may have a first length (L1). A portion of the second source / drain region (122) that overlaps the second portion (2002) of the first dielectric pattern (200) along the third direction (D3) may have a second length (L2). A portion of the third source / drain region (123) that overlaps the third portion (2003) of the first dielectric pattern (200) along the third direction (D3) may have a third length (L3). A portion of the fourth source / drain region (124) that overlaps with the fourth portion (2004) of the first dielectric pattern (200) along the third direction (D3) may have a fourth length (L4).

[0182] In some embodiments, the second length (L2) of the portion of the second source / drain region (122) may be greater than the first length (L1) of the portion of the first source / drain region (121). The third length (L3) of the portion of the third source / drain region (123) may be greater than the fourth length (L4) of the portion of the fourth source / drain region (124). The third length (L3) of the portion of the third source / drain region (123) may be greater than the first length (L1) of the portion of the first source / drain region (121). The second length (L2) of the portion of the second source / drain region (122) may be greater than the fourth length (L4) of the portion of the fourth source / drain region (124).

[0183] For example, a contact (150) may be placed on a portion of a third source / drain region (123) having a third length (L3). For example, a contact (150) may be placed on a portion of a second source / drain region (122) having a second length (L2).

[0184] The third length (W3) of the third region (200R3) of the first genetic pattern (200) and the fourth length (W4) of the fourth region (200R4) of the first genetic pattern (200) may be the same or different.

[0185]

[0186] Hereinafter, semiconductor devices according to some embodiments of the present invention will be described with reference to FIGS. 1, 2, 3, and 10. For clarity of explanation, details that overlap with those described above will be simplified or omitted.

[0187] Fig. 10 is a cross-sectional view taken along line CC' of Fig. 1.

[0188] Referring to FIGS. 1, 2, 3, and 10, the source / drain regions of semiconductor devices according to some embodiments of the present invention may have different lengths depending on the position at which they are placed.

[0189] In some embodiments, the second length (L2) of the portion of the second source / drain region (122) can be substantially equal to the first length (L1) of the portion of the first source / drain region (121). The third length (L3) of the portion of the third source / drain region (123) can be less than the fourth length (L4) of the portion of the fourth source / drain region (124). The third length (L3) of the portion of the third source / drain region (123) can be less than the first length (L1) of the portion of the first source / drain region (121). The second length (L2) of the portion of the second source / drain region (122) can be substantially equal to the fourth length (L4) of the portion of the fourth source / drain region (124).

[0190] For example, a contact (150) may be placed on a portion of a first source / drain region (121) having a first length (L1).

[0191] The third length (W3) of the third region (200R3) of the first dielectric pattern (200) and the fourth length (W4) of the fourth region (200R4) of the first dielectric pattern (200) may be different from each other. The third length (W3) of the third region (200R3) of the first dielectric pattern (200) may be longer than the fourth length (W4) of the fourth region (200R4) of the first dielectric pattern (200). The second length (W2) of the second region (200R2) of the first dielectric pattern (200) and the fourth length (W4) of the fourth region (200R4) of the first dielectric pattern (200) may be substantially the same.

[0192]

[0193] Hereinafter, semiconductor devices according to some embodiments of the present invention will be described with reference to FIGS. 1, 2, 3, and 11. For clarity of explanation, details that overlap with those described above will be simplified or omitted.

[0194] Fig. 11 is a cross-sectional view taken along line CC' of Fig. 1.

[0195] Referring to FIGS. 1, 2, 3, and 11, a fourth length (W4) of a fourth region (200R4) of a first dielectric pattern (200) of a semiconductor device according to some embodiments of the present invention may be longer than a third length (W3) of a third region (200R3) of the first dielectric pattern (200). A fourth length (W4) of a fourth region (200R4) of the first dielectric pattern (200) may be longer than a second length (W2) of a second region (200R2) of the first dielectric pattern (200). A fourth length (W4) of a fourth region (200R4) of the first dielectric pattern (200) may be shorter than a first length (W1) of a first region (200R1) of the first dielectric pattern (200).

[0196] A spacer material (170) may be placed between the third region (200R3) of the first dielectric pattern (200) and the first source / drain region (121). A spacer material (170) may be placed between the third region (200R3) of the first dielectric pattern (200) and the third source / drain region (123).

[0197]

[0198] Hereinafter, semiconductor devices according to some embodiments of the present invention will be described with reference to FIGS. 1, 2, 3, and 12. For clarity of explanation, details that overlap with those described above will be simplified or omitted.

[0199] Figure 12 is a cross-sectional view taken along line CC' of Figure 1.

[0200] Referring to FIGS. 1, 2, 3, and 12, a third length (W3) of a third region (200R3) of a first dielectric pattern (200) of a semiconductor device according to some embodiments of the present invention may be substantially equal to a fourth length (W4) of a fourth region (200R4) of the first dielectric pattern (200). The third length (W3) of the third region (200R3) of the first dielectric pattern (200) and the fourth length (W4) of the fourth region (200R4) of the first dielectric pattern (200) may be smaller than the first length (W1) of the first region (200R1) of the first dielectric pattern (200).

[0201] A spacer material (170) may be placed between the third region (200R3) of the first dielectric pattern (200) and the first source / drain region (121). A spacer material (170) may be placed between the fourth region (200R4) of the first dielectric pattern (200) and the fourth source / drain region (124).

[0202]

[0203] Hereinafter, a method for manufacturing a semiconductor device according to some embodiments of the present invention will be described with reference to FIGS. 13 to 27. For clarity of explanation, any details that overlap with those previously described will be simplified or omitted.

[0204] FIG. 13 is a flowchart illustrating a method for manufacturing a semiconductor device according to some embodiments of the present invention.

[0205] Referring to FIG. 13, a method for manufacturing a semiconductor device according to some embodiments of the present invention may include a step (S100) of forming a fin pattern.

[0206] FIG. 14 and FIG. 15 are drawings for explaining step S100 of FIG. 13, and may be perspective views of a semiconductor device.

[0207] Referring to FIGS. 13 and 14, a first layer (501) and a second layer (502) may be alternately laminated on a substrate. The substrate on which the first layer (501) and the second layer (502) are alternately laminated may be, for example, a PTS ion implantation region, which is a first region (101) of the substrate. For example, the first layer (501) and the second layer (502) may be alternately laminated on the first region (101) of the substrate.

[0208] Referring to FIGS. 13 and 15, a fin pattern (FP) may be formed. For example, a structure in which a first layer (501) and a second layer (502) are alternately laminated may be patterned to form a fin pattern (FP), and a second region (102) may be further formed below the fin pattern (FP) to define a substrate (100).

[0209]

[0210] Referring again to FIG. 13, a method for manufacturing a semiconductor device according to some embodiments of the present invention may include a step (S200) of forming a dummy wall.

[0211] FIG. 16 is a drawing for explaining step S200 of FIG. 13, and may be a perspective view of a semiconductor device.

[0212] Referring to FIGS. 13 and 16, a dummy wall (DW) surrounding a fin pattern (FP) may be formed on a substrate (100). The dummy wall (DW) may be formed on a second region (102) of the substrate (100). The dummy wall (DW) may be formed to cover all side walls and the upper surface of the fin pattern (FP).

[0213]

[0214] Referring again to FIG. 13, a method for manufacturing a semiconductor device according to some embodiments of the present invention may include a step (S300) of forming a first dummy pattern and a second dummy pattern that are spaced apart from each other.

[0215] FIG. 17 is a drawing for explaining step S300 of FIG. 13, and may be a perspective view of a semiconductor device.

[0216] Referring to FIGS. 13 and 17, a dummy wall (DW) may be patterned to form a first dummy pattern (DW1), a second dummy pattern (DW2), and a third dummy pattern (DW3) that are spaced apart from each other. The dummy wall (DW) may be patterned using a mask pattern (MP). The first dummy pattern (DW1), the second dummy pattern (DW2), and the third dummy pattern (DW3) may expose a portion of the second region (102) of the substrate (100).

[0217]

[0218] Referring again to FIG. 13, a method for manufacturing a semiconductor device according to some embodiments of the present invention may include a step (S400) of forming a first dielectric pattern.

[0219] FIG. 18 is a drawing for explaining step S400 of FIG. 13, and may be a perspective view of a semiconductor device.

[0220] Referring to FIG. 13 and FIG. 18, the mask pattern (MP) of FIG. 17 may be removed, and a portion of each of the first dummy pattern (DW1), the second dummy pattern (DW2), and the third dummy pattern (DW3) may be removed so that the upper surface of the second layer (502) is exposed. The first dielectric pattern (200) may be formed on the first dummy pattern (DW1) and the second dummy pattern (DW2). The first dielectric pattern (200) may be formed between the second dummy pattern (DW2) and the third dummy pattern (DW3). The first dielectric pattern (200) may be formed to cover the sidewalls of each of the first dummy pattern (DW1), the second dummy pattern (DW2), and the third dummy pattern (DW3). The first dielectric pattern may be formed on a portion of the second region (102) of the exposed substrate (100) when the first dummy pattern (DW1), the second dummy pattern (DW2), and the third dummy pattern (DW3) are formed.

[0221]

[0222] Referring again to FIG. 13, a method for manufacturing a semiconductor device according to some embodiments of the present invention may include a step (S500) of forming a first source / drain region.

[0223] FIG. 19 and FIG. 20 are drawings for explaining step S500 of FIG. 13, and may be perspective views of a semiconductor device.

[0224] Referring to FIGS. 13 and 19, a dummy gate (DG) may be formed on the structure of FIG. 18. For example, the dummy gate (DG) may be formed on the second dummy pattern (DW2).

[0225] Due to the formation of the dummy gate (DG), a second portion (2002) of the first dielectric pattern (200) can be defined.

[0226] Referring to FIGS. 13 and 20, a portion of each of the first layer (501) and the second layer (502) exposed by the dummy gate (DG) may be removed. A spacer material may be filled on both sidewalls of the dummy gate (DG) to form a free spacer (170p). The free spacer (170p) may be formed parallel to the second portion (2002) of the first dielectric pattern (200).

[0227] A first source / drain region (121) may be formed between the first dummy patterns (DW1), and a second source / drain region (122) may be formed between the third dummy patterns (DW3). The first source / drain region (121) may be formed on one side wall of the free spacer (170p) on the first region (101) of the substrate (100). The second source / drain region (122) may be formed on the other side wall of the free spacer (170p) on the first region (101) of the substrate (100).

[0228]

[0229] Referring again to FIG. 13, a method for manufacturing a semiconductor device according to some embodiments of the present invention may include a step (S600) of forming a first gate structure surrounding a first layer.

[0230] Figures 21 to 24 are drawings for explaining step S600 of Figure 13.

[0231] Referring to FIG. 13 and FIG. 21, a spacer material (170) may be formed. The spacer material (170) may be formed on one sidewall of the free spacer (170p), the upper surface of the first source / drain region (121), the upper surface of the first dummy pattern (DW1), a portion of the sidewall of the first dummy pattern (DW1), and a portion of the upper surface of the first dielectric pattern (200). The spacer material (170) may be formed on the other sidewall of the free spacer (170p), the upper surface of the second source / drain region (122), the upper surface of the third dummy pattern (DW3), a portion of the sidewall of the third dummy pattern (DW3), and another portion of the upper surface of the first dielectric pattern (200).

[0232] Dummy gates (DGs) can be removed.

[0233] Figure 22 is a cross-sectional view taken along line XX of Figure 21.

[0234] Referring to FIG. 13 and FIG. 22, the second dummy pattern (DW2) may be removed so that a second dummy hole (DW2H) may be formed between the first dielectric pattern (200) and the fin pattern (FP).

[0235] Figure 23 is a cross-sectional view taken along line XX of Figure 21.

[0236] Referring to FIGS. 13 and 23, after the second dummy hole (DW2H) is formed, the second layer (502) of the fin pattern (FP) can be removed.

[0237] Figure 24 is a cross-sectional view taken along line XX of Figure 21.

[0238] Referring to FIGS. 13 and 24, a first gate structure (111) can be formed in a portion where the second layer (502) has been removed.

[0239] The first gate insulating film (161) may be formed on all portions exposed by the removal of the second layer (502). For example, the first gate insulating film (161) may be formed to surround the first layer (501). The first gate insulating film (161) may be formed on the substrate (100). The first gate insulating film (161) may be formed along the sidewall of the first dielectric pattern (200).

[0240] The first gate electrode (111e) may be formed to fill the remaining portion after the first gate insulating film (161) is formed. The first gate electrode (111e) may be formed to surround the first layer (501). The first gate electrode (111e) may be formed between the substrate (100) and the first layer (501), and may be formed between the first layer (501) and the first dielectric pattern (200).

[0241]

[0242] Referring again to FIG. 13, a method for manufacturing a semiconductor device according to some embodiments of the present invention may include a step (S700) of removing a first dummy pattern.

[0243] Figures 25 to 27 are cross-sectional views taken along line YY of Figure 21.

[0244] Referring to FIGS. 13, 25, and 26, the first dummy pattern (DW1) between the first source / drain region (121) and the first dielectric pattern (200) can be removed. The third dummy pattern (DW3) between the second source / drain region (122) and the first dielectric pattern (200) can also be removed.

[0245] A first dummy pattern (DW1) may be removed to form a first dummy hole (DW1H). A third dummy hole may also be formed in a portion where a third dummy pattern (DW3) has been removed.

[0246] Referring to FIG. 13 and FIG. 27, a first silicide pattern (131) may be formed in the first dummy hole (DW1H). The first silicide pattern (131) may be formed between the first source / drain region (121) and the first dielectric pattern (200), and may be formed on the first source / drain region (121).

[0247]

[0248] A semiconductor device and a method for manufacturing the same according to an embodiment of the present invention can reduce a gap between transistors of the same type by arranging a patterned dielectric pattern between transistors of the same type. In addition, a semiconductor device and a method for manufacturing the same according to an embodiment of the present invention can improve a controllability for a gate and reduce electrical loss by allowing an active pattern operating as a channel region to be completely surrounded by the gate structure by arranging a part of a dielectric pattern (e.g., a first portion (2001) and a second portion (2002)) between a gate structure and a source / drain pattern. In addition, a semiconductor device and a method for manufacturing the same according to an embodiment of the present invention can reduce a parasitic resistance by arranging a silicide pattern between a dielectric pattern and a source / drain region.

[0249]

[0250] The above description is merely an example of the technical idea of ​​the present embodiment, and those skilled in the art will appreciate that various modifications and variations can be made without departing from the essential characteristics of the present embodiment. Therefore, the present embodiments are not intended to limit the technical idea of ​​the present embodiment, but rather to explain it, and the scope of the technical idea of ​​the present embodiment is not limited by these embodiments. The scope of protection of the present embodiment should be interpreted by the claims below, and all technical ideas within a scope equivalent thereto should be interpreted as being included in the scope of rights of the present embodiment.

Claims

1. Substrate; A first active pattern on the substrate; A first gate structure surrounding at least a portion of the first active pattern; A first source / drain region and a second source / drain region respectively disposed on the first side and the second side facing each other of the first gate structure; and A first dielectric pattern is disposed on a third side different from each of the first side and the second side of the first gate structure, The above first genetic pattern is, a first portion of the first dielectric pattern disposed between the first source / drain region and the first side of the first gate structure; and A second portion of the first dielectric pattern disposed between the second source / drain region and the second side of the first gate structure. Semiconductor devices.

2. In paragraph 1, The above first gate structure is, A portion of the first gate structure disposed between the first active pattern and the first dielectric pattern along a second direction intersecting the first direction perpendicular to the first gate structure and the substrate. Semiconductor devices.

3. In paragraph 2, The part of the first gate structure is disposed between the first part and the second part of the first dielectric pattern. Semiconductor devices.

4. In paragraph 1, a first silicide pattern disposed between the first source / drain region and the first dielectric pattern; and Further comprising a second silicide pattern disposed between the second source / drain region and the first dielectric pattern. Semiconductor devices.

5. In paragraph 1, a second active pattern on the substrate; and Further comprising a second gate structure surrounding at least a portion of the second active pattern, The first dielectric pattern is disposed between the first gate structure and the second gate structure, and is disposed between the first active pattern and the second active pattern. A first region of the first dielectric pattern between the first active pattern and the second active pattern has a first width, A second region of the first dielectric pattern between the first gate structure and the second gate structure has a second width, The above first width and the above second width are different, The first region of the first dielectric pattern includes the first portion. Semiconductor devices.

6. In paragraph 5, The above first width is greater than the above second width Semiconductor devices.

7. In paragraph 5, Further comprising a third source / drain region and a fourth source / drain region respectively disposed on the fifth and sixth sides facing each other of the second gate structure, The above first genetic pattern is, a third portion of the first dielectric pattern disposed between the third source / drain region and the fifth side of the second gate structure; and a fourth portion of the first dielectric pattern disposed between the fourth source / drain region and the sixth side of the second gate structure; The first region of the first dielectric pattern includes the third portion. Semiconductor devices.

8. In paragraph 7, A third region of the first dielectric pattern between the first source / drain region and the third source / drain region has a third width, The fourth region of the first dielectric pattern between the second source / drain region and the fourth source / drain region has a fourth width, The above third width and the above fourth width are different Semiconductor devices.

9. In paragraph 1, A first portion of the first gate structure disposed between the first portion and the second portion of the first dielectric pattern has a first width, A second portion of the first gate structure disposed between the first source / drain and the second source / drain and disposed on the first active pattern has a second width, The first width of the first portion of the first gate structure and the second width of the second portion of the first gate structure are different. Semiconductor devices.

10. In paragraph 1, The first portion of the first dielectric pattern further includes a first indented portion that is indented into the first source / drain region. Semiconductor devices.

11. In paragraph 10, The second portion of the first dielectric pattern further includes a second indented portion that is indented into the first source / drain region. Semiconductor devices.

12. Substrate; A first type of first transistor comprising a first active pattern on the substrate, and a first gate structure surrounding the first active pattern; A second type of second transistor comprising a second active pattern on the substrate, and a second gate structure surrounding the second active pattern; A patterned first dielectric pattern disposed between the first transistor and the second transistor; A third transistor of the second type comprising a third active pattern on the substrate, and a third gate structure surrounding the third active pattern; and comprising a patterned second dielectric pattern disposed between the second transistor and the third transistor; The first region of the second dielectric pattern between the second active pattern and the third active pattern has a first width, A second region of the second dielectric pattern between the second gate structure and the third gate structure has a second width, The above first width and the above second width are different Semiconductor devices.

13. In paragraph 12, Further comprising a first source / drain region and a second source / drain region respectively disposed on the first side and the second side facing each other of the first gate structure, The first dielectric pattern is arranged on a third side different from each of the first side and the second side, The above first genetic pattern is, a first portion of the first dielectric pattern disposed between the first source / drain region and the first side of the first gate structure; and A second portion of the first dielectric pattern disposed between the second source / drain region and the second side of the first gate structure. Semiconductor devices.

14. In paragraph 13, Further comprising a third source / drain region and a fourth source / drain region respectively disposed on the fifth and sixth sides facing each other of the second gate structure, The above first genetic pattern is, a third portion of the first dielectric pattern disposed between the third source / drain region and the fifth side of the second gate structure; and A fourth portion of the first dielectric pattern disposed between the fourth source / drain region and the sixth side of the second gate structure. Semiconductor devices.

15. In paragraph 14, The above second genetic pattern is, a fifth portion of the second dielectric pattern disposed between the third source / drain region and the fifth side of the second gate structure; and A sixth portion of the second dielectric pattern disposed between the fourth source / drain region and the sixth side of the second gate structure. Semiconductor devices.

16. In paragraph 14, A third region of the first dielectric pattern between the first source / drain region and the third source / drain region has a third width, The fourth region of the first dielectric pattern between the second source / drain region and the fourth source / drain region has a fourth width, The above third width and the above fourth width are different Semiconductor devices.

17. In paragraph 13, A first portion of the first gate structure disposed between the first portion and the second portion of the first dielectric pattern has a first width, A second portion of the first gate structure disposed between the first source / drain and the second source / drain and disposed on the first active pattern has a second width, The first width of the first portion of the first gate structure and the second width of the second portion of the first gate structure are different. Semiconductor devices.

18. In paragraph 13, The first portion of the first dielectric pattern further includes a first indented portion that is indented into the first source / drain region. Semiconductor devices.

19. In paragraph 18, The second portion of the first dielectric pattern further includes a second indented portion that is indented into the first source / drain region. Semiconductor devices.

20. A step of forming a fin pattern by alternately stacking a first layer and a second layer on a substrate and then patterning them; A step of forming a dummy wall surrounding the pin pattern on the substrate; A step of patterning the above dummy wall to form a first dummy pattern and a second dummy pattern that are spaced apart from each other; A step of forming a first dielectric pattern formed between the first dummy pattern and the second dummy pattern and formed to cover side walls of each of the first dummy pattern and the second dummy pattern; A step of forming a first source / drain region by removing a portion of the pin pattern on the first dummy pattern side; A step of forming a first gate structure surrounding the first layer by removing the second dummy pattern and the second layer; and including a step of removing the first dummy pattern; Method for manufacturing a semiconductor device.

21. In paragraph 20, After the first dummy pattern is removed, a step of forming a silicide pattern between the first dielectric pattern and the first source / drain region is further included. Method for manufacturing a semiconductor device.

22. In paragraph 20, The above first genetic pattern is, A first portion of the first dielectric pattern disposed between the first source / drain region and the first gate structure. Method for manufacturing a semiconductor device.

23. In paragraph 20, The step of forming the first dummy pattern and the second dummy pattern further includes the step of forming a third dummy pattern spaced apart from the first dummy pattern and the second dummy pattern, The first dielectric pattern is further formed between the second dummy pattern and the third dummy pattern, and is further formed to cover the side wall of the third dummy pattern. A step of forming a second source / drain region by removing another part of the pin pattern on the third dummy pattern side; and Further comprising a step of removing the third dummy pattern. Method for manufacturing a semiconductor device.

24. In paragraph 23, The above first genetic pattern is, a first portion of the first dielectric pattern disposed between the first source / drain region and the first side of the first gate structure; and A second portion of the first dielectric pattern disposed between the second source / drain region and the second side of the first gate structure. Method for manufacturing a semiconductor device.

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