Semiconductor device and manufacturing method therefor, and electronic device

Abstract

The present application relates to the technical field of semiconductors, and relates to a semiconductor device and a manufacturing method therefor, and an electronic device. The semiconductor device comprises: a multi-layer stacked memory cell array. The memory cell array comprises transistors (12), and each transistor (12) comprises a first source / drain (125), an insulating structure (121), a second source / drain (126), and a semiconductor layer (122), a gate insulating layer (123) and a gate electrode (124) that sequentially surround the periphery of the insulating structure 121. The material of the first source / drain (125) and the material of the second source / drain (126) comprise a metal, and the material of the insulating structure (121) comprises a metal oxide of the metal.

Description

Semiconductor device and manufacturing method thereof, and electronic device

[0001] Related applications

[0002] This application claims priority to Chinese patent application number 2024103603413, filed on March 27, 2024, entitled “Semiconductor device, manufacturing method thereof, and electronic device,” the entire text of which is hereby incorporated by reference. Technical Field

[0003] The present application relates to the field of semiconductor technology, and more specifically, to a semiconductor device and a manufacturing method thereof, and an electronic device. Background Art

[0004] With the development of integrated circuit technology, the critical dimensions of devices are shrinking, and the types and numbers of devices contained in a single chip are increasing accordingly, so that any slight difference in process production may affect device performance.

[0005] To minimize product costs, people hope to create as many device units as possible on a limited substrate. Since the advent of Moore's Law, the industry has proposed various semiconductor structure designs and process optimizations to meet people's current product needs.

[0006] Summary of the Invention

[0007] According to various embodiments of the present application, a semiconductor device, a manufacturing method thereof, and an electronic device are provided. The semiconductor device has a simple structure and is easy to manufacture.

[0008] An embodiment of the present application provides a semiconductor device, comprising: a multi-layer stacked memory cell array;

[0009] The memory cell array includes a plurality of memory cells stacked in a direction perpendicular to the substrate; each memory cell includes a transistor, the transistor including a first source / drain, an insulating structure, and a second source / drain arranged in sequence, and a semiconductor layer, a gate insulating layer, and a gate electrode surrounding the outer periphery of the insulating structure in sequence;

[0010] The material of the first source / drain and the second source / drain comprises metal, and the material of the insulating structure comprises metal oxide of the metal.

[0011] In some embodiments, a thickness of the insulating structure in a direction perpendicular to the substrate is smaller than a thickness of the first source / drain or the second source / drain in the direction perpendicular to the substrate.

[0012] In some embodiments, the insulating structure includes sidewalls in an extension direction extending from the first source / drain to the second source / drain, and the semiconductor layer surrounds the sidewalls of the insulating structure and extends onto the first source / drain and the second source / drain to contact the first source / drain and the second source / drain.

[0013] In some embodiments, the memory cell array further includes a plurality of bit lines extending along the column direction and arranged at intervals along the row direction, and each of the bit lines is connected to the first source / drain of each of the transistors of two columns of the memory cells.

[0014] In some embodiments, each of the storage units further comprises a capacitor; the capacitor comprises a first capacitor electrode, a first dielectric layer, and a second capacitor electrode;

[0015] The second source / drain of the transistor in each layer of the storage unit and the first capacitor electrode of the capacitor are different regions of the same metal layer.

[0016] In some embodiments, the material of the first source / drain and the second source / drain comprises metallic molybdenum, and the material of the insulating structure comprises molybdenum oxide; or

[0017] The material of the first source / drain and the second source / drain comprises metal tantalum, and the material of the insulating structure comprises tantalum oxide; or

[0018] The materials of the first source / drain and the second source / drain include metallic titanium, and the material of the insulating structure includes titanium oxide.

[0019] In some embodiments, the memory cell array further includes a plurality of word lines, which extend in a direction perpendicular to the substrate and surround the gate insulation layer of each transistor stacked in a direction perpendicular to the substrate, and the gate electrode includes an area where the word lines surround the periphery of the gate insulation layer.

[0020] In some embodiments, the material of the semiconductor layer includes a metal oxide semiconductor layer.

[0021] An embodiment of the present application provides an electronic device, including: the semiconductor device described in any of the above embodiments.

[0022] An embodiment of the present application provides a method for manufacturing a semiconductor device, comprising:

[0023] forming a stacked structure located on one side of the substrate, the stacked structure comprising a plurality of first insulating layers and a plurality of metal layers alternately stacked;

[0024] forming a plurality of first through holes penetrating the stacked structure on the stacked structure, wherein the first through holes are arranged at intervals in a column direction;

[0025] A plurality of the metal layers and a plurality of the first insulating layers are stacked between any two adjacent first through holes;

[0026] removing the first insulating layers exposed between any two adjacent first through holes to expose the sidewall regions of the metal layers between the first through holes;

[0027] The exposed metal layer is oxidized, and the metal oxide layer formed after oxidation serves as an insulating structure;

[0028] A semiconductor layer, a gate insulating layer and a gate electrode are sequentially formed at least on the periphery of the insulating structure.

[0029] In some embodiments, forming a semiconductor layer, a gate insulating layer, and a gate electrode in sequence at least on the periphery of the insulating structure includes:

[0030] Carving back the first insulating layer in the row direction in the first through hole to form two transverse grooves, wherein the two transverse grooves respectively expose a portion of the unoxidized metal layer;

[0031] A semiconductor layer, a gate insulating layer and a gate electrode are sequentially formed on the periphery of the insulating structure and in the lateral groove; wherein the unoxidized metal layers in the two lateral grooves are parts of the first source / drain and the second source / drain respectively.

[0032] In some embodiments, after sequentially forming a semiconductor layer, a gate insulating layer, and a gate electrode on the periphery of the insulating structure, the method further includes:

[0033] forming a second through hole penetrating the stacked structure;

[0034] The semiconductor layer in the transverse groove is exposed through the second through hole, and the semiconductor layer in each transverse groove is removed, so as to disconnect the semiconductor layers of the transistors stacked in a direction perpendicular to the substrate.

[0035] In some embodiments, the exposed metal layer includes at least one of metal molybdenum, metal tantalum, and metal titanium.

[0036] In some embodiments, before sequentially forming a semiconductor layer, a gate insulating layer, and a gate electrode on the periphery of the insulating structure, the method further includes:

[0037] The insulating structure is thinned.

[0038] In some embodiments, the exposed metal layer is subjected to an oxidation process, including:

[0039] The exposed metal layer is annealed in an oxygen atmosphere at a temperature higher than 250 degrees Celsius, so that the exposed metal layer is oxidized to form a metal oxide layer.

[0040] The details of one or more embodiments of the present disclosure are set forth in the accompanying drawings and the description below. Other features, objects, and advantages of the present application will become apparent from the description, drawings, and claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0041] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the conventional technology, the following briefly introduces the drawings required for use in the embodiments or the conventional technology descriptions. Obviously, the drawings described below are merely embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on the disclosed drawings without any creative work.

[0042] FIG1 is a top view of a semiconductor device provided by an embodiment of the present application, taken along a direction parallel to the substrate;

[0043] FIG2 is a schematic diagram of a cross-sectional structure perpendicular to the substrate along the BB direction in FIG1 ;

[0044] 3 is a schematic diagram of a three-dimensional structure of a group of transistors and word lines along a third direction in a semiconductor device provided by an embodiment of the present application;

[0045] FIG4 is a schematic diagram of a process flow of a method for manufacturing a semiconductor device provided in an embodiment of the present application;

[0046] 5 to 26 are schematic diagrams of intermediate structures obtained in each step of a flow diagram of a method for manufacturing a semiconductor structure provided in an embodiment of the present application.

[0047] Explanation of the accompanying drawings: 11-substrate; 12-transistor; 121-insulating structure; 122-semiconductor layer; 123-gate insulating layer; 124-gate electrode; 125-first source / drain; 126-second source / drain; 13-word line; 14-bit line; 15-first insulating layer; 151-insulating portion; 16-metal layer; 161-first metal structure; 162-metal line; 17-protective layer; 18-initial insulating structure; 19-second insulating layer; 21-capacitor; 211-first capacitor electrode; 212-first dielectric layer; 213-second capacitor electrode; 30-first through hole; 40-first trench; 50-second trench; 60-third trench; 70-second through hole. DETAILED DESCRIPTION

[0048] The following will be combined with the drawings in the embodiments of this application to clearly and completely describe the technical solutions in the embodiments of this application. Obviously, the embodiments described are only part of the embodiments of this application, not all of the embodiments. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of this application.

[0049] The following describes the embodiments of the present application in conjunction with the accompanying drawings. It should be understood that the embodiments described below in conjunction with the accompanying drawings are exemplary descriptions for explaining the technical solutions of the embodiments of the present application and do not constitute a limitation on the technical solutions of the embodiments of the present application.

[0050] Those skilled in the art will understand that, unless otherwise stated, the terms "said" and "the" used herein may also include plural forms. It should be further understood that the term "including" used in the specification of this application refers to the presence of the steps, elements, and / or components, but does not exclude the implementation of other steps, elements, components, and / or combinations thereof supported by the technical field. The term "and / or" used herein refers to at least one of the items defined by the term. For example, "A and / or B" can be implemented as "A", or as "B", or as "A and B".

[0051] In order to make the objectives, technical solutions and advantages of this application clearer, the implementation methods of this application will be further described in detail below with reference to the accompanying drawings.

[0052] The following is a detailed description of the technical solution of the present application and how the technical solution of the present application solves the above-mentioned technical problems with specific embodiments. It should be noted that the following embodiments can refer to, draw on, or combine with each other, and the same terms, similar features, and similar implementation steps in different embodiments will not be repeated.

[0053] An embodiment of the present application provides a semiconductor device, the structural schematic diagrams of which are shown in Figures 1 to 3, and include: a multi-layer stacked memory cell array.

[0054] Each layer of the memory cell array includes a plurality of memory cells distributed in an array; each memory cell includes a transistor 12, and each transistor 12 in the plurality of stacked memory cells is stacked in a direction perpendicular to the substrate;

[0055] The transistor 12 includes a first source / drain 125, an insulating structure 121, and a second source / drain 126 arranged in sequence, as well as a semiconductor layer 122, a gate insulating layer 123, and a gate electrode 124 surrounding the outer periphery of the insulating structure 121 in sequence; the material of the first source / drain 125 and the second source / drain 126 includes metal, and the material of the insulating structure 121 includes a metal oxide of the metal.

[0056] In the embodiment of the present application, the first source / drain, the insulating structure, and the second source / drain contain the same metal, resulting in a simple structure and ease of manufacture. Furthermore, the size of the semiconductor layer 122 is defined by the size of the insulating structure 121, making the size of the semiconductor layer 122 more controllable.

[0057] In some embodiments, the insulating structure 121 is a film layer parallel to the substrate, and the first source / drain 125 and the second source / drain 126 are film layers parallel to the substrate. The thickness of the insulating structure 121 in a direction perpendicular to the substrate 11 is less than the thickness of the first source / drain 125 in the direction perpendicular to the substrate 11, and / or the thickness of the insulating structure 121 in the direction perpendicular to the substrate 11 is less than the thickness of the second source / drain 126 in the direction perpendicular to the substrate.

[0058] In a specific process implementation, the first source / drain, the insulating structure, and the second source / drain can be implemented in different regions of a metal layer. The insulating structure is formed by oxidizing a portion of the metal layer to form a metal oxide. The thickness of each region of the metal layer is consistent. After oxidation to form the initial insulating structure, the initial insulating structure is thinned and trimmed to obtain the final insulating structure 121. This allows the semiconductor layer 122 formed in a subsequent process around the outer periphery of the insulating structure 121 to be connected to the unoxidized portions of the metal layer (the first source / drain 125 and the second source / drain 126).

[0059] In some embodiments, the insulating structure 121 extends from the first source / drain 125 to the second source / drain 126, and has sidewalls in the extension direction. The semiconductor layer 122 surrounds the sidewalls of the insulating structure 121 and extends onto the first source / drain 125 and the second source / drain 126 to contact the first source / drain 125 and the second source / drain 126.

[0060] Such a configuration can achieve more contacts between the semiconductor layer 122 and the first source / drain 125 and the second source / drain 126 , thereby improving contact reliability.

[0061] In some embodiments, for example, the material of the semiconductor layer 122 may be a wide bandgap material, such as a metal oxide material with a bandgap greater than 1.65 eV.

[0062] For example, the material of the semiconductor layer or channel may include a metal oxide of at least one of the following metals: indium, gallium, zinc, tin, tungsten, magnesium, zirconium, aluminum, hafnium, etc. Of course, the metal oxide may also contain compounds of other elements, such as nitrogen and silicon, or contain other small amounts of doping elements.

[0063] In some embodiments, the material of the semiconductor layer or the channel may include any one or more of the following: indium gallium zinc oxide (InGaZnO), indium zinc oxide (InZnO), indium gallium oxide (InGaO), indium tin oxide (InSnO), indium gallium tin oxide (InGaSnO), indium gallium zinc tin oxide (InGaZnSnO), indium oxide (InO), tin oxide (SnO), zinc tin oxide (ZnSnO, ZTO), indium aluminum zinc gold oxide (InAlZnO), zinc oxide (ZnO), indium gallium silicon oxide (InGaSiO), indium tungsten oxide (InWO, Materials such as IWO), titanium oxide (TiO), zinc oxynitride (ZnON), magnesium zinc oxide (MgZnO), zirconium indium zinc oxide (ZrInZnO), hafnium indium zinc oxide (HfInZnO), tin indium zinc oxide (SnInZnO), aluminum tin indium zinc oxide (AlSnInZnO), silicon indium zinc oxide (SiInZnO), aluminum zinc tin oxide (AlZnSnO), gallium zinc tin oxide (GaZnSnO), and zirconium zinc tin oxide (ZrZnSnO) can be used. Specific adjustments can be made based on actual conditions as long as the leakage current of the transistor meets the requirements.

[0064] These materials have a wider band gap and lower leakage current. For example, when the metal oxide material is IGZO, the leakage current of the transistor is less than or equal to 10-15A to 10-18A, thereby improving the operating performance of dynamic semiconductor devices.

[0065] It should be noted that, in order to make FIG. 1 clearer and easier for readers to read and understand, the substrate and each dielectric layer are not shown (or are shown in the form of transparent graphics) in the top view of FIG. 1 .

[0066] In some embodiments, the memory cell array may further include a plurality of bit lines 14, which extend along the column direction (first direction) and are arranged at intervals along the row direction (second direction), and each bit line 14 is connected to each first source / drain 125 of the transistor 12 of two columns of memory cells; the first direction and the second direction intersect and are both parallel to the substrate 11.

[0067] Referring to Figure 2, in some embodiments, the insulating structure 121 of the transistor 12 in each layer of the memory cell and the bit line 14 are formed by different regions of the same metal layer, the region corresponding to the bit line 14 is a metal layer containing metal, and the region corresponding to the insulating structure 121 is a metal oxide formed after the metal layer is oxidized.

[0068] It can be understood that the area corresponding to the bit line 14 and the area corresponding to the insulating structure 121 contain metal materials of the same type and content, the metal in the insulating structure 121 is oxidized into metal oxide, and the metal oxide is an insulating material, which can insulate the first source / drain 125 and the second source / drain 126 connected at both ends.

[0069] Since part of the same metal layer is oxidized into an insulating structure 121, the other part serves as the bit line 14, the first source / drain 125, and the second source / drain 126, thereby achieving a simplified device structure, reducing the number of manufacturing process steps and lowering manufacturing costs; and since the bit line 14 is made of metal material, the contact resistance with the semiconductor layer is smaller, and the resistance of the bit line itself is also smaller, which can improve the performance of the semiconductor device.

[0070] In some embodiments, the memory cell array may further include a plurality of word lines 13, the word lines 13 extending along a third direction perpendicular to the substrate 11, and surrounding the gate insulation layer 123 or the insulation structure of each transistor stacked in a direction perpendicular to the substrate 11, the gate electrode 124 including an area around the periphery of the gate insulation layer 123 where the word line 13 surrounds the gate electrode 123, and the gate electrode is part of the word line.

[0071] 1 and 2 , in some embodiments, each storage unit further includes a capacitor 21 ; the capacitor 21 includes a first capacitor electrode 211 , a first dielectric layer 212 , and a second capacitor electrode 213 .

[0072] The second source / drain 126 of the transistor 12 and the first capacitor electrode 211 of the capacitor 21 in each layer of the memory cell are different regions of the same metal layer, and the second source / drain 126 and the first capacitor electrode 211 of the capacitor 21 are an integrated structure.

[0073] Since a portion of the same metal layer serves as the second source / drain 126 of the transistor 12 and another portion serves as the first capacitor electrode 211 of the capacitor 21 , process steps can be reduced and manufacturing costs can be lowered.

[0074] Figures 1 to 3 illustrate a three-layer stacked memory cell array, where each layer includes memory cells arranged in two columns and three rows, each memory cell including a transistor 12 and a capacitor 21. Two adjacent memory cells along the row direction (second direction) share a bit line 14, resulting in a total of three bit lines 14 and six word lines 13. It should be noted that the number of memory cell arrays, bit lines 14, and word lines 13 in Figures 1 to 3 is merely exemplary and can be adjusted as needed in actual applications.

[0075] In some embodiments, the material of the first source / drain 125 and the second source / drain 126 includes metallic molybdenum, and the material of the insulating structure 121 includes molybdenum oxide; alternatively, the material of the first source / drain 125 and the second source / drain 126 includes metallic tantalum, and the material of the insulating structure 121 includes tantalum oxide; alternatively, the material of the first source / drain 125 and the second source / drain 126 includes metallic titanium, and the material of the insulating structure 121 includes titanium oxide.

[0076] In other words, the material of the metal layer includes at least one of metal molybdenum, metal tantalum and metal titanium, the first source / drain 125 and the second source / drain 126 are obtained by patterning the metal layer, and the insulating structure 121 is obtained by patterning the metal layer and then oxidizing it.

[0077] Since metal molybdenum, metal tantalum and metal titanium are easily oxidized in an oxygen atmosphere greater than 250°C, the exposed metal layer can be completely oxidized into an insulating structure 121, thereby avoiding the performance of the semiconductor device being affected by the remaining unoxidized metal material in the insulating structure 121.

[0078] The beneficial technical effects brought about by the technical solutions provided in the embodiments of the present application include:

[0079] In the embodiment of the present application, the first source / drain, the insulating structure, and the second source / drain are all made of the same metal material, which is simple in structure and easy to manufacture. In addition, metal materials as electrodes can effectively improve the electrical performance of semiconductor devices.

[0080] Furthermore, the size of the semiconductor layer 122 is defined by the size of the insulating structure, so that the size of the semiconductor layer 122 is more controllable.

[0081] Insulation structure 121 serves as the central structure of the semiconductor layer of transistor 12. Semiconductor layer 122 is disposed around the periphery (sidewalls) of insulation structure 121, surrounding the sidewalls. In the present embodiment, a metal oxide is used to implement an annular channel at least partially surrounded by a gate. Semiconductor layer 122 is an amorphous thin film, which provides a more stable process. This allows for stacking a higher number of layers while maintaining stable electrical properties, avoiding the problem of excessive dislocation density caused by stacking too many layers, and effectively improving the performance of the semiconductor device.

[0082] Based on the same inventive concept, an embodiment of the present application provides an electronic device, which includes a semiconductor device provided in any of the above embodiments.

[0083] In this embodiment, since the electronic device adopts any one of the semiconductor devices provided in the aforementioned embodiments, its principles and technical effects can be referred to in the aforementioned embodiments and will not be described in detail here.

[0084] Optionally, the electronic device may include a storage device, a smart phone, a computer, a tablet computer, an artificial intelligence device, a wearable device or a smart mobile terminal.

[0085] It should be noted that electronic devices are not limited to the above-mentioned ones. Those skilled in the art can set any semiconductor device provided in the above-mentioned embodiments of this application in different devices according to actual application requirements, thereby obtaining the electronic device provided in the embodiments of this application.

[0086] Based on the same inventive concept, an embodiment of the present application provides a method for manufacturing a semiconductor device. A flow chart of the manufacturing method is shown in FIG4 . The method includes steps S100 to S108 .

[0087] S100 : forming a stacked structure on one side of the substrate 11 ; the stacked structure includes multiple first insulating layers 15 and multiple metal layers 16 alternately stacked.

[0088] In some embodiments, the metal layer 16 may be made of metals such as molybdenum, tantalum, or titanium that are easily oxidized in an oxygen atmosphere at high temperatures. The first insulating layer 15 may be made of oxides of molybdenum, tantalum, or titanium.

[0089] Since metal molybdenum, metal tantalum and metal titanium are easily oxidized in an oxygen atmosphere greater than 250°C, the exposed metal layer can be completely oxidized into an insulating structure 121, thereby avoiding the performance of the semiconductor device being affected by the remaining unoxidized metal material in the insulating structure 121.

[0090] S101 : forming a plurality of first through holes 30 penetrating the stacked structure on the stacked structure, wherein the first through holes 30 are arranged at intervals in a column direction.

[0091] In some embodiments, in a column of first through-vias 30 , any two adjacent first through-vias 30 include first metal structures 161 in the metal layer 16 and insulating portions 151 in the first insulating layer 15 alternately stacked in a direction perpendicular to the substrate 11 .

[0092] 11 and 26 , in a column of first through holes 30 , each first through hole 30 is arranged along the column direction (first direction); the metal layer 16 between two adjacent columns of first through holes 30 forms a metal line 162, and the metal line 162 includes a first source / drain 125 and a bit line 14 distributed along the row direction (second direction) or in the width direction of the metal line; the first direction and the second direction intersect and are both parallel to the substrate 11.

[0093] In some embodiments, after step S100 , the method may further include forming a protective layer 17 on a side of the stacked structure away from the substrate 11 . Step S101 includes forming at least two rows of first through holes 30 on the protective layer 17 that penetrate the stacked structure and the protective layer 17 .

[0094] FIG5 is a schematic diagram of a cross-sectional structure perpendicular to the substrate 11 after the stacked structure and the protective layer 17 are sequentially formed away from the substrate 11 .

[0095] In some embodiments, the material of the protection layer 17 may be silicon nitride.

[0096] The patterned protection layer 17 can prevent the portion of the metal layer 16 other than the first metal structure 161 from being oxidized.

[0097] Figure 6 is a top view of the rear edge of multiple first through holes 30 formed through the stacked structure and the protective layer 17, which is parallel to the substrate 11; Figure 7 is a schematic diagram of the cross-sectional structure perpendicular to the substrate 11 along the AA direction after the rear edge of multiple first through holes 30 formed through the stacked structure and the protective layer 17 is parallel to the substrate 11; Figure 8 is a schematic diagram of the cross-sectional structure perpendicular to the substrate 11 along the BB direction after the rear edge of multiple first through holes 30 formed through the stacked structure and the protective layer 17.

[0098] Before step S103 , the process may further include removing the protective layer 17 between any adjacent first through holes 30 in each column to expose the first metal structure 161 formed by the metal layer 16 between any adjacent first through holes 30 in each column.

[0099] Figure 9 is a top view parallel to the substrate 11 after removing the protective layer 17 between any adjacent first through holes 30 in each column; Figure 10 is a schematic diagram of the cross-sectional structure perpendicular to the substrate 11 along the BB direction after removing the protective layer 17 between any adjacent first through holes 30 in each column.

[0100] It should be noted that the cross-sectional structure diagram perpendicular to the substrate 11 along the AA direction after removing the protective layer 17 between any adjacent first through holes 30 in each column is similar to FIG. 7 and will not be repeated here.

[0101] Referring to Figure 10, the first trench 40 is formed after removing the protective layer 17 between any adjacent first through holes 30 in each column, and the bottom of the first trench 40 exposes the first metal structure 161 formed by the metal layer 16 between any adjacent first through holes 30 in each column, thereby ensuring that the topmost first metal structure 161 can be fully oxidized by the subsequent oxidation process.

[0102] S102 : removing the exposed insulating portion 151 between any two adjacent first through-holes 30 in each column of the first through-holes 30 to expose the sidewall regions of the first metal structure 161 (also referred to as the exposed metal layer) between the first through-holes 30 .

[0103] In other words, the insulating portion 151 between any adjacent first metal structures 161 along the third direction is removed through the first through hole 30 , and the third direction is perpendicular to the substrate 11 .

[0104] The first metal structure 161 is the metal layer 16 between any adjacent first through holes 30 in each column.

[0105] 11 is a schematic cross-sectional structure diagram perpendicular to the substrate along the BB direction after removing the insulating portion 151 exposed between any two adjacent first through holes 30 in each column of the first through holes 30 to expose the sidewall regions of the first metal structure 161 between the first through holes 30 .

[0106] It should be noted that, after removing the insulating portion 151 exposed between any two adjacent first through holes 30 in each column of first through holes 30, the top view parallel to the substrate 11 of the side wall regions of the first metal structure 161 between the first through holes 30 is exposed is similar to Figure 6; after removing the insulating portion 151 exposed between any two adjacent first through holes 30 in each column of first through holes 30, the schematic diagram of the cross-sectional structure perpendicular to the substrate 11 along the AA direction is similar to Figure 7, and will not be repeated here.

[0107] Referring to FIG. 11 , after removing the exposed insulating portion 151 between any two adjacent first through-holes 30 in each column of first through-holes 30 through the first through-holes 30, a second trench 50 is formed. The second trench 50 penetrates two adjacent first through-holes 30, exposing the first metal structure 161 formed by the metal layer 16 between any adjacent first through-holes 30 in each column, so that the first metal structure 161 can be oxidized into the initial insulating structure 18 in a subsequent oxidation process. The first metal structure 161 extends along the row direction and has two ends and a sidewall between the two ends in the extension direction. The sidewall is the outer periphery of the first metal structure 161 mentioned above.

[0108] S103 : performing an oxidation process on the exposed first metal structure 161 , so that the first metal structure 161 is oxidized into an initial insulating structure 18 .

[0109] Figure 12 is a top view parallel to the substrate 11 after the exposed first metal structure 161 is oxidized into the initial insulating structure 18; Figure 13 is a schematic diagram of the cross-sectional structure perpendicular to the substrate 11 along the BB direction after the exposed first metal structure 161 is oxidized into the initial insulating structure 18.

[0110] It should be noted that the exposed first metal structure 161 is oxidized so that the cross-sectional structure diagram of the first metal structure 161 perpendicular to the substrate 11 along the AA direction after oxidation into the initial insulating structure 18 is similar to FIG. 7 , which will not be repeated here.

[0111] In some embodiments, step S103 may include: performing an annealing process on the exposed first metal structure 161 in an oxygen atmosphere at a temperature higher than 250 degrees Celsius, so that the first metal structure 161 is transformed into the insulating structure 121 .

[0112] Optionally, the material of the first source / drain 125 and the second source / drain 126 includes at least one of metal molybdenum, metal tantalum, and metal titanium. In other words, the material of the first metal structure 161 can be a metal that is easily oxidized in an oxygen atmosphere at a high temperature, such as metal molybdenum, metal tantalum, or metal titanium.

[0113] As the oxidation temperature increases, the thickness of the tantalum oxide gradually increases. For example, if the oxidation time is 1 hour and the oxidation temperature is 250 degrees Celsius, the thickness of the tantalum oxide is 4 nanometers; if the oxidation time is 1 hour and the oxidation temperature is 450 degrees Celsius, the thickness of the tantalum oxide is 29 nanometers.

[0114] Therefore, in some embodiments, the thickness of the metal layer 16 can be set to 40 nanometers to 80 nanometers, optionally to 60 nanometers, the oxidation temperature can be set to 250°C-550°C, optionally to 450°C, and the oxidation time can be set to 2 hours to 4 hours, optionally to 3 hours, so as to ensure that the first metal structure 161 is completely oxidized and avoid direct conduction of the metal on both sides of the transistor 12.

[0115] S104 : performing a thinning process on the initial insulating structure 18 , that is, removing a certain thickness of material from the periphery of the initial insulating structure 18 to obtain an insulating structure 121 after the periphery is thinned. The diameter and thickness of the longitudinal section of the insulating structure 121 become smaller.

[0116] Specifically, the initial insulating structure 18 extends along the second direction, and has two ends and a sidewall between the two ends in the extending direction. The sidewall is the outer peripheral portion of the initial insulating structure 18 mentioned above.

[0117] Figure 14 is a top view parallel to the substrate 11 of the insulating structure 121 obtained after the peripheral portion of the initial insulating structure 18 is removed; Figure 15 is a schematic diagram of the cross-sectional structure perpendicular to the substrate 11 along the BB direction after the peripheral portion of the initial insulating structure 18 is removed to obtain the insulating structure 121.

[0118] It should be noted that after removing the outer peripheral portion of the initial insulating structure 18 to obtain the insulating structure 121 , the cross-sectional structural diagram along the AA direction perpendicular to the substrate 11 is similar to FIG. 7 and will not be repeated here.

[0119] 15 , after the outer peripheral portion of the initial insulating structure 18 is removed, the end surface of the metal wire 162 can be exposed, facilitating the connection between the subsequently manufactured semiconductor layer 122 and the first source / drain 125 of the metal wire 162 .

[0120] S105 : forming a semiconductor layer 122 covering the first source / drain 125 and the second source / drain 126 at least on the outer periphery of the insulating structure 121 .

[0121] Along the second direction, two ends of the semiconductor layer 122 are connected to the first source / drain 125 and the second source / drain 126 respectively.

[0122] In some embodiments, step S105 includes the following sub-steps S51 to S52:

[0123] S51 : etching back the first insulating layer 15 in the row direction in the first through hole 30 to form two transverse grooves, wherein the two transverse grooves respectively expose a portion of the unoxidized metal layer.

[0124] The unoxidized metal layers in the two transverse grooves are respectively a part of the first source / drain 125 and the second source / drain 126 .

[0125] That is, by wet etching, part of the first insulating layer 15 is etched, thereby expanding the size of the second trench 50 along the second direction to form a third trench 60, thereby exposing part of the metal line 162, making it easier for subsequent processes to remove the parasitic semiconductor layer there to remove the parasitic transistor; at the same time, after the third trench 60 is expanded to form the hole, more contact can be achieved between the semiconductor layer 122 and the first source / drain 125 and the bit line 14 of the metal line 162, thereby improving contact reliability.

[0126] In some embodiments, step S51 may further include: removing the protective layer 17 remaining after the steps corresponding to Figures 9 and 10 (i.e., removing the protective layer 17 between any adjacent first through holes 30 in each column), thereby exposing the topmost metal layer 16 (the metal layer 16 farthest from the substrate 11).

[0127] Figure 16 is a top view parallel to the substrate 11 after removing the remaining protective layer 17 and removing part of the first insulating layer 15 in the stacked structure through the first through hole 30 to expose part of the metal wire 162; Figure 17 is a schematic diagram of the cross-sectional structure perpendicular to the substrate 11 along the AA direction after removing the remaining protective layer 17 and removing part of the first insulating layer 15 in the stacked structure through the first through hole 30 to expose part of the metal wire 162; Figure 18 is a schematic diagram of the cross-sectional structure perpendicular to the substrate 11 along the BB direction after removing the remaining protective layer 17 and removing part of the first insulating layer 15 in the stacked structure through the first through hole 30 to expose part of the metal wire 162.

[0128] S52 : manufacturing a semiconductor layer 122 around the outer periphery of the insulating structure 121 and within the lateral grooves.

[0129] In some embodiments, step S52 may include depositing a semiconductor layer 122 in the region where the first through-hole 30 and the third trench 60 are exposed.

[0130] That is, both ends of the semiconductor layer 122 respectively cover the peripheries of the first source / drain electrode 125 and the second source / drain electrode 126 .

[0131] S106 : manufacturing a gate insulating layer 123 on the periphery of the semiconductor layer 122 and only in the corresponding area of ​​the insulating structure 121 , and forming a word line 13 extending in a direction perpendicular to the substrate 11 and surrounding the gate insulating layer 123 of each transistor 12 stacked in the direction perpendicular to the substrate 11 .

[0132] The gate insulating layer 123 may be made of a high-K material, and the gate electrode 124 and the word line 13 may be made of indium tin oxide. The gate electrode 124 is part of the word line 13 , specifically, the gate electrode 124 is the area where the word line 13 surrounds the gate insulating layer 123 .

[0133] In other words, step S106 may include: after manufacturing the semiconductor layer 122 , forming the gate insulating layer 123 and the word line 13 in the region exposed by the first through hole 30 and the third trench 60 .

[0134] It should be noted that two adjacent word lines 13 are disconnected at the sidewall and bottom of the first through hole 30 to ensure insulation between the two.

[0135] Figure 19 is a top view parallel to the substrate 11 after the semiconductor layer 122 is manufactured on the periphery of the insulating structure 121 and the periphery of the first source / drain 125 and the second source / drain 126, and the gate insulating layer 123 is manufactured on the periphery of the semiconductor layer 122; Figure 20 is a schematic diagram of the cross-sectional structure perpendicular to the substrate 11 along the BB direction after the semiconductor layer 122 is manufactured on the periphery of the insulating structure 121 and the periphery of the first source / drain 125 and the second source / drain 126, and the gate insulating layer 123 is manufactured on the periphery of the semiconductor layer 122.

[0136] It should be noted that after a semiconductor layer 122 is manufactured on the periphery of the insulating structure 121 and the periphery of the first source / drain 125 and the second source / drain 126, and a gate insulating layer 123 is manufactured on the periphery of the semiconductor layer 122, the schematic diagram of the cross-sectional structure perpendicular to the substrate 11 along the AA direction is similar to Figure 17 and will not be repeated here.

[0137] 21 is a top view parallel to the substrate 11 after the word line 13 is manufactured on the periphery of the gate insulating layer 123 ; FIG. 22 is a schematic cross-sectional structure diagram perpendicular to the substrate 11 along the BB direction after the word line 13 is manufactured on the periphery of the gate insulating layer 123 .

[0138] It should be noted that the cross-sectional structural diagram perpendicular to the substrate 11 along the AA direction after the word line 13 is manufactured on the periphery of the gate insulating layer 123 is similar to FIG17 , and will not be repeated here.

[0139] In some embodiments, after step S106, the following steps S107 to S108 may be further included:

[0140] S107: forming a second through hole 70 penetrating the stacked structure.

[0141] In some embodiments, each second via 70 in at least one column of second vias 70 is located between each first source / drain 125 of a column of transistors, and each second via 70 in at least another column of second vias 70 is located between each second source / drain 126 of a column of transistors.

[0142] In some embodiments, step S107 may include: forming a penetrating second through hole 70 at the stacked structure including the second metal structure, so that the second metal structure is divided into at least one column of electrodes arranged along the column direction, the electrode including a first capacitor electrode 211 and a second source / drain 126 distributed along the row direction; the second metal structure is a metal layer 16 located on one side of two adjacent columns of first through holes 30 along the row direction.

[0143] Optionally, the second through-hole 70 can be used not only to disconnect the metal layer 16 to form the multiple first capacitor electrodes 211, but also to etch the parasitic semiconductor layer. Of course, different through-holes can also be provided to respectively disconnect the metal layer 16 to form the multiple first capacitor electrodes 211 and etch the parasitic semiconductor layer, which is not limited here.

[0144] In other words, by increasing the size of the second through hole 70 along the second direction, it is not only convenient for the first etching solution to flow in from the second through hole 70 to remove the semiconductor layer 122 between adjacent transistors 12 along the third direction (specifically, remove the parasitic semiconductor layer between the second source / drain 126 of adjacent layers or between the first source / drain 125 of adjacent layers) to remove the parasitic transistors, but also the second metal structure can be divided into at least one column of electrodes arranged along the column direction, and it is also convenient for the second etching solution to flow in from the second through hole 70 to remove the first insulating layer 15 between adjacent second metal structures along the third direction, thereby reserving space for the subsequent formation of the first dielectric layer 212 and the second capacitor electrode 213 of the capacitor 21.

[0145] S108 : exposing the semiconductor layer in the transverse grooves through the second through-holes 70 , and removing the semiconductor layer in each transverse groove, so as to disconnect the semiconductor layers 122 of the transistors 12 stacked in the third direction.

[0146] Figure 23 is a top view parallel to the substrate 11 after the semiconductor layer 122 between adjacent transistors 12 along the third direction is removed through the second through hole 70; Figure 24 is a schematic diagram of the cross-sectional structure perpendicular to the substrate 11 along the BB direction after the semiconductor layer 122 between adjacent transistors 12 along the third direction is removed through the second through hole 70.

[0147] It should be noted that after removing the semiconductor layer 122 between adjacent transistors 12 along the third direction through the second through hole 70 , the cross-sectional structural diagram perpendicular to the substrate 11 along the AA direction is similar to FIG17 and will not be repeated here.

[0148] By removing the semiconductor layer 122 between adjacent transistors 12 along the third direction through the second through hole 70, the semiconductor layer 122 of the adjacent transistors 12 stacked in the third direction can be completely disconnected, and the parasitic semiconductor layer between the second source / drain 126 of the adjacent layers or between the first source / drain 125 of the adjacent layers can be removed, thereby removing the parasitic transistors.

[0149] In some embodiments, after step S108 , the following steps may be performed: a first dielectric layer 212 and a second capacitor electrode 213 are sequentially manufactured around the first capacitor electrode 211 to form a capacitor 21 ; and the first capacitor electrode 211 of the capacitor 21 is connected to the semiconductor layer 122 of the transistor 12 .

[0150] The material of the first dielectric layer 212 may be a high-K material, and the material of the second capacitor electrode 213 may be titanium nitride.

[0151] Figure 25 shows a schematic cross-sectional structure perpendicular to substrate 11 along the BB direction after capacitor 21 is formed by sequentially fabricating a first dielectric layer 212 and a second capacitor electrode 213 around the periphery of first capacitor electrode 211. In some embodiments, after forming capacitor 21, a second insulating layer 19 may be added to fill the gaps in the intermediate structure after capacitor 21 is formed. This arrangement provides both protection and packaging.

[0152] The material of the second insulating layer 19 can be oxide such as silicon dioxide.

[0153] FIG26 is a schematic diagram of a cross-sectional structure perpendicular to the substrate 11 along the BB direction after the second insulating layer 19 is filled in the gap of the intermediate structure after the capacitor 21 is formed.

[0154] This embodiment is a manufacturing method corresponding to the semiconductor device in the aforementioned embodiment. Therefore, the technical details and technical effects of this embodiment and the aforementioned semiconductor device embodiment can be referenced to each other and will not be repeated here.

[0155] Those skilled in the art will appreciate that the steps, measures, and schemes in the various operations, methods, and processes discussed in this application may be interchanged, modified, combined, or deleted. Furthermore, other steps, measures, and schemes in the various operations, methods, and processes discussed in this application may also be interchanged, modified, rearranged, decomposed, combined, or deleted. Furthermore, steps, measures, and schemes in the related art that are similar to those disclosed in this application may also be interchanged, modified, rearranged, decomposed, combined, or deleted.

[0156] In the description of the present application, the directions or positional relationships indicated by words such as "center", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", and "outside" are based on the exemplary directions or positional relationships shown in the accompanying drawings. They are for the convenience of describing or simplifying the description of the embodiments of the present application, and do not indicate or imply that the device or component referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be understood as limitations on the present application.

[0157] The terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of the technical features being referred to. Thus, a feature specified as "first" or "second" may explicitly or implicitly include one or more of such features. Throughout this application, unless otherwise specified, "plurality" means two or more.

[0158] In the description of this application, it should be noted that, unless otherwise expressly specified or limited, the terms "installed", "connected", and "connected" should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a direct connection, an indirect connection through an intermediate medium, or a communication between the two components. For those of ordinary skill in the art, the specific meanings of the above terms in this application can be understood in specific circumstances. In the description of this specification, specific features, structures, materials, or characteristics can be combined in an appropriate manner in any one or more embodiments or examples.

[0159] The technical features of the above-described embodiments can be combined arbitrarily. In order to make the description concise, not all possible combinations of the technical features in the above-described embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification. The above-described embodiments only express several implementation methods of the present application, and their descriptions are relatively specific and detailed, but they cannot be understood as limiting the scope of the patent application. It should be pointed out that for ordinary technicians in this field, without departing from the concept of the present application, several variations and improvements can be made, which all fall within the scope of protection of the present application. Therefore, the scope of protection of the patent application of this application shall be based on the attached claims.

Claims

1. A semiconductor device comprising: Multi-layer stacked memory cell array; The memory cell array includes a plurality of memory cells stacked in a direction perpendicular to the substrate; each memory cell includes a transistor, the transistor including a first source / drain, an insulating structure, and a second source / drain arranged in sequence, and a semiconductor layer, a gate insulating layer, and a gate electrode surrounding the outer periphery of the insulating structure in sequence; and The material of the first source / drain and the second source / drain comprises metal, and the material of the insulating structure comprises metal oxide of the metal. 2 . The semiconductor device according to claim 1 , wherein a thickness of the insulating structure in a direction perpendicular to the substrate is smaller than a thickness of the first source / drain or the second source / drain in the direction perpendicular to the substrate.

3. The semiconductor device according to claim 1 or 2, wherein the insulating structure includes sidewalls in an extension direction extending from the first source / drain to the second source / drain, and the semiconductor layer surrounds the sidewalls of the insulating structure and extends onto the first source / drain and the second source / drain to contact the first source / drain and the second source / drain.

4. The semiconductor device according to claim 1, wherein the memory cell array further comprises a plurality of bit lines, the bit lines extending in a column direction and arranged at intervals in a row direction, each of the bit lines being connected to the first source / drain of each of the transistors of two columns of the memory cells.

5. The semiconductor device according to claim 1, wherein each of the memory cells further comprises a capacitor; the capacitor comprises a first capacitor electrode, a first dielectric layer, and a second capacitor electrode; The second source / drain of the transistor in each layer of the storage unit and the first capacitor electrode of the capacitor are different regions of the same metal layer.

6. The semiconductor device according to claim 1, wherein a material selected from the group consisting of the first source / drain and the second source / drain comprises metallic molybdenum, and a material of the insulating structure comprises molybdenum oxide; The materials of the first source / drain and the second source / drain include metallic tantalum, and the material of the insulating structure includes tantalum oxide; and The materials of the first source / drain and the second source / drain include metallic titanium, and the material of the insulating structure includes a group consisting of titanium oxide.

7. The semiconductor device according to claim 1, wherein the memory cell array further comprises a plurality of word lines, the word lines extending in a direction perpendicular to the substrate and surrounding the gate insulation layers of each transistor stacked in a direction perpendicular to the substrate, and the gate electrode comprising an area where the word lines surround the periphery of the gate insulation layer. The semiconductor device according to claim 1 , wherein a material of the semiconductor layer comprises a metal oxide.

9. An electronic device comprising: A semiconductor device as claimed in any one of claims 1 to 8.

10. A method for manufacturing a semiconductor device, comprising: forming a stacked structure located on one side of the substrate, the stacked structure comprising a plurality of first insulating layers and a plurality of metal layers alternately stacked; forming a plurality of first through holes penetrating the stacked structure on the stacked structure, wherein the first through holes are arranged at intervals in a column direction; A plurality of the metal layers and a plurality of the first insulating layers are stacked between any two adjacent first through holes; removing the first insulating layers exposed between any two adjacent first through holes to expose the sidewall regions of the metal layers between the first through holes; The exposed metal layer is oxidized, and the metal oxide layer formed after oxidation serves as an insulating structure; and A semiconductor layer, a gate insulating layer and a gate electrode are sequentially formed at least on the periphery of the insulating structure.

11. The method for manufacturing a semiconductor device according to claim 10, wherein forming a semiconductor layer, a gate insulating layer, and a gate electrode in sequence at least on the periphery of the insulating structure comprises: Carving back the first insulating layer in the row direction in the first through hole to form two transverse grooves, wherein the two transverse grooves respectively expose a portion of the unoxidized metal layer; and A semiconductor layer, a gate insulating layer and a gate electrode are sequentially formed on the periphery of the insulating structure and in the lateral groove; wherein the unoxidized metal layers in the two lateral grooves are parts of the first source / drain and the second source / drain respectively.

12. The method for manufacturing a semiconductor device according to claim 11, wherein after sequentially forming a semiconductor layer, a gate insulating layer, and a gate electrode on the periphery of the insulating structure, the method further comprises: forming a second through hole penetrating the stacked structure; and The semiconductor layer in the transverse groove is exposed through the second through hole, and the semiconductor layer in each transverse groove is removed, so as to disconnect the semiconductor layers of the transistors stacked in a direction perpendicular to the substrate. 13 . The method for manufacturing a semiconductor device according to claim 10 , wherein the exposed metal layer comprises at least one of metal molybdenum, metal tantalum, and metal titanium.

14. The method for manufacturing a semiconductor device according to claim 10, wherein before sequentially forming a semiconductor layer, a gate insulating layer, and a gate electrode on the periphery of the insulating structure, the method further comprises: The insulating structure is thinned.

15. The method for manufacturing a semiconductor device according to claim 10, wherein the step of performing an oxidation treatment on the exposed metal layer comprises: The exposed metal layer is annealed in an oxygen atmosphere at a temperature higher than 250 degrees Celsius, so that the exposed metal layer is oxidized to form a metal oxide layer.

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