Semiconductor device and dynamic random access memory

Abstract

Provided in the present disclosure are a semiconductor device and a dynamic random access memory. The semiconductor device comprises: a substrate; and a first structural unit arranged on the substrate. The first structural unit comprises transistors, the multiple transistors being stacked in a first direction. Each transistor comprises: a gate structure, an active layer, a first electrode and a second electrode; the first electrode and the second electrode are arranged on the two sides of the gate structure in a second direction, the active layer being connected to the first electrode and the second electrode; the active layer comprises a channel region, the channel region being located between the first electrode and the second electrode. The gate structures of the multiple transistors are connected in a first direction, the first direction intersecting the plane where the substrate is located, and the second direction intersecting the first direction; the multiple transistors at least comprise a first transistor and a second transistor, the width of the channel region of the first transistor far away from the substrate in the first direction being less than the width of the channel region of the second transistor close to the substrate in the first direction.

Description

Semiconductor devices and dynamic random access memory

[0001] This disclosure is based on and claims the priority of Chinese patent application with application number 202410374584.2, application date March 29, 2024, and application name “Semiconductor Device and Dynamic Random Access Memory”. The entire content of this Chinese patent application is hereby introduced into this disclosure as a reference. Technical Field

[0002] The present disclosure relates to the technical field of integrated circuits, and in particular to a semiconductor structure, and more specifically to a three-dimensional dynamic memory structure. Background Art

[0003] With the development of dynamic random access memory (DRAM) technology, the size of storage cells has become smaller and smaller, and traditional structures have reached their limits. In order to pursue higher-capacity DRAM devices, engineers have developed a three-dimensional dynamic memory structure.

[0004] However, as the number of layers of three-dimensional dynamic memory structures increases, many technical problems that have never been encountered in traditional structures arise during the manufacturing process and need to be solved urgently.

[0005] Summary of the Invention

[0006] Based on this, the present disclosure provides a semiconductor structure and a method for preparing the same, which can reduce the size of the device and reduce the difficulty of the preparation process.

[0007] According to one embodiment of the present invention, a semiconductor device includes: a substrate; a first structural unit disposed on the substrate, the first structural unit including: a transistor, wherein a plurality of transistors are stacked along a first direction;

[0008] The transistor includes: a gate structure, an active layer, a first electrode and a second electrode, the first electrode and the second electrode are arranged on both sides of the gate structure along a second direction, the active layer connects the first electrode and the second electrode, the active layer includes a channel region, and the channel region is located between the first electrode and the second electrode;

[0009] The gate structures of the plurality of transistors are connected along a first direction;

[0010] The first direction intersects with the plane of the substrate, and the second direction intersects with the first direction;

[0011] The plurality of transistors include at least a first transistor and a second transistor, wherein a channel region width of the first transistor farther from the substrate along a first direction is smaller than a channel region width of the second transistor closer to the substrate.

[0012] According to another embodiment of the present invention, in a semiconductor device, the channel region widths of a plurality of transistors decrease as the distance from the substrate increases along a first direction.

[0013] According to another embodiment of the present invention, a semiconductor device includes a plurality of first structure units stacked along a first direction, wherein gate structures of the plurality of first structure units are connected along the first direction.

[0014] According to another embodiment of the present invention, a semiconductor device includes a plurality of first structure units arranged along a third direction, the third direction intersecting with a second direction;

[0015] The second electrodes of the transistors arranged in the same layer in the plurality of first structural units are connected to the same bit line, and the bit line is arranged along the third direction.

[0016] According to another embodiment of the present invention, in a semiconductor device, the first structural unit further includes:

[0017] Capacitor structure, multiple capacitor structures are stacked along a first direction; the capacitor structure includes a first capacitor electrode, a second capacitor electrode, and a capacitor dielectric layer, and the capacitor dielectric layer is arranged between the first capacitor electrode and the second capacitor electrode; multiple capacitor structures are arranged corresponding to multiple transistors in the second direction, and the first capacitor electrodes of the capacitor structures are connected to the first electrodes of the corresponding transistors; the second capacitor electrodes of the multiple capacitor structures are connected along the first direction.

[0018] According to another embodiment of the present invention, in a semiconductor device, the first capacitor electrode is arranged in a ring shape around the second capacitor electrode, and the width of the second capacitor electrode corresponding to the first transistor in the first direction is smaller than the width of the second capacitor electrode corresponding to the second transistor in the first direction.

[0019] According to another embodiment of the present invention, in a semiconductor device, the material of the active layer is an oxide semiconductor material.

[0020] According to another embodiment of the present invention, in a semiconductor device, the oxide semiconductor material is tin-doped indium gallium zinc metal oxide.

[0021] According to another embodiment of the present invention, in a semiconductor device, the second electrode and / or the first electrode is selected from one or more of metal ruthenium, metal molybdenum, ruthenium oxide, or molybdenum oxide.

[0022] According to another embodiment of the present invention, in a semiconductor device, the first capacitor electrode is selected from one or more of metal ruthenium, metal molybdenum, ruthenium oxide, or molybdenum oxide.

[0023] According to another embodiment of the present invention, in a semiconductor device, the first capacitor electrode and the first electrode are integrally formed.

[0024] According to another embodiment of the present invention, in a semiconductor device, the first capacitor electrode and the first electrode include metal ruthenium.

[0025] According to another embodiment of the present invention, in a semiconductor device, the capacitor dielectric layer includes strontium titanium oxide.

[0026] According to one embodiment of the present invention, a dynamic random access memory includes: the aforementioned semiconductor device; a sub-word line driver connected to the gate structure; and a sense amplifier connected to the second electrode.

[0027] According to another embodiment of the present invention, in a dynamic random access memory, a sub-word line driver and / or a sense amplifier is disposed on a substrate.

[0028] According to another embodiment of the present invention, in a dynamic random access memory, a sub-word line driver and / or a sense amplifier are disposed on a control substrate, and the control substrate is bonded to a substrate.

[0029] The semiconductor structure and dynamic random access memory provided by the present disclosure have at least the following beneficial effects:

[0030] The semiconductor structure and dynamic random access memory provided by the present disclosure have better uniformity between transistors in different layers, higher storage capacity, better semiconductor performance, and better storage performance. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] In order to more clearly illustrate the embodiments of the present disclosure or the technical solutions in the traditional technology, the following briefly introduces the drawings required for use in the embodiments or the description of the traditional technology. Obviously, the drawings described below are only some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0032] FIG1 is a schematic diagram of a semiconductor structure provided by some embodiments of the present disclosure;

[0033] FIG2 is a schematic diagram of a semiconductor structure provided by other embodiments of the present disclosure;

[0034] FIG3 is a schematic diagram of a semiconductor structure provided by other embodiments of the present disclosure;

[0035] FIG4 is a schematic diagram of a semiconductor structure provided by other embodiments of the present disclosure;

[0036] FIG5 is a schematic diagram of a dynamic random access memory provided by some embodiments of the present disclosure;

[0037] FIG6 is a schematic diagram of a dynamic random access memory provided by other embodiments of the present disclosure;

[0038] FIG7 is a schematic diagram of a dynamic random access memory provided by other embodiments of the present disclosure; DETAILED DESCRIPTION

[0039] To facilitate understanding of the present disclosure, a more comprehensive description of the present disclosure will be provided below with reference to the accompanying drawings. The drawings illustrate preferred embodiments of the present disclosure. However, the present disclosure can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided to provide a more thorough and comprehensive understanding of the present disclosure.

[0040] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art in the art of the present disclosure. The terms used herein in the specification of the present disclosure are only for the purpose of describing specific embodiments and are not intended to limit the present disclosure.

[0041] It should be understood that when an element or layer is referred to as being "on," "adjacent to," "connected to," or "coupled to" another element or layer, it can be directly on, adjacent to, connected to, or coupled to the other element or layer, or there can be intervening elements or layers. Conversely, when an element is referred to as being "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" another element or layer, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, doping types, and / or portions, these elements, components, regions, layers, doping types, and / or portions should not be limited by these terms. These terms are merely used to distinguish one element, component, region, layer, doping type, or portion from another element, component, region, layer, doping type, or portion. Therefore, without departing from the teachings of the present invention, the first element, component, region, layer, doping type or portion discussed below may be represented as a second element, component, region, layer or portion; for example, the first doping type may be referred to as the second doping type, and similarly, the second doping type may be referred to as the first doping type; the first doping type and the second doping type are different doping types, for example, the first doping type may be P-type and the second doping type may be N-type, or the first doping type may be N-type and the second doping type may be P-type.

[0042] Spatially relative terms such as "under," "beneath," "beneath," "under," "above," "above," etc., may be used herein to describe the relationship of an element or feature shown in the figures to other elements or features. It should be understood that in addition to the orientations shown in the figures, spatially relative terms also include different orientations of the device in use and operation. For example, if the device in the drawings is turned over, the element or feature described as "under" or "beneath" or "beneath" the other elements will be oriented as "above" the other elements or features. Thus, the exemplary terms "under" and "under" can include both upper and lower orientations. In addition, the device can also include alternative orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptors used herein are interpreted accordingly.

[0043] As used herein, the singular forms "a," "an," and "the" may also include the plural forms, unless the context clearly indicates otherwise. It should also be understood that when the terms "comprising" and / or "including" are used in this specification, they may specify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. At the same time, when used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0044] Embodiments of the invention are described herein with reference to cross-sectional views which are schematic illustrations of idealized embodiments (and intermediate structures) of the invention, such that variations in the shapes shown due to, for example, manufacturing techniques and / or tolerances are anticipated. Accordingly, embodiments of the invention should not be limited to the specific shapes of the regions shown herein, but rather include deviations in shapes due to, for example, manufacturing techniques. For example, an implanted region shown as a rectangle typically has rounded or curved features and / or an implant concentration gradient at its edges rather than a binary change from an implanted region to a non-implanted region. Similarly, a buried region formed by implantation may result in some implantation in the region between the buried region and the surface through which the implantation occurs. Accordingly, the regions shown in the figures are schematic in nature, their shapes do not represent the actual shape of the region of the device, and do not limit the scope of the invention.

[0045] In a related embodiment, a three-dimensional stacked transistor structure is a new type of semiconductor structure that is often used in high-density integrated circuit structures due to its excellent capacity expansion capability. In a three-dimensional stacked transistor structure, the source and drain are arranged in the same layer, and there is a hole passing through the stacked structure between the source and drain. The active layer and the gate structure are arranged in the hole, and the active layer corresponding to the source and drain is the channel region. During the research and development process, the inventors found that if the thickness between the layers of the stacked structure is uniform, the performance of the transistor structure of the upper layer and the transistor structure of the lower layer are different, and the uniformity is poor. As the number of deposited layers increases, the difference in performance between the transistor of the upper layer and the transistor of the lower layer becomes more and more obvious.

[0046] The inventor obtained the measurement results through simulation software and then analyzed the simulation results to find the following problems:

[0047] As the number of stacked transistor layers increases, the diffusion rate of the etching solution during the creation of the hole between the source and drain electrodes causes the upper layer's hole diameter to become larger than the lower layer's, resulting in a tapered cross-section perpendicular to the substrate. This tapered cross-section changes the channel length, resulting in a gradual decrease in transistor performance from the upper layer to the lower layer at the same gate turn-on voltage.

[0048] In view of this, the present disclosure provides a semiconductor device in some embodiments as shown in FIG1 , the semiconductor device 10, comprising: a substrate 1000; a first structural unit 100 disposed on the substrate 1000, the first structural unit 100 comprising: transistors (900, 910, 920, 930), a plurality of transistors (900, 910, 920, 930) stacked along a first direction D1; taking transistor 900 as an example, it comprises: a gate structure 400, an active layer 500, a first electrode 200 and a second electrode 300, the first electrode 200 and the second electrode 300 being disposed on both sides of the gate structure 400 along a second direction D2, the active layer 500 being connected to the first electrode 400. The active layer 500 includes a first electrode 200 and a second electrode 300, and the active layer 500 includes a channel region 600, and the channel region 600 is located between the first electrode 200 and the second electrode 300; the gate structures of the plurality of transistors (900, 910, 920, 930) are connected along a first direction D1; the first direction D1 intersects with the plane of the substrate 1000, and the second direction D2 intersects with the first direction D1; the plurality of transistors (900, 910, 920, 930) include at least a first transistor and a second transistor, wherein the channel region width W of a transistor farther from the substrate along the first direction D1, such as the first transistor 930, is smaller than the channel region width W of the second transistor 900 closer to the substrate. A third direction D3 intersects with the second direction D2.

[0049] In some other embodiments, optionally, the channel region widths of the plurality of transistors decrease as they are farther from the substrate along the first direction.

[0050] The specific preparation method is as follows: first, a stacked structure is prepared on a substrate. The stacked structure is made by alternating deposition of two different material layers. The two material layers have a certain etching selectivity ratio, which is used for selective etching to form the required structure in the subsequent preparation process. One material layer is a support layer and the other material layer is a sacrificial layer. Optionally, silicon layers and silicon germanium layers are alternately deposited to form the stacked structure; alternatively, silicon nitride and silicon oxide are alternately deposited to form the stacked structure. By adjusting one or more of the deposition rate, deposition time, reaction temperature, or reaction gas flow rate of each layer, the thickness of the deposited layer is adjusted, so that the thickness of the support layer closer to the substrate is greater than the thickness of the support layer farther away from the substrate.

[0051] In other embodiments, the thickness of the support layer gradually decreases as the distance from the substrate increases.

[0052] In other embodiments, the thickness of the support layer decreases as a whole with increasing distance from the substrate, but the thickness of adjacent support layers can be equal, for example, the thickness of every few support layers is equal, and the thickness of the subsequently deposited support layers is also equal but less than the thickness of the previously deposited support layers.

[0053] In other embodiments, the sacrificial layers have the same thickness.

[0054] In other embodiments, the sacrificial layer has a thickness that decreases as it moves away from the substrate, similar to that of the support layer.

[0055] In other embodiments, the sacrificial layer has an opposite trend to that of the support layer, that is, the thickness of the sacrificial layer gradually increases as the distance from the substrate increases.

[0056] In other embodiments, the deposition method may be selected from one or more of high temperature furnace tube, chemical vapor deposition, physical vapor deposition or atomic layer deposition.

[0057] Two spaced holes or grooves are formed in the stacked structure obtained above through an etching process. The support layer is laterally etched through the holes or grooves to form lateral grooves. A first electrode and a second electrode are respectively formed in the lateral grooves of the two spaced holes or grooves. Since the first and second electrodes are formed in the lateral grooves, the width of the lateral grooves in the first direction is related to the thickness of the support layer. Therefore, the thickness of the first and second electrodes is related to the corresponding thickness of the support layer.

[0058] In other embodiments, the etching process for forming the holes or grooves is selected from dry etching or wet etching.

[0059] In other embodiments, the etching process for the side etching is dry etching or wet etching.

[0060] In other embodiments, the preparation method for forming the first electrode and the second electrode includes first depositing a continuous metal film layer to cover the surface of the stacked structure, the surface of the hole or groove, the exposed substrate of the hole or groove, and the inside of the lateral groove; through various anisotropic etching methods, retaining the metal film layer in the lateral groove to form the first electrode and the second electrode, and removing other metal film layers.

[0061] In other embodiments, the manufacturing process of depositing the metal film layer is selected from one or more of high-temperature furnace tube, chemical vapor deposition, physical vapor deposition or atomic layer deposition.

[0062] On the stacked structure, a gate hole is etched between the first electrode and the second electrode to ensure that the first electrode and the second electrode are exposed, and an active layer is formed between the first electrode and the second electrode in the gate hole; a gate structure is formed in the gate hole where the active layer is formed, and the gate structure includes an outer gate insulating layer and a gate electrode wrapped therein; the active layer corresponding to the first electrode and the second electrode and the portion overlapping with the gate structure is the channel region. Since the thickness of the first electrode and the second electrode is related to the thickness of the support layer, the thickness of the channel region is also related to the thickness of the support layer.

[0063] In other embodiments, the gate hole is formed before the first and second electrodes are formed, or in the same step as the hole or groove formed when the first and second electrodes are formed. After the gate hole is formed, it is filled with a filling material, which is then removed after the first and second electrodes are formed to allow for subsequent steps.

[0064] In other embodiments, the preparation of the active layer includes forming a continuous semiconductor material layer on the side wall of the gate hole to fill the gate hole. Optionally, the gate hole is filled after the gate structure is manufactured or filled with a filling material; removing the sacrificial layer in the stacked structure to expose the semiconductor material layer, and etching away the semiconductor material layer at a minimum portion corresponding to the sacrificial layer to form an active layer.

[0065] In other embodiments, the gate structure is prepared by first depositing a gate insulating layer, optionally one or more of oxide, nitride or oxynitride, and then making a gate in a gate hole deposited with the gate insulating layer, optionally one or more of metal, alloy, conductive compound or polysilicon.

[0066] In other embodiments, the present disclosure provides a semiconductor device as shown in FIG2 , wherein the semiconductor device 11 comprises: a substrate 1001; a first structural unit (101, 111) disposed on the substrate 1001, wherein the first structural unit 101 comprises: transistors (901, 911, 921, 931), wherein the plurality of transistors (901, 911, 921, 931) are stacked along a first direction D1; and taking the transistor 901 as an example, the semiconductor device 11 comprises: a gate structure 401, an active layer 501, a first electrode 201 and a second electrode 301, wherein the first electrode 201 and the second electrode 301 are disposed on both sides of the gate structure 401 along a second direction D2, wherein the active layer 501 is connected to the first electrode 201; An electrode 201 and a second electrode 301 are provided, and an active layer 501 includes a channel region 601, wherein the channel region 601 is located between the first electrode 201 and the second electrode 301. The gate structures of the plurality of transistors (901, 911, 921, 931) are connected along a first direction D1. The first direction D1 intersects with the plane of the substrate 1001, and the second direction D2 intersects with the first direction D1. The plurality of transistors (901, 911, 921, 931) include at least a first transistor and a second transistor, wherein the channel region width W of a transistor farther from the substrate along the first direction D1, such as the first transistor 931, is smaller than the channel region width W of the second transistor 901 closer to the substrate. The plurality of first structural units (101, 111) are stacked along the first direction, and the gate structures 401 of the plurality of first structural units are connected along the first direction D1. A third direction D3 intersects with the second direction D2.

[0067] The specific preparation method is as follows: first, a stacked structure is prepared on a substrate. The stacked structure is made by alternating deposition of two different material layers. The two material layers have a certain etching selectivity ratio, which is used for selective etching to form the required structure in the subsequent preparation process. One material layer is a support layer and the other material layer is a sacrificial layer. Optionally, silicon layers and silicon germanium layers are alternately deposited to form the stacked structure; alternatively, silicon nitride and silicon oxide are alternately deposited to form the stacked structure. By adjusting one or more of the deposition rate, deposition time, reaction temperature, or reaction gas flow rate of each layer, the thickness of the deposited layer is adjusted, so that the thickness of the support layer closer to the substrate is greater than the thickness of the support layer farther away from the substrate.

[0068] In other embodiments, the thickness of the support layer gradually decreases as the distance from the substrate increases.

[0069] In other embodiments, the thickness of the support layer decreases as a whole with increasing distance from the substrate, but the thickness of adjacent support layers can be equal, for example, the thickness of every few support layers is equal, and the thickness of the subsequently deposited support layers is also equal but less than the thickness of the previously deposited support layers.

[0070] In other embodiments, the sacrificial layers have the same thickness.

[0071] In other embodiments, the sacrificial layer has a thickness that decreases as it moves away from the substrate, similar to that of the support layer.

[0072] In other embodiments, the sacrificial layer has an opposite trend to that of the support layer, that is, the thickness of the sacrificial layer gradually increases as the distance from the substrate increases.

[0073] In other embodiments, the deposition method may be selected from one or more of high temperature furnace tube, chemical vapor deposition, physical vapor deposition or atomic layer deposition.

[0074] Two spaced holes or grooves are formed in the stacked structure obtained above through an etching process. The support layer is laterally etched through the holes or grooves to form lateral grooves. A first electrode and a second electrode are respectively formed in the lateral grooves of the two spaced holes or grooves. Since the first and second electrodes are formed in the lateral grooves, the width of the lateral grooves in the first direction is related to the thickness of the support layer. Therefore, the thickness of the first and second electrodes is related to the corresponding thickness of the support layer.

[0075] In other embodiments, the etching process for forming the holes or grooves is selected from dry etching or wet etching.

[0076] In other embodiments, the etching process for the side etching is dry etching or wet etching.

[0077] In other embodiments, the preparation method for forming the first electrode and the second electrode includes first depositing a continuous metal film layer to cover the surface of the stacked structure, the surface of the hole or groove, the exposed substrate of the hole or groove, and the inside of the lateral groove; through various anisotropic etching methods, retaining the metal film layer in the lateral groove to form the first electrode and the second electrode, and removing other metal film layers.

[0078] In other embodiments, the manufacturing process of depositing the metal film layer is selected from one or more of high-temperature furnace tube, chemical vapor deposition, physical vapor deposition or atomic layer deposition.

[0079] On the stacked structure, a gate hole is etched between the first electrode and the second electrode to ensure that the first electrode and the second electrode are exposed, and an active layer is formed between the first electrode and the second electrode in the gate hole; a gate structure is formed in the gate hole where the active layer is formed, and the gate structure includes an outer gate insulating layer and a gate electrode wrapped therein; the active layer corresponding to the first electrode and the second electrode and the portion overlapping with the gate structure is the channel region. Since the thickness of the first electrode and the second electrode is related to the thickness of the support layer, the thickness of the channel region is also related to the thickness of the support layer.

[0080] In other embodiments, the gate hole is formed before the first and second electrodes are formed, or in the same step as the hole or groove formed when the first and second electrodes are formed. After the gate hole is formed, it is filled with a filling material, which is then removed after the first and second electrodes are formed to allow for subsequent steps.

[0081] In other embodiments, the preparation of the active layer includes forming a continuous semiconductor material layer on the side wall of the gate hole to fill the gate hole. Optionally, the gate hole is filled after the gate structure is manufactured or filled with a filling material; removing the sacrificial layer in the stacked structure to expose the semiconductor material layer, and etching away the semiconductor material layer at a minimum portion corresponding to the sacrificial layer to form an active layer.

[0082] In other embodiments, the gate structure is prepared by first depositing a gate insulating layer, optionally one or more of oxide, nitride or oxynitride, and then making a gate in a gate hole deposited with the gate insulating layer, optionally one or more of metal, alloy, conductive compound or polysilicon.

[0083] In other embodiments, multiple first structural units are arranged from bottom to top, and each first structural unit is prepared separately by the aforementioned manufacturing process with similar manufacturing steps; the gate structures of the upper and lower adjacent first structural units are aligned and linked.

[0084] In other embodiments, multiple first structural units are arranged from bottom to top, and each first structural unit is prepared by the aforementioned manufacturing process. Each first structural unit first implements part of the manufacturing process, and finally the processes that can be integrated are prepared in the same step; optionally, holes or grooves are first made in the stacked structure and then filled with filling material, and then a group of stacked structures are made on the upper layer, and then holes or grooves are made at corresponding positions, and so on. After all the stacked structures with holes or grooves are made, at least one of the first electrode, second electrode, active layer or gate structure in different first structural units is prepared at the same time.

[0085] In some other embodiments, the transistors in two first structure units among the plurality of first structure units arranged from bottom to top do not have a relationship in which the width of the channel region of the transistor farther from the substrate is greater than the width of the channel region of the transistor closer to the substrate.

[0086] In some other embodiments, as shown in FIG3 , the semiconductor device 12 includes: a substrate 1002; a first structural unit (102, 112) disposed on the substrate 1002, the first structural unit (102, 112) including: transistors (902, 912, 922, 932, 942, 952, 962, 972), a plurality of transistors (902, 912, 922, 932, 942, 952, 962, 972) stacked along a first direction D1; taking the transistor (902, 942) as an example, the semiconductor device 12 includes: a gate structure (402, 412), an active layer (502, 512), a first electrode (202, 212) and a second electrode (302, 312), the first electrode and the second electrode being disposed on both sides of the gate structure along a second direction D2, The active layer connects the first electrode and the second electrode, and the active layer includes a channel region, and the channel region is located between the first electrode and the second electrode; the gate structures of the multiple transistors (902, 912, 922, 932) are connected along a first direction D1; the first direction D1 intersects with the plane where the substrate 1002 is located, and the second direction D2 intersects with the first direction D1; the multiple transistors (902, 912, 922, 932) include at least a first transistor and a second transistor, wherein the channel region width of the transistor far from the substrate along the first direction D1, such as the first transistor 902, is smaller than the channel region width W of the second transistor 932 close to the substrate, and similarly, the channel region width of the transistor 942 in the multiple transistors (942, 952, 962, 972) is smaller than the channel region width of the transistor 972. A plurality of first structural units (102, 112) are arranged on a substrate 1002 along a third direction D3, where the third direction D3 intersects with the second direction D2; second electrodes of transistors arranged in the same layer in the plurality of first structural units are connected to the same bit line (702, 712, 722, 732), where the bit line is arranged along the third direction.

[0087] The specific preparation method is as follows: first, a stacked structure is prepared on a substrate. The stacked structure is made by alternating deposition of two different material layers. The two material layers have a certain etching selectivity ratio, which is used for selective etching to form the required structure in the subsequent preparation process. One material layer is a support layer and the other material layer is a sacrificial layer. Optionally, silicon layers and silicon germanium layers are alternately deposited to form the stacked structure; alternatively, silicon nitride and silicon oxide are alternately deposited to form the stacked structure. By adjusting one or more of the deposition rate, deposition time, reaction temperature, or reaction gas flow rate of each layer, the thickness of the deposited layer is adjusted, so that the thickness of the support layer closer to the substrate is greater than the thickness of the support layer farther away from the substrate.

[0088] In other embodiments, the thickness of the support layer gradually decreases as the distance from the substrate increases.

[0089] In other embodiments, the thickness of the support layer decreases as a whole with increasing distance from the substrate, but the thickness of adjacent support layers can be equal, for example, the thickness of every few support layers is equal, and the thickness of the subsequently deposited support layers is also equal but less than the thickness of the previously deposited support layers.

[0090] In other embodiments, the sacrificial layers have the same thickness.

[0091] In other embodiments, the sacrificial layer has a thickness that decreases as it moves away from the substrate, similar to that of the support layer.

[0092] In other embodiments, the sacrificial layer has an opposite trend to that of the support layer, that is, the thickness of the sacrificial layer gradually increases as the distance from the substrate increases.

[0093] In other embodiments, the deposition method may be selected from one or more of high temperature furnace tube, chemical vapor deposition, physical vapor deposition or atomic layer deposition.

[0094] Two spaced holes or grooves are formed in the stacked structure obtained above through an etching process. The support layer is laterally etched through the holes or grooves to form lateral grooves. A first electrode and a second electrode are respectively formed in the lateral grooves of the two spaced holes or grooves. Since the first and second electrodes are formed in the lateral grooves, the width of the lateral grooves in the first direction is related to the thickness of the support layer. Therefore, the thickness of the first and second electrodes is related to the corresponding thickness of the support layer.

[0095] In other embodiments, the etching process for forming the holes or grooves is selected from dry etching or wet etching.

[0096] In other embodiments, the etching process for the side etching is dry etching or wet etching.

[0097] In other embodiments, the preparation method for forming the first electrode and the second electrode includes first depositing a continuous metal film layer to cover the surface of the stacked structure, the surface of the hole or groove, the exposed substrate of the hole or groove, and the inside of the lateral groove; through various anisotropic etching methods, retaining the metal film layer in the lateral groove to form the first electrode and the second electrode, and removing other metal film layers.

[0098] In other embodiments, the manufacturing process of depositing the metal film layer is selected from one or more of high-temperature furnace tube, chemical vapor deposition, physical vapor deposition or atomic layer deposition.

[0099] On the stacked structure, a gate hole is etched between the first electrode and the second electrode to ensure that the first electrode and the second electrode are exposed, and an active layer is formed between the first electrode and the second electrode in the gate hole; a gate structure is formed in the gate hole where the active layer is formed, and the gate structure includes an outer gate insulating layer and a gate electrode wrapped therein; the active layer corresponding to the first electrode and the second electrode and the portion overlapping with the gate structure is the channel region. Since the thickness of the first electrode and the second electrode is related to the thickness of the support layer, the thickness of the channel region is also related to the thickness of the support layer.

[0100] In other embodiments, the gate hole is formed before the first and second electrodes are formed, or in the same step as the hole or groove formed when the first and second electrodes are formed. After the gate hole is formed, it is filled with a filling material, which is then removed after the first and second electrodes are formed to allow for subsequent steps.

[0101] In other embodiments, the preparation of the active layer includes forming a continuous semiconductor material layer on the side wall of the gate hole to fill the gate hole. Optionally, the gate hole is filled after the gate structure is manufactured or filled with a filling material; removing the sacrificial layer in the stacked structure to expose the semiconductor material layer, and etching away the semiconductor material layer at a minimum portion corresponding to the sacrificial layer to form an active layer.

[0102] In other embodiments, the gate structure is prepared by first depositing a gate insulating layer, optionally one or more of oxide, nitride or oxynitride, and then making a gate in a gate hole deposited with the gate insulating layer, optionally one or more of metal, alloy, conductive compound or polysilicon.

[0103] In other embodiments, a plurality of first structural units are fabricated simultaneously, grooves are fabricated in the stacked structure, and the second electrode and the bit line are fabricated after side etching the support layer through the grooves.

[0104] In some other embodiments, the bit line and the corresponding second electrode are integrally formed.

[0105] In some other embodiments, the present disclosure provides a semiconductor device 13 as shown in FIG4 , comprising a first structural unit 103 arranged on a substrate 1003, the first structural unit comprising: transistors (903, 913, 923, 933), wherein the plurality of transistors (903, 913, 923, 933) are stacked along a first direction D1; taking the transistor (903) as an example, the semiconductor device 13 comprises: a gate structure (403), an active layer (503), a first electrode (203) and a second electrode (303), wherein the first electrode and the second electrode are arranged on both sides of the gate structure along a second direction D2, the active layer connects the first electrode and the second electrode, the active layer comprises a channel region, and the channel region is located between the first electrode and the second electrode; the gate structures of the plurality of transistors (903, 913, 923, 933) are connected along the first direction D1; the first direction D1 intersects with the plane where the substrate 1003 is located, and the second direction D2 intersects with the first direction D1; the plurality of crystals The transistor (903, 913, 923, 933) includes at least a first transistor and a second transistor, wherein the channel region width of the transistor farther from the substrate along the first direction D1, such as the first transistor 903, is smaller than the channel region width W of the second transistor 933 closer to the substrate; a capacitor structure (803, 813, 823, 833), wherein the plurality of capacitor structures (803, 813, 823, 833) are stacked along the first direction D1; the capacitor structure includes a first capacitor electrode 43, a second capacitor electrode 63, and a capacitor dielectric layer 53, wherein the capacitor dielectric layer is arranged between the first capacitor electrode and the second capacitor electrode; the plurality of capacitor structures (803, 813, 823, 833) and the plurality of transistors (903, 913, 923, 933) are correspondingly arranged in the second direction D2, the first capacitor electrode 43 of the capacitor structure is connected to the first electrode 203 of the corresponding transistor; and the second capacitor electrodes of the plurality of capacitor structures are connected along the first direction.

[0106] In other embodiments, the first capacitor electrode is arranged in a ring around the second capacitor electrode, and the width of the second capacitor electrode corresponding to the first transistor in the first direction is smaller than the width of the second capacitor electrode corresponding to the second transistor in the first direction. The specific preparation method is as follows: first, a stacked structure is prepared on a substrate, and the stacked structure is made by alternating deposition of two different material layers. The two material layers have a certain etching selectivity ratio, which is used for selective etching in the subsequent preparation process to form the required structure, wherein one material layer is a supporting layer and the other material layer is a sacrificial layer. Optionally, silicon layers and silicon germanium layers are alternately deposited to form a stacked structure; optionally, silicon nitride and silicon oxide are alternately deposited to form a stacked structure. By adjusting one or more of the factors such as the deposition rate of each layer, the deposition time, the reaction temperature, or the reaction gas flow rate, the thickness of the deposited layer is adjusted, and the thickness of the support layer deposited close to the substrate is greater than the thickness of the support layer away from the substrate.

[0107] In other embodiments, the thickness of the support layer gradually decreases as the distance from the substrate increases.

[0108] In other embodiments, the thickness of the support layer decreases as a whole with increasing distance from the substrate, but the thickness of adjacent support layers can be equal, for example, the thickness of every few support layers is equal, and the thickness of the subsequently deposited support layers is also equal but less than the thickness of the previously deposited support layers.

[0109] In other embodiments, the sacrificial layers have the same thickness.

[0110] In other embodiments, the sacrificial layer has a thickness that decreases as it moves away from the substrate, similar to that of the support layer.

[0111] In other embodiments, the sacrificial layer has an opposite trend to that of the support layer, that is, the thickness of the sacrificial layer gradually increases as the distance from the substrate increases.

[0112] In other embodiments, the deposition method may be selected from one or more of high temperature furnace tube, chemical vapor deposition, physical vapor deposition or atomic layer deposition.

[0113] Two spaced holes or grooves are formed in the stacked structure obtained above through an etching process. The support layer is laterally etched through the holes or grooves to form lateral grooves. A first electrode and a second electrode are respectively formed in the lateral grooves of the two spaced holes or grooves. Since the first and second electrodes are formed in the lateral grooves, the width of the lateral grooves in the first direction is related to the thickness of the support layer. Therefore, the thickness of the first and second electrodes is related to the corresponding thickness of the support layer.

[0114] In other embodiments, the etching process for forming the holes or grooves is selected from dry etching or wet etching.

[0115] In other embodiments, the etching process for the side etching is dry etching or wet etching.

[0116] In other embodiments, the preparation method for forming the first electrode and the second electrode includes first depositing a continuous metal film layer to cover the surface of the stacked structure, the surface of the hole or groove, the exposed substrate of the hole or groove, and the inside of the lateral groove; through various anisotropic etching methods, retaining the metal film layer in the lateral groove to form the first electrode and the second electrode, and removing other metal film layers.

[0117] In other embodiments, the manufacturing process of depositing the metal film layer is selected from one or more of high-temperature furnace tube, chemical vapor deposition, physical vapor deposition or atomic layer deposition.

[0118] On the stacked structure, a gate hole is etched between the first electrode and the second electrode to ensure that the first electrode and the second electrode are exposed, and an active layer is formed between the first electrode and the second electrode in the gate hole; a gate structure is formed in the gate hole where the active layer is formed, and the gate structure includes an outer gate insulating layer and a gate electrode wrapped therein; the active layer corresponding to the first electrode and the second electrode and the portion overlapping with the gate structure is the channel region. Since the thickness of the first electrode and the second electrode is related to the thickness of the support layer, the thickness of the channel region is also related to the thickness of the support layer.

[0119] In other embodiments, the gate hole is formed before the first and second electrodes are formed, or in the same step as the hole or groove formed when the first and second electrodes are formed. After the gate hole is formed, it is filled with a filling material, which is then removed after the first and second electrodes are formed to allow for subsequent steps.

[0120] In other embodiments, the preparation of the active layer includes forming a continuous semiconductor material layer on the side wall of the gate hole to fill the gate hole. Optionally, the gate hole is filled after the gate structure is manufactured or filled with a filling material; removing the sacrificial layer in the stacked structure to expose the semiconductor material layer, and etching away the semiconductor material layer at a minimum portion corresponding to the sacrificial layer to form an active layer.

[0121] In other embodiments, the gate structure is prepared by first depositing a gate insulating layer, optionally one or more of oxide, nitride or oxynitride, and then making a gate in a gate hole deposited with the gate insulating layer, optionally one or more of metal, alloy, conductive compound or polysilicon.

[0122] In other embodiments, a hole is made in the stacked structure, the supporting layer is laterally etched in the hole to form a lateral groove, and then the first electrode and the first capacitor electrode are made. Optionally, the first capacitor electrode is arranged in the lateral groove, so that the width of the first capacitor electrode in the first direction is related to the thickness of the supporting layer.

[0123] In other embodiments, the first electrode and the first capacitor electrode are integrally formed.

[0124] In other embodiments, the capacitor dielectric layers of the multiple capacitor structures arranged along the first direction are formed in the same preparation process, and the capacitor dielectric layers of the multiple capacitor structures may be continuous or independent of each other.

[0125] In some other embodiments, the second capacitor electrodes of the plurality of capacitor structures arranged along the first direction are formed in the same manufacturing process.

[0126] In some other embodiments, the material of the active layer is an oxide semiconductor material.

[0127] In some other embodiments, the material of the active layer is tin-doped indium gallium zinc metal oxide.

[0128] In other embodiments, the second electrode and / or the first electrode is selected from one or more of metal ruthenium, metal molybdenum, ruthenium oxide, or molybdenum oxide.

[0129] In other embodiments, the first capacitor electrode is selected from one or more of metal ruthenium, metal molybdenum, ruthenium oxide, or molybdenum oxide.

[0130] In other embodiments, the first capacitor electrode and the first electrode include metal ruthenium.

[0131] In other embodiments, the capacitor dielectric layer includes strontium titanium oxide.

[0132] In other embodiments, the present disclosure provides a dynamic random access memory 14 as shown in Figures 5 and 6, including: any of the aforementioned semiconductor devices, optionally including: a first structural unit (104, 114, 134, 144) arranged on a substrate 1004; the dynamic random access memory 14 also includes: a sub-word line driver SWD, the sub-word line driver is connected to the gate structure (404, 414, 434, 444); and a sensitive amplifier SA, the sensitive amplifier is connected to the second electrode.

[0133] In other embodiments, the sense amplifier SA is connected to the second electrode through a bit line ( 704 , 714 , 727 , 734 , 744 , 754 , 764 , 774 ).

[0134] In some other embodiments, the sub-word line driver SWD and the sense amplifier SA are disposed in different regions of the substrate 1004 .

[0135] In some other embodiments, after the sub-word line driver SWD and the sense amplifier SA are formed on the substrate, the first structure unit is manufactured on the same surface.

[0136] In some other embodiments, after forming the sub-wordline driver SWD and the sense amplifier SA on the substrate, a first structural unit is fabricated on the opposite surface. The sub-wordline driver SWD and the sense amplifier SA are connected to the first structural unit through through silicon vias (TSVs).

[0137] In other embodiments, the present disclosure provides a dynamic random access memory 15 as shown in FIG. 7 , wherein the sub-word line driver SWD is disposed on a control substrate 1015 , the sense amplifier SA is disposed on a substrate 1005 , and the control substrate is bonded to the substrate.

[0138] In some other embodiments, the sub-word line driver SWD is disposed on the substrate 1005 , and the sense amplifier SA is disposed on the control substrate 1015 , and the control substrate is bonded to the substrate.

[0139] In other embodiments, the sub-word line driver SWD and the sensitive amplifier SA are both arranged on the control substrate 1015, which is bonded to the substrate 1005 on which the first structural unit is arranged. The sub-word line driver SWD is connected to the gate structure of the first structural unit through a wiring, and the sensitive amplifier SA is connected to the second electrode through a wiring.

[0140] In some other embodiments, the bonding method between the control substrate and the substrate is hybrid bond.

[0141] Beneficial effects of the embodiments of the present disclosure:

[0142] By adjusting the thickness of the support layer in the stacked structure, a stacked transistor with a larger channel width in the lower layer and a smaller channel width in the upper layer can be obtained when manufacturing the stacked transistor. This can compensate for the effect of the tapered cross-section formed when etching the gate hole on the transistor properties, thereby achieving a more uniform semiconductor device.

[0143] Since the transistor is arranged at a position corresponding to the support layer, the sacrificial layer can compensate for the influence of the thickness variation of the support layer on the manufacturing process when the sacrificial layer has a trend opposite to that of the support layer, without affecting the channel width of the transistor.

[0144] The first capacitor electrode of the capacitor structure disposed within the hole is annular. This is also affected by the conical cross-section of the hole, resulting in the diameter of the first capacitor electrode of the upper capacitor structure being larger than the diameter of the first capacitor electrode of the lower capacitor structure. Therefore, the decrease in the width of the first capacitor electrode in the first direction as it moves away from the substrate can compensate for the increase in the diameter of the first capacitor electrode as it moves away from the substrate, thereby achieving a similar area between the upper and lower first capacitor electrodes, ultimately making the capacitance of the upper and lower capacitor structures similar. This results in a more uniform semiconductor device.

[0145] Oxide semiconductor materials are easier to prepare for the active layer.

[0146] The active layer is made of tin-doped indium gallium zinc metal oxide semiconductor with better performance.

[0147] The first electrode and the second electrode are selected from one or more of metal ruthenium, metal molybdenum, ruthenium oxide or molybdenum oxide. When the active layer selects an oxide semiconductor material, since ruthenium oxide or molybdenum oxide is an oxide, it will no longer be affected by the oxide semiconductor material. When metal ruthenium and metal molybdenum are affected by the oxygen in the oxide semiconductor material to form oxides, they are also conductors. Therefore, they will not be affected by the oxygen in the oxide semiconductor material to form oxides like other metals, resulting in increased resistance.

[0148] When metal ruthenium is selected as the first capacitor electrode and strontium titanium oxide is selected as the capacitor dielectric layer, since the lattice constant of metal ruthenium is close to that of strontium titanium oxide, metal ruthenium can be used as a seed layer to induce the deposition of strontium titanium oxide, which is beneficial to the process and device performance.

[0149] The sub-word line driver SWD and the sense amplifier SA are both arranged on the control substrate and then bonded to the substrate provided with the first structural unit. This design is easier to manufacture. The two different processes of the sub-word line driver SWD, the sense amplifier SA and the first structural unit do not affect each other, and a semiconductor device with better performance can be obtained.

[0150] Hybrid bonding can arrange bonding pads more densely to package control substrates and semiconductor devices with better performance.

[0151] Although the present disclosure has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein; and these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present disclosure.

Claims

1. A semiconductor device (10), characterized in that include: substrate (1000); A first structural unit (100) is provided on a substrate, the first structural unit comprising: Transistors (900, 910, 920, 930), a plurality of said transistors being stacked and arranged along a first direction (D1); The transistor comprises: a gate structure (400), an active layer (500), a first electrode (200) and a second electrode (300), wherein the first electrode and the second electrode are arranged on both sides of the gate structure along a second direction (D2), the active layer connects the first electrode and the second electrode, and the active layer comprises a channel region (600), wherein the channel region is located between the first electrode and the second electrode; The gate structures of the plurality of transistors are connected along the first direction; The first direction intersects with the plane where the substrate is located, and the second direction intersects with the first direction; The plurality of transistors include at least a first transistor and a second transistor, wherein a width of a channel region of the first transistor farther from the substrate along the first direction is smaller than a width of a channel region of the second transistor closer to the substrate.

2. The semiconductor device according to claim 1, wherein: The channel region widths of the plurality of transistors decrease as they are farther from the substrate along the first direction.

3. The semiconductor device according to claim 1, wherein: The semiconductor device includes a plurality of first structure units stacked along the first direction, and the gate structures of the plurality of first structure units are connected along the first direction.

4. The semiconductor device according to claim 1, wherein: The semiconductor device includes a plurality of the first structural units arranged along a third direction (D3), the third direction intersecting with the second direction; The second electrodes of the transistors arranged in the same layer in a plurality of the first structural units are connected to the same bit line (702, 712, 722, 732), and the bit line is arranged along a third direction.

5. The semiconductor device according to claim 1, wherein: The first structural unit further includes: Capacitor structures (803, 813, 823, 833), a plurality of the capacitor structures being stacked along the first direction; The capacitor structure comprises a first capacitor electrode (43), a second capacitor electrode (63), and a capacitor dielectric layer (53), wherein the capacitor dielectric layer is arranged between the first capacitor electrode and the second capacitor electrode; The plurality of capacitor structures and the plurality of transistors are arranged correspondingly in the second direction, and the first capacitor electrodes of the capacitor structures are connected to the first electrodes of the corresponding transistors; The second capacitor electrodes of the plurality of capacitor structures are connected along the first direction.

6. The semiconductor device according to claim 5, wherein: The first capacitor electrode is arranged in a ring shape around the second capacitor electrode, and the width of the second capacitor electrode corresponding to the first transistor in the first direction is smaller than the width of the second capacitor electrode corresponding to the second transistor in the first direction.

7. The semiconductor device according to any one of claims 1 to 6, characterized in that: The material of the active layer is tin-doped indium gallium zinc metal oxide.

8. The semiconductor device according to any one of claims 1 to 6, characterized in that: The second electrode and / or the first electrode are / is selected from one or more of metal ruthenium, metal molybdenum, ruthenium oxide or molybdenum oxide.

9. The semiconductor device according to claim 5 or 6, characterized in that: The first capacitor electrode is selected from one or more of metal ruthenium, metal molybdenum, ruthenium oxide or molybdenum oxide.

10. The semiconductor device according to claim 5 or 6, characterized in that: The first capacitor electrode and the first electrode are integrally formed.

11. The semiconductor device according to claim 10, wherein: The first capacitor electrode and the first electrode include metal ruthenium.

12. The semiconductor device according to claim 11, wherein: The capacitor dielectric layer includes strontium titanium oxide.

13. A dynamic random access memory (15), characterized in that: The dynamic random access memory comprises: a semiconductor device according to any one of claims 1-12; a sub-word line driver (SWD), the sub-word line driving connected to the gate structure; A sense amplifier (SA), wherein the sense amplifier is connected to the second electrode.

14. The dynamic random access memory according to claim 13, wherein: The sub-word line driver and / or the sense amplifier are disposed on the substrate.

15. The dynamic random access memory according to claim 13, wherein: The sub-word line driver and / or the sense amplifier are arranged on a control substrate (1015), and the control substrate is bonded to the substrate.

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