Demodulation circuit and server

Abstract

The present application relates to the field of data processing, and discloses a demodulation circuit and a server, for use in solving the problem of inaccurate pulse width measured by using an oscilloscope. An analysis circuit analyzes a high-level signal and a low-level signal in a first signal to obtain a corresponding first pulse width and a corresponding second pulse width, and a sampling control circuit controls a sampling timing to trigger a sampling circuit to sample the first pulse width and the second pulse width at the correct occasion, so as to realize analysis of hard disk data. According to the present application, circuit modules in the analysis circuit act together to realize accurate analysis of hard disk data; the response speed of a hardware circuit is high, so that the efficiency of analyzing the hard disk data can be improved; and according to the present application, a hard disk state pin for outputting a hard disk state signal is further used to output a first signal with the hard disk data, to acquire and analyze hard disk monitoring data without affecting the original function of the hard disk, so as to achieve monitoring of the hard disk.

Description

Demodulation circuit and server

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to a Chinese patent application filed with the Patent Office of China on March 29, 2024, with application number 202410382119.3 and application name “A Demodulation Circuit and Server,” the entire contents of which are incorporated herein by reference. Technical Field

[0003] The present application relates to the field of data processing, and in particular to a demodulation circuit and a server. Background Art

[0004] The hard disk is one of the most important storage devices in the computer. Therefore, the healthy operation of the hard disk is one of the key factors to ensure the reliability of the device server.

[0005] To ensure accurate control of the operating status of the hard drive, the device needs to monitor the hard drive during operation to obtain the hard drive status information. Currently, the main hard drive monitoring solutions are divided into in-band hard drive monitoring and out-of-band hard drive monitoring. In-band hard drive monitoring is to obtain the hard drive status information after the monitoring software running on the central processing unit (CPU) communicates data with the hard drive. This monitoring solution often has difficulty presenting the monitoring data to operation and maintenance personnel. Out-of-band hard drive monitoring is to monitor the hard drive status after obtaining the hard drive status information through the baseboard management controller (BMC). Pulse width is a form of data carried in data transmission. It is necessary to develop a method to demodulate the pulse width to realize data analysis. The current main method is to connect the pin that outputs the hard drive status information to an oscilloscope and measure the pulse width through the oscilloscope. However, the accuracy of this measurement method is low and the measurement process is slow.

[0006] Therefore, developing a hardware demodulation circuit for measuring pulse width to improve the accuracy of data analysis is a technical problem that needs to be solved urgently by those skilled in the art. Summary of the Invention

[0007] According to the embodiments disclosed in the present application, in a first aspect, the present application provides a demodulation circuit, including an analysis circuit, a sampling circuit and a sampling control circuit, the sampling circuit being connected to the analysis circuit and the sampling control circuit respectively; the analysis circuit is used to receive a first signal output by a hard disk status pin, and to analyze the high-level signal and the low-level signal in the first signal respectively to obtain a first pulse width corresponding to the high-level signal and a second pulse width corresponding to the low-level signal; the first signal includes hard disk data; and the sampling control circuit is used to trigger the sampling circuit to sample the first pulse width and the second pulse width according to the first signal, so as to analyze the hard disk data corresponding to the first signal according to the sampled first pulse width and second pulse width to realize monitoring of the hard disk.

[0008] According to the embodiment disclosed in the present application, in the second aspect, a server is also adopted, including a hard disk and a demodulation circuit as described above, and the demodulation circuit is connected to the hard disk; the demodulation circuit is used to receive a first signal output by a hard disk status pin of the hard disk, and demodulate the hard disk data according to the first signal to realize monitoring of the hard disk, and the first signal includes the hard disk data.

[0009] The details of one or more embodiments of the present application are set forth in the accompanying drawings and the description below. Other features and advantages of the present application will become apparent from the description, drawings, and claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following briefly introduces the prior art and the drawings required for use in the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0011] FIG1 is a schematic diagram of a system in which a demodulation circuit is provided according to one or more embodiments of the present application;

[0012] FIG2 is a schematic diagram of a demodulation circuit provided by one or more embodiments of the present application;

[0013] FIG3 is a partial schematic diagram of a detection circuit provided by one or more embodiments of the present application;

[0014] FIG4 is a schematic diagram of a trigger circuit provided by one or more embodiments of the present application;

[0015] FIG5 is a schematic diagram of a second integration circuit provided by one or more embodiments of the present application;

[0016] FIG6 is a schematic diagram of a third integration circuit provided by one or more embodiments of the present application;

[0017] FIG7 is a schematic diagram of a sampling control circuit and a delay circuit provided by one or more embodiments of the present application;

[0018] FIG8 is a schematic diagram of a logic circuit provided by one or more embodiments of the present application;

[0019] FIG9 is a schematic diagram of a driving circuit provided by one or more embodiments of the present application;

[0020] FIG10 is a timing diagram of various circuits provided in one or more embodiments of the present application. DETAILED DESCRIPTION

[0021] The core of this application is to provide a demodulation circuit and server, in which various circuit modules work together to achieve accurate analysis of hard disk data. Since the hardware circuit has a fast response speed, the efficiency of parsing hard disk data can be improved; this application also uses the hard disk status pin that outputs the hard disk status signal to output a first signal with hard disk data, thereby achieving the acquisition and analysis of hard disk monitoring data without affecting the original function of the hard disk, thereby realizing monitoring of the hard disk.

[0022] To make the purpose, technical solutions, and advantages of the embodiments of this application more clear, the technical solutions in the embodiments of this application will be clearly and completely described below in conjunction with the drawings in the embodiments of this application. Obviously, the described embodiments are part of the embodiments of this application, not all of the embodiments. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of this application.

[0023] To facilitate understanding, let's first introduce the aspects of out-of-band hard drive monitoring. Out-of-band management refers to managing the network through a dedicated network management channel, separating network management data from business data. This independent channel transmits only management data, separating network management data from business data. This improves network management efficiency and reliability, while also enhancing the security of network management data.

[0024] Because in-band monitoring cannot meet maintenance requirements, after server deployment, out-of-band management and monitoring capabilities are provided through a baseboard management controller (BMC). A BMC is a dedicated service processor that uses sensors to monitor the status of a computer, network server, or other hardware device and communicates with the device's system administrator via independent connections. In practice, the BMC is typically installed on the motherboard or main circuit board of the monitored device. The BMC uses sensors to measure internal physical variables such as temperature, humidity, power supply voltage, fan speed, communication parameters, and operating system (OS) functions. If any of these variables exceeds specified limits, the BMC notifies the system administrator. The BMC also provides web services, including network communication capabilities and a webpage displaying the monitoring interface. Maintenance personnel can access BMC monitoring data by connecting to the BMC of the monitored device via a network cable at the facility site or by connecting the BMCs of multiple monitored devices via a network in a data center.

[0025] Due to the limited performance and pin count of the BMC circuitry within a BMC system, as the number of components and items requiring monitoring increases, complex programmable logic devices (CPLDs) are often incorporated into BMC systems to offload performance pressure from the BMC circuitry and provide more pins for connecting sensors or monitored components. CPLDs primarily consist of three components: logic blocks, programmable interconnects, and input / output (I / O) blocks. A logic block in a CPLD typically includes 4 to 20 macrocells, each of which typically consists of a product term array, a product term allocation, and programmable registers. Each macrocell has multiple configurations and can be cascaded, enabling the implementation of complex combinational and sequential logic functions. CPLDs with higher integration densities often also include embedded array blocks with on-chip random access memory (RAM) / read-only memory (ROM). The programmable interconnects primarily provide the interconnect network between the logic blocks, macrocells, and I / O pins. Input / output blocks (I / O blocks) provide the interface between internal logic and the device's I / O pins.

[0026] As an important component of the server, the hard disk is an important target for out-of-band monitoring and management. According to the type of communication interface, it is mainly divided into Serial Attached SCSI (SAS) / Serial Advanced Technology Attachment (SATA) interface hard disks and Non-Volatile Memory Host Controller Interface Specification (NVMHCIS or NVM Express, NVMe) interface hard disks. Among them, the SAS interface is compatible with the SATA interface. According to the type of storage medium, hard disks are mainly divided into mechanical hard disks (HDD) and solid-state drives (SSD). Among them, mechanical hard disks mainly have SAS or SATA interfaces. Solid-state drives include SAS, SATA, and NVMe interface hard disks.

[0027] It should be noted that in some embodiments of the present application, the baseboard management controller may only include a baseboard management controller circuit, or it may be a system including a baseboard management controller circuit and a complex programmable logic device. The complex programmable logic device may be a complex programmable logic device only provided on the hard disk backplane or a complex programmable logic device provided on the server motherboard.

[0028] Furthermore, in this application, the hard disk selects the hard disk status pin to send data to the baseboard management controller because:

[0029] Hard drive pins are primarily categorized into three types: data pins, power pins, and hard drive status pins. The hard drive's data pins connect to the in-band system, while the hard drive's power pins are used to connect power and ground signals. Therefore, the baseboard management controller can only directly access the hard drive's status pins.

[0030] The hard disk status pins of the hard disk mainly include the hard disk status indication pin, the hard disk production debugging pin and the hard disk idle pin.

[0031] Among them, the hard disk status indication pins include the hard disk in-place status indication pin and the hard disk read / write status indication pin. The hard disk status indication pins are pins used by the hard disk to output hard disk status indication signals. For example, the hard disk in-place status indication pin is used to output the hard disk in-place status signal, and the hard disk read / write status indication pin is used to output the hard disk read / write status signal.

[0032] When a hard drive is connected to the hard drive backplane, the hard drive status indicator pins can be connected in two main ways: one to the baseboard management controller (BMC) to transmit the corresponding hard drive status data, and the other to the control circuit on the hard drive backplane to control the status of the corresponding controlled components, thereby informing the user of the corresponding hard drive status. For example, the hard drive backplane features a hard drive status indicator to indicate the hard drive's operating status. For example, when the hard drive is in the read / write state, the hard drive read / write status indicator pin can be controlled to output a square wave signal to the status indicator's amplification and drive circuit, causing the status indicator to illuminate. When the hard drive is not in the read / write state (idle state), the status indicator pin can be controlled to output a constant-level signal (e.g., a constant high-level signal) to turn off the status indicator, indicating the hard drive is in the idle state. The user can observe the on / off status indicator to determine whether the hard drive is in the read / write state. The same principle applies to the hard drive status display based on the hard drive presence status indicator pin. Alternatively, the hard drive can also output two different constant-level signals (one high, one low) through these hard drive status indicator pins to indicate different states. These signals can be input to the BMC to trigger corresponding recording, processing, or control.

[0033] The production debug pins of hard drives are mainly the pins (debug pins) next to the SAS or SATA interface of hard drives. These pins are usually used during the production debug phase of the hard drive. In actual use of the hard drive, the production debug pins can be used to output boot information during the hard drive initialization phase.

[0034] On the NVMe interface hard drive, in addition to the above-mentioned hard drive status indication pin, there is also a hard drive idle pin.

[0035] The above-mentioned hard disk status pins are not the pins used by the hard disk to output data, and there is no risk of leaking user data stored in the hard disk. Currently, after the hard disk is inserted into the hard disk backplane, these hard disk status pins are directly connected to the baseboard management controller or have the authority to connect to the baseboard management controller.

[0036] In an embodiment of the present application, the hard disk status pin of the hard disk may include at least one of a hard disk status indication pin, a hard disk production debugging pin, and a hard disk idle pin.

[0037] In an embodiment of the present application, if hard disk status indication pins such as a hard disk in-place status indication pin and a hard disk read / write status indication pin are used, since these hard disk status pins are usually already connected to the general-purpose input / output (GPIO) pins of the baseboard management controller circuit in the baseboard management controller or the input / output (I / O) pins of the complex programmable logic device, this hardware architecture can be directly adopted without making changes to the hardware architecture of the server, which is simple and convenient to implement.

[0038] Currently, the hard drive production debug pins on devices are usually left floating, typically consisting of four pins. If the embodiments of the present application use the hard drive production debug pins as the hard drive status pins for outputting hard drive log data, a connector with a corresponding number of pins can be used to connect the hard drive production debug pins to the GPIO pins of the baseboard management controller circuit or the I / O pins of a complex programmable logic device.

[0039] Since the hard disk idle pin is usually only available in the interface of NVMe interface hard disks, high-speed signals cannot be left floating. Currently, the hard disk idle pin in the NVMe interface is grounded through the resistor and capacitor circuit on the hard disk backplane after the hard disk is connected to the hard disk backplane. If the embodiment of the present application uses the hard disk idle pin as the hard disk status pin for the hard disk to output hard disk log data, the connection relationship between the hard disk idle pin and the hard disk backplane is changed to a GPIO pin connected to the baseboard management controller circuit or an I / O pin of a complex programmable logic device.

[0040] In an out-of-band system, if the hard drive expansion card has an integrated circuit bus connected to the baseboard management controller circuit, the baseboard management controller circuit can access the hard drive expansion card via the integrated circuit bus and forward commands or hard drive log data to the hard drive through the hard drive expansion card. Furthermore, within the baseboard management controller, the baseboard management controller circuit can also connect to a complex programmable logic device (CPLD) via the IC bus, and then connect to the hard drive status pin of the hard drive through the CPLD. Alternatively, the baseboard management controller circuit can directly connect to the hard drive status pin of the hard drive.

[0041] As shown in Figure 1, in order to directly obtain the hard disk log data through the hard disk status pin without occupying other pins, a demodulation circuit is required to parse the first signal output by the hard disk through the hard disk status pin; the hard disk data obtained by parsing is transmitted to the hard disk monitoring service module. After receiving the hard disk data, the hard disk monitoring service module sends an interrupt signal to the baseboard management controller and responds to the data read request sent by the baseboard management controller to feed back the hard disk data to the baseboard management controller.

[0042] In the first aspect, as shown in Figure 2, the present application provides a demodulation circuit, including an analysis circuit 11, a sampling circuit 12 and a sampling control circuit 15, and the sampling circuit 12 is connected to the analysis circuit 11 and the sampling control circuit 15 respectively; the analysis circuit 11 is used to receive a first signal output by the hard disk status pin, and to analyze the high-level signal and the low-level signal in the first signal respectively to obtain a first pulse width corresponding to the high-level signal and a second pulse width corresponding to the low-level signal; the first signal includes hard disk data; and the sampling control circuit 15 is used to trigger the sampling circuit 12 to sample the first pulse width and the second pulse width according to the first signal, so as to parse the hard disk data in the first signal according to the sampled first pulse width and second pulse width to realize monitoring of the hard disk.

[0043] The demodulation circuit in this embodiment includes an analysis circuit 11, a sampling circuit 12 and a sampling control circuit 15. Among them, the analysis circuit 11 is used to receive the first signal output by the hard disk status pin and analyze the first signal. Specifically, the high-level signal and the low-level signal are analyzed respectively to obtain a first pulse width corresponding to the high-level signal and a second pulse width of the low-level signal. The first signal includes hard disk data, and this hard disk data is used to achieve monitoring. In certain embodiments of the present application, this first signal can be a signal modulated by the hard disk according to the hard disk log data and the hard disk status signal corresponding to the hard disk status pin, that is, the hard disk status signal and the hard disk log data can be transmitted simultaneously through the hard disk status pin.

[0044] The sampling control circuit 15 controls when the sampling circuit 12 samples the first pulse width and the second pulse width. Specifically, the sampling control circuit 15 triggers the sampling circuit 12 according to the first signal to ensure that sampling is performed at the appropriate time, thereby facilitating the parsing of hard disk data based on the sampled first pulse width and the second pulse width.

[0045] The sampling circuit 12 receives the first pulse width and the second pulse width output by the analysis circuit 11 and samples the first pulse width and the second pulse width according to the timing triggered by the sampling control circuit 15. When the first pulse width and the second pulse width are analog signals, the sampling circuit 12 can be implemented as an analog-to-digital converter.

[0046] The demodulation circuit in the present application can be set as a separate circuit module, which is directly connected to the hard disk status pin of the hard disk to achieve direct acquisition and analysis of the hard disk log data.

[0047] In summary, the demodulation circuit of this embodiment achieves accurate analysis of hard disk data through the coordinated action of analysis circuit 11, sampling circuit 12, and sampling control circuit 15. Furthermore, this demodulation circuit utilizes the first signal output by the hard disk status pin to acquire and analyze hard disk data, thereby enabling hard disk monitoring. Furthermore, the hardware circuit has a relatively high processing speed, which improves the efficiency of hard disk data analysis.

[0048] In certain embodiments of the present application, the analysis circuit 11 includes a charging circuit and a discharging circuit, and the demodulation circuit further includes a loop control circuit 13, the charging circuit is respectively connected to the sampling control circuit 15, the loop control circuit 13 and the discharging circuit; the charging circuit is used to charge according to the preset level signal in the first signal when it is turned on to obtain the i-th pulse width; the discharging circuit is used to discharge according to the non-preset level signal in the first signal when it is turned on; the sampling control circuit 15 is specifically used to delay the first time to trigger the sampling circuit 12 to sample the i-th pulse width after the charging circuit is charged; the loop control circuit 13 is used to control the charging circuit to be turned on according to the first signal, and after the sampling control circuit 15 triggers the sampling circuit 12 to sample the i-th pulse width, delay the second time to control the discharge circuit to be turned on; wherein, when the preset level signal is a high level signal, i is one, and when the preset level signal is a low level signal, i is two.

[0049] This embodiment describes the specific components of the analysis circuit 11, which includes a charging circuit and a discharging circuit. The charging circuit charges according to a preset level signal in the first signal to obtain the i-th pulse width; the discharging circuit discharges according to a non-preset level signal in the first signal. The circuit control circuit 13 controls the timing of the charging and discharging circuits based on the first signal.

[0050] Specifically, when the preset level signal is a high level signal, the charging circuit charges according to the high level signal. After charging is completed, if the signal is converted to a low level signal, under the control of the sampling control circuit 15, the sampling circuit 12 samples the first pulse width corresponding to the high level signal obtained by the charging circuit after a first time. Under the control of the circuit control circuit 13, the discharge circuit is turned on for a second time after the sampling circuit 12 samples the first pulse width corresponding to the high level signal obtained by the charging circuit, thereby achieving discharge. More specifically, when the preset level signal is a high level signal, the circuit control circuit 13 may detect a rising edge of the first signal, indicating a high level signal, and control the charging circuit to be turned on, thereby charging according to the high level signal and obtaining the first pulse width corresponding to the high level signal. When the circuit control circuit 13 detects a falling edge of the first signal, indicating the end of the high level signal and the completion of charging of the charging circuit, the sampling circuit 12 is triggered to sample the first pulse width. After the sampling circuit 12 is triggered to sample, the discharge circuit is controlled to be turned on for a first time, thereby achieving discharge.

[0051] Similarly, when the preset level signal is a low-level signal, the charging circuit charges according to the low-level signal. After charging is completed, if it is converted to a high-level signal, then under the action of the sampling control circuit 15, the sampling circuit 12 samples the second pulse width corresponding to the low-level signal obtained by the charging circuit after the first time. Under the action of the circuit control circuit 13, the discharge circuit is turned on for a first time after triggering the sampling circuit 121 to sample the second pulse width, so as to achieve discharge. More specifically, when the preset level signal is a low level signal, the loop control circuit 13 receives the first signal through the first inverter 16. When the rising edge of the output of the first inverter 16 is detected, it means that the high level signal output by the first inverter 16 is detected, which also means that the first signal is a low level signal. The charging circuit is turned on, and the charging circuit is charged using the high level signal output by the first inverter 16 to obtain the second pulse width corresponding to the low level signal corresponding to the first signal; when the falling edge of the output of the first inverter 16 is detected, it means that the low level signal output by the first inverter 16 is detected, which also means that the first signal is a high level signal. The charging circuit is fully charged, and the sampling circuit 12 is triggered to sample the second pulse width. After the sampling circuit 12 is triggered to sample, the second time is delayed to control the discharge circuit to be turned on, and the discharge circuit discharges using the low level signal output by the first inverter 16.

[0052] The purpose of delaying the first time sampling circuit 12 after charging is complete is to ensure that the charging circuit is stable after charging is complete, thereby ensuring the accuracy and stability of data sampling. Specifically, the delayed triggering of sampling circuit 12 allows sampling to be performed when the signal is stable after charging is complete, avoiding data distortion caused by sampling during fluctuating or unstable signals. This allows accurate acquisition of data on the first and second pulse widths, and thus accurate analysis of hard disk data.

[0053] Among them, after triggering the sampling circuit 12 to perform sampling, the function of delaying the second time to control the conduction of the discharge circuit is to give the sampling circuit 12 sufficient sampling time to prevent the parameters corresponding to the charging circuit (such as the voltage value) from being in an unstable state during the sampling process, that is, to ensure the stability of the output end of the charging circuit and prevent the sampling process from being interrupted. Therefore, after the second time, the discharge circuit is controlled to be turned on to ensure that the sampling circuit 12 can effectively sample the first pulse width or the second pulse width, and then accurately analyze the hard disk data in the first signal, thereby realizing accurate monitoring of the hard disk, which can improve the performance and stability of the demodulation circuit.

[0054] In certain embodiments of the present application, the first signal is a signal obtained by modulating the hard disk according to the hard disk log data and the hard disk status signal corresponding to the hard disk status pin, and the hard disk status pin continuously outputs a first control signal of a first level when the hard disk is in a preset state, and outputs a second control signal when the hard disk is in a non-preset state, and the second control signal is a rectangular wave signal; in the preset state, the hard disk inserts a plurality of second-level pulse signals into the first control signal, and uses the pulse signal to divide the first control signal to obtain the first signal; in the non-preset state, the hard disk encodes each data bit in the hard disk log data into a level signal of a preset width corresponding to each data bit to obtain the first signal; and the demodulation circuit also includes: a detection circuit 14, the detection circuit 14 is connected to the loop control circuit 13; the detection circuit 14 is used to detect whether there is a pulse signal in the first signal, and adjust the first time and / or the second time according to the detection result.

[0055] Specifically, when the hard disk status pin is a status indicator pin, and the status indicator pin continuously outputs a first control signal of a first level when the hard disk is in a preset state, and outputs a second control signal to flash the status indicator when the hard disk is in a non-preset state, the hard disk modulates the hard disk status signal and the hard disk log signal to obtain the first signal in the following manner: when the hard disk is in a preset state, by inserting a plurality of second-level pulse signals into the first control signal, the first control signal can be divided by the pulse signal to obtain a plurality of first-level pulse width signals, thereby obtaining the first signal, wherein the hard disk log data includes a plurality of data bits, and each data bit corresponds to a first-level pulse width signal, and the parsing circuit 11 identifies the pulse width of the first-level pulse width signal to determine the corresponding data bit, thereby realizing the parsing of the hard disk log data.

[0056] Based on this modulated signal, the demodulation circuit is further provided with a detection circuit 14, which is connected to the sampling control circuit 15 and the loop control circuit 13, respectively. The function of the detection circuit 14 is to detect whether a pulse signal is present in the first signal and adjust the delay times corresponding to the sampling control circuit 15 and the loop control circuit 13 based on the detection result. In other words, the detection circuit 14 is primarily used to control the loop control circuit 13 to control the conduction of the discharge circuit at different timings based on the encoding method of the first signal currently output by the hard disk status pin.

[0057] Specifically, in the preset state, the width of the pulse signal is relatively narrow, so that the sampling control circuit 15 selects a smaller time delay to trigger the sampling circuit 12 for sampling, and the loop control circuit 13 also delays a smaller time to control the discharge loop to conduct, thereby being able to respond to changes in the pulse signal more quickly and complete the processing of the pulse signal as quickly as possible. This can improve the system's sensitivity and real-time performance to the pulse signal, and is conducive to accurately analyzing and interpreting the information carried by the pulse signal. In the non-preset state, when there is no pulse signal, the sampling control circuit 15 selects a smaller time delay to trigger the sampling circuit 12 for sampling, and the loop control circuit 13 also delays a smaller time to control the discharge loop to conduct, in order to stabilize the operation of the system and ensure normal data processing flow. Because when no pulse signal is detected, the first signal is a level signal with a larger width relative to the pulse signal. At this time, a longer delay is required to process the normal data flow to prevent premature interruption or interference with data processing. Therefore, selecting a larger time delay can ensure that the system can maintain a stable working state when no pulse signal is detected, avoid unnecessary interference or malfunction, maintain smooth data processing, and improve the stability and reliability of the system.

[0058] In addition, the preset state can also be the hard disk in-place state or out-of-place state, and this method can also be used when the first level signal is continuously output in the preset state, and the implementation method is the same, which is not repeated in this application.

[0059] In summary, in this embodiment, the sampling control circuit 15 and the loop control circuit 13 control the conduction of the charging circuit and the discharging circuit according to the signal of the detection circuit 14. After the charging circuit is charged, the sampling control circuit 15 selects a smaller time delay to trigger the sampling circuit 12 for sampling, and the loop control circuit 13 selects a corresponding delay time to control the conduction of the discharging circuit. In this way, the working state of the demodulation circuit can be controlled according to the information in the first signal, thereby realizing the monitoring of the hard disk status and the reliability of the hard disk data analysis.

[0060] The hard disk modulates the hard disk status signal and the hard disk log signal to obtain the first signal in the following specific manner: when the hard disk is in a non-preset state, each data bit in the hard disk log data will be encoded into a level signal of a preset width corresponding to each data bit, that is, different information in the hard disk log data is represented by different level signals, thereby obtaining the first signal. Specifically, there are two ways to encode each data bit into a level signal of a preset width: one is to encode each data bit into a pulse width signal corresponding to a duty cycle, that is, each data bit corresponds to the same period, and different data bits correspond to different duty cycles. The parsing circuit 11 can identify the current data bit by determining the duty cycle of each period, thereby implementing the parsing of the hard disk log data; the other is to encode each data bit into a level signal of a preset width, and when the level signals of two adjacent data bits are opposite or the level signals of two adjacent data bits are the same, an opposite level signal of a certain width is inserted between the two adjacent data bits to achieve a spacing between the two data bits. For example, the first data bit is encoded as a high level of a first width, the second data bit is encoded as a low level of a second width, and so on; or the first data bit is encoded as a first width, and the second data bit is encoded as a second width, and both high and low levels are acceptable, and an opposite level is inserted between the two data bits to achieve a spacing; then, by identifying the pulse width of each level, the parsing circuit 11 can determine the corresponding data bit, thereby implementing the parsing of the hard disk log data and further implementing the monitoring of the hard disk.

[0061] In certain embodiments of the present application, the detection circuit 14 is specifically configured to control the sampling control circuit 15 to operate in the first mode when it is determined that a pulse signal exists in the first signal, and to control the sampling control circuit 15 to operate in the second mode when it is determined that no pulse signal exists in the first signal; the sampling control circuit 15 is specifically configured to, after the charging circuit is charged, in response to operating in the first mode, delay a first preset time to trigger the sampling circuit 12 to sample the i-th pulse width, and in response to operating in the second mode, delay a second preset time to trigger the sampling circuit 12 to sample the i-th pulse width, wherein the first preset time is less than the second preset time, and the first time is the first preset time or the second preset time.

[0062] This embodiment adjusts the working mode of the sampling control circuit 15 through the detection result of the detection circuit 14, thereby achieving adjustment of the first time. Specifically, when there is a pulse signal, a smaller first preset time delay is selected to trigger the sampling circuit 12 because the pulse width of the pulse signal is small, so it needs to be sampled and processed as soon as possible to ensure timely acquisition of key information. The smaller delay (first preset time) can ensure that sampling can be triggered quickly after the pulse signal appears, reducing information loss or delay. This embodiment selects a larger second preset time delay to trigger the sampling circuit 12 when there is no pulse signal because the width of each level in the first signal is larger than the width of the pulse signal. Therefore, a larger delay can be selected to reduce the system's demand for resources, save energy and reduce unnecessary data sampling; in addition, through a larger delay, sampling can be performed when the signal is stable, avoiding resource waste and system burden caused by frequent sampling.

[0063] In summary, this embodiment selects different delay strategies to trigger the sampling circuit 12 according to the presence or absence of the pulse signal and the timeliness and accuracy requirements for data sampling, which can better balance system resource utilization, real-time performance and data sampling effectiveness.

[0064] In certain embodiments of the present application, the detection circuit 14 is specifically configured to control the loop control circuit 13 to operate in the third mode when determining that a pulse signal exists in the first signal, and to control the loop control circuit 13 to operate in the fourth mode when determining that a pulse signal does not exist in the first signal;

[0065] The loop control circuit 13 is specifically configured to, after the sampling control circuit triggers the sampling circuit to sample the i-th pulse width, delay the discharge circuit for a third preset time in response to operating in the third mode, and delay the discharge circuit for a fourth preset time in response to operating in the fourth mode, wherein the third preset time is less than the fourth preset time, and the second time is either the third preset time or the fourth preset time. This embodiment adjusts the operating mode of the loop control circuit 13 based on the detection result of the detection circuit 14, thereby adjusting the second time. Specifically, when a pulse signal is present, a smaller third preset time delay is selected to control the discharge circuit conduction because the pulse signal has a smaller pulse width and needs to be processed as quickly as possible to ensure efficient and timely analysis of hard disk data. A smaller delay (the third preset time) ensures rapid discharge after the pulse signal appears, thereby improving data processing efficiency. In this embodiment, when there is no pulse signal, a larger fourth preset time is selected to control the discharge circuit to be turned on because the width of each level in the first signal is larger than the width of the pulse signal. Therefore, a larger delay can be selected to reduce the system's demand for resources, save energy consumption and reduce unnecessary data sampling; in addition, a larger delay can ensure that the sampling circuit 12 performs sampling when the signal is stable, avoiding inaccurate sampling.

[0066] In this embodiment, the loop control circuit 13 and the sampling control circuit 15 are combined to jointly implement the sampling control circuit 15 delaying the third time to trigger the sampling circuit 12, and the loop control circuit 13 delaying the first preset time on the basis of the third time (that is, the loop control circuit 13 delays the first time) to control the discharge loop to be turned on; or to jointly implement the sampling control circuit 15 delaying the fourth time to trigger the sampling circuit 12, and the loop control circuit 13 delaying the second preset time on the basis of the fourth time (that is, the loop control circuit 13 delays the second time) to control the discharge loop to be turned on.

[0067] In this embodiment, the loop control circuit 13 is arranged after the sampling control circuit 15 in order to enable the loop control circuit 13 to perform corresponding delay control according to the output signal of the sampling control circuit 15, giving the sampling circuit 12 a sampling time to ensure that the discharge circuit is correctly turned on after the sampling is completed.

[0068] Furthermore, if in a preset state, the hard disk status signal is a constant level signal; the hard disk is modulated according to the hard disk log data and the hard disk status signal, and the process of obtaining the first signal includes: encoding each data bit into a pulse signal with a certain voltage amplitude, the first signal includes multiple pulse signals corresponding to multiple data bits one by one, and there is a preset time interval between two adjacent pulse signals, the hard disk log data includes multiple data bits, and each data bit and the voltage amplitude are in a preset mapping relationship, and the level of the constant level signal is opposite to the level of the pulse signal.

[0069] The first signal, which is composed of multiple pulse signals and constant level signals, is theoretically still a pulse width signal and can still indicate whether the hard disk is currently in the preset state. The hard disk status pin and pulse amplitude modulation are used to encode the hard disk log data and hard disk status signal.

[0070] At this time, the demodulation circuit determines the data bit corresponding to each pulse signal by analyzing the voltage amplitude corresponding to each pulse signal, thereby realizing the analysis of the hard disk log data; if the demodulation module is implemented as a circuit, the demodulation module may include a detection circuit and a voltage measurement circuit; the detection circuit is used to detect whether there is a pulse signal, and if so, the voltage amplitude of the pulse signal is measured using the voltage measurement circuit.

[0071] As shown in Figure 2, in certain embodiments of the present application, the detection circuit 14 includes a first integration circuit 141, a comparison circuit 142 and a trigger circuit 143 connected in sequence, and the trigger circuit 143 is respectively connected to the sampling control circuit 15 and the loop control circuit 13; the first integration circuit 141 is used to integrate the signal of the second level in the first signal to obtain a first integral value; the comparison circuit 142 is used to compare the first integral value with the first preset integral value and the second preset integral value, respectively, and if the first integral value is greater than the first preset integral value, output a first trigger signal; if the first integral value is greater than the second preset integral value, output a second trigger signal, and the first preset integral value is less than the second preset integral value; the trigger circuit 143 is used to adjust the first time and / or the second time according to the first trigger signal or the second trigger signal.

[0072] As shown in FIG3 , in certain embodiments of the present application, the first integration circuit 141 includes a third amplifier U13B, a fifth capacitor C5, and a thirteenth resistor R13; the comparison circuit 142 includes a third comparator U14A, a fourth comparator U14B, a first reference circuit, and a second reference circuit; the trigger circuit 143 includes a trigger; the first end of the thirteenth resistor R13 is connected to the hard disk status pin through the first inverter 16, the second end of the thirteenth resistor R13 is connected to the input positive terminal of the third amplifier U13B and the first end of the fifth capacitor C5, the second end of the fifth capacitor C5 is grounded, and the third amplifier U13B is connected to the first end of the fifth capacitor C5. The negative input terminal of 13B is respectively connected to the output terminal of the third amplifier U13B, the negative input terminal of the third comparator U14A and the negative input terminal of the fourth comparator U14B, the positive input terminal of the third comparator U14A is connected to the first reference circuit, the positive input terminal of the fourth comparator U14B is connected to the second reference circuit, the output terminal of the third comparator U14A is connected to the first input terminal of the trigger, the output terminal of the fourth comparator U14B is connected to the second input terminal of the trigger, the output terminal of the trigger is the output terminal of the detection circuit 14, and the first reference voltage output by the first reference circuit is less than the second reference voltage output by the second reference circuit.

[0073] Specifically, please refer to Figure 3. In Figure 3, the output end of the first integration circuit 141 is the output end of the third amplifier U13B. If the second level is a low level, the first integration circuit 141 integrates the pulse signal of the second level by: first, using the first inverter 16 to flip the level of the first signal. At this time, the level corresponding to the pulse signal is a high level, and the signal waveform output by the third amplifier U13B is a triangular wave obtained by integrating the high-level signal output by the first inverter 16.

[0074] The first reference circuit in comparator circuit 142 is a first voltage divider circuit formed by R15 and R16, and the second reference circuit is a second voltage divider circuit formed by R17 and R18. The first reference circuit provides a first reference voltage that is lower than the second reference voltage provided by the second reference circuit. If a pulse signal is present, the peak voltage of the triangular wave output by U13B should be lower. If a pulse signal is absent, the peak voltage of the triangular wave output by U13B should be higher. The triangular wave is compared with the first and second reference voltages. If the peak voltage is greater than the first reference voltage, a pulse signal is determined to be present. If the peak voltage is greater than the second reference voltage, a pulse signal is determined to be absent, indicating a normal level signal encoded with a preset width.

[0075] The trigger circuit 143 may be a JK trigger, as shown in FIG4 . The J terminal of the JK trigger is connected to the output terminal of the third comparator U14A, the K terminal of the JK trigger is connected to the output terminal of the fourth comparator U14B, and the CLK terminal of the JK trigger (not shown in FIG4 ) is connected to the output terminal of the first inverter 16 (the output terminal of the first inverter 16 may also be connected to the CLK terminal via R19 to improve the reliability of the reverse first signal input to the JK trigger), for inputting the reverse first signal. The Q terminal of the JK trigger is the output terminal of the detection circuit 14. The truth table of the JK trigger is shown in Table 1:

[0076] Table 1

[0077] In the detection circuit 14, the parameter design satisfies: R16×C5=t2 / 5;

[0078] Where E is the output upper limit of the amplifier, is the voltage value at the connection point of R14 and R15, te is the duration of the pulse signal, t1 is the shortest pulse width when there is no pulse signal, is the voltage value at the connection point of R17 and R18.

[0079] Furthermore, a buffer circuit U13A may be provided between the first end of the thirteenth resistor R13 and the output end of the first inverter 16 for buffering the reverse first signal to ensure the reliability of the back-end detection circuit 14 operating based on the reverse first signal.

[0080] In certain embodiments of the present application, the loop control circuit 13 includes a delay circuit 131 and a logic circuit 132;

[0081] The output end of the delay circuit 131 is connected to the first input end of the logic circuit 132, the control end of the delay circuit 131 is connected to the detection circuit 14, the second input end of the logic circuit 132 is connected to the hard disk status pin, and the output end of the logic circuit 132 is connected to the charging circuit and the discharging circuit respectively;

[0082] The delay circuit 131 is used to delay the first signal by a second time and output it;

[0083] The logic circuit 132 is configured to perform a logic operation based on the first signal output by the delay circuit 131 and the first signal output by the hard disk status pin, so as to output a first on-state signal when a starting edge of a preset level signal of the first signal output by the hard disk status pin is detected, and output a second on-state signal when an ending edge of the preset level signal of the first signal output by the delay circuit 131 is detected.

[0084] a charging circuit, specifically configured to be turned on upon receiving a first conduction signal, so as to charge according to a preset level signal to obtain an i-th pulse width;

[0085] The discharge circuit is specifically configured to be turned on when receiving a second conduction signal, so as to discharge according to a non-preset level signal.

[0086] In this embodiment, the loop control circuit 13 includes two parts: a delay circuit 131 and a logic circuit 132. The function of the delay circuit 131 in this demodulation circuit is to delay the first signal for a first time before outputting it. Specifically, upon receiving the first signal output by the hard disk status pin, the delay circuit 131 delays the signal output by the first time. The logic circuit 132 is used to perform logical operations based on the first signal output by the delay circuit 131 and the first signal output by the hard disk status pin. Specifically, the logic circuit 132 has two input terminals, one connected to the output terminal of the delay circuit 131 and the other connected to the hard disk status pin. It also has two output terminals, one connected to the charging circuit and the other connected to the discharging circuit. When the logic circuit 132 detects the starting edge of the preset level signal of the first signal output by the hard disk status pin and outputs a first conduction signal, it turns on the charging circuit to charge according to the preset level signal, thereby obtaining a specific pulse width, namely the i-th pulse width. When the logic circuit 132 detects the ending edge of the preset level signal of the first signal output by the delay circuit 131 , the discharge loop is turned on to perform a discharge operation according to the non-preset level signal.

[0087] Since the delay circuit 131 serves to delay the output of the first signal for the first time, the delay circuit 131 is combined with the roadbed circuit in this embodiment, so that when the edge (rising edge or falling edge) of the level begins, the charging circuit is triggered to charge accordingly, and when the edge (falling edge or rising edge) of the level ends, the discharge circuit is triggered to discharge accordingly after the first time.

[0088] In summary, this embodiment describes the collaborative working mode of the delay circuit 131 and the logic circuit 132 in the loop control circuit 13, which controls the conduction of the charging circuit and the discharging circuit through logical judgment and delay operation to realize the processing and analysis of the hard disk status signal.

[0089] In certain embodiments of the present application, the charging circuit includes a first charging circuit and a second charging circuit, and the discharging circuit includes a first discharging circuit and a second discharging circuit; the first output end of the logic circuit 132 is respectively connected to the control end of the first charging circuit and the control end of the first discharging circuit, the hard disk status pin is respectively connected to the input end of the first charging circuit, the input end of the first discharging circuit, the input end of the second charging circuit and the input end of the second discharging circuit, the sampling circuit 12 is respectively connected to the output end of the first charging circuit and the output end of the second charging circuit; the second output end of the logic circuit 132 is respectively connected to the control end of the second charging circuit and the control end of the second discharging circuit; the first charging circuit is configured to be turned on when the logic circuit 132 detects a rising edge of the first signal output by the hard disk status pin to start charging, and to be turned off when the logic circuit 132 detects a falling edge of the first signal output by the hard disk status pin to stop charging, thereby obtaining a first charging voltage value corresponding to a high-level signal; a first discharging circuit, configured to be turned on when the logic circuit 132 detects a falling edge of the first signal output by the delay circuit 131 to start discharging; a second charging circuit, configured to be turned on when the logic circuit 132 detects a falling edge of the first signal output by the hard disk status pin to start charging, and to be cut off when the logic circuit 132 detects a rising edge of the first signal output by the hard disk status pin to stop charging, thereby obtaining a second charging voltage value corresponding to a low-level signal in the first signal; a second discharging circuit, configured to be turned on when the logic circuit 132 detects a rising edge of the first signal output by the delay circuit 131 to start discharging; a sampling control circuit 15, specifically configured to delay a first time to trigger the sampling circuit 12 to sample the first charging voltage value when charging of the first charging circuit is completed, and to trigger the sampling circuit 12 to sample the second charging voltage value when charging of the second charging circuit is completed.

[0090] This embodiment describes the specific structure of the charging circuit and the discharging circuit, as well as their connection relationship with the logic circuit 132, the hard disk status pin, and the sampling circuit 12. Specifically, the charging circuit includes a first charging circuit and a second charging circuit: wherein the first charging circuit is configured to be turned on and start charging when the logic circuit 132 detects a rising edge of the first signal output by the hard disk status pin, and to be turned off and stop charging when the logic circuit 132 detects a falling edge of the first signal output by the hard disk status pin, thereby obtaining a first charging voltage value corresponding to a high-level signal; and the second charging circuit is configured to be turned on and start charging when the logic circuit 132 detects a falling edge of the first signal output by the hard disk status pin, and to be turned off and stop charging when the logic circuit 132 detects a rising edge of the first signal output by the hard disk status pin, thereby obtaining a second charging voltage value corresponding to a low-level signal.

[0091] The discharge circuit includes a first discharge circuit and a second discharge circuit: the first discharge circuit is used to be turned on and start discharging when the logic circuit 132 detects the falling edge of the first signal output by the delay circuit 131, that is, it is delayed to be turned on after the first charging circuit is charged to start discharging; the second discharge circuit is cut off and stops discharging when the logic circuit 132 detects the rising edge of the first signal output by the delay circuit 131, that is, it is delayed to be turned on after the second charging circuit is charged to start discharging.

[0092] Accordingly, when the first charging circuit completes charging according to a high-level signal (i.e., upon detecting the falling edge of the first signal output by the hard disk status pin), the sampling control circuit 15 triggers the sampling circuit 12 to sample the first charging voltage value. When the second charging circuit completes charging according to a low-level signal (i.e., upon detecting the rising edge of the first signal output by the hard disk status pin), the sampling control circuit 15 triggers the sampling circuit 12 to sample the second charging voltage value. The first charging voltage value and the second charging voltage value represent the width of the high-level signal and the width of the low-level signal, respectively. The first pulse width and the second pulse width can be determined by sampling the first and second charging voltage values, thereby parsing the hard disk log data in the first signal to achieve hard disk monitoring.

[0093] In summary, the structure and functional design described in this embodiment can effectively monitor and analyze the hard disk status, and through the coordinated work of the charge and discharge circuit, the logic circuit 132 and the sampling control circuit 15, effective monitoring of the hard disk and data acquisition are achieved.

[0094] As shown in FIG5 , in certain embodiments of the present application, when the second integration circuit 111 includes a first charging circuit and a first discharging circuit, the circuit structure of the second integration circuit 111 includes a first resistor R1, a second resistor R2, a third resistor R3, a first capacitor C1, a first switch K1, and a first amplifier U1B;

[0095] The first end of the first resistor R1 is connected to the hard disk status pin, the second end of the first resistor R1 is respectively connected to the negative input end of the first amplifier U1B, the first end of the first capacitor C1 and the first end of the third resistor R3, the second end of the third resistor R3 is connected to the first end of the first switch K1, the second end of the first switch K1 is respectively connected to the second end of the first capacitor C1 and the output end of the first amplifier U1B, the first end of the second resistor R2 is grounded, the second end of the second resistor R2 is connected to the positive input end of the first amplifier U1B, the control end of the first switch K1 is connected to the output end of the logic circuit 132. The first switch K1 is used to disconnect when the logic circuit 132 detects the rising edge of the first signal output by the hard disk status pin, so that the first capacitor C1 is charged through the first resistor R1, and close when the logic circuit 132 detects the falling edge of the first signal output by the delay circuit 131, so that the first capacitor C1 is discharged through the third resistor R3.

[0096] Furthermore, a buffer circuit 17 (labeled as U1A in FIG5 ) may be provided between the first end of the first resistor R1 and the hard disk status pin to buffer the first signal and improve the reliability of the operation of the back-end second integration circuit 111 .

[0097] In Figure 5, R1 is a charging resistor, R3 is a discharging resistor, and C1 is a charging capacitor. When K1 is disconnected, C1 can be charged through R1; when K1 is closed, C1 can be discharged through R3; K1 is a two-way single-pole switch, where R1=R2=100R3. In order to ensure sufficient discharge even under a pulse signal, the multiple between R3 and R1 / R2 is 100; the output signal is connected to the sampling circuit 12 (such as the analog-to-digital converter used to convert the first charging voltage value output by the second amplifier U2B into a digital signal).

[0098] The output voltage of the first amplifier U1B is U1. Let the high level voltage of the single-wire communication protocol be u and the low level be 0. The output upper limit of all amplifiers is E, and u≥E. Let the high level integration time be t h , the low level integration time is t l R1 = R (resistance of the first resistor R1), C1 = C (capacitance of the first capacitor C1); then the instantaneous value U1(t) of the output voltage of the first amplifier U1B is:

[0099] The output voltage U1 is proportional to the output time t. The parameters should be selected according to the actual circuit. h U1 reaches its maximum value U1max during the stage, ensuring U1max <E。

[0100] The discharge process is a discharge circuit composed of C1 and R3. The instantaneous voltage U1(t) during the discharge process satisfies:

[0101] R3 is the resistance of the third resistor.

[0102] As shown in FIG6 , in certain embodiments of the present application, when the third integration circuit 112 includes a second charging circuit and a second discharging circuit, the circuit structure of the third integration circuit 112 includes a first inverter 16 , a fourth resistor R4 , a fifth resistor R5 , a sixth resistor R6 , a second capacitor C2 , a second switch K2 , and a second amplifier U2B;

[0103] A first end of a fourth resistor R4 is connected to the hard disk status pin via a first inverter 16. A second end of the fourth resistor R4 is respectively connected to the negative input terminal of the second amplifier U2B, the first end of the second capacitor C2, and the first end of a sixth resistor R6. A second end of the sixth resistor R6 is connected to the first end of a second switch K2. A second end of the second switch K2 is respectively connected to the second end of the second capacitor C2 and the output terminal of the second amplifier U2B. A first end of a fifth resistor R5 is grounded. A second end of the fifth resistor R5 is connected to the positive input terminal of the second amplifier U2B. A control end of the second switch K2 is connected to the output terminal of the logic circuit 132.

[0104] The second switch K2 is disconnected when the logic circuit 132 detects the falling edge of the first signal output by the hard disk status pin, so that the second capacitor C2 is charged through the fourth resistor R4, and is closed when the logic circuit 132 detects the rising edge of the first signal output by the delay circuit 131, so that the second capacitor C2 is discharged through the sixth resistor R6.

[0105] Furthermore, a buffer circuit U2A may be provided between the first end of the fourth resistor R4 and the first inverter 16 to buffer the first signal and improve the reliability of the operation of the back-end third integration circuit 112 .

[0106] D1 flips the level of the first signal. The buffer circuit 17 formed by U2A and the third integrator circuit 112 formed by U2B integrate the low-level pulse width. R4 is a charging resistor, R6 is a discharging resistor, and C2 is a charging capacitor. When K2 is disconnected, C2 can be charged through R4; when K2 is closed, C1 can be discharged through R6. K2 is a two-way single-pole switch, where R4 = R5 = 10R6. The output second charging voltage value signal is connected to the sampling circuit 12 (e.g., an analog-to-digital converter, used to convert the second voltage value into a digital signal).

[0107] The voltage at the output of U2B is U2, R4=R1=R, C1=C2=C;

[0108] Then there is,

[0109] As shown in FIG7 , in certain embodiments of the present application, the sampling control circuit 15 includes a seventh resistor R7 , an eighth resistor R8 , a ninth resistor R9 , a third capacitor C3 , a sixth capacitor C6 , a third switch K3 , and a first comparator U3B;

[0110] A first end of a ninth resistor R9 is connected to the hard disk status pin, a second end of the ninth resistor R9 is respectively connected to the first end of the third switch K3 and the positive input terminal of the first comparator U3B, a second end of the third switch K3 is grounded via a third capacitor C3, and a third end of the third switch K3 is grounded via a sixth capacitor C6. A first end of a seventh resistor R7 is connected to the power module V, a second end of the seventh resistor R7 is respectively connected to the first end of the eighth resistor R8 and the negative input terminal of the first comparator U3B, a second end of the eighth resistor R8 is grounded, an output terminal of the first comparator U3B is connected to the sampling circuit 12, and a capacitance of the third capacitor C3 is greater than a capacitance of the sixth capacitor C6.

[0111] The first and second ends of the third switch K3 are turned on when the sampling control circuit 15 operates in the second mode, and the first and third ends of the third switch K3 are turned on when the sampling control circuit 15 operates in the first mode.

[0112] In Figure 7, U3A forms a buffer circuit 17, and the output signal is sent to R9 and C3 / C6 to form an RC filter circuit. The signal at the positive input end of U3B is a triangular wave signal of the charging and discharging of the C3 / C6 capacitor. This triangular wave signal is compared with the voltage set by R7 and R8. U3B is a comparator circuit; among them, the setting of the C3 / C6 capacitor is related to the working mode of the sampling control circuit 15 (that is, the delay time).

[0113] Among them, K3 is a single-pole double-throw switch used to switch the integral capacitor, C3 is a large capacitor used to control the data conversion timing when there is no pulse signal; C6 is a small capacitor used to control the data conversion timing when there is a pulse signal;

[0114] Among them, the parameter selection of C6 needs to meet the integral saturation requirement of the pulse signal duration te, that is: R9×C6=te / 5;

[0115] R9 and C3 form a filter circuit. The voltage on C3 is set to Uc3. When the starting voltage of Uc3 is 0V, the instantaneous voltage U C3 (t) is:

[0116] In order to ensure that C3 can completely discharge the charge during the discharge process, the shortest pulse width t1 can also reach the maximum voltage when there is no pulse signal, that is, Uc3max=E, and take: R9×C3=t2 / 5;

[0117] The instantaneous voltage U at the first terminal of C3 during dischargeC3 (t):

[0118] The sampling control circuit 15 outputs the waveform L1 of the logic signal, which is composed of the comparator circuit composed of U3B. in, is the voltage value of the second terminal of R7.

[0119] As shown in FIG7 , in some embodiments of the present application, the delay circuit 131 includes a tenth resistor R10 , an eleventh resistor R11 , a twelfth resistor R12 , a fourth capacitor C4 , a seventh capacitor C7 , a fourth switch K4 , and a second comparator U3B;

[0120] A first end of the tenth resistor R10 is connected to the power module V, a second end of the tenth resistor R10 is respectively connected to the first end of the eleventh resistor R11 and the negative input terminal of the second comparator U3B, a second end of the eleventh resistor R11 is grounded, a first end of the twelfth resistor R12 is connected to the output terminal of the sampling control circuit 15, a second end of the twelfth resistor R12 is respectively connected to the first end of the fourth switch K4 and the positive input terminal of the second comparator U3B, a second end of the fourth switch K4 is grounded via a fourth capacitor C4, a third end of the fourth switch K4 is grounded via a seventh capacitor C7, an output terminal of the second comparator U3B is connected to the first input terminal of the logic circuit 132, and the capacitance of the fourth capacitor C4 is greater than that of the seventh capacitor C7;

[0121] The first and second ends of the fourth switch K4 are turned on when the delay circuit 131 operates in the fourth mode, and the first and third ends of the fourth switch K4 are turned on when the delay circuit 131 operates in the third mode.

[0122] The working principle of the delay circuit 131 is the same as that of the sampling control circuit 15. R12 and C4 / C7 form an RC filter circuit, so that the positive input end of U4B is a triangular wave. The triangular wave is compared with the voltage value of the voltage divider circuit composed of U4B and R10 and R11 to obtain the first signal after delay.

[0123] Specifically, when the starting voltage of Uc4 is 0V, the instantaneous voltage of C4 during the charging process of the RC filter circuit is U C4 (t):

[0124] If the maximum voltage reached during the charging process is Uc4max, the instantaneous voltage of C4 during discharge is:

[0125] The switch output of U4B controls the logic L2 of P, which is composed of the comparator circuit formed by U4B:

[0126] in, is the voltage at the connection point of R10 and R11.

[0127] As shown in FIG8 , in certain embodiments of the present application, the logic circuit 132 includes a second inverter D2 , a third inverter D3 , a first AND gate U7 , and a second AND gate U8 ;

[0128] The input end of the second inverter D2 is connected to the hard disk status pin, the output end of the second inverter D2 is connected to the first input end of the first AND gate U7, the input end of the third inverter D3 is connected to the output end of the delay circuit 131, the output end of the third inverter D3 is connected to the second input end of the first AND gate U7, the output end of the first AND gate U7 is the first output end of the logic circuit 132, the first input end of the second AND gate U8 is connected to the hard disk status pin, the second input end of the second AND gate U8 is connected to the output end of the delay circuit 131, and the output end of the second AND gate U8 is the second output end of the logic circuit 132.

[0129] Switch control P is the first signal, and switch control Q is the signal output by delay circuit 131. Switch control P is connected to U7 via D3, and switch control Q is connected to U7 via D2. The signal at the output of U7 is used to control K1 in the second integrator circuit 111. In addition, switch control P is connected to U8, and switch control Q is connected to U8. The signal at the output of U8 is used to control K2 in the third integrator circuit 112.

[0130] In certain embodiments of the present application, the first signal is a signal modulated by the hard disk according to the hard disk log data and the hard disk status signal corresponding to the hard disk status pin, the hard disk status pin is the status indicator pin of the hard disk, the status indicator pin continuously outputs a first control signal of a first level when the hard disk is in a preset state, and outputs a second control signal when the hard disk is in a non-preset state, and the second control signal is a rectangular wave signal; when the hard disk is in the preset state, a plurality of second-level pulse signals are inserted into the first control signal of the first level, and the first control signal is divided by the pulse signal to obtain the first signal; in the non-preset state, the first signal is obtained by encoding each data bit in the hard disk log data into a level signal of a preset width corresponding to each data bit; the demodulation circuit also includes an indicator driving circuit, which is connected to the status indicator; the indicator driving circuit is used to receive the first signal output by the hard disk status pin, and when the hard disk is in a non-preset state, output the first signal to the status indicator to make the status indicator flash; when the hard disk is in the preset state, the second-level pulse signal is filtered out to output the first control signal of the first level to the status indicator.

[0131] As shown in FIG9 , in certain embodiments of the present application, the indicator light driving circuit includes a filter circuit, a fourth amplifier U16 , and a fourteenth resistor R14 ;

[0132] The filter circuit is connected to the hard drive status pin. The output of the filter circuit is connected to the positive input of the fourth amplifier U16. The negative input of the fourth amplifier U16 is connected to its own output and the first end of a fourteenth resistor R14, respectively. The second end of the fourteenth resistor R14 is connected to one end of the status indicator, and the other end of the status indicator is grounded. Specifically, in this embodiment, the hard drive status pin is limited to the status indicator pin. The status indicator pin outputs a fixed-level signal when the hard drive is in a preset state, and outputs a pulse-width signal to cause the indicator to flash when the hard drive is not in the preset state. This ensures that the original function of the indicator is not affected when the status indicator pin is used to output hard drive log data.

[0133] In this embodiment, when the hard disk is in a non-preset state, since the first signal obtained by encoding the hard disk log data and the hard disk status signal is a pulse width signal having a preset width, directly outputting this first signal to the indicator light can drive the indicator light to flash, thereby acknowledging that the hard disk is currently in a non-preset state. When the hard disk is in the preset state, since the first signal obtained by encoding the hard disk log data and the hard disk status signal includes a pulse signal of a second level opposite to the first level, if the width of this pulse signal can be limited to a minimum value such that the human eye cannot distinguish the flashing of the indicator light, then no processing can be performed. If the pulse signal is not limited to a minimum value, a filter circuit can be provided to filter out the pulse signal, obtaining a signal of a constant first level, and using this signal to drive the indicator light. Furthermore, a fourth amplifier U16 and a fourteenth resistor R14 (for current limiting) can be provided between the indicator light and the filter circuit to achieve reliable driving of the indicator light.

[0134] Furthermore, in one implementation, a separate driving circuit can be provided, and the detection circuit 14 controls the driving circuit to generate different driving signals based on the result of determining whether a pulse signal is present. Specifically, when a pulse signal is present, the driving circuit is controlled to generate a signal of a first level to drive the indicator light. When a pulse signal is not present, the driving circuit is controlled to generate a preset square wave to drive the indicator light to flash. In this manner, by regenerating the driving indicator light signal, regardless of how the hard disk log data and hard disk status signal are encoded, as long as the current state of the hard disk can be identified, the indicator light can be driven, and the driving frequency and the like are not affected at all.

[0135] In certain embodiments of the present application, a buffer circuit 17 is further included, which is connected to the analysis circuit 11 and the sampling control circuit 15 respectively; the buffer circuit 17 is used to receive the first signal output by the hard disk status pin, buffer the first signal, and output the buffered first signal to the analysis circuit 11 and the sampling control circuit 15 respectively.

[0136] The buffer circuit in Figure 2 corresponds to U13A in Figure 3, U1A in Figure 5, U2A in Figure 6, and U2A in Figure 7.

[0137] In parameter design, if the hard disk log data and hard disk status signal are encoded using different encoding methods, the pulse width of the first signal is t∈[t1,t2], where t2 is the longest pulse width when there is no pulse signal, then the following is stipulated:

[0138] Special note: [t1, t2] does not include the pulse width of the pulse signal;

[0139] In the instantaneous voltage formula during the charging process and the voltage formula during the discharging process of the RC filter circuit of the sampling control circuit 15, let T is the intermediate parameter; then:

[0140] Solve ts (the delay time of the sampling control circuit 15) according to the above formula. If ts∈(0, t1), then keep it; if Then let ts = t1 / 8;

[0141] Substitute ts into the formula to obtain The value of , according to the analysis, sets the relevant parameters in the circuit;

[0142] Similarly, we can get

[0143] The solved ts is the delay time of the sampling control circuit 15 for the original first signal. This delay time continues to be delayed by td (the delay time of the delay circuit 131 in the loop control circuit 13) based on the circuit U4B. The principle of this circuit is that after the high / low level integration is completed, the sampling circuit 12 samples the integrated value after a delay of ts, and then discharges the integration capacitor after a delay of td.

[0144] As shown in FIG10 , FIG10 is a schematic diagram of waveforms output by each circuit under the action of each of the above circuit modules.

[0145] On the second aspect, some embodiments of the present application also adopt a server, including a hard disk and a demodulation circuit as described above, and the demodulation circuit is connected to the hard disk; the demodulation circuit is used to receive a first signal output by the hard disk status pin of the hard disk, and demodulate the hard disk data according to the first signal to realize monitoring of the hard disk, and the first signal includes the hard disk data.

[0146] For an introduction to the server, please refer to the above embodiment, and this application will not go into details here.

[0147] It should also be noted that, in this specification, relational terms such as first and second, etc., are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the terms "comprises," "comprising," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus comprising a series of elements includes not only those elements, but also other elements not explicitly listed, or elements inherent to such process, method, article, or apparatus. In the absence of further limitations, an element defined by the phrase "comprising a ..." does not exclude the presence of additional identical elements in the process, method, article, or apparatus comprising the element.

[0148] The above description of the disclosed embodiments is intended to enable one skilled in the art to implement or use the present application. Various modifications to these embodiments will be readily apparent to one skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present application. Therefore, the present application is not limited to the embodiments shown herein, but is intended to conform to the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A demodulation circuit, characterized in that: It includes an analytical circuit, a sampling circuit and a sampling control circuit, wherein the sampling circuit is connected to the analytical circuit and the sampling control circuit respectively; The analysis circuit is configured to receive a first signal output by a hard disk status pin and analyze a high-level signal and a low-level signal in the first signal to obtain a first pulse width corresponding to the high-level signal and a second pulse width corresponding to the low-level signal; the first signal includes hard disk data; and The sampling control circuit is used to trigger the sampling circuit to sample the first pulse width and the second pulse width according to the first signal, so as to parse the hard disk data corresponding to the first signal according to the sampled first pulse width and second pulse width to realize monitoring of the hard disk.

2. The demodulation circuit according to claim 1, wherein: The analysis circuit includes a charging circuit and a discharging circuit, and the demodulation circuit further includes a circuit control circuit, wherein the charging circuit is connected to the sampling control circuit, the circuit control circuit and the discharging circuit respectively; The charging circuit is configured to charge according to a preset level signal in the first signal when the charging circuit is turned on, thereby obtaining an i-th pulse width; The discharge circuit is configured to discharge according to the non-preset level signal in the first signal when the discharge circuit is turned on; The sampling control circuit is configured to delay triggering the sampling circuit to sample the i-th pulse width for a first time after the charging circuit is charged; as well as The loop control circuit is configured to delay a second time to control the discharge loop to be turned on after the sampling control circuit triggers the sampling circuit to sample the i-th pulse width; When the preset level signal is a high level signal, i is one; when the preset level signal is a low level signal, i is two.

3. The demodulation circuit according to claim 2, wherein: When the preset level signal is a high level signal, the loop control circuit controls the charging loop to be turned on when detecting a rising edge of the first signal, and triggers the sampling circuit to sample the first pulse width when detecting a falling edge of the first signal; And when the preset level signal is a low level signal, the loop control circuit receives the first signal through the first inverter, and when the rising edge of the output of the first inverter is detected, the charging circuit is controlled to be turned on, and when the falling edge of the output of the first inverter is detected, the sampling circuit is triggered to sample the second pulse width.

4. The demodulation circuit according to claim 2, wherein: The first signal is a signal modulated by the hard disk according to the hard disk log data and the hard disk status signal corresponding to the hard disk status pin. The hard disk status pin continuously outputs a first control signal of a first level when the hard disk is in a preset state, and outputs a second control signal when the hard disk is in a non-preset state. The second control signal is a rectangular wave signal. In the preset state, the hard disk inserts a plurality of pulse signals of a second level into the first control signal and divides the first control signal using the pulse signals to obtain the first signal. In the non-preset state, the hard disk encodes each data bit in the hard disk log data into a level signal of a preset width corresponding to each data bit to obtain the first signal. The demodulation circuit further includes: a detection circuit, wherein the detection circuit is connected to the sampling control circuit and the loop control circuit respectively; as well as The detection circuit is used to detect whether the pulse signal exists in the first signal, and adjust the first time and / or the second time according to the detection result.

5. The demodulation circuit according to claim 4, wherein: Methods for encoding each data bit into a level signal of a preset width include: Encode each data bit into a pulse width signal corresponding to the duty cycle; or Each data bit is encoded as a level signal of a preset width, and when the level signals of two adjacent data bits are opposite or the level signals of two adjacent data bits are the same, an opposite level signal of a certain width is inserted between the two adjacent data bits.

6. The demodulation circuit according to claim 4, wherein: the detection circuit is configured to control the sampling control circuit to operate in a first mode when it is determined that the pulse signal exists in the first signal, and to control the sampling control circuit to operate in a second mode when it is determined that the pulse signal does not exist in the first signal; and The sampling control circuit is configured to, after the charging circuit is fully charged, delay a first preset time to trigger the sampling circuit to sample the i-th pulse width in response to operating in the first mode; and delay a second preset time to trigger the sampling circuit to sample the i-th pulse width in response to operating in the second mode, wherein the first preset time is less than the second preset time, and the first time is either the first preset time or the second preset time.

7. The demodulation circuit according to claim 4, wherein: the detection circuit is configured to control the loop control circuit to operate in a third mode when it is determined that the pulse signal exists in the first signal, and to control the loop control circuit to operate in a fourth mode when it is determined that the pulse signal does not exist in the first signal; and The loop control circuit is configured to, after the sampling control circuit triggers the sampling circuit to sample the i-th pulse width, delay the discharge loop for a third preset time in response to operating in the third mode, and delay the discharge loop for a fourth preset time in response to operating in the fourth mode, wherein the third preset time is less than the fourth preset time, and the second time is the third preset time or the fourth preset time.

8. The demodulation circuit according to claim 4, wherein: The detection circuit includes a first integration circuit, a comparison circuit and a trigger circuit connected in sequence, and the trigger circuit is connected to the sampling control circuit and the loop control circuit respectively; The first integration circuit is configured to integrate the signal of the second level in the first signal to obtain a first integrated value; the comparison circuit being configured to compare the first integral value with a first preset integral value and a second preset integral value, and output a first trigger signal in response to the first integral value being greater than the first preset integral value, and output a second trigger signal in response to the first integral value being greater than the second preset integral value, and the first preset integral value being less than the second preset integral value; as well as The trigger circuit is configured to adjust the first time and / or the second time according to the first trigger signal or the second trigger signal.

9. The demodulation circuit according to claim 4, wherein: The loop control circuit includes a delay circuit and a logic circuit; The output end of the delay circuit is connected to the first input end of the logic circuit, the control end of the delay circuit is connected to the detection circuit, the second input end of the logic circuit is connected to the hard disk status pin, and the output end of the logic circuit is connected to the charging circuit and the discharging circuit respectively; The delay circuit is used to delay the first signal by the second time and output it; The logic circuit is configured to perform a logic operation based on the first signal output by the delay circuit and the first signal output by the hard disk status pin, so as to output a first conduction signal when a starting edge of a preset level signal of the first signal output by the hard disk status pin is detected, and output a second conduction signal when an ending edge of the preset level signal of the first signal output by the delay circuit is detected; The charging circuit is configured to be turned on upon receiving the first conduction signal, so as to charge according to the preset level signal to obtain the i-th pulse width; and The discharge circuit is configured to be turned on upon receiving the second conduction signal, so as to discharge according to the non-preset level signal.

10. The demodulation circuit according to claim 9, wherein: The charging circuit includes a first charging circuit and a second charging circuit, and the discharging circuit includes a first discharging circuit and a second discharging circuit; The first output end of the logic circuit is connected to the control end of the first charging circuit and the control end of the first discharging circuit respectively; the hard disk status pin is connected to the input end of the first charging circuit, the input end of the first discharging circuit, the input end of the second charging circuit, and the input end of the second discharging circuit respectively; the sampling circuit is connected to the output end of the first charging circuit and the output end of the second charging circuit respectively; and the second output end of the logic circuit is connected to the control end of the second charging circuit and the control end of the second discharging circuit respectively; The first charging circuit is configured to be turned on to start charging when the logic circuit detects a rising edge of the first signal output by the hard disk status pin, and to be turned off to stop charging when the logic circuit detects a falling edge of the first signal output by the hard disk status pin, thereby obtaining a first charging voltage value corresponding to the high-level signal; The first discharging circuit is configured to be turned on when the logic circuit detects a falling edge of the first signal output by the delay circuit to start discharging; The second charging circuit is configured to be turned on to start charging when the logic circuit detects a falling edge of the first signal output by the hard disk status pin, and to be turned off to stop charging when the logic circuit detects a rising edge of the first signal output by the hard disk status pin, thereby obtaining a second charging voltage value corresponding to a low-level signal in the first signal; The second discharging circuit is configured to be turned on when the logic circuit detects a rising edge of the first signal output by the delay circuit to start discharging; and The sampling control circuit is used to delay a first time to trigger the sampling circuit to sample the first charging voltage value when the first charging circuit is fully charged, and to trigger the sampling circuit to sample the second charging voltage value when the second charging circuit is fully charged.

11. The demodulation circuit according to claim 10, wherein: When the second integration circuit includes the first charging circuit and the first discharging circuit, the circuit structure of the second integration circuit includes a first resistor, a second resistor, a third resistor, a first capacitor, a first switch, and a first amplifier; a first end of the first resistor being connected to the hard disk status pin, a second end of the first resistor being respectively connected to the negative input terminal of the first amplifier, the first end of the first capacitor, and the first end of the third resistor, a second end of the third resistor being connected to the first end of the first switch, a second end of the first switch being respectively connected to the second end of the first capacitor and the output terminal of the first amplifier, a first end of the second resistor being grounded, a second end of the second resistor being connected to the positive input terminal of the first amplifier, and a control end of the first switch being connected to the output terminal of the logic circuit; and The first switch is used to disconnect when the logic circuit detects the rising edge of the first signal output by the hard disk status pin, so that the first capacitor is charged through the first resistor, and to close when the logic circuit detects the falling edge of the first signal output by the delay circuit, so that the first capacitor is discharged through the third resistor.

12. The demodulation circuit according to claim 10, wherein: When the third integration circuit includes the second charging circuit and the second discharging circuit, the circuit structure of the third integration circuit includes a first inverter, a fourth resistor, a fifth resistor, a sixth resistor, a second capacitor, a second switch, and a second amplifier; a first end of the fourth resistor being connected to the hard disk status pin via a first inverter, a second end of the fourth resistor being connected to the negative input terminal of the second amplifier, the first end of the second capacitor, and the first end of the sixth resistor, a second end of the sixth resistor being connected to the first end of the second switch, and a second end of the second switch being connected to the second end of the second capacitor and the output terminal of the second amplifier, a first end of the fifth resistor being grounded, a second end of the fifth resistor being connected to the positive input terminal of the second amplifier, and a control end of the second switch being connected to the output terminal of the logic circuit; and The second switch is disconnected when the logic circuit detects the falling edge of the first signal output by the hard disk status pin, so that the second capacitor is charged through the fourth resistor, and is closed when the logic circuit detects the rising edge of the first signal output by the delay circuit, so that the second capacitor is discharged through the sixth resistor.

13. The demodulation circuit according to claim 6, wherein: The sampling control circuit includes a seventh resistor, an eighth resistor, a ninth resistor, a third capacitor, a sixth capacitor, a third switch, and a first comparator; A first end of the ninth resistor is connected to the hard disk status pin, a second end of the ninth resistor is respectively connected to the first end of the third switch and the positive input end of the first comparator, a second end of the third switch is grounded via the third capacitor, and a third end of the third switch is grounded via the sixth capacitor, a first end of the seventh resistor is connected to the power module, a second end of the seventh resistor is respectively connected to the first end of the eighth resistor and the negative input end of the first comparator, a second end of the eighth resistor is grounded, an output end of the first comparator is connected to the sampling circuit, and a capacitance of the third capacitor is greater than a capacitance of the sixth capacitor; as well as The first and second ends of the third switch are conductive when the sampling control circuit operates in the second mode, and the first and third ends of the third switch are conductive when the sampling control circuit operates in the first mode.

14. The demodulation circuit according to claim 9, wherein: The delay circuit includes a tenth resistor, an eleventh resistor, a twelfth resistor, a fourth capacitor, a seventh capacitor, a fourth switch and a second comparator; A first end of the tenth resistor is connected to the power module, a second end of the tenth resistor is respectively connected to the first end of the eleventh resistor and the negative input end of the second comparator, a second end of the eleventh resistor is grounded, a first end of the twelfth resistor is connected to the output end of the sampling control circuit, a second end of the twelfth resistor is respectively connected to the first end of the fourth switch and the positive input end of the second comparator, a second end of the fourth switch is grounded via the fourth capacitor, a third end of the fourth switch is grounded via the seventh capacitor, an output end of the second comparator is connected to the first input end of the logic circuit, and a capacitance of the fourth capacitor is greater than a capacitance of the seventh capacitor; as well as The first and second ends of the fourth switch are turned on when the delay circuit operates in the fourth mode, and the first and third ends of the fourth switch are turned on when the delay circuit operates in the third mode.

15. The demodulation circuit according to claim 9, wherein: The logic circuit includes a second inverter, a third inverter, a first AND gate, and a second AND gate; The input end of the second inverter is connected to the hard disk status pin, the output end of the second inverter is connected to the first input end of the first AND gate, the input end of the third inverter is connected to the output end of the delay circuit, the output end of the third inverter is connected to the second input end of the first AND gate, the output end of the first AND gate is the first output end of the logic circuit, the first input end of the second AND gate is connected to the hard disk status pin, the second input end of the second AND gate is connected to the output end of the delay circuit, and the output end of the second AND gate is the second output end of the logic circuit.

16. The demodulation circuit according to claim 8, wherein: The first integration circuit includes a third amplifier, a fifth capacitor, and a thirteenth resistor; the comparison circuit includes a third comparator, a fourth comparator, a first reference circuit, and a second reference circuit; the trigger circuit includes a trigger; The first end of the thirteenth resistor is connected to the hard disk status pin through the first inverter, the second end of the thirteenth resistor is respectively connected to the positive input end of the third amplifier and the first end of the fifth capacitor, the second end of the fifth capacitor is grounded, the negative input end of the third amplifier is respectively connected to the output end of the third amplifier, the negative input end of the third comparator and the negative input end of the fourth comparator, the positive input end of the third comparator is connected to the first reference circuit, the positive input end of the fourth comparator is connected to the second reference circuit, the output end of the third comparator is connected to the first input end of the trigger, the output end of the fourth comparator is connected to the second input end of the trigger, the output end of the trigger is the output end of the detection circuit, and the first reference voltage output by the first reference circuit is less than the second reference voltage output by the second reference circuit.

17. The demodulation circuit according to any one of claims 1 to 16, wherein: The first signal is a signal modulated by the hard disk according to the hard disk log data and the hard disk status signal corresponding to the hard disk status pin. The hard disk status pin is a status indicator pin of the hard disk. The status indicator pin continuously outputs a first control signal of a first level when the hard disk is in a preset state, and outputs a second control signal to flash the status indicator when the hard disk is in a non-preset state. The second control signal is a rectangular wave signal. The hard disk, in the preset state, inserts a plurality of pulse signals of the second level into the first control signal of the first level, and divides the first control signal using the pulse signals to obtain the first signal. In the non-preset state, the hard disk obtains the first signal by encoding each data bit in the hard disk log data into a level signal of a preset width corresponding to each data bit. as well as The demodulation circuit further includes: an indicator light driving circuit, wherein the indicator light driving circuit is connected to the status indicator light; The indicator light driving circuit is used to receive the first signal output by the hard disk status pin, and when the hard disk is in a non-preset state, output the first signal to the status indicator light to make the status indicator light flash; when the hard disk is in the preset state, filter out the second level pulse signal to output the first control signal of the first level to the status indicator light.

18. The demodulation circuit according to claim 17, wherein: The indicator light driving circuit includes a filter circuit, a fourth amplifier, and a fourteenth resistor; The filter circuit is connected to the hard disk status pin, the output end of the filter circuit is connected to the positive input end of the fourth amplifier, the negative input end of the fourth amplifier is respectively connected to its own output end and the first end of the fourteenth resistor, the second end of the fourteenth resistor is connected to one end of the status indicator light, and the other end of the status indicator light is grounded.

19. The demodulation circuit according to any one of claims 1 to 16, wherein: It also includes a buffer circuit, wherein the buffer circuit is connected to the analytical circuit and the sampling control circuit respectively; The buffer circuit is used to receive the first signal output by the hard disk status pin, buffer the first signal, and output the buffered first signal to the analysis circuit and the sampling control circuit respectively.

20. A server, characterized in that: comprising a hard disk and a demodulation circuit according to any one of claims 1 to 19, wherein the demodulation circuit is connected to the hard disk; The demodulation circuit is used to receive a first signal output by a hard disk status pin of the hard disk, and demodulate the hard disk log data according to the first signal to monitor the hard disk, wherein the first signal includes hard disk data.

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