Printed circuit board and manufacturing method therefor

Abstract

In the embodiments of the present disclosure, provided are a printed circuit board and a manufacturing method therefor. The printed circuit board comprises: a signal plane portion, which comprises a plurality of metal layers for transmitting signals; a power plane portion, which is stacked with the signal plane portion by means of a connection layer, and comprises a plurality of metal layers for providing power; a plurality of power vias, each of which extends from the surface of the signal plane portion that faces away from the power plane portion, through the signal plane portion, the connection layer and the power plane portion, to the surface of the power plane portion that faces away from the signal plane portion; and a plurality of signal vias, each of which extends from the surface of the signal plane portion that faces away from the power plane portion into the signal plane portion, but not into the power plane portion, the radial dimension of each signal via among the plurality of signal vias being smaller than the radial dimension of each power via among the plurality of power vias.

Description

Printed circuit board and method for manufacturing the same

[0001] This application claims priority to the Chinese invention patent application entitled “Printed circuit board and method for manufacturing the same” filed on March 27, 2024, with application number 202410362817.7. The entire contents of that application are incorporated herein by reference. Technical Field

[0002] Embodiments of the present disclosure generally relate to the technical field of electronic devices, and more particularly, to a printed circuit board and a method for manufacturing the same. Background Art

[0003] The ever-increasing signal rates transmitted by integrated circuit chips are leading to a further increase in the required channel bandwidth. To meet this requirement, chip size is increasing, the number of signal pins on chips is increasing, and the spacing between pins is shrinking. This increase in the number of signal pins on chips requires more signal planes, while the increased chip power consumption requires more power planes.

[0004] In this case, the vias in the printed circuit board (PCB) used to carry the chip will be more dense, so vias with smaller diameters will need to be used. In addition, due to the increase in bandwidth and the reduction in pin spacing, crosstalk between signals is more difficult to control, and more via shielding is needed to solve the crosstalk problem. In addition, the increase in the number of layers of the signal plane leads to an increase in the thickness of the PCB board, which will increase the length of the signal via. In addition to the signal plane, more power planes are required to ensure the current flow capacity of the chip, which leads to a further increase in the thickness of the PCB. In addition, the increase in board thickness and the decrease in via diameter will lead to an increase in the ratio of board thickness to via aperture (also referred to as aspect ratio in this article), which makes the manufacturing difficulty of the via more difficult and affects the processing yield of the PCB. In addition, the reduction in via diameter will lead to an increase in the inductive load of the via, causing the signal via reflection to be too large, affecting the signal integrity of the chip. At the same time, dense signal vias will affect the current flow capacity of the chip. Summary of the Invention

[0005] In one aspect of the present disclosure, a printed circuit board is provided, comprising: a signal plane portion, comprising a plurality of metal layers for transmitting signals; a power plane portion, overlapping the signal plane portion through a connection layer, and comprising a plurality of metal layers for providing power; a plurality of power vias, each extending from a surface of the signal plane portion facing away from the power plane portion, through the signal plane portion, the connection layer and the power plane portion, to a surface of the power plane portion facing away from the signal plane portion; and a plurality of signal vias, each extending from a surface of the signal plane portion facing away from the power plane portion into the signal plane portion, and not extending into the power plane portion, wherein a radial dimension of each of the plurality of signal vias is smaller than a radial dimension of each of the plurality of power vias.

[0006] In another aspect of the present disclosure, a method for manufacturing a printed circuit board is provided, comprising: forming a signal plane portion, the signal plane portion comprising a plurality of metal layers for transmitting signals; forming a plurality of signal vias in the signal plane portion, the plurality of signal vias respectively extending from a surface of the signal plane portion into the signal plane portion; forming a power plane portion, the power plane portion comprising a plurality of metal layers for providing power; overlapping the power plane portion with the signal plane portion through a connecting layer, wherein the surface of the signal plane portion faces away from the power plane portion; and forming a plurality of power vias in the signal plane portion and the power plane portion, the plurality of power vias respectively extending from the surface of the signal plane portion to a surface of the power plane portion facing away from the signal plane portion, wherein a radial dimension of each of the plurality of signal vias is smaller than a radial dimension of each of the plurality of power vias.

[0007] It should be understood that the content described in this content section is not intended to limit the key features or important features of the embodiments of the present disclosure, nor is it intended to limit the scope of the present disclosure. Other features of the present disclosure will become easily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] The above and other features, advantages and aspects of the embodiments of the present disclosure will become more apparent with reference to the following detailed description in conjunction with the accompanying drawings. In the accompanying drawings, the same or similar reference numerals represent the same or similar elements, wherein:

[0009] 1A and 1B show schematic cross-sectional views of conventional printed circuit boards;

[0010] 2A to 2D illustrate exemplary arrangements of conventional pads and vias;

[0011] FIG3 shows a schematic cross-sectional view of a printed circuit board according to some embodiments of the present disclosure;

[0012] 4A and 4B illustrate exemplary placement of capacitive loading pads relative to vias; and

[0013] 5A to 5E illustrate a process of manufacturing a printed circuit board according to some embodiments of the present disclosure.

[0014] Explanation of the reference numerals: 100 printed circuit board; 110, 110' signal plane portion; 111 first surface; 112 second surface; 140, 140' metal layer; 150, 150' dielectric layer; 120, 120' power plane portion; 123 third surface; 124 fourth surface; 130 connection layer; 160, 160' power via; 161, 161' signal via; 1611 first signal via; 1612 second signal via; 171, 171' signal pad; 172, 172' power pad; 180 capacitive load pad; 181 first end; 182 second end; 183 third end; 184 fourth end; 190' trace. DETAILED DESCRIPTION

[0015] The preferred embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. Although preferred embodiments of the present disclosure are shown in the accompanying drawings, it should be understood that the present disclosure can be implemented in various forms and should not be limited by the embodiments set forth herein. Rather, these embodiments are provided to make the present disclosure more thorough and complete, and to fully convey the scope of the present disclosure to those skilled in the art.

[0016] As used herein, the term "including" and its variations represent open inclusion, i.e., "including but not limited to." Unless otherwise stated, the term "or" means "and / or." The term "based on" means "based at least in part on." The terms "one example embodiment" and "an embodiment" mean "at least one example embodiment." The term "another embodiment" means "at least one additional embodiment." The terms "first," "second," etc. may refer to different or identical objects.

[0017] As briefly mentioned above, vias in PCBs are becoming increasingly dense, necessitating the use of vias with smaller diameters. Furthermore, due to increased bandwidth and reduced pin spacing, crosstalk between signals is becoming increasingly difficult to control, necessitating the addition of more via shielding to address this issue. Furthermore, the increased number of signal plane layers leads to increased PCB thickness, which in turn increases the length of the signal vias. In addition to the signal planes, more power planes are required to ensure the chip's current flow capacity, further increasing the PCB's thickness. Furthermore, the increased board thickness and reduced via diameter lead to an increase in the ratio of board thickness to via diameter (also referred to herein as the aspect ratio), which increases the manufacturing difficulty of the vias and affects the PCB's processing yield. Furthermore, the reduced size of the signal vias leads to an increase in the via's inductive load, resulting in excessive signal via reflections, which impacts the chip's signal integrity. Furthermore, the densely packed signal vias can affect the chip's current flow capacity. This will be further described below in conjunction with Figures 1A to 2D. Figures 1A and 1B show schematic cross-sectional views of a conventional printed circuit board. 2A to 2D illustrate exemplary arrangements of conventional pads and vias.

[0018] As shown in FIG1A , a conventional printed circuit board (PCB) includes a signal plane portion 110' and power plane portions 120' located on either side of the signal plane portion 110'. The signal plane portion 110' and the two power plane portions 120' are laminated together in a single step to form a symmetrical stacked structure. Each of the signal plane portion 110' and the two power plane portions 120' includes multiple metal layers 140' and a dielectric layer 150' located between adjacent metal layers 140'. Signal vias 161' extend from the surface of the power plane portion 120' into the signal plane portion 110'. Signal pads 171' connected to the signal vias 161' are located on the surface of the power plane portion 120'. The maximum length of the signal vias 161' is equal to the overall thickness of the PCB minus the thickness of the underlying power plane portion 120'. For example, if the PCB thickness is 6 millimeters (mm) and each power plane portion 120' is 1.5 mm thick, the maximum length of the signal vias 161' is 4.5 mm.

[0019] As shown in FIG1B , another conventional printed circuit board includes a power plane portion 120 ′ and a signal plane portion 110 ′ located on both sides of the power plane portion 120 ′. The power plane portion 120 ′ and the two signal plane portions 110 ′ are formed into a symmetrical stacked structure by a single lamination. The power plane portion 120 ′ and the two signal plane portions 110 ′ each include a plurality of metal layers 140 ′ and a dielectric layer 150 ′ located between adjacent metal layers 140 ′. A signal via 161 ′ extends from the surface of one signal plane portion 110 ′ to the surface of the other signal plane portion 110 ′. A signal pad 171 ′ connected to the signal via 161 ′ is provided on the surface of the signal plane portion 110 ′. The maximum length of the signal via 161 ′ is equal to the overall thickness of the printed circuit board. As an example, when the thickness of the printed circuit board is 6 mm, the maximum length of the signal via 161 ′ is 6 mm.

[0020] It should be noted that the numbers, values, etc. mentioned above and elsewhere in this disclosure are exemplary and are not intended to limit the scope of this disclosure in any way. Any other appropriate numbers and values ​​are possible.

[0021] As shown in Figure 2A, multiple signal pads 171' and multiple power pads 172' can be arranged in an array. Each of the signal pads 171' and the power pads 172' can have a diameter of 0.5mm, and the spacing between adjacent pads can be 1mm. A signal via 161' is provided at the center of each signal pad 171', and a power via 160' is provided at the center of each power pad 172'. Each via in the signal via 161' and the power via 160' can have a diameter of 0.3mm. The spacing between adjacent vias can also be 1mm.

[0022] As shown in Figure 2B, multiple signal pads 171' and multiple power pads 172' can be arranged in an array. Each of the signal pads 171' and the power pads 172' can have a diameter of 0.5mm, and the spacing between adjacent pads can be 1mm. The outside of each signal pad 171' is provided with a corresponding signal via 161', and the signal via 161' is connected to the signal pad 171' through a trace 190'. The outside of each power pad 172' is provided with a power via 160', and the power via 160' is connected to the power pad 172' through a trace 190'. Each via in the signal via 161' and the power via 160' can have a diameter of 0.3mm. The spacing between adjacent vias can also be 1mm.

[0023] Each of the signal via 161 ′ and the power via 160 ′ shown in FIG. 2A and FIG. 2B may be formed in the printed circuit board by a drill having a radial dimension of 0.3 mm.

[0024] As shown in Figure 2C, as the pin density and signal rate of the chip increase, the spacing between adjacent pads in signal pads 171' and power pads 172' further decreases. For example, when the pad diameter is 0.5mm, the spacing between adjacent pads can be 0.8mm. The reduced spacing between adjacent pads makes it more difficult to control crosstalk between signals. In addition, when the pad size and via size remain unchanged, the reduced spacing between vias will lead to an increase in the impedance deviation of the vias.

[0025] In order to reduce the crosstalk between signals caused by the reduction in the spacing between vias, the spacing between the vias and the via diameter can be reduced to optimize the shielding effect. As shown in Figure 2D, when the pad diameter is 0.5mm and the spacing between adjacent pads is 0.8mm, each via in the signal via 161' and the power via 160' can have a diameter of 0.2mm, and the spacing between adjacent vias can be reduced to 0.6mm. In the case where the thickness of the printed circuit board is large, the thickness-to-diameter ratio of the printed circuit board will be too large. For example, when the thickness of the printed circuit board is 6mm and the via diameter is 0.2mm, the thickness-to-diameter ratio is 30:1. In addition, the thinning of the via will cause the inductive load of the signal via 161' to continue to increase, making the reflection of the signal via 161' too large, affecting the signal integrity of the chip. In addition, the dense signal vias 161' will affect the current flow capacity of the chip.

[0026] Embodiments of the present disclosure provide a printed circuit board and a method for manufacturing the same, thereby achieving a smaller signal via diameter, reducing the spacing between vias, improving circuit board processing yield, reducing crosstalk between signals, lowering inductive loads, ensuring signal integrity, and improving current flow capacity. The embodiments of the present disclosure are described below with reference to Figures 3 to 5E.

[0027] Figure 3 shows a schematic cross-sectional view of a printed circuit board according to some embodiments of the present disclosure. As shown in Figure 3 , the printed circuit board 100 described herein generally includes a signal plane portion 110 , a power plane portion 120 , a connection layer 130 , a plurality of power vias 160 , and a plurality of signal vias 161 .

[0028] The signal plane portion 110 includes multiple metal layers 140 for transmitting signals. Adjacent metal layers 140 of the signal plane portion 110 are separated by dielectric layers 150. Similarly, the power plane portion 120 includes multiple metal layers 140 for providing power. Adjacent metal layers 140 of the power plane portion 120 are separated by dielectric layers 150. A connection layer 130 is disposed between the power plane portion 120 and the signal plane portion 110 to connect them together, so that the power plane portion 120 and the signal plane portion 110 overlap each other. Unlike the symmetrical stacking structure of the printed circuit board shown in Figures 1A and 1B, the printed circuit board 100 shown in Figure 3 has an asymmetrical stacking structure. When the printed circuit board 100 is positioned in the orientation shown in Figure 3, the signal plane portion 110 is positioned above the power plane portion 120. It should be understood that when the printed circuit board 100 is positioned in other orientations, the power plane portion 120 and the signal plane portion 110 may have other relative positions.

[0029] As shown in FIG3 , a power via 160 extends from the surface of the signal plane portion 110 facing away from the power plane portion 120, through the signal plane portion 110, the connection layer 130, and the power plane portion 120, to the surface of the power plane portion 120 facing away from the signal plane portion 110. The power via 160 can be electrically connected to the power plane portion 120 and the metal layer 140 in the signal plane portion 110. FIG3 shows only a single power via 160 as an example to illustrate the principles of the present disclosure. It should be understood that other power vias 160 can also have a similar arrangement, namely, extending from the surface of the signal plane portion 110 facing away from the power plane portion 120 to the surface of the power plane portion 120 facing away from the signal plane portion 110.

[0030] As shown in FIG. 3 , power pads 172 electrically connected to the power vias 160 may be provided on the surfaces of the signal plane portion 110 and the power plane portion 120 for connection to corresponding pins on the chip.

[0031] As shown in FIG3 , a signal via 161 extends from a surface of the signal plane portion 110 facing away from the power plane portion 120 into the signal plane portion 110 and does not extend into the power plane portion 120. The signal via 161 can be electrically connected to the metal layer 140 in the signal plane portion 110. FIG3 shows only a single signal via 161 as an example to illustrate the principles of the present disclosure. It should be understood that other signal vias 161 may have a similar arrangement, namely, extending from a surface of the signal plane portion 110 facing away from the power plane portion 120 into the signal plane portion 110 and not extending into the power plane portion 120. The radial dimension of each signal via 161 in the plurality of signal vias 161 is smaller than the radial dimension of each power via 160 in the plurality of power vias 160. For example, if the radial dimension of the power via 160 is 0.3 mm, the radial dimension of the signal via 161 may be 0.2 mm.

[0032] As shown in FIG. 3 , a signal pad 171 electrically connected to the signal via 161 may be provided on the surface of the signal plane portion 110 for connection to a corresponding pin on the chip.

[0033] As an example, the overall thickness of the printed circuit board 100 can be 6 mm, of which the power plane 120 is approximately 3.5 mm thick, the signal plane 110 is approximately 2.5 mm thick, and the connection layer 130 is relatively thin and negligible. In this case, the aspect ratio of the signal plane 110 to the signal via 161 is 17.5:1, a 41% reduction compared to the aspect ratio of 30:1. This reduction in aspect ratio can reduce the manufacturing difficulty of the printed circuit board 100 and improve the manufacturing yield.

[0034] In some embodiments, the signal plane portion 110 is formed in a first lamination process, the power plane portion 120 is formed in a second lamination process, and the signal plane portion 110 and the power plane portion 120 are stacked together via the connection layer 130 in a third lamination process. A plurality of signal vias 161 are formed in the power plane portion 120 after the first lamination process and before the third lamination process, and a plurality of power vias 160 are formed in the signal plane portion 110 and the power plane portion 120 after the third lamination process. By laminating the signal plane portion 110 and the power plane portion 120 separately, signal vias 161 having a smaller diameter can be pre-formed in the signal plane portion 110, and the spacing between the signal vias 161 can be reduced, thereby resolving the problem of crosstalk between signals.

[0035] 3 , at least one signal via 161 extends from a surface of the signal plane portion 110 facing away from the power plane portion 120 to a metal layer 140 adjacent to the connection layer 130 among the plurality of metal layers 140 of the signal plane portion 110. Of course, some of the plurality of signal vias 161 may also extend from a surface of the signal plane portion 110 facing away from the power plane portion 120 to an intermediate metal layer 140 of the signal plane portion 110.

[0036] As mentioned above, a reduction in the diameter of the signal via will cause the via's inductive load to increase continuously, resulting in excessive signal via reflection, which will affect the chip's signal integrity. At the same time, dense signal vias will affect the chip's current flow capacity. To this end, capacitive load pads can be provided in the signal plane portion 110 to alleviate signal reflections caused by the inductive load. Figures 4A and 4B show an exemplary arrangement of capacitive load pads relative to the vias.

[0037] In some embodiments, as shown in Figures 4A and 4B , multiple capacitive loading pads 180 are formed in multiple metal layers 140 of the signal plane portion 110 and are electrically connected to at least a portion of the multiple signal vias 161. In some embodiments, capacitive loading pads 180 may be provided in each metal layer 140 of the signal plane portion 110. In some embodiments, capacitive loading pads 180 may be provided in only a portion of the metal layers 140 of the signal plane portion 110. The capacitive loading pads 180 connected to each signal via 161 may form a capacitor. Figures 4A and 4B illustrate only two signal vias 161 as an example to illustrate the arrangement of capacitive loading pads 180. It should be understood that other signal vias 161 may also be connected to corresponding capacitive loading pads 180. By providing capacitive loading pads 180, the problem of excessive signal reflection caused by inductive loads can be resolved, ensuring signal integrity.

[0038] In some embodiments, as shown in FIG4A and FIG4B , at least one pair of adjacent signal vias 161 among the plurality of signal vias 161 can be respectively connected to at least two capacitive load pads 180 among the plurality of capacitive load pads 180. Each pair of adjacent signal vias 161 among the at least one pair of adjacent signal vias 161 can include a first signal via 1611 and a second signal via 1612. The at least two capacitive load pads 180 connected to the first signal via 1611 can be offset in a direction away from the corresponding second signal via 1612, and the at least two capacitive load pads 180 connected to the second signal via 1612 can be offset in a direction away from the corresponding first signal via 1611. By offsetting the capacitive load pads 180, a smaller spacing can be achieved between adjacent signal vias 161 while preventing short circuits between adjacent signal vias 161.

[0039] In some embodiments, as shown in FIG4A and FIG4B , each capacitive load pad 180 of the plurality of capacitive load pads 180 has an elliptical shape. Each of the at least two capacitive load pads 180 connected to the first signal via 1611 has a first end 181 and a second end 182 along the longitudinal direction. First end 181 is closer to the second signal via 1612 than second end 182, and first end 181 is closer to the first signal via 1611 than second end 182. Each of the at least two capacitive load pads 180 connected to the second signal via 1612 has a third end 183 and a fourth end 184 along the longitudinal direction. Third end 183 is closer to the first signal via 1611 than fourth end 184, and third end 183 is closer to the second signal via 1612 than fourth end 184. With this arrangement, the inductive load of adjacent signal vias 161 can be reliably reduced, and a smaller spacing can be achieved to avoid the occurrence of short circuits.

[0040] It should be understood that the capacitive loading pad 180 may have any other suitable shape, such as a circle, a polygon, etc.

[0041] Next, an example manufacturing process of the printed circuit board 100 will be described with reference to FIG. 5A to FIG. 5E .

[0042] As shown in FIG5A , a signal plane portion 110 is formed. The signal plane portion 110 includes a plurality of metal layers 140 for transmitting signals. Adjacent metal layers 140 of the signal plane portion 110 are separated by a dielectric layer 150. The signal plane portion 110 includes a first surface 111 and a second surface 112 facing each other.

[0043] As shown in FIG5B , a plurality of signal vias 161 are formed in the signal plane portion 110 , each extending from the first surface 111 of the signal plane portion 110 into the signal plane portion 110 . FIG5B shows only a single signal via 161 as an example to illustrate the principles of the present disclosure. It should be understood that other signal vias 161 may also have a similar arrangement.

[0044] 5B , at least one signal via 161 extends from the first surface 111 of the signal plane portion 110 to a metal layer 140 adjacent to the second surface 112 of the plurality of metal layers 140 of the signal plane portion 110. Alternatively, some of the plurality of signal vias 161 may extend from the first surface 111 of the signal plane portion 110 to an intermediate metal layer 140 of the signal plane portion 110.

[0045] In some embodiments, as shown in FIG5C , a power plane portion 120 is formed. The power plane portion 120 includes a plurality of metal layers 140 for providing power. Adjacent metal layers 140 of the power plane portion 120 are separated by a dielectric layer 150. The power plane portion 120 includes a third surface 123 and a fourth surface 124 that are opposite to each other.

[0046] 5D , the power plane portion 120 overlaps the signal plane portion 110 via a connection layer 130 . The first surface 111 of the signal plane portion 110 faces away from the power plane portion 120 .

[0047] As shown in FIG5E , a plurality of power vias 160 are formed in the signal plane portion 110 and the power plane portion 120. The plurality of power vias 160 extend from the first surface 111 of the signal plane portion 110 to the fourth surface 124 of the power plane portion 120 facing away from the signal plane portion 110. The radial dimension of each of the plurality of signal vias 161 is smaller than the radial dimension of each of the plurality of power vias 160.

[0048] In some embodiments, the signal plane portion 110 is formed in a first lamination process, the power plane portion 120 is formed in a second lamination process, and the signal plane portion 110 and the power plane portion 120 are stacked together via the connection layer 130 in a third lamination process.

[0049] In some embodiments, forming the signal plane portion 110 further includes forming a plurality of capacitive loading pads 180 in the plurality of metal layers 140 of the signal plane portion 110, as shown in Figures 4A and 4B. The plurality of capacitive loading pads 180 is configured to be electrically connected to at least a portion of the plurality of signal vias 161.

[0050] In some embodiments, at least one pair of adjacent signal vias 161 among the multiple signal vias 161 are respectively connected to at least two capacitive load pads 180 among the multiple capacitive load pads 180, each pair of adjacent signal vias 161 in the at least one pair of adjacent signal vias 161 includes a first signal via 1611 and a second signal via 1612, and at least two capacitive load pads 180 connected to the first signal via 1611 are offset in a direction away from the corresponding second signal via 1612, and at least two capacitive load pads 180 connected to the second signal via 1612 are offset in a direction away from the corresponding first signal via 1611.

[0051] In some embodiments, each capacitive load pad 180 of the plurality of capacitive load pads 180 is elliptical, wherein each of the at least two capacitive load pads 180 connected to the first signal via 1611 has a first end and a second end along the long axis direction, the first end is closer to the second signal via 1612 than the second end, and the first end is closer to the first signal via 1611 than the second end, and wherein each of the at least two capacitive load pads 180 connected to the second signal via 1612 has a third end and a fourth end along the long axis direction, the third end is closer to the first signal via 1611 than the fourth end, and the third end is closer to the second signal via 1612 than the fourth end.

[0052] Embodiments of the present disclosure are also embodied in the following examples.

[0053] Example 1. A printed circuit board comprising:

[0054] A signal plane portion, comprising a plurality of metal layers for transmitting signals;

[0055] a power plane portion, overlapping the signal plane portion through a connection layer and comprising a plurality of metal layers for providing power;

[0056] a plurality of power vias, each extending from a surface of the signal plane portion facing away from the power plane portion, through the signal plane portion, the connection layer and the power plane portion, to a surface of the power plane portion facing away from the signal plane portion; and

[0057] A plurality of signal vias each extend from a surface of the signal plane portion facing away from the power plane portion into the signal plane portion and do not extend into the power plane portion, wherein a radial dimension of each of the plurality of signal vias is smaller than a radial dimension of each of the plurality of power vias.

[0058] Example 2. The printed circuit board according to Example 1, wherein the signal plane portion is formed in a first lamination process, the power plane portion is formed in a second lamination process, and the signal plane portion and the power plane portion are stacked together via the connection layer in a third lamination process, and

[0059] The plurality of signal vias are formed in the power plane portion after the first lamination process and before the third lamination process, and the plurality of power vias are formed in the signal plane portion and the power plane portion after the third lamination process.

[0060] Example 3. A printed circuit board according to Example 1, wherein at least one of the plurality of signal vias extends from a surface of the signal plane portion facing away from the power plane portion to a metal layer adjacent to the connection layer among the plurality of metal layers of the signal plane portion.

[0061] Example 4. The printed circuit board of any one of Examples 1 to 3, further comprising:

[0062] A plurality of capacitive load pads are formed in the plurality of metal layers of the signal plane portion and are electrically connected to at least a portion of the plurality of signal vias.

[0063] Example 5. A printed circuit board according to Example 4, wherein at least one pair of adjacent signal vias among the plurality of signal vias is respectively connected to at least two capacitive load pads among the plurality of capacitive load pads, each pair of adjacent signal vias among the at least one pair of adjacent signal vias includes a first signal via and a second signal via, the at least two capacitive load pads connected to the first signal via are offset in a direction away from the corresponding second signal via, and the at least two capacitive load pads connected to the second signal via are offset in a direction away from the corresponding first signal via.

[0064] Example 6. The printed circuit board of Example 5, wherein each of the plurality of capacitive loading pads is elliptical in shape,

[0065] wherein each of the at least two capacitive load pads connected to the first signal via has a first end and a second end along a long axis direction, the first end being closer to the second signal via than the second end, and the first end being closer to the first signal via than the second end, and

[0066] Each of the at least two capacitive load pads connected to the second signal via has a third end and a fourth end along the long axis direction, the third end is closer to the first signal via than the fourth end, and the third end is closer to the second signal via than the fourth end.

[0067] Example 7. A method for manufacturing a printed circuit board, comprising:

[0068] forming a signal plane portion, the signal plane portion including a plurality of metal layers for transmitting signals;

[0069] forming a plurality of signal vias in the signal plane portion, wherein the plurality of signal vias extend from a surface of the signal plane portion into the signal plane portion respectively;

[0070] forming a power plane portion, the power plane portion including a plurality of metal layers for providing power;

[0071] overlapping the power plane portion and the signal plane portion through a connection layer, wherein the surface of the signal plane portion faces away from the power plane portion; and

[0072] A plurality of power vias are formed in the signal plane portion and the power plane portion, and the plurality of power vias extend from the surface of the signal plane portion to the surface of the power plane portion facing away from the signal plane portion, respectively, wherein a radial dimension of each of the plurality of signal vias is smaller than a radial dimension of each of the plurality of power vias.

[0073] Example 8. The method according to Example 7, wherein the signal plane portion is formed in a first pressing process, the power plane portion is formed in a second pressing process, and the signal plane portion and the power plane portion are stacked together through the connection layer in a third pressing process.

[0074] Example 9. The method of Example 7, wherein at least one signal via of the plurality of signal vias extends from the surface of the signal plane portion to a metal layer of the plurality of metal layers of the signal plane portion that is adjacent to the connection layer.

[0075] Example 10. A method according to any one of Examples 7 to 9, wherein forming the signal plane portion further comprises forming a plurality of capacitive load pads in the plurality of metal layers of the signal plane portion, the plurality of capacitive load pads being used to electrically connect to at least a portion of the plurality of signal vias.

[0076] Example 11. A method according to Example 10, wherein at least one pair of adjacent signal vias among the multiple signal vias are respectively connected to at least two capacitive load pads among the multiple capacitive load pads, each pair of adjacent signal vias among the at least one pair of adjacent signal vias includes a first signal via and a second signal via, the at least two capacitive load pads connected to the first signal via are offset in a direction away from the corresponding second signal via, and the at least two capacitive load pads connected to the second signal via are offset in a direction away from the corresponding first signal via.

[0077] Example 12. The method of Example 11, wherein each of the plurality of capacitive load pads is elliptical in shape,

[0078] wherein each of the at least two capacitive load pads connected to the first signal via has a first end and a second end along a long axis direction, the first end being closer to the second signal via than the second end, and the first end being closer to the first signal via than the second end, and

[0079] Each of the at least two capacitive load pads connected to the second signal via has a third end and a fourth end along the long axis direction, the third end is closer to the first signal via than the fourth end, and the third end is closer to the second signal via than the fourth end.

[0080] While various embodiments of the present disclosure have been described above, the above descriptions are illustrative, non-exhaustive, and not intended to be limiting of the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments. The terminology used herein is selected to best explain the principles of the embodiments, their practical applications, or technological improvements in the marketplace, or to enable other persons skilled in the art to understand the embodiments disclosed herein.

Claims

1. A printed circuit board (100), comprising: A signal plane portion (110) including a plurality of metal layers (140) for transmitting signals; A power plane portion (120) overlaps the signal plane portion (110) via a connection layer (130) and includes a plurality of metal layers (140) for providing power; a plurality of power vias (160), each extending from a surface of the signal plane portion (110) facing away from the power plane portion (120), through the signal plane portion (110), the connection layer (130) and the power plane portion (120), to a surface of the power plane portion (120) facing away from the signal plane portion (110); as well as A plurality of signal vias (161) each extend from a surface of the signal plane portion (110) facing away from the power plane portion (120) into the signal plane portion (110) and do not extend into the power plane portion (120), wherein a radial dimension of each signal via (161) in the plurality of signal vias (161) is smaller than a radial dimension of each power via (160) in the plurality of power vias (160).

2. The printed circuit board (100) according to claim 1, wherein the signal plane portion (110) is formed in a first lamination process, the power plane portion (120) is formed in a second lamination process, and the signal plane portion (110) and the power plane portion (120) are stacked together via the connection layer (130) in a third lamination process, and The plurality of signal vias (161) are formed in the power plane portion (120) after the first pressing process and before the third pressing process, and the plurality of power vias (160) are formed in the signal plane portion (110) and the power plane portion (120) after the third pressing process.

3. The printed circuit board (100) according to claim 1, wherein at least one signal via (161) among the plurality of signal vias (161) extends from a surface of the signal plane portion (110) facing away from the power plane portion (120) to a metal layer (140) among the plurality of metal layers (140) of the signal plane portion (110) that is adjacent to the connection layer (130).

4. The printed circuit board (100) according to any one of claims 1 to 3, further comprising: A plurality of capacitive load pads (180) are formed in the plurality of metal layers (140) of the signal plane portion (110) and are electrically connected to at least a portion of the plurality of signal vias (161).

5. The printed circuit board (100) according to claim 4, wherein at least one pair of adjacent signal vias (161) among the plurality of signal vias (161) is respectively connected to at least two capacitive load pads (180) among the plurality of capacitive load pads (180), each pair of adjacent signal vias (161) among the at least one pair of adjacent signal vias (161) comprises a first signal via (1611) and a second signal via (1612), the at least two capacitive load pads (180) connected to the first signal via (1611) are offset in a direction away from the corresponding second signal via (1612), and the at least two capacitive load pads (180) connected to the second signal via (1612) are offset in a direction away from the corresponding first signal via (1611).

6. The printed circuit board (100) according to claim 5, wherein each of the plurality of capacitive loading pads (180) is elliptical in shape, wherein each of the at least two capacitive load pads (180) connected to the first signal via (1611) has a first end (181) and a second end (182) along the long axis direction, the first end (181) is closer to the second signal via (1612) than the second end (182), and the first end (181) is closer to the first signal via (1611) than the second end (182), and Each of the at least two capacitive load pads (180) connected to the second signal via (1612) has a third end (183) and a fourth end (184) along the long axis direction, the third end (183) is closer to the first signal via (1611) than the fourth end (184), and the third end (183) is closer to the second signal via (1612) than the fourth end (184).

7. A method for manufacturing a printed circuit board (100), comprising: forming a signal plane portion (110), wherein the signal plane portion (110) includes a plurality of metal layers (140) for transmitting signals; forming a plurality of signal vias (161) in the signal plane portion (110), wherein the plurality of signal vias (161) respectively extend from a surface of the signal plane portion (110) into the signal plane portion (110); forming a power plane portion (120) comprising a plurality of metal layers (140) for providing power; The power plane portion (120) is stacked on the signal plane portion (110) via a connection layer (130), wherein the surface of the signal plane portion (110) faces away from the power plane portion (120); as well as A plurality of power vias (160) are formed in the signal plane portion (110) and the power plane portion (120), wherein the plurality of power vias (160) extend from the surface of the signal plane portion (110) to the surface of the power plane portion (120) facing away from the signal plane portion (110), wherein the radial dimension of each signal via (161) in the plurality of signal vias (161) is smaller than the radial dimension of each power via (160) in the plurality of power vias (160).

8. The method according to claim 7, wherein the signal plane portion (110) is formed in a first pressing process, the power plane portion (120) is formed in a second pressing process, and the signal plane portion (110) and the power plane portion (120) are stacked together through the connection layer (130) in a third pressing process.

9. The method according to claim 7, wherein at least one signal via (161) of the plurality of signal vias (161) extends from the surface of the signal plane portion (110) to a metal layer (140) adjacent to the connection layer (130) among the plurality of metal layers (140) of the signal plane portion (110).

10. The method according to any one of claims 7 to 9, wherein forming the signal plane portion (110) further comprises forming a plurality of capacitive load pads (180) in the plurality of metal layers (140) of the signal plane portion (110), the plurality of capacitive load pads (180) being used to electrically connect to at least a portion of the plurality of signal vias (161).

11. The method according to claim 10, wherein at least one pair of adjacent signal vias (161) among the plurality of signal vias (161) is respectively connected to at least two capacitive load pads (180) among the plurality of capacitive load pads (180), each pair of adjacent signal vias (161) among the at least one pair of adjacent signal vias (161) comprises a first signal via (1611) and a second signal via (1612), the at least two capacitive load pads (180) connected to the first signal via (1611) are offset in a direction away from the corresponding second signal via (1612), and the at least two capacitive load pads (180) connected to the second signal via (1612) are offset in a direction away from the corresponding first signal via (1611).

12. The method of claim 11, wherein each of the plurality of capacitive loading pads (180) is elliptical in shape, wherein each of the at least two capacitive load pads (180) connected to the first signal via (1611) has a first end (181) and a second end (182) along the long axis direction, the first end (181) is closer to the second signal via (1612) than the second end (182), and the first end (181) is closer to the first signal via (1611) than the second end (182), and Each of the at least two capacitive load pads (180) connected to the second signal via (1612) has a third end (183) and a fourth end (184) along the long axis direction, the third end (183) is closer to the first signal via (1611) than the fourth end (184), and the third end (183) is closer to the second signal via (1612) than the fourth end (184).

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