Display substrate and display device

Abstract

A display substrate and a display device. The display substrate comprises a base substrate, a plurality of sub-pixels (Pxij), a plurality of data lines (24), a plurality of first contact pads (25), a plurality of second contact pads (26), a plurality of connecting wires (27), an organic protection layer, and an inorganic protection layer; at least one groove (28) is formed in the organic protection layer; the inorganic protection layer is located on the side of the organic protection layer away from the base substrate and covers the at least one groove (28); and the inorganic protection layer is in direct contact with at least one of the plurality of connecting wires (27) by means of the at least one groove (28). According to the display substrate and the display device of the present disclosure, the grooving design of the organic protection layer is used to reduce the size of the organic protection layer in a first frame area, the continuous and large-area organic protection layer is prevented from being divided into a plurality of units, and the groove (28) can also directly isolate water vapor.

Description

Display substrate and display device

[0001] This application claims priority to the Chinese patent application filed on March 29, 2024, with application number 202410383186.7 and invention name “Display Substrate and Display Device”, the content of which should be understood as incorporated into this application by reference. Technical Field

[0002] The present disclosure relates to, but is not limited to, the field of display devices, and in particular to a display substrate and a display apparatus. Background Art

[0003] Organic Light Emitting Diode (OLED) is an active light-emitting display device. Depending on the driving method, OLED can be divided into two types: Passive Matrix (PM) and Active Matrix (AM). AMOLED is a current-driven device that uses independent thin-film transistors (TFTs) to control each sub-pixel. Each sub-pixel can be driven continuously and independently to emit light.

[0004] To ensure that AMOLED display panels can display normally under various complex conditions, we conduct reliability tests on the panels in various environments, such as high pressure, high temperature, and high humidity. Currently, the stability of the film structure of AMOLED display panels is not ideal, and reliability issues exist. Summary of the Invention

[0005] The following is a summary of the subject matter described in detail herein. This summary is not intended to limit the scope of the claims.

[0006] At least one embodiment of the present disclosure provides a display substrate, including a base substrate, the base substrate including a display area and a first frame area located on at least one side of the display area, the first frame area including a first binding area and a second binding area, the second binding area being located on a side of the first binding area away from the display area;

[0007] A plurality of sub-pixels are located on one side of the base substrate and in the display area;

[0008] a plurality of data lines, located in the display area and the first frame area, the plurality of data lines being electrically connected to the plurality of sub-pixels;

[0009] a plurality of first contact pads located in the first binding area, the plurality of first contact pads being configured to be bound to a driver chip, the plurality of first contact pads comprising at least one row of first input contact pads and at least one row of first output contact pads, the at least one row of first input contact pads being located on a side of the at least one row of first output contact pads away from the display area, the plurality of data lines being electrically connected to the at least one row of first output contact pads;

[0010] a plurality of second contact pads located in the second binding area, wherein the plurality of second contact pads are configured to be bound to the circuit board;

[0011] a plurality of connection lines located between the at least one row of first input contact pads and the plurality of second contact pads, the plurality of connection lines being configured to connect the at least one row of first input contact pads and the plurality of second contact pads;

[0012] an organic protective layer, located on a side of the plurality of connection lines away from the base substrate, the organic protective layer being provided with at least one groove, the groove penetrating the organic protective layer in a direction perpendicular to the base substrate;

[0013] The inorganic protective layer is located on a side of the organic protective layer away from the base substrate and covers the at least one groove. The inorganic protective layer is in direct contact with at least one connecting line among the plurality of connecting lines through the at least one groove.

[0014] In some exemplary embodiments, an extension direction of the at least one groove intersects an extension direction of the plurality of connecting lines, and an orthographic projection of the at least one groove on the substrate overlaps with an orthographic projection of the plurality of connecting lines on the substrate.

[0015] The inorganic protection layer is in direct contact with the plurality of connection lines through the at least one groove.

[0016] In some exemplary embodiments, the at least one groove includes a first groove and a second groove, and the second groove is located on a side of the first groove away from the display area.

[0017] In some exemplary embodiments, the organic protective layer includes a plurality of protective units, the plurality of protective units are located in the first border area and are arranged sequentially in a direction away from the display area, and the at least one groove is configured to separate two adjacent protective units among the plurality of protective units.

[0018] In some exemplary embodiments, at least one of the plurality of protection units includes a first body, a surface of the first body close to the groove is an inclined surface, and the inclined surface is inclined toward one side of the groove.

[0019] In some exemplary embodiments, the slope angle of the inclined surface is set to α, 5°≤α≤45°.

[0020] In some exemplary embodiments, the inclined surface is configured as an arc-shaped surface, and the arc-shaped surface is configured to protrude toward a side away from the base substrate.

[0021] In some exemplary embodiments, at least one of the protection units further includes a second body, the first body is located on a side of the second body close to the groove, and a thickness of the first body is less than or equal to a thickness of the second body.

[0022] In some exemplary embodiments, the first input contact pad and the second contact pad are arranged in a one-to-one correspondence and are connected via one connecting line; or,

[0023] One of the first input contact pads is connected to a plurality of the second contact pads via one of the connecting lines; or,

[0024] A plurality of the first input contact pads are connected to one of the second contact pads via one of the connecting lines; or,

[0025] A plurality of the first input contact pads are connected to a plurality of the second contact pads via one connecting line.

[0026] In some exemplary embodiments, at least one of the plurality of connection lines includes a first metal line and a second metal line, the second metal line is located on a side of the first metal line away from the substrate, and the first metal line and the second metal line are in direct contact and electrically connected.

[0027] In some exemplary embodiments, the display substrate includes a circuit structure layer and a light emitting structure layer sequentially arranged in a direction away from the base substrate;

[0028] At least one sub-pixel among the plurality of sub-pixels includes a pixel circuit, a first switching electrode, and a light-emitting element, wherein the pixel circuit and the first switching electrode are located in the circuit structure layer, the light-emitting element is located in the light-emitting structure layer, and the pixel circuit is electrically connected to the light-emitting element through the first switching electrode;

[0029] The circuit structure layer further includes a first flat layer and a second flat layer, wherein the first flat layer is located on a side of the first switching electrode close to the base substrate, and the second flat layer is located on a side of the first switching electrode away from the base substrate;

[0030] The organic protection layer and the second planar layer are located on the same layer and are made of the same material.

[0031] In some exemplary embodiments, the display substrate further comprises a touch structure layer located on a side of the light-emitting structure layer away from the base substrate, the touch structure layer comprising a first touch conductive layer, a touch interlayer insulating layer, and a second touch conductive layer sequentially arranged away from the base substrate;

[0032] The inorganic protection layer and the touch interlayer insulating layer are located on the same layer.

[0033] In some exemplary embodiments, the pixel circuit includes a transistor, the transistor including an active layer, a gate located on a side of the active layer away from the substrate, and a source and a drain located on a side of the gate away from the substrate, and the first transfer electrode is located on a side of the source and the drain away from the substrate;

[0034] The connecting line includes a first metal line and a second metal line that are stacked, the first metal line and the source or the drain are located in the same layer, and the second metal line and the first transfer electrode are located in the same layer.

[0035] In some exemplary embodiments, at least one sub-pixel among the plurality of sub-pixels includes a second switching electrode, and the first switching electrode is located on a side of the second switching electrode close to the base substrate;

[0036] The connecting wire includes a first metal wire and a second metal wire that are stacked. The first metal wire and the first switching electrode are located in the same layer, and the second metal wire and the second switching electrode are located in the same layer.

[0037] At least one embodiment of the present disclosure provides a display device including the above-mentioned display substrate.

[0038] Still other aspects will become apparent upon reading and understanding the accompanying drawings and detailed description.

[0039] Summary of the Figures

[0040] The accompanying drawings are used to provide an understanding of the technical solution of the present disclosure and constitute a part of the specification. Together with the embodiments of the present disclosure, they are used to explain the technical solution of the present disclosure and do not constitute a limitation to the technical solution of the present disclosure.

[0041] FIG1 is a schematic structural diagram of a display device;

[0042] FIG2 is a schematic diagram of a planar structure of a display substrate;

[0043] FIG3 is a schematic cross-sectional view taken along line AA in FIG2 ;

[0044] FIG4 is a schematic diagram of a display substrate according to this exemplary embodiment;

[0045] FIG5 is a schematic cross-sectional view taken along line BB in FIG4 ;

[0046] FIG6 is a partial enlarged schematic diagram of point C in FIG4 ;

[0047] FIG7 is a partial enlarged schematic diagram of point D in FIG5 .

[0048] DESCRIPTION OF NUMERALS: 10 - substrate; 20 - circuit structure layer; 30 - light-emitting structure layer; 40 - packaging structure layer; 50 - touch structure layer; 60 - color filter layer; 101 - first gate insulating layer; 102 - second gate insulating layer; 103 - interlayer insulating layer; 104 - passivation layer; 105 - first planarizing layer; 106 - second planarizing layer; 107 - third planarizing layer; 21 - thin film transistor; 210 - active layer; 211 - source electrode; 212 - drain electrode; 213 - gate electrode; 2100 - channel region; 2101 - first region; 2102 - second region; 22 - capacitor; 221 - first plate; 222 - second plate; 231 - first transfer electrode; 232 - second transfer electrode; 232 - second transfer electrode; 301 - First electrode; 302 - Organic light-emitting layer; 303 - Second electrode; 304 - Pixel definition layer; 401 - First encapsulation layer; 402 - Second encapsulation layer; 403 - Third encapsulation layer; 501 - Touch buffer layer; 502 - Touch interlayer insulating layer; 511 - First touch conductive layer; 512 - Second touch conductive layer; 601 - Color filter buffer layer; 602 - Color filter protective layer; 610 - Black matrix; 611 - Filter unit; 24 - Data line; 25 - First contact pad; 251 - First input contact pad; 252 - First output contact pad; 26 - Second contact pad; 27 - Connecting line; 271 - First metal line; 272 - Second metal line; 28 - Groove; 281 - First groove; 282 - Second groove; 29 - Organic protective layer;291 - protection unit; 292 - first body; 293 - second body; 294 - first protection unit; 295 - second protection unit; 296 - third protection unit; 297 - inclined surface; 31 - inorganic protection layer; 108 - semiconductor layer; 109 - first gate metal layer; 110 - second gate metal layer; 111 - first source / drain metal layer; 112 - second source / drain metal layer; 113 - third source / drain metal layer.

[0049] Details

[0050] In order to make the purpose, technical solutions and advantages of the present disclosure clearer, the embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. Note that the embodiments can be implemented in a variety of different forms. A person of ordinary skill in the art can easily understand the fact that the methods and contents can be transformed into various forms without departing from the purpose and scope of the present disclosure. Therefore, the present disclosure should not be interpreted as being limited to the contents described in the following embodiments. In the absence of conflict, the embodiments in the present disclosure and the features in the embodiments can be arbitrarily combined with each other.

[0051] The scales of the figures in this disclosure can be used as a reference for actual processes, but are not limited to this. For example, the width-to-length ratio of the channel, the thickness and spacing of each film layer, and the width and spacing of each signal line can be adjusted according to actual needs. The number of pixels in the display panel and the number of sub-pixels in each pixel are not limited to the numbers shown in the figures. The figures described in this disclosure are only structural schematics, and one embodiment of the present disclosure is not limited to the shapes or values ​​shown in the figures.

[0052] In this specification, ordinal numbers such as “first”, “second” and “third” are provided to avoid confusion among constituent elements, and are not intended to limit the number.

[0053] In this specification, for convenience, words and phrases indicating orientation or positional relationships, such as "middle," "upper," "lower," "front," "back," "vertical," "horizontal," "top," "bottom," "inside," and "outside," are used to illustrate the positional relationships of constituent elements with reference to the accompanying drawings. This is merely for the purpose of facilitating the description of this specification and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed, or operate in a specific orientation. Therefore, they should not be construed as limiting the present disclosure. The positional relationships of constituent elements may be appropriately changed depending on the direction in which each constituent element is described. Therefore, the present disclosure is not limited to the words and phrases described in the specification and may be appropriately replaced according to the circumstances.

[0054] In this specification, unless otherwise specified or limited, the terms "mounted," "connected," and "connected" should be understood broadly. For example, they can refer to fixed, removable, or integral connections; mechanical or electrical connections; direct connections, indirect connections through intermediaries, or internal communication between two components. Those skilled in the art will understand the specific meanings of these terms in this disclosure.

[0055] In this specification, a transistor refers to an element that includes at least three terminals: a gate electrode, a drain electrode, and a source electrode. A transistor has a channel region between a drain electrode (drain electrode terminal, drain region, or drain electrode) and a source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. Note that in this specification, the channel region refers to the region through which current primarily flows.

[0056] In this specification, the first electrode can be a drain electrode and the second electrode can be a source electrode, or vice versa. The functions of "source electrode" and "drain electrode" may be interchanged when using transistors with opposite polarity or when the direction of current changes during circuit operation. Therefore, in this specification, "source electrode" and "drain electrode" can be interchanged, and "source terminal" and "drain terminal" can be interchanged.

[0057] In this specification, "electrically connected" includes components connected together via an element having some electrical function. There are no particular limitations on the "element having some electrical function" as long as it enables the transfer of electrical signals between the connected components. Examples of "element having some electrical function" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other components with various functions.

[0058] In this specification, "parallel" refers to a state where the angle formed by two straight lines is greater than -10° and less than 10°, and thus also includes a state where the angle is greater than -5° and less than 5°. Furthermore, "perpendicular" refers to a state where the angle formed by two straight lines is greater than 80° and less than 100°, and thus also includes a state where the angle is greater than 85° and less than 95°.

[0059] In this specification, the terms "film" and "layer" may be interchanged. For example, "conductive layer" may be replaced with "conductive film." Similarly, "insulating film" may be replaced with "insulating layer."

[0060] The triangles, rectangles, trapezoids, pentagons or hexagons in this specification are not in the strict sense, but may be approximate triangles, rectangles, trapezoids, pentagons or hexagons, etc. There may be some small deformations caused by tolerances, and there may be chamfers, arc edges and deformations.

[0061] The term "about" in the embodiments of the present disclosure does not strictly define the limits and allows for numerical values ​​within the range of process and measurement errors.

[0062] Figure 1 is a schematic diagram of the structure of a display device. As shown in Figure 1, the display device may include a timing controller, a data driver, a scan driver, a light-emitting driver, and a pixel array. The timing controller is respectively connected to the data driver, the scan driver, and the light-emitting driver. The data driver is respectively connected to a plurality of data signal lines (D1 to Dn), the scan driver is respectively connected to a plurality of scan signal lines (S1 to Sm), and the light-emitting driver is respectively connected to a plurality of light-emitting signal lines (E1 to Eo). The pixel array may include a plurality of sub-pixels Pxij, where i and j may be natural numbers. At least one sub-pixel Pxij may include a circuit unit and a light-emitting device connected to the circuit unit. The circuit unit may include a pixel driving circuit, and the pixel driving circuit may be connected to the scan signal lines, the light-emitting signal lines, and the data signal lines. In an exemplary embodiment, the timing controller may provide grayscale values ​​and control signals suitable for the specifications of the data driver to the data driver, may provide clock signals, scan start signals, etc. suitable for the specifications of the scan driver to the scan driver, and may provide clock signals, emission stop signals, etc. suitable for the specifications of the light-emitting driver to the light-emitting driver. The data driver can generate data voltages to be supplied to data signal lines D1, D2, D3, ..., and Dn using grayscale values ​​and control signals received from a timing controller. For example, the data driver can sample grayscale values ​​using a clock signal and apply data voltages corresponding to the grayscale values ​​to data signal lines D1 to Dn on a per-row basis, where n can be a natural number. The scan driver can generate scan signals to be supplied to scan signal lines S1, S2, S3, ..., and Sm by receiving clock signals, scan start signals, and the like from the timing controller. For example, the scan driver can sequentially supply scan signals having on-level pulses to scan signal lines S1 to Sm. For example, the scan driver can be configured as a shift register and can sequentially transmit scan start signals provided in the form of on-level pulses to the next-stage circuit under the control of a clock signal, where m can be a natural number. The light driver can generate emission signals to be supplied to light signal lines E1, E2, E3, ..., and Eo by receiving clock signals, emission stop signals, and the like from the timing controller. For example, the light emitting driver may sequentially provide emission signals having off-level pulses to the light emitting signal lines E1 to Eo. For example, the light emitting driver may be configured as a shift register and may generate emission signals by sequentially transmitting emission stop signals provided in the form of off-level pulses to the next stage circuit under the control of a clock signal. o may be a natural number. In an exemplary embodiment, the pixel array may be provided on a display substrate.

[0063] Figure 2 is a schematic diagram of a planar structure of a display substrate. As shown in Figure 2, the display substrate may include a plurality of pixel units P arranged in a matrix, and at least one pixel unit P may include a first sub-pixel P1 that emits a first color light, a second sub-pixel P2 that emits a second color light, and a third sub-pixel P3 that emits a third color light. Each sub-pixel may include a circuit unit and a light-emitting device. The circuit unit may include at least a pixel driving circuit. The pixel driving circuit is respectively connected to a scan signal line, a light-emitting signal line, and a data signal line. The pixel driving circuit is configured to receive a data voltage transmitted by the data signal line under the control of the scan signal line and the light-emitting signal line, and output a corresponding current to the light-emitting device. The light-emitting device in each sub-pixel is respectively connected to the pixel driving circuit of the sub-pixel in which it is located. The light-emitting device is configured to emit light of corresponding brightness in response to the current output by the pixel driving circuit of the sub-pixel in which it is located.

[0064] In an exemplary embodiment, the first subpixel P1 may be a red subpixel (R) that emits red light, the second subpixel P2 may be a blue subpixel (B) that emits blue light, and the third subpixel P3 may be a green subpixel (G) that emits green light. In an exemplary embodiment, the subpixels may be rectangular, diamond-shaped, pentagonal, or hexagonal, and the three subpixels may be arranged horizontally, vertically, or in a triangular pattern, although this disclosure is not limited thereto.

[0065] In an exemplary embodiment, a pixel unit may include four sub-pixels, and the four sub-pixels may be arranged in a horizontal parallel arrangement, a vertical parallel arrangement, or a square arrangement, etc., which is not limited in the present disclosure.

[0066] Figure 3 is a schematic cross-sectional view taken along the AA line in Figure 2. Figure 3 illustrates the structure of a sub-pixel in the display area as an example. In this example, the same type of multiple transistors in the pixel circuit is used as an example for illustration. For example, multiple transistors in the pixel circuit can all use low-temperature polysilicon thin-film transistors or oxide thin-film transistors. In other examples, multiple transistors in the pixel circuit can use low-temperature polysilicon thin-film transistors and oxide thin-film transistors. In addition, this example takes the display panel integrating a mutual capacitance touch structure to form a flexible multi-layer covering surface (Flexible Multi-Layer On Cell, FMLOC for short) structure as an example for illustration.

[0067] In some exemplary embodiments, as shown in FIG3 , in a direction perpendicular to the display panel, the display area of ​​the display panel may include: a base substrate 10, and a circuit structure layer 20, a light-emitting structure layer 30, an encapsulation structure layer 40, a touch structure layer 50, and a color filter layer 60 sequentially disposed on the base substrate 10. The circuit structure layer 20 may include at least: pixel circuits for multiple sub-pixels, each of which may include multiple transistors and at least one capacitor. The light-emitting structure layer 30 may include at least: light-emitting elements for multiple sub-pixels.

[0068] In some exemplary embodiments, as shown in FIG3 , the circuit structure layer 20 in the display region may include: a semiconductor layer 108, a first gate metal layer 109, a second gate metal layer 110, a first source / drain metal layer 111, a second source / drain metal layer 112, and a third source / drain metal layer 113, disposed on a base substrate 10. The first gate metal layer 109, the second gate metal layer 110, the first source / drain metal layer 111, the second source / drain metal layer 112, and the third source / drain metal layer 113 are stacked sequentially in a direction away from the base substrate 10. A first gate insulating layer 101 may be disposed between the semiconductor layer 108 and the first gate metal layer 109, a second gate insulating layer 102 may be disposed between the first gate metal layer 109 and the second gate metal layer 110, an interlayer insulating layer 103 may be disposed between the second gate metal layer 110 and the first source / drain metal layer 111, a passivation layer 104 and a first planarizing layer 105 may be disposed between the first source / drain metal layer 111 and the second source / drain metal layer 112, a second planarizing layer 106 may be disposed between the second source / drain metal layer 112 and the third source / drain metal layer 113, and a third planarizing layer 107 may be disposed on the side of the third source / drain metal layer 113 away from the substrate 10. The first gate insulating layer 101, the second insulating layer 102, the interlayer insulating layer 103, and the passivation layer 104 may be inorganic insulating layers, and the first planarizing layer 105, the second planarizing layer 106, and the third planarizing layer 107 may be organic insulating layers. However, this embodiment is not limited to this. In other examples, a buffer layer may be provided on the side of the semiconductor layer 108 close to the base substrate 10. The buffer layer may prevent harmful substances in the substrate from invading the interior of the display panel and may also increase the adhesion of the film layer in the display panel to the base substrate 10. In other examples, a bottom shielding metal layer (BSM) may be provided on the side of the buffer layer close to the base substrate 10. The bottom shielding metal layer may be configured to at least partially cover the active layer of the thin film transistor of the pixel circuit to prevent external light from affecting the performance of the thin film transistor. In other examples, the passivation layer may be omitted between the first source-drain metal layer 111 and the second source-drain metal layer 112, and only a first flat layer may be provided between the first source-drain metal layer 111 and the second source-drain metal layer 112.

[0069] In some exemplary embodiments, as shown in FIG3 , the semiconductor layer 108 in the display area may include at least an active layer 210 of a thin film transistor 21. The active layer 210 of the thin film transistor 21 may include a first region 2101, a second region 2102, and a channel region 2100 located between the first region 2101 and the second region 2102. The first gate metal layer 109 may include at least a gate electrode 213 of the thin film transistor 21 and a first plate 221 of the capacitor 22. The orthographic projection of the gate electrode 213 of the thin film transistor 21 on the substrate 10 may overlap the orthographic projection of the channel region 2100 of the active layer 210 on the substrate 10. The second gate metal layer 110 may include at least a second plate 222 of the capacitor 22. The orthographic projections of the second plate 222 and the first plate 221 of the capacitor 22 on the substrate 10 may at least partially overlap, for example, they may coincide. The first source / drain metal layer 111 may include at least a source electrode 211 and a drain electrode 212 of the thin film transistor 21. The interlayer insulating layer 103 may have multiple vias (e.g., including a first pixel via and a second pixel via) in the display area. The interlayer insulating layer 103, the second gate insulating layer 102, and the first gate insulating layer 101 within the first pixel via can be removed, exposing at least a portion of the surface of the first region 2101 of the active layer 210. The interlayer insulating layer 103, the second gate insulating layer 102, and the first gate insulating layer 101 within the second pixel via can be removed, exposing at least a portion of the surface of the second region 2102 of the active layer 210. The source electrode 211 of the thin-film transistor 21 may be electrically connected to the first region 2101 of the active layer 210 through the first pixel via, and the drain electrode 212 may be electrically connected to the second region 2102 of the active layer 210 through the second pixel via. The second source-drain metal layer 112 may include at least a first transfer electrode 231. The first transfer electrode 231 can be electrically connected to the drain 212 of the thin-film transistor 21 of the pixel circuit through a third pixel via hole provided in the passivation layer 104 and the first planar layer 105. The third source-drain metal layer 113 can include at least a second transfer electrode 232. The second transfer electrode 232 can be electrically connected to the first transfer electrode 231 located in the second source-drain metal layer 112 through a fourth pixel via hole provided in the second planar layer 106. The second transfer electrode 232 can be electrically connected to the first electrode 301 (e.g., an anode) of the light-emitting element through a fifth pixel via hole provided in the third planar layer 107. In this example, the electrical connection between the pixel circuit and the light-emitting element can be achieved through the first transfer electrode 231 and the second transfer electrode 232.

[0070] In some examples, the gate lines of the display area can be located in the first gate metal layer 109, the data lines of the display area can be located in the second source / drain metal layer 112 or the third source / drain metal layer 113, and the high-potential power lines of the display area can be located in at least one of the second source / drain metal layer 112 and the third source / drain metal layer 113. This embodiment is not limited to this. In this example, the circuit structure layer can include three source / drain metal layers, which can avoid arranging a large number of traces within a single source / drain metal layer, thereby facilitating the realization of a narrow frame structure.

[0071] In some exemplary embodiments, as shown in FIG3 , the light-emitting structure layer 30 may include a pixel definition layer 304 and multiple light-emitting elements. For example, each light-emitting element may include a stacked first electrode 301, an organic light-emitting layer 302, and a second electrode 303. The first electrode 301 of the light-emitting element may be an anode. The first electrode 301 may be disposed on the third planar layer 107 and electrically connected to the second transfer electrode 232 through a fifth pixel via provided in the third planar layer 107. The pixel definition layer 304 is disposed on the first electrode 301 and the third planar layer 107. The pixel definition layer 304 may have multiple pixel openings, each of which may expose at least a portion of the surface of a corresponding first electrode 301. At least a portion of the organic light-emitting layer 302 may be disposed within a pixel opening and connected to the corresponding first electrode 301. The second electrode 303 may be disposed on and connected to the organic light-emitting layer 302. Driven by the first electrode 301 and the second electrode 303, the organic light-emitting layer 302 may emit light of a corresponding color. An isolation column layer may be further provided on a side of the pixel definition layer 304 away from the base substrate 10 . The isolation column layer may include a plurality of isolation columns (PS).

[0072] In some exemplary embodiments, the organic light-emitting layer 302 of the light-emitting element may include an emitting layer (EML), and one or more layers selected from the group consisting of a hole injection layer (HIL), a hole transport layer (HTL), a hole blocking layer (HBL), an electron blocking layer (EBL), an electron injection layer (EIL), and an electron transport layer (ETL). Driven by the voltage of the first electrode 301 and the second electrode 303, the organic material's luminescence characteristics can be utilized to generate light at desired grayscales.

[0073] In some exemplary embodiments, the light-emitting layers of light-emitting elements of different colors may be different. For example, a red light-emitting element includes a red light-emitting layer, a green light-emitting element includes a green light-emitting layer, and a blue light-emitting element includes a blue light-emitting layer. In order to reduce the process difficulty and improve the yield, the hole injection layer and the hole transport layer on one side of the light-emitting layer may adopt a common layer, and the electron injection layer and the electron transport layer on the other side of the light-emitting layer may adopt a common layer. In some examples, any one or more layers of the hole injection layer, the hole transport layer, the electron injection layer and the electron transport layer can be made by a one-time process (a one-time evaporation process or a one-time inkjet printing process), and isolation is achieved by means of a surface step difference of the formed film layer or by surface treatment. For example, any one or more layers of the hole injection layer, the hole transport layer, the electron injection layer and the electron transport layer corresponding to adjacent sub-pixels can be isolated. In some examples, the organic light-emitting layer can be formed by evaporation using a fine metal mask (FMM) or an open mask (Open Mask), or by inkjet technology.

[0074] In some exemplary embodiments, as shown in FIG3 , the encapsulation structure layer 40 may include a stacked first encapsulation layer 401, a second encapsulation layer 402, and a third encapsulation layer 403. The first encapsulation layer 401 and the third encapsulation layer 403 may be made of inorganic materials, and the second encapsulation layer 402 may be made of organic materials. The second encapsulation layer 402 may be disposed between the first encapsulation layer 401 and the third encapsulation layer 403 to prevent external moisture from entering the light-emitting element. However, this embodiment is not limited to this. For example, the encapsulation structure layer may have a five-layer stacked structure of inorganic / organic / inorganic / organic / inorganic.

[0075] In some exemplary embodiments, as shown in FIG3 , the touch structure layer 50 may include: a touch buffer layer (TBL) 501, a first touch conductive layer 511, a touch interlayer insulating layer (TLD) 502, and a second touch conductive layer 512, which are arranged in sequence. The touch buffer layer 501 may be an inorganic insulating layer, and the touch interlayer insulating layer 502 may be an inorganic insulating layer or an organic insulating layer. In this example, by setting the touch interlayer insulating layer 502 as an organic insulating layer, the crack problem generated by the display panel during reliability testing (such as the crack problem generated during the anti-arch test of the foldable display panel) can be improved, thereby improving the display panel's anti-bending ability, which is beneficial to improving the product yield and competitiveness of the display panel.

[0076] Currently, the border area of ​​a display substrate typically has a large, continuous organic protective layer. This continuous organic protective layer results in a thicker film and a larger area. The film thickness of the organic protective layer is the dimension of the organic protective layer perpendicular to the substrate. The applicant discovered that during high-temperature and high-humidity testing, when water vapor intrudes into the organic protective layer, the continuous and thick film makes it difficult for the water vapor to diffuse outward. Instead, the water vapor continues to diffuse upward. Upward diffusion refers to the diffusion of water vapor toward the side away from the substrate, affecting the stability of the film structure, thereby affecting the test results and causing reliability issues.

[0077] Figure 4 is a schematic diagram of a display substrate according to an exemplary embodiment. Figure 5 is a schematic cross-sectional view taken along line BB in Figure 4 . Figure 6 is a partially enlarged schematic diagram of point C in Figure 4 . This exemplary embodiment provides a display substrate. As shown in Figures 4 to 6 , the display substrate may include a base substrate 10, a plurality of sub-pixels Pxij, a plurality of data lines 24, a plurality of first contact pads 25, a plurality of second contact pads 26, a plurality of connection lines 27, an organic protective layer 29, and an inorganic protective layer 31. The base substrate 10 may include a display area AA and a first border region B1 located on at least one side of the display area AA. The first border region B1 may include a first binding region B3 and a second binding region B4. The second binding region B4 may be located on a side of the first binding region B3 away from the display area AA. The plurality of sub-pixels Pxij are located on one side of the base substrate 10 and in the display area AA. The plurality of data lines 24 may be located in the display area AA and the first border region B1. The plurality of data lines 24 may be electrically connected to the plurality of sub-pixels Pxij. A plurality of first contact pads 25 may be located in the first bonding area B3 and configured to be bonded to a driver chip (not shown). The plurality of first contact pads 25 may include at least one row of first input contact pads 251 and at least one row of first output contact pads 252. The at least one row of first input contact pads 251 may be located on a side of the at least one row of first output contact pads 252 away from the display area AA. The plurality of data lines 24 are electrically connected to the at least one row of first output contact pads 252. A plurality of second contact pads 26 may be located in the second bonding area B4 and configured to be bonded to a circuit board (not shown). A plurality of connecting lines 27 may be located between the at least one row of first input contact pads 251 and the plurality of second contact pads 26, connecting the at least one row of first input contact pads 251 to the plurality of second contact pads 26. An organic protective layer 29 may be located on a side of the plurality of connecting lines 27 away from the base substrate 10. The organic protective layer 29 may have at least one groove 28 formed therein. The groove 28 may extend through the organic protective layer 29 in a direction perpendicular to the base substrate. The inorganic protective layer 31 can be located on a side of the organic protective layer 29 away from the base substrate 10 and cover at least one groove 28. The inorganic protective layer 31 directly contacts at least one of the plurality of connecting lines 27 through the at least one groove 28. Thus, the display substrate of this example, by providing the groove 28 in the organic protective layer 29 in the first border region B1, can directly block the diffusion of water vapor and reduce the thickness of the organic protective layer 29, avoiding a large continuous area of ​​the organic protective layer. This makes it difficult for water vapor to diffuse upward and affect the stability of the organic protective layer 29, thereby preventing the organic protective layer 29 and the inorganic protective layer 31 from peeling off.

[0078] In some exemplary embodiments, as shown in Figures 4 to 6, the base substrate 10 may include a display area AA and a border area BB located around the display area AA. The border area BB may include a first border region B1 located on one side of the display area AA and a second border region B2 located on the remaining sides of the display area AA. For example, the first border region B1 may include the bottom border of the array substrate, and the second border region B2 may include the top, left, and right borders of the display substrate. The first border area B1 is located on one side of the display area AA in the first direction (Y direction), and the first direction (Y direction) is parallel to the base substrate 10. The first border area B1 may include a first binding area B3 and a second binding area B4. The second binding area B4 may be located on the side of the first binding area B3 away from the display area AA in the first direction (Y direction). The first binding area B3 may be a chip binding area, and the second binding area B4 may be a circuit board binding area. The driver chip (Display driver IC, DIC for short) can be bound to the first binding area B3 on the display substrate through a COP (Chip On Pi) process, and the flexible printed circuit (FPC for short) can be bound to the second binding area B4 on the display substrate through an FOP (FPC On COPBonding) process.

[0079] In some exemplary embodiments, as shown in Figures 4 to 6, the base substrate 10 may be a flexible substrate, which may be, but is not limited to, one or more of polyethylene terephthalate, polyethylene terephthalate, polyetheretherketone, polystyrene, polycarbonate, polyarylate, polyarylate, polyimide, polyvinyl chloride, polyethylene, and textile fibers.

[0080] In some exemplary embodiments, as shown in Figures 4 to 6, the plurality of first contact pads 25 may include at least one row of first input contact pads 251 and at least one row of first output contact pads 252. The at least one row of first input contact pads 251 may be located on a side of the at least one row of first output contact pads 252 away from the display area AA. In this example, the plurality of first output contact pads 252 may be arranged in three rows, with the plurality of first output contact pads 252 in a row spaced apart along a second direction (X direction), which is perpendicular to the first direction (Y direction) and parallel to the base substrate 10. The plurality of data lines 24 extend from the display area AA to the first binding area B3 and are electrically connected to the plurality of first output contact pads 252. In this example, the plurality of first input contact pads 251 may be arranged in a row, with the plurality of first input contact pads 251 in a row spaced apart along the second direction (X direction). In this example, there are a plurality of second contact pads 26, and the plurality of second contact pads 26 may be arranged in a row, with the plurality of second contact pads 26 in a row spaced apart along the second direction (X direction).

[0081] In some exemplary embodiments, as shown in Figures 4 to 6, multiple connection lines 27 may be located between the first input contact pads 251 and the second contact pads 26. The multiple connection lines 27 may connect at least one row of first input contact pads 251 and a plurality of second contact pads 26. In this example, the number of first input contact pads 251 and second contact pads 26 is the same, forming a one-to-one correspondence. Corresponding first input contact pads 251 and second contact pads 26 are connected by a connection line 27, i.e., one end of the connection line 27 is connected to one first input contact pad 251, and the other end of the connection line 27 is connected to one corresponding second contact pad 26. For example, the number of first input contact pads 251, second contact pads 26, and connection lines 27 is all a, and the two ends of each connection line 27 are respectively connected to one first input contact pad 251 and one second contact pad 26. But not limited to this, for example, a first input contact pad 251 can be connected to multiple second contact pads 26 through a connecting line 27; for another example, multiple first input contact pads 251 can be connected to one second contact pad 26 through a connecting line 27; for another example, multiple first input contact pads 251 can be connected to multiple second contact pads 26 through a connecting line 27.

[0082] FIG7 is a partial enlarged schematic diagram of point D in FIG5 . In some exemplary embodiments, as shown in FIG3 , FIG5 , FIG6 , and FIG7 , at least one of the plurality of connecting lines 27 includes a first metal line 271 and a second metal line 272 . The second metal line 272 is located on a side of the first metal line 271 away from the base substrate 10 . The first metal line 271 and the second metal line 272 are in direct contact and electrically connected. The display substrate may include a circuit structure layer 20 and a light emitting structure layer 30 , which are sequentially arranged away from the base substrate 10 . The sub-pixel Pxij includes a pixel circuit, a first transfer electrode 231 , a second transfer electrode 232 , and a light emitting element. The pixel circuit, the first transfer electrode 231 , and the second transfer electrode 232 may be located in the circuit structure layer 20 , and the light emitting element is located in the light emitting structure layer 30 . The pixel circuit is electrically connected to the light emitting element via the first transfer electrode 231 and the second transfer electrode 232 . The first transfer electrode 231 is located on a side of the second transfer electrode 232 that is closer to the base substrate 10 . The pixel circuit includes a thin film transistor 21, which includes an active layer 210, a gate 213 located on the side of the active layer 210 away from the substrate 10, and a source 211 and a drain 212 located on the side of the gate 213 away from the substrate 10. A first transfer electrode 231 is located on the side of the source 211 and drain 212 away from the substrate 10. A first metal line 271 can be located on the same layer as the source 211 and drain 212, that is, both are located in the first source-drain metal layer 111, and the first metal line 271 can be made of the same material as the source 211 and drain 212. A second metal line 272 can be located on the same layer as the first transfer electrode 231, that is, both are located in the second source-drain metal layer 112, and the second metal line 272 can be made of the same material as the first transfer electrode 231.

[0083] In some exemplary embodiments, as shown in Figures 3, 5, 6, and 7, at least one of the plurality of connection lines 27 includes a first metal line 271 and a second metal line 272. The second metal line 272 is located on a side of the first metal line 271 away from the base substrate 10. The first metal line 271 and the second metal line 272 are in direct contact and electrically connected. The display substrate may include a circuit structure layer 20 and a light-emitting structure layer 30, which are sequentially arranged away from the base substrate 10. The sub-pixel Pxij includes a pixel circuit, a first transfer electrode 231, a second transfer electrode 232, and a light-emitting element. The first transfer electrode 231 and the second transfer electrode 232 may be located in the circuit structure layer 20, and the light-emitting element is located in the light-emitting structure layer 30. The pixel circuit is electrically connected to the light-emitting element via the first transfer electrode 231 and the second transfer electrode 232. The first transfer electrode 231 is located on a side of the second transfer electrode 232 closer to the base substrate 10. The first metal wire 271 and the first transfer electrode 231 are located in the same layer, that is, both are in the second source-drain metal layer 112, and the first metal wire 271 can be made of the same material as the first transfer electrode 231; the second metal wire 272 and the second transfer electrode 232 are located in the same layer, that is, both are in the third source-drain metal layer 113, and the second metal wire 272 and the second transfer electrode 232 are made of the same material.

[0084] In some exemplary embodiments, the first metal wire 271 may be located in the same layer as the source 211 and the drain 212, that is, they are all in the first source-drain metal layer 111, and the first metal wire 271 may be made of the same material as the source 211 and the drain 212; the second metal wire 272 and the second transfer electrode 232 are located in the same layer, that is, they are all in the third source-drain metal layer 113, and the second metal wire 272 and the second transfer electrode 232 are made of the same material.

[0085] In some exemplary embodiments, at least one connecting line 27 among the multiple connecting lines 27 includes a first metal line 271 and a second metal line 272, and the first metal line 271 and the second metal line 272 may be located in any two layers of the first gate metal layer 109, the second gate metal layer 110, the first source-drain metal layer 111, the second source-drain metal layer 112 and the third source-drain metal layer 113.

[0086] In some exemplary embodiments, as shown in Figures 3 to 6, a sub-pixel Pxij includes a pixel circuit, a first transfer electrode 231, a second transfer electrode 232, and a light-emitting element. The pixel circuit is electrically connected to the light-emitting element via the first transfer electrode 231 and the second transfer electrode 232. The circuit structure layer 20 also includes a first planar layer 105, a second planar layer 106, and a third planar layer 107. The first planar layer 105 is located on the side of the first transfer electrode 231 closer to the base substrate 10, the second planar layer 106 is located on the side of the first transfer electrode 231 farther from the base substrate 10, and the third planar layer 107 is located on the side of the second transfer electrode 232 farther from the base substrate 10. The pixel circuit is electrically connected to the first transfer electrode 231 through a via in the first planar layer 105. The first transfer electrode 231 is electrically connected to the second transfer electrode 232 through a via in the second planar layer 106. The second transfer electrode 232 is electrically connected to the anode (first electrode 301) of the light-emitting element through a via in the third planar layer 107. In this example, the organic protection layer 29 may be located on the same layer as the second planar layer 106 and made of the same material, but is not limited thereto. For example, the organic protection layer 29 may be located on the same layer as the third planar layer 107 and made of the same material.

[0087] In some exemplary embodiments, as shown in Figures 5 and 7, the depth direction of the groove 28 is consistent with the third direction, the third direction is perpendicular to the base substrate 10, the groove 28 penetrates the organic protective layer 29 in the third direction, the notch of the groove 28 is located at the end of the groove 28 away from the base substrate 10, and the bottom of the groove 28 is located at the end of the organic protective layer 29 close to the base substrate 10, so that the groove 28 can extend in the third direction to the end of the connecting line 27 away from the base substrate 10, exposing the connecting line 27.

[0088] In some exemplary embodiments, as shown in FIG5 and FIG7 , a plurality of grooves 28 may be provided. The grooves 28 may be elongated grooves extending along a straight line, but are not limited thereto. For example, the grooves 28 may be circular grooves, diamond grooves, fan-shaped grooves, etc. In this example, the plurality of grooves 28 are elongated grooves extending along a straight line and are parallel to each other. The grooves 28 are arranged to extend along a second direction (X direction). The second direction (X direction) may be arranged to intersect with the first direction (Y direction), and the second direction (X direction) is parallel to the substrate 10. In this example, the second direction (X direction) is perpendicular to the first direction (Y direction), that is, the extending direction of the grooves 28 is perpendicular to the first direction (Y direction). However, the embodiment of the present invention is not limited thereto. For example, the plurality of grooves 28 may not be parallel, but the plurality of grooves 28 do not intersect. For another example, the plurality of grooves 28 may be parallel to each other, and the grooves 28 may be arranged to extend along the second direction (X direction). The second direction (X direction) and the first direction (Y direction) intersect, but the second direction (X direction) and the first direction (Y direction) are not perpendicular. The groove 28 extending along the second direction (X direction) may intersect all the connecting lines 27, so that the projection of the groove 28 on the base substrate 10 overlaps with the projection of all the connecting lines 27 on the base substrate 10. In this example, the number of grooves 28 may be two, and the two grooves 28 are arranged at intervals in the first direction (Y direction). The two grooves 28 may divide the organic protective layer 29 located in the first border area B1 into three protective units 291, but the present invention is not limited thereto. For example, the number of grooves 28 may be one, and the organic protective layer 29 located in the first border area B1 may be divided into two protective units 291; for another example, the number of grooves 28 may be three, and the organic protective layer 29 located in the first border area B1 may be divided into four protective units 291; the number of grooves 28 may be five, and the organic protective layer 29 located in the first border area B1 may be divided into six protective units 291.

[0089] In some exemplary embodiments, as shown in Figures 5 and 7, at least one protective unit 291 may include a first body 292. The surface of the first body 292 adjacent to the groove 28 is an inclined surface 297. The inclined surface 297 is inclined toward the side facing away from the groove 28 in the first direction (the Y direction), and the inclined surface 297 forms a groove sidewall of the groove 28. As a result, the groove 28 may have a larger opening at one end and a smaller opening at the other end. The bottom of the groove 28 (i.e., the end of the groove 28 closer to the base substrate 10 in the third direction) is smaller in the first direction than the groove opening of the groove 28 (i.e., the end of the groove 28 farther from the base substrate 10 in the third direction), forming a trumpet-shaped groove. The third direction is perpendicular to the base substrate 10.

[0090] In some exemplary embodiments, as shown in FIG5 and FIG7 , the inclined surface 297 is configured as an arcuate surface, and the arcuate surface is configured to protrude toward a side away from the base substrate 10. The slope angle of the inclined surface 297 is set to α, where 5°≤α≤45°. Because the inclined surface 297 is an arcuate surface, the slope angle at each position on the inclined surface 297 is different. In this example, the slope angle of the inclined surface 297 can be the angle between a tangent line at a point on the inclined surface 297 and a plane parallel to the base substrate 10. For example, the slope angle of point A on the inclined surface 297 is α1, the tangent of the inclined surface 297 passing through point A is L1, and the angle between the tangent L1 and the plane parallel to the base substrate 10 is α1; for another example, the slope angle of point B on the inclined surface 297 is α2, the tangent of the inclined surface 297 passing through point B is L2, and the angle between the tangent L2 and the plane parallel to the base substrate 10 is α2; the slope angle of point C on the inclined surface 297 is α3, the tangent of the inclined surface 297 passing through point C is L3, and the angle between the tangent L3 and the plane parallel to the base substrate 10 is α3; wherein the angles α1, α2, and α3 are all within the range of 5° to 45°, so that the slope angle of the inclined surface 297 is relatively small.

[0091] In some exemplary embodiments, as shown in Figures 5 and 7, at least one protective unit 291 may further include a second body 293. The first body 292 is located on a side of the second body 293 in the first direction (Y direction) that is closer to the groove 28. The first body 292 and the second body 293 are made of the same material. The thickness of the first body 292 is the dimension of the first body 292 in the third direction, and the thickness of the second body 293 is the dimension of the second body 293 in the third direction. The thickness of the first body 292 is greater than or equal to the thickness of the second body 293. The ratio of the maximum dimension of the second body 293 in the third direction to the maximum dimension of the first body 292 in the third direction may be 1 to 1.5.

[0092] In some exemplary embodiments, as shown in Figures 5 and 7, three protective units 291 include a first protective unit 294, a second protective unit 295, and a third protective unit 296, wherein the first protective unit 294, the second protective unit 295, and the third protective unit 296 are arranged sequentially in the first direction (Y direction). A groove 28 is provided between the first protective unit 294 and the second protective unit 295, and between the second protective unit 295 and the third protective unit 296, so that the first protective unit 294 and the second protective unit 295 are separated, and the second protective unit 295 and the third protective unit 296 are separated. The two grooves 28 include a first groove 281 and a second groove 282. The first groove 281 is located between the second protective unit 295 and the third protective unit 296, and the second groove 282 is located between the first protective unit 294 and the second protective unit 295. The second groove 282 is located on the side of the first groove 281 away from the display area. The first protective unit 294 is located on the side of the second protective unit 295 away from the display area AA, and the third protective unit 296 is located on the side of the second protective unit 295 closer to the display area AA. The first protective unit 294 includes a second body 293 and two first bodies 292 located on either side of the second body 293. The second protective unit 13 also includes a second body 293 and two first bodies 292 located on either side of the second body 293. The third protective unit 296 includes a first body 292, so that the groove 8 is sandwiched between the two first bodies 292. The two grooves 28, the plurality of first bodies 292, and the plurality of second bodies 293 in the organic protective layer 29 in the frame area can be arranged in a first order: first body 292, groove 28, first body 292, second body 293, first body 292, groove 28, first body 292, second body 293, and first body 292, arranged in sequence in the first direction (Y direction).

[0093] In some exemplary embodiments, as shown in Figures 5 and 7, the organic protective layer 29 can be formed using a half-tone process. That is, after forming the connecting line 27, a layer of insulating film can be covered on the connecting line 27 and the base substrate 10, and then the groove 28 and the inclined surface 297 can be formed using the half-tone process. The half-tone process is a key technology used in display devices. It can control the exposure level of the photoresist (PR) by using a semi-transparent area. It improves the image quality and color performance by precisely controlling the exposure and etching process. Therefore, the display substrate of this example adopts a groove design of the organic protective layer 29 (i.e., providing grooves 28), which reduces the volume of the organic protective layer 29 and avoids a continuous and large area of ​​the organic protective layer 29. It is divided into multiple units. At the same time, the grooves 28 can also directly isolate water vapor. Secondly, a half-tone process forms an inclined surface at the edge of the protective unit, resulting in a smaller average film thickness for the protective unit and a smaller slope angle for the first body. This prevents uneven stress caused by an excessively large slope angle, which could lead to film detachment. When water vapor intrudes, the provision of grooves 28 directly blocks the diffusion of water vapor, preventing it from being transmitted along the first direction (Y direction). Furthermore, during high-temperature and high-humidity testing, the thinner edges of the protective unit with a smaller slope angle also drive invading water vapor upward while also making it easier to diffuse in all directions (in the first or second direction) rather than just upward, thereby ensuring the stability of the film structure.

[0094] In some exemplary embodiments, as shown in Figures 3, 5, and 7, the display substrate includes a touch structure layer 50 located on the side of the light-emitting structure layer 30 facing away from the base substrate 10. The touch structure layer 50 may include: a touch buffer layer (TBL) 501, a first touch conductive layer 511, a touch interlayer insulating layer (TLD) 502, and a second touch conductive layer 512, arranged in sequence. The inorganic protective layer 31 may be located on the same layer and made of the same material as the touch interlayer insulating layer 502. The groove 28 extends perpendicular to the base substrate 10 (the third direction) to the surface of the connecting line 27 facing away from the base substrate 10, leaving the portion of the connecting line 27 facing away from the base substrate 10 exposed by the groove 28. The inorganic protective layer 31 covers the surface of the organic protective layer 29 facing away from the base substrate 10. Furthermore, the inorganic protective layer 31 also covers the portion of the connecting line 27 exposed by the groove 28, ensuring that the inorganic protective layer 29 covers the groove 28 and is in direct contact with the connecting line 27 through the groove 28.

[0095] In some exemplary embodiments, a display device may include the display substrate described above. In some exemplary embodiments, the display device is a product with an image display function, such as a monitor, television, billboard, digital photo frame, telephone, mobile phone, digital camera, camcorder, navigation system, home appliance, or other device with a display function. The embodiments of this application do not impose any particular limitations on the specific form of the display device described above.

[0096] In the above embodiment, the display substrate of this example reduces the volume of the organic protective layer 29 in the border area by adopting a groove design of the organic protective layer 29 (i.e., providing a groove 28), and avoids a continuous and large area of ​​the organic protective layer 29, and is divided into multiple units. An inorganic protective layer 29 is provided on the side of the groove 28 and the organic protective layer 29 away from the base substrate 10, so that the inorganic protective layer 29 is in direct contact with the connecting line 27, forming an inorganic protective layer 31 to block the organic protective layer 29, thereby blocking the path of water vapor transmission and directly isolating water vapor. Secondly, an inclined surface is formed at the edge of the protective unit through a halftone process, thereby forming a smaller average film thickness of the protective unit and a smaller slope angle of the first body, avoiding uneven stress caused by an excessively large slope angle, which may cause the film to detach. At the same time, during high temperature and high humidity testing, because of the use of a groove design of the organic protective layer 29, combined with the smaller thickness and slope angle of the film layer, the invading water vapor can diffuse to the surroundings, greatly reducing the water vapor that diffuses upward and reducing the impact of water vapor on the film structure.

[0097] Although the embodiments disclosed in this disclosure are as described above, the contents described are merely embodiments adopted to facilitate understanding of the disclosure and are not intended to limit the disclosure. Any person skilled in the art to which the disclosure belongs may make any modifications and changes in the form and details of the implementation without departing from the spirit and scope of the disclosure. However, the scope of patent protection of the present invention shall still be based on the scope defined by the appended claims.

Claims

1. A display substrate, wherein: The substrate includes a display area and a first frame area located on at least one side of the display area, wherein the first frame area includes a first binding area and a second binding area, and the second binding area is located on a side of the first binding area away from the display area; A plurality of sub-pixels are located on one side of the base substrate and in the display area; a plurality of data lines, located in the display area and the first frame area, the plurality of data lines being electrically connected to the plurality of sub-pixels; a plurality of first contact pads located in the first binding area, the plurality of first contact pads being configured to be bound to a driver chip, the plurality of first contact pads comprising at least one row of first input contact pads and at least one row of first output contact pads, the at least one row of first input contact pads being located on a side of the at least one row of first output contact pads away from the display area, the plurality of data lines being electrically connected to the at least one row of first output contact pads; a plurality of second contact pads located in the second binding area, wherein the plurality of second contact pads are configured to be bound to the circuit board; a plurality of connection lines located between the at least one row of first input contact pads and the plurality of second contact pads, the plurality of connection lines being configured to connect the at least one row of first input contact pads and the plurality of second contact pads; an organic protective layer, located on a side of the plurality of connection lines away from the base substrate, the organic protective layer being provided with at least one groove, the groove penetrating the organic protective layer in a direction perpendicular to the base substrate; The inorganic protective layer is located on a side of the organic protective layer away from the base substrate and covers the at least one groove. The inorganic protective layer is in direct contact with at least one connecting line among the plurality of connecting lines through the at least one groove.

2. The display substrate according to claim 1, wherein An extension direction of the at least one groove intersects an extension direction of the plurality of connecting lines, and an orthographic projection of the at least one groove on the base substrate overlaps with an orthographic projection of the plurality of connecting lines on the base substrate; The inorganic protection layer is in direct contact with the plurality of connection lines through the at least one groove.

3. The display substrate according to claim 2, wherein: The at least one groove includes a first groove and a second groove, wherein the second groove is located on a side of the first groove away from the display area.

4. The display substrate according to claim 2, wherein: The organic protection layer includes a plurality of protection units, the plurality of protection units are located in the first frame area and are sequentially arranged in a direction away from the display area, and the at least one groove is configured to separate the plurality of protection units.

5. The display substrate according to claim 4, wherein: At least one of the plurality of protection units includes a first body, a surface of the first body close to the groove is an inclined surface, and the inclined surface is inclined toward one side of the groove. The display substrate according to claim 5 , wherein: The slope angle of the inclined surface is set to α, 5°≤α≤45°.

7. The display substrate according to claim 5, wherein: The inclined surface is configured as an arc-shaped surface, and the arc-shaped surface is configured to protrude toward a side away from the base substrate.

8. The display substrate according to claim 5, wherein: At least one of the protection units further includes a second body, the first body is located on a side of the second body close to the groove, and a thickness of the first body is less than or equal to a thickness of the second body.

9. The display substrate according to claim 1, wherein: The first input contact pad and the second contact pad are arranged in a one-to-one correspondence and are connected via one of the connecting lines; or, One of the first input contact pads is connected to a plurality of the second contact pads via one of the connecting lines; or, A plurality of the first input contact pads are connected to one of the second contact pads via one of the connecting lines; or, A plurality of the first input contact pads are connected to a plurality of the second contact pads via one connecting line.

10. The display substrate according to claim 1, wherein At least one of the plurality of connection lines includes a first metal line and a second metal line, the second metal line is located on a side of the first metal line away from the substrate, and the first metal line and the second metal line are in direct contact and electrically connected.

11. The display substrate according to claim 1, wherein: The display substrate comprises a circuit structure layer and a light emitting structure layer which are sequentially arranged away from the base substrate; At least one sub-pixel among the plurality of sub-pixels includes a pixel circuit, a first switching electrode, and a light-emitting element, wherein the pixel circuit and the first switching electrode are located in the circuit structure layer, the light-emitting element is located in the light-emitting structure layer, and the pixel circuit is electrically connected to the light-emitting element through the first switching electrode; The circuit structure layer further includes a first flat layer and a second flat layer, wherein the first flat layer is located on a side of the first switching electrode close to the base substrate, and the second flat layer is located on a side of the first switching electrode away from the base substrate; The organic protection layer and the second planar layer are located on the same layer and are made of the same material.

12. The display substrate according to claim 11, wherein: The display substrate further includes a touch structure layer located on a side of the light emitting structure layer away from the base substrate, the touch structure layer including a first touch conductive layer, a touch interlayer insulating layer, and a second touch conductive layer sequentially arranged away from the base substrate; The inorganic protection layer and the touch interlayer insulating layer are located on the same layer.

13. The display substrate according to claim 11, wherein: The pixel circuit includes a transistor, the transistor includes an active layer, a gate located on a side of the active layer away from the substrate, and a source and a drain located on a side of the gate away from the substrate, and the first transfer electrode is located on a side of the source and the drain away from the substrate; The connecting line includes a first metal line and a second metal line that are stacked, the first metal line and the source or the drain are located in the same layer, and the second metal line and the first transfer electrode are located in the same layer.

14. The display substrate according to claim 11, wherein At least one sub-pixel among the plurality of sub-pixels includes a second switching electrode, and the first switching electrode is located on a side of the second switching electrode close to the base substrate; The connecting wire includes a first metal wire and a second metal wire that are stacked. The first metal wire and the first switching electrode are located in the same layer, and the second metal wire and the second switching electrode are located in the same layer.

15. A display device, wherein: The display substrate comprises the display substrate according to any one of claims 1 to 14.

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