Digital-to-analog converter

Abstract

Provided in the embodiments of the present disclosure is a digital-to-analog converter. First data and second data are generated by means of a data link, the first data is input into a first switch circuit Switch1, and the second data is input into a second switch circuit Switch2; the first switch circuit Switch1 and the second switch circuit Switch2 output a differential voltage Vout on the basis of the first data and the second data, and share a first charge with an output end; and a first charge compensation device and a second charge compensation device share a second charge with the output end, wherein the second charge and the first charge have opposite polarities, and the second charge and the first charge are mutually neutralized.

Description

A digital-to-analog converter

[0001] Cross-references to related publications

[0002] The present disclosure is based on Chinese Patent Publication No. 2024103799950 filed on March 29, 2024, entitled “A Digital-to-Analog Converter”, and claims the priority of the patent disclosure, and all the disclosed contents thereof are incorporated into the present disclosure by reference. Technical Field

[0003] The embodiments of the present disclosure relate to the field of communication technology, and in particular to a digital-to-analog converter. Background Art

[0004] The core circuit of a current-steering digital-to-analog converter is divided into multiple units (slices) for data reception. The switching of input data in the switching circuit will share charge to the output of the digital-to-analog converter (DAC) through the gate-drain capacitance of the switching circuit. When the DAC full-scale current (i.e., the sum of the current sources of all units in the DAC core circuit) changes, the shared charge does not change linearly, resulting in the differential voltage amplitude of the DAC output not changing linearly with the DAC full-scale current. It will also cause the phase of the DAC differential output to not remain constant when the DAC full-scale current changes. In the transmission chain of communication applications, in order to compensate for the power fluctuations of the DAC's post-stage power amplifier, the DAC needs to be adaptively adjusted within a wider full-scale current range, and the DAC output voltage is required to change linearly within this full-scale current range, and the output phase is required to be constant. The traditional current-steering digital-to-analog converter core circuit structure cannot meet these requirements.

[0005] There is no solution to the problem in the related art that the current-steering digital-to-analog converter cannot meet the requirements of linear voltage change and constant phase output within the full current range. Summary of the Invention

[0006] An embodiment of the present disclosure provides a digital-to-analog converter.

[0007] According to one embodiment of the present disclosure, a digital-to-analog converter is provided, comprising: a data link and a digital-to-analog converter core circuit, wherein the digital-to-analog converter core circuit comprises a first switching circuit Switch1, a second switching circuit Switch2, a first charge compensation device, and a second charge compensation device, wherein the first switching circuit Switch1 is connected to the first charge compensation device, and the second switching circuit Switch2 is connected to the second charge compensation device;

[0008] The data link is configured to generate first data and second data, and input the first data into the first switch circuit Switch1, and input the second data into the second switch circuit Switch2;

[0009] The first switch circuit Switch1 and the second switch circuit Switch2 are configured to output a differential voltage Vout according to the first data and the second data, and share a first charge to an output terminal;

[0010] The first charge compensation device and the second charge compensation device are configured to share a second charge to the output end, wherein the second charge has a polarity opposite to that of the first charge, and the second charge and the first charge neutralize each other. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] FIG1 is a block diagram of the core circuit structure of a current-steering digital-to-analog converter in the related art;

[0012] FIG2 is a block diagram of a digital-to-analog converter according to an embodiment of the present disclosure;

[0013] FIG3 is a first structural diagram of a core circuit of a current-steering digital-to-analog converter according to this embodiment;

[0014] FIG4 is a second structural diagram of the core circuit of the current-steering digital-to-analog converter according to this embodiment;

[0015] FIG5 is a third structural diagram of the core circuit of the current-steering digital-to-analog converter according to this embodiment;

[0016] FIG6 is a fourth structural diagram of the core circuit of the current-steering digital-to-analog converter according to this embodiment;

[0017] FIG7 is a schematic structural diagram of a digital-to-analog converter according to an embodiment of the present disclosure;

[0018] FIG8 is a fifth structural diagram of the core circuit of the current-steering digital-to-analog converter according to this embodiment. DETAILED DESCRIPTION

[0019] Hereinafter, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings and in conjunction with embodiments.

[0020] It should be noted that the terms "first", "second", etc. in the specification and claims of the present disclosure and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence.

[0021] Figure 1 is a core circuit block diagram of a current-steering DAC in the related art. As shown in Figure 1, data reception is performed in multiple units (Slices). The actual data D output by the switch driver is<N:0> and Db<N:0> They are connected to the gates of the switch circuits Switch1 and Switch2 in the DAC core circuit respectively, and are set to select the output current of the current source Current Source to the upper port of the load resistor RL1 or RL2 (that is, the positive or negative end of the DAC differential output). The Switch is a PMOS tube for illustration only, and an NMOS tube can also be used as a switch circuit. The drains of Switch1 of all DAC core circuit units are connected together, and the drains of all Switch2 are connected together. For the entire DAC core circuit, according to the D<N:0> and Db<N:0> Due to the different data, the total current flowing into RL1 and the total current flowing into RL2 are different, and the corresponding differential output voltage Vout is also different, ultimately achieving a linear conversion relationship between the output differential voltage Vout and the input data.

[0022] The switching of input data at the gates of the switch circuits Switch1 and Switch2 will share charge with the DAC output through the gate-drain capacitance of the switch circuits. When the DAC full-scale current (i.e., the sum of the currents of the current sources of all units in the DAC core circuit) changes, the shared charge does not change linearly, resulting in the DAC differential output voltage amplitude not changing linearly with the DAC full-scale current. This will also cause the phase of the DAC differential output to not remain constant when the DAC full-scale current changes. In the transmission chain of communication applications, in order to compensate for the power fluctuations of the DAC's post-stage power amplifier, the DAC needs to be adaptively adjusted within a wider full-scale current range. The DAC output voltage is also required to change linearly within this full-scale current range, and the output phase is required to be constant. The core circuit structure of the current-steering digital-to-analog converter cannot meet these requirements.

[0023] Based on this, a digital-to-analog converter is provided in this embodiment. FIG2 is a block diagram of a digital-to-analog converter according to an embodiment of the present disclosure. As shown in FIG2 , the digital-to-analog converter includes: a data link and a digital-to-analog converter core circuit, wherein the digital-to-analog converter core circuit includes a first switching circuit Switch1, a second switching circuit Switch2, a first charge compensation device, and a second charge compensation device. The first switching circuit Switch1 is connected to the first charge compensation device, and the second switching circuit Switch2 is connected to the second charge compensation device.

[0024] The data link is configured to generate first data and second data, and input the first data into the first switch circuit Switch1 and input the second data into the second switch circuit Switch2;

[0025] The first switch circuit Switch1 and the second switch circuit Switch2 are configured to output a differential voltage Vout according to the first data and the second data, and share the first charge to the output end;

[0026] The first charge compensation device and the second charge compensation device are configured to share a second charge to the output end, wherein the second charge has a polarity opposite to that of the first charge and the second charge and the first charge neutralize each other.

[0027] The digital-to-analog converter in this embodiment, through charge sharing at the DAC output end by the first charge compensation device, the second charge compensation device, and the switching device, can solve the problem in the related art that the current-steering digital-to-analog converter cannot meet the requirements of linear voltage change and constant phase output within the full current range, and realizes linear voltage change and constant phase output of the DAC within the full current range.

[0028] In one embodiment, the first charge compensation device is configured to invert the first data and share the second charge to the output terminal to neutralize the first charge shared by the first switch circuit Switch1 to the output terminal;

[0029] The second charge compensation device is configured to invert the second data and share the second charge to the output end to neutralize the first charge shared by the second switch circuit Switch2 to the output end.

[0030] In one embodiment, the first charge compensation device and the second charge compensation device are one of the following: a metal oxide semiconductor capacitor (MOSCAP), a series-parallel combination of MOSCAPs, a metal oxide metal capacitor (MOMCAP), a series-parallel combination of MOMCAPs, a metal insulator metal capacitor (MIMCAP), and a series-parallel combination of MIMCAPs.

[0031] In one embodiment, when the first charge compensation device and the second charge compensation device are moscaps or a series-parallel combination of moscaps, they are configured to share the second charge to the output end through a gate-source capacitor or a gate-drain capacitor;

[0032] When the first charge compensation device and the second charge compensation device are one of the following: momcap, a series-parallel combination of momcaps, mimcap, and a series-parallel combination of mimcaps, they are configured to share the second charge to the output end through a capacitor.

[0033] In the case where the first charge compensation device is a first moscap (corresponding to moscap1) and the second charge compensation device is a second moscap (corresponding to moscap2), FIG3 is a structural schematic diagram of the core circuit of the current steering digital-to-analog converter according to this embodiment. As shown in FIG3, two moscaps (named moscap1 and moscap2) are introduced. The gate of the first moscap is connected to the gate of the second switch circuit Switch2, the source of the first moscap is connected to the drain of the first switch circuit Switch1, and the gate of the second moscap is connected to the drain of the first switch circuit Switch2. The gate of h1 is connected, the source of the second moscap is connected to the drain of the second switching circuit Switch2, and the drain of the first moscap and the drain of the second moscap are floating; or the gate of the first moscap is connected to the gate of the second switching circuit Switch2, the drain of the first moscap is connected to the drain of the first switching circuit Switch1, the gate of the second moscap is connected to the gate of the first switching circuit Switch1, the drain of the second moscap is connected to the drain of the second switching circuit Switch2, and the source of the first moscap and the source of the second moscap are floating. The aspect ratio of moscap1 and moscap2 is consistent with that of DAC switches Switch1 and Switch2. The data connected to the gate of moscap1 is the inverse of the data connected to Switch1, and the data connected to the gate of moscap2 is the inverse of the data connected to Switch2. One end of the source or drain of moscap1 is connected to the drain of Switch1, and the other end is floating. One end of the source or drain of moscap2 is connected to the drain of Switch2, and the other end is floating (described).

[0034] Switch1 and Switch2 will input real data D<N:0> and Db<N:0> The output current of the current source Current Source is determined by the upper port of the load resistor RL1 or RL2 (i.e., the positive or negative terminal of the DAC differential output). Switching the gates of Switch1 and Switch2 will share charge with the DAC output through their own gate-drain capacitance. Switching the gates of the newly introduced moscap1 and moscap2 will share charge with the DAC output through the gate-source capacitance or gate-drain capacitance of moscap1 and moscap2. This shared charge has opposite polarity to the charge shared with the DAC output by the gate-drain capacitance of Switch1 / Switch2, neutralizing each other and compensating for the impact of the original shared charge on the DAC output amplitude and phase.

[0035] In an embodiment of the present disclosure, first data and second data are generated through a data link, and the first data is input into the first switching circuit Switch1, and the second data is input into the second switching circuit Switch2; the first switching circuit Switch1 and the second switching circuit Switch2 output a differential voltage Vout according to the first data and the second data, and share a first charge to the output end; the first charge compensation device and the second charge compensation device share a second charge to the output end, wherein the second charge has an opposite polarity to the first charge and the second charge and the first charge neutralize each other, which can solve the problem in the related art that the current-steering digital-to-analog converter cannot meet the requirements of linear voltage change and constant phase output within the full current range. By neutralizing the charge sharing of the DAC output end by the first charge compensation device and the second charge compensation device and the switching device, the linear voltage change and constant phase output by the DAC within the full current range are achieved.

[0036] FIG4 is a second structural diagram of the core circuit of the current-steering DAC according to this embodiment. As shown in FIG4 , the MOSCAP gate connection method remains unchanged, and the floating ends of the two MOSCAPs are connected together, or the floating ends are no longer floating but connected to a fixed potential. The gate of the first moscap (corresponding to moscap1) is connected to the gate of the second switching circuit Switch2, the source of the first moscap is connected to the drain of the first switching circuit Switch1, the gate of the second moscap is connected to the gate of the first switching circuit Switch1, the source of the second moscap (corresponding to moscap2) is connected to the drain of the second switching circuit Switch2, and the drain of the first moscap is connected to the drain of the second switching circuit moscap2; or the gate of the first moscap is connected to the gate of the second switching circuit Switch2, the gate of the first moscap is connected to the drain of the first switching circuit Switch1, the gate of the second moscap is connected to the gate of the first switching circuit Switch1, the gate of the second moscap is connected to the drain of the second switching circuit Switch2, and the source of the first moscap is connected to the source of the second switching circuit moscap2.

[0037] FIG5 is a third structural diagram of the core circuit of the current-steering DAC according to this embodiment. As shown in FIG5 , the source and drain of the MOSCAP are short-circuited and simultaneously connected to the drain of the switch, etc. Depending on the connection method, the aspect ratio of the MOSCAP can also be adjusted accordingly. The source of the first moscap (corresponding to moscap1) is connected to the drain of the first switching circuit Switch1, the gate of the second moscap (corresponding to moscap2) is connected to the gate of the first switching circuit Switch1, the source of the second moscap is connected to the drain of the second switching circuit Switch2, the source of the first moscap is connected to the drain of the first moscap, and the source of the second moscap is connected to the drain of the second moscap; or the gate of the first moscap is connected to the gate of the second switching circuit Switch2, the drain of the first moscap is connected to the drain of the first switching circuit Switch1, the gate of the second moscap is connected to the gate of the first switching circuit Switch1, the drain of the second moscap is connected to the drain of the second switching circuit Switch2, the source of the first moscap is connected to the drain of the first moscap, and the source of the second moscap is connected to the drain of the second moscap.

[0038] In the case where the first charge compensation device is a parallel connection of moscaps (corresponding to moscap1 and moscap1' in parallel), and the second charge compensation device is a parallel connection of moscaps (corresponding to moscap2 and moscap2' in parallel), FIG6 is a structural schematic diagram of the core circuit of the current steering type digital-to-analog converter according to this embodiment. As shown in FIG6, moscap1 and moscap1' are connected in parallel and then connected to Switch1, and moscap2 and moscap2' are connected in parallel and then connected to Switch2. The specific connection method after parallel connection is similar to the first moscap and the second moscap in FIG3, and will not be repeated here. The first charge compensation device is a series connection of moscaps (corresponding to moscap1 and moscap1' in series), and the second charge compensation device is a series connection of moscaps (corresponding to moscap2 and moscap2' in series) and the parallel connection is similar, and will not be repeated here.

[0039] FIG7 is a schematic diagram of the structure of a digital-to-analog converter according to an embodiment of the present disclosure. As shown in FIG7 , the digital-to-analog converter includes a data path, a clock path, and a digital-to-analog converter core circuit (DAC Core). The data path includes an interface circuit, a digital data path, a decoder, a serializer, and a switch driver; the clock path includes a clock receiver, a delay-locked loop (DLL), a divider, and some clock drivers, etc.; and the digital-to-analog converter core circuit includes multiple digital-to-analog converter core units (DAC Core Slices). For DAC, the design of the digital-to-analog converter core circuit is crucial, affecting multiple indicators such as linearity, power consumption, noise, and output power. The digital-to-analog converter core circuit in this embodiment includes multiple digital-to-analog converter core units, wherein the drains of the first switch circuits Switch1 of the multiple digital-to-analog converter core units are connected together, and the drains of the second switch circuits Switch2 of the multiple digital-to-analog converter core units are connected together. The first switch circuit Switch1, the second switch circuit Switch2, the first MOSCAP (MOSCAP1) and the second MOSCAP (MOSCAP2) are on the same substrate. Furthermore, the first switch circuit Switch1, the second switch circuit Switch2, the first MOSCAP and the second MOSCAP have the same or different sizes.

[0040] FIG8 is a structural diagram of the core circuit of the current steering digital-to-analog converter according to the present embodiment. As shown in FIG8 , when the first charge compensation device is momcap1 or mimcap1 (corresponding to cap1) and the second charge compensation device is momcap2 or mimcap2 (corresponding to cap2), the upper plate of the momcap1 or mimcap1 is connected to the drain of the first switch circuit Switch1, and the lower plate of the momcap1 or mimcap1 is connected to the gate of the second switch circuit Switch2; the upper plate of the momcap2 or mimcap2 is connected to the drain of the second switch circuit Switch1. The drain of ch2 is connected, and the lower plate of the momcap2 or mimcap2 is connected to the gate of the first switch circuit Switch1; or the lower plate of the momcap1 or mimcap1 is connected to the drain of the first switch circuit Switch1, and the upper plate of the momcap1 or mimcap1 is connected to the gate of the second switch circuit Switch2; the lower plate of the momcap2 or mimcap2 is connected to the drain of the second switch circuit Switch2, and the upper plate of the momcap2 or mimcap2 is connected to the gate of the first switch circuit Switch1. The series and parallel connection of momcap and / or mimcap is also similar. After the series and parallel connection, they can be connected to Switch1 and Switch2, which will not be repeated here.

[0041] In a data link, input digital signals are first received and processed through the interface circuit and digital data link. The decoder's primary function is to perform DAC segment encoding (typically thermometer code for the DAC's upper bits and binary encoding for the lower bits). Furthermore, the decoder can apply algorithms such as DEM, dithering, and rotation to the data. In these digital modules, each DAC bit is typically transmitted in multiple phases. The serializer's primary function is to convert multi-phase data into a single phase or fewer phases. The switch driver's primary function is to synchronize each bit of data and increase drive capability. The distinction between switch drivers and serializers can sometimes be blurred, as the switch driver may also perform some serialization. The switch driver's output is fed into the digital-to-analog converter core unit, which performs the digital-to-analog conversion function. The clock link's function is to provide clocks of various frequencies and phases to the data link.

[0042] In this embodiment, the first switch circuit Switch1 and the second switch circuit Switch2 are PMOS transistors or NMOS transistors.

[0043] This embodiment introduces two MOSFETs (MOSFETs) with the same size as the DAC switches into the core circuit structure of a current-steering digital-to-analog converter. The gates are connected to data inversion, sharing charges of opposite polarity with the connected DAC switch source, compensating for the effects of gate-drain charge sharing on the DAC output amplitude and phase. This overcomes the problem of related art in achieving linear output voltage variation and constant output phase over a wide full-scale current range. Within the 0-30dB DAC full-scale current range, the DAC output voltage amplitude varies by greater than 29dB (very close to linear variation), with a phase deviation of less than 5 degrees.

[0044] The aspect ratio of the newly introduced moscap1 and moscap2 can be adjusted (not necessarily consistent with the aspect ratio of the DAC switches Switch1 and Switch2). This can adjust the charge neutralization effect, and thus adjust the impact of shared charge on the DAC output amplitude and phase. The moscap connection method can have many variations, as long as it can provide a shared path to the DAC output. For example: as shown in Figure 4, the moscap gate connection method remains unchanged, the floating terminals of the original two moscaps are connected together, or the floating terminals are no longer floating but connected to a fixed potential, or as shown in Figure 5, the moscap source and drain are shorted and connected to the drain of the switch at the same time. Depending on the connection method, the aspect ratio of the moscap can also be adjusted accordingly.

[0045] Although the connection methods of Figures 4 and 5 are different from those of Figure 3, the basic operating principles are similar. Both use the newly introduced MOSCAP to share charge to the DAC output, offsetting the effect of Switch1 / Switch2 sharing charge to the DAC output.

[0046] The charge compensation device in this embodiment may be a MOSCAP, or other types of capacitors (caps), such as a series-parallel combination of MOSCAPs, a MOMCAP, a MIMCAP, a series-parallel combination of MOSCAP / MOMCAP / MIMCAP, or other similar capacitors, or other circuits capable of providing a sharing path, such as the parallel connection of MOSCAPs or MOMCAPs as shown in FIG6 .

[0047] For specific examples in this embodiment, reference may be made to the examples described in the above embodiments and exemplary implementation modes, and this embodiment will not be described in detail here.

[0048] The foregoing description is merely a preferred embodiment of the present disclosure and is not intended to limit the present disclosure. Those skilled in the art will readily appreciate that various modifications and variations of the present disclosure are possible. Any modifications, equivalent substitutions, or improvements made within the principles of the present disclosure shall be included within the scope of protection of the present disclosure.

Claims

1. A digital-to-analog converter, comprising: A data link and a digital-to-analog converter core circuit, wherein the digital-to-analog converter core circuit includes a first switching circuit Switch1, a second switching circuit Switch2, a first charge compensation device, and a second charge compensation device, wherein the first switching circuit Switch1 is connected to the first charge compensation device, and the second switching circuit Switch2 is connected to the second charge compensation device; The data link is configured to generate first data and second data, and input the first data into the first switch circuit Switch1 and input the second data into the second switch circuit Switch2; The first switch circuit Switch1 and the second switch circuit Switch2 are configured to output a differential voltage Vout according to the first data and the second data, and share a first charge to an output terminal; The first charge compensation device and the second charge compensation device are configured to share a second charge to the output end, wherein the second charge has a polarity opposite to that of the first charge, and the second charge and the first charge neutralize each other.

2. The digital-to-analog converter according to claim 1, wherein: The first charge compensation device is configured to invert the first data and share the second charge to the output end to neutralize the first charge shared by the first switch circuit Switch1 to the output end; The second charge compensation device is configured to invert the second data and share the second charge to the output end to neutralize the first charge shared by the second switch circuit Switch2 to the output end.

3. The digital-to-analog converter according to claim 2, wherein: The first charge compensation device and the second charge compensation device are one of the following: a metal-oxide-silicon capacitor moscap, a series-parallel combination of moscaps, a metal-oxide-metal capacitor momcap, a series-parallel combination of momcaps, a metal-insulator-metal capacitor mimcap, and a series-parallel combination of mimcaps.

4. The digital-to-analog converter according to claim 3, wherein: When the first charge compensation device and the second charge compensation device are MOSCAPs or a series-parallel combination of MOSCAPs, they are configured to share the second charge to the output end through a gate-source capacitor or a gate-drain capacitor; When the first charge compensation device and the second charge compensation device are one of the following: momcap, a series-parallel combination of momcaps, mimcap, and a series-parallel combination of mimcaps, they are configured to share the second charge to the output end through a capacitor.

5. The digital-to-analog converter according to claim 4, wherein: In the case where the first charge compensation device is a first MOScap and the second charge compensation device is a second MOScap, the gate of the first MOScap is connected to the gate of the second switch circuit Switch2, the source of the first MOScap is connected to the drain of the first switch circuit Switch1, the gate of the second MOScap is connected to the gate of the first switch circuit Switch1, the source of the second MOScap is connected to the drain of the second switch circuit Switch2, and the drain of the first MOScap and the drain of the second MOScap are floating; or The gate of the first moscap is connected to the gate of the second switch circuit Switch2, the drain of the first moscap is connected to the drain of the first switch circuit Switch1, the gate of the second moscap is connected to the gate of the first switch circuit Switch1, the drain of the second moscap is connected to the drain of the second switch circuit Switch2, and the source of the first moscap and the source of the second moscap are floating.

6. The digital-to-analog converter according to claim 4, wherein: In the case where the first charge compensation device is a first MOScap and the second charge compensation device is a second MOScap, the gate of the first MOScap is connected to the gate of the second switch circuit Switch2, the source of the first MOScap is connected to the drain of the first switch circuit Switch1, the gate of the second MOScap is connected to the gate of the first switch circuit Switch1, the source of the second MOScap is connected to the drain of the second switch circuit Switch2, and the drain of the first MOScap is connected to the drain of the second switch circuit Moscap2; or The gate of the first moscap is connected to the gate of the second switch circuit Switch2, the gate of the first moscap is connected to the drain of the first switch circuit Switch1, the gate of the second moscap is connected to the gate of the first switch circuit Switch1, the gate of the second moscap is connected to the drain of the second switch circuit Switch2, and the source of the first moscap is connected to the source of the second switch circuit Moscap2.

7. The digital-to-analog converter according to claim 4, wherein: In the case where the first charge compensation device is a first MOScap and the second charge compensation device is a second MOScap, the gate of the first MOScap is connected to the gate of the second switch circuit Switch2, the source of the first MOScap is connected to the drain of the first switch circuit Switch1, the gate of the second MOScap is connected to the gate of the first switch circuit Switch1, the source of the second MOScap is connected to the drain of the second switch circuit Switch2, the source of the first MOScap is connected to the drain of the first MOScap, and the source of the second MOScap is connected to the drain of the second MOScap; or The gate of the first moscap is connected to the gate of the second switching circuit Switch2, the drain of the first moscap is connected to the drain of the first switching circuit Switch1, the gate of the second moscap is connected to the gate of the first switching circuit Switch1, the drain of the second moscap is connected to the drain of the second switching circuit Switch2, the source of the first moscap is connected to the drain of the first moscap, and the source of the second moscap is connected to the drain of the second moscap.

8. The digital-to-analog converter according to any one of claims 5 to 7, wherein: The first switch circuit Switch1 , the second switch circuit Switch2 , the first MOSCAP and the second MOSCAP are on the same substrate.

9. The digital-to-analog converter according to any one of claims 5 to 7, wherein: The sizes of the first switch circuit Switch1 , the second switch circuit Switch2 , the first MOSCAP, and the second MOSCAP are consistent or inconsistent.

10. The digital-to-analog converter according to claim 4, wherein: When the first charge compensation device is momcap1 or mimcap1 and the second charge compensation device is momcap2 or mimcap2, the upper plate of the momcap1 or mimcap1 is connected to the drain of the first switching circuit Switch1, and the lower plate of the momcap1 or mimcap1 is connected to the gate of the second switching circuit Switch2; the upper plate of the momcap2 or mimcap2 is connected to the drain of the second switching circuit Switch2, and the lower plate of the momcap2 or mimcap2 is connected to the gate of the first switching circuit Switch1; or The lower plate of the momcap1 or the mimcap1 is connected to the drain of the first switching circuit Switch1, and the upper plate of the momcap1 or the mimcap1 is connected to the gate of the second switching circuit Switch2; the lower plate of the momcap2 or the mimcap2 is connected to the drain of the second switching circuit Switch2, and the upper plate of the momcap2 or the mimcap2 is connected to the gate of the first switching circuit Switch1.

11. The digital-to-analog converter according to any one of claims 1 to 7 and 10, The digital-to-analog converter core circuit includes a plurality of digital-to-analog converter core units, wherein: The drains of the first switch circuits Switch1 of the multiple digital-to-analog converter core units are connected together, and the drains of the second switch circuits Switch2 of the multiple digital-to-analog converter core units are connected together.

12. The digital-to-analog converter according to any one of claims 1 to 7 and 10, The first switch circuit Switch1 and the second switch circuit Switch2 are PMOS transistors or NMOS transistors.

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