Semiconductor power device and manufacturing method therefor

Abstract

Provided in the present invention are a semiconductor power device and a manufacturing method therefor. The semiconductor power device comprises: a semiconductor substrate layer; a drift layer, located on one side of the bottom of the semiconductor substrate layer; a gate structure, located in the drift layer; well regions, which are respectively provided in the drift layer on two sides of the gate structure; and a protective unit, which surrounds the bottom surface and part of the side wall of the gate structure in the drift layer. The protective unit comprises: a first doped protective layer, located in the drift layer at part of the bottom of the gate structure; and a second doped protective layer, which is located at part of the side wall of the gate structure and part of the bottom drift layer, the conductivity type of the first doped protective layer being the same as that of the well regions and being opposite to that of the second doped protective layer, the doping concentration of the second doped protective layer being greater than that of the drift layer, and the second doped protective layer and the first doped protective layer forming a PN junction. The present invention increases protection on gate dielectric layers.

Description

Semiconductor power device and preparation method thereof

[0001] This application claims priority to Chinese patent application CN202410375859.4, entitled “Semiconductor power device and preparation method thereof,” filed on March 29, 2024, the entire contents of which are incorporated herein by reference. Technical Field

[0002] The present invention relates to the field of semiconductor technology, and in particular to a semiconductor power device and a preparation method thereof. Background Art

[0003] Power semiconductor devices are core components for power conversion and circuit control in power electronics. With the recent development of industries such as new energy vehicles, photovoltaics, rail transit, and smart grids, market demand for power devices has rapidly increased. Third-generation semiconductor SiC materials offer significant advantages in bandgap, thermal conductivity, critical breakdown field strength, and electron saturation drift velocity, aligning with the future trend of power electronics systems toward miniaturization, lightweighting, efficient integration, safety, and reliability.

[0004] With the continuous iteration of planar SiC MOSFET technology, its ability to reduce cell size is gradually reaching its limit. In comparison, trench SiC MOSFET, with its inherent advantages such as smaller cell size and higher channel density, is destined to be the development trend of next-generation SiC power devices. For trench SiC MOSFETs, electric field concentration at the bottom gate oxide in the reverse blocking state is a key issue that restricts their performance and reliability. Summary of the Invention

[0005] The technical problem to be solved by the present invention is how to improve the problem of electric field concentration in the bottom region of the gate structure of a semiconductor power device in a reverse blocking state.

[0006] In order to solve the above technical problems, the present invention provides a semiconductor power device, which includes: a semiconductor substrate layer; a drift layer located on one side of the semiconductor substrate layer; a gate structure located in the drift layer; a well region, respectively located in the drift layer on both sides of the gate structure; and a protection unit surrounding the bottom surface and part of the side wall of the gate structure in the drift layer, the protection unit including: a first doped protection layer, located in the drift layer at the bottom of the gate structure; and a second doped protection layer, located in the drift layer at the side wall and part of the bottom of the gate structure, the conductivity type of the first doped protection layer is the same as the conductivity type of the well region and is opposite to the conductivity type of the second doped protection layer, the doping concentration of the second doped protection layer is greater than the doping concentration of the drift layer, and the second doped protection layer and the first doped protection layer form a PN junction.

[0007] Optionally, a portion of the well region serves as a channel region, the channel region contacts a sidewall of the gate structure, and a doping concentration of the channel region is lower than a doping concentration of the well region outside the channel region.

[0008] Optionally, the doping concentration of the channel region is 1E16 atom / cm 3 ~5E17atom / cm 3 The doping concentration of the well region outside the channel region is 5E16atom / cm 3 ~2E18atom / cm 3 .

[0009] Optionally, the well region includes a first well region and a second well region on the side of the first well region facing the semiconductor substrate layer, the second well region is in contact with the first well region, a portion of the first well region serves as a channel region, and the second doping protection layer on the side wall of the gate structure is located between the second well region and the gate structure.

[0010] Optionally, the doping concentration of the second well region is lower than the doping concentration of the first well region outside the channel region.

[0011] Optionally, a surface of the channel region facing the semiconductor substrate layer is flush with a surface of the well region outside the channel region facing the semiconductor substrate layer.

[0012] Optionally, a longitudinal distance between a surface of the well region facing the semiconductor substrate layer and a surface of the first doping protection layer facing the semiconductor substrate layer is 0.3 micrometers to 1.5 micrometers.

[0013] Optionally, the doping concentration of the second doping protection layer is 2 to 10 times the doping concentration of the drift layer.

[0014] Optionally, the second doping protection layer is located on both sides of the first doping protection layer along the width direction of the gate structure and does not surround the surface of the first doping protection layer facing the semiconductor substrate layer, or the second doping protection layer is located on both sides of the first doping protection layer along the width direction of the gate structure and also surrounds the surface of the first doping protection layer facing the semiconductor substrate layer.

[0015] Optionally, the doping concentration of the first doping protection layer is greater than the doping concentration of the second doping protection layer.

[0016] Optionally, the semiconductor power device is a SiC-based semiconductor power device.

[0017] The present invention also provides a method for preparing a semiconductor power device, the preparation method comprising: forming a drift layer on one side of a semiconductor substrate layer; and forming a gate structure, a well region and a protection unit in the drift layer, the well regions being respectively located in the drift layer on both sides of the gate structure, the protection unit surrounding the bottom surface and part of the side wall of the gate structure, the formation of the protection unit comprising: forming a first doped protection layer, the first doped protection layer being located in the drift layer at the bottom portion of the gate structure; and forming a second doped protection layer, the second doped protection layer being located in the drift layer at part of the side wall and part of the bottom portion of the gate structure, the conductivity type of the first doped protection layer being the same as the conductivity type of the well region and opposite to the conductivity type of the second doped protection layer, the doping concentration of the second doped protection layer being greater than the doping concentration of the drift layer, and the second doped protection layer and the first doped protection layer forming a PN junction.

[0018] Optionally, the process of forming the gate structure, the well region and the protection unit in the drift layer includes: forming a first doping region in the drift layer extending from a surface of the drift layer on a side facing away from the semiconductor substrate to a portion of the thickness; forming an initial well region in the drift layer on both sides of the first doping region and in the first doping region, wherein the doping concentration of the initial well region in the first doping region is less than the doping concentration of the initial well regions on both sides of the first doping region, and a surface of the initial well region in the first doping region facing the semiconductor substrate layer is farther away from the semiconductor substrate layer than a surface of the first doping region facing the semiconductor substrate layer; forming a trench in the first doping region that penetrates the initial well region in the first doping region and extends to the bottom of the initial well region, wherein the lateral dimension of the trench is smaller than the lateral dimension of the first doping region, and the bottom surface of the trench is farther away from the semiconductor substrate layer than a surface of the first doping region facing the semiconductor substrate layer, wherein the remaining initial well region around the trench forms the well region, and the remaining first doping region around the trench forms the second doped protection layer; and after forming the trench, forming a first doped protection layer in the drift layer at a portion of the bottom of the trench.

[0019] Optionally, the side surface of the initial well region in the first doping region facing the semiconductor substrate layer is flush with the side surface of the initial well region on both sides of the first doping region facing the semiconductor substrate layer, or the side surface of the initial well region in the first doping region facing the semiconductor substrate layer is farther away from the semiconductor substrate layer relative to the side surface of the initial well region on both sides of the first doping region facing the semiconductor substrate layer.

[0020] The technical solution of the present invention has the following technical effects:

[0021] The semiconductor power device provided by the technical solution of the present invention comprises a protection unit disposed in the drift layer, surrounding the bottom surface and a portion of the sidewalls of the gate structure. The protection unit comprises: a first doped protection layer, located in the drift layer at the bottom portion of the gate structure; and a second doped protection layer, located in the drift layer at the bottom portion of the gate structure's sidewalls and a portion of the gate structure's bottom portion. The first doped protection layer has the same conductivity type as the well region and an opposite conductivity type to the second doped protection layer. The second doped protection layer has a greater doping concentration than the drift layer, and the second doped protection layer and the first doped protection layer form a PN junction. This allows the PN junction to deplete during reverse breakdown, shifting a portion of the electric field peak to the PN junction boundary. The PN junction protects the gate dielectric layer at the bottom of the gate structure. Furthermore, the well region and the drift layer at the bottom of the well region deplete, shifting a portion of the electric field peak to the boundary between the well region and the drift layer, protecting the gate dielectric layer in the sidewall region of the gate structure. This increased protection of the gate dielectric layer improves the reverse breakdown voltage.

[0022] Secondly, when the semiconductor power device is forward-conducting, electrons pass from the first source region through the channel region and the second doped protection layer at the bottom of the channel region. Because the doping concentration of the second doped protection layer is greater than the doping concentration of the drift layer, the forward conduction resistance is reduced.

[0023] Furthermore, the doping concentration of the channel region is lower than the doping concentration of the well region outside the channel region, so that the channel region is more easily inverted and the channel resistance is smaller.

[0024] The present invention provides a method for preparing a semiconductor power device, forming a protection unit comprising a first doped protection layer and a second doped protection layer. The second doped protection layer and the first doped protection layer form a PN junction. During reverse withstand voltage, the PN junction depletes, and a portion of the electric field peak is transferred to the junction of the PN junction. The PN junction protects the gate dielectric layer at the bottom of the gate structure. Furthermore, the well region and the drift layer at the bottom of the well region deplete, and a portion of the electric field peak is transferred to the junction of the well region and the drift layer, protecting the gate dielectric layer in the sidewall region of the gate structure. Due to the increased protection of the gate dielectric layer, the withstand voltage capability of the device is improved.

[0025] Furthermore, after the first doped region and the trench is formed, the second doped protective layer is formed from the remaining first doped region around the trench. Since the first doped region is formed before the trench is formed, the edge position and edge morphology of the first doped region can be well controlled. Therefore, the morphology and size of the formed second doped protective layer can be well controlled without increasing the size of the cell. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] In order to more clearly illustrate the specific embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the specific embodiments or the description of the prior art. Obviously, the drawings described below are some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0027] FIG1 is a schematic structural diagram of a semiconductor power device provided by an embodiment of the present invention;

[0028] FIG2 is a schematic structural diagram of a semiconductor power device provided by another embodiment of the present invention;

[0029] FIG3 is a schematic structural diagram of a semiconductor power device provided by another embodiment of the present invention;

[0030] FIG4 is a schematic structural diagram of a semiconductor power device provided by another embodiment of the present invention;

[0031] 5 to 13 are schematic structural diagrams of a semiconductor power device manufacturing process according to an embodiment of the present invention;

[0032] 14 to 16 are schematic structural diagrams of a semiconductor power device manufacturing process according to another embodiment of the present invention;

[0033] 17 to 23 are schematic structural diagrams of a semiconductor power device manufacturing process according to another embodiment of the present invention;

[0034] 24 and 25 are schematic structural diagrams of a semiconductor power device manufacturing process according to another embodiment of the present invention. DETAILED DESCRIPTION

[0035] The technical solution of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the embodiments described are only some embodiments of the present invention, not all embodiments. All other embodiments obtained by ordinary technicians in this field based on the embodiments of the present invention without making any creative efforts shall fall within the scope of protection of the present invention.

[0036] In the description of the present invention, it should be noted that the terms "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer," etc., indicating orientations or positional relationships, are based on the orientations or positional relationships shown in the accompanying drawings and are intended solely to facilitate and simplify the description of the present invention. They are not intended to indicate or imply that the devices or components referred to must have, be constructed, or operate in a specific orientation, and therefore should not be construed as limitations on the present invention. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0037] In the description of the present invention, it should be noted that, unless otherwise expressly specified or limited, the terms "installed," "connected," and "connected" should be understood in a broad sense. For example, they can refer to fixed connections, detachable connections, or integral connections; mechanical connections or electrical connections; direct connections or indirect connections through an intermediate medium; internal connections between two components; wireless connections or wired connections. Those skilled in the art will understand the specific meanings of the above terms in the present invention based on specific circumstances.

[0038] In addition, the technical features involved in the different embodiments of the present invention described below can be combined with each other as long as they do not conflict with each other.

[0039] An embodiment of the present invention provides a semiconductor power device. Referring to FIG1 , the semiconductor power device includes:

[0040] a semiconductor substrate layer 100;

[0041] a drift layer 110 located on one side of the semiconductor substrate layer 100;

[0042] a gate structure located in the drift layer 110;

[0043] Well regions 150 are respectively located in the drift layer 110 on both sides of the gate structure; and

[0044] A protection unit is formed in the drift layer 110 and surrounds the bottom surface and a portion of the sidewall of the gate structure.

[0045] The protection unit includes: a first doped protection layer 140 located in the drift layer 110 at the bottom of the gate structure; and a second doped protection layer 130 located in the drift layer 110 at the sidewalls and bottom of the gate structure. The conductivity type of the first doped protection layer 140 is the same as that of the well region 150 and opposite to that of the second doped protection layer 130. The doping concentration of the second doped protection layer 130 is greater than that of the drift layer 110. The second doped protection layer 130 and the first doped protection layer 140 form a PN junction.

[0046] The gate structure includes a gate dielectric layer 121 and a gate electrode layer 122 .

[0047] In this embodiment, during the reverse withstand voltage test of the semiconductor power device, the PN junction formed by the second doped protection layer 130 and the first doped protection layer 140 is depleted, and the electric field peak is transferred to the junction of the PN junction. The PN junction protects the gate dielectric layer 121 at the bottom of the gate structure. Secondly, the well region 150 and the drift layer 110 at the bottom of the well region 150 are depleted, protecting the gate dielectric layer 121 in the sidewall region of the gate structure. Because the electric field strength at the location of the gate dielectric layer 121 is reduced, the protection capability of the gate dielectric layer 121 is improved.

[0048] Secondly, the doping concentration of the second doped protection layer 130 is greater than the doping concentration of the drift layer 110 , so when the semiconductor power device is forward-conducted, the resistance of the second doped protection layer 130 is small, thereby reducing the forward conduction resistance.

[0049] It should be noted that if a protection unit is not provided, even if depletion occurs in the well region and the drift layer at the bottom of the well region, there is little protection for the gate dielectric layer in the sidewall region of the gate structure. This is because, in the reverse blocking state of the semiconductor power device, an electric field concentration will occur at the bottom gate dielectric layer of the gate structure of the semiconductor power device without a protection unit, and the gate dielectric layer at the bottom of the gate structure is easily broken down. Therefore, the depletion of the drift layer in the well region and the bottom of the well region has no chance to play a protective role for the gate dielectric layer in the sidewall region of the gate structure. However, after the protection unit is provided, in the reverse blocking state of the semiconductor power device, the protection unit can alleviate the electric field concentration at the bottom gate dielectric layer of the gate structure. The protection unit provides better protection for the gate dielectric layer, and the gate dielectric layer is not easily broken down. Therefore, the depletion of the drift layer in the well region and the bottom of the well region can increase the protection of the gate dielectric layer.

[0050] In this embodiment, the new generation of SiC-based semiconductor power devices represented by SiC have higher reverse withstand voltage capability, lower forward conduction loss, faster switching frequency and stronger environmental tolerance compared to Si-based semiconductor power devices, and are therefore considered to be a new hope in the field of power conversion. It should be noted that in this embodiment, the semiconductor substrate layer 100 is silicon carbide (SiC) doped with conductive ions. In one embodiment, the conductive ions in the semiconductor substrate layer 100 are N-type ions. In other embodiments, there is no restriction on the conductivity type of the semiconductor substrate layer 100.

[0051] In one embodiment, the conductivity type of the drift layer 110 is the same as that of the semiconductor substrate layer 100, and the doping concentration of the drift layer 110 is lower than the doping concentration of the semiconductor substrate layer 100. In one embodiment, the drift layer is made of silicon carbide doped with N-type conductive ions. The N-type conductive ions may be phosphorus ions or nitrogen ions.

[0052] The conductivity type of the well region 150 is opposite to the conductivity type of the drift layer 110. In this embodiment, when the conductivity type of the drift layer 110 is N-type, the conductivity type of the well region 150 is P-type.

[0053] In this embodiment, the semiconductor power device further includes a first source region 160 located in the well region 150. The conductivity type of the first source region 160 is opposite to the conductivity type of the well region 150. In this embodiment, when the conductivity type of the well region 150 is P-type, the conductivity type of the first source region 160 is N-type.

[0054] In this embodiment, the semiconductor power device further includes a second source region 170 located in the well region 150. The conductivity type of the second source region 170 is opposite to that of the first source region 160. The second source region 170 is located on a side of the first source region 160 away from the gate structure along the width direction of the gate structure.

[0055] In this embodiment, the semiconductor power device further includes a drain electrode layer 180 located on a surface of the semiconductor substrate layer 100 facing away from the drift layer 110 .

[0056] The gate structure includes a gate dielectric layer 121 and a gate electrode layer 122 . The gate dielectric layer 121 is located on the surface of the gate electrode layer 122 facing the semiconductor substrate layer 100 (ie, the bottom surface of the gate electrode layer 122 ) and the sidewalls of the gate electrode layer 122 .

[0057] In one embodiment, the gate dielectric layer 121 is made of silicon oxide, and the gate electrode layer 122 is made of polysilicon.

[0058] In one embodiment, a portion of the well region 150 serves as a channel region 151, and the channel region 151 contacts the sidewalls of the gate structure. Specifically, the channel region 151 contacts a portion of the gate dielectric layer 121 located on the side of the gate electrode layer 122. The doping concentration of the channel region 151 is lower than the doping concentration of the well region 150 outside the channel region 151. This makes the channel region 151 more susceptible to inversion and reduces the channel resistance.

[0059] In one embodiment, the doping concentration of the channel region 151 is 1E16 atom / cm 3 ~5E17atom / cm 3 The doping concentration of the well region 150 outside the channel region 151 is 5E16atom / cm 3 ~2E18atom / cm 3 .

[0060] In one embodiment, referring to FIG. 1 , a surface of the channel region 151 facing the semiconductor substrate layer 100 is flush with a surface of the well region 150 outside the channel region 151 facing the semiconductor substrate layer 100 .

[0061] In one embodiment, a longitudinal distance between a surface of the well region 150 facing the semiconductor substrate layer 100 and a surface of the first doping protection layer 140 facing the semiconductor substrate layer 100 is in a range of 0.3 microns to 1.5 microns, for example, 0.3 microns, 0.5 microns, 0.8 microns, 1.0 microns, 1.2 microns, or 1.5 microns, and the direction of the longitudinal distance is parallel to the thickness direction of the semiconductor substrate layer 100. The longitudinal distance between the surface of the well region 150 facing the semiconductor substrate layer 100 and the surface of the first doping protection layer 140 facing the semiconductor substrate layer 100 is less than or equal to 1.5 microns, so that the longitudinal distance between the surface of the well region 150 facing the semiconductor substrate layer 100 and the surface of the first doping protection layer 140 facing the semiconductor substrate layer 100 is shorter, thereby better protecting the gate dielectric layer in the sidewall region of the gate structure due to depletion of the well region 150 and the drift layer 100 at the bottom of the well region 150. The longitudinal distance between the surface of the well region 150 facing the semiconductor substrate layer 100 and the surface of the first doped protection layer 140 facing the semiconductor substrate layer 100 is greater than or equal to 0.3 microns. This distance between the interface between the well region 150 and the drift layer 100 at the bottom of the well region 150 and the protection unit at the bottom of the gate structure is too close, which affects the width of the forward conduction path in the first doped protection layer 140 and limits the degree to which the resistance of the forward conduction path can be reduced. Therefore, a preferred range of the longitudinal distance between the surface of the well region 150 facing the semiconductor substrate layer 100 and the surface of the first doped protection layer 140 facing the semiconductor substrate layer 100 is 0.3 to 1.5 microns.

[0062] In other embodiments, there is no limitation on the longitudinal distance between the surface of the well region 150 facing the semiconductor substrate layer 100 and the surface of the first doping protection layer 140 facing the semiconductor substrate layer 100 .

[0063] In one embodiment, the doping concentration of the second doped protection layer 130 is 2 to 10 times the doping concentration of the drift layer 110, for example, 2 times, 5 times, or 10 times. In one embodiment, for example, the doping concentration of the second doped protection layer 130 is 1E16 atom / cm 3 ~2E17atom / cm 3If the doping concentration of the second doped protection layer 130 is too high, the PN junction formed by the second doped protection layer 130 and the first doped protection layer 140 will easily break down prematurely when the electric field is too high in the reverse blocking state, and the degree of protection for the gate dielectric layer will be small. If the doping concentration of the second doped protection layer 130 is too low, the effect of the protection unit in alleviating the electric field concentration at the bottom gate dielectric layer in the gate structure will be weakened, which is not conducive to further improving the effect of protecting the gate dielectric layer.

[0064] In one embodiment, the second doping protection layer 130 is located on both sides of the first doping protection layer 140 along the width direction of the gate structure and further surrounds a surface of the first doping protection layer 140 facing the semiconductor substrate layer 100 .

[0065] In one embodiment, the doping concentration of the first doping protection layer 140 is greater than the doping concentration of the second doping protection layer 130. Since the area of ​​the second doping protection layer 130 is larger than that of the first doping protection layer 140, it is necessary to set the doping concentration of the first doping protection layer 140 to be greater than the doping concentration of the second doping protection layer 130 to achieve charge balance between the first doping protection layer 140 and the second doping protection layer 130 as much as possible, so that the depletion between the first doping protection layer 140 and the second doping protection layer 130 is more sufficient.

[0066] In one embodiment, the second doping protection layer 130 has a thickness of 0.1 micrometer to 2 micrometers, for example, 0.1 micrometer, 0.5 micrometer, 1 micrometer, 1.5 micrometers, or 2 micrometers.

[0067] In one embodiment, the thickness of the first doped protection layer 140 is 0.1 micron to 2 microns, for example, 0.1 micron, 0.5 micron, 1 micron, 1.5 microns, or 2 microns. The surface of the second doped protection layer 130 located on the sidewall of the gate structure facing away from the semiconductor substrate layer 100 contacts the surface of the channel region 151 facing the semiconductor substrate layer 100.

[0068] It should be noted that when the semiconductor power device is forward-conducting, electrons flow from the first source region 160 through the channel region 151 and the second doped protection layer 130 at the bottom of the channel region 151, and continue downward to the drain electrode layer 180. Because the doping concentration of the second doped protection layer 130 is greater than the doping concentration of the drift layer 110, the forward on-resistance is reduced.

[0069] Another embodiment of the present invention provides a semiconductor power device. Referring to FIG. 2 , this embodiment differs from the embodiment corresponding to FIG. 1 in that the second doping protection layer 130 is located on both sides of the first doping protection layer 140a along the width direction of the gate structure and does not surround the surface of the first doping protection layer 140a facing the semiconductor substrate layer 100. This increases the thickness of the first doping protection layer 140a, further distances the gate dielectric layer in the bottom region of the gate structure from the electric field peak at the depletion location of the PN junction formed by the first doping protection layer 140a and the second doping protection layer 130, and provides better protection for the gate dielectric layer in the bottom region of the gate structure.

[0070] In one embodiment, the second doping protection layer 130 has a thickness of 0.1 micrometer to 2 micrometers, for example, 0.1 micrometer, 0.5 micrometer, 1 micrometer, 1.5 micrometers, or 2 micrometers.

[0071] In one embodiment, the thickness of the first doping protection layer 140 a is 0.1 micrometer to 2 micrometers, for example, 0.1 micrometer, 0.5 micrometer, 1 micrometer, 1.5 micrometers, or 2 micrometers.

[0072] The doping concentration of the first doping protection layer 140a is similar to that of the previous embodiment. The doping concentration of the second doping protection layer 130 is similar to that of the previous embodiment. The other structures of this embodiment refer to the description of the embodiment corresponding to FIG1 and are not described in detail here.

[0073] Another embodiment of the present invention provides a semiconductor power device. Referring to Figure 3, the difference between this embodiment and the semiconductor power device corresponding to Example 1 is that: the well region includes a first well region 1501a and a second well region 1502a on the side of the first well region 1501a facing the semiconductor substrate layer 100, and the second well region 1502a is in contact with the first well region 1501a; a portion of the first well region 1501a serves as a channel region 151; and the second doping protection layer 130 on the side wall of the gate structure is located between the second well region 1502a and the gate structure.

[0074] In one embodiment, the doping concentration of the second well region 1502 a is less than the doping concentration of the first well region 1501 a outside the channel region 151 .

[0075] Since the second well region 1502a is in contact with the second doped protection layer 130 on the side wall of the gate structure, the longitudinal distance between the interface position of the second well region 1502a and the drift layer 110 at the bottom of the second well region 1502a and the surface of the first doped protection layer 140 facing the semiconductor substrate layer 100 is relatively small, so that the depletion of the drift layer 110 at the bottom of the second well region 1502a and the second well region 1502a can better protect the gate dielectric layer.

[0076] A surface of the second doping protection layer 130 located on the sidewall of the gate structure facing away from the semiconductor substrate layer 100 contacts a surface of the channel region 151 facing the semiconductor substrate layer 100 .

[0077] In one embodiment, the longitudinal distance between the surface of the well region 150 facing the semiconductor substrate layer 100 and the surface of the first doping protection layer 140 facing the semiconductor substrate layer 100 is 0.3 microns to 1.5 microns. Specifically, the longitudinal distance between the surface of the second well region 1502a facing the semiconductor substrate layer 100 and the surface of the first doping protection layer 140 facing the semiconductor substrate layer 100 is 0.3 microns to 1.5 microns.

[0078] In one embodiment, the doping concentration of the first doping protection layer 140 is greater than the doping concentration of the second doping protection layer 130 .

[0079] Other identical contents of the semiconductor power device in this embodiment and in the first embodiment will not be described in detail.

[0080] Another embodiment of the present invention provides a semiconductor power device. Referring to FIG. 4 , this embodiment differs from the semiconductor power device corresponding to FIG. 3 in that the second doping protection layer 130 is located on both sides of the first doping protection layer 140a along the width direction of the gate structure and does not surround the surface of the first doping protection layer 140a facing the semiconductor substrate layer 100. This increases the thickness of the first doping protection layer 140a, further distances the gate dielectric layer in the bottom region of the gate structure from the electric field peak at the depletion location of the PN junction formed by the first doping protection layer 140a and the second doping protection layer 130, and provides better protection for the gate dielectric layer in the bottom region of the gate structure.

[0081] In one embodiment, the second doping protection layer 130 has a thickness of 0.1 micrometer to 2 micrometers, for example, 0.1 micrometer, 0.5 micrometer, 1 micrometer, 1.5 micrometers, or 2 micrometers.

[0082] In one embodiment, the thickness of the first doping protection layer 140 a is 0.1 micrometer to 2 micrometers, for example, 0.1 micrometer, 0.5 micrometer, 1 micrometer, 1.5 micrometers, or 2 micrometers.

[0083] The doping concentration of the first doping protection layer 140 a and the doping concentration of the second doping protection layer 130 are similar to those of the above embodiment.

[0084] Regarding other structures of this embodiment, please refer to the description of the embodiment corresponding to FIG3 and will not be described in detail.

[0085] Another embodiment of the present invention also provides a method for preparing a semiconductor power device, the method comprising: forming a drift layer on one side of a semiconductor substrate layer; and forming a gate structure, a well region, and a protection unit in the drift layer, wherein the well regions are respectively located in the drift layer on both sides of the gate structure, and the protection unit surrounds the bottom surface and a portion of the sidewalls of the gate structure. Forming the protection unit comprises: forming a first doped protection layer, wherein the first doped protection layer is located in the drift layer at the bottom portion of the gate structure; and forming a second doped protection layer, wherein the second doped protection layer is located in the drift layer at a portion of the sidewalls and a portion of the bottom portion of the gate structure, wherein the conductivity type of the first doped protection layer is the same as the conductivity type of the well region and is opposite to the conductivity type of the second doped protection layer, the doping concentration of the second doped protection layer is greater than the doping concentration of the drift layer, and the second doped protection layer and the first doped protection layer form a PN junction.

[0086] In one embodiment, the process of forming the gate structure, the well region, and the protection unit in the drift layer includes: forming a first doping region in the drift layer extending from a surface of the drift layer facing away from the semiconductor substrate to a portion of the thickness; forming initial well regions in the drift layer on both sides of the first doping region and in the first doping region, wherein the doping concentration of the initial well region in the first doping region is less than the doping concentration of the initial well regions on both sides of the first doping region, and a surface of the initial well region in the first doping region facing the semiconductor substrate layer is farther away from the semiconductor substrate layer than a surface of the first doping region facing the semiconductor substrate layer; forming a trench in the first doping region that penetrates the initial well region in the first doping region and extends to the bottom of the initial well region, wherein the lateral dimension of the trench is smaller than the lateral dimension of the first doping region, and a bottom surface of the trench is farther away from the semiconductor substrate layer than a surface of the first doping region facing the semiconductor substrate layer; wherein the remaining initial well region around the trench forms the well region, and the remaining first doping region around the trench forms the second doped protection layer; and after forming the trench, forming a first doped protection layer in the drift layer at a portion of the bottom of the trench.

[0087] The following describes in detail the method for preparing a semiconductor power device with reference to FIG. 5 to FIG. 13 .

[0088] 5 , a drift layer 110 is formed on one side of a semiconductor substrate layer 100 .

[0089] The material description of the drift layer 110 and the material description of the semiconductor substrate layer 100 refer to the contents of the aforementioned embodiment and will not be described in detail.

[0090] The formation process of the drift layer 110 includes an epitaxial process.

[0091] 6 , a first doped region 200 is formed in the drift layer 110 , extending from a surface of the drift layer 110 facing away from the semiconductor substrate 100 to a portion of the thickness of the drift layer 110 .

[0092] The process of forming the first doping region 200 includes an ion implantation process.

[0093] The doping concentration of the first doping region 200 is greater than the doping concentration of the drift layer 110 , and the conductivity type of the first doping region 200 is the same as that of the drift layer 110 .

[0094] Referring to Figure 7, initial well regions are formed in the drift layer 110 on both sides of the first doping region 200 and in the first doping region 200, the doping concentration of the initial well region 220 in the first doping region 200 is less than the doping concentration of the initial well regions 210 on both sides of the first doping region 200, and the side surface of the initial well region 220 in the first doping region 200 facing the semiconductor substrate layer 100 is away from the semiconductor substrate layer 100 relative to the side surface of the first doping region 200 facing the semiconductor substrate layer 100.

[0095] In one embodiment, the initial well regions 210 on both sides of the first doping region 200 have their surfaces facing the semiconductor substrate layer 100 farther away from the semiconductor substrate layer 100 than the surface of the first doping region 200 facing the semiconductor substrate layer 100 .

[0096] In one embodiment, a surface of the initial well region 220 in the first doping region 200 facing the semiconductor substrate layer 100 is flush with surfaces of the initial well regions 210 on both sides of the first doping region 200 facing the semiconductor substrate layer 100 .

[0097] The process for forming the initial well region includes an ion implantation process. During the process of forming the initial well region in the drift layer 110 on both sides of the first doping region 200 and in the first doping region 200, a portion of the well ions implanted into the first doping region 200 by the ion implantation process will neutralize with the doping ions in the first doping region 200. As a result, the doping concentration of the formed initial well region 220 is lower than the doping concentration of the initial well region 210.

[0098] 8 , a first initial source region 230 and a second source region 170 are formed in the drift layer 110. The conductivity type of the first initial source region 230 is the same as that of the drift layer 110 and is opposite to that of the second source region 170. The second source region 170 is located on both sides of the first initial source region 230.

[0099] The process of forming the first preliminary source region 230 includes an ion implantation process. The process of forming the second source region 170 includes an ion implantation process.

[0100] Referring to Figure 9, a trench C is formed in the first doping region 200, which penetrates the initial well region 220 in the first doping region 200 and extends to the bottom of the initial well region 220. The lateral dimension of the trench C is smaller than the lateral dimension of the first doping region 200, and the bottom surface of the trench C is away from the semiconductor substrate layer 100 relative to the surface of the first doping region 200 on the side facing the semiconductor substrate layer 100. The remaining initial well region around the trench C forms a well region 150, the remaining first doping region 200 around the trench C forms a second doping protection layer 130, and the remaining first initial source region 230 around the trench C forms a first source region 160.

[0101] The well region 150 is located on both sides of the gate structure along the width direction. The first source region 160 is located on both sides of the gate structure along the width direction.

[0102] The remaining initial well regions 210 and 220 around the trench C form the well region 150 .

[0103] Since the doping concentration of the initial well region 220 is lower than that of the initial well region 210 , and the remaining initial well region 220 around the trench C constitutes the channel region 151 , the doping concentration of the channel region 151 is lower than that of the well region 150 outside the channel region 151 .

[0104] In this embodiment, the method for preparing a semiconductor power device also includes: before forming the trench C, forming a mask layer Y on a partial area of ​​the first initial source region 230 and the second source region 170; etching the initial well region 220 and the first doped region 200 at the bottom of the initial well region 220 using the mask layer Y as a mask to form a trench C in the first doped region 200 that penetrates the initial well region 220 and extends to the bottom of the initial well region 220.

[0105] The material of the mask layer Y includes photoresist or silicon oxide.

[0106] In this embodiment, ion compensation is used to make the doping concentration of the initial well region 220 lower than the doping concentration of the initial well region 210. The well region 150 is formed during the process of forming the trench C. This further makes the doping concentration of the channel region 151 lower than the doping concentration of the well region 150 outside the channel region 151. No additional process steps are required to form the channel region 151 separately. This ensures that the position of the channel region 151 is more precise and that it is well aligned with other structures in the channel region 151.

[0107] In one embodiment, referring to FIG. 9 , a surface of the channel region 151 facing the semiconductor substrate layer 100 is flush with a surface of the well region 150 outside the channel region 151 facing the semiconductor substrate layer 100 .

[0108] Since the second doping protection layer 130 is formed by the first doping region 200 remaining around the trench C, and the first doping region 200 is formed before the trench C is formed, the edge position and edge morphology of the first doping region 200 can be well controlled, so the morphology and size of the formed second doping protection layer 130 can be well controlled without increasing the size of the cell.

[0109] It should be noted that if an ion implantation process is used to form a second doped protective layer after the trench is formed, the ions need to be implanted obliquely at the sidewalls of the trench and vertically at the bottom of the trench. The implantation requires multiple steps, and it is difficult to control the edge morphology of the second doped protective layer formed by the implantation in the process. Secondly, it is easy to make the size of the second doped protective layer larger than the designed size, and the size of the cell will increase.

[0110] 10 , a sidewall spacer Y1 is formed on the sidewall of the trench C.

[0111] The process of forming the sidewall Y1 includes: forming initial sidewalls on the sidewalls and bottom wall of the trench C; etching the initial sidewalls to remove the initial sidewalls on the bottom wall of the trench C, and the remaining initial sidewalls on the sidewalls of the trench C form the sidewall Y1.

[0112] The material of the sidewall spacer Y1 includes silicon oxide or silicon nitride.

[0113] 10 , after the trench C is formed, a first doping protection layer 140 is formed in the drift layer 110 at a portion of the bottom of the trench C.

[0114] The process of forming the first doped protection layer 140 in the drift layer 110 at the bottom portion of the trench C is as follows: ion implantation is performed on the drift layer 110 at the bottom portion of the trench C using the sidewall Y1 as a mask to form the first doped protection layer 140. Furthermore, ion implantation is performed on the drift layer 110 at the bottom portion of the trench C using the sidewall Y1 and the mask layer Y as masks to form the first doped protection layer 140. The sidewall Y1 defines the edge position of the first doped protection layer 140 and protects the sidewall structure of the trench C.

[0115] It should be noted that, in other embodiments, the sidewall spacer Y1 may not be formed.

[0116] The second doping protection layer 130 is located on both sides of the first doping protection layer 140 along the width direction of the gate structure and further surrounds a surface of the first doping protection layer 140 facing the semiconductor substrate layer 100 .

[0117] 11 , after forming the first doping protection layer 140 , the sidewall spacer Y1 is removed.

[0118] 12 , after the first doping protection layer 140 is formed, the mask layer Y is removed.

[0119] It should be noted that the order of removing the spacer Y1 and the step of removing the mask layer Y can be adjusted, that is, removing the spacer Y1 followed by the mask layer Y, or removing the mask layer Y followed by the spacer Y1.

[0120] 13 , a gate structure is formed in the trench C. The gate structure includes a gate dielectric layer 121 and a gate electrode layer 122 . A drain electrode layer 180 is formed on a surface of the semiconductor substrate layer 100 facing away from the drift layer 110 .

[0121] Another embodiment of the present invention further provides a method for fabricating a semiconductor power device. This embodiment differs from the previous embodiment in that the second doping protection layer is located on both sides of the first doping protection layer 140a along the width direction of the gate structure and does not surround the surface of the first doping protection layer 140a facing the semiconductor substrate layer 100.

[0122] The following describes a method for manufacturing a semiconductor power device with reference to FIG. 14 to FIG. 16 .

[0123] 14 , which is a schematic diagram based on FIG. 9 , a sidewall Y1 is formed on the sidewall of the trench C; and a first doped protection layer 140 a is formed in the drift layer 110 at a portion of the bottom of the trench C.

[0124] The process of forming the first doped protection layer 140a in the drift layer 110 at the bottom of part of the trench C is an ion implantation process, and the depth of the ion implantation process is controlled so that the second doped protection layer is located on both sides of the first doped protection layer 140a along the width direction of the gate structure and does not surround the surface of the first doped protection layer 140a facing the semiconductor substrate layer 100.

[0125] The process of forming the first doped protection layer 140a in the drift layer 110 at the bottom portion of the trench C is as follows: ion implantation is performed on the drift layer 110 at the bottom portion of the trench C using the sidewall Y1 as a mask to form the first doped protection layer 140a. Furthermore, ion implantation is performed on the drift layer 110 at the bottom portion of the trench C using the sidewall Y1 and the mask layer Y as masks to form the first doped protection layer 140a. The sidewall Y1 defines the edge position of the first doped protection layer 140a and protects the sidewall structure of the trench C.

[0126] It should be noted that, in other embodiments, the sidewall spacer Y1 may not be formed.

[0127] 15 , the sidewall spacer Y1 and the mask layer Y are removed.

[0128] 16 , a gate structure is formed in the trench C. The gate structure includes a gate dielectric layer 121 and a gate electrode layer 122 . A drain electrode layer 180 is formed on a surface of the semiconductor substrate layer 100 facing away from the drift layer 110 .

[0129] The contents of this embodiment that are the same as those of the previous embodiment will not be described in detail.

[0130] Another embodiment of the present invention also provides a method for preparing a semiconductor power device. The difference between this embodiment and the method for preparing a semiconductor power device of the corresponding embodiments of Figures 5 to 13 is that the surface of the side of the initial well region in the first doping region facing the semiconductor substrate layer is away from the semiconductor substrate layer relative to the surface of the side of the initial well region facing the semiconductor substrate layer on both sides of the first doping region.

[0131] The following describes a method for manufacturing a semiconductor power device with reference to FIG. 17 to FIG. 23 .

[0132] Referring to Figure 17, Figure 17 is a schematic diagram based on Figure 6. Initial well regions are formed in the drift layer 110 on both sides of the first doping region 200 and in the first doping region 200. The doping concentration of the initial well region 220a in the first doping region 200 is less than the doping concentration of the initial well regions 210 on both sides of the first doping region 200. The side surface of the initial well region 220a in the first doping region 200 facing the semiconductor substrate layer 100 is away from the semiconductor substrate layer 100 relative to the side surface of the first doping region 200 facing the semiconductor substrate layer 100.

[0133] In one embodiment, the initial well regions 210 on both sides of the first doping region 200 have their surfaces facing the semiconductor substrate layer 100 farther away from the semiconductor substrate layer 100 than the surface of the first doping region 200 facing the semiconductor substrate layer 100 .

[0134] In one embodiment, the initial well region 220 a in the first doping region 200 faces the semiconductor substrate layer 100 and is further away from the semiconductor substrate layer 100 than the initial well regions 210 on both sides of the first doping region 200 face the semiconductor substrate layer 100 .

[0135] The process for forming the initial well region includes an ion implantation process. During the process of forming the initial well region in the drift layer 110 on both sides of the first doping region 200 and in the first doping region 200, a portion of the well ions implanted into the first doping region 200 by the ion implantation process will neutralize with the doping ions in the first doping region 200. As a result, the doping concentration of the formed initial well region 220a is lower than the doping concentration of the initial well region 210.

[0136] In one embodiment, the concentration distribution of the trapped ions implanted in the first doping region 200 during the ion implantation process for forming the initial well region generally follows a regular pattern along the thickness direction: the concentration in the middle region of the region where the trapped ions are implanted is higher, and the concentration in the region near the bottom surface of the first doping region 200 is lower. In other words, the concentration of the trapped ions in the first doping region 200 in the partial region near the bottom surface of the first doping region 200 is relatively low. Therefore, the trapped ions in the partial region near the bottom surface of the first doping region 200 are neutralized by the doping ions in the first doping region 200, and the partial region near the bottom surface of the first doping region 200 with the trapped ions exhibits the conductivity type of the first doping region 200. For regions with a relatively high concentration of trapped ions in the first doping region 200, some of the trapped ions are neutralized by the doping ions in the first doping region 200, and the remaining trapped ions in the region make the conductivity type of the region opposite to that of the first doping region 200, forming the initial well region 220a.

[0137] 18 , a first initial source region 230 and a second source region 170 are formed in the drift layer 110. The conductivity type of the first initial source region 230 is the same as that of the drift layer 110 and is opposite to that of the second source region 170. The second source region 170 is located on both sides of the first initial source region 230.

[0138] The process of forming the first preliminary source region 230 includes an ion implantation process. The process of forming the second source region 170 includes an ion implantation process.

[0139] Referring to Figure 19, a trench C1 is formed in the first doping region 200, which penetrates the initial well region 220a in the first doping region 200 and extends to the bottom of the initial well region 220a. The lateral dimension of the trench C1 is smaller than the lateral dimension of the first doping region 200, and the bottom surface of the trench C1 is away from the semiconductor substrate layer 100 relative to the surface of the first doping region 200 on the side facing the semiconductor substrate layer 100. The remaining initial well region around the trench C1 forms a well region 150a, the remaining first doping region 200 around the trench C1 forms a second doping protection layer 130, and the remaining first initial source region 230 around the trench C1 forms a first source region 160.

[0140] The well regions 150a are located on both sides of the gate structure along the width direction. The first source regions 160 are located on both sides of the gate structure along the width direction.

[0141] The remaining initial well region 210 and the initial well region 220 a around the trench C1 form the well region 150 a .

[0142] Since the doping concentration of the initial well region 220 a is lower than that of the initial well region 210 , and the remaining initial well region 220 a around the trench C1 constitutes the channel region 151 , the doping concentration of the channel region 151 is lower than that of the well region 150 a outside the channel region 151 .

[0143] In this embodiment, the method for manufacturing a semiconductor power device further includes: before forming the trench C1, forming a mask layer Y on a portion of the first initial source region 230 and the second source region 170; and etching the initial well region 220a and the first doped region 200 at the bottom of the initial well region 220a using the mask layer Y as a mask to form a trench C1 in the first doped region 200 that penetrates the initial well region 220a and extends to the bottom of the initial well region 220a. The material of the mask layer Y includes photoresist or silicon oxide.

[0144] The well region 150a includes a first well region 1501a (refer to Figure 23) and a second well region 1502a (refer to Figure 23) on the side of the first well region 1501a facing the semiconductor substrate layer 100, and the second well region 1502a is in contact with the first well region 1501a; a portion of the first well region 1501a serves as a channel region 151; the second doping protection layer 130 on the side wall of the gate structure is located between the second well region 1502a and the gate structure.

[0145] In one embodiment, the doping concentration of the second well region 1502 a is less than the doping concentration of the first well region 1501 a outside the channel region 151 .

[0146] Since the second well region 1502a is in contact with the second doped protection layer 130 on the side wall of the gate structure, the longitudinal distance between the interface position of the second well region 1502a and the drift layer 110 at the bottom of the second well region 1502a and the surface of the first doped protection layer 140 facing the semiconductor substrate layer 100 is relatively small, so that the depletion of the drift layer 110 at the bottom of the second well region 1502a and the second well region 1502a can better protect the gate dielectric layer.

[0147] 20 , a sidewall Y1 is formed on the sidewall of the trench C1 . After the trench C1 is formed, a first doping protection layer 140 is formed in the drift layer 110 at a portion of the bottom of the trench C1 .

[0148] The process of forming the first doped protection layer 140 in the drift layer 110 at the bottom portion of the trench C1 is as follows: ion implantation is performed on the drift layer 110 at the bottom portion of the trench C1 using the sidewall Y1 as a mask to form the first doped protection layer 140. Furthermore, ion implantation is performed on the drift layer 110 at the bottom portion of the trench C1 using the sidewall Y1 and the mask layer Y as masks to form the first doped protection layer 140.

[0149] It should be noted that, in other embodiments, the sidewall spacer Y1 may not be formed.

[0150] The second doping protection layer 130 is located on both sides of the first doping protection layer 140 along the width direction of the gate structure and further surrounds a surface of the first doping protection layer 140 facing the semiconductor substrate layer 100 .

[0151] 21 , after forming the first doping protection layer 140 , the sidewall spacer Y1 is removed; and after forming the first doping protection layer 140 , the mask layer Y is removed.

[0152] The mask layer Y is removed after the sidewall spacer Y1 is removed, or the mask layer Y is removed before the sidewall spacer Y1 is removed.

[0153] 22 , a gate structure is formed in the trench C, the gate structure including a gate dielectric layer 121 and a gate electrode layer 122 ; and a drain electrode layer 180 is formed on a surface of the semiconductor substrate layer 100 facing away from the drift layer 110 .

[0154] Another embodiment of the present invention also provides a method for preparing a semiconductor power device. The difference between this embodiment and the previous embodiment is that the second doping protection layer 130 is located on both sides of the first doping protection layer 140a along the width direction of the gate structure and does not surround the surface of the first doping protection layer 140a facing the semiconductor substrate layer 100.

[0155] The following describes a method for manufacturing a semiconductor power device with reference to FIG. 24 and FIG. 25 .

[0156] 24 , which is a schematic diagram based on FIG. 19 , a sidewall Y1 is formed on the sidewall of the trench C1 ; and a first doped protection layer 140 a is formed in the drift layer 110 at a portion of the bottom of the trench C1 .

[0157] The process of forming the first doped protection layer 140a in the drift layer 110 at the bottom of part of the trench C1 is an ion implantation process, and the depth of the ion implantation process is controlled so that the second doped protection layer 130 is located on both sides of the first doped protection layer 140a along the width direction of the gate structure and does not surround the surface of the first doped protection layer 140a facing the semiconductor substrate layer 100.

[0158] The process of forming the first doped protection layer 140a in the drift layer 110 at the bottom portion of the trench C1 is as follows: ion implantation is performed on the drift layer 110 at the bottom portion of the trench C1 using the sidewall Y1 as a mask to form the first doped protection layer 140a. Furthermore, ion implantation is performed on the drift layer 110 at the bottom portion of the trench C1 using the sidewall Y1 and the mask layer Y as masks to form the first doped protection layer 140a.

[0159] It should be noted that, in other embodiments, the sidewall spacer Y1 may not be formed.

[0160] Referring to Figure 25, the side wall Y1 and the mask layer Y are removed; after removing the side wall Y1 and the mask layer Y, a gate structure is formed in the trench C1, and the gate structure includes a gate dielectric layer 121 and a gate electrode layer 122; a drain electrode layer 180 is formed on the surface of the side of the semiconductor substrate layer 100 away from the drift layer 110.

[0161] Obviously, the above embodiments are merely examples for clarity of explanation and are not intended to limit the implementation methods. Those skilled in the art will readily appreciate that other variations or modifications based on the above descriptions are possible. It is not necessary and impossible to enumerate all implementation methods here. Obvious variations or modifications arising therefrom remain within the scope of protection of the present invention.

Claims

1. A semiconductor power device, characterized in that: The semiconductor power device comprises: semiconductor substrate layer; a drift layer located on one side of the semiconductor substrate layer; a gate structure located in the drift layer; Well regions are respectively located in the drift layer on both sides of the gate structure; and a protection unit in the drift layer surrounding the bottom surface and part of the sidewall of the gate structure, The protection unit includes: a first doped protection layer, located in the drift layer at the bottom of the gate structure; and a second doped protection layer, located in the drift layer on part of the sidewall and part of the bottom of the gate structure, the conductivity type of the first doped protection layer is the same as the conductivity type of the well region and is opposite to the conductivity type of the second doped protection layer, the doping concentration of the second doped protection layer is greater than the doping concentration of the drift layer, and the second doped protection layer and the first doped protection layer form a PN junction.

2. The semiconductor power device according to claim 1, wherein: Part of the well region serves as a channel region, the channel region contacts a sidewall of the gate structure, and a doping concentration of the channel region is lower than a doping concentration of the well region outside the channel region.

3. The semiconductor power device according to claim 2, characterized in that The doping concentration of the channel region is 1E16atom / cm 3 ~5E17atom / cm 3 The doping concentration of the well region outside the channel region is 5E16atom / cm 3 ~2E18atom / cm 3 .

4. The semiconductor power device according to claim 1, wherein: The well region includes a first well region and a second well region on the side of the first well region facing the semiconductor substrate layer, the second well region is in contact with the first well region, a portion of the first well region serves as a channel region, and the second doping protection layer on the side wall of the gate structure is located between the second well region and the gate structure.

5. The semiconductor power device according to claim 4, characterized in that: The doping concentration of the second well region is lower than the doping concentration of the first well region outside the channel region.

6. The semiconductor power device according to claim 2, wherein: A surface of the channel region facing the semiconductor substrate layer is flush with a surface of the well region outside the channel region facing the semiconductor substrate layer.

7. The semiconductor power device according to claim 1, 4 or 6, characterized in that: A longitudinal distance between a surface of the well region facing the semiconductor substrate layer and a surface of the first doping protection layer facing the semiconductor substrate layer is 0.3 micrometers to 1.5 micrometers.

8. The semiconductor power device according to claim 1, wherein: The doping concentration of the second doping protection layer is 2 to 10 times the doping concentration of the drift layer.

9. The semiconductor power device according to claim 1, wherein: The second doping protection layer is located on both sides of the first doping protection layer along the width direction of the gate structure and does not surround the surface of the first doping protection layer facing the semiconductor substrate layer. Alternatively, the second doping protection layer is located on both sides of the first doping protection layer along the width direction of the gate structure and also surrounds the surface of the first doping protection layer facing the semiconductor substrate layer.

10. The semiconductor power device according to claim 1, wherein: The doping concentration of the first doping protection layer is greater than the doping concentration of the second doping protection layer.

11. The semiconductor power device according to claim 1, wherein: The semiconductor power device is a SiC-based semiconductor power device.

12. A method for preparing a semiconductor power device, characterized in that: The preparation method comprises: forming a drift layer on one side of the semiconductor substrate layer; and forming a gate structure, a well region and a protection unit in the drift layer, The well regions are respectively located in the drift layer on both sides of the gate structure, and the protection unit surrounds the bottom surface and part of the side wall of the gate structure. Forming the protection unit includes: forming a first doped protection layer, the first doped protection layer is located in the drift layer at the bottom of the gate structure; and forming a second doped protection layer, the second doped protection layer is located in the drift layer at part of the sidewall and part of the bottom of the gate structure, the conductivity type of the first doped protection layer is the same as the conductivity type of the well region and is opposite to the conductivity type of the second doped protection layer, the doping concentration of the second doped protection layer is greater than the doping concentration of the drift layer, and the second doped protection layer and the first doped protection layer form a PN junction.

13. The method for preparing a semiconductor power device according to claim 12, wherein: The process of forming the gate structure, the well region and the protection unit in the drift layer includes: forming a first doping region in the drift layer extending from a surface of the drift layer facing away from the semiconductor substrate to a portion of the thickness; forming initial well regions in the drift layer on both sides of the first doping region and in the first doping region, wherein the doping concentration of the initial well region in the first doping region is less than the doping concentration of the initial well regions on both sides of the first doping region, and a surface of the initial well region in the first doping region facing the semiconductor substrate layer is farther away from the semiconductor substrate layer than a surface of the first doping region facing the semiconductor substrate layer; forming a trench in the first doping region that penetrates the initial well region in the first doping region and extends to the bottom of the initial well region, wherein the lateral dimension of the trench is smaller than the lateral dimension of the first doping region, and the bottom surface of the trench is farther away from the semiconductor substrate layer than a surface of the first doping region facing the semiconductor substrate layer, wherein the remaining initial well region around the trench forms the well region, and the remaining first doping region around the trench forms the second doped protection layer; and after forming the trench, forming a first doped protection layer in the drift layer at a portion of the bottom of the trench.

14. The method for preparing a semiconductor power device according to claim 13, wherein: A surface of the initial well region in the first doping region facing the semiconductor substrate layer is flush with surfaces of the initial well regions on both sides of the first doping region facing the semiconductor substrate layer. Alternatively, a surface of the initial well region in the first doping region facing the semiconductor substrate layer is farther away from the semiconductor substrate layer than a surface of the initial well region on both sides of the first doping region facing the semiconductor substrate layer.

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