Solar cell and preparation method therefor

Abstract

The present disclosure provides a solar cell and a preparation method therefor. The solar cell comprises a silicon substrate; the silicon substrate comprises a first surface and a second surface which are oppositely arranged; a diffusion layer is formed on the first surface of the silicon substrate; the first surface comprises first areas and second areas distributed at intervals; the second surface comprises third areas and fourth areas distributed at intervals; each first area is provided with a first tunnel passivation structure and a first electrode; and each third area is provided with a second tunnel passivation structure and a second electrode.

Description

Solar cell and preparation method thereof

[0001] This application claims priority to the Chinese patent application filed with the China Patent Office on March 29, 2024 with application number 202410377188.5, the Chinese patent application filed with the China Patent Office on April 28, 2024 with application number 202410522507.7, and the Chinese patent application filed with the China Patent Office on March 10, 2025 with application number 202510282775.0, the entire contents of which are incorporated by reference into this application. Technical Field

[0002] The present application relates to the technical field of solar cells, for example, a solar cell and a method for preparing the same. Background Art

[0003] With the rapid development of the photovoltaic industry, the performance and efficiency requirements of solar cells in both domestic and international markets are constantly increasing. Consequently, industry manufacturers are focusing on the research and development of high-efficiency cells. TOPCon (Tunnel Oxide Passivated Contact) cells utilize an ultra-thin tunnel oxide layer and a doped polysilicon layer sequentially deposited on the back of the cell. This improves the cell's surface passivation, reduces the metal contact recombination current, and effectively increases the cell's open-circuit voltage and short-circuit current.

[0004] The TOPCon battery of related technology is usually a single-sided TOPCon structure, and the emitter is usually prepared by a boron diffusion process on the front. Due to the low diffusion doping concentration, the contact resistance with the metal electrode is high. At the same time, the metal is in direct contact with the silicon substrate, and the recombination of the metal area is still relatively high, resulting in a large reverse saturation current, which limits the improvement of battery efficiency.

[0005] Therefore, in order to solve the above technical problems, it is necessary to provide a solar cell and a method for preparing the same. Summary of the Invention

[0006] The following is a summary of the subject matter described in detail herein. This summary is not intended to limit the scope of the claims.

[0007] The present application provides a solar cell and a method for preparing the same, in order to improve cell efficiency and optimize the preparation process.

[0008] The technical solution provided by an embodiment of the present application is as follows:

[0009] A solar cell includes a silicon substrate, the silicon substrate including a first surface and a second surface arranged opposite to each other, a diffusion layer formed on the first surface of the silicon substrate, the first surface including a first region and a second region distributed at intervals, the second surface including a third region and a fourth region distributed at intervals, the first region being provided with a first tunneling passivation structure and a first electrode, and the third region being provided with a second tunneling passivation structure and a second electrode.

[0010] In one embodiment, the first surface of the silicon substrate is recessed in the second region relative to the first region; and / or,

[0011] The second surface of the silicon substrate is recessed relative to the third region in a fourth region.

[0012] In one embodiment, the first surface of the silicon substrate is recessed in the second region to a depth of 1 μm to 6 μm; and / or,

[0013] The second surface of the silicon substrate is recessed in the fourth region to a depth of 1 μm to 6 μm.

[0014] In one embodiment, a height difference between a surface of the first tunneling passivation structure facing away from the silicon substrate and the first surface of the silicon substrate in the second region is 0.1 μm to 6 μm; and / or,

[0015] A height difference between a surface of the second tunneling passivation structure facing away from the silicon substrate and the second surface of the silicon substrate in the fourth region is 0.1 μm to 6 μm.

[0016] In one embodiment, the diffusion layer includes a first diffusion layer located in the first region and a second diffusion layer located in the second region.

[0017] In one embodiment, the doping concentration of the second diffusion layer is greater than the doping concentration of the first diffusion layer; and / or,

[0018] The doping concentration of the second diffusion layer is 1E18cm -3 ~5E19cm -3 and / or,

[0019] The doping concentration of the first diffusion layer is 1E17 cm -3 ~5E19cm -3 .

[0020] In one embodiment, the first tunneling passivation structure includes a first tunneling layer and a first doping layer stacked sequentially in the first region, the second tunneling passivation structure includes a second tunneling layer and a second doping layer stacked sequentially in the third region, the first electrode is electrically contacted with the first doping layer, the second electrode is electrically contacted with the second doping layer, the first doping layer and the diffusion layer have the same doping type, and the second doping layer and the first doping layer have a doping type opposite.

[0021] In one embodiment, the diffusion layer includes a first diffusion layer located in the first region, and the doping concentration of the first diffusion layer is lower than the doping concentration of the first doping layer.

[0022] In one embodiment, the first tunneling layer is any one or more combinations of a silicon oxide layer and a silicon oxynitride layer; and / or,

[0023] The thickness of the first tunneling layer is 1.5 nm to 2.5 nm or 1.8 nm to 2.2 nm; and / or,

[0024] The first doped layer is a doped polysilicon layer with a thickness of 80nm to 400nm or 200nm to 300nm;

[0025] The doping concentration of the first doping layer is 1E19cm -3 ~1E20cm -3 and / or,

[0026] The second tunneling layer is any one or more combinations of a silicon oxide layer and a silicon oxynitride layer; and / or,

[0027] The thickness of the second tunneling layer is 0.5 nm to 3 nm or 1.5 nm to 1.8 nm; and / or,

[0028] The second doped layer is a doped polysilicon layer with a thickness of 50 nm to 150 nm or 90 nm to 130 nm; and / or,

[0029] The silicon substrate is an N-type silicon substrate, the diffusion layer is a P-type diffusion layer, the first doping layer is a P-type doping layer, and the second doping layer is an N-type doping layer.

[0030] In one embodiment, a first passivation layer covering the first tunnel passivation structure and the second region of the silicon substrate is provided on the first surface of the silicon substrate, and a second passivation layer covering the second tunnel passivation structure and the fourth region of the silicon substrate is provided on the second surface of the silicon substrate.

[0031] In one embodiment, a height difference between the first region and the second region of the first passivation layer on a side facing away from the silicon substrate is 0.1 μm to 6 μm; and / or,

[0032] A height difference between the third region and the fourth region of the second passivation layer on a side facing away from the silicon substrate is 0.1 μm to 6 μm.

[0033] In one embodiment, the first passivation layer includes a combination of one or more layers selected from the group consisting of a silicon oxide layer, an aluminum oxide layer, a silicon nitride layer, and a silicon oxynitride layer; and / or,

[0034] The second passivation layer includes one or more layers selected from the group consisting of a silicon oxide layer, an aluminum oxide layer, a silicon nitride layer, and a silicon oxynitride layer.

[0035] In one embodiment, the first passivation layer comprises an aluminum oxide layer and a silicon nitride layer stacked in sequence, wherein the thickness of the aluminum oxide layer is 3 nm to 6 nm, and the thickness of the silicon nitride layer is 60 nm to 100 nm; and / or,

[0036] The second passivation layer includes an aluminum oxide layer and a silicon nitride layer stacked in sequence, wherein the thickness of the aluminum oxide layer is 3 nm to 6 nm, and the thickness of the silicon nitride layer is 60 nm to 100 nm.

[0037] In one embodiment, the first region in the first surface of the silicon substrate is a suede surface with a pyramid structure or a polished surface with a pyramid base, and the second region in the first surface of the silicon substrate is a suede surface with a pyramid structure.

[0038] In one embodiment, the base width of the pyramid structure in the first region is 0.5 μm to 1.5 μm, and the height is 0.3 μm to 1 μm; or, the base width of the pyramid structure in the first region is 1 μm to 5 μm, and the height of the pyramid structure is 0.1 μm to 0.4 μm; and / or,

[0039] The bottom width of the pyramid structure in the second region is 1.5 μm to 2.2 μm, and the height is 1 μm to 1.3 μm.

[0040] In one embodiment, the third region and the fourth region in the second surface of the silicon substrate are both polished surfaces.

[0041] In one embodiment, the width of the first region is 20 μm to 200 μm or 80 μm to 100 μm; and / or,

[0042] The width of the third region is 20 μm to 200 μm or 80 μm to 100 μm.

[0043] Another embodiment of the present application provides a technical solution as follows:

[0044] A method for preparing a solar cell, comprising the following steps:

[0045] Providing a silicon substrate, the silicon substrate comprising a first surface and a second surface opposite to each other, the first surface comprising a first region and a second region spaced apart from each other, and the second surface comprising a third region and a fourth region spaced apart from each other;

[0046] preparing a first tunneling passivation structure in a first region of the first surface, and then forming a diffusion layer below the first surface of the silicon substrate;

[0047] preparing a second tunneling passivation structure in a third region of the second surface;

[0048] A first electrode is formed on a first region of the first surface, and a second electrode is formed on a third region of the second surface.

[0049] In one embodiment, forming a first tunneling passivation structure in a first region of the first surface includes:

[0050] forming a first tunneling layer, a first intrinsic layer and a first mask layer on the first surface;

[0051] Using a laser process to pattern the first mask layer in the second area to expose the first intrinsic layer in the second area;

[0052] removing the first intrinsic layer and the first tunneling layer in the second region by a wet etching process to expose the silicon substrate in the second region;

[0053] removing the first mask layer in the first region to expose the first intrinsic layer in the first region;

[0054] The first intrinsic layer is transformed into a first doped layer by a diffusion process.

[0055] In one embodiment, the preparation method further comprises:

[0056] The first intrinsic layer and the first tunneling layer in the second region are removed by a wet etching process, and a portion of the silicon substrate in the second region is etched.

[0057] In one embodiment, the first intrinsic layer is an intrinsic polysilicon layer, the first tunneling layer is any one or more combinations of a silicon oxide layer and a silicon oxynitride layer, and the etching solution in the wet etching process is an alkaline solution; and / or,

[0058] The first mask layer is any one or more combinations of a silicon oxide layer, a silicon oxynitride layer, and a silicon nitride layer, and the first mask layer is removed using an acid solution; and / or,

[0059] The thickness of the first mask layer is 20 nm to 80 nm.

[0060] In one embodiment, the preparation method further comprises:

[0061] Before forming the first tunneling layer, the first intrinsic layer and the first mask layer on the first surface, a velvet surface having a pyramid structure is prepared on the first surface of the silicon substrate by an alkali texturing process, wherein the bottom width of the pyramid structure is 0.5 μm to 1.5 μm and the height is 0.3 μm to 1 μm; or, a polished surface having a tower base is prepared on the first surface of the silicon substrate by an alkali texturing process and an alkali polishing process, wherein the tower base has a width of 1 μm to 5 μm and a height of 0.1 μm to 0.4 μm;

[0062] After removing the first intrinsic layer and the first tunneling layer of the second area by a wet etching process, the second area on the first surface of the silicon substrate is subjected to an alkali texturing process to prepare a velvet surface with a pyramid structure, wherein the bottom width of the pyramid structure is 1.5μm to 2.2μm and the height is 1μm to 1.3μm.

[0063] In one embodiment, a one-step diffusion process is used to transform the first intrinsic layer into a first doped layer, and simultaneously a first diffusion layer and a second diffusion layer are formed in the first region and the second region of the first surface of the silicon substrate, respectively.

[0064] In one embodiment, the doping concentration of the first diffusion layer is lower than the doping concentration of the first doping layer, and the doping concentration of the second diffusion layer is higher than the doping concentration of the first diffusion layer.

[0065] In one embodiment, the preparation method further comprises:

[0066] An acid solution is used to remove the wrap-around layer generated on the second surface of the silicon substrate during the diffusion process;

[0067] The second surface of the silicon substrate is etched using an alkaline solution.

[0068] In one embodiment, forming a second tunneling passivation structure in the third region of the second surface includes:

[0069] forming a second tunneling layer, a second doping layer and a second mask layer on the second surface;

[0070] Using a laser process to pattern the second mask layer in the fourth region to expose the second doping layer in the fourth region;

[0071] removing the second doping layer and the second tunneling layer in the fourth region by a wet etching process to expose the silicon substrate in the fourth region;

[0072] The second mask layer in the third region is removed to expose the second doping layer in the third region.

[0073] In one embodiment, the preparation method further comprises:

[0074] The second doping layer and the second tunneling layer in the fourth region are removed by a wet etching process, and a portion of the silicon substrate in the fourth region is etched.

[0075] In one embodiment, the second doped layer is a doped polysilicon layer, the second tunneling layer is any one or more combinations of a silicon oxide layer and a silicon oxynitride layer, and the etching solution in the wet etching process is an alkaline solution; and / or,

[0076] The second mask layer is any one or more combinations of a silicon oxide layer, a silicon oxynitride layer, and a silicon nitride layer, and the second mask layer is removed using an acid solution; and / or,

[0077] The thickness of the second mask layer is 15 nm to 25 nm.

[0078] In one embodiment, the preparation method further comprises:

[0079] After the second doping layer and the second tunneling layer in the fourth region are removed by a wet etching process, an alkali polishing process is performed on the silicon substrate in the fourth region.

[0080] In one embodiment, the preparation method further comprises:

[0081] forming a first passivation layer on the first surface of the silicon substrate, and forming a first electrode in a first region of the first surface that penetrates the first passivation layer and is in electrical contact with the first tunneling passivation structure, wherein the first passivation layer comprises a combination of one or more layers of a silicon oxide layer, an aluminum oxide layer, a silicon nitride layer, and a silicon oxynitride layer; and / or,

[0082] A second passivation layer is prepared on the second surface of the silicon substrate, and a second electrode is prepared in a third area of ​​the second surface, which penetrates the second passivation layer and is in electrical contact with the second tunneling passivation structure. The second passivation layer includes a combination of one or more layers of a silicon oxide layer, an aluminum oxide layer, a silicon nitride layer, and a silicon oxynitride layer.

[0083] Compared with the related art, this application has the following beneficial effects:

[0084] The solar cell of the present application is a double-sided TOPCon cell, with local tunneling passivation structures on both the front and back sides, which ensures passivation contact of the front metal area and reduces parasitic absorption of the front non-metallic area, thereby significantly improving cell efficiency.

[0085] Still other aspects will become apparent upon reading and understanding the accompanying drawings and detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0086] To more clearly illustrate the technical solutions in the embodiments of this application or related technologies, the following briefly introduces the drawings required for use in the embodiments or related technology descriptions. Obviously, the drawings described below are only some of the embodiments described in this application. For those of ordinary skill in the art, other drawings can be derived from these drawings without inventive effort.

[0087] FIG1 is a schematic structural diagram of a solar cell in Example 1 of the present application;

[0088] FIG2 is a schematic diagram of a partially enlarged structure of point A in FIG1 ;

[0089] FIG3 is a schematic diagram of a partially enlarged structure of point B in FIG1 ;

[0090] Figures 4a to 4k are flow charts of the preparation process of the solar cell in Example 1 of the present application;

[0091] FIG5 is a schematic structural diagram of a solar cell in Example 3 of the present application;

[0092] FIG6 is a schematic structural diagram of a solar cell in Example 4 of the present application.

[0093] Explanation of main figure marks: 10-substrate, 11-diffusion layer, 111-first diffusion layer, 112-second diffusion layer, 21-first tunneling layer, 22-second tunneling layer, 31-first doping layer, 31'-first intrinsic layer, 32-second doping layer, 41-first electrode, 42-second electrode, 51-first passivation layer, 52-second passivation layer, 511-first aluminum oxide layer, 512-first silicon nitride layer, 521-second aluminum oxide layer, 522-second silicon nitride layer, 61-first mask layer, 62 second mask layer, S1-first surface, S11-first region, S12-second region, S2-second surface, S21-third region, S22-fourth region. DETAILED DESCRIPTION

[0094] In order to enable those skilled in the art to better understand the technical solutions in this application, the technical solutions in the embodiments of this application will be clearly and completely described below in conjunction with the drawings in the embodiments of this application. Obviously, the described embodiments are only part of the embodiments of this application, not all of the embodiments. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative work should fall within the scope of protection of this application.

[0095] In this application, unless otherwise expressly specified or limited, when a first feature is "above" or "below" a second feature, it may mean that the first and second features are in direct contact, or the first and second features are in indirect contact through an intermediate medium. Furthermore, when a first feature is "above," "above," or "above" a second feature, it may mean that the first feature is directly above or diagonally above the second feature, or simply means that the first feature is at a higher level than the second feature. When a first feature is "below," "below," or "below" a second feature, it may mean that the first feature is directly below or diagonally below the second feature, or simply means that the first feature is at a lower level than the second feature.

[0096] The present application discloses a solar cell, comprising a silicon substrate, the silicon substrate comprising a first surface and a second surface arranged opposite to each other, a diffusion layer formed on the first surface of the silicon substrate, the first surface comprising a first region and a second region distributed at intervals, the second surface comprising a third region and a fourth region distributed at intervals, the first region being provided with a first tunneling passivation structure and a first electrode, and the third region being provided with a second tunneling passivation structure and a second electrode.

[0097] The present application also discloses a method for preparing a solar cell, comprising the following steps:

[0098] Providing a silicon substrate, the silicon substrate comprising a first surface and a second surface opposite to each other, the first surface comprising a first region and a second region spaced apart from each other, and the second surface comprising a third region and a fourth region spaced apart from each other;

[0099] A first tunneling passivation structure is formed in a first region of the first surface, and a diffusion layer is formed below the first surface of the silicon substrate;

[0100] preparing a second tunneling passivation structure in a third region of the second surface;

[0101] A first electrode is formed on a first region of the first surface, and a second electrode is formed on a third region of the second surface.

[0102] The solar cell of the present application is a double-sided TOPCon cell, which has a local tunneling passivation structure on both the front and back sides, ensuring the passivation contact of the front metal area while reducing the parasitic absorption of the front non-metallic area. Compared with the single-sided TOPCon cell in the related art, the cell efficiency can be greatly improved.

[0103] The present application is further described below with reference to specific embodiments.

[0104] Example 1:

[0105] 1 and 2, and 3, the solar cell in this embodiment is a bifacial TOPCon cell, comprising a silicon substrate 10, the silicon substrate 10 comprising a first surface S1 and a second surface S2 arranged opposite to each other, the first surface S1 comprising a first region S11 and a second region S12 spaced apart, the second surface S2 comprising a third region S21 and a fourth region S22 spaced apart, the first surface S1 being the front side (i.e., the primary light-receiving surface) of the silicon substrate 10, the second surface S2 being the back side (i.e., the secondary light-receiving surface) of the silicon substrate 10, the first region S11 being the front side metal region, the second region S12 being the front side non-metal region, the third region S21 being the back side metal region, and the fourth region S22 being the back side non-metal region. Of course, in other embodiments, the first surface S1 may also be the back side (i.e., the secondary light-receiving surface) of the silicon substrate 10, and the second surface S2 being the front side (i.e., the primary light-receiving surface) of the silicon substrate 10.

[0106] In the bifacial TOPCon cell of this embodiment, first tunneling passivation structures are provided at intervals on the first surface S1, and second tunneling passivation structures are provided at intervals on the second surface S2. A diffusion layer 11 is formed on the entire first surface S1 through a diffusion process. Specifically, the first tunneling passivation structure includes a first tunneling layer 21 and a first doping layer 31 sequentially stacked in the first region S11, and the second tunneling passivation structure includes a second tunneling layer 22 and a second doping layer 32 sequentially stacked in the third region S21.

[0107] In addition, a first electrode 41 is provided on the first region S11 of the first surface S1, and the first electrode 41 is in electrical contact with the first doped layer 31. A second electrode 42 is provided on the third region S21 of the second surface S2, and the second electrode 42 is in electrical contact with the second doped layer 32. In this embodiment, the first doped layer 31 and the diffusion layer 11 have the same doping type, and the second doped layer 32 has a doping type opposite to that of the first doped layer 31.

[0108] Furthermore, in this embodiment, a first passivation layer 51 covering the first tunneling passivation structure and the second area S12 of the silicon substrate 10 is provided on the first surface S1 of the silicon substrate 10, and a second passivation layer 52 covering the second tunneling passivation structure and the fourth area S22 of the silicon substrate 10 is provided on the second surface S2 of the silicon substrate 10.

[0109] The materials, thickness, doping type, etc. of each layer in the solar cell of this embodiment are described in detail below.

[0110] The silicon substrate 10 in this embodiment is an N-type silicon substrate with a resistivity of 0.3 Ω·cm to 7 Ω·cm, optionally 0.5 Ω·cm to 3.5 Ω·cm. Optionally, a light-trapping structure is formed on the first surface S1 of the silicon substrate 10 in this embodiment. For example, a velvet surface having a pyramid structure can be produced by an alkali texturing process, or a polished surface having a pyramid base can be produced by an alkali texturing and alkali polishing process. The entire second surface S2 of the silicon substrate 10 is a polished surface with a reflectivity of 45% to 55%.

[0111] In this embodiment, the first tunneling layer 21 is a combination of any one or more of a silicon oxide layer, a silicon oxynitride layer, etc., with a thickness of 1.5 nm to 2.5 nm, and can be optionally 1.8 nm to 2.2 nm; the second tunneling layer 22 is a combination of any one or more of a silicon oxide layer, a silicon oxynitride layer, etc., with a thickness of 0.5 nm to 3 nm, and can be optionally 1.5 nm to 1.8 nm.

[0112] In this embodiment, both the first doped layer 31 and the second doped layer 32 can be a single doped polysilicon layer or multiple doped polysilicon layers with a gradient increasing doping concentration from the inside out (i.e., away from the silicon substrate). The thickness of the first doped layer 31 is 80 nm to 400 nm, optionally 200 nm to 300 nm; the thickness of the second doped layer 32 is 50 nm to 150 nm, optionally 90 nm to 130 nm. The first doped layer 31 is a P-type doped polysilicon layer, such as a boron-doped layer; the second doped layer 32 is an N-type doped polysilicon layer, such as a phosphorus-doped layer.

[0113] In addition, the silicon substrate in this embodiment is an N-type silicon substrate, and the diffusion layer 11 is a P-type diffusion layer. For example, a boron diffusion process is used to form a boron diffusion layer below the first surface S1 (i.e., inside the silicon substrate), thereby forming a PN junction. Electron-hole pairs are generated after light exposure, and the diffusion layer in the second region S12 can ensure a better photovoltaic effect, thereby increasing the current and improving the battery efficiency. For example, the doping concentration of the diffusion layer 11 is 1E19cm -3 ~1E20cm -3 .

[0114] Furthermore, in this embodiment, the first doped layer 31 is a P-type doped polysilicon layer formed by a diffusion process. For example, an intrinsic polysilicon layer is first deposited on the first tunneling layer 21, and then a boron diffusion process is used to convert the intrinsic polysilicon layer into a boron-doped polysilicon layer. Optionally, the first doped layer 31 and the diffusion layer 11 are formed using a one-step diffusion process.

[0115] 2 , the diffusion layer 11 in this embodiment includes a first diffusion layer 111 located in the first region S11 and a second diffusion layer 112 located in the second region S12. For example, the doping concentration of the second diffusion layer 112 is 1E18 cm -3~5E19cm -3 The doping concentration of the first diffusion layer 111 is 1E17 cm -3 ~5E19cm -3 .

[0116] Referring to FIG. 1 and FIG. 2 , in this embodiment, a first tunneling passivation structure is provided only in a first region S11 on the first surface S1 of the silicon substrate 10, while no first tunneling passivation structure is provided in a second region S12. Furthermore, the second region S12 of the silicon substrate 10 is recessed relative to the first region S11. The height of the surface of the first doped layer 31 in the first region S11, facing away from the silicon substrate, is higher than the height of the first surface S1 of the silicon substrate 10 in the second region S12. The height difference H1 between the two is the sum of the thickness of the first tunneling layer 21, the thickness of the first doped layer 31, and the depth of the recess in the second region S12. In this embodiment, the height difference H1 ranges from 0.1 μm to 6 μm. Optionally, the depth of the recess in the second region 12 relative to the first region S11 ranges from 1 μm to 6 μm. The magnitude of the height difference H1 is affected by the process and is typically at least 1 μm. A larger height difference H1 increases the frontal light-receiving area and improves light absorption, thereby further improving cell efficiency.

[0117] In addition, since the width of the second area S12 in the first surface S1 is larger and the width of the first area S11 is smaller, in order to ensure that the first surface S11 has a better light-trapping effect, a velvet surface with a better light-trapping effect needs to be formed on the second area S12, while a velvet surface with a poor light-trapping effect can be formed on the first area S11. The larger the size of the pyramid structure, the better the light-trapping effect.

[0118] For example, in this embodiment, the first region S11 of the first surface S1 is a velvet surface having a pyramid structure, wherein the base width of the pyramid structure is 1.5 μm to 2.2 μm and the height is 1 μm to 1.3 μm; and the second region S12 of the first surface S1 is a velvet surface having a pyramid structure, wherein the base width of the pyramid structure is 1.5 μm to 2.2 μm and the height is 1 μm to 1.3 μm. The velvet surface having a pyramid structure is formed after the alkali texturing process on the surface of the silicon substrate. The base shape of the pyramid structure can be a triangle, a quadrilateral, etc. The base width of the pyramid structure is defined as the average of the base widths of the pyramid structure. For example, if the base shape is a square, the base width is the side length of the square.

[0119] Referring to Figure 1 and in combination with Figure 3, on the second surface S2 of the silicon substrate 10 in this embodiment, a second tunneling passivation structure is provided only in the third region S21, and there is no second tunneling passivation structure in the fourth region S22, and the fourth region S22 of the silicon substrate 10 is recessed relative to the third region S21, and the height of the surface of the second doped layer 32 in the third region S21 facing away from the silicon substrate is higher than the height of the second surface S2 of the silicon substrate 10 in the fourth region S22, and the height difference H2 between the two is the sum of the thickness of the second tunneling layer 22, the thickness of the second doped layer 32 and the recess depth of the fourth region S22. In this embodiment, the height difference H2 is 0.1μm~6μm. Optionally, the recess depth of the fourth region S22 relative to the third region S21 is 1μm~6μm.

[0120] In addition, in this embodiment, a first passivation layer 51 and a second passivation layer 52 are stacked on the first surface S1 and the second surface S2 of the silicon substrate, respectively.

[0121] Specifically, the first passivation layer 51 covers the first tunnel passivation structure and the second region S12 of the silicon substrate 10, and the second passivation layer 52 covers the second tunnel passivation structure and the fourth region S22 of the silicon substrate 10. The first passivation layer 51 and the second passivation layer 52 can be silicon oxide (SiO X ) layer, aluminum oxide (AlO X ) layer, silicon nitride (SiN X ) layer and silicon oxynitride (SiN X O Y ) layers or a combination of one or more layers.

[0122] For example, the first passivation layer 51 in this embodiment includes a first aluminum oxide layer 511 and a first silicon nitride layer 512 stacked in sequence, and the second passivation layer 52 includes a second aluminum oxide layer 521 and a second silicon nitride layer 522 stacked in sequence. The first aluminum oxide layer 511 is in direct electrical contact with the surface of the silicon substrate in the second region S12, and the second aluminum oxide layer 521 is in direct electrical contact with the surface of the silicon substrate in the fourth region S22, thereby ensuring the passivation effect of the front and back non-metallic regions. Optionally, the thickness of the first aluminum oxide layer 511 and the second aluminum oxide layer 521 are both 3nm to 6nm, and the thickness of the first silicon nitride layer 512 and the second silicon nitride layer 522 are both 60nm to 100nm.

[0123] As shown in Figure 2, the thickness of the first passivation layer 51 in the first area S11 and the second area S12 in this embodiment is equal. Therefore, the surface of the first passivation layer 51 facing away from the silicon substrate 10 has a height difference H3 in the first area S11 and the second area S12, and the height difference H3 is equal to the height difference H1, which is 0.1μm to 6μm.

[0124] As shown in Figure 3, the thickness of the second passivation layer 52 in the third region S21 and the fourth region S22 is equal. Therefore, the surface of the second passivation layer 52 facing away from the silicon substrate 10 has a height difference H4 in the third region S21 and the fourth region S22, and the height difference H4 is equal to the height difference H2, which is 0.1μm to 6μm.

[0125] In this embodiment, the first electrode 41 on the first surface S1 is in electrical contact with the first doped layer 31, but does not damage the bottom-most first tunneling layer 21, thereby ensuring the tunneling effect of the first tunneling layer 21. The second electrode 42 on the second surface S2 is in electrical contact with the second doped layer 32, but does not damage the bottom-most second tunneling layer 22, thereby ensuring the tunneling effect of the second tunneling layer 22.

[0126] Referring again to FIG. 2 , the first electrode 41 in this embodiment is distributed directly above the first region S11, and the projection of the first electrode 41 on the first surface S1 is within the first region S11. Taking the gate line electrode as an example, the gate line electrode may include a plurality of vertically distributed main gate lines and a plurality of secondary gate lines (or fine gate lines). The main gate lines are typically prepared using a non-burn-through paste. The first electrode 41 in this application is described using the secondary gate lines as an example. The width of the secondary gate lines may be 5 μm to 40 μm. The first region S11 includes a plurality of linear regions distributed at intervals. The width of the first region S11 is 20 μm to 200 μm, and may optionally be 80 μm to 100 μm.

[0127] Taking a 210TOPCon battery as an example, the battery size is 203.396±15mm, with 230 grid lines with a width of 15μm to 100μm, and the spacing between adjacent grid lines is 0.907±0.015mm. The spacing between adjacent first regions S11 is equal to the spacing between adjacent grid lines. Each first region S11 is distributed with a grid line, and the width of the first region S11 is greater than the width of the grid lines. For example, if the width of the grid lines is 40μm, the width of the first region S11 is 80μm.

[0128] The first electrode 41 and the first region S11 on the first surface S1 of the silicon substrate 10 are used as an example for the description above. The second electrode 42 and the third region S21 on the second surface S2 of the silicon substrate 10 are substantially the same as those on the first surface S1 and are not described again here.

[0129] The method for preparing a solar cell in this embodiment specifically includes the following steps:

[0130] 1. Double-sided polishing

[0131] Referring to FIG4a , a silicon substrate 10 is provided. The silicon substrate 10 includes a first surface S1 and a second surface S2 that are arranged opposite to each other. The first surface S1 includes a first region S11 and a second region S12 that are spaced apart. The second surface S2 includes a third region S21 and a fourth region S22 that are spaced apart. The first surface S1 is the front surface (i.e., the primary light-receiving surface) of the silicon substrate 10, and the second surface S2 is the back surface (i.e., the secondary light-receiving surface) of the silicon substrate 10. The first region S11 is the front metal region, the second region S12 is the front non-metal region, the third region S21 is the back metal region, and the fourth region S22 is the back non-metal region. Of course, in other embodiments, the first surface S1 may also be the back surface (i.e., the secondary light-receiving surface) of the silicon substrate 10, and the second surface S2 may be the front surface (i.e., the primary light-receiving surface) of the silicon substrate 10.

[0132] The silicon substrate 10 in this embodiment is an N-type silicon substrate with a resistivity of 0.3 Ω·cm to 7 Ω·cm, optionally 0.5 Ω·cm to 3.5 Ω·cm. An alkaline polishing process is used to polish the first surface S1 and the second surface S2 of the silicon substrate 10 to form a polished surface with a reflectivity of 45% to 55%. The alkaline polishing solution can contain NaOH, KOH, TMAH, etc.

[0133] Optionally, the first surface S1 and the second surface S2 of the silicon substrate are subjected to an alkali texturing process to prepare a textured surface having a pyramid structure, wherein the bottom width of the pyramid structure is 0.5 μm to 1.5 μm and the height is 0.3 μm to 1 μm.

[0134] 2. Preparation of the first tunnel passivation structure

[0135] A first tunneling layer 21 and a first doping layer 31 are sequentially stacked in the first region S11 of the first surface S1. The steps include:

[0136] First, referring to FIG. 4 b , a first tunneling layer 21 and a first intrinsic layer 31 ′ are deposited entirely on the first surface S1 .

[0137] For example, in this embodiment, the LPCVD (Low Pressure Chemical Vapor Deposition) process is used for deposition. The first tunneling layer 21 is a combination of one or more of a silicon oxide layer, a silicon oxynitride layer, and the like, with a thickness of 1.5 nm to 2.5 nm, optionally 1.8 nm to 2.2 nm. The first intrinsic layer 31' is an intrinsic polysilicon layer with a thickness of 80 nm to 400 nm, optionally 200 nm to 300 nm. Compared to the PECVD process, the LPCVD process deposits a higher quality intrinsic polysilicon film.

[0138] Then, referring to FIG. 4 c , a first mask layer 61 is deposited on the first intrinsic layer 31 ′.

[0139] For example, the first mask layer 61 is deposited by using a PECVD (Plasma Enhanced Chemical Vapor Deposition) process. The first mask layer 61 is an inorganic mask, such as silicon oxide (SiO X ) mask, with a thickness of 20nm to 80nm, optionally 30nm to 40nm.

[0140] Then, referring to FIG. 4 d , the first mask layer 61 in the second region S12 is patterned and opened by a laser process to expose the first intrinsic layer 31 ′ in the second region S12 .

[0141] A laser process is used for patterned film opening. According to the number of gate line electrodes and the width of the first area S11, the first mask layer 61 of the second area S12 is removed, and only the first mask layer 61 of the first area S11 is retained. For example, in this embodiment, the width of the first area S11 is 20μm to 200μm, and can be optionally 80μm to 100μm.

[0142] Finally, referring to FIG. 4e , a wet etching process is used to remove the first intrinsic layer 31 ′ and the first tunneling layer 21 in the second region S12 to expose the silicon substrate 10 in the second region S12 , and to remove the first mask layer 61 in the first region S11 to expose the first intrinsic layer 31 ′ in the first region S11 .

[0143] The wet etching process includes the following steps:

[0144] First, an alkaline etching process is used to remove the first intrinsic layer 31' and the first tunneling layer 21 in the second region S12, and a portion of the silicon substrate in the second region S12 is etched to form a groove in the second region S12 of the first surface S1. The first intrinsic layer 31' below the first region S11 is not etched because it is blocked by the first mask layer 61.

[0145] Then, the second area S12 on the first surface S1 is textured by an alkali texturing process, and a velvet surface with a pyramid structure is prepared in the second area S12. For example, in this embodiment, the bottom width of the pyramid structure in the second area S12 is 1.5 μm to 2.2 μm, and the height is 1 μm to 1.3 μm, while the first area S11 is the original pyramid structure velvet surface, and the bottom width of the pyramid structure is 0.5 μm to 1.5 μm, and the height is 0.3 μm to 1 μm.

[0146] Finally, an acid solution is used to remove the first mask layer 61 and simultaneously remove silicon oxide formed on the surface during the deposition process.

[0147] 3. Front diffusion process

[0148] 4 f , a diffusion process is used to diffuse the first surface S1 of the silicon substrate 10 and the first intrinsic layer 31 ′ to form a diffusion layer 11 and a first doped layer 31 .

[0149] Specifically, a P-type doped diffusion layer 11 (ie, a P+ emitter) is formed on the first surface S1 of the silicon substrate 10 by a boron diffusion process, and the diffusion temperature is 920° C. to 980° C.

[0150] In the second region S12, since there is no obstruction of the first tunneling layer 21 above, boron atoms diffuse directly downward from the first surface S1 of the silicon substrate, thereby forming a second diffusion layer 112; while in the first region S11, boron atoms first diffuse into the intrinsic layer, and then diffuse downward through the first tunneling layer 21, thereby forming a first diffusion layer 111 in the first region S11; In addition, the first intrinsic layer 31' can be simultaneously doped with boron during the diffusion process, thereby forming a boron-doped polysilicon layer. Optionally, the doping concentration of the second diffusion layer 112 is 1E18cm -3 ~5E19cm -3 The doping concentration of the first diffusion layer 111 is 1E17 cm -3 ~5E19cm -3 The doping concentration of the first doping layer 31 is 1E19 cm -3 ~1E20cm -3 In the boron diffusion process, BSG (borosilicate glass) is formed on the second surface S2 of the silicon substrate.

[0151] In this embodiment, an intrinsic polysilicon layer is first formed, and then a boron diffusion layer and a boron-doped polysilicon layer are simultaneously formed using a one-step diffusion process. This optimizes the process and improves cell efficiency. If boron diffusion is first performed on the first surface S1 of the silicon substrate 10, and then the first tunneling layer and the boron-doped polysilicon layer are sequentially deposited, the boron diffusion layer formed in the second region S12 will be etched away during the subsequent wet etching process on the second region S12, reducing the built-in electric field of the front PN junction, affecting the photovoltaic effect, and thus reducing cell efficiency.

[0152] 4. Backside de-wrapping and backside etching

[0153] Using a chain machine, an acid solution (such as HF solution) is used to remove the wrap-around layer generated on the second surface S2 of the silicon substrate 10 during the diffusion process. Taking the boron diffusion process as an example, the wrap-around layer is borosilicate glass (BSG);

[0154] The second surface S2 of the silicon substrate 10 is etched with an alkaline solution by a slot machine to remove the P+ junction formed by backside expansion during the diffusion process.

[0155] 5. Preparation of the second tunnel passivation structure

[0156] A second tunneling layer 22 and a second doping layer 32 are sequentially stacked in the third region S21 of the second surface S1. The steps include:

[0157] First, referring to FIG. 4 g , a second tunneling layer 22 , a second doping layer 32 and a second mask layer 62 are deposited on the entire surface of the second surface S1 .

[0158] For example, in this embodiment, a PECVD (Plasma Enhanced Chemical Vapor Deposition) process is used for deposition; the second tunneling layer 22 is a combination of any one or more of a silicon oxide layer, a silicon oxynitride layer, etc., with a thickness of 0.5 nm to 3 nm, optionally 1.5 nm to 1.8 nm; the second doping layer 32 is a doped polysilicon layer with a thickness of 50 nm to 150 nm, optionally 90 nm to 130 nm; the second mask layer 62 is an inorganic mask, such as silicon oxide (SiO X ) mask with a thickness of 15nm to 25nm.

[0159] Then, referring to FIG. 4 h , the second mask layer 62 in the fourth region S22 is patterned and opened by a laser process to expose the second doping layer 32 in the fourth region S22 .

[0160] A laser process is used for patterned film opening. According to the number of gate line electrodes and the width of the third area S21, the second mask layer 62 of the fourth area S22 is removed, and only the second mask layer 62 of the third area S21 is retained. For example, in this embodiment, the width of the third area S21 is 20μm to 200μm, and can be optionally 80μm to 100μm.

[0161] Finally, referring to FIG4i, a wet etching process is used to remove the second doping layer 32 and the second tunneling layer 22 in the fourth region S22 to expose the silicon substrate 10 in the fourth region S22, and the second mask layer 62 in the third region S21 is removed to expose the second doping layer 32 in the first region S11.

[0162] The wet etching process includes the following steps:

[0163] First, an alkaline etching process is used to remove the second doped layer 32 and the second tunneling layer 22 in the fourth area S22, and part of the silicon substrate in the fourth area S22 is etched to form a groove in the fourth area S22 of the second surface S2. Since the third area S21 is blocked by the second mask layer 62, the second doped layer 32 thereunder will not be etched; the alkaline etching process can simultaneously remove the polysilicon plated on the front side.

[0164] Then, the fourth region S22 on the second surface S2 is polished using an alkali polishing process.

[0165] Finally, an acid solution is used to remove the second mask layer 62 and simultaneously remove silicon oxide formed on the surface during the deposition process.

[0166] 6. Double-sided passivation

[0167] As shown in FIG4 j , a passivation layer is prepared on the first surface S1 and the second surface S2 .

[0168] Specifically, in this embodiment, an ALD (Atomic Layer Deposition) process is used to form a first passivation layer 51 and a second passivation layer 52 on the first surface S1 and the second surface S2, respectively. The first passivation layer 51 includes a first aluminum oxide layer 511 and a first silicon nitride layer 512 stacked in sequence, and the second passivation layer 52 includes a second aluminum oxide layer 521 and a second silicon nitride layer 522 stacked in sequence. The thickness of the first aluminum oxide layer 511 and the second aluminum oxide layer 521 are both 3 nm to 6 nm, and the thickness of the first silicon nitride layer 512 and the second silicon nitride layer 522 are both 60 nm to 100 nm.

[0169] 7. Preparation of metal electrodes

[0170] 4 k , a first electrode 41 in ohmic contact with the silicon substrate 10 is formed in the first region S11 of the first surface S1 , and a second electrode 42 in ohmic contact with the silicon substrate 10 is formed on the second surface S2 .

[0171] Specifically, in this embodiment, a screen printing process is used to print metal layers in the first area S11 in the first surface S1 and the third area S21 in the second surface S2, respectively, to form a first electrode 41 and a second electrode 42 that are in ohmic contact with the silicon substrate 10. Optionally, the first electrode 41 and the second electrode 42 in this embodiment are both silver grid line electrodes.

[0172] 8. LIF process

[0173] The LIF (Laser Induced Firing) process is used to sinter the electrode, which can increase the contact between the electrode and the doping layer and significantly reduce the contact resistance between the metal and the doping layer.

[0174] Example 2:

[0175] The structure and preparation method of the solar cell in this embodiment are roughly the same as those in Example 1, except that, in this embodiment, the first area S11 in the first surface S1 forms a tower base with poor light trapping effect, and the second area S12 forms a velvet surface with better light trapping effect. Compared with the pyramid structure and tower base of the same size, the pyramid structure has better light trapping effect.

[0176] For example, in this embodiment, the first area S11 in the first surface S1 is a polished surface with a tower base, the width of the tower base is 1μm to 5μm, and the height of the tower base is 0.1μm to 0.4μm; and the second area S12 in the first surface S1 is a velvet surface with a pyramid structure, the bottom width of the pyramid structure is 1.5μm to 2.2μm, and the height is 1μm to 1.3μm. Among them, the velvet surface of the pyramid structure will be formed after the alkali velveting process on the surface of the silicon substrate, and then after the alkali polishing process, the pyramid structure is polished to form a tower base, and the tower base is the base left after the velvet surface of the pyramid structure is polished. The bottom of the pyramid structure and the shape of the bottom of the tower base can be a triangle, a quadrilateral, etc. The bottom width of the pyramid structure is defined as the average value of the width of the bottom shape of the pyramid structure, and the bottom width of the tower base is defined as the average value of the width of the bottom shape of the tower base. Taking the bottom shape as a square as an example, the bottom width is the side length of the square.

[0177] Example 3:

[0178] As shown in FIG5 , the structure and preparation method of the solar cell in this embodiment are substantially the same as those in Example 1, except that, in this embodiment, the first surface S1 of the silicon substrate is flush with the first region S11 and the second region S12, and in the wet etching process, the parameters of the alkaline etching process are controlled to stop etching after the first intrinsic layer 31 ′ and the first tunneling layer 21 in the second region S12 are etched away.

[0179] Compared with Example 1, the surface of the second region in this embodiment is smoother, so that the first passivation layer subsequently deposited on the silicon substrate has better uniformity and better passivation performance, which can improve the composite defect problem of the solar cell.

[0180] Example 4:

[0181] As shown in Figure 6, the structure and preparation method of the solar cell in this embodiment are roughly the same as those in Example 1, except that, in this embodiment, the second surface S2 of the silicon substrate is flush in the third region S21 and the fourth region S22, and in the wet etching process step, the parameters of the alkaline etching process are controlled to stop etching after the second doping layer 32 and the second tunneling layer 22 in the fourth region S22 are etched away.

[0182] Compared with Example 1, the surface of the fourth region in this embodiment is smoother, so that the second passivation layer subsequently deposited on the silicon substrate has better uniformity and better passivation performance, which can improve the composite defect problem of the solar cell.

[0183] The double-sided TOPCon cells in the above embodiments use a Poly-finger structure with local tunneling passivation contacts on both the front and back sides, ensuring contact passivation in the first area on the front side and the third area on the back side, while reducing parasitic absorption in the second area on the front side. Compared with the single-sided TOPCon cells in the related art, the cell efficiency can be greatly improved, and the preparation process is simple, making it suitable for mass production.

[0184] The metal areas on the front and back of the battery are made of polysilicon (poly) technology, which minimizes the recombination of the metal areas, effectively reduces the reverse saturation current, and can significantly improve battery efficiency.

[0185] It will be apparent to those skilled in the art that the present application is not limited to the details of the exemplary embodiments described above, and that the present application can be implemented in other specific forms without departing from the spirit or essential characteristics of the present application. Therefore, the embodiments should be considered in all respects as illustrative and non-restrictive, and the scope of the present application is defined by the appended claims, not the foregoing description, and all variations within the meaning and range of equivalents of the claims are intended to be included therein. Any reference sign in a claim should not be construed as limiting the claim to which it relates.

[0186] In addition, it should be understood that although this specification is described in terms of implementation methods, not every implementation method contains only one independent technical solution. This narrative method of the specification is only for the sake of clarity. Those skilled in the art should regard the specification as a whole. The technical solutions in each embodiment can also be appropriately combined to form other implementation methods that can be understood by those skilled in the art.

Claims

1. A solar cell comprising a silicon substrate, the silicon substrate comprising a first surface and a second surface opposite to each other, a diffusion layer formed on the first surface of the silicon substrate, the first surface comprising a first region and a second region spaced apart, the second surface comprising a third region and a fourth region spaced apart, the first region being provided with a first tunneling passivation structure and a first electrode, and the third region being provided with a second tunneling passivation structure and a second electrode.

2. The solar cell according to claim 1, wherein The first surface of the silicon substrate is arranged to be recessed in the second region relative to the first region; and / or, The second surface of the silicon substrate is recessed relative to the third region in a fourth region.

3. The solar cell according to claim 1 or 2, wherein The first surface of the silicon substrate is recessed in the second region to a depth of 1 μm to 6 μm; and / or, The second surface of the silicon substrate is recessed in the fourth region to a depth of 1 μm to 6 μm.

4. The solar cell according to claim 1 or 2, wherein A height difference between a surface of the first tunneling passivation structure facing away from the silicon substrate and the first surface of the silicon substrate in the second region is 0.1 μm to 6 μm; and / or, A height difference between a surface of the second tunneling passivation structure facing away from the silicon substrate and the second surface of the silicon substrate in the fourth region is 0.1 μm to 6 μm.

5. The solar cell according to claim 1, wherein The diffusion layer includes a first diffusion layer located in the first region and a second diffusion layer located in the second region.

6. The solar cell according to claim 5, wherein The doping concentration of the second diffusion layer is greater than the doping concentration of the first diffusion layer; and / or, The doping concentration of the second diffusion layer is 1E18cm -3 ~5E19cm -3 and / or, The doping concentration of the first diffusion layer is 1E17 cm -3 ~5E19cm -3 .

7. The solar cell according to claim 1, wherein The first tunneling passivation structure includes a first tunneling layer and a first doped layer sequentially stacked in the first region, the second tunneling passivation structure includes a second tunneling layer and a second doped layer sequentially stacked in the third region, the first electrode is electrically contacted with the first doped layer, the second electrode is electrically contacted with the second doped layer, the first doped layer and the diffusion layer have the same doping type, and the second doped layer and the first doped layer have a doping type opposite.

8. The solar cell according to claim 7, wherein The diffusion layer includes a first diffusion layer located in the first region, and the doping concentration of the first diffusion layer is lower than the doping concentration of the first doping layer.

9. The solar cell according to claim 7, wherein The first tunneling layer is any one or more combinations of a silicon oxide layer and a silicon oxynitride layer; and / or, The thickness of the first tunneling layer is 1.5 nm to 2.5 nm or 1.8 nm to 2.2 nm; and / or, The first doped layer is a doped polysilicon layer with a thickness of 80nm to 400nm or 200nm to 300nm; The doping concentration of the first doping layer is 1E19cm -3 ~1E20cm -3 and / or, The second tunneling layer is any one or more combinations of a silicon oxide layer and a silicon oxynitride layer; and / or, The thickness of the second tunneling layer is 0.5 nm to 3 nm or 1.5 nm to 1.8 nm; and / or, The second doped layer is a doped polysilicon layer with a thickness of 50 nm to 150 nm or 90 nm to 130 nm; and / or, The silicon substrate is an N-type silicon substrate, the diffusion layer is a P-type diffusion layer, the first doping layer is a P-type doping layer, and the second doping layer is an N-type doping layer.

10. The solar cell according to claim 1, wherein A first passivation layer covering the first tunnel passivation structure and the second region of the silicon substrate is provided on the first surface of the silicon substrate, and a second passivation layer covering the second tunnel passivation structure and the fourth region of the silicon substrate is provided on the second surface of the silicon substrate.

11. The solar cell according to claim 10, wherein The height difference between the first region and the second region of the first passivation layer on the side facing away from the silicon substrate is 0.1 μm to 6 μm; and / or, A height difference between the third region and the fourth region of the second passivation layer on a side facing away from the silicon substrate is 0.1 μm to 6 μm.

12. The solar cell according to claim 10, wherein The first passivation layer includes one or more layers selected from the group consisting of a silicon oxide layer, an aluminum oxide layer, a silicon nitride layer, and a silicon oxynitride layer; and / or, The second passivation layer includes one or more layers selected from the group consisting of a silicon oxide layer, an aluminum oxide layer, a silicon nitride layer, and a silicon oxynitride layer.

13. The solar cell according to claim 10, wherein The first passivation layer comprises an aluminum oxide layer and a silicon nitride layer stacked in sequence, wherein the thickness of the aluminum oxide layer is 3 nm to 6 nm, and the thickness of the silicon nitride layer is 60 nm to 100 nm; and / or, The second passivation layer includes an aluminum oxide layer and a silicon nitride layer stacked in sequence, wherein the thickness of the aluminum oxide layer is 3 nm to 6 nm, and the thickness of the silicon nitride layer is 60 nm to 100 nm.

14. The solar cell according to claim 1, wherein The first area in the first surface of the silicon substrate is a suede surface with a pyramid structure or a polished surface with a pyramid base, and the second area in the first surface of the silicon substrate is a suede surface with a pyramid structure.

15. The solar cell according to claim 14, wherein The base width of the pyramid structure in the first region is 0.5 μm to 1.5 μm, and the height is 0.3 μm to 1 μm; or, the base width of the pyramid structure in the first region is 1 μm to 5 μm, and the height of the pyramid structure is 0.1 μm to 0.4 μm; and / or, The bottom width of the pyramid structure in the second region is 1.5 μm to 2.2 μm, and the height is 1 μm to 1.3 μm.

16. The solar cell according to claim 1, wherein The third region and the fourth region in the second surface of the silicon substrate are both polished surfaces.

17. The solar cell according to claim 1, wherein The width of the first region is 20 μm to 200 μm or 80 μm to 100 μm; and / or, The width of the third region is 20 μm to 200 μm or 80 μm to 100 μm.

18. A method for preparing a solar cell, comprising the following steps: Providing a silicon substrate, the silicon substrate comprising a first surface and a second surface opposite to each other, the first surface comprising a first region and a second region spaced apart from each other, and the second surface comprising a third region and a fourth region spaced apart from each other; preparing a first tunneling passivation structure in a first region of the first surface, and then forming a diffusion layer below the first surface of the silicon substrate; preparing a second tunneling passivation structure in a third region of the second surface; A first electrode is formed on a first region of the first surface, and a second electrode is formed on a third region of the second surface.

19. The preparation method according to claim 18, wherein Preparing a first tunneling passivation structure in the first region of the first surface includes: forming a first tunneling layer, a first intrinsic layer and a first mask layer on the first surface; Using a laser process to pattern the first mask layer in the second area to expose the first intrinsic layer in the second area; removing the first intrinsic layer and the first tunneling layer in the second region by a wet etching process to expose the silicon substrate in the second region; removing the first mask layer in the first region to expose the first intrinsic layer in the first region; The first intrinsic layer is transformed into a first doped layer by using a diffusion process.

20. The preparation method according to claim 19, wherein The preparation method further comprises: The first intrinsic layer and the first tunneling layer in the second region are removed by a wet etching process, and a portion of the silicon substrate in the second region is etched.

21. The preparation method according to claim 19, wherein The first intrinsic layer is an intrinsic polysilicon layer, the first tunneling layer is any one or more combinations of a silicon oxide layer and a silicon oxynitride layer, and the etching solution in the wet etching process is an alkaline solution; and / or, The first mask layer is any one or more combinations of a silicon oxide layer, a silicon oxynitride layer, and a silicon nitride layer, and the first mask layer is removed using an acid solution; and / or, The thickness of the first mask layer is 20 nm to 80 nm.

22. The preparation method according to claim 19, wherein The preparation method further comprises: Before forming the first tunneling layer, the first intrinsic layer and the first mask layer on the first surface, a velvet surface having a pyramid structure is prepared on the first surface of the silicon substrate by an alkali texturing process, wherein the bottom width of the pyramid structure is 0.5 μm to 1.5 μm and the height is 0.3 μm to 1 μm; or, a polished surface having a tower base is prepared on the first surface of the silicon substrate by an alkali texturing process and an alkali polishing process, wherein the tower base has a width of 1 μm to 5 μm and a height of 0.1 μm to 0.4 μm; After removing the first intrinsic layer and the first tunneling layer of the second area by a wet etching process, the second area on the first surface of the silicon substrate is subjected to an alkali texturing process to prepare a velvet surface with a pyramid structure, wherein the bottom width of the pyramid structure is 1.5μm to 2.2μm and the height is 1μm to 1.3μm.

23. The preparation method according to claim 19, wherein A one-step diffusion process is used to transform the first intrinsic layer into a first doped layer, and simultaneously a first diffusion layer and a second diffusion layer are formed in the first area and the second area of ​​the first surface of the silicon substrate respectively.

24. The preparation method according to claim 23, wherein The doping concentration of the first diffusion layer is lower than the doping concentration of the first doping layer, and the doping concentration of the second diffusion layer is higher than the doping concentration of the first diffusion layer.

25. The preparation method according to claim 19, wherein The preparation method further comprises: An acid solution is used to remove the wrap-around layer generated on the second surface of the silicon substrate during the diffusion process; The second surface of the silicon substrate is etched using an alkaline solution.

26. The preparation method according to claim 18, wherein Preparing a second tunneling passivation structure in the third region of the second surface includes: forming a second tunneling layer, a second doping layer and a second mask layer on the second surface; Using a laser process to pattern the second mask layer in the fourth region to expose the second doping layer in the fourth region; removing the second doping layer and the second tunneling layer in the fourth region by a wet etching process to expose the silicon substrate in the fourth region; The second mask layer in the third region is removed to expose the second doping layer in the third region.

27. The preparation method according to claim 26, wherein The preparation method further comprises: The second doping layer and the second tunneling layer in the fourth region are removed by a wet etching process, and a portion of the silicon substrate in the fourth region is etched.

28. The preparation method according to claim 26, wherein The second doped layer is a doped polysilicon layer, the second tunneling layer is any one or more combinations of a silicon oxide layer and a silicon oxynitride layer, and the etching solution in the wet etching process is an alkaline solution; and / or, The second mask layer is any one or more combinations of a silicon oxide layer, a silicon oxynitride layer, and a silicon nitride layer, and the second mask layer is removed using an acid solution; and / or, The thickness of the second mask layer is 15 nm to 25 nm.

29. The preparation method according to claim 26, wherein The preparation method further comprises: After the second doping layer and the second tunneling layer in the fourth region are removed by a wet etching process, an alkali polishing process is performed on the silicon substrate in the fourth region.

30. The preparation method according to claim 18, wherein The preparation method further comprises: forming a first passivation layer on the first surface of the silicon substrate, and forming a first electrode in a first region of the first surface that penetrates the first passivation layer and is in electrical contact with the first tunneling passivation structure, wherein the first passivation layer comprises a combination of one or more layers of a silicon oxide layer, an aluminum oxide layer, a silicon nitride layer, and a silicon oxynitride layer; and / or, A second passivation layer is prepared on the second surface of the silicon substrate, and a second electrode is prepared in a third area of ​​the second surface, which penetrates the second passivation layer and is in electrical contact with the second tunneling passivation structure. The second passivation layer includes a combination of one or more layers of a silicon oxide layer, an aluminum oxide layer, a silicon nitride layer, and a silicon oxynitride layer.

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